WO2025244715A1 - A design strategy for high-performance p-type two-dimensional field effect transistors - Google Patents

Abstract

Embodiments can relate to a Field Effect Transistor (FET) including a substrate having a 2D material formed on a surface thereof. The 2D material can have a source contact region, a drain contact region, and a channel region. The channel region can include one to three monolayers of the 2D material. The source contact region can include three to six monolayers of the 2D material. The drain contact region can include three to six monolayers of the 2D material. Embodiments can relate to a method for generated a FET structure. The method can involve forming three to six monolayers of 2D material on a surface of a substrate, and then removing three to five monolayers of the 2D material to generate a channel region, wherein the source contact region and the drain contact region can include three to six monolayers of the 2D material.

Description

A DESIGN STRATEGY FOR HIGH-PERFORMANCE P-TYPE TWO-DIMENSIONAL

FIELD EFFECT TRANSISTORS

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This patent application is related to and claims the benefit of priority of U.S. provisional patent application no. 63/649,715, filed on May 20, 2024, the entire contents of which is incorporated herein by reference.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] This invention was made with government support under Grant No. ECCS-2042154 awarded by the National Science Foundation. The Government has certain rights in the invention.

FIELD OF THE INVENTION

[0003] Embodiments can relate to a Field Effect Transistor (FET) including a substrate having a 2D material formed on a surface thereof, wherein a channel region includes one to three monolayers of the 2D material.

BACKGROUND OF THE INVENTION

[0004] The rise of two-dimensional (2D) semiconductors as potential alternatives to silicon in CMOS technology, especially at scaled process nodes, is promising due to their atomically thin nature. Semiconducting transition metal dichalcogenides (TMDs) like M0S2, MoSe2, and WSe2, with thicknesses as thin as ~0.6 nm at the monolayer level, offer atomically smooth surfaces and hold significant potential for high-performance field-effect transistors (FETs). Notable progress has been made in n-type FETs based on 2D materials such as M0S2 and WS2, driven by advancements in material growth, contact engineering, channel length scaling, and high-k dielectric integration bringing them closer to meeting the requirements set by International Roadmap for Devices and Systems (IRDS). However, achieving high-performance p-type FETs has been slower due to challenges related to Fermi level pinning at metal/2D interfaces.

[0005] In 2D TMDs like M0S2 and WS2, Fermi level pinning near the conduction band edge can be overcome by using low work-function metals as contact electrodes to realize high- performance n-type FETs. However, it results in significant contact resistance (Rc) for hole injection.

[0006] Additionally, the challenge is exacerbated in monolayers due to larger bandgap values. In contrast, transition metal selenides like MoSe2 and WSe? facilitate relatively easier hole injection due to Fermi level pinning near the middle of the bandgap. Here however tunneling injection across the Schottky barrier leads to diminished ON-state performance (ION). Reducing Rc by cutting short the tunneling distance is imperative by degenerate doping underneath the contacts, a strategy long adopted in the semiconductor industry for both n- and p-type FETs. Applying this approach to 2D FETs presents its own challenges.

[0007] On examining 2D FETs based on pristine and doped MoSe2 and WSe2 single crystal flakes it was observed that while n-type transport dominates in pristine flakes, thick doped flakes demonstrate degenerate p-type doping, resulting in improved FET characteristics. However, thick flakes lack electrostatic gate control, leading to a poor on/off current ratio. As the flake thickness decreases, doping effectiveness diminishes due to quantum confinement effects. This underscores the importance of degenerate doping to decrease Rc and the necessity of maintaining a thin channel for improved electrostatics.

SUMMARY OF THE INVENTION

[0008] Embodiments can relate to a novel FET structure comprising thin channel layers and degenerately doped multilayer contact regions, to achieve high performance (7rAv~85pA/pm) with low Ac (~2 kQ-pm) and high ON/OFF current ratio (10⁴). Furthermore, applying the novel FET design on a scaled dual-gated FET is demonstrated, showcased improved performance (ION~212pA/pm). This design approach can be extended to various 2D materials, facilitating advancements in both n- and p-type doping for 2D FET technology and underscoring the significance of doped multilayer 2D materials on a wafer scale.

[0009] Doping is crucial for shaping semiconductors and electronic devices, particularly in fieldeffect transistors (FETs). Degenerate doping in the silicon channel beneath the source and drain regions is vital for high-performance n- and p-type devices as it reduces contact resistance (Rc). In contrast, 2D semiconductors mainly rely on metal work-function engineering to lower Ac. While successful for n-type 2D FETs, achieving the same for p-type ones has been challenging. To address this, the present disclosure demonstrates degenerate p-type doping in thick MoSe2 and WSez FETs 4-6 monolayers) via transition metal substitution (V, Nb, Ta) and an observation of weakened gate control and a poor on/off current ratio. Interestingly, thinner flakes ( 1-3 monolayers) show reduced doping effectiveness due to quantum confinement effects, restoring gate control. Based on this observation, the present disclosure provides for designed a FET structure where the channel is fabricated using thinner 2D material which are relatively less doped, while the contact regions consist of degenerately doped thicker layers, allowing us to achieve both low Rc and high on/off current ratio. The doping and device design approach are relevant for synthetic 2D materials and n-type 2D FETs.

[0010] Embodiments can relate to a Field Effect Transistor (FET) including a substrate having a 2D material formed on a surface thereof. The 2D material can have a source contact region, a drain contact region, and a channel region. The channel region can include one to three monolayers of the 2D material. The source contact region can include three to six monolayers of the 2D material. The drain contact region can include three to six monolayers of the 2D material.

[0011] In some embodiments, the channel region can consist essentially of one to three monolayers of the 2D material. The source contact region can consist essentially of three to six monolayers of the 2D material. The drain contact region can consist essentially of three to six monolayers of the 2D material.

[0012] In some embodiments, the channel region can consist of one to three monolayers of the 2D material. The source contact region can consist of three to six monolayers of the 2D material. The drain contact region can consist of three to six monolayers of the 2D material. [0013] In some embodiments, the source contact region can include degenerately doped 2D material. The drain contact region can include degenerately doped 2D material.

[0014] In some embodiments, the FET can include a source contact formed on the source contact region. A drain contact can be formed on the drain contact region.

[0015] In some embodiments, the channel region can be formed between the source contact region and the drain contact region.

[0016] In some embodiments, the 2D material can include one or more types of 2D material. [0017] In some embodiments, the 2D material of the channel region can be the same as or different from the 2D material of the source contact region. The 2D material of the channel region can be the same as or different from the 2D material of the drain contact region. The 2D material of the source contact region can be the same as or different from the 2D material of the drain contact region.

[0018] In some embodiments, the 2D material of one monolayer of the channel region can be the same as or different from the 2D material of another monolayer of the channel region. The 2D material of one monolayer of the source contact region can be the same as or different from the 2D material of another monolayer of the source contact region. The 2D material of one monolayer of the drain contact region can be the same as or different from the 2D material of another monolayer of the drain contact region.

[0019] In some embodiments, the substrate can be a p-type doped substrate. The substrate can be a n-type doped substrate.

[0020] In some embodiments, the FET can yield a performance of at least ION = 85pA/pm. The FET can exhibit a contact resistance (Rc) of less than 2 kQ-pm. The FET can exhibit an ON/OFF current ratio > IO⁴

[0021] Embodiments can relate to a method for generated a FET structure. The method can involve forming three to six monolayers of 2D material on a surface of a substrate. The method can involve removing three to five monolayers of the 2D material to generate a channel region. The channel region can be between a source contact region and a drain contact region. The source contact region can include three to six monolayers of the 2D material. The drain contact region can include three to six monolayers of the 2D material.

[0022] In some embodiments, removing three to five monolayers can involve a self-limiting etching technique.

[0023] In some embodiments, the self-limiting etching technique can involve radio frequency (RF) plasma-based oxidation.

[0024] In some embodiments, RF plasma-based oxidation can remove three to five monolayers in a layer-by-layer fashion.

[0025] In some embodiments, the forming three to six monolayers of 2D material on a surface of a substrate can involve forming a first layer on the substrate, a second layer on the first layer, a third layer on the second layer, a fourth layer on the third layer, a fifth layer on the fourth layer, and a sixth layer on the fifth layer. RF plasma-based oxidation can be used on the sixth layer to generate a passivating and sub-stoichiometric sixth layer, wherein the passivating and sub- stoichiometric sixth layer is dissolved. RF plasma-based oxidation can be used on the fifth layer to generate a passivating and sub -stoichiometric fifth layer, wherein the passivating and sub- stoichiometric fifth layer is dissolved. RF plasma-based oxidation can be used on the fourth layer to generate a passivating and sub-stoichiometric fourth layer, wherein the passivating and sub-stoichiometric fourth layer is dissolved.

[0026] In some embodiments, the 2D material can be doped single crystals.

[0027] In some embodiments, the 2D material can be doped using a chemical vapor transport technique.

[0028] In some embodiments, the 2D material can be formed on the surface of the substrate via a chemical vapor transport technique.

[0029] Exemplary embodiments can relate to a Field Effect Transistor (FET). The FET can include a substrate having a 2D material formed on a surface thereof, the 2D material having a source contact region, a drain contact region, and a channel region. The channel region can have less than four monolayers of the 2D material. The source contact region can include more than four monolayers of the 2D material. The drain contact region can include more than four monolayers of the 2D material.

[0030] In some embodiments, the source contact region can include heavily/degenerately doped 2D material. The drain contact region can include heavily/degenerately doped 2D material. The channel region can include include pristine/lightly/moderately doped 2D material.

[0031] In some embodiments, the 2D material can include one or more types of 2D material.

The 2D material of the channel region can be the same as or different from the 2D material of the source contact region. The 2D material of the channel region can be the same as or different from the 2D material of the drain contact region. The 2D material of the source contact region can be the same as or different from the 2D material of the drain contact region.

[0032] In some embodiments, the 2D material of one monolayer of the channel region can be the same as or different from the 2D material of another monolayer of the channel region. The 2D material of one monolayer of the source contact region can be the same as or different from the 2D material of another monolayer of the source contact region. The 2D material of one monolayer of the drain contact region can be the same as or different from the 2D material of another monolayer of the drain contact region.

[0033] Further features, aspects, objects, advantages, and possible applications of the present invention will become apparent from a study of the exemplary embodiments and examples described below, in combination with the Figures, and the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and other objects, aspects, features, advantages and possible applications of the present innovation will be more apparent from the following more particular description thereof, presented in conjunction with the following drawings. Like reference numbers used in the drawings may identify like components.

[0035] FIG. 1 shows an exemplary architecture of an embodiment of the 2D FET.

[0036] FIG. 2 show an exemplary process of forming an embodiment of te 2D FET.

[0037] FIG. 3 shows substitutionally doped p-type MoSe? FETs.

[0038] FIG. 4 shows electronic band structure of pristine and doped MoSe2, wherein the band structure of pristine (panel a) and V- (panel b), Nb- (panel c), and Ta- (panel d) doped 2H-phase MoSe? for single-layer (IL), double-layer (2L), and eight-layer (8L) optimized structure is shown. A bar plot showing the relative position of Fermi level (E_F) with respect to the valence band (E_v), i.e., E_F — E_v for IL, 2L and 8L-MoSe2 for each of the group VB dopants is shown in panel e. A bar plot showing band gap (E_G) for pristine as well as V-, Nb- and Ta-doped MoSe2 for each thicknesses is shown in panel f.

[0039] FIG. 5 shows impact of degenerate doping on contact resistance, wherein transfer characteristics of V-, Nb-, and Ta-doped thick MoSe2 flakes for different L_ch (panel a), corresponding TLM data, i.e., R_T versus L_ch obtained at V_BG = -8 V along with the linear fits to extract the 2R_C values from the y-intercepts (panel b), and R_c values obtained from TLM measurements for V-, Nb-, and Ta-doped MoSe2 flakes with different thicknesses (panel c) are shown.

[0040] FIG. 6 shows an exemplary embodiment of a 2D FET design.

[0041] FIG. 7 shows an exemplary high performance p-type dual-gated 2D FET.

[0042] FIG. 8 shows electrical characterization ofNb-doped CVD-grown large-area MoSe2 FETs. [0043] FIG. 9 shows Fermi-level pinning at metal/2D contact interfaces, wherein band alignment and band bending at metal/2D interface for panel a) transition metal sulfides such as M0S2 and WS2 and panel b) transition metal selenides such as MoSe2 and WSe2 is shown.

[0044] FIG. 10 shows dopant concentration in V-, Nb-, and Ta-doped MoSe2 and WSe2 crystals, wherein panels a), b), c, d), e), and f) are bar plots showing the dopant concentrations for V, Nb, and Ta, determined using inductively coupled plasma atomic emission spectroscopy (ICP-AES) for MoSe2 (panel a) and WSe2 (panel b), and dopant concentrations for V, Nb, and Ta are extracted using scanning electron microscopy-electron dispersive X-ray spectroscopy (SEM- EDS) (panel c) MoSe? and WSe? (panel d), and bulk carrier concentrations (NB) at room temperature is obtained from Hall measurements for MoSe2 (panel e) and WSe2 (panel f) doped with V, Nb, and Ta.

[0045] FIG. 11 shows electrical characterization of pristine MoSe2 and WSe2 FETs, wherein transfer characteristics for thick (~4-6 monolayers) (panel a) and thin (~l-3 monolayers) (panel b) MoSe2 FETs, and transfer characteristics for thick (~4-6 monolayers) (panel c) and thin (~l-3 monolayers) (panel d) WSe2 FETs are shown.

[0046] FIG. 12 shows substitutionally doped p-type WSe2 FETs.

[0047] FIG. 13 shows optimized structures used for DFT simulation, wherein an optimized structure of 5X5X1 supercell for !L-MoSe2 (panel a), 4X4X2 supercell for 2L-MoSe2 (panel b), 2X2X8 supercell of 8L-MoSe2 (panel c), V, Nb and Ta doped lL-MoSe2 (panel d), 2L-MoSe2 (panel e), and 8L-MoSe2 (panel f) are shown. All the axis for the respective optimized structure is also shown.

[0048] FIG. 14 shows band alignment of pristine and dopedlL, 2L and 8L-MoSe2.

[0049] FIG. 15 shows projected density of states (PDOS) for pristine and doped MoSe2, and in particular projected density of states (PDOS) for pristine IL, 2L and 8L-MoSe2 with ~3 atomic percentage of V, Nb and Ta doping in each structure.

[0050] FIG. 16 shows field effect mobility (p_FE) and 4-point probe mobility (p_4PP) for MoSe2 and WSe2 FETs, wherein hole field-effect mobility (p_FE), extracted from peak transconductance for thick channel (panel a) and thin channel (panel b) FETs based on V-, Nb-, and Ta-doped MoSe2 and for thick channel (panel c) and thin channel (panel d) FETs based on V-, Nb-, and Ta-doped WSe2, and bar plots showing the 4-point probe mobility (p_4PP) extracted from Hall measurement for holes for MoSe2 (panel e) and WSe2 (panel f) specimens with dopants V, Nb, and Ta are shown.

[0051] FIG. 17 shows a scanning electron microscope (SEM) image depicting the TLM structure of a representative Nb-doped MoSe2 field-effect transistor (FET) with LCH values 500 nm, 200 nm, 100 nm, 50 nm, and 40 nm.

[0052] FIG. 18 shows impact of contact resistance on the performance of 2D FET, wherein I_0N as a function of L_ch for a supply voltage of V_DD = 1 V for lowest-R_c values were obtained experimentally from V-, Nb-, and Ta-doped thick MoSe2 FETs.

[0053] FIG. 19 shows layer by layer thinning of multilayer MoSe2 flake.

[0054] FIG. 20 shows atomic resolution imaging of Nb-doped MoSe2 FETs. HAADF-STEM images revealing the cross-sectional TLM structure with channel lengths of 50 nm, 100 nm, and 200 nm.

[0055] FIG. 21 shows as-fabricated and post-processed Nb-doped MoSe2 FETs.

[0056] FIG. 22 shows as-fabricated and post-processed Ta-doped MoSe2 FETs.

[0057] FIG. 23 shows resistor network for carrier transport in our proposed 2D FET.

[0058] FIG. 24 shows output characteristics of Nb-doped MoSe2 FET, wherein output characteristics of Nb-doped MoSe2 FET at 300 K (panel a) and 25 K (panel b) are illustrated.

[0059] FIG. 25 shows Schottky barrier (4>SB-P) heights for doped MoSe2 and WSe2 FETs and temperature dependence of output characteristics for Nb-doped MoSe2DGFETs.

[0060] FIG. 26 shows spectroscopic characterization of Nb-doped CVD-grown large-area MoSe2.

[0061] FIG. 27 shows a benchmark table.

[0062] FIG. 28 shows an exemplary FET having a thick channel (panel a) and a thin channel (panel b).

[0063] FIG. 29 shows a schematic depicting the TLM structure of a representative Nb-doped MoSe2 field-effect transistor (FET) with LCH values 500 nm, 200 nm, 100 nm, 50 nm, and 40 nm.

DETAILED DESCRIPTION OF THE INVENTION

[0064] The following description is of exemplary embodiments that are presently contemplated for carrying out the present invention. This description is not to be taken in a limiting sense, but is made merely for the purpose of describing the general principles and features of the present invention. The scope of the present invention is not limited by this description.

[0065] Referring to FIGS. 1-2, embodiments can relate to a Field Effect Transistor (FET) 100 including a substrate 102 (e.g., a semiconductor substrate) having a 2D material 104 (e.g., a crystalline solid having a single layer (monolayer) of atoms) formed on a surface thereof. The 2D material can be a MoSe2, a WSe? etc. single crystal or poly crystalline. The 2D material 104 can have a source contact region 106 (e.g., a region configured to facilitate carriers entering the channel region 110), a drain contact region 108 (e.g., a region configured to facilitate carriers leaving the channel region 110), and a channel region 110 (e.g., a region configured to have its conductivity modulated by a gate terminal). For instance, the FET 100 can include a source contact 112 (e.g., a source terminal - Pd/Au contact for example) formed on the source contact region 106, a drain contact 114 (e.g., a drain terminal - Pd/Au contact for example) formed on the drain contact region 108, and a gate contact (e.g., a gate terminal - AI2O3 on top of Ti/Pt for example) on which the channel region 110 is formed, wherein the channel region 110 lies between the source contact region 106 and the drain contact region 108. An exemplary FET 100 structure can be a p-type silicon substrate with a layer of SiCE formed thereon, a layer of Ti formed on the SiCE, a layer of Pt formed on the Ti, a layer of AI2O3 formed on the Pt, the 2D material 104 formed on the AI2O3 (in this case the substrate 102 is the Si, SiCE, Ti, Pt, and AI2O3 structure), and Pd/Au source and drain contacts 112, 114 formed on the 2D material 104. The 2D material 104 under the source and drain contacts 112, 114 is 3-6 layers thick and the 2D material 104 in the channel region 110 is 1-3 layers thick.

[0066] The channel region 110 can include a small number of monolayers of the 2D material 104. For instance, the channel region 110 can have one to three monolayers of the 2D material 104. The source contact region 106 and/or the drain contact region 108 can include a larger number of monolayers of the 2D material 104. For instance, the source contact region 106 can include three to six monolayers of the 2D material 104. The drain contact region 108 can include three to six monolayers of the 2D material 104.

[0067] As will be explained herein, the number of monolayers of 2D material 104 for the source contact, drain contact, and channel regions 106, 108, 110 can provide for enhanced operational improvements and device characteristics for the FET 100. In some embodiments, the channel region 110 can consist essentially of one to three monolayers of the 2D material 104, whereas source contact region 106 and the drain contact region 108 can consist essentially of three to six monolayers of the 2D material 104.

[0068] The source contact region 106 and/or the drain contact region 108 can include degenerately doped 2D material 104. For instance, sticking with the example of the 2D material 104 being MoSe2 or WSe2 single crystals, the 2D material 104 can be doped with V, Nb, Ta, etc. (e.g., doped during growth using a chemical vapor transport technique). The 2D material 104 for a FET 100 can be one or more types of 2D material 104. For instance, the 2D material 104 of the channel region 110 can be the same as or different from the 2D material 104 of the source contact region 106. The 2D material 104 of the channel region 110 can be the same as or different from the 2D material 104 of the drain contact region 108. The 2D material 104 of the source contact region 106 can be the same as or different from the 2D material 104 of the drain contact region 108. In addition, the 2D material 104 of one monolayer of the channel region 110 can be the same as or different from the 2D material 104 of another monolayer of the channel region 110. The 2D material 104 of one monolayer of the source contact region 106 can be the same as or different from the 2D material 104 of another monolayer of the source contact region 106. The 2D material 104 of one monolayer of the drain contact region 108 can be the same as or different from the 2D material 104 of another monolayer of the drain contact region 108.

[0069] The substrate 102 can be a p-type doped substrate or a n-type doped substrate. As will be explained herein, the prescribed layers of 2D material 104 can generate a FET 100 that can yield a performance of at least ION ^::= 85pA/pm, can exhibit a contact resistance (Rc) of less than 2 kQ- pm, and/or can exhibit an ON/OFF current ratio > 10⁴.

[0070] Embodiments can relate to a method for generated a FET 100 structure. The method can involve forming three to six monolayers of 2D material 104 on a surface of a substrate 102 (e.g., the 2D material 104 can be formed on the surface of the substrate 102 via chemical vapor transport). The method can involve removing three to five monolayers of the 2D material 104 to generate a channel region 110. The channel region 110 can be between a source contact region 106 and a drain contact region 108. The source contact region 106 can include three to six monolayers of the 2D material 104. The drain contact region 108 can include three to six monolayers of the 2D material 104. [0071] Removal of the monolayers can involve a self-limiting etching technique (e.g., radio frequency (RF) plasma-based oxidation). The self-limiting etching technique can remove layers in a layer-by-layer fashion - e.g., it is self-limiting in that only one layer at a time can be removed. For instance, generating an exemplary FET 100 structure can involve forming six monolayers of 2D material 104 on a surface of the substrate 102. This can involve forming a first layer on the substrate 102, a second layer on the first layer, a third layer on the second layer, a fourth layer on the third layer, a fifth layer on the fourth layer, and a sixth layer on the fifth layer. The self-limiting etching technique can be used on the sixth layer to generate a passivating and sub-stoichiometric sixth layer, wherein the passivating and sub-stoichiometric sixth layer is dissolved (e.g., via an application of DI water). The self-limiting etching technique can be used on the fifth layer to generate a passivating and sub-stoichiometric fifth layer, wherein the passivating and sub-stoichiometric fifth layer is dissolved. RF plasma-based oxidation can be used on the fourth layer to generate a passivating and sub-stoichiometric sixth layer, wherein the passivating and sub-stoichiometric fourth layer is dissolved.

[0072] While the above example formed 6 layers and removed 3 layers, it is understood that more or less layers can be formed and more or less layers can be removed to meet a particular design criterion.

[0073] EXAMPLES

[0074] The following examples include exemplary implementations and test results of embodiments disclosed herein.

[0075] Doping plays a critical role in tailoring the characteristics of semiconducting materials and electronic devices. Specifically, in the context of field-effect transistors (FETs), degenerate doping in the silicon channel beneath the source and drain regions has become essential for achieving high-performance n- and p-type devices by significantly reducing contact resistance (R_c) In contrast, two-dimensional (2D) semiconductors have mainly relied on metal workfunction engineering to lower R_c. While this approach has proven successful for n-type 2D FETs due to the natural tendency of the metal Fermi level to align near the conduction band edge, it has been challenging to achieve the same for p-type 2D FETs. To address this, first, we demonstrate that degenerate p-type doping can be accomplished in thick (>3 monolayers) MoSe2 and WSe2 FETs through substitutional doping with V, Nb, and Ta. However, the degenerate doping leads to weakened electrostatic gate control, resulting in a poor on/off current ratio. Interestingly, the doping effectiveness is significantly reduced in thinner flakes (< 3 monolayers) due to strong quantum confinement effects, thereby restoring the electrostatic gate control.

Based on this observation, we designed a FET structure where the channel is constructed using thinner 2D material, while the contact regions consist of degenerately doped thicker layers, allowing us to achieve both low R_c and high on/off current ratio. The doping and device design approach we propose should be just as relevant for synthetic 2D materials and n-type 2D FETs. Our insights may steer the direction of large-scale synthesis methods, prioritizing the creation of doped multilayers over monolayers to further progress in 2D FET technology.

[0076] The emergence of two-dimensional (2D) semiconductors as potential alternatives to silicon in complementary metal oxide semiconductor (CMOS) technology, especially at aggressively scaled process nodes, is highly promising due to their atomically thin nature. Molybdenum (Mo) and tungsten (W) based semiconducting transition metal dichalcogenides (TMDs) such as M0S2, MoSe?, WSe2, etc. can be as thin as ~0.6 nm at the monolayer limit and yet offer atomically smooth and dangling bond-free surfaces that is difficult to achieve in bulk semiconductors when scaled to similar thicknesses. Substantial strides have been made in n-type field-effect transistors (FETs) based on 2D materials like M0S2 and WS2, bringing them closer to meeting the requirements set forth by the International Roadmap for Devices and Systems (1RDS). Achievements in high-quality material growth, contact engineering, aggressive channel length scaling, and high-k dielectric integration have contributed to this success. However, the progress of p-type 2D FETs has been significantly slower in meeting the performance standards. [0077] FIG. 9 shows Fermi-level pinning at metal/2D contact interfaces, wherein band alignment and band bending at metal/2D interface for panel a) transition metal sulfides such as M0S2 and WS2 and panel b) transition metal selenides such as MoSe2 and WSe2 is shown. In the case of M0S2 and WS2, the proximity between the metal Fermi level (E_F) and the conduction band (E_c) results in a decrease in the height of the Schottky barrier (SB) for electron injections (<[>SB-N), while simultaneously increasing the height of the SB for holes injection (4>SB— p ⁼ E_G — <|)SB-N) This situation presents a challenge to obtain high-performance in p-type 2D FETs based on M0S2 and WS2. In contrast, MoSe2 and WSe2 offer a more favorable scenario, with mid-gap pinning, lowering the height of the SB for hole injection. [0078] The absence of p-type transport in 2D TMDs is attributed to the phenomenon of Fermi level pinning at the metal/2D contact interfaces. In the case of transition metal sulfides like M0S2 and WS2, the pinning occurs near the conduction band edge (E_c) as illustrated in FIG. 9 (panel a). Consequently, achieving high-performance n-type 2D FETs is feasible for M0S2 and WS2 when low work-function metals like Sc, Bi, Sb, etc., are used as contact electrodes, which leads to near-zero Schottky barrier (SB) height for electron injection Nevertheless, this inherently gives rise to a substantial SB height for hole injection that remains unaffected even when high work-function metals such as Ni, Pd, Pt, etc. are employed, thereby contributing to significant contact resistance (Rc ) This challenge is further exacerbated in monolayers due to larger bandgap (E_G) values compared to corresponding multilayer bandgaps, explaining the absence of reported p-type FETs based on monolayer M0S2 and WS2. In contrast, in transition metal selenides like MoSe2 and WSe2, the metal Fermi level pinning occurs near the middle of the bandgap facilitating relatively easier hole injection as illustrated in FIG. 9 (panel b). However, due to the prevalence of tunneling injection across the SB as opposed to thermionic emission over the SB, 2D FETs utilizing MoSe2 and WSe2 exhibit diminished ON-state performance (I_0N). To achieve high-performance p-type 2D FET, one needs to reduce R_c either by eliminating ^or by reducing the SB tunneling distance Note that is the width of the depletion region at the metal/semiconductor interface, which is determined by the semiconductor doping (N_D) following Eq. 1.

[0079] In Eq. 1 is the permittivity of the semiconducting channel. The semiconductor industry has long adopted the strategy to reduce R_c for both n- and p-type FETs through degenerate doping of silicon (Si) underneath the contacts since Fermi level pinning occurs for metal-silicide junctions as well. The channel, however, is kept intrinsic or non-degenerately doped based on the threshold voltage requirements set forth by circuit designers. In other words, selected area substitutional doping plays a critical role in enabling high-performance Si FETs. For 2D FETs, a similar approach is necessary, but it presents its own challenges, which we will address in this study and propose a solution to overcome them.

[0080] In this study, we investigated 2D FETs based on pristine and V-, Nb-, and Ta-doped MoSe? and WSe2 single crystals flakes. While pristine flakes demonstrated dominant n-type transport irrespective of the flake thickness, FETs based on thick flakes (~4-6 monolayers) of these doped 2D crystals demonstrated degenerate p-type doping. In addition, these multilayer FETs also exhibited I_0N as high as ~ 1.8 mA/pm , better channel length scaling, and R_c as low as ~ 95 Q-pm. However, these FETs lacked electrostatic gate control resulting in poor on/off current ratio (< 20). Interestingly, as the thickness of the flake decreased, the effectiveness of doping also diminished due to quantum confinement effects, which can be explained using the density functional theory (DFT) calculations. We found that FETs based on thin flakes (~l-3 monolayers) demonstrate large on/off current ratio (> 10⁵) but were limited in I_ON (< 10 pA/pm) owing to high-/?_c > 25 kQ-pm. These findings underscored the significance of employing degenerate doping to decrease R_c as well as emphasized the necessity of maintaining a thin channel for improved electrostatics. Achieving this goal proves challenging when dealing with a uniformly thick 2D channel. This led us to design an FET structure where the channel consists of 3-4 layers of 2D material, whereas the contact regions are comprised of degenerately doped multilayers ( > 6 layers) allowing us to achieve both high I_0N (~85 pA/pm) due to low R_c ~ 2 kQ-pm and high on/off current ratio of > 10⁴ in a back-gated device. We also realized an aggressively scaled dual-gated FET with channel length, L_ch = 50 nm, and demonstrated even higher 1_ON ~ 212 pA/pm owing to better electrostatic control of the channel region. To implement this structure, a controlled layer-by-layer thinning method was used to reduce the thickness of the channel region to a monolayer while protecting the multilayer regions underneath the contacts. Overall, the design approach utilized for 2D FETs in this research can be expanded across diverse 2D materials, catering to both n- and p-type doping. Additionally, the approach can be extended to large-area synthetic 2D materials. Overall, this investigation underscores the significance of producing doped multilayer 2D materials on a wafer scale, shifting the focus from exclusive concentration on monolayer synthesis, and thereby propelling the advancement of 2D FET technology.

[0081] Layer thickness dependent doping efficacy in 2D materials [0082] FIG. 10 shows dopant concentration in V-, Nb-, and Ta-doped MoSe2 and WSe? crystals, wherein panels a), b), c, d), e), and f) are bar plots showing the dopant concentrations for V, Nb, and Ta, determined using inductively coupled plasma atomic emission spectroscopy (ICP-AES) for MoSe2 (panel a) and WSe2 (panel b), and dopant concentrations for V, Nb, and Ta are extracted using scanning electron microscopy-electron dispersive X-ray spectroscopy (SEM- EDS) (panel c) MoSe2 and WSe2 (panel d), and bulk carrier concentrations (NB) at room temperature is obtained from Hall measurements for MoSe2 (panel e) and WSe2 (panel f) doped with V, Nb, and Ta.

[0083] First, pristine, and doped MoSe2 and WSe2 single crystals were prepared using chemical vapor transport (CVT) technique introducing dopants such as V, Nb, and Ta, which belongs to group VB with different atomic radii. These dopants were selected based on prior DFT calculations, aiming to discover appropriate transition metal (TM) dopants capable of inducing p-type doping in single-layer WSe2. After the crystals were synthesized, inductively coupled plasma atomic emission spectroscopy (ICP-AES) was used to determine the bulk doping concentrations for various dopants as shown in FIG. 10 (panels a and b) for MoSe2 and WSe2, respectively. To confirm that the bulk doping concentration translates to micrometer scale flakes, energy dispersive X-ray spectroscopy (EDX) measurements were also performed using scanning electron microscopy (SEM) for various dopants and the results are summarized in FIG. 10 (panels c and d) for MoSe2 and WSe2, respectively. Clearly, the results from ICP-AES and SEM-EDX were found to be similar. The concentration of V, Nb, and Ta, were found to be less than 0.8 at.% and 0.4 at% for MoSe2 and WSe2, respectively. Furthermore, for both materials, the doping concentration for Ta was found to be the highest, whereas V-doping was the lowest. [0084] Although ICP-AES and SEM-EDX results validate the presence of incorporated dopants within the crystals, they do not ascertain whether the introduced dopant atoms attain electrical activation and contribute to the intended electronic properties of the semiconductor material. To address this, Hall measurements were conducted to determine the carrier concentration and type, providing a comprehensive assessment of the material’s electrical behavior. FIG. 10 (panels e and f) show the room temperature bulk carrier concentrations (N_B) obtained from Hall measurements for V-, Nb-, and Ta-doped MoSe2 and WSe2, respectively. For all dopant variations in both materials, the carrier concentrations were consistently identified as p-type. For MoSe2, N_B values were found to be 1.51* 10¹⁹ cm'³, 1.57* 10¹⁹ cm'³, and 5.36x 10¹⁹ cm'³ for V-, Nb-, and Ta-doped crystals, which corresponds to active dopant concentration of -0.08 at.%, -0.085 at.%, and -0.285 at.%, respectively. For WSe2, N_B values were found to be 1 .74x10¹⁹ cm'³, 2.13xl0¹⁹ cm'³, and 1.91 x lO¹⁹ cm'³ for V-, Nb-, and Ta-doped crystals, which corresponds to active dopant concentration of -0.115 at.%, -0. 14 at.%, and -0. 125 at.%, respectively. These results confirm partial electrical activation of the respective dopant atoms in the corresponding bulk crystals. FIG. 11 shows electrical characterization of pristine MoSe2 and WSe2 FETs, wherein transfer characteristics for thick (-4-6 monolayers) (panel a) and thin (-1-3 monolayers) (panel b) MoSe2 FETs, and transfer characteristics for thick (-4-6 monolayers) (panel c) and thin (-1-3 monolayers) (panel d) WSe2 FETs are shown.

[0085] Next, field-effect transistors (FETs) were fabricated using exfoliated flakes from these crystals on a Si-substrate featuring a global back-gate stack of 50 nm AI2O3, grown via atomic layer deposition (ALD), on top of electron beam (e-beam) evaporated Ti/Pt. To define the source and drain contacts, e-beam lithography was employed, followed by e-beam evaporation of 40/30 nm Pd/Au as the contact metal. The utilization of Pd is driven by its high work-function, which facilitates more efficient hole injection. FIG. 11 (panels a and b) show the transfer characteristics, e.g., source-to-drain current (J_DS) as a function of the back-gate voltage (V_BC) for a constant source-to-drain bias of, V_DS = 1 V, for representative thick (-4-6 monolayers) and thin (-1-3 monolayers) pristine MoSe2 FETs. FIG. 11 (panels c and d) show similar results for pristine thick and thin WSe2 FETs, respectively. All FETs have a channel length (L_CH) of 500 nm. Note that, it is difficult to confirm whether the n-type doping observed in FETs based on pristine MoSe2 and WSe2 are due to impurities present in the as grown materials or from the substrate. We note that the substrate used for our device fabrication, i.e., ALD-grown A12O3, which is known to introduce n-type doping in 2D semiconductors. Furthermore, metal Fermi level pinning can also influence the observed n-type transport. According to our experimental results, both TMDCs display dominant n-type transport behavior with comparatively weaker hole branches. This observation indicates that the metal Fermi level is pinned closer to the middle of the bandgap, exhibiting greater proximity to the conduction band rather than the valence band. [0086] FIG. 3 shows the transfer characteristics for several thick (~4-6 monolayers) and thin (~l-3 monolayers) V-, Nb-, and Ta-doped MoSe2 FETs, respectively. In FIG. 3, transfer characteristics, i.e., source-to-drain current (I_DS) as a function of the back-gate voltage (V_BG) for a constant source-to-drain bias of V_DS = 1 V for V- (panel a), Nb- (panel b), and Ta- (panel c) doped MoSe2 FETs with thick (~4-6 monolayers) channels. These FETs show high on-state current (I_0N) and poor electrostatic gate control (low ION/IOFF) confirming degenerate p-type doping. In contrast, transfer characteristics for V- (panel d), Nb- (panel e), and Ta- (panel f) doped MoSe2 FETs with thin (~l-3 monolayers) channels retained high ION/IOFF more than 10⁵. However, I_ON values were significantly lower. Corresponding scatter plots with I_0N measured at V_BG = -15 V and IQN/IOFF as the two axes for V- (panel g), Nb- (panel h), and Ta- (panel i) doped FETs with thick and thin MoSe2 channels. All FETs have a channel length (L_CH) of 500 nm.

[0087] FIG. 12 shows similar results for V-, Nb-, and Ta-doped thick and thin WSe2 FETs, respectively. FIG. 12 shows substitutionally doped p-type WSe2 FETs. In FIG. 12, transfer characteristics, i.e., source-to-drain current (I_DS) as a function of the back-gate voltage (V_BG) for a constant source-to-drain bias of V_DS = 1 V for V- (panel a), Nb- (panel b), and Ta- (panel c) doped WSe2 FETs with thick (~4-6 monolayers) channels. These FETs show high on-state current (IQN) (except for the case of V-doped \VSe2) and poor electrostatic gate control (low IQN/IOFF) confirming degenerate p-type doping. In contrast, transfer characteristics for V- (panel d), Nb- (panel e), and Ta- (panel f) doped WSe2 FETs with thin (~l-3 monolayers) channels retained high IQN/IOFF more than 1 CP. However, I_0N values were significantly lower. Corresponding scatter plots with I_0N measured at V_BG = -15 V and IQN/IOFF as the two axes for V- (panel g), Nb- (panel h), and Ta- (panel i) doped FETs with thick and thin \VSe2 channels. All FETs have a channel length (L_CH) of 500 nm. . While degenerate p-type doping is seen in FETs with thick channels for both materials, irrespective of the dopant type, none of the FETs based on thick flakes could be turned off using the gate voltage (V_BG) range of -15 V to 15 V, resulting in poor current on/off ratios (JON/IQFF)- Iⁿ contrast, the FETs based on thin channels were found to be non-degenerately doped irrespective of the dopant type for both MoSe2 and WSe2, enabling the retention of electrostatic gate control and resulting in I_ON/I_OFF exceeding 10⁵. Although these thin FETs show ambipolar transfer characteristics, it is reasonable to assert that the incorporation of V, Nb, and Ta dopants resulted in p-type doping, even within thinner flakes. This assertion is supported by the fact that the intrinsic materials exclusively exhibited n- type unipolar transport. As we will elucidate later using DFT calculations, the ambipolar transport is also facilitated due to bandgap narrowing in doped MoSe2. FIG. 3 (panels g-i) and FIG. 12 (panels g-i) show the scatter plots for these V, Nb-, and Ta-doped FETs with thick and thin MoSe? and WSe2 channels with I_0N values measured at using and a^s the two axes, respectively. Clearly, the MoSe2 FETs with thicker channels demonstrate median l_0N values of -38 pA/pm, ~ 45 pA/pm, and -100 pA/pm for V, Nb, and Ta dopants, whereas, the median I_0N values dropped to 1.4 pA/pm, - 2.5 pA/pm, and -10 pA/pm for the same dopant type for the MoSe2 FETs with thinner channels, respectively. However, the median was found to be very poor, -2, -68, and -3 for the MoSe2 FETs with thicker channels for V, Nb, and Ta dopants, respectively, whereas all thinner channel FETs demonstrated irrespective of the dopant type. Similar results were obtained for doped WSe2 FETs as evident from FIG. 12. FIG. 28 shows the schematic for thin and thick 2D FETs. FIG. 28 (panel a) shows a MoSe2/WSe2 based 2D FET with a thick channel (-4-6 monolayers) while FIG. 28 (panel b) shows the same for a thin channel (-1-3 monolayers). FIG. 13 shows optimized atomic structures used for DFT simulation, wherein an optimized structure of 5X5X1 supercell for lL-MoSe2 (panel a), 4X4X2 supercell for 2L-MoSe2 (panel b), 2X2X8 supercell of 8L-MoSe2 (panel c), V, Nb and Ta doped !L-MoSe2 (panel d), 2L-MoSe2 (panel e), and 8L-MoSe2 (panel f) are shown. All the axis for the respective optimized structure is also shown. FIG. 4 shows electronic band structure of pristine and doped MoSe2, wherein the band structure of pristine (panel a) and V- (panel b), Nb- (panel c), and Ta- (panel d) doped 2H-phase MoSe2 for single-layer (IL), double-layer (2L), and eight-layer (8L) optimized structure is shown. A bar plot showing the relative position of Fermi level (E_F) with respect to the valence band (E_v), i.e., E_F — E_v for IL, 2L and 8L-MoSe2 for each of the group VB dopants is shown in panel e. A bar plot showing band gap (E_G) for pristine as well as V-, Nb- and Ta-doped MoSe2 for each thickness is shown in panel f. In order to comprehend the FET characteristics that vary with the thickness of the doped MoSe2 layers, we conducted DFT-driven band structure calculations. These calculations reveal the precise position of the Fermi level (E_F) within the doped MoSe2 samples. FIG. 13 (panels a-d) show the atomic structures used for DFT simulation and FIG. 4 (panels a-d) show the calculated electronic band structure for pristine and V-, Nb-, and Ta-doped 2H-phase MoSesfor single-layer (IL), double-layer (2L), and eight-layer (8L) configurations, respectively. While IL-MoSez exhibits a direct (K-K) band gap (E_G) of -1.44 eV, 2L-, and 8L-MoSe2 display indirect (T-K) E_G of -1.09 eV and -0.91 eV, respectively, which are consistent with previously documented findings. The intrinsic Fermi-level (£_F), as expected, were found to be located mid-gap, irrespective of the layer thickness in pristine MoSe2.

However, E_p was found to be shifted below the valence band maximum (E_v) near the K-point of the Brillouin zone for lL-MoSe2, and at the T point for both 2L- and 8L-MoSe2 for V-, Nb-, and Ta-doped crystals. While the exact location of E_F differed across dopant types and layer numbers as shown in FIG. 14, the consistent observation of E_F being positioned below E_v confirmed degenerate p-type doping of MoSe2 for each of V, Nb, and Ta dopants at -3% atomic doping, which were used for the DFT calculations. FIG. 14 shows band alignment of pristine and dopedlL, 2L and 8L-MoSe2. In this observation, it is evident that the introduction of V, Nb, and Ta doping results in a reduction of the band gap, and there is also a notable shift of the Fermi level below the valence band.

[0088]

[0089] FIG. 4 (panel e) shows E_v — E_F for different layer thicknesses for each of the dopants. Clearly, the shift in E_F are more prominent in 8L- and 2L-MoSe2 as compared to !L-MoSe2 for all dopant types. For example, in the case of Nb doping, E_v — E_F - 30 meV, -200 meV, and -300 meV, for 1L-, 2L, and 8L-MoSe2, respectively. This can be explained from the shifts in the electronic band structure caused by the quantum confinement effect in thinner layers. In addition, while the pristine band structure of IL, 2L, and 8L MoSe2 remained largely intact after doping, a reduction in the magnitude of E_G is evident in doped MoSe2 as illustrated in FIG. 4 (panel f). For example, E_G values were found to be reduced from 0.9 eV to 0.53 eV, 0.51 eV, and 0.5 eV for V-, Nb, and Ta-doped 8L-MoSe2, respectively. This effect stems from the disparity in atomic radii between the Mo atom and the transition metal dopants, leading to lattice strain. The E_G narrowing is proportional to the amount of strain, which is directly connected to the atomic radii, with V having the smallest atomic radius and Ta having the largest. Similar trends were observed for 2L- and !L-MoSe2 as well. However, as evident, the impact of strain induced E_G narrowing is found to be minimal for !L-MoSe2. These observations also align with the results obtained from the analysis of the projected density of states (PDOS) as shown in FIG. 15 (FIG. 15 shows projected density of states (PDOS) for pristine and doped MoSe2, and in particular projected density of states (PDOS) for pristine IL, 2L and 8L-MoSe2 with -3 atomic percentage of V, Nb and Ta doping in each structure.). It is also worth mentioning that while QCE impacts the position of Er and Ec, the energetic positions of the dopant states, which are localized within material layers, are less affected by QCE compared to the band edges. As a result, the energy gap between dopant states and band edges increases as the layer thickness decreases, which in turn lowers the efficiency of dopant activation. DFT results, however, fail to account for the absence of degenerate doping in experimental devices featuring thin channels. This discrepancy arises due to the significantly elevated (> 10x) doping concentration employed in DFT simulations at 3% atomic doping, amounting to over -30,000 ppm, which stands in contrast to the doping concentrations achieved in actual synthesized crystals. This deliberate adjustment was made to reduce the computational demands, given that the size of the unit cell used for DFT calculations becomes unmanageably large when the dopant concentration is too minimal. However, DFT calculations are able to confirm the experimental observation on layer thickness dependent dopant efficacy in MoSe2. FIG. 16 shows field effect mobility (PFE) and 4- point probe mobility (p_4PP) for MoSe2 and WSe2 FETs, wherein hole field-effect mobility (PFEX extracted from peak transconductance for thick channel (panel a) and thin channel (panel b) FETs based on V-, Nb-, and Ta-doped MoSe2 and for thick channel (panel c) and thin channel (panel d) FETs based on V-, Nb-, and Ta-doped WSe?, and bar plots showing the 4-point probe mobility (p_4PP) extracted from Hall measurement for holes for MoSe2 (panel e) and WSe2 (panel f) specimens with dopants V, Nb, and Ta are shown.

[0090] FIG. 16 shows the field effect mobility values for holes extracted from the peak transconductance for and Ta-doped MoSe2 and WSe2 FETs, respectively. We found that the thicker flakes have better p._PE values in the range of 5-10 for both Nb- and Ta- doped MoSe2 and WSe2. In comparison thinner flakes were found to possess This can be attributed to higher R_c values associated with the thinner flakes. We also found lower fi_PE values for V-doped samples irrespective of the flake thickness for both MoSe2 and WSe2. Since, values are known to be prone to measurement artifacts, we also extracted the 4-point probe (4PP) mobility for the bulk samples using Hall measurements. [0091] FIG. 16 (panels e-f) show values for and Ta-doped MoSez and respectively. Although the specific values vary', the /i_PE and measurements were observed to be within a comparable range.

[0092] Impact of degenerate doping on contact resistance

[0093] As mentioned earlier, degenerate doping has played a crucial role in optimizing the performance of Si FETs by reducing R_c, improving carrier injection efficiency, and enhancing overall device characteristics. FIG. 17 shows a scanning electron microscope (SEM) image of a representative TLM structures used for extracting R_c from MoSe2 FETs with Pd/Au contacts. FIG. 5 (panel a) shows the transfer characteristics of “best-performing” V-, Nb-, and Ta-doped thick MoSe? FETs taken at V_DS = 1 V, for L_CH = 50 nm, 100 nm, 200 nm, and 500 nm. Note that Nb- and Ta-doped p-type MoSe2 FETs can achieve I_0N as high as 1.8 mA/pm and 0.83 mA/pm, respectively, for L_CH = 50 nm, albeit weak electrostatic gate control leading to poor IQN^OFF- FIG. 5 (panel b) shows the total resistance R_T (normalized by width) measured at V_BG = -8 V versus L_CH for these V-, Nb-, and Ta-doped thick MoSe2 FETs, respectively. Next, Eq. 2 is used to extract R_c.

[0094] As indicated by Eq. 2, R_CH decreases as L_CH is scaled. R_c, however, is independent of L_CH and can thus be extracted from the y-intercept of the given R_T versus L_CH plots, albeit as 2R_C. The slope of the linear-fit line represents the sheet resistance FIG. 5 (panel c) shows the bar plot for R_c extracted for V-, Nb-, and Ta-doped MoSe2 FETs with different flake thicknesses, respectively. It is important to recognize that for sufficiently thick flakes (> 10 layers), the values for V-, Nb-, and Ta-doped MoSe2 can be as low as -740 Q-pm, 95 Q-pm and 125 Q-pm, respectively. FIG. 18 displays I_0N as a function of L_cfl for a supply voltage of following Eq. 2 for these values obtained experimentally. Note that, even with a value as high as 20 , achieving an I_ON > 1 mA/pm is feasible for Nb- and Ta- doped MoSe2 FETs when the channel length is reduced to L_ch < 15 nm. These findings highlight the importance of degenerate doping in lowering R_c to meet the IRDS requirements for high- performance FETs in advanced technology nodes.

[0095] A new approach to 2D FET design [0096] FIG. 6 shows an exemplary embodiment of a 2D FET design. FIG. 6 (panel a) is a schematic of our proposed 2D FET architecture involving thicker multilayer (~4-6 monolayers) channel beneath the source and drain contacts, while maintaining a thinner channel (~l-3 monolayers) region between the contacts. The thicker channel enables degenerate p-type doping and thereby reduce R_c while enhancing I_ON, whereas the thin channel ensures precise electrostatic gate control, resulting in high I_ON/IOFF - FIG 6 (panel b) shows a cross-sectional scanning transmission electron microscopy (STEM) image in high-angle annular dark-field (HAADF) mode and the accompanying energy-dispersive X-ray spectroscopy (EDS) elemental mapping of the fabricated prototype 2D FET device. The channel maintains a thickness of approximately 6 monolayers beneath the source and drain contacts, while remaining thin (3 monolayers) between these contacts. Three consecutive cycles of oxygen plasma treatment, followed by immersion in water was carried out to thin the central channel region layer-by-layer. FIG. 6 (panel c) shows transfer characteristics of the Nb-doped MoSe2 FET before and after plasma treatment for L_CH = 100 nm. The on-state performance is largely retained, with high I_0N of 85 pA/pm at V_DS = 1 V while the I_0N /l_0FF is substantially enhanced from ~3 to ~4x 10⁴.

[0097]

[0098] We present a design aimed at optimizing the performance of p-type 2D FETs by carefully manipulating three key parameters: low-/?_c, high-/_ow, and precise gate control to achieve high- ION^OFF - This approach involves tailoring the thickness of the 2D channel material to achieve the desired outcomes. Drawing from experimental findings, where low RC was observed in thicker, multilayered Nb-doped MoSe2 and enhanced gate control was achieved in its monolayer form, we propose a transistor architecture that combines these advantages. As shown in FIG. 6 (panel a), our proposed design involves maintaining a thicker multilayer structure (~4-6 layers) beneath the source and drain contacts, while ensuring the central channel region between the contacts remains thin (~l-3 layers) to preserve effective gate control. To achieve controlled thinning of substitutionally doped multilayered 2D materials, we employ a self-limiting etching technique. Specifically, we utilize mild RF plasma-based oxidation of the top layer, resulting in the formation of a passivating and sub-stoichiometric MoOs layer that can be selectively dissolved in DI water. In other words, this technique allows for layer-by-layer removal of the 2D channel region between the contacts, while leaving the material beneath the contacts untouched. [0099] FIG. 19 shows layer by layer thinning of multilayer MoSe2 flake. FIG. 19 (panel a) shows optical images of MoSe2 flakes taken before and after successive treatment with mild oxygen plasma followed by DI water rinse to remove the top-layer of MoO_x. The layer-by-layer thinning is evident from the contrast of the flakes that transitions from a deep brown hue to a lighter shade of brown. FIG. 19 (panel b) shows AFM images of the evolution of layer-by-layer thinning of MoSe2 flakes subjected to O2 plasma. Each plasma step is followed by a DI water dip before subsequent AFM measurements. The height profile of the flake along line 1 is also depicted and reveals a reduction of about 0.8 nm after each plasma step suggesting the removal of a single layer of MoSe2 flake.

[00100] FIG. 19 (panel a) shows optical images confirming the layer-by-layer thinning of Nb-doped multilayer MoSe2 flakes. Additionally, FIG. 19 (panel b) presents atomic force microscopy (AFM) images alongside their respective height profiles for another multilayer Nb- doped MoSe? flake subjected to five rounds of plasma thinning process. Evidently, there is a reduction in layer thickness of approximately 0.8 nm after each etching cycle, which substantiates the occurrence of layer-by-layer etching.

[00101] A comprehensive visual representation of the ultimate prototype 2D FET device is presented in FIG. 6 (panel b) using the cross-sectional scanning transmission electron microscopy (STEM) image in high-angle annular dark-field (HAADF) mode and the accompanying energy-dispersive X-ray spectroscopy (EDS) elemental mapping. Clearly, as designed, the channel remains thick (~ 6 monolayers) beneath the source and drain contacts and thin (3 monolayers) between the contacts.

[00102] FIG. 20 shows atomic resolution imaging of Nb-doped MoSe2 FETs. HAADF- STEM images revealing the cross-sectional TLM structure with channel lengths of 50 nm, 100 nm, and 200 nm. The structure showcases thicker channels beneath the contacts and thinned- down channels between the contacts. Note that we carried out three successive rounds of oxygen plasma treatment, followed by immersion in water. FIG. 20 shows the HAADF-STEM image of the entire TLM structure with thick channels underneath the contacts and thinned down channels between the contacts. The resulting transfer characteristics of the Nb-doped MoSe2 FET before and after plasma treatment are shown in FIG. 6 (panel c) for L_CH = 100 nm. Clearly, the on-state performance is largely retained, while the 1_ON/IOFF is substantially enhanced from ~3 to ~4>< 10⁴. [00103] FIG. 21 shows as-fabricated and post-processed Nb-doped MoSe2 FETs. Transfer characteristics of as-fabricated (FIG. 21 panel a) and post-processed (FIG. 21 panel b) Nb-doped MoSe2 FETs with L_CH = 50 nm, 100 nm, 150 nm, 200 nm, and 500 nm are shown. Three successive rounds of oxygen plasma treatment, followed by immersion in DI water, were carried out to reduce the thickness of the channel between the contacts while keeping the channel thicker underneath the contacts. FIG. 21 (panel c) shows corresponding total resistance R_T (normalized by width) measured at V_BG = -15 V versus L_CH for as-fabricated and post-processed Nb-doped MoSe2 FETs. FIGS. 21 (panels a-c) show the transfer characteristics of the Nb-doped MoSe2 LCH and the extracted Rc before and after the plasma treatment. Clearly, _c, a significant hurdle in achieving efficient p-FET performance, remains consistently low even after the controlled layer-by-layer thinning. The R_c value was found to be around resulting in high I_0N of 85 pA/pm for a device with L_CH = 100 nm = 1 V and for a carrier concentration of n_s ~ 2* 10¹³ cm’². Similar results were also obtained for Ta-doped MoSe2 FETs as illustrated in FIG. 22. FIG. 22 shows as-fabricated and post-processed Ta-doped MoSe2 FETs. Transfer characteristics of as-fabricated (panel a) and post-processed (panel b) Ta-doped MoSe2 FETs with 100 nm, 200 nm, and 500 nm are shown. Three successive rounds of oxygen plasma treatment, followed by immersion in DI water, were carried out to reduce the thickness of the channel between the contacts while keeping the channel thicker underneath the contacts. FIG. 22 (panel c) shows corresponding total resistance (normalized by width) measured at versus L_CH for as-fabricated and post-processed Ta-doped MoSe2 FETs. Clearly, the on-state performance is largely retained, while the is substantially enhanced from -15 to ~10⁴. The R_c value for post-processed Ta-doped MoSe2 FETs was found to be around 5 kQ-pm, resulting in high I_ON of -100 pA/pm for a device with L_CH = 100 nm at V_DS = 1 V. Here as well, the on-state performance is largely retained, while the is substantially enhanced from -15 to -10⁴ after thinning the channel regions between the contacts. The R_c value for post-processed Ta-doped MoSe2 FETs was found to be around 5 k£l-pm, resulting in high I_0N of -100 pA/pm for a device with L_CH = 100 nm at Fps = 1 V. The increases in R_c after the channel etching process can be explained using a simple resistor network model illustrated in in FIG. 23. FIG. 23 shows resistor network for carrier transport in our proposed 2D FET. FIG. 23 (panel a) shows a resistor network with essential resistance components associated with carrier transport in our proposed 2D FET structure. FIG. 23 (panel b) shows a schematic and corresponding band-diagrams for MoSes based 2D FETs with thick channels underneath the contacts and multilayer channels between the contacts. FIG. 23 (panel c) and FIG. 23 (panel d) show the corresponding shows a schematic and band-diagrams for bilayer and monolayer channels between the contacts respectively. The bandgap mismatch between thicker and thinner regions increases giving rise to an additional energy barrier at the interface between the thinner channel and thicker contact regions. This energy barrier remains relatively small for channels over 2 layers, as the MoSe2 bandgap stays nearly constant. However, the barrier height can increase markedly when the channel becomes monolayer, due to the transition from indirect to direct bandgap between bi-layer and monolayer. This alteration can lead to a considerable increase in Rc. FIG. 23 (panel c) shows transfer characteristics of a multilayer Nb-doped MoSe2 FET after each etch cycle, and FIG. 23 (panel d) shows corresponding bar plot of the R_c values obtained from TLM measurements.

[00104] FIG. 23 shows a resistor network that describes the essential resistances associated with carrier transport in our proposed 2D FET structure involving a thinner channel between the contacts and a thicker channel underneath the contacts. We categorize the resistance components as follows: 1) , the resistance offered by the thin channel between the contacts , the resistance of the thicker channel under the contacts, incorporating the metal/channel interface resistance due to the Schottky barrier, and 3) the resistance at the interface between thick and thin channels. The sum of and constitutes the contact resistance, R_c, and hence the total resistance (R_T) of the FET is given by the equation R_T =

[00105] Note that, as the channel is thinned down, - remains constant since the channel underneath the contacts remain untouched. However, as depicted in FIG. 23 (panel b) through schematic and band-diagrams, R_Tt increases with the thinning of the channel due to the bandgap mismatch between thicker and thinner regions. The bandgap of multilayer MoSej is ~1.1 eV, which increases to ~1.5 eV in a monolayer film due to the quantum confinement effect. This bandgap mismatch gives rise to an additional energy barrier for carrier injection into the thinner channel from the thicker regions. This energy barrier remains relatively small for channels over 2 layers, as the MoSej bandgap stays nearly constant until reduced to a bilayer. However, the barrier height can increase markedly when the channel becomes monolayer, due to the transition from indirect to direct bandgap between bi-layer and monolayer. This alteration can lead to a considerable increase in R_c. Therefore, it's preferable to maintain the channel between the contacts at more than one layer. FIG. 23 (panel c) illustrates the transfer characteristics of a multilayer Nb-doped MoSes FET after each etching step, and FIG. 23 (panel d) shows the corresponding R_c values from TLM measurements. The R_c values remain nearly constant at -200 Q-pm until the 4* etching iteration but increases to -1.2 kQ-prn after the 5^th iteration. Beyond this point, the device fails, indicating the initial flake was about 6 layers thick. In other words, R_Tt shows minimal increase until the channel is thinned to 2 layers but rises significantly when it becomes monolayer confirming the resistor network model described above

[00106] High-performance dual -gated p-type 2D FETFIG. 7 shows an exemplary high- performance p-type dual-gated 2D FET. FIG. 7 (pane a) shows a schematic, FIG. 7 (panel b) shows a high-resolution cross-sectional transmission electron microscope (HRTEM) image, and FIG. 7 (panel c) shows an energy-dispersive X-ray spectroscopy (EDS) elemental mapping of a representative dual-gated Nb-doped MoSe2 FET with thicker channel underneath the source/drain contacts and thinner channel between the contacts. FIG. 7 (panel d) shows mapping for each element within the dual-gated FET structure. FIG. 7 (panel e) shows transfer characteristics of a representative FET with the structure presented in panel a), where the back gate voltage (V_BG) is swept from -8 V to 8 V while stepping the top gate voltage (V_TG) from -10 V to 10 V. The drain bias was IV. FIG. 7 (panel f) shows transfer characteristics of the same devices in both linear and logarithmic scale when the top and bottom gates are shorted and the voltage applied to the dual gate (VDG) is swept from -10 V to 10 V with an applied drain bias of IV. FIG. 7 (panel g) shows a bar plot illustrating the maximum ON current (I_ON ) f°^r four devices, with the highest I_ON reaching 212 pA/pm and median I_0N of 160 pA/pm. FIG. 7 (panel h) shows corresponding current ON/OFF ratio, ION/OFF f°^{r eac}h device, with the highest IQN/OFF reaching 10⁵ and median ION/OFF of 3.3>< 10⁴.

[00107] To further improve the performance of our proposed p-type 2D FET, we have scaled the channel length down to L_ch = 50 nm and improved the electrostatic control of the channel by introducing a dual-gated device geometry. FIG. 7 (panels a-d), respectively, show the schematic, cross-sectional HRTEM image of a representative dual-gated Nb-doped MoSe2 FET with thicker channel underneath the source/ drain contacts, and thinner channel between the contacts with accompanying energy-dispersive X-ray spectroscopy (EDS) elemental mapping. As evident from these images, we have used 20 nm and 25 nm thick AhCh as the top and bottom gate dielectrics grown using ALD, respectively. We have also used Pt/Ti and Ni/Au as the bottom and top gate electrode, and Pd/Au as the source/drain metal contacts. Employing metals with high work functions for the source, drain, and gate electrodes provides the optimal opportunity to realize high-performance p-type 2D FETs.

[00108] FIG. 7 (panel e) shows a series of transfer characteristic of a representative dualgated FET, with the structure presented above, where the back gate voltage is swept from - 8 V to 8 V while stepping the top gate voltage (V_T6) from -10 V to 10 V. Note that, highest I_0N is achieved when both the bottom- and top-gate voltages are negative allowing maximum charge accumulation in the channel. Similarly, the highest IQN/^OFF obtained when both the bottom- and top-gate voltages are positive allowing maximum charge depletion in the channel. In other words, when both gates work in conjunction it is possible to achieve better electrostatic control of the channel compared to a single gate FIG. 7 (panel f) shows the transfer characteristics of the same devices when the top and bottom gates are shorted, and the voltage applied to the dual gate (V_DG) is swept from -10 V to 10 V. Clearly, dual-gated Nb-doped MoSe2 FETs (DGFETs) with thin channel between the contacts and thicker channel underneath the contacts is able to demonstrate and at the same time display allowing us to surpass p-type FET performance better than previous demonstrations. FIG. 7 (panels g-h) show⁷ bar plots for and for several p-type 2D DGFETs. The median _N and were found to be 160 pA/pm and 4.4><10³, respectively.

[00109] In the above context, we also wish to highlight the rarity and significance of successfully implementing a dual-gated 2D FET within the 2D device community. Firstly, the challenge of depositing high-quality ALD films on 2D materials is substantial, primarily due to the inert nature of their basal planes. Secondly, while there have been some reports on successful top-gate device fabrication, there is often a notable disparity in the electrostatic strength between the top and bottom gates. This discrepancy is usually attributed to thicker and low-k back gate dielectric, which leads to a higher effective oxide thickness (EOT), compared to the thinner and high-k top gate dielectric that offers a low⁷er EOT. Such differences hinder effective dual-gate operation, as applying the same voitage to both gates are not feasible. This manuscript presents an efficient or possibly the only demonstration of a dual-gated 2D FET that achieves a comparable electrostatic strength between the top and bottom gates. Thi s method allows for improved control, leading to the development of p-type 2D FETs that outperform previous demonstrati ons.

[00110] FIG. 24 shows the output characteristics of a high-performance Nb-doped MoSe2 FET measured at and 300 K, respectively The output characteristics exhibit more Schottky-type behavior at 25 K and becomes linear at 300 K. FIG. 25 shows Schottky barrier (<PSB-P) heights for doped and WSe? FETs and temperature dependence of output characteristics for Nb-doped MoSe2 DGFETs. values were obtained for pristine, V-, Nb-, and Ta-doped MoSe2 (FIG. 25 (panel a)) and WSe? FETs (FIG. 25 (panel b)). FIG. 25 (panel c and d show schematic of band diagrams for intrinsic and heavily p-type doped semiconductors in contact with a metal. FIG. 25 (panel e) shows a band diagram portraying the broadening of the Fermi-Dirac tail with increasing temperature, providing additional holes for tunnelling through the narrower region of the Schottky barrier. The enhanced tunnelling of holes results in a Ohmic like characteristics at higher temperatures. Output characteristics measured at a constant VBG of -8 V as the temperature is increased from 75 K to 300 K. The output characteristics transitioned from mostly Schottky type to nearly Ohmic-like. We extracted the Schottky barrier (SB) heights for hole injection (</>SB-P) iⁿ pristine, and V-, Nb-, and Ta-doped MoSe2 and WSe2 for Pd contacts as shown in FIG. 25 (panels a and b), respectively. The values were found to be -500 meV for MoSe2 and -800 meV for WSe2 with Pd contacts, regardless of dopant type. This is expected since doping does not typically change the SB height at metal-semiconductor contacts, which is primarily determined by the work function of the contact metal and the electron affinity or bandgap of the semiconductor. However, doping does impact the SB width (T_SB-P ) at the metal/2D interface, with heavier doping resulting in a narrower barrier, as illustrated using the energy band diagrams in FIG. 25 (panels c-d). Additionally, FIG. 25 (panel e) presents the output characteristics at small drain biases, ranging from -100 mV to 100 mV, across different temperatures spanning 75 K to 300 K, A noticeable increase in linearity with temperature is observed, which can be attributed to the temperature-assisted tunneling process at the metal/2D contact interfaces with large SB heights At higher temperatures, Fermi-level broadening allows more carriers to tunnel through the thinner part of the SB, increasing the tunneling current and giving the output characteristics a more linear appearance. This observation challenges a common misconception in the field that linear output characteristics results from Ohmic contacts. Even at low temperatures, output characteristics can appear linear for a SB contact if sufficient tunneling is enabled, a result of reduction through degenerate doping.

[00111] Towards large-area doped p-type 2D FETs

[00112] FIG. 8 shows electrical characterization of Nb-doped CVD-grown large-area MoSe? FETs. FIG. 8 (panel a) shows an 20X optical image of Nb-doped large-area MoSe? film grown using CVD. The film predominantly consists of monolayers with some bi-, tri- and multilayer regions. FIG. 8 (panel b) shows a 100X optical image of each of the mono-, bi-, tri- and multi-layer regions are shown. FIG. 8 (panel c) shows an optical image and FIG. 8 (panel d) shows transfer characteristics of FETs fabricated with mono-, bi-, tri- and multi-layer Nb-doped MoSe? as the channel. The devices have an L_CH = 200 nm and W_CH =1 pm, respectively. While the monolayer MoSe2 FETs showed a stronger n-type transport compared to p-type transport, with increasing thickness of the film, the FETs exhibited a distinct p-type behavior which can be attributed to the presence of larger concentrations of Nb atoms in the multilayered films. While our study on exfoliated flakes play a crucial role in guiding the materials science field toward focusing on key areas relevant to device research, we recognize the scalability limitations of the CVT method. Therefore, we have made some preliminary effort on growing Nb-doped MoSe2 using the chemical vapor deposition (CVD) technique as evident from the optical image shown in FIG. 8 (panel a). It should be noted that although the film is predominantly monolayer, there are also regions with bi-layer, tri-layer, and multi-layer structures, as illustrated in FIG. 8 (panel b). The growth details are provided herein.

[00113] FIG. 26 shows spectroscopic characterization of Nb-doped CVD-grown large- area MoSe2. FIG. 26 (panel a) show Raman spectra obtained from mono-, bi-, tri- and multilayer MoSe2 films showing the characteristic A_lg and E^g peak. The B^g can be seen in both the bi-layer and tri-layer regions, attributed to the interlayer interaction. FIG. 26 (panel b) show photoluminescence (PL) spectroscopy of mono-, bi-, tri- and multi-layer MoSe2 films. While the PL signal is very high for the monolayer films, attributed to the direct bandgap in these films, a sharp PL quenching was observed in the bi-, tri- and multi-layer films.

[00114] FIG. 26 shows the Raman and PL spectra obtained from the mono-, bi-, tri-, and multi-layer regions of the Nb-doped MoSes film indicating high quality of the CVD-grown MoSei films. Next, we transferred these films onto a global back-gate substrate with a 25 nm layer of ALD-grown AI2O3 and constructed FETs with a channel length of 200 nm and width of 1pm, as depicted in FIG. 9 (panel c). While degenerate doping was not observed in films of any channel thickness, a distinct pattern emerges in the transfer characteristics with the increase in channel thickness, as shown in FIG. 8 (panel d). The monolayers exhibit stronger n-type than p- type conduction, but as we move to bi-layer, tri-layer, and multi-layer structures, the p-type conduction intensifies, with the multi-layers displaying the highest I_ON at 5 pA/pm. We believe that the concentrations of Nb dopant in these films were not high enough to cause degenerate doping. Nonetheless, the findings from CVD-grown large-area films align with our findings on exfoliated flakes and DFT calculations. Both studies suggest a diminishing effectiveness of dopants as the layer thickness decreases. In other words, for achieving degenerately doped contact regions, growth of multilayer films are important. In our future work, we will aim to optimize the CVD growth of multi-layer and doped MoSez films.

[00115] Benchmarking Discussion

[00116] A benchmarking table showing the advances demonstrated in this work over previous attempts at achieving high performance p-type 2D FETs is provided FIG. 27. Noteworthy among these findings is the work by Cai el al. exploiting surface charge transfer doping (SCTD) technique based on an ultrathin MOOI layer synthesized through flame-based methods serving as a hole doping layer for FETs. An I_0N of 100 pA/pm was achieved owing to relatively low-/?_c of 0.8 kQ-pm. However, the degenerate p-type doping significantly reduced the on/off current ratio (~10). In comparison, our results on Ta doped MoSe? FET have achieved a record high 1_ON of 527 pA/pm owing to a record-low R_c of 0.4 with a similar current ratio of ~15. In a more recent work, Chiang el al. [29] utilized NO_X treatment to dope the complete channel region of a monolayer WSe? FET, achieving a remarkable I_0N of 300 pA/pm, a high on/off current ratio of 2x 10⁶ and a low-/?_c of 0.95 kQ-pm. While this method holds significance, its applicability is limited to WSe?, and its feasibility for other 2D materials remains to be tested. Chou el al. reported CVD-grown monolayer WSez with Sb/Pt contact and combined it with oxide-based encapsulation/doping technology to reach l_0N 150 pA/pm and an R_c of 0.75 k£l-pm. Without the encapsulation layer, the 1_ON value decreased to around 25 pA/pm. In comparison, our work achieved an I_0N - 212 pA/pm, without the use of an encapsulation layer. This distinction is significant because the presence of encapsulation layers can hinder the fabrication of top gates, which is ultimately needed for circuit design. Besides the SCTD approaches, successful demonstrations of substitutional p-type doping in 2D TMDs have been achieved using transition metals like Nb, Ta, V, and other. However, none of the previous studies were able to achieve as high I_ON as reported for our Nb— doped dual -gated MoSe2 FETs, featuring thin channels between the contacts and thicker channels underneath the contacts.

[00117] FIG. 28 shows an exemplary FET having a thick channel (panel a) and a thin channel (panel b). FIG. 29 shows a schematic depicting the TLM structure of a representative Nb-doped MoSe2 field-effect transistor (FET) with LCH values 500 nm, 200 nm, 100 nm, 50 nm, and 40 nm.

[00118] Methods

[00119] DFT calculations

[00120] To model the investigation of substitutional doping by group VB elements in the 2H phase of MoSe2, all DFT computations were executed using the Kohn Sham Hamiltonian. The utilized exchange-correlation functionals were outlined under the generalized gradient approximation (GGA), following the Perdew-Burke-Ernzerhof (PBE) description, which implemented in Virtual Nano lab Quantum ATK (2022.12-SP1). To optimize the lattice structure, we employed an energy cut-off of 125 Hartree, alongside a k-grid sampling of 5 x 5 x 1. This approach considers electrons residing in Mo (5s¹, 4d⁵) orbitals, Se (4s²4p⁴) orbitals, Nb (4d⁵, 5s¹), V (3d³4s²) and Ta (5d³6s²) orbitals as valence electrons. To simulate doping by group VB elements in MoSe?, we constructed hexagonal supercells of (5 x 5 x 1), (4 x 4 x 2), and (2 x 2 x 8) for IL, 2L, and 8L-MoSe2 respectively. Within these structures, we selectively replaced one Mo atom with a VB atom, resulting in the creation of M024 (D)Seso, Mo3i(D)Se64, and Mo3i(D)Se64 arrangements, where "D" signifies the dopant atom. This VB atom substitution corresponds to a doping percentage of 4.12% in lL-MoSe2, and 3.12% in both 2L and 8L- MoSe2. Furthermore, the influence of van der Waals forces in 2L and 8L-MoSe2 was considered by including the Grimme DFT-D2 dispersion-correction method. Structures were optimized to minimize total energy until atom forces were below 0.01 eV/A, with a tolerance limit of 10 ⁵ using a limited memory Broyden-Fletcher-Goldfarb-Shannon (LBFGS) method. High- symmetry k-points (T-M-K-F) were employed for the band structure calculation. Here our objective is to find appropriate VB group element dopants capable of creating p-type doping in MoSe? for FET applications. The effect of spin-orbit coupling (SOC) was not considered in the band structure calculation. It is noted that spin polarization is necessary to understand the magnetic properties of transition metal doped MoSe?.

[00121] 2D Material growth by Chemical Vapor Transport (CVT)

[00122] Crystals of MoSe2, WSe2 and doped counterparts were prepared by chemical vapor transport method in quartz glass ampoule using SeCU as a transport agent. For the synthesis, 3 at% of dopant (W(Mo)o.97DOPoo3Se2o2) (DOP denotes the different dopants used) was used and excess of selenium to reduce the vacancy density in the growth crystals. For the undoped crystal growth was done using composition W(Mo)Se2o2. The mixture of elements (W, +99.999%, -100 mesh, Mo +99.999%, -100 mesh, Se 99.9999%, 2-4 mm granules, Ta 99.9%, - 100 mesh, Nb, +99.9%, V, +99.9%, -100 mesh) corresponding to 50 g were placed in ampoule (50x250 mm) together with 0.5 g of SeCU (99.9%) inside glovebox and melt sealed under high vacuum (diffusion oil pumping with LN2 trap, under 1x10-3 Pa) using oxygen-hydrogen welding torch. The ampoule was placed in muffle furnace and heated on 500 °C for 25 hours, on 600 °C for 50 hours and on 800 °C for 50 hours. The heating and cooling rate was l°C/min and between each temperature step the reaction mixture was homogenized by shaking for 5 minutes. The formed polycrystalline diselenide was placed in two zone horizontal crystal growth furnace for CVT crystal growth. First the growth zone was heated on 1000 °C while source zone was kept on 700°C. After 50 hours the thermal gradient was reversed, and the source zone was kept at 1000°C while the temperature of growth zone was reduced from 950 °C to 900 °C over a period of ten days. Finally, the growth zone was heated to 500°C for two hours to remove transport medium and excess of selenium from the growth crystals. Over a 10 days period over 40 g of crystals was obtained. The ampoules were open in an argon filled glovebox and crystal were stored under inert atmosphere.

[00123] 2D Material growth by Chemical Vapor Deposition (CVD) [00124] Nb doped MoSe2 film was synthesized using liquid-phase precursor-assisted chemical vapor deposition, as detailed in references. The fdm was grown in a two-zone furnace on Si/SiOs substrates with a 300 nm oxide layer. Metal precursors consisted of a combination of Mo-based solution and a Nb-based solution. The Mo-based solution consists of 1 :4 volume ratio of ammonium molybdate tetrahydrate ((NTU^MoCh • 4H2O) and sodium cholate hydrate (C24H39NaOs • XH2O) in deionized water. The Nb-doping solution is a mixture of ammonium niobate oxalate hydrate (C4H4NNbC>9 • XH2O) and deionized water. After spin-coating the metal precursor onto Si/SiC>2 substrate, it was placed within a quartz tube at the center of the furnace. Simultaneously, 300 mg of selenium powder was introduced in an alumina boat at a second heating zone in the upstream region. The growth reaction occurred when the substrate temperature maintained at 800-825 °C for a 15-minute period, while the selenium heating zone was maintained at 375 °C. 100 seem Ar gas was used for ramping up the furnace and 200 seem Ar/H2 (9: 1) was used as the carrier gas during the growth period. After synthesis, the furnace naturally cooled down. The presence of MoSe2 was confirmed with Raman and photoluminescence spectroscopy using a 532 nm laser in a Horiba LabRAM.

[00125] Raman and photoluminescence (PL) spectroscopy

[00126] Raman and PL spectroscopy of the as-grown Nb-doped MoSe2 film were performed on a Horiba LabRAM HR Evolution confocal Raman microscope with a 532 nm laser. The objective magnification was 100x with a numerical aperture of 0.9, and the grating had a spacing of 1800 gr/mm for Raman and 300 gr/mm for PL.

[00127] Hall-Bar Measurements

[00128] Hall bar measurements were performed in room temperature using a DX-100 Hall effect system on bulk samples by making 4-point probe contacts with Cr/Au (van der Pauw geometry), while the magnetic field was swept ±500 mT.

[00129] Inductively Coupled Plasma Emission Spectroscopy (ICP-AES)

[00130] The bulk as-grown 2D material crystals were digested in acid. The acid solution was consequently nebulized into a fine aerosol which was then introduced into a high energy plasma (Temperature between 7,000 to 10,000 K). The plasma excites the atoms and ions to higher energy levels. As they drop back down to their normal levels, they do so by emitting energy wavelengths that are specific to the particular element. The wavelengths of emitted energy are separated in an optical chamber. By monitoring what wavelengths are emitted, we can determine how much of each element is present (quantitative determination).

[00131] Energy Dispersive Spectroscopy (EDS)

[00132] Energy dispersive X-ray spectroscopic analysis was carried on micrometer sized bulk flakes of the crystals using ESEM Q250 scanning electron microscope (SEM). An accelerating voltage of 30kV with a tungsten (W) source was used to detect the concentration of dopants in the crystals.

[00133] 2D Film Transfer to Target Substrates

[00134] To fabricate the FETs, 2D TMD flakes were exfoliated on a 30 nm gold coated silicon wafer. The flakes were then transferred from the gold substrate to the global back-gated AhCh/Pt/Ti/p -Si substrate using a polymethyl -methacryl ate (PMMA)-assisted wet transfer process. First, the exfoliated TMD flakes on the gold substrate were spin-coated with PMMA and baked at 150 °C for 2 min to ensure good PMMA/2D film adhesion. The comers of the spin-coated film were scratched using a razor blade and immersed inside a 1 M NaOH solution kept at 90 °C. Capillary action caused the NaOH to be preferentially drawn into the substrate/film interface due to the hydrophilic nature of gold and the hydrophobic nature of 2D and PMMA, separating the PMMA/2D film from the gold substrate. The separated film was then fished from the NaOH solution using a clean glass slide and rinsed in three separate water baths for 15 min each before finally being transferred onto the target substrate. Subsequently, the substrate was baked at 50 °C and 70 °C for 10 min each to remove moisture and promote film adhesion, thus ensuring a pristine interface, before the PMMA was removed using acetone immersion overnight and the film was cleaned with IPA.

[00135] 2D FET Fabrication

[00136] 2D FETs were fabricated using ZEP 520A 1 : 1 as the e-beam resist. The sample is initially dipped in Surpass 4K for 60 s, rinsed in DI water, and then baked at 100 °C for 1 min. This is done to improve the adhesion of the resist to the substrate that contains exposed metal alignment markers. ZEP 1 : 1 was spun at 5000 RPM for 45 s and baked at 180 °C for 3 min. E- beam lithography is carried out at a beam energy of 100 keV and is developed in n-amyl acetate chilled at -10 °C for 3 min and IPA at room -temperature for 60 s. Post-develop, 15 nm of palladium (Pd) is evaporated using e-beam evaporation, which now serves as contacts to the 2D FETs.

[00137] Oxygen Plasma Layer Thinning Treatment

[00138] The substrate containing the flakes were exposed to radio frequency (RF) generated Oxygen (O2) plasma in Tepla M4L dry etch system. O2 flow was set at 150 seem and Helium (He) at 50 seem, which acts as the carrier gas for O2 in the process. The chamber pressure was maintained at 550 mTorr and the sample was exposed to plasma at an RF power of 50 W for 15 seconds. Then the sample was subsequently dipped in DI water in a beaker for 2 minutes before drying with nitrogen.

[00139] Top-gated Fabrication for 2D FETs

[00140] A 2 nm thick layer of Aluminium was deposited on the 2D FET by electron beam evaporation which serves as the seed layer for atomic layer deposition (ALD) of the top-gate dielectric. Subsequently a 20 nm thick alumina (AI2O3) layer was grown with the seed layer by ALD. Next the substrate was lithographically patterned using E-beam followed by the deposition of the top gate electrode consisting of 20nm nickel (Ni) and lOnm gold (Au) by electron beam evaporation. Finally, the regions above the source and drain contacts were lithographically patterned and exposed to reactive ion etching (RIE) with BCEto access the source drain contact pads.

[00141] Scanning Electron Microscope (SEM)

[00142] SEM images of 2D FETs were obtained using a Ziess Gemini 500 field emission scanning electron microscope (FESEM) with an accelerating voltage of 5kV.

[00143] TEM Sample Preparation

[00144] A thin TEM sample was prepared using the Thermo Fisher Scientific Helios and Sciocs 2 DualBeam Focused Ion Beam Scanning Electron Microscope. The sample was first coated with a carbon layer, 0.5 pm thick, using a 1.6nA electron beam to protect the surface MoSe2 layer from Ga ion beam damage. Subsequently, another carbon layer, approximately 4pm thick, was deposited on top of the electron beam carbon layer using a 0.12 nA Ga ion beam. This layer served to protect the sample surface during ion beam milling and sample thinning. Following this, a 2 pm thick lamella of the sample cross-section around the electrode region was lifted out and in-situ transferred to a copper half-grid. The lamella was then thinned using a Ga ion beam at five decreasing voltage levels: 30 kV, 16 kV, 8 kV, 5 kV, and 2 kV. As the lamella became progressively thinner, the ion beam voltage was gradually reduced to minimize damage. [00145] STEM Characterization of the Cross-section

[00146] STEM and EDS characterizations were conducted on Titan FEI Titan3 G2 60-300 S/TEM, operating at an accelerating voltage of 300 kV, with spot size of 6, C2 aperture of 70 pm, and convergent angle of 25.2 mrad. The elemental maps from the Energy-dispersive X-ray spectroscopy (EDS) were acquired using the SuperX EDS system (Bruker) under STEM mode and are intensity plot images. The comprehensive double electrode STEM image and the corresponding EDS image in FIG. 12 (panel b) was taken under beam current of 0.6 nA. Meanwhile, the enlarged single electrode STEM image and its associated EDS image in FIG. 12 (panel b) utilized a beam current of 0.07 nA.

[00147] Atomic Force Microscopy

[00148] Atomic force microscopy was utilized to investigate the thickness profile of exfoliated multilayer flakes before and after plasma treatments. RTESPA-150 probe tips were used with a Bruker dimension icon AFM. All images were collected in peak force tapping mode with a peak force of 12 nN and a scan rate of .5 Hz. Images were processed and exported using gwyddion.

[00149] Electrical Characterization

[00150] Electrical characterization of the fabricated devices was performed using a Lake Shore CRX-VF probe station in atmospheric conditions with a Key sight Bl 500A parameter analyzer. Statistical measurements were performed using a semi-automated Formfactor 12000 probe station in atmospheric conditions also with a Keysight B1500A parameter analyzer.

[00151] Conclusion

[00152] In summary, we examined 2D FETs based on pristine and doped MoSe? and WSe2 crystals. Pristine flakes showed n-type transport, while thick doped flakes (4-6 monolayers) exhibited degenerate p-type doping with enhanced I_0N (as high as 1.8 mA/pm) and reduced R_c (as low as 95 Q-pm), but poor I_0N /I_OPP (< 20). In contrast, thinner flakes (1-3 monolayers) displayed high I_0N /l_OPF (> IO³) but low I_ON due to high R_c. By ingeniously devising FETs featuring monolayer channels and doped multilayer contacts, we harmonized these traits, achieving high /_ow, low R_c, and large I_ON /I_0PF. Furthermore, we combine this strategy with channel length scaling, and dual-gated architecture to achieve I_0N as high as 212 gA/pm for p-type Nb-doped MoSe2 FETs. Our approach can be extended to diverse 2D materials, accommodating n- and p-type doping, as well as large-scale synthesis. In fact, we were also able to demonstrate layer-thickness dependent doping efficacy in large-area Nb-doped MoSe2 grown via CVD technique. Our study underscores the significance of doped multilayer materials, steering 2D FET advancement beyond the confines of monolayer-centric approaches. [00153] References

[00154] The references listed below are incorporated herein by reference in their entireties.

S. Manzeli, D. Ovchinnikov, D. Pasquier, O. V. Yazyev, and A. Kis, "2D transition metal dichalcogenides," Nature Reviews Materials, vol. 2, p. 17033, 2017.

G. R. Bhimanapati, Z. Lin, V. Meunier, Y. Jung, J. Cha, S. Das, et al., "Recent Advances in Two-Dimensional Materials beyond Graphene," ACS Nano, vol. 9, pp. 11509-11539, 2015/12/22 2015.

W. Choi, N. Choudhary, G. H. Han, J. Park, D. Akinwande, and Y. H. Lee, "Recent development of two-dimensional transition metal dichalcogenides and their applications," Materials Today, vol. 20, pp. 116-130, 2017.

D. Geng and H. Y. Yang, "Recent advances in growth of novel 2D materials: beyond graphene and transition

A. Sebastian, R. Pendurthi, T. H. Choudhury, J. M. Redwing, and S. Das, "Benchmarking monolayer MoS2 and WS2 field-effect transistors," Nature Communications, vol. 12, p. 693, 2021/01/29 2021.

P.-C. Shen, C. Su, Y. Lin, A.-S. Chou, C.-C. Cheng, J.-H. Park, et al., "Ultralow contact resistance between semimetal and monolayer semiconductors," Nature, vol. 593, pp. 211- 217, 2021/05/01 2021.

W. Li, X. Gong, Z. Yu, L. Ma, W. Sun, S. Gao, et al., "Approaching the quantum limit in two-dimensional semiconductor contacts," Nature, vol. 613, pp. 274-279, 2023.

C. D. English, K. K. H. Smithe, R. L. Xu, and E. Pop, "Approaching ballistic transport in monolayer MoS<inf>2</inf> transistors with self-aligned 10 nm top gates," in 2016 IEEE International Electron Devices Meeting (IEDM), 2016, pp. 5.6.1-5.6.4. Y. Zhang, J. Yu, R. Zhu, M. Wang, C. Tan, T. Tu, et al., "A single-crystalline native dielectric for two-dimensional semiconductors with an equivalent oxide thickness below 0.5 nm," Nature Electronics, vol. 5, pp. 643-649, 2022/10/01 2022.

T. Li, T. Tu, Y. Sun, H. Fu, J. Yu, L. Xing, et al., "A native oxide high-K gate dielectric for two-dimensional electronics," Nature Electronics, vol. 3, pp. 473-478, 2020.

D. E. Nikonov and I. A. Young, "Benchmarking of beyond-CMOS exploratory devices for logic integrated circuits," IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 1, pp. 3-11, 2015.

S. S. Sylvia, K. Alam, and R. K. Lake, "Uniform benchmarking of low-voltage van der Waals FETs," IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 2, pp. 28-35, 2016.

C.-S. Lee, B. Cline, S. Sinha, G. Yeric, and H. S. P. Wong, "32-bit Processor core at 5- nm technology: Analysis of transistor and interconnect impact on VLSI system performance," pp. 28.3.1-28.3.4, 2016.

T. Agarwal, A. Szabo, M. G. Bardon, B. Soree, I. Radu, P. Raghavan, et al., "Benchmarking of monolithic 3D integrated MX2 FETs with Si FinFETs," pp. 5.7.1- 5.7.4, 2017.

D. S. Schulman, A. J. Arnold, and S. Das, "Contact engineering for 2D materials and devices," Chem Soc Rev, Mar 2 2018.

S. Das, H. Y. Chen, A. V. Penumatcha, and J. Appenzeller, "High performance multilayer MoS2 transistors with scandium contacts," Nano Lett, vol. 13, pp. 100-5, Jan 09 2013.

S. Das and J. Appenzeller, "WSe2 field effect transistors with enhanced ambipolar characteristics," Applied Physics Letters, vol. 103, Sep 22013.

X. Zhang, F. Zhang, Y. Wang, D. S. Schulman, T. Zhang, A. Bansal, et al., "Defect- Controlled Nucleation and Orientation of WSe2 on hBN: A Route to Single-Crystal Epitaxial Monolayers," ACS Nano, 2019/02/13 2019.

Z. Zhang, Y. Guo, and J. Robertson, "Origin of Weaker Fermi Level Pinning and Localized Interface States at Metal Silicide Schottky Barriers," The Journal of Physical Chemistry C, vol. 124, pp. 19698-19703, 2020. metal di chalcogenides," Advanced Materials, vol. 30, p. 1800865, 2018.

S. Manzeli, D. Ovchinnikov, D. Pasquier, O. V. Yazyev, and A. Kis, "2D transition metal di chalcogenides," Nature Reviews Materials, vol. 2, p. 17033, 2017.

G. R. Bhimanapati, Z. Lin, V. Meunier, Y. Jung, J. Cha, S. Das, et al., "Recent Advances in Two-Dimensional Materials beyond Graphene," ACS Nano, vol. 9, pp. 11509-11539, 2015/12/22 2015.

W. Choi, N. Choudhary, G. H. Han, J. Park, D. Akinwande, and Y. H. Lee, "Recent development of two-dimensional transition metal dichalcogenides and their applications," Materials Today, vol. 20, pp. 116-130, 2017.

D. E. Nikonov and 1. A. Young, "Benchmarking of beyond-CMOS exploratory devices for logic integrated circuits," IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 1, pp. 3-11, 2015.

S. S. Sylvia, K. Alam, and R. K. Lake, "Uniform benchmarking of low-voltage van der Waals FETs," IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 2, pp. 28-35, 2016.

C.-S. Lee, B. Cline, S. Sinha, G. Yeric, and H. S. P. Wong, "32-bit Processor core at 5- nm technology: Analysis of transistor and interconnect impact on VLSI system performance," pp. 28.3.1-28.3.4, 2016.

T. Agarwal, A. Szabo, M. G. Bardon, B. Soree, I. Radu, P. Raghavan, et al., "Benchmarking of monolithic 3D integrated MX2 FETs with Si FinFETs," pp. 5.7.1- 5.7.4, 2017.

D. Geng and H. Y. Yang, "Recent advances in growth of novel 2D materials: beyond graphene and transition metal dichalcogenides," Advanced Materials, vol. 30, p. 1800865, 2018.

A. Sebastian, R. Pendurthi, T. H. Choudhury, J. M. Redwing, and S. Das, "Benchmarking monolayer MoS2 and WS2 field-effect transistors," Nature Communications, vol. 12, p. 693, 2021/01/29 2021. P.-C. Shen, C. Su, Y. Lin, A.-S. Chou, C.-C. Cheng, J.-H. Park, et al., "Ultralow contact resistance between semimetal and monolayer semiconductors," Nature, vol. 593, pp. 211- 217, 2021/05/01 2021.

W. Li, X. Gong, Z. Yu, L. Ma, W. Sun, S. Gao, et al., "Approaching the quantum limit in two-dimensional semiconductor contacts," Nature, vol. 613, pp. 274-279, 2023.

C. D. English, K. K. H. Smithe, R. L. Xu, and E. Pop, "Approaching ballistic transport in monolayer MoS<inf>2</inf> transistors with self-aligned 10 nm top gates," in 2016 IEEE International Electron Devices Meeting (IEDM), 2016, pp. 5.6.1-5.6.4.

Y. Zhang, J. Yu, R. Zhu, M. Wang, C. Tan, T. Tu, et al., "A single-crystalline native dielectric for two-dimensional semiconductors with an equivalent oxide thickness below 0.5 nm," Nature Electronics, vol. 5, pp. 643-649, 2022/10/01 2022.

T. Li, T. Tu, Y. Sun, H. Fu, J. Yu, L. Xing, et al., "A native oxide high-K gate dielectric for two-dimensional electronics," Nature Electronics, vol. 3, pp. 473-478, 2020.

D. S. Schulman, A. J. Arnold, and S. Das, "Contact engineering for 2D materials and devices," Chem Soc Rev, Mar 2 2018.

S. Das, H. Y. Chen, A. V. Penumatcha, and J. Appenzeller, "High performance multilayer MoS2 transistors with scandium contacts," Nano Lett, vol. 13, pp. 100-5, Jan 09 2013.

S. Das and J. Appenzeller, "WSe2 field effect transistors with enhanced ambipolar characteristics," Applied Physics Letters, vol. 103, Sep 2 2013.

X. Zhang, F. Zhang, Y. Wang, D. S. Schulman, T. Zhang, A. Bansal, et al., "Defect- Controlled Nucleation and Orientation of WSe2 on hBN: A Route to Single-Crystal Epitaxial Monolayers," ACS Nano, 2019/02/13 2019.

Z. Zhang, Y. Guo, and J. Robertson, "Origin of Weaker Fermi Level Pinning and Localized Interface States at Metal Silicide Schottky Barriers," The Journal of Physical Chemistry C, vol. 124, pp. 19698-19703, 2020.

S. Chowdhury, P. Venkateswaran, and D. Somvanshi, "A systematic study on the electronic structure of 3d, 4d, and 5d transition metal-doped WSe2 monolayer," Superlattices and Microstructures, vol. 148, p. 106746, 2020. S. Tongay, J. Zhou, C. Ataca, K. Lo, T. S. Matthews, J. Li, et al., "Thermally Driven Crossover from Indirect toward Direct Bandgap in 2D Semiconductors: MoSe2 versus MoS2," Nano Letters, vol. 12, pp. 5576-5580, 2012/11/14 2012.

S. K. Ghosh and D. Somvanshi, "First-principal insight of the gold-metal interaction to bilayer MoSe2 of AB and AA stacking order," Solid State Communications, vol. 342, p. 114613, 2022/02/01/ 2022.

S. Bhattacharyya and A. K. Singh, "Semiconductor-metal transition in semiconducting bilayer sheets of transition-metal di chalcogenides," Physical Review B, vol. 86, p. 075454, 08/24/ 2012.

J. Gusakova, X. Wang, L. L. Shiau, A. Krivosheeva, V. Shaposhnikov, V. Borisenko, et al., "Electronic Properties of Bulk and Monolayer TMDs: Theoretical Study Within DFT Framework (GVJ-2e Method)," physica status solidi (a), vol. 214, p. 1700218, 2017.

A. Kuc, N. Zibouche, and T. Heine, "Influence of quantum confinement on the electronic structure of the transition metal sulfide $T$S${}_{2}$," Physical Review B, vol. 83, p. 245213, 06/30/ 2011.

- J. R. Nasr, D. S. Schulman, A. Sebastian, M. W. Horn, and S. Das, "Mobility Deception in Nanoscale Transistors: An Untold Contact Story," Advanced Materials, vol. 31, p. 1806020, 2019.

A.-S. Chou, Y.-T. Lin, Y. C. Lin, C.-H. Hsu, M.-Y. Li, S.-L. Liew, et al., "High- performance monolayer WSe2 p/n FETs via antimony-platinum modulated contact technology towards 2D CMOS electronics," in 2022 International Electron Devices Meeting (IEDM), 2022, pp. 7.2. 1-7.2. 4.

L. Cai, C. J. McClellan, A. L. Koh, H. Li, E. Yalon, E. Pop, et al., "Rapid flame synthesis of atomically thin MoO3 down to monolayer thickness for effective hole doping of WSe2," Nano letters, vol. 17, pp. 3854-3861, 2017.

C.-C. Chiang, H.-Y. Lan, C.-S. Pang, J. Appenzeller, and Z. Chen, "Air-stable P-doping in record high-performance monolayer WSe 2 devices," IEEE Electron Device Letters, vol. 43, pp. 319-322, 2021. S. K. Pandey, H. Alsalman, J. G. Azadani, N. Izquierdo, T. Low, and S. A. Campbell, "Controlled p-type substitutional doping in large-area monolayer WSe 2 crystals grown by chemical vapor deposition," Nanoscale, vol. 10, pp. 21374-21385, 2018.

A. Kozhakhmetov, S. Stolz, A. M. Z. Tan, R. Pendurthi, S. Bachu, F. Turker, et al., "Controllable p-type doping of 2D WSe2 via vanadium substitution," Advanced Functional Materials, vol. 31, p. 2105252, 2021.

- V. T. Vu, T. T. H. Vu, T. L. Phan, W. T. Kang, Y. R. Kim, M. D. Tran, et al., "One-step synthesis of NbSe2/Nb-doped-WSe2 metal/doped-semiconductor van der Waals heterostructures for doping controlled ohmic contact," ACS nano, vol. 15, pp. 13031- 13040, 2021.

X. Li, M. W. Lin, L. Basile, S. M. Hus, A. A. Puretzky, J. Lee, et al., "Isoelectronic tungsten doping in monolayer MoSe2 for carrier type modulation," Advanced Materials, vol. 28, pp. 8240-8247, 2016.

F. Zhong, J. Ye, T. He, L. Zhang, Z. Wang, Q. Li, et al., "Substitutionally Doped MoSe2 for High-Performance Electronics and Optoelectronics," Small, vol. 17, p. 2102855, 2021.

H. Fang, S. Chuang, T. C. Chang, K. Takei, T. Takahashi, and A. Javey, "High- performance single layered WSe2 p-FETs with chemically doped contacts," Nano letters, vol. 12, pp. 3788-3792, 2012.

C. S. Pang, T. Y. Hung, A. Khosravi, R. Addou, Q. Wang, M. J. Kim, et al., "Atomically Controlled Tunable Doping in High-Performance WSe2 Devices," Advanced Electronic Materials, vol. 6, p. 1901304, 2020.

M. Yamamoto, S. Nakaharai, K. Ueno, and K. Tsukagoshi, "Self-limiting oxides on WSe2 as controlled surface acceptors and low-resistance hole contacts," Nano letters, vol. 16, pp. 2720-2727, 2016.

S. Yang, G. Lee, and J. Kim, "Selective p-doping of 2D WSe2 via UV/ozone treatments and its application in field-effect transistors," ACS Applied Materials & Interfaces, vol. 13, pp. 955-961, 2020.

A. S. Chou, Y. T. Lin, Y. C. Lin, C. H. Hsu, M. Y. Li, S. L. Liew, et al., "High- Performance Monolayer WSe2 p/n FETs via Antimony -Platinum Modulated Contact Technology towards 2D CMOS Electronics," in 2022 International Electron Devices Meeting (IEDM), 2022, pp. 7.2.1-7.2.4.

T. Zhang, K. Fujisawa, F. Zhang, M. Liu, M. C. Lucking, R. N. Gontijo, et al., "Universal in situ substitutional doping of transition metal dichalcogenides by liquid-phase precursor-assisted synthesis," ACS nano, vol. 14, pp. 4326-4335, 2020.

Y. T. H. Pham, M. Liu, V. O. Jimenez, Z. Yu, V. Kalappattil, F. Zhang, et al., "Tunable ferromagnetism and thermally induced spin flip in Vanadium-doped tungsten diselenide monolayers at room temperature," Advanced Materials, vol. 32, p. 2003607, 2020.

[00155] It should be understood that the disclosure of a range of values is a disclosure of every numerical value within that range, including the end points. It should also be appreciated that some components, features, and/or configurations may be described in connection with only one particular embodiment, but these same components, features, and/or configurations can be applied or used with many other embodiments and should be considered applicable to the other embodiments, unless stated otherwise or unless such a component, feature, and/or configuration is technically impossible to use with the other embodiment. Thus, the components, features, and/or configurations of the various embodiments can be combined together in any manner and such combinations are expressly contemplated and disclosed by this statement.

[00156] It will be apparent to those skilled in the art that numerous modifications and variations of the described examples and embodiments are possible considering the above teachings of the disclosure. The disclosed examples and embodiments are presented for purposes of illustration only. Other alternate embodiments may include some or all of the features disclosed herein. Therefore, it is the intent to cover all such modifications and alternate embodiments as may come within the true scope of this invention, which is to be given the full breadth thereof.

[00157] It should be understood that modifications to the embodiments disclosed herein can be made to meet a particular set of design criteria. Therefore, while certain exemplary embodiments of the systems, compositions, materials, apparatuses, and methods of using and making the same disclosed herein have been discussed and illustrated, it is to be distinctly understood that the invention is not limited thereto but may be otherwise variously embodied and practiced within the scope of the following claims.

Claims

WHAT IS CLAIMED IS:

1. A Field Effect Transistor (FET), comprising: a substrate having a 2D material formed on a surface thereof, the 2D material having a source contact region, a drain contact region, and a channel region; wherein: the channel region comprises less than four monolayers of the 2D material; the source contact region comprises more than four monolayers of the 2D material; and the drain contact region comprises more than four monolayers of the 2D material.

2. The FET of claim 1, wherein: the source contact region includes heavily/degenerately doped 2D material; and the drain contact region includes heavily/degenerately doped 2D material; and the channel region includes pristine/lightly/moderately doped 2D material.

3. The FET of claim 1, wherein: the 2D material includes one or more types of 2D material; the 2D material of the channel region is the same as or different from the 2D material of the source contact region; and the 2D material of the channel region is the same as or different from the 2D material of the drain contact region; and the 2D material of the source contact region is the same as or different from the 2D material of the drain contact region.

4. The FET of claim 1, wherein: the 2D material of one monolayer of the channel region is the same as or different from the 2D material of another monolayer of the channel region; the 2D material of one monolayer of the source contact region is the same as or different from the 2D material of another monolayer of the source contact region; and the 2D material of one monolayer of the drain contact region is the same as or different from the 2D material of another monolayer of the drain contact region.