WO2025243156A1 - Semiconductor device - Google Patents

Abstract

The present invention provides a semiconductor device that has a novel configuration. A p-channel transistor and one n-channel transistor have a first semiconductor layer that contains silicon. A second n-channel transistor has a second semiconductor layer that contains indium oxide. One of either the source or the drain of the second n-channel transistor is electrically connected to one of either the source or the drain of the first n-channel transistor. The other of either the source or the drain of the second n-channel transistor is electrically connected to a second power line. A signal line electrically connected to the gate of the second n-channel transistor has a function of conveying a signal for turning off the second n-channel transistor during a period in which a logic circuit is inactive. A first power line is provided in a layer below the layer in which the logic circuit is provided. The second power line is provided in a layer above the layer in which the logic circuit is provided.

Description

Semiconductor Devices

This specification describes semiconductor devices, etc.

Note that one embodiment of the present invention is not limited to the above technical field. Examples of technical fields of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, imaging devices, display devices, light-emitting devices, power storage devices, memory devices, display systems, electronic devices, lighting devices, input devices, input/output devices, and driving methods thereof or manufacturing methods thereof.

In recent years, efforts to combat global warming have become increasingly important. Energy consumption continues to increase, and carbon dioxide emissions, one of the causes of global warming, have yet to be reduced. Simply reducing energy consumption may actually result in a loss of convenience. In order to reduce energy consumption without sacrificing convenience, low-power consumption technologies are becoming extremely important.

In logic circuits that perform arithmetic processing, such as CPUs (Central Processing Units) and GPUs (Graphics Processing Units), transistors are becoming increasingly miniaturized and integrated to improve performance. Logic circuits have a circuit structure (also known as CMOS (Complementary Metal-Oxide-Semiconductor)) that combines n-channel transistors (also known as nMOS) and p-channel transistors (also known as pMOS). In CMOS, power consumption increases due to factors such as leakage currents that accompany transistor miniaturization and through currents that occur when transistors switch between on and off states.

Transistors with FinFET and Gate All Around (GAA) structures are being put into practical use as a countermeasure to the leakage current that accompanies miniaturization. Furthermore, three-dimensional packaging technology for stacking transistors is being considered as an integration technique to further improve performance. For example, a complementary field-effect transistor (CFET) has been proposed, in which transistors with a GAA nanosheet structure are stacked vertically on a silicon substrate (see, for example, Patent Document 1 and Non-Patent Document 1).

International Publication No. 2019/112952

J. Park et al. , “First demonstration of 3-dimensional stacked FET with top/bo ttom source-drain isolation and stacked n/p metal gate"IEDM2023 Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https://unit.aist.go.jp/rpd-envene/PV/ja/results/2019/oral/T13.pdf>

Technologies such as the FinFET structure, GAA nanosheet structure, and CFET are important for miniaturizing transistors and increasing their integration density. However, in the case of CMOS, a circuit structure that combines nMOS and pMOS, leakage current increases as the number of transistors increases. To prevent this, power gating, which cuts off leakage current when the logic circuit is inactive, is effective.

However, when power gating transistors are arranged on a logic circuit basis, there is a risk that the level of integration will decrease as the number of transistors increases. Alternatively, there is a risk that power consumption will increase due to leakage current from the power gating transistors themselves. Alternatively, there is a risk that the operating speed will decrease if the current supply capacity of the power gating switches is low. Alternatively, there is a risk that the wiring between the signal lines and transistors will become more complex if there are additional signal lines that transmit signals to control the power gating transistors, in addition to the signal lines that transmit input and output signals to control the logic circuit and the signal lines that transmit the power supply potential to operate the logic circuit.

An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure. Another object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which transistors for power gating can be arranged in units of logic circuits without reducing the degree of integration of the transistors. Another object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which power gating transistors themselves can consume less power due to leakage current. Another object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which a decrease in operating speed is suppressed by increasing the current supply capability of the transistors for power gating. Another object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which connections between signal lines and transistors can be efficiently arranged.

Note that one embodiment of the present invention does not necessarily have to solve all of the above problems, but it is sufficient if it can solve at least one of the problems. Furthermore, the description of the above problems does not preclude the existence of other problems. Problems other than these will become apparent from the description in the specification, claims, drawings, etc., and it is possible to extract other problems from the description in the specification, claims, drawings, etc.

One aspect of the present invention includes a logic circuit having a p-channel transistor, a first n-channel transistor, and a second n-channel transistor; a first signal line that supplies a control signal to the logic circuit; a first power supply line that supplies a high power supply potential; and a second power supply line that supplies a low power supply potential. The p-channel transistor and the first n-channel transistor have a first semiconductor layer containing silicon, the second n-channel transistor has a second semiconductor layer containing indium oxide, and one of the source and drain of the second n-channel transistor is connected to the source of the first n-channel transistor. The semiconductor device has a first signal line electrically connected to the gate of the second n-channel transistor, a first source or drain of the p-channel transistor electrically connected to a first power supply line, and a second signal line electrically connected to the gate of the second n-channel transistor, which supplies a signal that turns off the second n-channel transistor during a period when the logic circuit is inactive. The first power supply line is provided below the layer in which the logic circuit is provided, and the second power supply line is provided above the layer in which the logic circuit is provided.

One aspect of the present invention includes a logic circuit having a p-channel transistor, a first n-channel transistor, and a second n-channel transistor; a first signal line that supplies a control signal to the logic circuit; a first power supply line that supplies a high power supply potential; and a second power supply line that supplies a low power supply potential, wherein the p-channel transistor and the first n-channel transistor have a first semiconductor layer having silicon, the second n-channel transistor has a second semiconductor layer having indium oxide, and one of the source and drain of the second n-channel transistor is connected to the source or drain of the first n-channel transistor. One of the source or drain of the p-channel transistor is electrically connected to a first power supply line, and the other of the source or drain of the second n-channel transistor is electrically connected to a second power supply line. A first signal line electrically connected to the gate of the second n-channel transistor has a function of supplying a signal that turns off the second n-channel transistor during a period when the logic circuit is inactive, and the first power supply line is provided below the layer in which the p-channel transistor is provided, and the second power supply line is provided above the layer in which the second n-channel transistor is provided.

One embodiment of the present invention includes a logic circuit having a p-channel transistor, a first n-channel transistor, and a second n-channel transistor; a first signal line that supplies a control signal to the logic circuit; a first power supply line that supplies a high power supply potential; and a second power supply line that supplies a low power supply potential. The p-channel transistor and the first n-channel transistor have a first semiconductor layer containing silicon, the second n-channel transistor has a second semiconductor layer containing indium oxide, and one of the source and drain of the second n-channel transistor is electrically connected to one of the source and drain of the first n-channel transistor. The semiconductor device is connected to a first power supply line, one of the source or drain of the p-channel transistor is electrically connected to a first power supply line, and the other of the source or drain of the second n-channel transistor is electrically connected to a second power supply line. A first signal line electrically connected to the gate of the second n-channel transistor has a function of supplying a signal that turns off the second n-channel transistor during a period when the logic circuit is inactive. The first power supply line and the second power supply line are each provided in a layer below the layer in which the p-channel transistor is provided, and the signal lines are each provided in a layer above the layer in which the second n-channel transistor is provided.

In one aspect of the present invention, the semiconductor device preferably has a structure in which the first semiconductor layer is surrounded by the gate of one p-channel transistor and the gate of one n-channel transistor.

In one aspect of the present invention, the semiconductor device preferably includes a first power supply line and a second power supply line, each of which includes a third power supply line that supplies a high power supply potential and a fourth power supply line that supplies a low power supply potential, the third power supply line being provided below the layer in which the p-channel transistor is provided, and the fourth power supply line being provided above the layer in which the second n-channel transistor is provided.

In one embodiment of the present invention, a semiconductor device preferably has a third n-channel transistor, and a second signal line electrically connected to the gate of the first n-channel transistor and the gate of the p-channel transistor is electrically connected to one of the source and drain of the third n-channel transistor, and has a function of maintaining the potential of the second signal line by turning off the third n-channel transistor.

Further aspects of the present invention are described in the following embodiments and drawings.

One embodiment of the present invention can provide a semiconductor device with a novel structure. Alternatively, one embodiment of the present invention can provide a semiconductor device with a novel structure in which a transistor for power gating is provided for each logic circuit without reducing the integration density of the transistors. Alternatively, one embodiment of the present invention can provide a semiconductor device with a novel structure in which power consumption due to leakage current of the transistor for power gating itself is reduced. Alternatively, one embodiment of the present invention can provide a semiconductor device with a novel structure in which a decrease in operating speed is suppressed by increasing the current supply capability of the transistor for power gating. Alternatively, one embodiment of the present invention can provide a semiconductor device with a novel structure in which wiring between signal lines and transistors can be efficiently arranged.

The description of multiple effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily have to have all of the effects exemplified. Furthermore, issues, effects, and novel features of one embodiment of the present invention other than those described above will become apparent from the description and drawings in this specification.

1A and 1B are circuit diagrams illustrating a semiconductor device according to one embodiment of the present invention, and timing charts illustrating a semiconductor device according to one embodiment of the present invention.
FIG. 2 is a schematic diagram illustrating a semiconductor device of one embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention.
FIG. 4 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention.
FIG. 5 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention.
FIG. 6 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention.
FIG. 7 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention.
8A and 8B are circuit diagrams illustrating a semiconductor device according to one embodiment of the present invention, and timing charts illustrating a semiconductor device according to one embodiment of the present invention.
9A and 9B are circuit diagrams illustrating a semiconductor device according to one embodiment of the present invention, and timing charts illustrating a semiconductor device according to one embodiment of the present invention.
FIG. 10 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention.
FIG. 11 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention.
12A to 12C are circuit diagrams illustrating a semiconductor device of one embodiment of the present invention.
FIG. 13 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention.
FIG. 14 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention.
15A is a plan view showing an example of a semiconductor device, and FIGS. 15B to 15D are cross-sectional views showing the example of the semiconductor device.
16A is a plan view showing an example of a semiconductor device, and FIGS. 16B to 16D are cross-sectional views showing an example of the semiconductor device.
17A is a plan view showing an example of a semiconductor device, and FIGS. 17B to 17D are cross-sectional views showing an example of the semiconductor device.
18A is a plan view showing an example of a semiconductor device, and FIGS. 18B and 18C are cross-sectional views showing the example of the semiconductor device.
19A and 19B are diagrams illustrating the carrier concentration dependence of Hall mobility, and Fig. 19C is a cross-sectional view illustrating an indium oxide film.
20A to 20D are cross-sectional views showing an example of a semiconductor device.
FIG. 21 is a cross-sectional view showing an example of a semiconductor device.
FIG. 22 is a cross-sectional view showing an example of a semiconductor device.
23A and 23B are diagrams illustrating an example of an electronic component.
24A to 24C are diagrams showing an example of a mainframe computer, Fig. 24D is a diagram showing an example of space equipment, and Fig. 24E is a diagram showing an example of a storage system applicable to a data center.

The following describes an embodiment of the present invention. However, one aspect of the present invention is not limited to the following description, and those skilled in the art will readily understand that various changes in form and details may be made without departing from the spirit and scope of the present invention. Therefore, one aspect of the present invention should not be interpreted as being limited to the description of the embodiment shown below.

In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Nor do they limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

In the drawings, identical elements, elements with similar functions, elements made of the same material, or elements formed at the same time may be given the same reference numerals, and repeated explanations may be omitted.

In this specification, for example, the power supply potential VDD may be abbreviated as potential VDD, VDD, etc. This also applies to other components (for example, signals, voltages, circuits, elements, electrodes, wiring, etc.).

Furthermore, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "_2", "[n]", or "[m, n]" may be added to the reference numeral. For example, the second wiring GL is written as wiring GL[2].

(Embodiment 1)
The structure, operation, and the like of a semiconductor device according to one embodiment of the present invention will be described.

In this specification, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as logic circuits that include such semiconductor elements, are examples of semiconductor devices.

One embodiment of the present invention can be applied to logic circuits having a CMOS circuit configuration, such as basic logic gates such as NOT (also referred to as an inverter or NOT circuit), NAND (also referred to as a NAND circuit), NOR (also referred to as a NOR circuit), AND (also referred to as an AND circuit), and OR (also referred to as a NAND circuit). It can also be applied to circuits such as flip-flops, registers, and shift registers, which are combinations of these logic gates. It can also be applied to large-scale arithmetic circuits, which are combinations of a plurality of these circuits.

<Configuration and Operation Examples of Semiconductor Device>
FIG. 1A shows an example of a semiconductor device that functions as a NOT circuit. The NOT circuit 100 shown in FIG. 1A includes transistors 101, 102, and 106. As shown in FIG. 1A, the transistor 101 is a p-channel transistor (pMOS), and the transistors 102 and 106 are n-channel transistors (nMOS). The transistor 102 is also referred to as a first n-channel transistor, and the transistor 106 is also referred to as a second n-channel transistor. FIG. 1A also shows power supply lines VHL and VLL, and signal lines INL1, INL2, and OUTL.

The transistors and power supply lines VHL and VLL of the NOT circuit 100, and the transistors and signal lines INL1, INL2, and OUTL of the NOT circuit 100 are connected as shown in FIG. 1A.

Specifically, the gate of transistor 101 and the gate of transistor 102 are connected to signal line INL2. The gate of transistor 106 is connected to signal line INL1. One of the source or drain of transistor 101 is connected to signal line OUTL. One of the source or drain of transistor 102 is connected to signal line OUTL. The other of the source or drain of transistor 101 is connected to power supply line VHL. The other of the source or drain of transistor 102 is connected to one of the source or drain of transistor 106. The other of the source or drain of transistor 106 is connected to power supply line VLL.

The power supply line VHL is a power supply line that transmits a high power supply potential. The power supply line VHL is also called the first power supply line. The power supply line VLL is a power supply line that transmits a low power supply potential. The power supply line VLL is also called the second power supply line.

Signal line INL1 is a wiring that transmits a signal that controls the on state (conducting state) or off state (non-conducting state) of transistor 106. Transistor 106 is a transistor that functions as a switch. Transistor 106 is in the on state when the potential of signal line INL1 is at H (High) level, and in the off state when it is at L (Low) level. One of the source or drain of transistor 106 is directly connected to the other of the source or drain of transistor 102.

By controlling signal line INL1, the current flowing between power supply line VHL and power supply line VLL is cut off, enabling power gating of each logic circuit such as NOT circuit 100. When the potential of signal line INL1 is at H level, NOT circuit 100 functions as a NOT circuit, and when the potential of signal line INL1 is at L level, NOT circuit 100 functions as a circuit that outputs the logic of the previous state. Note that power gating here refers to the operation of cutting off leakage current flowing from signal line OUTL, which transmits the output signal, to power supply line VLL.

Signal line INL2 is a wiring that transmits an input signal to the NOT circuit, which is a logic circuit. Signal line OUTL is a wiring that transmits an output signal from the NOT circuit, which is a logic circuit.

When the potential of the signal line INL1 is set to the L level, it is preferable to do so during a period when the input signal to the logic circuit is at the L level and the input signal is not being switched. During other periods, it is preferable to keep the potential of the signal line INL1 at the H level. This configuration can reduce the leakage current flowing through the transistor 102 when the input signal is at the L level and the output signal is continuously at the H level.

Depending on the type of logic circuit, there may be multiple transistors equivalent to transistor 102. In this case, multiple transistors 106 are provided to match the number of transistors 102. Signal line INL1 is connected to multiple transistors 106.

In the case of the NOT circuit 100 shown in FIG. 1A, when the potential of signal line INL1 is at H level and signal line INL2 is at H level, transistor 101 is in the OFF state and transistor 102 is in the ON state, and when signal line INL2 is at L level, transistor 102 is in the OFF state. As a result, when signal line INL2 is at H level, signal line OUTL is at L level, and when signal line INL2 is at L level, signal line OUTL is at H level.

As described above, when the NOT circuit 100 shown in FIG. 1A is power-gated, that is, when the potential of signal line INL2 is continuously at the L level, signal line INL1 is set to the L level. Transistor 101 is turned on, and transistors 102 and 106 are turned off. As a result, signal line INL2 is at the L level and signal line OUTL is at the H level. Since transistor 106 is also turned off in addition to transistor 102, the leakage current in transistor 102 can be reduced. As a result, fluctuations in the H-level potential of signal line OUTL can be reduced.

When the potential of signal line INL2 is at H level, the NOT circuit 100 shown in FIG. 1A does not perform power gating. Therefore, signal line INL1 remains at H level. Transistor 101 is in the OFF state, and transistors 102 and 106 are in the ON state. As a result, signal line INL2 is at H level and signal line OUTL is at L level.

A NOT circuit is a logic gate with one input and one output, but some logic gates may have multiple inputs and multiple outputs. In this case, the logic gate will have multiple transistors equivalent to transistors 101 and 102. There will be multiple signal lines INL2 corresponding to the multiple transistors 101 and 102.

FIG. 1B is a timing chart explaining the operation of the NOT circuit of FIG. 1A described above. FIG. 1B illustrates the potential of the signal transmitted to signal line INL1 that switches the on/off state of transistor 106, the potential of the input signal of NOT circuit 100 transmitted to signal line INL2, and the potential of the output signal of NOT circuit 100 transmitted to signal line OUTL.

In Figure 1B, period T0 is the non-operating period of the NOT circuit (before operation), period T1 is the operating period of the NOT circuit, and period T2 is the non-operating period of the NOT circuit (after operation). Note that the non-operating period is a period during which the input signal to the logic circuit is not switched. Furthermore, the operating period is a period during which the input signal to the logic circuit is switched.

During the non-operating period of period T0, the potential of signal line INL2 remains at L level (L in the diagram) and the potential is not switched. As a result, power gating of the NOT circuit 100 can be performed, and the potential of signal line INL1 is set to L level (L in the diagram) during period T0. The transistor 106 is turned off. The current flowing between the signal line OUTL and the power supply line VLL is cut off, allowing power gating of each logic circuit, such as the NOT circuit 100.

During the operation period of period T1, the potential of signal line INL2 is switched. Therefore, power gating of NOT circuit 100 is not performed, and the potential of signal line INL1 is set to the H level (H in the figure). Transistor 106 is turned on. It is possible to change the potential of the output signal of signal line OUTL in response to changes in the potential of the input signal of signal line INL2. In the example of Figure 1B, the logic circuit is a NOT circuit, and in this case, the output signal of signal line OUT can be the inverted logic of the input signal of signal line INL2.

During the non-operating period of period T2, the potential of signal line INL2 remains at the L level (L in the diagram) and the potential is not switched. This allows power gating of the NOT circuit 100, and the potential of signal line INL1 is set to the L level during period T2. The transistor 106 is turned off. The current flowing between the signal line OUTL and the power supply line VLL is cut off, allowing power gating of each logic circuit, such as the NOT circuit 100.

In one embodiment of the present invention, when the signal line INL2, which is an input signal, is at an L level and the signal line OUTL outputs an H level during a non-operation period in which power gating is performed for each logic circuit, the leakage current flowing through the transistor 102 can be reduced. This reduces power consumption caused by the leakage current flowing through the transistor 102. This also makes it easier to maintain the H-level potential of the signal line OUTL. This allows the capacitance value of the storage capacitor connected to the signal line OUT to be reduced in order to maintain the potential. As a result, high-speed operation of the logic circuit can be achieved.

Note that during the period when signal line INL2 maintains the L level, the signal for controlling power gating transmitted to signal line INL1 is switched to the L level. Furthermore, during the period when signal line INL2, which is the input signal, is set to the H level and the period when signal line IHL2, which is the input signal, is frequently switched between the H level and the L level, the signal for controlling power gating transmitted to signal line INL1 is switched to the H level. This configuration makes it easier to maintain the H level potential of signal line OUTL, reduces the frequency of switching the signal for controlling power gating, and enables lower power consumption.

In the case of a multi-input, multi-output logic circuit, there may be multiple wirings corresponding to signal line INL2 and signal line OUTL. In this case, when multiple signal lines INL2 are all at L level and multiple signal lines OUTL are all at H level, the signal for controlling power gating transmitted to signal line INL1 is set to L level. This configuration makes it easier to maintain the H level potential of signal line OUTL, reduces the frequency of switching the signal for controlling power gating, and enables lower power consumption.

<Schematic diagram of semiconductor device>
Fig. 2 is a diagram schematically illustrating a three-dimensional structure of the logic circuit exemplified by the NOT circuit 100 in Fig. 1A. Fig. 3 is a circuit diagram illustrating the connection relationship between transistors 101, 102, and 106, signal lines INL1, INL2, and OUTL, and power supply lines VHL and VLL, which are stacked in the Z direction in accordance with the three-dimensional structure of the NOT circuit 100 in Fig. 2.

In the three-dimensional structure of the logic circuit illustrated in Figure 2, the insulating layers surrounding the conductive and semiconductor layers have been omitted to simplify the drawing. Also, some of the semiconductor layers in Figure 2 are shown with dotted lines to show how they are surrounded by conductive layers via insulating layers.

In the schematic diagrams and circuit diagrams shown in Figures 2 and 3, in order to explain the arrangement of each component, the direction perpendicular to the surface of the substrate on which the NOT circuit 100 is provided is defined as the Z-axis direction. For ease of understanding, the Z-axis direction may also be referred to as the direction perpendicular to the surface of the substrate throughout this specification. Note that "perpendicular" refers to an arrangement at an angle of 85 degrees or greater and 95 degrees or less.

In this specification and drawings, the X, Y, and Z directions may be defined to explain the arrangement of each element. For example, in the schematic diagrams and circuit diagrams shown in Figures 2 and 3, the X, Y, and Z directions are defined to explain the arrangement of each element that makes up the semiconductor device. The X, Y, and Z directions are perpendicular to each other.

In the schematic diagram shown in Figure 2, conductive layers that function as signal line INL2, power supply line VHL, and signal line OUTL are shown on the substrate side. The conductive layers that function as signal line INL2, power supply line VHL, and signal line OUTL are wiring provided on layer L1 in the schematic diagram shown in Figure 3.

The wiring provided in layer L1 corresponds to a conductive layer provided in a semiconductor substrate containing silicon, germanium, silicon-germanium, etc., or in a Si-On-Insulator (SOI) substrate. The wiring provided in layer L1 can be formed, for example, by processing a silicon substrate and filling grooves with a conductor. When forming power supply lines VHL and VLL by processing a silicon substrate, the width and depth of the wiring can be made larger than when the power supply lines VHL and VLL are provided in the upper layer, layer L5. This makes it possible to reduce the voltage drop associated with the placement of the power supply lines VHL and VLL.

In the schematic diagram shown in FIG. 2, conductive layer 101S, semiconductor layer 101I, conductive layer 101D, and conductive layer 101G of transistor 101 are shown above the conductive layers that function as signal line INL2, power supply line VHL, and signal line OUTL (insulating layers around conductive layer 101S, semiconductor layer 101I, conductive layer 101D, and conductive layer 101G are not shown). Conductive layer 101S and conductive layer 101D are electrodes that function as the source or drain of transistor 101. Conductive layer 101G is an electrode that functions as the gate of transistor 101. Semiconductor layer 101I is a semiconductor layer that has a channel formation region of transistor 101. Transistor 101, which includes conductive layer 101S, semiconductor layer 101I, conductive layer 101D, and conductive layer 101G, is a transistor provided in layer L2 in the schematic diagram shown in FIG. 3.

As shown in Figures 2 and 3, transistor 101 is connected to signal line INL2, for example, via conductive layer 101G and conductive layer 101L. As shown in Figures 2 and 3, transistor 101 is connected to power supply line VHL, for example, via conductive layer 101S. As shown in Figures 2 and 3, transistor 101 is connected to signal line OUTL, for example, via conductive layer 101D and conductive layer 101M.

2, the conductive layer 102S, semiconductor layer 102I, conductive layer 102D, and conductive layer 102G of transistor 102 are shown above transistor 101, which has conductive layer 101S, semiconductor layer 101I, conductive layer 101D, and conductive layer 101G (insulating layers around conductive layer 102S, semiconductor layer 102I, conductive layer 102D, and conductive layer 102G are not shown). Conductive layer 102S and conductive layer 102D are electrodes that function as the source or drain of transistor 102. Conductive layer 102G is an electrode that functions as the gate of transistor 102. Semiconductor layer 102I is a semiconductor layer that has a channel formation region of transistor 102. Transistor 102, which has conductive layer 102S, semiconductor layer 102I, conductive layer 102D, and conductive layer 102G, is a transistor provided in layer L3 of the schematic diagram shown in FIG. 3.

As shown in Figures 2 and 3, transistor 102 is connected to signal line INL2 via, for example, conductive layer 102G, conductive layer 101G, and conductive layer 101L. Because conductive layer 102G is connected to conductive layer 101G, the conductive layer can be shared. As shown in Figures 2 and 3, transistor 102 is connected to transistor 106 via conductive layer 102S and conductive layer 102L. As shown in Figures 2 and 3, transistor 102 is connected to signal line OUTL via conductive layer 101D, conductive layer 102N, conductive layer 102M, and conductive layer 101M.

Figure 2 shows a configuration in which layer L2, which has pMOS transistor 101, and layer L3, which has nMOS transistor 102, are driven by the same conductive layer that functions as a gate. It is also possible to form layer L2, which has pMOS transistor 101, and layer L3, which has nMOS transistor 102, on separate substrates and then bond them together.

In the schematic diagram shown in Figure 2, transistors 101 and 102 are shown as having a GAA nanosheet structure. The GAA nanosheet structure allows the semiconductor layer to be surrounded by a conductive layer that functions as the gate, enabling transistors to be miniaturized and highly integrated.

Semiconductor layers 101I and 102I are preferably made of silicon. Transistors 101 and 102 having silicon in semiconductor layers 101I and 102I are also called Si transistors. When semiconductor layers 101I and 102I are made of silicon, silicon and silicon germanium can be alternately stacked, and silicon germanium can be used as a sacrificial layer that is selectively etched. Therefore, semiconductor layers 101I and 102I can be surrounded by conductive layers 101G and 102G that function as gates.

Transistor 101 can be made a pMOS by selectively doping p-type impurities into semiconductor layer 101I. Transistor 102 can be made an nMOS by selectively doping n-type impurities into semiconductor layer 102I. As shown in Figure 2, a CFET can be formed by stacking transistor 101, a pMOS with a GAA nanosheet structure, and transistor 102, an nMOS with a GAA nanosheet structure, in the Z direction.

Conductive layers 101L, 101M, 102L, 102M, 102N, 101G, and 102G are preferably made of a material containing a metal element such as titanium or aluminum. Furthermore, conductive layers 101S and 101D, as well as conductive layers 102S and 102D, are preferably made of conductive silicon. When semiconductor layers 101I and 102I are made of silicon, conductive silicon can be formed by epitaxially growing semiconductor layers 101I and 102I and adding an element that imparts conductivity to the silicon obtained.

Note that while the schematic diagram in Figure 2 shows transistors 101 and 102 as having a GAA nanosheet structure, other structures are also possible. Transistors 101 and 102 may have any structure that allows for miniaturization and high integration, and may also have, for example, a FinFET structure or a planar structure.

2, the conductive layer 106S, semiconductor layer 106I, conductive layer 106D, and conductive layer 106G of transistor 106 are shown above transistor 102, which has conductive layer 102S, semiconductor layer 102I, conductive layer 102D, and conductive layer 102G (insulating layers around conductive layer 106S, semiconductor layer 106I, conductive layer 106D, and conductive layer 106G are not shown). Conductive layer 106S and conductive layer 106D are electrodes that function as the source or drain of transistor 106. Conductive layer 106G is an electrode that functions as the gate of transistor 106. Semiconductor layer 106I is a semiconductor layer that has a channel formation region of transistor 106. Transistor 106, which has conductive layer 106S, semiconductor layer 106I, conductive layer 106D, and conductive layer 106G, is a transistor provided in layer L4 of the schematic diagram shown in FIG. 3.

As shown in Figures 2 and 3, transistor 106 is connected to signal line INL1 via, for example, conductive layer 106G and conductive layer 102L. As shown in Figures 2 and 3, transistor 106 is connected to transistor 102 via conductive layer 106S and conductive layer 102L. As shown in Figures 2 and 3, transistor 106 is connected to power supply line VLL via conductive layer 101D.

In the schematic diagram shown in Figure 2, the transistor 106 is shown as having a planar structure. It is also possible to provide a conductive layer that functions as a back gate in the region that overlaps with the conductive layer 106G, sandwiching the semiconductor layer 106I. The transistor 106 may have any structure that allows for miniaturization and high integration of the transistor, and may also have, for example, a planar structure, a vertical transistor, or a GAA nanosheet structure.

The conductive layers 106L, 106G, 106S, and 106D are preferably made of a material containing a metal element such as titanium or aluminum. The semiconductor layer 106I is preferably made of indium oxide. A transistor 106 having indium oxide in the semiconductor layer 106I is also referred to as an IO transistor. For a configuration example of an IO transistor, see Embodiment 2 described below.

Furthermore, an oxide semiconductor such as In-Ga-Zn oxide (IGZO) can also be used for the semiconductor layer 106I. A transistor having IGZO in the semiconductor layer 106I is called an IGZO transistor. The above-described transistor having indium oxide in the semiconductor layer 106I and a transistor having IGZO in the semiconductor layer 106I are collectively referred to as OS transistors.

Here we will explain indium oxide, which is used in the semiconductor layer of IO transistors.

The indium oxide film that can be used for the semiconductor layer 106I of the transistor 106 is a film through which one or both of hydrogen and oxygen move more easily than, for example, an In-Ga-Zn oxide film (IGZO film). Therefore, it can be said that the indium oxide film is a film through which one or both of hydrogen and oxygen are more easily supplied and from which one or both of hydrogen and oxygen are more easily discharged than, for example, an IGZO film. Note that it can be said that the indium oxide film is a film that is more permeable to one or both of hydrogen and oxygen than, for example, an IGZO film. In other words, it can be said that the indium oxide film is a film that has lower barrier properties against one or both of hydrogen and oxygen than, for example, an IGZO film.

An indium oxide film has a property that oxygen permeates at, for example, 1×10 ²⁰ atoms/cm ³ to 2×10 ²¹ atoms/cm ³ , preferably 2×10 ²⁰ atoms/cm ³ to 1×10 21 atoms/cm ³ , during heat treatment at a heating temperature of 400° C. for 8 hours. Furthermore, an indium oxide film has a property that oxygen diffuses within crystal grains at, for example, 1×10 ²⁰ atoms/cm ³ to 2×10 ²¹ atoms/cm ³ , preferably 2×10 ²⁰ atoms/cm ³ to 1×10 ²¹ atoms/cm ³ , during heat treatment at a heating temperature ^of 400° C. for 8 hours.

Oxygen in the indium oxide film diffuses through the crystal grains and the crystal grain boundaries, thereby reducing V 2 _O present in the crystal grains or the crystal grain boundaries, thereby improving the electrical characteristics and reliability of the transistor.

The content of the first element in the semiconductor layer of the IO transistor is preferably low. Furthermore, the concentration of the first element in the semiconductor layer is preferably low. In particular, the concentration of the first element in the channel formation region is preferably low. Here, the first element is at least one of boron, carbon, aluminum, silicon, zinc, and gallium. In other words, in the semiconductor layer, the concentration of any one of boron, carbon, aluminum, silicon, zinc, and gallium is preferably low; it is more preferable that the concentrations of two selected from boron, carbon, aluminum, silicon, zinc, and gallium are low; and it is even more preferable that the concentrations of all of boron, carbon, aluminum, silicon, zinc, and gallium are low. The concentration of the first element in the semiconductor layer is, for example, preferably 1 atomic% or less, more preferably 0.1 atomic% or less, and even more preferably 0.01 atomic% (100 ppm) or less. The preferred concentration of the first element in the semiconductor layer can also be said to be the preferred concentration of the first element in the channel formation region.

By lowering the concentrations of boron, carbon, aluminum, and silicon in the semiconductor layer, the crystallinity of the semiconductor layer can be improved.

When the semiconductor layer of an IO transistor contains gallium atoms, the gallium atoms bond with excess oxygen atoms to form a Ga-O structure. The Ga-O structure functions as an acceptor that traps electrons. Therefore, in IO transistors containing gallium atoms and excess oxygen atoms, the threshold voltage fluctuation in PBTS (Positive Bias Temperature Stress) testing is large. Therefore, by lowering the gallium concentration in the semiconductor layer, the threshold voltage fluctuation in PBTS testing can be reduced. This results in a transistor with high reliability when a positive bias is applied. Note that the same phenomenon as when gallium atoms are included can occur when the semiconductor layer of an IO transistor contains zinc atoms.

Furthermore, compared to indium atoms, aluminum atoms, gallium atoms, and zinc atoms have stronger bonding strength with oxygen atoms. Therefore, by lowering the concentrations of aluminum, gallium, and zinc in the indium oxide film, it is possible to prevent a decrease in permeability to oxygen.

Furthermore, impurities such as the first element contained in the indium oxide film can become crystal nuclei. By reducing the impurities in the indium oxide film as much as possible, the number of crystal nuclei can be reduced, promoting the growth of larger crystal grain sizes.

Furthermore, when the indium oxide film is a polycrystalline film, the first element segregates at the grain boundaries, forming an oxide containing the first element. Because this oxide has insulating properties, it may cause a decrease in the on-state current or field-effect mobility of the transistor. By reducing the first element in the indium oxide film as much as possible, the on-state current or field-effect mobility of the transistor can be increased.

Furthermore, by reducing the impurities in the indium oxide film, impurity scattering can be suppressed. Therefore, a transistor with high field-effect mobility can be realized. For example, by setting the concentration of the first element in the semiconductor layer within the above preferred range, the field-effect mobility of the transistor can be 100 cm ² /(V·s) or more, preferably 150 cm ² /(V·s) or more, more preferably 200 cm ² /(V·s) or more, and further preferably 250 cm ² /(V·s) or more. Therefore, an OS transistor including an IO transistor can be a transistor with excellent field-effect mobility.

The band gap of indium oxide is 2.5 eV or more and 3.7 eV or less. By using indium oxide, which has a wide band gap, for the semiconductor layer, the off-state current of the transistor can be reduced, and the power consumption of the semiconductor device can be significantly reduced.

IO transistors are accumulation-type transistors that use electrons as the majority carriers. In other words, the carriers in IO transistors are electrons. Assuming that the carrier relaxation time is a constant value, the smaller the effective mass of the electron (carrier), the higher the electron mobility (carrier mobility). In other words, by using a metal oxide with a small effective electron mass in the semiconductor layer of a transistor, the on-current or field-effect mobility of the transistor can be increased.

The effective mass of electrons in indium oxide is small. Therefore, by using indium oxide, which has a small effective electron mass, in the semiconductor layer, it is possible to realize transistors with large on-state currents, high field-effect mobility, and high frequency characteristics (also called f-characteristics). Another feature of indium oxide is that the effective mass of electrons is almost independent of crystal orientation. Furthermore, the effective mass of electrons in indium oxide is smaller than the effective mass of electrons in silicon, for example. Therefore, from the perspective of effective electron mass, the f-characteristics of a transistor using indium oxide in the channel formation region are higher than the f-characteristics of a Si transistor.

Indium oxide has a large effective mass of holes. Therefore, by using indium oxide, which has a large effective mass of holes, in the semiconductor layer, it is possible to realize a transistor with an extremely small off-state current. Furthermore, the effective mass of holes in indium oxide is larger than the effective mass of holes in, for example, silicon. Therefore, from the perspective of the effective mass of holes, the off-state current of an IO transistor is significantly smaller than the off-state current of a Si transistor.

The off-state current per μm of channel width of an IO transistor at room temperature can be set to 1×10 ⁻¹⁷ A/μm or less, preferably 1×10 ⁻¹⁸ A/μm or less, and more preferably 1× ^{10 −19 A} /μm or less. The off-state current per μm of channel width at 85° C. can be set to 1×10 ⁻¹⁶ A/μm or less, preferably 1×10 −17 A/μm or less, and more preferably 1×10 ⁻¹⁸ A/μm or less. Therefore, OS transistors including IO transistors can be transistors with an extremely low off-state current per μm of channel width at 85° C.

As described above, by using an OS transistor as the transistor 106, it is possible to realize a transistor that has both field-effect mobility comparable to that of a Si transistor and extremely low leakage current. Therefore, when a CMOS logic circuit is configured using a Si pMOS transistor and an OS nMOS transistor, the transistor sizes can be made approximately the same. By using a combination of OS transistors and Si transistors, a CMOS logic circuit that consumes low power and operates at high speed can be realized.

Furthermore, because IO transistors have semiconductor layers with excellent crystallinity, they can be made into highly reliable transistors. By combining IO transistors with Si transistors, it is possible to realize highly reliable CMOS logic circuits capable of high-speed operation.

The above is an explanation of a transistor that has indium oxide in the semiconductor layer.

In the schematic diagram shown in FIG. 2, conductive layers functioning as a signal line INL1 and a power supply line VLL are shown in the upper layer of the transistor 106, which has conductive layer 106S, semiconductor layer 106I, conductive layer 106D, and conductive layer 106G. The conductive layers functioning as the signal line INL1 and power supply line VLL are wiring provided on layer L5 in the schematic diagram shown in FIG. 3.

In the circuit diagram shown in Figure 3, transistors 101, 102, and 106 of a logic circuit such as a NOT circuit are provided on layers L2 to L4, and a power supply line VHL that transmits a high power supply potential is provided on layer L1. In the circuit diagram shown in Figure 3, transistors 101, 102, and 106 of a logic circuit such as a NOT circuit are provided on layers L2 to L4, and a power supply line VLL that transmits a low power supply potential is provided on layer L5. This configuration makes it possible to arrange the power supply lines, logic circuits, and signal lines so that they overlap in the Z direction. This allows for shorter wiring between the logic circuits and signal lines, and between the logic circuits and power supply lines. Furthermore, even when a transistor for controlling power gating and wiring that controls this transistor are added, it is possible to prevent a decrease in integration level and an increase in layout area.

The circuit diagram shown in Figure 3 also illustrates a configuration in which pMOS transistor 101 is provided in layer L2, and a power supply line VHL that transmits a high power supply potential is provided in layer L1. The circuit diagram shown in Figure 3 also illustrates a configuration in which nMOS transistor 106 is provided in layer L4, and a power supply line VLL that transmits a low power supply potential is provided in layer L5. The circuit diagram shown in Figure 3 also illustrates a configuration in which transistor 106 is provided in layer L4, and a signal line INL1 that transmits a signal to control transistor 106 is provided in layer L5. This configuration makes it possible to shorten the length of the wiring between the signal line and the transistor, and the length of the wiring between the power supply line and the transistor.

Also shown is a configuration in which transistor 101, which is controlled by the same signal, is provided on layer L2, and transistor 102 is provided on layer L3. This configuration makes it possible to shorten the wiring connecting transistors 101 and 102, which are arranged on layers adjacent in the Z direction. Also shown is a configuration in which signal line INL1, which transmits a signal to control transistors 101 and 102, is provided on layer L1. This configuration makes it possible to shorten the length of the wiring between the signal line and the transistor, compared to when signal line INL1 is arranged on an upper layer, for example, layer L5.

As described above, by providing transistor 106, which functions as a switch that controls power gating, on a logic circuit that includes transistors 101 and 102, it is possible to arrange transistors for power gating on a logic circuit basis without reducing the degree of integration of the transistors. Furthermore, by using an OS transistor, which has both field-effect mobility comparable to that of a Si transistor and extremely low leakage current, as transistor 106, it is possible to reduce power consumption due to leakage current during power gating and to suppress a decrease in operating speed during normal operation.

<Configuration example of connection between transistor and signal line>
Although an example of a semiconductor device to which one embodiment of the present invention is applied has been described above in which power supply lines and signal lines are arranged in a layer below a logic circuit, one embodiment of the present invention is not limited to this. Hereinafter, a structural example of a connection between a transistor and a signal line according to one embodiment of the present invention, which is different from the structural example shown in FIG. 3, will be described. Note that the above description will be used for the same structure as that shown in FIG. 3, and repeated description may be omitted.

FIG. 4 is a circuit diagram in which signal lines INL1, INL2, and OUTL are arranged on layer L5, which is an upper layer above layers L2 to L4 in which transistors 101, 102, and 106 that constitute the logic circuit illustrated by NOT circuit 100 in FIG. 3 are provided, and power supply lines VHL and VLL are arranged on layer L1, which is a lower layer.

The signal lines INL1, INL2, and OUTL provided on layer L5 can be more easily connected to the wiring provided on multiple layers above layer L5 than the wiring provided on layers L1 to L4. Therefore, by arranging the signal lines INL1, INL2, and OUTL that transmit signals from the logic circuit on layer L5, the degree of freedom in arranging the wiring for connections within the logic circuit can be increased.

By arranging the signal lines INL1, INL2, and OUTL in multiple layers above layer L5, the effects of noise between the wiring that transmits signals can be reduced. Furthermore, by arranging the signal lines INL1, INL2, and OUTL in multiple layers above layer L5, the effects on the signal lines INL1, INL2, and OUT caused by the switching of the on/off states of the transistors provided on layers L2 to L4 can be reduced.

Furthermore, the power supply lines VHL and VLL that transmit the power supply potential are arranged across the area where the logic circuit is located. When the power supply lines VHL and VLL that transmit the power supply potential are formed by processing a silicon substrate or the like corresponding to the lower layer L1, the width and depth of the power supply lines VHL and VLL can be made wider than when they are arranged in the upper layer L5. This makes it possible to reduce the voltage drop associated with the arrangement of the power supply lines VHL and VLL.

Figure 5 is a circuit diagram in which power supply lines VHL and VLL are arranged on both layer L5, which is the layer above layers L2 to L4 in which transistors 101, 102, and 106 that make up the logic circuit illustrated as a NOT circuit in Figure 4 are provided, and layer L1, which is the layer below.

By arranging power supply lines VHL and VLL in the upper layer L5 in addition to layer L1, the voltage drop associated with the arrangement of power supply lines VHL and VLL can be further reduced. Furthermore, by arranging power supply lines VHL and VLL in multiple layers, layers L1 and L5, transistors in layers close to layer L5 can be connected to the power supply lines VHL and VLL of layer L5, and transistors close to layer L1 can be connected to the power supply lines VHL and VLL of layer L1. This makes it easier to connect to transistors 101, 102, and 106 that make up the logic circuit.

FIG. 6 is a circuit diagram in which the transistor 106 of layer L4, which is provided in the logic circuit illustrated as the NOT circuit 100 in FIG. 3, is omitted from the logic circuit that functions as another NOT circuit 103.

Depending on the logic circuit, power gating may be performed infrequently. In this case, the configuration includes a NOT circuit 100 that includes a transistor 106, and a NOT circuit 103 that does not include a transistor 106. In this configuration, compared to a case in which a transistor 106 is provided as in the NOT circuit 100, it is possible to partially omit the transistor 106 and signal line INL1, as in the NOT circuit 103. It is effective to apply this configuration to logic circuits in which power gating cannot be expected to reduce power consumption.

FIG. 7 is a circuit diagram in which the transistor 106 constituting the logic circuit exemplified by the NOT circuit 100 in FIG. 6 is provided on layer L3.

In Figures 3 and 4, examples have been described in which layers for providing nMOSs are provided across two layers, layer L3 and layer L4, and different types of semiconductor layers are arranged, but when different types of semiconductor layers are arranged, they can also be arranged in the same layer. For example, if transistors 102 and 106 are both OS transistors, they can be arranged side by side in the same layer, layer L3 or layer L4. It is also possible to omit the layer having nMOS Si transistors.

Furthermore, one embodiment of the present invention can be configured such that additional functions are added by connecting transistors to signal lines of a logic circuit.

FIG. 8A illustrates the configuration of a circuit diagram in which a transistor 104A and a capacitance element CS are added to the semiconductor device that functions as the NOT circuit described in FIG. 1A. Note that the above description applies to the configuration shown in FIG. 8A that is similar to that of FIG. 1A, and repeated description may be omitted.

One of the source or drain of transistor 104A is connected to signal line INL2. The other of the source or drain of transistor 104A is connected to one electrode of capacitance element CS. The gate of transistor 104A is connected to signal line INS1. The other end of capacitance element CS is connected to a constant potential line, for example, a ground line.

Signal line INS1 is a wiring that transmits a signal that controls the on/off state of transistor 104A. Transistor 104A functions as a switch. Transistor 104A is in the on state when the potential of signal line INS1 is H level, and in the off state when it is L level.

The transistor 104A is preferably an n-channel transistor, particularly an OS transistor. An OS transistor can have both field-effect mobility comparable to that of a Si transistor and extremely low leakage current. Therefore, by turning off the transistor 104A, a charge corresponding to the potential of the signal transmitted to the signal line INL2 can be held in the capacitor CS.

Figure 8B is a timing chart explaining the operation of the circuit having the transistor 104A and capacitor CS in Figure 8A described above. Figure 8B illustrates the potential of the signal transmitted to signal line INS1 that switches the on/off state of transistor 104A, the input signal of NOT circuit 100 transmitted to signal line INL2, and the input signal corresponding to the potential held in capacitor CS.

In Figure 8B, at time T11, the signal on signal line INS1 is set to H level, turning transistor 104A on. Signal line INL2 and capacitance element CS are brought into a conductive state. As a result, the potential V1 of the input signal can be applied to capacitance element CS. Thereafter, the signal on signal line INS1 is set to L level, turning transistor 104A off. Signal line INL2 and capacitance element CS are brought into a non-conductive state. As a result, the potential V1 of the input signal is held in capacitance element CS. The potential V1 held in capacitance element CS can continue to be held even after the potential of signal line INL2 changes.

Also in Figure 8B, at time T12, the signal on signal line INS1 is again set to H level, turning transistor 104A on. Signal line INL2 and capacitance element CS are brought into a conductive state. As a result, the potential V2 of the input signal can be applied to capacitance element CS. Thereafter, the signal on signal line INS1 is set to L level, turning transistor 104A off. Signal line INL2 and capacitance element CS are brought into a non-conductive state. As a result, the potential V1 of the input signal is held in capacitance element CS. The potential V2 held in capacitance element CS can continue to be held even after the potential of signal line INL2 changes.

As shown in FIG. 8B, the circuit in FIG. 8A that includes the transistor 104A and the capacitor CS can hold a potential corresponding to the input signal on the signal line INL2 at any timing. Therefore, the potential corresponding to the input signal held in the capacitor CS can be used as backup data for the input signal. By using this backup data, a semiconductor device that functions as a NOT circuit can quickly restore a state using the backup data. Furthermore, since the signal line INL2 and the capacitor CS are electrically disconnected during the period when the transistor 104A is in the off state, the addition of the capacitor CS can reduce the impact on the charging and discharging of the signal supplied to the signal line INL2 during normal operation.

Furthermore, Figure 9A illustrates a configuration example different from that of Figure 8A in a semiconductor device that functions as the NOT circuit described in Figure 1A. Figure 9A illustrates a circuit diagram configuration in which transistor 104B is added. Note that in the configuration illustrated in Figure 9A, the above explanation is used for the same configuration as in Figure 1A, and repeated explanation may be omitted.

One of the source or drain of transistor 104B is connected to signal line INL0. The other of the source or drain of transistor 104B is connected to signal line INL2. The gate of transistor 104B is connected to signal line INS2.

Signal line INS2 is a wiring that transmits a signal that controls the on/off state of transistor 104B. Transistor 104B is a transistor that functions as a switch. Transistor 104B is in the on state when the potential of signal line INS2 is H level, and in the off state when it is L level.

The transistor 104B is preferably an n-channel transistor, particularly an OS transistor. An OS transistor can be a transistor that combines field-effect mobility comparable to that of a Si transistor with extremely low leakage current. Therefore, by turning off the transistor 104B, a charge corresponding to the potential of the signal transmitted to the signal line INL0 can be held in the signal line INL2.

Figure 9B is a timing chart explaining the operation of the circuit having transistor 104B in Figure 9A described above. Figure 9B illustrates the potential of the signal transmitted to signal line INS2 that switches transistor 104B between the on and off states, and the potential of the input signal to NOT circuit 100 transmitted to signal lines INL0 and INL2.

In Figure 9B, at time T21, the signal on signal line INS2 is set to L level, turning transistor 104B off. Signal lines INL0 and INL2 become non-conductive. Signal line INL2 can hold signal D21, which was supplied immediately before by signal line INL0, specifically a charge corresponding to the potential of signal D21. Signal D21 held in signal line INL2 can continue to be held even if the supply of the signal to signal line INL0 is stopped.

Also in Figure 9B, at time T22, the signal on signal line INS2 goes high, turning on transistor 104B. Signal lines INL0 and INL2 become conductive. This allows the signal D22 on signal line INL0 to be transmitted to signal line INL2.

As shown in FIG. 9B, the circuit including the transistor 104B in FIG. 9A can maintain a potential corresponding to the signal on the signal line INL2 at any timing. Therefore, the circuit can continue to operate even when the supply of a signal to the signal line INL0 is stopped. Furthermore, as described above, the transistor 104B, which is an OS transistor, can maintain a potential corresponding to the signal on the signal line INL2 by turning it off, so the circuit can maintain the signal immediately before turning it off.

<Logic circuit configuration example>
Although the NOT circuit has been described above as an example of a semiconductor device to which one embodiment of the present invention is applied, one embodiment of the present invention is not limited thereto. Hereinafter, a semiconductor device that functions as a logic circuit of one embodiment of the present invention, which is different from a NOT circuit, will be described.

[NAND circuit]
10 shows an example of a semiconductor device that functions as a NAND circuit. A NAND circuit 111 shown in Fig. 10 includes transistors 101a, 101b, 102a, 102b, and 106. The transistors 101a, 101b, 102a, 102b, and the transistor 106 are connected as shown in Fig. 10.

As shown in FIG. 10, the NAND circuit 111 is connected to the power supply lines VHL and VLL. A signal line INL1 is connected to the gate of transistor 106. A signal line INL2_A is connected to the gates of transistors 101a and 102a. A signal line INL2_B is connected to the gates of transistors 101b and 102b. A signal line OUTL is connected to either the source or drain of transistors 101a, 101b, and 102a.

In FIG. 10, transistors 101a and 101b correspond to the above-mentioned transistor 101, and transistors 102a and 102b correspond to the above-mentioned transistor 102. Signal lines INL2_A and INL2_B correspond to the above-mentioned signal line INL2.

As shown in FIG. 10, by providing transistor 106 between transistor 102b and power supply line VLL, power gating can be achieved by turning transistor 106 off when not in operation, thereby reducing the power consumption of NAND circuit 111. Specifically, by turning transistor 106 off during a period when there is no change in the potential input to signal line INL2_A and signal line INL2_B, leakage current from transistors 102a and 102b can be suppressed.

[NOR circuit]
11 shows an example of a semiconductor device that functions as a NOR circuit. A NOR circuit 112 shown in FIG. 11 includes transistors 101a, 101b, 102a, 102b, 106a, and 106b. The transistors 101a, 101b, 102a, 102b, 106a, and 106b are connected as shown in FIG.

As shown in FIG. 11, the NOR circuit 112 is connected to the power supply lines VHL and VLL. A signal line INL1 is connected to the gates of transistors 106a and 106b. A signal line INL2_A is connected to the gates of transistors 101a and 102a. A signal line INL2_B is connected to the gates of transistors 101b and 102b. A signal line OUTL is connected to either the source or drain of transistors 101a, 102a, and 102b.

In FIG. 11, transistors 101a and 101b correspond to the above-mentioned transistor 101, transistors 102a and 102b correspond to the above-mentioned transistor 102, and transistors 106a and 106b correspond to the above-mentioned transistor 106. Signal lines INL2_A and INL2_B correspond to the above-mentioned signal line INL2.

As shown in FIG. 11, by providing transistor 106a between transistor 102a and power supply line VLL and transistor 106b between transistor 102b and power supply line VLL, power gating can be achieved by turning off transistors 106a and 106b when not in operation. As a result, the power consumption of the NOR circuit 112 can be reduced. Specifically, by turning off transistors 106a and 106b during a period when there is no change in the potential input to signal line INL2_A and signal line INL2_B, leakage current from transistors 102a and 102b can be suppressed.

[flip flop]
As described above, since leakage current can be suppressed in NOT circuits, NOR circuits, and NAND circuits, the occurrence of leakage current can be suppressed in various logic circuits such as flip-flops, frequency dividers, and ring oscillators.

FIG. 12A shows a D flip-flop as an example of a semiconductor device that functions as a flip-flop. In the D flip-flop 113 shown in FIG. 12A, an input signal is input to terminal D, and a clock signal is input to terminal CLK. Furthermore, a first output signal is output from terminal Q, and a second output signal is output from terminal Qb.

FIG. 12B shows an example of a specific circuit configuration of the D flip-flop 113. The D flip-flop 113 includes NAND circuits 111a to 111d. The terminals of the NAND circuits 111a to 111d and the D flip-flop 113 are connected as shown in FIG. 11.

Here, by using a semiconductor device that functions as the NAND circuit shown in FIG. 10 as the NAND circuits 111a to 111d, it is possible to reduce leakage current in the NAND circuits 111a to 111d. This makes it possible to reduce power consumption in the D flip-flop 113 when it is not operating. Note that it is sufficient that at least a portion of the NAND circuits 111a to 111d included in the D flip-flop 113 are configured to reduce off-state current when it is not operating.

Note that, although this embodiment shows an example in which a D flip-flop is formed as the flip-flop, this is not limited thereto, and leakage current can be reduced by using the configuration shown in this embodiment in various flip-flops such as an RS flip-flop, a JK flip-flop, and a T flip-flop.

Furthermore, Figure 12C shows an example of a frequency divider circuit formed using the configuration described in this embodiment. The frequency divider circuit 114 shown in Figure 12C has D flip-flops 113a to 113c. The D flip-flops 113a to 113c have the same configuration as the D flip-flop 113 shown in Figure 12A. The terminal CLK of the D flip-flop 113a functions as the input terminal of the frequency divider circuit 114, the terminal Qb is connected to the terminal D, and the terminal Q is connected to the terminal CLK of the D flip-flop 113b. The terminal Qb of the D flip-flop 113b is connected to the terminal D, and the terminal Q is connected to the terminal CLK of the D flip-flop 113c. The terminal Qb of the D flip-flop 113c is connected to the terminal D, and the terminal Q functions as the output terminal of the frequency divider circuit 114.

Here, because the D flip-flops 113a to 113c are D flip-flops with reduced leakage current, it is possible to reduce the leakage current in the D flip-flops 113a to 113c. This makes it possible to suppress an increase in leakage current in the frequency divider circuit 114 and reduce power consumption when not in operation. Note that although the frequency divider circuit 114 shown in Figure 12C uses three D flip-flops, this is not limited to this and can be set as appropriate.

[Register]
13 shows an example of a semiconductor device that functions as a register. The register 115 shown in FIG. 13 includes NOT circuits 100a and 100b and switches 161 and 162. The NOT circuit 100a includes transistors 101a, 102a, and 106a. The NOT circuit 100b includes transistors 101b, 102b, and 106b. The transistors 101a, 102a, 106a, 101b, 102b, and 106b and the switches 161 and 162 are connected as shown in FIG.

Register 115 is connected to power supply lines VHL and VLL as shown in FIG. 13. Signal line INL1 is connected to the gates of transistors 106a and 106b. Signal line INL1 is connected to the gates of transistors 101a and 102a via switch 161. Either the source or drain of transistors 101a and 102a is connected to the gates of transistors 101b and 102b and signal line OUTL. Either the source or drain of transistors 101b and 102b is connected to the gates of transistors 101a and 102a via switch 162.

In Figure 13, NOT circuits 100a and 100b correspond to the NOT circuit 100 described above, transistors 101a and 101b correspond to the transistor 101 described above, transistors 102a and 102b correspond to the transistor 102 described above, and transistors 106a and 106b correspond to the transistor 106 described above. Switches 161 and 162 can use transistors fabricated in the same layer as any of the transistors described above.

By turning switch 161 on and switch 162 off, the input signal to register 115 provided to signal line INL2 is taken into register 115. Also, by turning switch 161 off and switch 162 on, the input signal taken into register 115 is held.

As shown in FIG. 13, transistor 106a is provided between transistor 102a and power supply line VLL, and transistor 106b is provided between transistor 102b and power supply line VLL. With this configuration, power gating can be achieved by turning off transistors 106a and 106b when not in operation, reducing the power consumption of register 115. Specifically, by turning off transistors 106a and 106b during a period when the input signal on signal line INL2 remains unchanged at L level, leakage current from transistors 102a and 102b can be prevented.

[Ring Oscillator]
An example of a semiconductor device that functions as a ring oscillator is shown in Fig. 14. The ring oscillator 116 shown in Fig. 13 has NOT circuits 100a to 100e. The NOT circuits 100a to 100e are connected as shown in Fig. 14.

Here, because the NOT circuit 100 with reduced leakage current described above is used as the NOT circuits 100a to 100e, it is possible to reduce the leakage current in the NOT circuits 100a to 100e. This makes it possible to suppress an increase in leakage current in the ring oscillator 116 and reduce power consumption when not in operation. Note that although the ring oscillator shown in FIG. 14 uses five NOT circuits, this is not limited to this and the number can be set as appropriate.

As described above, in a semiconductor device, a transistor with a low off-state current, such as an OS transistor, is provided between the power supply lines used in the CMOS logic circuit that is provided in series with the pMOS and nMOS, and when the nMOS Si transistor is off, the transistor with a low off-state current is turned off. This makes it possible to suppress leakage current that occurs in the CMOS logic circuit provided in the semiconductor device and reduce power consumption during operation.

This embodiment can be implemented by appropriately combining at least a portion of it with other embodiments described in this specification.

(Embodiment 2)
In this embodiment, a structural example of a transistor applicable to the IO transistor described in Embodiment 1 and a structural example of a transistor applicable to a Si transistor will be described.

<Configuration Example 1 of IO Transistor>
15A and 15D show an example of a cross-sectional configuration of a transistor applicable to the IO transistor of the first embodiment.

Figure 15A is a plan view of a transistor 200 applicable to the IO transistor of embodiment 1 above. Figure 15B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in Figure 15A, and is also a cross-sectional view of transistor 200 in the channel length direction. Figure 15C is a cross-sectional view of the portion indicated by the dashed dotted line A3-A4 in Figure 15A, and is also a cross-sectional view of transistor 200 in the channel width direction. Figure 15D is a cross-sectional view of the portion indicated by the dashed dotted line A5-A6 in Figure 15A. Note that some elements have been omitted from the plan view of Figure 15A to clarify the illustration. Some elements may also be omitted from the subsequent plan views.

Transistor 200 has a conductive layer 205, an insulating layer 221 on conductive layer 205, an insulating layer 222 on insulating layer 221, an insulating layer 224 on insulating layer 222, a layer 229 on insulating layer 224, a semiconductor layer 230 covering layer 229, conductive layers 242a and 242b on semiconductor layer 230, an insulating layer 250 on semiconductor layer 230, and a conductive layer 260 on insulating layer 250.

In the transistor 200, the conductive layer 260 functions as a first gate electrode (which can also be referred to as an upper gate electrode or a top gate electrode), and the insulating layer 250 functions as a first gate insulating layer. The conductive layer 205 functions as a second gate electrode (which can also be referred to as a lower gate electrode, a bottom gate electrode, or a back gate), and the insulating layers 224, 222, and 221 each function as a second gate insulating layer. The conductive layer 242a functions as one of a source electrode and a drain electrode, and the conductive layer 242b functions as the other of the source electrode and the drain electrode.

An insulating layer 275 is provided on the conductive layers 242a and 242b, and an insulating layer 280 is provided on the insulating layer 275. An opening 289 is formed in the insulating layers 280 and 275, reaching the insulating layer 222 and the semiconductor layer 230, and the opening 289 overlaps the region between the conductive layers 242a and 242b. In a plan view, the side of the insulating layer 280 at the opening 289 coincides or approximately coincides with the side of the conductive layer 242a and the side of the conductive layer 242b.

Insulating layer 250 and conductive layer 260 are disposed inside opening 289. Insulating layer 282 is provided in contact with the upper surface of insulating layer 280, the upper end of insulating layer 250, and the upper surface of conductive layer 260. Insulating layer 283 is provided on insulating layer 282. Insulating layer 216 is provided below insulating layer 221, insulating layer 214 is provided below insulating layer 216 and conductive layer 205, and insulating layer 212 is provided below insulating layer 214. Insulating layer 212 is provided on a substrate (not shown). Insulating layers 212, 214, 280, 282, 283, and 285 function as interlayer films.

Openings reaching conductive layer 242a are formed in insulating layers 285, 283, 282, 280, and 275, and conductive layers 243a and 241a are provided in the openings. Insulating layer 241a is provided in contact with the sidewalls of the openings, and conductive layer 243a is provided inside insulating layer 241a. Openings reaching conductive layer 242b are formed in insulating layers 285, 283, 282, 280, and 275, and conductive layers 243b and 241b are provided in the openings. Insulating layer 241b is provided in contact with the sidewalls of the openings, and conductive layer 243b is provided inside insulating layer 241b. Conductive layers 243a and 243b function as vias connecting wiring or the like provided on transistor 200 to the source or drain of transistor 200.

The semiconductor layer 230 includes a channel formation region, and a source region and a drain region sandwiching the channel formation region, as in the transistor 200. That is, the semiconductor layer 230 has a channel formation region, a source region, and a drain region. At least a portion of the channel formation region overlaps with the conductive layer 260. The source region overlaps with the conductive layer 242a, and the drain region overlaps with the conductive layer 242b. Note that the source region and the drain region can be interchanged. The source region and the drain region are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region. The semiconductor layer 230 may have a single-layer structure or a stacked structure of two or more layers.

The semiconductor layer 230 is physically separated between adjacent transistors 200 in the channel length direction. This configuration prevents the Row Hammer effect and the passing gate effect when the transistor 200 is used in a memory cell. The Row Hammer effect refers to a phenomenon in which accumulated charge leaks to an adjacent word line, causing malfunction, in a configuration in which the word lines (conductive layers 260) of two transistors are adjacent and the channel formation regions of the two transistors are connected. The passing gate effect refers to a phenomenon in which charge moves to a floating gate or gate insulating layer, forming an unintended current path or causing changes in characteristics such as threshold voltage fluctuations.

In the semiconductor device shown in Figures 15A to 15D, the opening in which conductive layer 243a is provided is located so as not to overlap layer 229. Furthermore, in a plan view, conductive layer 243a is provided so as to be located between layer 229 and conductive layer 260. This configuration allows the shape of the opening to be improved. Therefore, contact defects can be suppressed, and a highly reliable semiconductor device can be provided.

Here, we will explain layer 229, which can improve the crystallinity of semiconductor layer 230.

Layer 229 has crystals. Layer 229 functions as a seed or nucleus when a process for increasing the crystallinity of semiconductor layer 230 is performed. In other words, layer 229 functions as a seed or nucleus when crystals of semiconductor layer 230 grow. In this specification and the like, layer 229 or the crystals contained in layer 229 can be referred to as seed crystals or crystal nuclei. Furthermore, since layer 229 has crystals, layer 229 can be referred to as a crystalline portion.

Note that a step of removing layer 229 may be performed after treatment to increase the crystallinity of semiconductor layer 230. In this case, although layer 229 shown in Figures 15A and 15B and semiconductor layer 230 around layer 229 are removed, transistor 200 can be obtained using semiconductor layer 230 with increased crystallinity. Therefore, even if layer 229 is not shown in transistors 200A to 200C described later, transistors 200A to 200C can be obtained using semiconductor layer 230 with increased crystallinity.

Indium oxide crystals have a cubic crystal structure (bixbyite type). When indium oxide is used for the semiconductor layer 230, the layer 229 preferably has, for example, a hexagonal or trigonal crystal structure. In this case, when the layer 229 has crystals with a <001> crystal orientation with respect to the surface or surface on which the layer 229 is formed, the semiconductor layer 230 can be formed with crystals with a <111> crystal orientation. When the crystals of the layer 229 have a <001> crystal orientation with respect to the surface or surface on which the layer 229 is formed, the c-axis of the crystals is perpendicular to the surface or surface on which the layer 229 is formed. Note that a crystal with a hexagonal or trigonal crystal structure can sometimes be referred to as a crystal with a layered structure. Therefore, the above structure can be understood as a structure in which a semiconductor layer 230 having crystals with a cubic crystal structure is formed on a layer 229 having crystals with a layered structure. In other words, it can be thought of as a layered structure fabricated using heteroepitaxial growth technology or a technology similar to heteroepitaxial growth.

In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by placing a superscript bar above the number; however, due to formatting constraints, in this specification, numbers may be expressed by placing a - (minus sign) before them instead of placing a bar above them. Individual orientations indicating directions within a crystal are expressed in [ ], collective orientations indicating all equivalent orientations are expressed in < >, individual planes indicating crystal planes are expressed in ( ), and collective planes with equivalent symmetry are expressed in { }.

In this specification, the crystal orientation of a crystal refers to the orientation relative to the surface of the film containing the crystal or the surface on which it is formed. Therefore, for example, a crystal with a crystal orientation of <100> can be said to be a crystal whose (100) plane is parallel to the surface of the film containing the crystal or the surface on which it is formed.

Specific examples of materials that can be used for layer 229 include zinc oxide, In-Ga oxide, gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), In-Al-Zn oxide, In-Ga-Zn oxide, and In-Sn-Zn oxide. Layer 229 preferably uses In-Ga-Zn oxide. In this case, layer 229 contains indium, gallium, zinc, and oxygen. Specifically, the composition is preferably In:Ga:Zn = 1:1:1 [atomic ratio] or a composition close thereto, or In:Ga:Zn = 1:3:2 [atomic ratio] or a composition close thereto. Metal oxides with these compositions are suitable for layer 229 because they readily form a layered structure.

In-Ga-Zn oxide, In-Sn-Zn oxide, and the like tend to have a CAAC structure. When an oxide having a CAAC structure is used for layer 229, the c-axis of the crystal nuclei is perpendicular to the surface of layer 229 or the surface on which it is formed. In other words, by using an oxide that tends to have a CAAC structure for layer 229, it is possible to improve the controllability of the crystal orientation of the crystal nuclei.

When an oxide that easily has a CAAC structure is used for layer 229, a semiconductor layer 230 having crystals with a <111> crystal orientation can be formed.

Layer 229 can also be made of an oxide whose crystals have a cubic crystal structure. When the crystals of layer 229 have the same crystal structure as the crystals of semiconductor layer 230, semiconductor layer 230 can grow epitaxially using layer 229 as a nucleus, thereby improving the crystallinity of semiconductor layer 230. Note that crystals of oxides containing Group 3 elements in the periodic table tend to have a cubic crystal structure. Furthermore, Group 3 elements in such crystals exist primarily as trivalent cations. Therefore, layer 229 preferably contains at least one element that can become a trivalent cation. The element that layer 229 contains that can become a trivalent cation is preferably scandium, yttrium, cerium, gadolinium, erbium, ytterbium, or the like.

For example, oxides containing one or both of yttrium and zirconium, erbium oxide, etc. can be used for layer 229. Examples of oxides containing one or both of yttrium and zirconium include yttrium oxide, zirconium oxide, and yttrium zirconium oxide.

Furthermore, it is preferable that the difference (also referred to as lattice mismatch) between the lattice constant or unit lattice vector of the crystal nucleus and the lattice constant or unit lattice vector of the crystal of the semiconductor layer 230 is small. By using an oxide that reduces the lattice mismatch for the layer 229, the crystallinity of the semiconductor layer 230 can be improved.

One method for evaluating the degree of lattice mismatch is the lattice mismatch. The lattice mismatch Δa [%] of the crystals of the formed film relative to the crystals of the film to be formed is calculated using the following formula (1). Hereinafter, the lattice mismatch Δa of the crystals of the formed film relative to the crystals of the film to be formed may be simply referred to as the lattice mismatch Δa of the formed film relative to the film to be formed.

In the formula (1), L ₁ is the lattice constant or unit lattice vector of the crystal of the forming film, and L ₂ is the lattice constant or unit lattice vector of the crystal of the film to be formed.

The lattice mismatch Δa of the crystal grains in semiconductor layer 230 with respect to the crystal nuclei is preferably between -10% and 10%, more preferably between -5% and 5%, and even more preferably between -3% and 3%. By using a material for layer 229 that reduces the lattice mismatch with semiconductor layer 230, the crystallinity of semiconductor layer 230 can be improved.

For example, the lattice constant of indium oxide crystal (bixbyite type) is said to be 1.01194 nm. Furthermore, the lattice constant of yttrium oxide crystal (bixbyite type) is said to be 1.05976 nm. Therefore, the lattice mismatch between the crystal of indium oxide and the crystal of yttrium oxide is -4.5%. Therefore, when indium oxide is used for semiconductor layer 230, yttrium oxide can be used for layer 229.

For example, the lattice constant of erbium oxide crystal (bixbyite type) is said to be 1.0582 nm. Therefore, the lattice mismatch between the crystal of erbium oxide and the crystal of indium oxide is -4.4%. Therefore, when indium oxide is used for semiconductor layer 230, erbium oxide can be used for layer 229.

For example, the lattice constant of _{Zr0.9Y0.1O1.95} crystal (fluorite type) _, which is an example of yttrium _zirconium oxide _, is 0.51481 nm (see ICSD coll.code.248790). Therefore, the lattice mismatch of indium oxide with _{Zr0.9Y0.1O1.95} crystal is -1.7%. Therefore, when indium oxide is used for the semiconductor layer 230, yttrium zirconium oxide can be suitably _used for the layer 229. Note that yttrium zirconium oxide contains yttrium, zirconium, and oxygen.

By adding yttrium or yttrium oxide to zirconium oxide, that is, by increasing the yttrium content in yttrium zirconium oxide to greater than 0 atomic%, the crystal structure of zirconium oxide can be stabilized. However, if the content becomes too high, the crystal structure of yttrium zirconium oxide may change from a cubic system to another system, so it is preferable that the content not be too high. Therefore, for example, the yttrium content in yttrium zirconium oxide is preferably 2 atomic% or more and 15 atomic% or less, and more preferably 5 atomic% or more and 10 atomic% or less.

Alternatively, indium oxide may be used for layer 229. By using indium oxide for layer 229, the semiconductor layer 230 can be grown homoepitaxially using layer 229 as a nucleus, thereby improving the crystallinity of the semiconductor layer 230. In this case, the crystal orientation of the crystals in layer 229 and the crystal orientation of the crystals in semiconductor layer 230 coincide or nearly coincide.

There are no particular limitations on the material that can be used for layer 229. Layer 229 may be made of an insulating material, a semiconductor material, or a conductive material. When a semiconductor material is used for layer 229, layer 229 may be considered to be part of semiconductor layer 230.

FIG. 15A shows an example in which layer 229 is circular in plan view. However, the present invention is not limited to this. In plan view, layer 229 can be, for example, a circle or an approximately circle such as an oval, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, a star-shaped polygon, or any of these polygons with rounded corners. Furthermore, when sputtered particles are used as layer 229, layer 229 may be triangular or hexagonal in plan view.

The above is a description of layer 229. Note that in the example configurations of IO transistors described hereinafter in this specification, a configuration equivalent to layer 229 can be applied to improve the crystallinity of the configuration equivalent to semiconductor layer 230.

<Configuration Example 2 of IO Transistor>
16A to 16D show examples of cross-sectional structures of transistors applicable to the IO transistor of the first embodiment.

FIG. 16A is a plan view of a transistor 200A applicable to the IO transistor of the first embodiment. FIG. 16B is a cross-sectional view taken along dashed lines A1-A2 in FIG. 16A. FIG. 16C is a cross-sectional view taken along dashed lines A3-A4 in FIG. 16A. FIG. 16D is a cross-sectional view taken along dashed lines A5-A6 in FIGS. 16B and 16C.

Transistor 200A has a conductive layer 220, a conductive layer 240, a semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.

The conductive layer 220 is provided on the insulating layer 210, the insulating layer 280 is provided on the conductive layer 220, and the conductive layer 240 is provided on the insulating layer 280. An opening 290 is formed in the conductive layer 240 and the insulating layer 280, reaching the conductive layer 220, and the semiconductor layer 230 is provided along the bottom and sidewalls of the opening 290. The semiconductor layer 230 has a portion that contacts the conductive layer 240 and a portion that contacts the conductive layer 220.

In transistor 200A, conductive layer 260 functions as a gate electrode, and insulating layer 250 functions as a gate insulating layer. Furthermore, conductive layer 220 functions as one of a source electrode and a drain electrode, and conductive layer 240 functions as the other of the source electrode and the drain electrode.

The semiconductor layer 230 has a region that overlaps with the conductive layer 260 via the insulating layer 250. At least a portion of this region functions as the channel formation region of the transistor 200A. One of the region of the semiconductor layer 230 near the conductive layer 220 and the region of the semiconductor layer 230 near the conductive layer 240 functions as the source region, and the other functions as the drain region. In other words, the channel formation region is sandwiched between the source region and the drain region.

The semiconductor layer 230 is provided inside the opening 290. Furthermore, the transistor 200A has a configuration in which one of the source and drain electrodes (conductive layer 220 in this case) is located at the bottom and the other of the source and drain electrodes (conductive layer 240 in this case) is located at the top, allowing current to flow vertically. In other words, a channel is formed along the side of the opening 290. This allows the transistor 200A to occupy a smaller area than a planar transistor in which the channel formation region, source region, and drain region are separately provided on the XY plane. This allows for a higher degree of integration of the semiconductor device. Furthermore, when the transistor 200A is used in a memory device, the memory capacity per unit area can be increased. Since the channel length direction of the transistor 200A can be said to have a component in the height direction (vertical direction), the transistor 200A can be called a VFET (Vertical Field Effect Transistor), vertical transistor, vertical channel transistor, vertical channel transistor, etc.

As shown in Figure 16D, by forming the opening 290 so that it has a circular shape in a plan view, the semiconductor layer 230, insulating layer 250, and conductive layer 260 are arranged concentrically. Therefore, the distance between the conductive layer 260 and the semiconductor layer 230 is approximately uniform, allowing a gate electric field to be applied to the semiconductor layer 230 approximately uniformly.

Furthermore, in this embodiment, an example is shown in which opening 290 is circular in plan view. By making it circular, the processing precision when forming the opening can be improved, and openings of a fine size can be formed. However, the present invention is not limited to this. In plan view, opening 290 can be, for example, a circle or an approximately circle such as an oval, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, a star-shaped polygon, or any of these polygons with rounded corners.

<Configuration Example 3 of IO Transistor>
17A to 17D show examples of cross-sectional structures of transistors applicable to the IO transistor of the first embodiment.

Figure 17A is a plan view of transistor 200B applicable to the IO transistor of embodiment 1 above. Figure 17B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in Figure 17A, and is also a cross-sectional view of transistor 200B in the channel length direction. Figure 17C is a cross-sectional view of the portion indicated by the dashed dotted line A3-A4 in Figure 17A, and is also a cross-sectional view of transistor 200B in the channel width direction. Figure 17D is a cross-sectional view of the portion indicated by the dashed dotted line A5-A6 in Figure 17A.

Transistor 200B has conductive layer 220, conductive layer 240a and conductive layer 240b on insulating layer 280, layer 229a on conductive layer 240a, layer 229b on conductive layer 240b, semiconductor layer 230 on layers 229a and 229b, insulating layer 250 on semiconductor layer 230, and conductive layer 260 on insulating layer 250. Insulating layer 280 is located on conductive layer 220.

The conductive layer 220 is provided on the insulating layer 210, an insulating layer 280 is provided on the conductive layer 220, and conductive layers 240a and 240b are provided on the insulating layer 280. A groove 291 reaching the conductive layer 220 is formed in the conductive layers 240a and 240b and the insulating layer 280, and the semiconductor layer 230 is provided along the bottom and sidewalls of the groove 291. The semiconductor layer 230 has a portion in contact with layers 229a and 229b and the conductive layers 240a and 240b, and a portion in contact with the conductive layer 220. Furthermore, an insulating layer 283 is provided on the insulating layer 250. An insulating layer 285 is provided on the insulating layer 283. In addition, conductive layers 243a and 243b, which have portions in contact with layers 229a and 229b and conductive layers 240a and 240b, are provided over layers 229a and 229b and conductive layers 240a and 240b. In addition, conductive layer 246, which is in contact with conductive layers 243a and 243b, is provided over conductive layers 243a and 243b.

In transistor 200B, conductive layer 260 functions as a gate wiring, and insulating layer 250 functions as a gate insulating layer. Furthermore, conductive layer 220 functions as one of a source electrode and a drain electrode, and conductive layers 240a and 240b function as the other of the source electrode and the drain electrode.

The semiconductor layer 230 has a region that overlaps with the conductive layer 260 via the insulating layer 250. At least a portion of this region functions as the channel formation region of the transistor 200B. One of the region of the semiconductor layer 230 near the conductive layer 220 and the region of the semiconductor layer 230 near the conductive layer 240 functions as the source region, and the other functions as the drain region. In other words, the channel formation region is sandwiched between the source region and the drain region.

The semiconductor layer 230 is provided inside the groove 291. Therefore, the conductive layer 260 is provided to extend in the direction in which the groove 291 extends. Furthermore, in the transistor 200B, one of the source and drain electrodes (conductive layer 220 in this case) is located on the bottom, and the other of the source and drain electrodes (conductive layers 240a and 240b in this case) is located on the top, so that current flows vertically. In other words, a channel is formed along the side surface of the groove 291. As a result, compared to a planar transistor in which the channel formation region, source region, and drain region are provided separately on the XY plane, the transistor 200B can occupy a smaller area. This allows for a higher degree of integration of the semiconductor device. Furthermore, when the transistor 200B is used in a memory device, the memory capacity per unit area can be increased.

The semiconductor layer 230 contacts the bottom and side surfaces of the recess in the conductive layer 220. The presence of a recess in the conductive layer 220 increases the contact area between the semiconductor layer 230 and the conductive layer 220. This reduces the contact resistance between the semiconductor layer 230 and the conductive layer 220.

The width D1 of the groove 291 is set by the film thickness of the semiconductor layer 230, insulating layer 250, and conductive layer 260 provided within the groove 291. In a plan view, the side surface of the conductive layer 260 provided in the groove 291 has a portion that faces the side surface of the semiconductor layer 230, with the insulating layer 250 interposed therebetween. Therefore, the channel width of the transistor 200B is determined by the width D2 of the semiconductor layer 230 (see Figure 17D). The channel width of the transistor 200B can be calculated as "2 x D2".

Increasing the width D2 of the semiconductor layer 230 increases the channel width per unit area, thereby increasing the on-current. Meanwhile, the area occupied by the transistor 200B, for example, the area of the transistor 200B in a planar view, is roughly determined by the width D1 of the groove 291 and the width D2 of the semiconductor layer 230. Reducing the width D1 of the groove 291 and the width D2 of the semiconductor layer 230 reduces the area occupied by the transistor 200B, allowing for a higher level of integration of the semiconductor device.

The channel length of transistor 200B is the distance between the source region and the drain region. In other words, the channel length of transistor 200B is determined by the thickness of insulating layer 280 on conductive layer 220. Therefore, the channel length of transistor 200B does not affect the area occupied by transistor 200B, for example, the area of transistor 200B in a planar view. This makes it possible to improve productivity and yield in forming insulating layer 280 and forming grooves 291 in insulating layer 280. Furthermore, the on-current of transistor 200B increases, enabling improved frequency characteristics.

<Configuration Example 4 of IO Transistor>
18A to 18C show examples of cross-sectional structures of transistors applicable to the IO transistor of Embodiment 1. FIG.

Figure 18A is a plan view of transistor 200C applicable to the IO transistor of embodiment 1 above. Figure 18B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in Figure 18A, and is also a cross-sectional view of transistor 200C in the channel length direction. Figure 18C is a cross-sectional view of the portion indicated by the dashed dotted line B1-B2 in Figure 18A, and is also a cross-sectional view of transistor 200B in the channel width direction. Note that some components (such as insulating layer 280) are omitted from Figure 18A.

Transistor 200C has multiple semiconductor layers (semiconductor layers 230_1 to 230_3), an insulating layer 250, a conductive layer 260, a pair of conductive layers 220 (conductive layer 220a and conductive layer 220b), a pair of conductive layers 240 (conductive layer 240a and conductive layer 240b), and multiple pairs of buffer layers 231 (buffer layer 231_1 to buffer layer 231_4). Here, a transistor having three semiconductor layers will be described. A portion of the insulating layer 250 functions as a gate insulating layer, and a portion of the conductive layer 260 functions as a gate electrode. The conductive layers 220a and 220b function as a source electrode and a drain electrode, respectively. The conductive layers 240a and 240b also function as a source electrode and a drain electrode, respectively.

Transistor 200C is provided on an insulating layer 210 provided on a substrate (not shown). The insulating layer 210 functions as a base insulating layer.

A pair of buffer layers 231_1 is provided on the insulating layer 210, and a semiconductor layer 230_1 is provided on the buffer layer 231_1. The pair of buffer layers 231_1 are provided at a distance from each other, and the semiconductor layer 230_1 has a region between a portion located on one buffer layer 231_1 and a portion located on the other buffer layer 231_1 that does not overlap with either buffer layer 231_1.

A pair of buffer layers 231_2 are provided on the semiconductor layer 230_1. Each of the pair of buffer layers 231_2 is provided at a position overlapping with the buffer layer 231_1. The semiconductor layer 230_1 has a region between the pair of buffer layers 231_2 that does not overlap with either of the buffer layers 231_2.

Similarly to the above, semiconductor layer 230_2, buffer layer 231_3, semiconductor layer 230_3, and buffer layer 231_4 are stacked in this order on buffer layer 231_2. Furthermore, conductive layer 240a and conductive layer 240b are each provided on buffer layer 231_4.

A region of the semiconductor layer 230 that is located between a pair of buffer layers 231 located below the semiconductor layer 230 and between a pair of buffer layers 231 located above the semiconductor layer 230, and that does not overlap with either buffer layer 231, functions as a channel formation region.

Conductive layer 220a and conductive layer 220b are provided in contact with the side of each semiconductor layer 230, the outer side of each buffer layer 231 (the side opposite to the conductive layer 260), and the outer side of conductive layer 240a or conductive layer 240b, respectively. Conductive layer 220 can connect each semiconductor layer 230 and conductive layer 240.

Here, as shown in Figure 18B etc., each semiconductor layer 230 preferably has a protruding portion 21t that protrudes outward beyond the respective side surfaces of the buffer layer 231 that it contacts. Furthermore, the conductive layer 220 is preferably provided in contact with not only the side surfaces of the protruding portion 21t of each semiconductor layer 230, but also the upper and lower surfaces of the protruding portion 21t. This increases the contact area between the conductive layer 220 and the semiconductor layer 230, thereby reducing the contact resistance between them.

The insulating layer 250 is provided so as to surround the regions of the semiconductor layer 230 that do not overlap with the buffer layer 231. The insulating layer 250 is provided in contact with the upper and lower surfaces of each semiconductor layer 230 in the regions that do not overlap with each pair of buffer layers 231. Furthermore, as shown in FIG. 18C, the insulating layer 250 is provided so as to surround the upper, lower, and both side surfaces of the semiconductor layer 230 in the channel width direction.

The conductive layer 260 is arranged to surround the top, side, and bottom surfaces of each semiconductor layer 230 via the insulating layer 250. This allows an electric field from the conductive layer 260 to be applied to the channel formation region of the semiconductor layer 230 from above and below, thereby increasing the on-current per semiconductor layer 230. Furthermore, by having multiple semiconductor layers 230, the on-current of the transistor 200C can be made extremely high.

Furthermore, insulating layers 250 are provided between each buffer layer 231 and conductive layer 260, and between each conductive layer 240 and conductive layer 260, to insulate them. This makes it possible to prevent electrical short circuits between the buffer layer 231 and conductive layer 260, and between the conductive layer 240 and conductive layer 260.

Insulating layer 280 is provided covering conductive layer 220 and conductive layer 240. A slit is provided in insulating layer 280, and insulating layer 250 and conductive layer 260 are formed inside the slit. Insulating layer 250 is provided along the side of the slit in insulating layer 280, and conductive layer 260 is provided so as to fill the slit in insulating layer 250. A portion of conductive layer 260 functions as wiring that follows the shape of the slit.

Here, it is preferable to use a metal oxide (oxide semiconductor) that exhibits semiconductor properties for the semiconductor layer 230. In this case, it is preferable to use a conductive metal oxide (oxide conductor) for the conductive layer 220 that is in contact with the semiconductor layer 230. By using a metal oxide for the conductive film that is in contact with the metal oxide-containing semiconductor layer 230, it is possible to reduce the contact resistance therebetween, reduce the wiring load, and increase the on-current of the transistor 200C.

The conductive layer 220 preferably contains a metal oxide containing the same metal element as the semiconductor layer 230. In particular, it is preferable that both the conductive layer 220 and the semiconductor layer 230 contain a metal oxide containing indium. This reduces the contact resistance between the semiconductor layer 230 and the conductive layer 220. Furthermore, when processing the conductive layer 220 and the semiconductor layer 230, etching can be performed under the same conditions, simplifying the manufacturing process and improving yield and productivity. It is particularly preferable to use a metal oxide containing indium and tin for the conductive layer 220, as this can increase conductivity.

Furthermore, it is preferable to use a metal oxide for the buffer layer 231 as well. By using a metal oxide for the buffer layer 231, the buffer layer 231 itself can function as a source electrode or a drain electrode. Furthermore, by using a metal oxide for both the buffer layer 231 and the conductive layer 220, not only can the contact resistance between them be reduced, but the current path between the semiconductor layer 230 and the conductive layer 240 can also be expanded, further reducing the load on the wiring.

Although the above describes a configuration in which three semiconductor layers 230 are stacked, the number of semiconductor layers 230 included in the transistor 200C is not limited to this. The more semiconductor layers 230 there are, the greater the on-state current of the transistor 200C can be, which is preferable. On the other hand, the fewer the number of semiconductor layers 230, the simpler the manufacturing process for the transistor 200C can be, and the higher the yield can be.

<Constituent materials of semiconductor device>
Materials that can be used for the IO transistor of this embodiment will be described below. Note that each layer constituting the IO transistor of this embodiment may have a single-layer structure or a stacked-layer structure.

[Semiconductor layer]
Indium oxide is preferably used for the semiconductor layer 230 of the semiconductor device. By using indium oxide for the semiconductor layer, the transistor can have large on-state current and high frequency characteristics.

In this specification and the like, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). For example, examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be described below. Fig. 19A is a schematic diagram showing the carrier concentration dependence of the Hall mobility for silicon (Si) and indium oxide (InO _x ), and Fig. 19B is a schematic diagram showing the carrier concentration dependence of the Hall mobility for IGZO.

First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as indicated by the arrows in Figure 19B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as indicated by the arrows in Figure 19A (see Non-Patent Document 2). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic the indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties closer to silicon. Note that the characteristics of indium oxide shown in Figure 19A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 19A.

19A , the low carrier concentration range R1 has extremely high hole mobility, and can therefore be considered a carrier concentration range suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, range R1 is a range including a carrier concentration value of 1×10 ¹⁵ cm ⁻³ , for example, a range of 1×10 ¹⁴ cm ⁻³ or more and 1×10 ¹⁸ cm ⁻³ or less. By sufficiently reducing the carrier concentration, it is expected that the hole mobility value can be increased to approximately 270 cm ² /(V·s).

In addition, in indium oxide, the region where the carrier concentration is in range R1 can contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. Range R2 is a range in which the carrier concentration value includes 1×10 ²⁰ cm ⁻³ , for example, a range of 1×10 ¹⁹ cm ⁻³ or more and 1×10 ²² cm ⁻³ or less. By sufficiently increasing the carrier concentration, it is expected that the resistivity can be reduced to 1×10 ⁻⁴ Ω·cm or less.

Indium oxide, the region with a carrier concentration in range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the region contains the same element as the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. It is particularly preferable to use an element whose oxide has conductive or semiconducting properties. Methods for supplying an element that increases the carrier concentration include forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, and plasma treatment. Unless otherwise specified, the present specification does not limit the use of mass separation. For example, in the present specification, a method of supplying ions after mass separation is referred to as ion implantation, and a method of supplying ions without mass separation is referred to as ion doping.

In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be considered an oxide capable of valence electron control. Note that with IGZO, strain can form in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so strain does not need to be formed in the film as with IGZO. Minimizing strain in the film is expected to improve reliability. For example, by creating regions with carrier concentrations in range R1 and range R2 shown in Figure 19A within an indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in silicon-based transistors is generally known. However, valence electron control in indium oxide-based transistors is a novel technological concept that would not normally be conceived.

By using the above technical concept, the transistor containing indium oxide in this specification has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) A high on-state current (in other words, high mobility). (2) A low off-state current. (3) Normally-off operation is possible. (4) High reliability. (5) A high cutoff frequency (fT). For example, the transistor containing indium oxide in this specification has high mobility, a low off-state current, and is normally-off operation. This transistor has high mobility and is different from a normally-on transistor.

Note that a semiconductor being i-type can be said to have the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in Figure 19B, in IGZO, the lower the carrier concentration, the lower the hole mobility. Therefore, when Ef = Ei, the carriers disappear (in other words, the material becomes similar to an insulator), and the transistor may no longer function. On the other hand, in indium oxide, as shown in Figure 19A, the lower the carrier concentration, the higher the hole mobility. When Ef = Ei, the hole mobility is maximized. In other words, a transistor containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Note that a transistor containing indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor containing indium oxide can be normally-off and achieve high field-effect mobility.

Note that normally-off refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. Furthermore, normally-off can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated by a constant current method. More specifically, Vth is defined as the gate voltage (Vg) when the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of the transistor is 1 nA (1 × 10 ⁻⁹ A). Furthermore, Vsh is the gate voltage (Vg) at the intersection between the tangent to the maximum slope when the drain current (Id) in the Id-Vg characteristics of the transistor is expressed logarithmically and the line of Id = 1 pA (1 × 10 ^-12 A), or the Vg at the intersection between the line extrapolated from between two points where the slope when Id in the Id-Vg characteristics of the transistor is expressed logarithmically and the line of Id = 1 pA. For example, if either one or both of Vth and Vsh are zero or a positive value, the transistor can be considered to be normally off.

Furthermore, in a transistor containing indium oxide, the film structure in contact with the indium oxide film is important for making the semiconductor i-type, i.e., achieving Ef = Ei. For example, in a transistor containing indium oxide, a film structure in which a silicon oxide film in contact with the indium oxide film, a hafnium oxide film, and a silicon nitride film are stacked is one example. With this film structure, a highly reliable semiconductor device with Ef = Ei can be obtained.

In the above film configuration, instead of the silicon oxide film, a film containing oxygen, such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film, can also be used. Also, in the above film configuration, instead of the silicon nitride film, a silicon nitride oxide film, a silicon oxynitride film, or the like can also be used. Furthermore, the hafnium oxide film, which is located closer to the indium oxide film than the silicon nitride film, functions as a gettering site for hydrogen.

The above film configuration can also be considered as a stacked structure of a film capable of supplying oxygen to the indium oxide film from the indium oxide film side (e.g., a silicon oxide film), a film capable of gettering hydrogen (e.g., a hafnium oxide film), and a film that suppresses the penetration of oxygen and hydrogen (e.g., a silicon nitride film). With this configuration, oxygen vacancies in the indium oxide film are filled with oxygen in the silicon oxide film. Furthermore, hydrogen in the indium oxide film is captured by the hafnium oxide film by heat treatment or the like. Furthermore, the provision of a silicon nitride film results in a film configuration that reduces the penetration of oxygen and hydrogen from the outside. In other words, the above film configuration allows the indium oxide film to become closer to i-type. Therefore, a transistor having the above-described indium oxide film has high field-effect mobility and high reliability.

Next, we will explain indium oxide films used in transistors. It is preferable that the indium oxide film be crystalline (i.e., have crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also known as microcrystalline films). In particular, polycrystalline indium oxide films are preferred, and single-crystal films are even more preferred. Single-crystal films do not have grain boundaries. Impurities that impede carrier flow (typically, insulating impurities, insulating oxides, etc.) tend to segregate at grain boundaries. Using a single-crystal film can suppress carrier scattering at grain boundaries, resulting in a transistor with high field-effect mobility. It also offers the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and as few crystal grain boundaries as possible. Note that in a transistor using a polycrystalline film of indium oxide, if there are no crystal grain boundaries in the channel formation region or no crystal grain boundaries are observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to use single-crystal indium oxide.

The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, analysis may be performed by combining multiple of these techniques.

Furthermore, in this specification, a semiconductor layer in which no crystal grain boundaries are observed in the channel formation region, a semiconductor layer in which the channel formation region is contained in a single crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions within the channel formation region can be referred to as a single crystal film. Furthermore, a semiconductor layer in which, within a single crystal grain in the channel formation region, the direction of the other crystal axis changes continuously around a certain crystal axis or a certain crystal orientation as the axis of rotation can be referred to as a single crystal film.

The channel formation region refers to the region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, source electrode, and drain electrode.

The lower the impurity concentration in the indium oxide film in the channel formation region, the better. Impurities in the indium oxide film in the channel formation region can act as a source of carrier scattering, which can reduce field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Impurities in the indium oxide film include boron and silicon. The indium oxide film preferably has a concentration of these impurities of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that carbon, hydrogen, and other elements can be contained in the film formation gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above impurities.

The indium oxide film in the channel formation region may contain elements that can become the same trivalent cations as indium, as long as the crystals maintain a cubic crystal structure (bixbyite type). Examples include elements in Group 13 of the periodic table, such as gallium and aluminum, and elements in Group 3 of the periodic table. These elements exist primarily as trivalent cations in oxides, allowing the carrier concentration of the indium oxide to be maintained low.

By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm ² /(V·s) or more, preferably 100 cm ² /(V·s) or more, more preferably 150 cm ² /(V·s) or more, even more preferably 200 cm ² /(V·s) or more, and still more preferably 250 cm ² /(V·s) or more.

One of the features of an indium oxide film is its high oxygen permeability (diffusibility) compared to an IGZO film. As shown in FIG. 19C , oxygen (O) diffusing into an indium oxide film (denoted as _InOX ) passes through the indium oxide film and is released as oxygen molecules (O ₂ ). It may also react with hydrogen contained in the film and be released as water molecules (H ₂ O). Furthermore, if oxygen vacancies ( _VO ) exist in the film, the diffusing oxygen atoms compensate for the oxygen vacancies. Since oxygen easily diffuses through an indium oxide film, it can be said that oxygen vacancies are more easily compensated for in an indium oxide film compared to an IGZO film.

As such, indium oxide films are easier to reduce oxygen vacancies in than IGZO films, and by applying such indium oxide films to transistors, it is possible to create transistors that exhibit extremely high reliability.

19C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and is released as hydrogen molecules (H ₂ ). Alternatively, hydrogen reacts with oxygen contained in the film and is released as water molecules.

Transistors using indium oxide film are accumulation-type transistors that use electrons as majority carriers. Assuming that the carrier relaxation time is a constant value, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, using indium oxide, which has a small effective electron mass, in a transistor can increase the transistor's on-current or field-effect mobility.

Table 1 shows the effective masses of single-crystal indium oxide (here, In ₂ O ₃ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Furthermore, the effective mass of electrons in indium oxide is characterized by being almost independent of the crystal orientation. Therefore, by using crystalline indium oxide for a transistor, a transistor with high field-effect mobility and high frequency characteristics (also referred to as f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely low off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-state current per 1 μm of channel width can be 1 fA (1×10 ⁻¹⁵ A) or less or 1 aA (1×10 ⁻¹⁸ A) or less in an environment of 125° C., and 1 aA (1×10 ⁻¹⁸ A) or less or 1 zA (1×10 ⁻²¹ A) or less in an environment of room temperature (25° C.). Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

It is preferable to provide a seed layer so that it is in contact with at least a portion of the crystalline indium oxide film. For the seed layer, it is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

One method for evaluating the degree of lattice mismatch is to use the lattice mismatch value shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, an indium oxide film) with respect to the crystals of the seed layer is calculated by Δa = (( _L1 - _L2 ) / _L2 ) × 100, where _L1 is the length or lattice constant of the unit lattice vector of the crystals of the formed film, and _L2 is the length or lattice constant of the unit lattice vector of the crystals of the seed layer.

The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the better, with 0 being most preferable. For example, Δa can be set to between -5% and 5%, preferably between -4% and 4%, more preferably between -3% and 3%, and even more preferably between -2% and 2%.

Here, the indium oxide crystals have a cubic crystal structure (bixbyite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystals with the cubic YSZ crystals is within the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

The crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having hexagonal or trigonal crystal structure can be used under an indium oxide film having cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to [001] and the crystal orientation of the underside of the indium oxide film to [111], the requirements regarding the crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or _trigonal crystals include _wurtzite structure, _YbFe2O4 structure, _Yb2Fe3O7 structure, and _modified structures _thereof . An example of a crystal having _{a YbFe2O4} structure or _{a Yb2Fe3O7} structure is IGZO. Note that a single crystal film of indium oxide can be formed not only on a YSZ substrate but also on an insulating film. On the other hand, it is difficult to form a single crystal film of silicon on an insulating film. Silicon crystals have a diamond structure. As such, indium oxide and silicon have similar properties in terms of single crystals. However, when comparing indium oxide and silicon from the perspective of whether they can form single crystals on an insulating film, they have different properties.

[Insulating layer]
It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 212, insulating layer 214, insulating layer 216, insulating layer 221, insulating layer 222, insulating layer 224, insulating layer 241a, insulating layer 241b, insulating layer 250, insulating layer 275, insulating layer 280, insulating layer 282, insulating layer 283, insulating layer 285, etc.) included in the semiconductor device. Examples of the inorganic insulating film include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of the oxide insulating film include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of the nitride insulating film include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. An insulating layer included in a semiconductor device may be an organic insulating film.

For example, as transistors become more miniaturized and highly integrated, thinner gate insulating layers can cause problems such as leakage current. Using a high-dielectric-constant (high-k) material for the gate insulating layer makes it possible to lower the voltage required for transistor operation while maintaining the physical film thickness. It also makes it possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer. Meanwhile, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is preferable to select materials based on the function of the insulating layer. Materials with a low dielectric constant also have high dielectric strength.

Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, as well as resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide with vacancies. These silicon oxides may contain nitrogen.

Furthermore, a material that can exhibit ferroelectricity may be used for the insulating layer of a semiconductor device. As a material that can exhibit ferroelectricity, it is preferable to use an oxide containing one or both of hafnium and zirconium. Examples of such oxides include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Furthermore, as a material that can exhibit ferroelectricity, a material in which element J1 (here, element J1 is one or more selected from the other of hafnium and zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to a metal oxide containing one of hafnium and zirconium may also be used.

Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the concentration of oxygen vacancies in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in an oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% or more and 10 atomic% or less, more preferably 0.1 atomic% or more and 5 atomic% or less, and even more preferably 0.1 atomic% or more and 3 atomic% or less. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

Furthermore, examples of materials that may exhibit ferroelectricity include metal nitrides containing nitrogen and at least one of the elements M1 and M2. Here, the element M1 is one or more elements selected from aluminum, gallium, indium, etc. Furthermore, the element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. Furthermore, examples of materials that may exhibit ferroelectricity include materials in which the element M3 is added to the above metal nitrides. Furthermore, the element M3 is one or more elements selected from magnesium, calcium, strontium, zinc, cadmium, etc.

Examples of materials that can have ferroelectricity include perovskite-type oxynitrides such as SrTaO ₂ N and BaTaO ₂ N, and GaFeO ₃ with a κ-alumina structure. Examples of materials that can have ferroelectricity include piezoelectric ceramics with a perovskite structure, such as lead titanate (PbTiO _x ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate.

In the above explanation, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides, in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides, in which oxygen is added to the aforementioned metal nitrides, may also be used.

Furthermore, materials that can exhibit ferroelectricity can be, for example, mixtures or compounds made up of multiple materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above can change not only depending on the film formation conditions but also on various processes, in this specification and other documents, materials that exhibit ferroelectricity are not only referred to as ferroelectrics, but also as materials that can exhibit ferroelectricity.

In this specification, a layer of a material that may have ferroelectric properties may be referred to as a ferroelectric layer, metal oxide film, or metal nitride film. Furthermore, in this specification, a device having such a ferroelectric layer, metal oxide film, or metal nitride film may be referred to as a ferroelectric device.

It is preferable that the ferroelectric layer contains crystals having an orthorhombic crystal structure, as this will result in the development of ferroelectricity. The crystal structure of the crystals contained in the ferroelectric layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The ferroelectric layer may also have an amorphous structure. In this case, the ferroelectric layer may have a composite structure having an amorphous structure and a crystalline structure.

Metal oxides containing either or both of hafnium and zirconium are also insulating materials that have the ability to capture or fix hydrogen. Therefore, by using a metal oxide containing either or both of hafnium and zirconium in at least a portion of the gate insulating layer, it is possible to capture or fix hydrogen contained in the oxide semiconductor layer, thereby reducing the hydrogen concentration in the oxide semiconductor layer. Furthermore, a transistor having such a gate insulating layer can function as an FeFET (Ferroelectric Field Effect Transistor).

Furthermore, the electrical characteristics of a transistor using metal oxide can be stabilized by surrounding it with an insulating layer that functions to suppress the permeation of impurities and oxygen. The insulating layer that functions to suppress the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that functions to suppress the permeation of impurities and oxygen can be made of metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; metal nitrides such as aluminum nitride or silicon nitride; or metal nitride oxides such as silicon nitride oxide.

Specific examples of insulating layer materials that function to suppress the permeation of impurities such as water and hydrogen, and oxygen include metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Other examples include metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, and silicon nitride. Other examples include metal nitride oxides such as silicon nitride oxide. Gallium oxide is also an example of an insulating layer material that functions to suppress the permeation of oxygen.

Furthermore, an insulating layer, such as a gate insulating layer, that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer that has a region containing excess oxygen. For example, when an insulating layer that has a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. For insulating layers that are likely to form a region containing excess oxygen, see the description in <Structure of Semiconductor Device>.

It is preferable to use a barrier insulating layer against hydrogen as an insulating layer in contact with an oxide semiconductor layer or an insulating layer provided near the oxide semiconductor layer. When the insulating layer has barrier properties against hydrogen, it can suppress the diffusion of hydrogen into the oxide semiconductor layer. A barrier insulating layer against hydrogen can also be said to be an insulating layer that has a function of suppressing the diffusion of hydrogen.

Insulating materials capable of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), and hafnium silicate. These metal oxides may also contain zirconium, such as oxides containing hafnium and zirconium.

An insulating layer that has the function of capturing or fixing hydrogen preferably has an amorphous structure. In metal oxides with an amorphous structure, some oxygen atoms have dangling bonds, which gives them a high ability to capture or fix hydrogen. Therefore, by having the insulating layer have an amorphous structure, the ability to capture or fix hydrogen can be enhanced.

By making the insulating layer an amorphous structure, it is possible to suppress the formation of grain boundaries. Suppressing the formation of grain boundaries can improve the flatness of the insulating layer. This makes the film thickness distribution of the insulating layer uniform, reducing areas with extremely thin film thickness, thereby improving the dielectric strength of the insulating layer. It also makes it possible to uniform the film thickness distribution of the film provided on the insulating layer. Furthermore, by suppressing the formation of grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels in the grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

Furthermore, the ability to capture or fix the corresponding substance can also be said to have the property of making the corresponding substance difficult to diffuse. Therefore, the ability to capture or fix the corresponding substance can be rephrased as barrier properties.

In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The term "barrier properties" refers to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). When hydrogen is described as a corresponding substance, it refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, a substance bonded to hydrogen, such as a water molecule or OH ⁻ . When impurities are described as corresponding substances, they refer to impurities in a channel formation region or a semiconductor layer, and refer to at least one of, for example, a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (such as N ₂ O, NO, and NO ₂ ), a copper atom, and the like. When oxygen is described as a corresponding substance, it refers to at least one of, for example, an oxygen atom, an oxygen molecule, and the like.

Materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), silicon nitride, and silicon nitride oxide.

The inorganic insulating layers listed as insulating layers with the function of capturing or fixing hydrogen and insulating layers with the function of suppressing hydrogen diffusion also have barrier properties against oxygen. Examples of materials for oxygen barrier insulating layers include oxides containing either or both of aluminum and hafnium, magnesium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing either or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and hafnium silicate.

[Conductive layer]
For the conductive layers (conductive layer 205, conductive layer 220, conductive layer 240, conductive layer 242a, conductive layer 242b, conductive layer 243a, conductive layer 243b, conductive layer 246, conductive layer 260, etc.) included in the semiconductor device, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, lanthanum, etc., or an alloy containing any of the above metal elements as a component, or an alloy combining any of the above metal elements, etc. As the alloy containing any of the above metal elements as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

Furthermore, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; conductive materials containing oxygen, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have the function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, ITO, indium tin oxide containing titanium oxide, ITSO, In-Zn oxide, and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

Furthermore, multiple conductive layers formed from the above materials may be stacked and used. For example, a layered structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing oxygen. Furthermore, a layered structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing nitrogen. Furthermore, a layered structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing oxygen and a conductive material containing nitrogen.

When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as the gate electrode preferably has a stacked structure that combines a material containing the metal element described above and a conductive material containing oxygen. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is more easily supplied to the channel formation region.

[substrate]
Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates having an insulating region within the semiconductor substrate, such as an SOI substrate, are also available. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride or a metal oxide. Other examples include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, these substrates may be provided with elements. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

<Configuration example of Si transistor>
20A and 20B show examples of cross-sectional structures of transistors applicable to the Si transistor of Embodiment 1. Fig. 20A shows an example of a cross-sectional structure of a planar Si transistor in the channel length direction. Fig. 20B shows an example of a cross-sectional structure of a planar Si transistor in the channel width direction.

Transistor 130 is composed of a first semiconductor material. Examples of semiconductors that can be used as the first semiconductor material include silicon, germanium, and silicon germanium. Transistor 130 is provided on semiconductor substrate 131 and has a semiconductor layer 132 made of part of semiconductor substrate 131, a gate insulating film 134, a gate electrode 135, and low-resistance layers 133a and 133b that function as source and drain regions.

Transistor 130 can be used as either a pMOS or nMOS, depending on the impurity elements added. Transistor 130 can be of an appropriate conductivity type depending on the circuit configuration, driving method, etc.

It is preferable that the region where the channel of the semiconductor layer 132 is formed, the region nearby, the low-resistance layer 133a and the low-resistance layer 133b that form the source region or drain region, etc., contain a semiconductor such as a silicon-based semiconductor.

Transistor 130 can also be configured to have regions 176a and 176b, which are LDD (Lightly Doped Drain) regions.

Low-resistance layer 133a and low-resistance layer 133b contain, in addition to the semiconductor material used in semiconductor layer 132, an element that imparts n-type conductivity, such as phosphorus, or an element that imparts p-type conductivity, such as boron.

The gate electrode 135 can be made of a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, such as silicon containing an element that imparts n-type conductivity, such as phosphorus, or an element that imparts p-type conductivity, such as boron. It is particularly preferable to use a high-melting-point material such as tungsten or molybdenum, which has both heat resistance and conductivity, and tungsten is particularly preferred.

In addition, transistor 130 may be replaced with a transistor 190 as shown in Figures 20C and 20D. Figure 20C is an example of the cross-sectional configuration in the channel length direction of a Si transistor with a FinFET structure. Figure 20D is an example of the cross-sectional configuration in the channel length direction of a Si transistor with a FinFET structure.

In the transistor 190, the semiconductor layer 132 (part of the semiconductor substrate) where the channel is formed has a convex shape, and a gate insulating film 134 and a gate electrode 135 are provided along the side and top surfaces of the semiconductor layer. An element isolation layer 181 is also provided between the transistors. Note that the transistor 190 may have an insulating film that contacts the top of the convex portion of the semiconductor substrate and functions as a mask for forming the convex portion. While the example shown here shows a case where the convex portion is formed by processing a part of the semiconductor substrate, a semiconductor layer having a convex shape may also be formed by processing an SOI substrate.

FIG. 21 also shows a cross-sectional structure in which the transistor 200 described above, which is an example of an IO transistor, is stacked on the transistor 130 described above, which is an example of a Si transistor. FIG. 21 illustrates a cross-sectional structure in which a wiring layer 902 having a conductive layer is provided on an element layer 901 having the transistor 130, and an element layer 903 having the transistor 200 is provided on the wiring layer 902 having the conductive layer.

Element layer 901 is a layer containing Si transistors. Wiring layer 902 is a layer containing conductive layers for connecting elements such as upper and lower layer transistors and capacitor elements. Element layer 903 is a layer containing IO transistors.

In the element layer 901 shown in FIG. 21, insulating films 136, 137, and 138 are stacked in this order to cover the transistor 130.

Insulating film 136 functions as a protective film when activating the elements that impart conductivity added to low-resistance layer 133a and low-resistance layer 133b during the manufacturing process of the semiconductor device. Insulating film 136 does not have to be provided if it is not needed.

When a silicon-based semiconductor material is used for the semiconductor layer 132, the insulating film 137 preferably contains an insulating material containing hydrogen. By providing the insulating film 137 containing hydrogen on the transistor 130 and performing heat treatment, the hydrogen in the insulating film 137 terminates the dangling bonds in the semiconductor layer 132, thereby improving the reliability of the transistor 130.

The insulating film 138 functions as a planarizing layer that flattens steps caused by the transistor 130 and other elements provided below it. The top surface of the insulating film 138 may be planarized by a planarization process using a CMP (Chemical Mechanical Polishing) method or the like to improve the flatness of the top surface.

Furthermore, plugs 140 that connect to low-resistance layers 133a, 133b, etc., and plugs 139 that connect to gate electrodes 135 of transistors 130, etc., are embedded in insulating films 136, 137, and 138. Conductive layer 251 is provided on plug 140, and conductive layer 151 is provided on plug 139.

In the wiring layer 902 shown in FIG. 21, a conductive layer 252 is provided. The conductive layer 252 functions as wiring that connects a conductive layer provided in the element layer 903 located above, a conductive layer provided in the element layer 901 located below, and the like. The wiring layer 902 can be provided by stacking conductive layers 252 across multiple layers (multilayering).

The element layer 903 shown in FIG. 21 has a transistor 200 provided above the transistor 130. The transistor 200 is provided with insulating layers 241a and 241b, conductive layers 243a and 243b, as well as insulating layer 241c and conductive layer 243c. The transistor 200 can be connected to the transistor 130 via the insulating layer 241c, conductive layer 243c, conductive layer 251, and plug 140.

In addition, Figure 22 illustrates a cross-sectional structure different from that of Figure 21, in which a wiring layer 902 having a conductive layer is provided over an element layer 901 having a transistor 190, an element layer 903 having a transistor 200 is provided over the wiring layer 902 having the conductive layer, and a memory element 950 having a capacitor 930 and a transistor 940 is further provided over the wiring layer 902, across element layers 904_1 to 904_3.

The element layer 901 shown in Figure 22 illustrates a transistor 190, which is a Si transistor with a FinFET structure. The transistor 190 has a semiconductor layer 132 in which an element isolation layer 181 and a low-resistance layer 133 are provided on a semiconductor substrate 131. The transistor 190 also has a gate insulating film 134 and a gate electrode 135.

In the wiring layer 902 shown in Figure 22, a conductive layer 252 is provided, similar to Figure 21.

In the element layer 903 shown in FIG. 22, a transistor 200 is provided, as in FIG. 21. In FIG. 22, the transistor 200 has a semiconductor layer 230, a conductive layer 242 on the semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.

The memory element 950 shown in Figure 22 is a 1T (transistor) 1C (capacitor) type DOSRAM (Dynamic Oxide Semiconductor Random Access Memory) memory element. DOSRAM is a memory that takes advantage of the low off-state current of transistors, and by using an IO transistor for the transistor 940, it is possible to achieve both high-speed operation and low power consumption.

In element layers 904_1 to 904_3 shown in Figure 22, a memory element 950 including a capacitor 930 and a transistor 940 is stacked. The transistor 940 can be manufactured in a manner similar to that of the transistor 200 described above. The capacitor 930 can be manufactured by stacking conductive layers 932 and 933 with an insulating layer 931 sandwiched therebetween. The multiple memory elements 950 shown in Figure 22 are connected via conductive layers, such as the conductive layer 934, shown in the element layers 904_1 to 904_3.

By stacking a memory circuit having multiple memory elements 950 on element layers 901 and 903 on which a logic circuit is provided, the semiconductor device can have an on-chip memory configuration. With an on-chip memory configuration, the signal propagation distance can be shortened, enabling faster operation of the interface between the logic circuit and the memory circuit. Furthermore, by using an on-chip memory configuration, the number of wirings between the logic circuit and the memory circuit can be increased, improving the bandwidth (also called memory bandwidth) of the memory circuit. Therefore, a memory circuit provided on a logic circuit can be used in applications such as high bandwidth memory (HBM).

This embodiment can be combined with other embodiments as appropriate. Furthermore, in this specification, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

(Embodiment 3)
In this embodiment, application examples of the semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 23A to 24E.

A semiconductor device of one embodiment of the present invention can be used in, for example, electronic components, mainframe computers, space equipment, data centers (also referred to as DCs), and various electronic devices. By using a semiconductor device of one embodiment of the present invention, low power consumption and high performance can be achieved for electronic components, mainframe computers, space equipment, data centers, and various electronic devices.

Electronic devices include, for example, electronic devices with relatively large screens such as televisions, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.

The electronic device of this embodiment may have a sensor (including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).

The electronic device of this embodiment can have a variety of functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, etc.

[Electronic Components]
FIG. 23A shows a perspective view of a substrate (mounting substrate 989) on which an electronic component 980 is mounted. The electronic component 980 shown in FIG. 23A has a semiconductor device 981 inside a mold 984. FIG. 23A omits some parts in order to show the interior of the electronic component 980. The electronic component 980 has lands 985 on the outside of the mold 984. The lands 985 are connected to electrode pads 986, and the electrode pads 986 are connected to the semiconductor device 981 via wires 987. The electronic component 980 is mounted on, for example, a printed circuit board 988. A plurality of such electronic components are combined and connected on the printed circuit board 988 to complete the mounting substrate 989.

The semiconductor device 981 also has a drive circuit layer 982 and a memory layer 983. The memory layer 983 is configured by stacking multiple memory cell arrays. The stacked configuration of the drive circuit layer 982 and the memory layer 983 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 982 and the memory layer 983, it is possible to achieve a so-called on-chip memory configuration, in which the memory is formed directly on the processor, for example. The on-chip memory configuration makes it possible to increase the operation speed of the interface between the processor and memory.

Furthermore, by configuring the memory on-chip, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, making it possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, making it possible to improve the memory bandwidth (also known as memory bandwidth).

Furthermore, it is preferable that the multiple memory cell arrays included in the memory layer 983 are formed using OS transistors and that the multiple memory cell arrays are monolithically stacked. By configuring the multiple memory cell arrays as a monolithic stack, it is possible to improve either or both of the memory bandwidth and memory access latency. Note that bandwidth refers to the amount of data transferred per unit time, and access latency refers to the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 983, it is more difficult to achieve a monolithic stack configuration than OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stack configuration.

Semiconductor device 981 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

Next, Figure 23B shows a perspective view of electronic component 990. Electronic component 990 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). Electronic component 990 has an interposer 991 provided on a package substrate 992 (printed circuit board), and a semiconductor device 994 and multiple semiconductor devices 981 provided on interposer 991.

Electronic component 990 shows an example in which semiconductor device 981 is used as a wideband memory. Furthermore, semiconductor device 994 can be used in integrated circuits such as a CPU, GPU, or FPGA (Field Programmable Gate Array).

The package substrate 992 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 991 can be, for example, a silicon interposer or a resin interposer.

The interposer 991 has multiple wiring lines and functions to connect multiple integrated circuits with different terminal pitches. The multiple wiring lines are provided in a single layer or multiple layers. The interposer 991 also functions to connect the integrated circuits provided on the interposer 991 to electrodes provided on the package substrate 992. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 991, and these through electrodes are used to connect the integrated circuits to the package substrate 992. In addition, with silicon interposers, TSVs can also be used as through electrodes.

In an HBM, many wiring connections are required to achieve a wide memory bandwidth. For this reason, the interposer on which the HBM is mounted must be able to form fine, high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

Furthermore, in SiPs and MCMs that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is less likely. Furthermore, because the surface of a silicon interposer is highly flat, poor connections between the integrated circuit mounted on the silicon interposer and the silicon interposer are less likely to occur. It is particularly preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging), in which multiple integrated circuits are arranged horizontally on an interposer.

On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, TSV, or the like, space is required to accommodate the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 990, the width of the terminal pitch becomes an issue, and it may become difficult to provide the large number of wirings required to achieve a wide memory bandwidth. Therefore, as mentioned above, a monolithic stacked configuration using OS transistors is preferable. A composite structure may also be used that combines a memory cell array stacked using TSVs with a monolithic stacked memory cell array.

A heat sink (heat sink) may also be provided overlapping the electronic component 990. When a heat sink is provided, it is preferable to align the height of the integrated circuit provided on the interposer 991. For example, in the electronic component 990 shown in this embodiment, it is preferable to align the height of the semiconductor device 981 and the semiconductor device 994.

Electrodes 993 may be provided on the bottom of the package substrate 992 in order to mount the electronic component 990 on another substrate. Figure 23B shows an example in which the electrodes 993 are formed from solder balls. By providing solder balls in a matrix on the bottom of the package substrate 992, BGA (Ball Grid Array) mounting can be achieved. The electrodes 993 may also be formed from conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 992, PGA (Pin Grid Array) mounting can be achieved.

Electronic component 990 can be mounted on other substrates using a variety of mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[Large computer]
Next, Fig. 24A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 shown in Fig. 24A has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

Computer 5620 can have the configuration shown in the perspective view in Figure 24B, for example. In Figure 24B, computer 5620 has a motherboard 5630, which has multiple slots 5631 and multiple connection terminals. PC card 5621 is inserted into slot 5631. In addition, PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to motherboard 5630.

PC card 5621 shown in Figure 24C is an example of a processing board equipped with a CPU, GPU, memory device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that Figure 24C illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for these semiconductor devices, please refer to the descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 described below.

The connection terminal 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of standards for the connection terminal 5629 include PCI Express (Tokiriki trademark).

Connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to PC card 5621, inputting signals, etc. They can also be, for example, interfaces for outputting signals calculated by PC card 5621. Examples of standards for connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Also, when outputting video signals from connection terminals 5623, 5624, and 5625, examples of standards for each include HDMI (registered trademark).

The semiconductor device 5626 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 5626 can be connected to the board 5622 by inserting these terminals into sockets (not shown) provided on the board 5622.

The semiconductor device 5627 has multiple terminals, and the semiconductor device 5627 can be connected to the board 5622 by soldering the terminals to wiring on the board 5622, for example, using a reflow soldering method. Examples of the semiconductor device 5627 include FPGAs, GPUs, and CPUs. For example, the electronic component 990 can be used as the semiconductor device 5627.

The semiconductor device 5628 has multiple terminals, and the semiconductor device 5628 can be connected to the board 5622 by soldering the terminals to wiring on the board 5622, for example, using a reflow soldering method. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 990 can be used as the semiconductor device 5628.

The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, artificial intelligence learning and inference.

[Space equipment]
The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

A semiconductor device according to one embodiment of the present invention includes an OS transistor. Compared to Si transistors, OS transistors exhibit smaller variations in electrical characteristics due to radiation exposure. In other words, OS transistors have high radiation resistance and are therefore highly reliable and suitable for use in environments where radiation may be incident. For example, OS transistors are suitable for use in outer space. Specifically, OS transistors can be used as transistors for semiconductor devices installed in space shuttles, artificial satellites, or space probes. Examples of radiation include X-rays and neutron rays. Note that outer space refers to an altitude of 100 km or higher, and the outer space described in this specification can include one or more of the thermosphere, mesosphere, and stratosphere.

Figure 24D shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Figure 24D also shows a planet 6804 in space.

Although not shown in FIG. 24D, the secondary battery 6805 may be provided with a battery management system (also referred to as a BMS) or a battery control circuit. The use of OS transistors in the battery management system or battery control circuit described above is preferable because they consume less power and have high reliability even in space.

In addition, outer space is an environment with radiation levels more than 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

When sunlight is irradiated onto the solar panel 6802, the power required for the satellite 6800 to operate is generated. However, for example, in situations where sunlight is not irradiated onto the solar panel, or where the amount of sunlight irradiating the solar panel is low, the amount of power generated will be small. Therefore, there is a possibility that the power required for the satellite 6800 to operate will not be generated. In order to operate the satellite 6800 even in situations where the amount of power generated is low, it is recommended that a secondary battery 6805 be provided on the satellite 6800. Note that the solar panel is sometimes called a solar cell module.

Satellite 6800 can generate a signal. This signal is transmitted via antenna 6803, and can be received, for example, by a receiver located on the ground or by another satellite. By receiving the signal transmitted by satellite 6800, the position of the receiver that received the signal can be determined. As described above, satellite 6800 can constitute a satellite positioning system.

The control device 6807 also has a function of controlling the satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the control device 6807 is preferably a semiconductor device including an OS transistor, which is one embodiment of the present invention.

Furthermore, the artificial satellite 6800 can be configured to include a sensor. For example, by configuring it to include a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected off an object on the ground. Or, by configuring it to include a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an Earth observation satellite.

Note that although an artificial satellite is used as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, a semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

As explained above, OS transistors have the advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance compared to Si transistors.

[Data Center]
The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. To manage long-term data, the building must be large enough to accommodate the installation of storage devices and servers for storing a huge amount of data, a stable power source for storing the data, or cooling equipment required for storing the data.

By using a semiconductor device according to one embodiment of the present invention in a storage system applied to a data center, the power required to store data can be reduced and the semiconductor device that stores data can be made smaller. This allows for the storage system to be made smaller, the power supply for storing data to be made smaller, and cooling equipment to be made smaller. This allows for space savings in the data center.

Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, and therefore heat generation from the circuit can be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

Figure 24E shows a storage system applicable to a data center. The storage system 7010 shown in Figure 24E has multiple servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has multiple storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

Storage 7003 uses flash memory to reduce data access speed, i.e., the time required to store and output data, but this time is significantly longer than the time required for DRAM (Dynamic Random Access Memory), which can be used as cache memory within the storage. In order to solve the problem of the slow access speed of storage 7003, storage systems typically provide cache memory within the storage to reduce the time required to store and output data.

The aforementioned cache memory is used within the storage control circuit 7002 and storage 7003. Data exchanged between the host 7001 and storage 7003 is stored in the cache memory within the storage control circuit 7002 and storage 7003, and then output to the host 7001 or storage 7003.

By using OS transistors as transistors for storing data in the cache memory and maintaining a potential corresponding to the data, the frequency of refreshes can be reduced, lowering power consumption. Furthermore, by stacking the memory cell array, miniaturization is possible.

<Additional notes regarding the present specification etc.>
The above-described embodiments and the respective components in the embodiments will be described below with additional notes.

The configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments to form one aspect of the present invention. Furthermore, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

Furthermore, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and/or the content (or even a part of the content) described in one or more other embodiments.

Note that the content described in the embodiments refers to the content described in each embodiment using various figures or the content described using text in the specification.

Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and/or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

In addition, in this specification and elsewhere, block diagrams classify components by function and show them as independent blocks. However, in actual circuits and elsewhere, it is difficult to separate components by function, and there may be cases where a single circuit is involved in multiple functions, or where a single function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification and may be rephrased appropriately.

Furthermore, in the drawings, sizes, layer thicknesses, and regions are shown at arbitrary sizes for the convenience of explanation. Therefore, they are not necessarily limited to that scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences, etc. may be included.

In this specification and elsewhere, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the transistor's structure or operating conditions, etc. The source and drain of a transistor can also be appropriately referred to as source (drain) terminal, source (drain) electrode, etc.

Furthermore, the terms "electrode" and "wiring" used in this specification do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are formed as a single unit.

Furthermore, in this specification, voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential; for example, if the reference potential is a ground voltage (earth voltage), then voltage can be interchanged with potential. Ground potential does not necessarily mean 0V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

In this specification, terms such as "film" and "layer" can be interchanged. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

In this specification, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has the function of controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching the path through which a current flows.

In this specification, the channel length of a planar transistor refers to, for example, the distance between the source and drain in the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is on) and the gate overlap in a plan view of the transistor, or the region where the channel is formed.

In this specification, the term "channel width" refers to, for example, the length of the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

Furthermore, in this specification, etc., a node can be referred to as a terminal, wiring, electrode, conductive layer, conductor, impurity region, etc. depending on the circuit configuration, device structure, etc. Furthermore, a terminal, wiring, etc. can be referred to as a node.

In this specification, the "on state" of a transistor refers to, for example, a state in which the source and drain of the transistor can be considered to be short-circuited. For example, the "on state" refers to a state in which the voltage between the gate and source of an n-channel transistor is higher than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is lower than the threshold voltage. Note that the "on state" of a transistor refers to a state in which current can flow between the source and drain. Therefore, the "on state" of a transistor may also be referred to as the "conducting state" of the transistor.

In this specification, the "off state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be cut off. For example, the "off state" refers to a state in which the voltage between the gate and source of an n-channel transistor is lower than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is higher than the threshold voltage. The "off state" of a transistor may also be referred to as the "non-conducting state" of the transistor.

In this specification, the voltage between the gate and source (gate-source) is sometimes referred to as the "gate voltage," the voltage between the drain and source (drain-source) is sometimes referred to as the "drain voltage," and the voltage between the backgate and source (backgate-source) is sometimes referred to as the "backgate voltage." Additionally, the current flowing from the drain to the source is sometimes referred to as the "drain current."

In this specification, unless otherwise specified, the "off-state current" of a transistor refers to the drain current when the transistor is in an off state. Note that in this specification, the off-state current and the current flowing from the gate to the source and drain (also referred to as gate leakage current) may also be referred to as leakage current.

In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; note that wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A and B represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an electrical potential interaction occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Furthermore, even if there is a time during the operation of the circuit when no electrical signal exchange or electrical potential interaction occurs between A and B, if there is a time during the operation of the circuit when an electrical signal exchange or electrical potential interaction occurs between A and B, then it can still be defined that "A and B are indirectly connected."

An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, this would be the case when a capacitive element is connected between A and B, or when a transistor gate insulating film or the like is present between A and B. Therefore, it cannot be said that "the transistor gate (A) and the transistor source or drain (B) are indirectly connected."

Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another from a power supply, GND, etc.

100: NOT circuit, 101: transistor, 102: transistor, 106: transistor

Claims (8)

a logic circuit having a p-channel transistor, a first n-channel transistor, and a second n-channel transistor;
a first signal line for supplying a signal for controlling the logic circuit;
a first power supply line for supplying a high power supply potential and a second power supply line for supplying a low power supply potential;
the p-channel transistor and the first n-channel transistor each have a first semiconductor layer including silicon;
the second n-channel transistor has a second semiconductor layer containing indium oxide;
one of a source and a drain of the second n-channel transistor is electrically connected to one of a source and a drain of the first n-channel transistor;
one of the source and the drain of the p-channel transistor is electrically connected to the first power supply line;
the other of the source and the drain of the second n-channel transistor is electrically connected to the second power supply line;
the first signal line electrically connected to the gate of the second n-channel transistor has a function of supplying a signal for turning off the second n-channel transistor during a period in which the logic circuit is inactive;
the first power supply line is provided in a layer below the layer in which the logic circuit is provided;
the second power supply line is provided in a layer above the layer in which the logic circuit is provided;
Semiconductor device. a logic circuit having a p-channel transistor, a first n-channel transistor, and a second n-channel transistor;
a first signal line for supplying a control signal to the logic circuit;
a first power supply line for supplying a high power supply potential and a second power supply line for supplying a low power supply potential;
the p-channel transistor and the first n-channel transistor each have a first semiconductor layer including silicon;
the second n-channel transistor has a second semiconductor layer containing indium oxide;
one of a source and a drain of the second n-channel transistor is electrically connected to one of a source and a drain of the first n-channel transistor;
one of the source and the drain of the p-channel transistor is electrically connected to the first power supply line;
the other of the source and the drain of the second n-channel transistor is electrically connected to the second power supply line;
the first signal line electrically connected to the gate of the second n-channel transistor has a function of supplying a signal for turning off the second n-channel transistor during a period in which the logic circuit is inactive;
the first power supply line is provided in a layer below a layer in which the p-channel transistor is provided;
the second power supply line is provided in a layer above a layer in which the second n-channel transistor is provided;
Semiconductor device. In claim 1 or claim 2,
the first semiconductor layer has a structure surrounded by the gate of the p-channel transistor and the gate of the first n-channel transistor;
Semiconductor device. In claim 1 or claim 2,
a third power supply line that supplies a high power supply potential and a fourth power supply line that supplies a low power supply potential;
the third power supply line is provided in a layer below a layer in which the p-channel transistor is provided,
the fourth power supply line is provided in a layer above a layer in which the second n-channel transistor is provided;
Semiconductor device. In claim 1 or claim 2,
a third n-channel transistor;
a second signal line electrically connected to a gate of the first n-channel transistor and a gate of the p-channel transistor is electrically connected to one of a source and a drain of the third n-channel transistor;
a third n-channel transistor being turned off to hold the potential of the second signal line;
Semiconductor device. a logic circuit having a p-channel transistor, a first n-channel transistor, and a second n-channel transistor;
a first signal line for supplying a control signal to the logic circuit;
a first power supply line for supplying a high power supply potential and a second power supply line for supplying a low power supply potential;
the p-channel transistor and the first n-channel transistor each have a first semiconductor layer including silicon;
the second n-channel transistor has a second semiconductor layer containing indium oxide;
one of a source and a drain of the second n-channel transistor is electrically connected to one of a source and a drain of the first n-channel transistor;
one of the source and the drain of the p-channel transistor is electrically connected to the first power supply line;
the other of the source and the drain of the second n-channel transistor is electrically connected to the second power supply line;
the first signal line electrically connected to the gate of the second n-channel transistor has a function of supplying a signal for turning off the second n-channel transistor during a period in which the logic circuit is inactive;
the first power supply line and the second power supply line are provided in a layer below a layer in which the p-channel transistor is provided;
the first signal lines are provided in a layer above a layer in which the second n-channel transistors are provided;
Semiconductor device. In claim 6,
the first semiconductor layer has a structure surrounded by the gate of the p-channel transistor and the gate of the first n-channel transistor;
Semiconductor device. In claim 6,
a third n-channel transistor;
a second signal line electrically connected to the gate of the first n-channel transistor and the gate of the p-channel transistor is electrically connected to one of the source and the drain of the third n-channel transistor;
a third n-channel transistor being turned off to hold the potential of the second signal line;
Semiconductor device.