WO2025138620A1 - Computing device - Google Patents

Abstract

A computing device, comprising a mainboard, a first memory expansion board, a first memory module, a second memory expansion board, and a second memory module. A first CPU is provided on the mainboard, and the first CPU comprises a first interface and a second interface, wherein the first interface and the second interface are memory interfaces, and belong to a same interface group of the first CPU. A first memory expansion controller is provided on the first memory expansion board, and a second memory expansion controller is provided on the second memory expansion board. The first interface is electrically connected to the first memory module via the first memory expansion controller, and the second interface is electrically connected to the second memory module via the second memory expansion controller. In this way, since the first interface and the second interface of the first CPU belong to the same interface group, when the first CPU accesses the first memory module and the second memory module, cross-group access is not needed, so that an access path can be shortened, and data transmission speed can be increased.

Description

A computing device

This application claims priority to the Chinese patent application filed with the China Patent Office on December 28, 2023, with application number 202311841697.0 and application name “A Computing Device”, the entire contents of which are incorporated by reference into this application.

Technical Field

The present application relates to the field of communication technology, and in particular to a computing device.

Background Art

A computing device (such as a server) may include a motherboard, and one or more central processing units (CPUs) may be provided on the motherboard. Each CPU may be electrically connected to a memory module via a memory expansion controller, so that the CPU may exchange data with the memory module. For example, the CPU may write data to the memory module, or read data from the memory module.

As the amount of data storage increases, the speed at which the CPU and memory modules exchange data is critical. However, there is a technical problem that the CPU on the current motherboard has a slow data transmission speed when transmitting data to the memory module.

Therefore, how to increase the data transmission speed between the CPU and the memory module has become a technical problem that needs to be solved urgently.

Summary of the invention

An embodiment of the present application provides a computing device that can increase the data transmission speed between a CPU and a memory module.

In the first aspect, the present application provides a computing device, the computing device includes a mainboard, a first memory expansion board, a first memory module, a second memory expansion board and a second memory module; the mainboard is provided with a first CPU, the first CPU includes a first interface and a second interface, the first interface and the second interface are memory interfaces, belonging to the same interface group of the first CPU; the first memory expansion board is provided with a first memory expansion controller, the second memory expansion board is provided with a second memory expansion controller; the first memory expansion controller is electrically connected to the first interface and the first memory module respectively, and the second memory expansion controller is electrically connected to the second interface and the second memory module respectively. In this way, since the first interface and the second interface of the first CPU belong to the same interface group, when the first CPU accesses the first memory module and the second memory module, there is no need to cross-group access, the access path can be shortened, and thus the data transmission speed can be increased.

In a possible implementation, the computing device further includes a third memory module and a fourth memory module; a third memory expansion controller is further provided on the first memory expansion board, and a fourth memory expansion controller is further provided on the second memory expansion board; the first interface is electrically connected to the third memory module via the third memory expansion controller, and the second interface is electrically connected to the fourth memory module via the fourth memory expansion controller. In this way, since the first interface and the second interface of the first CPU belong to the same interface group, when the first CPU accesses the first memory module, the second memory module, the third memory module, and the fourth memory module, there is no need to cross-group access, which can shorten the access path, thereby increasing the data transmission speed.

In a possible implementation, the computing device further includes a third memory expansion board, a fourth memory expansion board, a fifth memory module, and a sixth memory module; a second CPU is also provided on the mainboard, the second CPU includes a third interface and a fourth interface, the third interface and the fourth interface are memory interfaces, and belong to the same interface group of the second CPU; the second CPU is electrically connected to the first CPU via an xGMI bus; the fifth memory expansion controller is electrically connected to the third interface and the fifth memory module, respectively, and the sixth memory expansion controller is electrically connected to the fourth interface and the sixth memory module, respectively. In this way, since the third interface and the fourth interface of the second CPU belong to the same interface group, when the first CPU or the second CPU accesses the fifth memory module and the sixth memory module, there is no need to cross-group access, and the access path can be shortened, thereby improving the data transmission speed. In addition, when the second CPU accesses the memory module connected to the first interface and the second interface of the first CPU, the data transmission speed can also be improved.

In a possible implementation, the computing device also includes a seventh memory module and an eighth memory module; a seventh memory expansion controller is also provided on the third memory expansion board, and an eighth memory expansion controller is also provided on the fourth memory expansion board; the seventh memory expansion controller is electrically connected to the third interface and the seventh memory module, respectively, and the eighth memory expansion controller is electrically connected to the fourth interface and the eighth memory module, respectively. Therefore, when the first CPU or the second CPU accesses the fifth memory module, the sixth memory module, the seventh memory module and the eighth memory module, there is no need for cross-group access, the access path can be shortened, and the data transmission speed can be increased.

In a possible implementation, the first interface and the second interface are fast computing link CXL interfaces. Thus, the memory interface is specifically a fast computing link CXL interface.

In a possible implementation, the first CPU accesses the first memory module and the second memory module in a memory interleaving manner. Thus, the first CPU accesses the first memory module and the second memory module in a memory interleaving manner to provide the first memory module and the second memory module with a memory interleaving manner. Write (or read) data from the memory module.

In a possible implementation, a first power module is provided on the mainboard; an output end of the first power module is electrically connected to the first memory expansion board and the second memory expansion board. In this way, the first power module on the mainboard can supply power to the first memory expansion board and also to the second memory expansion board.

In a possible implementation, the first memory module includes at least one dual inline memory module DIMM, and the second memory module includes at least one dual inline memory module DIMM; the first memory module is plugged into the first memory expansion board, and the second memory module is plugged into the second memory expansion board. In this way, the specific form of the first memory module can be at least one dual inline memory module DIMM.

In a possible implementation, it is characterized in that the first memory expansion board is provided with a first connector, the main board is provided with a second connector, and the second memory expansion board is provided with a third connector; the first memory expansion board is electrically connected to the first interface through the first connector and the second connector, and the second memory expansion board is electrically connected to the second interface through the third connector and the second connector. In this way, the first interface is electrically connected to the memory expansion board through the first connector and the second connector, so that the first CPU can exchange data with the DIMM of the memory expansion board through the first interface.

In a possible implementation, the first memory module is a DDR4 memory or a DDR5 memory, and the second memory module is a DDR4 memory or a DDR5 memory. In this way, the first memory module can use either a DDR4 memory or a DDR5 memory. The same is true for the second memory module.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application;

FIG2 is a schematic diagram of the structure of a CPU in an embodiment of the present application;

FIG3 is a schematic diagram of the structure of a memory expansion board provided in an embodiment of the present application;

FIG4 is a schematic diagram of the structure of another computing device provided in an embodiment of the present application;

FIG5 is a schematic diagram of the structure of another computing device provided in an embodiment of the present application;

FIG6 is a schematic diagram of the structure of another computing device provided in an embodiment of the present application;

FIG7 is a schematic diagram of the structure of another computing device provided in an embodiment of the present application;

FIG8 is a schematic diagram of the structure of another computing device provided in an embodiment of the present application.

DETAILED DESCRIPTION

The term "and/or" in this article is a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and/or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The symbol "/" in this article indicates that the associated objects are in an or relationship, for example, A/B means A or B.

The terms "first" and "second" in the specification and claims herein are used to distinguish different objects rather than to describe a specific order of the objects. For example, a first response message and a second response message are used to distinguish different response messages rather than to describe a specific order of the response messages.

In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more than two. For example, multiple processing units refer to two or more processing units, etc.; multiple elements refer to two or more elements, etc.

The compute express link (CXL) protocol is a high-speed serial protocol that allows fast and reliable data transmission between different components within a computer system. It is designed to address bottlenecks in high-performance computing, including memory capacity, memory bandwidth, and input-output latency. The CXL protocol can also enable memory expansion and memory sharing, and can communicate with external devices such as computing accelerators (such as graphics processors GPUs and field-programmable gate array chips FPGAs), providing faster and more flexible data transmission methods.

The CXL protocol is developed based on the PCIE5.0 protocol. The CXL protocol is based on the physical layer of the fifth-generation peripheral component interconnect express 5 (PCIE5.0) and is a new protocol optimized for cache and memory. The CXL protocol has the same electrical characteristics as the PCIE5.0 protocol. The CXL function requires the use of a flexible interface (e.g., CXL interface), which can decide whether to use the PCIE protocol or the CXL protocol based on link layer negotiation.

The computing device may include a mainboard, on which a CPU is disposed, and the CPU may include a plurality of memory interfaces. The computing device may also include a memory expansion board, on which a memory expansion controller (MXC) is disposed.

In the related art, a memory expansion controller can be connected to a memory interface (such as a CXL interface) of a CPU, and at the same time, the memory expansion controller can also be connected to a memory module. In this way, the CPU can exchange data with the memory module through the memory expansion controller. Specifically, the CPU can read data from the memory module through the memory expansion controller, and can also write data to the memory module through the memory expansion controller. However, when the CPU and the memory module exchange data, a technical problem of low data transmission rate between the CPU and the memory module often occurs.

To facilitate understanding of the technical solutions in the embodiments of the present application, the terms involved in the embodiments of the present application are explained below.

Double Data Rate Synchronous Dynamic Random Access Memory DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM) is an SDRAM with double data transfer rate. Its data transfer speed is twice the system main frequency. Due to the increased speed, its transmission performance is better than traditional SDRAM (Synchronous Dynamic Random Access Memory, SDRAM). DDR SDRAM can transmit data at both the rising and falling edges of the system clock. To simplify the description, DDR SDRAM is referred to as DDR below. DDR memory is commonly used in computers, servers, routers and other devices. It is a high-performance, low-power memory technology that can improve system performance and bandwidth to meet the storage needs of different devices.

At present, DDR has developed to the fifth generation DDR5. Compared with DDR4, DDR5 has stronger standardization and lower power consumption, and all DDR5 chips have ECC (Error Checking and Correcting, ECC) function, which can detect and correct errors before data is sent to the CPU. The memory chip in the memory module of the embodiment of the present application takes DDR5 as an example, but is not limited to DDR5, and can also be other memory chips.

Different generations of DDR memory have different interfaces. The first generation of DDR includes DDR interface, the second generation of DDR2 includes DDR2 interface, the third generation of DDR3 includes DDR3 interface, the fourth generation of DDR4 includes DDR4 interface and the fifth generation of DDR5 includes DDR5 interface. The interface is used to transmit high-speed signals. Each interface has different specifications and performance. The main features of DDR interface are high-speed transmission and low power consumption. It can transmit more data at the same frequency, thereby improving system performance.

The main advantages of DDR memory interface include the following:

1. High-speed transmission: DDR memory can transmit data twice in each clock cycle, so it is faster than SDR memory.

2. Low power consumption: DDR memory uses low voltage and therefore consumes less power.

3. Higher bandwidth: DDR memory can transmit more data at the same frequency, thereby increasing the bandwidth of the system.

4. Larger capacity: DDR memory can support larger capacity to meet higher storage requirements.

Memory interleaving refers to the technology of interleaving access on different memories to improve memory access performance. The memory controller in the CPU distributes data between different memory modules in an alternating pattern, allowing the memory controller to access each memory module to obtain smaller bits of data, rather than accessing a single memory module to obtain the entire data block, providing the memory controller with more bandwidth for accessing the same amount of data across channels (memory channels), rather than traversing a single channel to store all data in a single memory module.

Next, the computing device provided in the embodiment of the present application is introduced in detail.

Exemplarily, an embodiment of the present application provides a computing device 1, as shown in Figure 1. The computing device 1 is a device, equipment or platform with data processing capabilities. In one example, the computing device 1 can be a server.

The computing device 1 may include a motherboard 11, on which a CPU 111 is disposed. The CPU 111 includes a plurality of memory interfaces. The memory interface may specifically be a PCIE interface or a CXL interface, that is, an interface for communicating with a memory module through a PCIE protocol or a CXL protocol. For example, the four CXL interfaces are interface P0, interface P1, interface P2, and interface P3. Among them, interface P0 and interface P1 belong to the same interface group, interface P2 and interface P3 belong to the same interface group, and the same interface group is the same corner.

The corner here refers to the corner of the chip. As shown in FIG. 2 , the interface P0 and the interface P1 of the embodiment of the present application belong to corner1, and the interface P2 and the interface P3 belong to corner2.

The computing device 1 also includes a memory expansion board A and a memory expansion board B. The memory expansion board A is provided with a memory expansion controller MXC0, and the memory expansion board B is provided with a memory expansion controller MXC1.

The interface of the memory expansion controller MXC0 supports connecting to DDR5 or DDR4, and can communicate with DDR4 or DDR5 using CXL or PCIE protocol, and MXC0 and CPU111 can also communicate through the CXL protocol or PCIE protocol. Exemplarily, when the CXL protocol is adopted, the interfaces that connect MXCO to CPU111 and memory module a respectively can be referred to as the first CXL interface and the second CXL interface; the embodiment of the present application takes the communication between the memory expansion controller MXCO and the CPU and memory module a using the CXL protocol as an example, and the protocol of the memory expansion controller MXC1 is the same as that of MXCO, which will not be repeated here. The first CXL interface of the memory expansion controller MXC0 can be connected to the interface P0 of the CPU, and the second CXL interface of the memory expansion controller MXC0 can be electrically connected to the memory module a. Among them, the memory module a is a DDR5 memory. memory module or DDR4 memory module.

In this way, CPU111 can exchange data with memory module a through memory expansion controller MXC0. Specifically, CPU111 can read data from memory module a through interface P0 and memory expansion controller MXC0, and can also write data to memory module a through interface P0 and memory expansion controller MXC0.

Similarly, the first CXL interface of the memory expansion controller MXC1 can be connected to the interface P1 of the CPU, and the second CXL interface of the memory expansion controller MXC1 can be electrically connected to the memory module b. In this way, the CPU 111 can read data from the memory module b through the interface P1 and the memory expansion controller MXC1, and can also write data to the memory module b through the interface P1 and the memory expansion controller MXC1.

When the memory interleaving technology is used, continuous memory addresses can be mapped to different CXL devices at uniform intervals, specifically memory module a and memory module b. If memory module a is connected to interface P0 of CPU 111, and memory module b is connected to interface P2 of CPU 111, since interface P0 and interface P2 do not belong to the same interface group, when CPU 111 accesses memory module a and memory module b, there is a technical problem that the access path is too long and the data transmission speed is slow.

In contrast, the interface P0 and interface P1 of the CPU 111 in the embodiment of the present application belong to the same interface group (same group) of the CPU 111 interface, which is defined in the product manual of the CPU of Advanced Micro Devices (AMD). Interfaces P0 and P1 belong to the same interface group, and interfaces P2 and P3 belong to another interface group. The functions of the P0-P3 interfaces are the same, and they are all used to connect to a memory stick or a memory expansion board to read or write data from the memory stick, wherein the memory stick can be DDR4, DDR5, and the memory expansion board can be a CXL expansion board. Therefore, when CPU 111 accesses memory module a and memory module b, there is no need to cross-group access, which can shorten the access path and thus increase the data transmission speed.

It should be noted that the memory bars on the CXL expansion boards respectively connected to the same interface group of the CPU may or may not apply the memory interleaving technology, which is not specifically limited here.

In addition, when CPU 111 accesses memory module a, it is actually the core of CPU 111 that accesses memory module a through the CXL controller corresponding to interface P0. Similarly, when CPU 111 accesses memory module b, it is actually the core of CPU 111 that accesses memory module b through the CXL controller corresponding to interface P1.

It should be noted that memory interleaving is a technology used by AMD CPU to increase the memory bandwidth available to applications. Without memory interleaving, continuous memory blocks are read from the same physical memory, such as the memory stick of the same memory channel. The CPU obtains the entire data block by accessing continuous memory blocks on a memory stick. When memory interleaving is used, continuous memory blocks can be located on memory sticks of different memory channels. The CPU can concurrently access continuous memory blocks on memory sticks of different channels to obtain the entire data block, which is beneficial to improving the memory bandwidth available to applications and reducing memory latency.

Exemplarily, the memory module a may be a DIMM (dual-inline-memory-modules), the number of which is determined by the number of the second CXL interfaces of the memory expansion controller and the size of the memory expansion board, and each second CXL interface may be connected to one or two DIMMs. The structure of the memory module b is the same as that of the memory module a, and will not be described in detail here.

The structure of DIMM is described in detail below.

Inside the DIMM, the memory data is written into a large storage unit matrix in bits. As long as a row and a column are specified, a storage unit can be accurately located. This is the basic principle of memory chip addressing. We call such an array a logical bank of memory.

Due to technological reasons, this storage unit array cannot be made too large, so the memory capacity is generally divided into several arrays in DIMMs, that is, there are multiple logical banks in the DIMM. As the chip capacity continues to increase, the number of logical banks is also increasing. The address lines of the logical banks are universal, and different banks can be distinguished by the logical bank numbers. For example, a DIMM includes 4 logical banks, and the banks are numbered from Bank0 to Bank3, and each bank includes 8M storage units. Then the storage capacity of a logical bank is 64Mbit (8M×8bit), and the total storage capacity of 4 logical banks is 256Mbit (32MB).

In addition, the interface P0 and the interface P1 in the embodiment of the present application are only exemplary. The memory expansion board A in the embodiment of the present application can be connected to the interface P2, and the memory expansion board B can be connected to the interface P3. The implementation method is the same as the previous description and will not be described in detail here.

The specific structure of the memory expansion board A is exemplarily introduced below. As shown in FIG3 , the memory expansion board A may be provided with a UBC connector 0, a memory expansion controller MXC0, a DIMM slot 1, and a DIMM slot 2. Each pin of the UBC connector 0 may be electrically connected to MXC0 through a metal trace. MXC0 may be electrically connected to the pins of the DIMM slot 1 and the pins of the DIMM slot 2 through a metal trace. The memory module a may include two DIMMs. The P0 interface of the CPU 111 may be connected to another UBC connector on the motherboard. When the user connects the UBC connector to the UBC connector 0 through a cable and inserts two DIMMs into the DIMM slot 1 and the DIMM slot 2, the CPU 111 may exchange data with the two DIMMs through the interface P0.

It should be noted that the above examples are only for illustrative purposes. The UBC connector 0 can also be replaced with other types of connectors, such as the DIMM connector. The number of slots may also be 1.

In addition, the structure of the memory expansion board B is the same as that of the memory expansion board A, and will not be described in detail here.

In the second embodiment of the present application, based on the first embodiment of the present application, a memory expansion controller MXC2 may be further provided on the memory expansion board A, and a memory expansion controller MXC3 may be further provided on the memory expansion board B, as shown in FIG4 .

The interface of the memory expansion controller MXC2 supports connecting to DDR5 or DDR4, and can communicate with DDR4 or DDR5 using CXL or PCIE protocol, and MXC0 and CPU111 can also communicate through CXL protocol or PCIE protocol, and the interface connecting MXC2 to CPU111 and memory module a respectively is called the first CXL interface and the second CXL interface of MXC2; the embodiment of the present application takes the communication between the memory expansion controller MXC2 and the CPU and memory module a using CXL protocol as an example, and the protocol of the memory expansion controller MXC3 is the same as MXC2, which will not be repeated here. The first CXL interface of the memory expansion controller MXC2 can be connected to the interface P0 of the CPU, and the second CXL interface of the memory expansion controller MXC2 can be electrically connected to the memory module c. Among them, the memory module c is a DDR5 memory module or a DDR4 memory module. In this way, the CPU111 can exchange data with the memory module c through the interface P0 and the memory expansion controller MXC2.

Similarly, the first CXL interface of the memory expansion controller MXC3 can be connected to the interface P1 of the CPU, and the second CXL interface of the memory expansion controller MXC3 can be electrically connected to the memory module d. In this way, the CPU 111 can exchange data with the memory module d through the interface P1 and the memory expansion controller MXC3.

Among them, the structures of memory module c and memory module d are the same as the aforementioned memory module a. The structure of the memory expansion board of the present application can also refer to the structure of the memory expansion board in the first embodiment, which will not be described in detail here.

Since interface P0 and interface P1 of CPU111 in the embodiment of the present application belong to the same interface group, CPU111 does not need to access across groups when accessing memory module a, memory module b, memory module c and memory module d, which can shorten the access path and thus increase the data transmission speed.

In the third embodiment of the present application, based on the first embodiment of the present application, the computing device 1 may further include a memory expansion board C and a memory expansion board D, the memory expansion board C is provided with a memory expansion controller MXC4, and the memory expansion board D is provided with a memory expansion controller MXC5, as shown in FIG5 .

The interface of the memory expansion controller MXC4 supports connecting to DDR5 or DDR4, and can communicate with DDR4 or DDR5 using the CXL or PCIE protocol. MXC4 and CPU111 can also communicate through the CXL protocol or the PCIE protocol, and the interfaces connecting MXC4 to the CPU112 and the memory module a respectively are called the first CXL interface and the second CXL interface of MXC4; the embodiment of the present application takes the communication between the memory expansion controller MXC4 and the CPU and the memory module a using the CXL protocol as an example. The protocol of the memory expansion controller MXC5 is the same as that of MXC4, which will not be repeated here.

The mainboard 1 is also provided with a CPU 112, and the CPU 112 is connected to the CPU 111 by a socket/inter-chip global memory interconnect (xGMI) bus so that the two can exchange data.

It should be noted that the xGMI bus is a new high-speed interconnect bus for communication between sockets launched by the AMD platform (core architecture Zen platform). It consists of 4 groups of x16 links, each of which contains 16 channels (lane), and each channel contains 2 pairs of bidirectional high-speed differential pairs. Among them, the two ends of data exchange are realized through a bidirectional communication connection, and one end of the communication connection is called a socket.

The structure of CPU 112 may be the same as that of CPU 111. CPU 112 may be provided with multiple CXL interfaces, for example, 4 CXL interfaces, namely interface P0, interface P1, interface P2 and interface P3, wherein interface P0 and interface P1 belong to the same interface group, and interface P2 and interface P3 belong to the same interface group.

The first CXL interface of the memory expansion controller MXC4 can be connected to the interface P0 of the CPU 112, and the second CXL interface of the memory expansion controller MXC4 can be electrically connected to the memory module e. The memory module e is a DDR5 memory module or a DDR4 memory module. In this way, the CPU 112 can exchange data with the memory module e through the interface P0 and the memory expansion controller MXC4.

Similarly, the first CXL interface of the memory expansion controller MXC5 can be connected to the interface P1 of the CPU 112, and the second CXL interface of the memory expansion controller MXC5 can be electrically connected to the memory module f. In this way, the CPU 112 can exchange data with the memory module f through the interface P1 and the memory expansion controller MXC5.

Among them, the structures of memory module e and memory module f are the same as the aforementioned memory module a. The structure of the memory expansion board of the present application can also refer to the structure of the memory expansion board in the first embodiment, which will not be described in detail here.

Since interface P0 and interface P1 of CPU112 in the embodiment of the present application belong to the same interface group, CPU112 does not need to access across groups when accessing memory module e and memory module f, which can shorten the access path and thus improve the data transmission speed between CPU112 and memory module e and memory module f.

Similarly, when CPU111 accesses memory module e and memory module f, it can exchange data with CPU112 through the xGMI bus, and then CPU112 can exchange data with memory module e and memory module f. When CPU112 accesses memory module e and memory module f, it does not need to cross-group access, which can shorten the access path, thereby improving the data transmission speed between CPU111 and memory module e and memory module f.

Similarly, when CPU112 accesses memory module a and memory module b, it can exchange data with CPU111 through the xGMI bus, and then CPU111 interacts with memory module a and memory module b. When CPU111 accesses memory module a and memory module b, there is no need for cross-group access, which can shorten the access path and thus improve the data transmission speed between CPU112 and memory module a and memory module b.

In the fourth embodiment of the present application, the memory expansion board and memory module connected to the CPU 111 in the embodiment of the present application are the same as those in the second embodiment of the present application, and the memory expansion board and memory module connected to the CPU 112 in the embodiment of the present application are the same as those in the third embodiment of the present application, as shown in Figure 6.

In this way, since interface P0 and interface P1 of CPU111 in the embodiment of the present application belong to the same interface group, CPU111 does not need to access across groups when accessing memory module a, memory module b, memory module c and memory module d, and the access path can be shortened, thereby improving the data transmission speed between CPU111 and memory module a, memory module b, memory module c and memory module d.

Similarly, when CPU 112 accesses memory module e and memory module f, it does not need to access across groups, which can shorten the access path, thereby increasing the data transmission speed between CPU 112 and memory module e and memory module f.

Similarly, when CPU111 accesses memory module e and memory module f, it can exchange data with CPU112 through the xGMI bus, and then CPU112 can exchange data with memory module e and memory module f. When CPU112 accesses memory module e and memory module f, it does not need to cross-group access, which can shorten the access path, thereby improving the data transmission speed between CPU111 and memory module e and memory module f.

Similarly, when CPU112 accesses memory module a, memory module b, memory module c, and memory module d, it can exchange data with CPU111 through the xGMI bus, and then CPU111 can exchange data with memory module a, memory module b, memory module c, and memory module d. When CPU111 accesses memory module a, memory module b, memory module c, and memory module d, it does not need to cross-group access, which can shorten the access path, thereby improving the data transmission speed between CPU112 and memory module a, memory module b, memory module c, and memory module d.

In the fifth embodiment of the present application, the memory expansion board and memory module connected to the CPU 111 in the embodiment of the present application are the same as those in the second embodiment of the present application. As for the memory expansion board and memory module connected to the CPU 112, compared with the CPU 112 and the memory expansion board and memory module connected thereto in the third embodiment, the memory expansion board C in the embodiment of the present application may also be provided with a memory expansion controller MXC6, and the memory expansion board D may also be provided with a memory expansion controller MXC7, as shown in FIG. 7 .

The interface of the memory expansion controller MXC6 supports connecting to DDR5 or DDR4, and can enable it to communicate with DDR4 or DDR5 using the CXL or PCIE protocol, and MXC4 and CPU111 can also communicate through the CXL protocol or the PCIE protocol, and the interfaces that connect MXC6 to the CPU112 and the memory module a respectively are called the first CXL interface and the second CXL interface of MXC6; the embodiment of the present application takes the use of the CXL protocol between the memory expansion controller MXC6 and the CPU and the memory module a as an example, the protocol of the memory expansion controller MXC7 is the same as that of MXC6, which will not be repeated here.

The first CXL interface of the memory expansion controller MXC6 can be connected to the interface P0 of the CPU 112, and the second CXL interface of the memory expansion controller MXC6 can be electrically connected to the memory module g. Among them, the memory module g is a DDR5 memory module or a DDR4 memory module. In this way, the CPU 112 can exchange data with the memory module g through the interface P0 and the memory expansion controller MXC6.

Similarly, the first CXL interface of the memory expansion controller MXC7 can be connected to the interface P1 of the CPU 112, and the second CXL interface of the memory expansion controller MXC7 can be electrically connected to the memory module h. Among them, the memory module h is a DDR5 memory module or a DDR4 memory module. In this way, the CPU 112 can exchange data with the memory module h through the interface P1 and the memory expansion controller MXC7.

Among them, the structures of memory module g and memory module h are the same as the aforementioned memory module a. The structure of the memory expansion board of the present application can also refer to the structure of the memory expansion board in the first embodiment, which will not be described in detail here.

In this way, since interface P0 and interface P1 of CPU111 in the embodiment of the present application belong to the same interface group, CPU111 does not need to access across groups when accessing memory module a, memory module b, memory module c and memory module d, and the access path can be shortened, thereby improving the data transmission speed between CPU111 and memory module a, memory module b, memory module c and memory module d.

Similarly, when CPU 112 accesses memory module e, memory module f, memory module g, and memory module h, it does not need to cross-group access, which can shorten the access path, thereby improving the data transmission rate between CPU 112 and memory module e, memory module f, memory module g, and memory module h. Transfer speed.

Similarly, when CPU111 accesses memory module e, memory module f, memory module g, and memory module h, it can exchange data with CPU112 through the xGMI bus, and then CPU112 exchanges data with memory module e, memory module f, memory module g, and memory module h. When CPU112 accesses memory module e, memory module f, memory module g, and memory module h, it does not need to cross-group access, which can shorten the access path, thereby improving the data transmission speed between CPU111 and memory module e, memory module f, memory module g, and memory module h.

Similarly, when CPU112 accesses memory module a, memory module b, memory module c, and memory module d, it can exchange data with CPU111 through the xGMI bus, and then CPU111 can exchange data with memory module a, memory module b, memory module c, and memory module d. When CPU111 accesses memory module a, memory module b, memory module c, and memory module d, it does not need to cross-group access, which can shorten the access path, thereby improving the data transmission speed between CPU112 and memory module a, memory module b, memory module c, and memory module d.

The sixth embodiment of the present application is a specific implementation of the fifth embodiment. Specifically, as shown in FIG8 , a power module 1 is provided on the mainboard 11, and specifically, the power module 1 can be a switching power supply. Correspondingly, a power supply connector 1 is provided on the memory expansion board A, and a power supply connector 2 is provided on the memory expansion board B. When the user needs to use the memory expansion boards A and B, a cable can be used to connect the output end of the power module 1 to the power supply connector 1 and the power supply connector 2, so that the power module 1 can supply power to the memory expansion boards A and B.

Similarly, the output end of the power module 2 on the mainboard 11 can supply power to the memory expansion board C via the power connector 3, and can also supply power to the memory expansion board D via the power connector 4. In the connection mode shown in FIG8 , one memory channel connects two memory bars; for example, DIMM1 and DIMM2 are connected to MXC1 via the same memory channel, and DIMM3 and DIMM4 are connected to MXC2 via the same memory channel... The connection mode of other memory bars is the same as that of DIMM1 and DIMM2, and will not be described in detail.

The mainboard 11 includes a UBC connector A0 , and the interface P0 is electrically connected to the UBC connector A0 via metal traces on the mainboard 1 .

The memory expansion board A is provided with a UBC connector B0 and a UBC connector B1. The UBC connector B0 is electrically connected to MXC0 via a metal trace, and the UBC connector B1 is electrically connected to MXC2 via a metal trace. A memory channel of MXC0 can be connected to DIMM slot 1 and DIMM slot 2. Memory module a can include DIMM1 and DIMM2, DIMM slot 1 can be inserted with DIMM1, and DIMM slot 2 can also be inserted with DIMM2.

When the user connects UBC connector A0 to UBC connector B0 and UBC connector B1 with a cable, CPU111 can exchange data with DIMM1 and DIMM2 through interface P0 and MXC0. CPU111 can also exchange data with DIMM3 and DIMM4 through interface P0 and MXC2.

Similarly, the structure of the memory expansion board B is the same as that of the memory expansion board A. When the user connects the UBC connector A1 with the UBC connector B2 and the UBC connector B3 with a cable, the CPU 111 can exchange data with DIMM5 and DIMM6 through the interface P1 and MXC1, and the CPU 111 can also exchange data with DIMM7 and DIMM8 through the interface P1 and MXC3.

Since interface P0 and interface P1 of CPU111 in the embodiment of the present application belong to the same interface group, CPU111 does not need to cross-group access when accessing DIMM1 to DIMM8, which can shorten the access path and thus improve the data transmission speed between CPU111 and DIMM1 to DIMM8.

Similarly, the structure of memory expansion boards C and D is the same as that of memory expansion board A. When the user connects UBC connector A2 with UBC connector B4 and UBC connector B5 with a cable, CPU112 can exchange data with DIMM9 and DIMM10 through interface P0 and MXC4, and CPU112 can also exchange data with DIMM11 and DIMM12 through interface P0 and MXC6. Similarly, when the user connects UBC connector A3 with UBC connector B6 and UBC connector B7 with a cable, CPU112 can exchange data with DIMM13 and DIMM14 through interface P1 and MXC5, and CPU112 can also exchange data with DIMM15 and DIMM16 through interface P1 and MXC7.

Since interface P0 and interface P1 of CPU112 in the embodiment of the present application belong to the same interface group, CPU112 does not need to cross-group access when accessing DIMM9 to DIMM16, which can shorten the access path and thus improve the data transmission speed between CPU112 and DIMM9 to DIMM16.

Similarly, when CPU 111 accesses DIMM 9 to DIMM 16, it can exchange data with CPU 112 through the xGMI bus, and then CPU 112 can exchange data with DIMM 9 to DIMM 16. When CPU 112 accesses DIMM 9 to DIMM 16, it does not need to cross-group access, which can shorten the access path, thereby improving the data transmission speed between CPU 111 and DIMM 9 to DIMM 16.

When CPU 112 accesses DIMM 1 to DIMM 8, it can exchange data with CPU 111 through the xGMI bus, and then CPU 111 can exchange data with DIMM 1 to DIMM 8. When CPU 111 accesses DIMM 1 to DIMM 8, it does not need to cross-group access, which can shorten the access path, thereby improving the data transmission speed between CPU 112 and DIMM 1 to DIMM 8.

The inventor used the computing device provided by the sixth embodiment to test the data transmission speed between the CPU and the memory module. The technical effects produced by the embodiments of the present application are specifically described through actual test data.

In the prior art, a person skilled in the art may connect a memory module to a CXL interface that does not belong to the same interface group. In one example, interface P2 (not interface P0) in CPU 111 connects memory module a and memory module c through memory expansion board A, and the connection relationship of interface P1 of CPU 111 is shown in FIG8 . When this connection relationship is adopted, the CXL interface to which memory module a and memory module c are connected is interface P2, and the CXL interface to which memory module b and memory module d are connected is interface P1, and interface P1 and interface P2 do not belong to the same interface group.

The inventor found in actual tests that the data transmission speed between CPU111 and memory module a, memory module b, memory module c and memory module d is 60G/s, and the data transmission speed between CPU112 and memory module a, memory module b, memory module c and memory module d is also 60G/s.

In contrast, when CPU 111 adopts the connection relationship in the sixth embodiment, interface P0 and interface P1 belong to the same interface group. The inventor found in actual tests that the data transmission speed between CPU 111 and memory module a, memory module b, memory module c and memory module d is increased to 80G/s, and the data transmission speed between CPU 112 and memory module a, memory module b, memory module c and memory module d is increased to 80G/s.

Similarly, in one example, the interface P2 (rather than the interface P0) of the CPU 112 is connected to the memory module e and the memory module g through the memory expansion board C, and the connection relationship of the interface P1 of the CPU 112 is shown in FIG8 . At this time, the data transmission speed between the CPU 111 and the memory module e, the memory module f, the memory module g, and the memory module h is 60G/s, and the data transmission speed between the CPU 112 and the memory module e, the memory module f, the memory module g, and the memory module h is also 60G/s. When the CPU 112 adopts the connection relationship in the sixth embodiment, the above two data transmission speeds are both increased to 80G/s.

It is to be understood that the structure of the computing device 1 illustrated in the embodiment of the present application does not constitute a specific limitation on the computing device 1. In other embodiments of the present application, the computing device 1 may include more or fewer components than shown in the figure, or combine certain components, or split certain components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

In addition, the various numerical numbers involved in the embodiments of the present application are only used for the convenience of description and are not used to limit the scope of the embodiments of the present application.

The above is only a specific implementation of the embodiments of the present application, but the protection scope of the embodiments of the present application is not limited to this. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the embodiments of the present application, which should be covered within the protection scope of the embodiments of the present application.

Claims (10)

A computing device, characterized in that the computing device comprises a mainboard, a first memory expansion board, a first memory module, a second memory expansion board and a second memory module; a first CPU is arranged on the mainboard, the first CPU comprises a first interface and a second interface, the first interface and the second interface are memory interfaces, and belong to the same interface group of the first CPU; A first memory expansion controller is provided on the first memory expansion board, and a second memory expansion controller is provided on the second memory expansion board; The first memory expansion controller is electrically connected to the first interface and the first memory module respectively, and the second memory expansion controller is electrically connected to the second interface and the second memory module respectively. The computing device according to claim 1, characterized in that the computing device further comprises a third memory module and a fourth memory module; The first memory expansion board is also provided with a third memory expansion controller, and the second memory expansion board is also provided with a fourth memory expansion controller; The third memory expansion controller is electrically connected to the first interface and the third memory module respectively, and the fourth memory expansion controller is electrically connected to the second interface and the fourth memory module respectively. The computing device according to claim 1 or 2, characterized in that the computing device further comprises a third memory expansion board, a fourth memory expansion board, a fifth memory module and a sixth memory module; The mainboard is also provided with a second CPU, the second CPU includes a third interface and a fourth interface, the third interface and the fourth interface are memory interfaces, and belong to the same interface group of the second CPU; the second CPU is electrically connected to the first CPU via an xGMI bus; The fifth memory expansion controller is electrically connected to the third interface and the fifth memory module respectively, and the sixth memory expansion controller is electrically connected to the fourth interface and the sixth memory module respectively. The computing device according to claim 3, characterized in that the computing device further comprises a seventh memory module and an eighth memory module; The third memory expansion board is further provided with a seventh memory expansion controller, and the fourth memory expansion board is further provided with an eighth memory expansion controller; The seventh memory expansion controller is electrically connected to the third interface and the seventh memory module respectively, and the eighth memory expansion controller is electrically connected to the fourth interface and the eighth memory module respectively. The computing device according to any one of claims 1 to 4, characterized in that the first interface and the second interface are fast computing link CXL interfaces. The computing device according to any one of claims 1 to 5 is characterized in that the first CPU accesses the first memory module and the second memory module in a memory interleaving manner. The computing device according to any one of claims 1 to 6, characterized in that a first power module is provided on the mainboard; The output end of the first power module is electrically connected to the first memory expansion board and the second memory expansion board. The computing device according to claim 1 is characterized in that the first memory module includes at least one dual in-line memory module DIMM, and the second memory module includes at least one dual in-line memory module DIMM; the first memory module is inserted into the first memory expansion board, and the second memory module is inserted into the second memory expansion board. The computing device according to any one of claims 1 to 8 is characterized in that the first memory expansion board is provided with a first connector, the main board is provided with a second connector, and the second memory expansion board is provided with a third connector; the first memory expansion board is electrically connected to the first interface through the first connector and the second connector, and the second memory expansion board is electrically connected to the second interface through the third connector and the second connector. The computing device according to any one of claims 1 to 9 is characterized in that the first memory module is a DDR4 memory or a DDR5 memory, and the second memory module is a DDR4 memory or a DDR5 memory.