WO2025130918A1 - Service processing apparatus and method, and device and storage medium - Google Patents

Abstract

The embodiments of the present application relate to the technical field of electronics. Provided are a service processing apparatus and method, and a device and a storage medium, which are used for reducing the cache miss rate when a plurality of processing cores process services, improving the prediction accuracy and the IPC, and further improving the operation efficiency of the services. The service processing apparatus comprises: a global predictor, and a plurality of processing cores coupled to the global predictor, wherein the global predictor is configured to cache historical operation information of at least one of the plurality of processing cores; a first processing core among the plurality of processing cores is configured to acquire first historical operation information from among the historical operation information, and operate a first service on the basis of the first historical operation information, so as to obtain first operation information; the first processing core is any one of the plurality of processing cores; and the global predictor is further configured to cache the first operation information.

Description

A business processing device, method, equipment and storage medium

This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on December 22, 2023, with application number 202311795739.1 and application name “A business processing device, method, equipment and storage medium”, all contents of which are incorporated by reference in this application.

Technical Field

The present application relates to the field of electronic technology, and in particular to a business processing device, method, equipment and storage medium.

Background Art

At present, a central processing unit (CPU) subsystem is usually used for business processing. The CPU subsystem includes multiple processing cores, which can be used to perform benchmark performance testing, business performance testing, similar business deployment, or business suite deployment. The scale of instructions and data of the above-mentioned businesses is large, and the cache resources of the multiple processing cores in the CPU subsystem are limited, so the CPU subsystem has a low efficiency problem when running the above-mentioned businesses.

Summary of the invention

The present application provides a business processing apparatus, method, device and storage medium for improving the operating efficiency when multiple processing cores run businesses.

To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

In a first aspect, a business processing device is provided, comprising: a global predictor, and multiple processing cores coupled to the global predictor; the global predictor is used to cache historical operation information of at least one processing core among the multiple processing cores, and the at least one processing core may be part or all of the multiple processing cores; a first processing core among the multiple processing cores is used to obtain first historical operation information among the historical operation information, and operate a first business according to the first historical operation information to obtain first operation information, and the first historical operation information may be operation information related to the first business, and the first processing core is any processing core among the multiple processing cores; the global predictor is also used to cache the first operation information, that is, the global predictor can dynamically update the historical operation information according to the operation information obtained by any processing core among the multiple processing cores when operating the business.

In the above technical solution, historical operation information is cached by a global predictor, as well as operation information generated by any processing core among multiple processing cores when running a business, so as to update the cached operation information for subsequent use. Any processing core among the multiple processing cores can obtain the required operation information from the global predictor when running a business. In this way, compared with expanding a larger capacity cache for the multiple processing cores, this solution can reduce the cache miss rate when the multiple processing cores process the business, improve the prediction accuracy and IPC, and thus improve the operation efficiency of the business.

In a possible implementation of the first aspect, the historical operation information includes historical operation information of multiple services, and the historical operation information of the multiple services includes first historical operation information; the global predictor includes: multiple buffers, used to cache the historical operation information of the multiple services respectively, wherein the first buffer of the multiple buffers is used to cache the first historical operation information, for example, the historical operation information of different services can be cached in different buffers accordingly. In the above possible implementation, by caching the historical operation information of the multiple services in multiple buffers respectively, it is possible to prevent any of the multiple processing cores from obtaining historical operation information that does not belong to its own service, and to prevent the overflow of historical operation information in the global predictor from causing security information leakage, thereby improving the security of the historical operation information in the global predictor.

In a possible implementation of the first aspect, the first processing core is further used to: obtain configuration information for the first service, the configuration information is used to indicate the first buffer (for example, to indicate the size of the first buffer, and/or to indicate the address space corresponding to the first buffer), the configuration information may be sent by the software running on the multiple processing cores, or may be pre-configured in the first processing core; configure the first buffer for the first service according to the configuration information, wherein configuring the first buffer includes enabling, disabling or clearing the first buffer, for example, enabling the first buffer through the configuration information when it is needed, and disabling or clearing the first buffer through the configuration information after use. In the above possible implementation, by configuring a corresponding buffer in the global predictor for a service of any of the multiple processing cores through the configuration information, the resources in the global predictor can be configured to the key services running on the processing core, thereby avoiding resource bottlenecks and further improving the operating efficiency of the services; in addition, by enabling, disabling or clearing the buffer in the global predictor, the utilization rate of the resources in the global predictor can also be improved.

In a possible implementation of the first aspect, the size (or size) of each buffer in the multiple buffers is determined according to the business to which the historical operation information cached in the buffer belongs, for example, the size of the first buffer is determined according to the first business. In the above possible implementation, determining the size of the buffer used to cache the historical operation information of a business according to a certain business can improve the accuracy of the configured buffer size, thereby avoiding the problem of wasting resources or insufficient resources.

In a possible implementation of the first aspect, the multiple processing cores also include: a second processing core, which is used to: when the first service is switched from the first processing core to the second processing core, obtain the first historical operation information from the first buffer, and run the first service according to the first historical operation information. In the above possible implementation, when the first service is switched from the first processing core to the second processing core, the second processing core can still obtain the first historical operation information from the first buffer that caches the first service, thereby avoiding the problem of a large number of cold misses in the second processing core when the first service is switched.

In a possible implementation of the first aspect, the historical operation information or the first operation information includes at least one of the following: branch address pair information, jump information, instruction trace, data trace, cache hot and cold information, scheduling recommendation information, page table information, hardware prefetching regularity information or difficult-to-predict address information. In the above possible implementation, the speculation accuracy and speculation efficiency of the above at least one information can be greatly improved, thereby improving the operation efficiency of the business.

In a possible implementation of the first aspect, the historical operation information or the first operation information further includes a branch block index, and the branch block index is used to index the at least one item; in this case, when the branch block corresponding to the branch block index is accessed, a search of the global predictor can be triggered. In the above possible implementation, the speculation accuracy and speculation efficiency of the branch blocks in the business can be greatly improved, thereby improving the operation efficiency of the business.

In a possible implementation of the first aspect, the first processing core includes: a buffer, which is used to obtain at least part of the first historical operation information from the global predictor and cache the at least part. In the above possible implementation, by setting a buffer with a smaller capacity in the first processing core, and dynamically obtaining the operation information required for the operation of the first service from the first historical operation information of the global predictor through the buffer, the influence of the transmission delay of the first historical operation information on the operation efficiency of the first service is avoided, thereby improving the operation efficiency of the first service.

In a possible implementation of the first aspect, the first historical operation information is historical operation information of other services that are the same as or belong to the same type as the first service. In the above possible implementation, when the first historical operation information is historical operation information of other services that are the same as or belong to the same type as the first service, the operation information of the first service has a large degree of duplication and similarity with the first historical operation information. At this time, the first processing core runs the first service according to the first historical operation information, which can greatly improve the operation efficiency of the first service.

In a second aspect, a business processing method is provided, which is applied to a business processing device, the device comprising a global predictor and a plurality of processing cores coupled to the global predictor; the method comprising: the global predictor caches historical operation information of at least one processing core among the plurality of processing cores; a first processing core among the plurality of processing cores obtains first historical operation information in the historical operation information, and runs a first business according to the first historical operation information to obtain first operation information, the first processing core being any processing core among the plurality of processing cores; the global predictor caches the first operation information.

In a possible implementation of the second aspect, the historical operation information includes historical operation information of multiple businesses, and the historical operation information of the multiple businesses includes first historical operation information; the global predictor caches historical operation information of at least one processing core among the multiple processing cores, including: multiple buffers of the global predictor respectively cache the historical operation information of the multiple businesses, wherein the first buffer among the multiple buffers is used to cache the first historical operation information.

In a possible implementation of the second aspect, the method also includes: the first processing core obtains configuration information for the first service, and the configuration information is used to indicate a first buffer; the first processing core configures the first buffer for the first service according to the configuration information, wherein configuring the first buffer includes enabling, disabling or clearing the first buffer.

In a possible implementation manner of the second aspect, the size of the first buffer is determined according to the first service.

In a possible implementation of the second aspect, the multiple processing cores also include a second processing core, and the method also includes: when the first business is switched from the first processing core to the second processing core, the second processing core obtains the first historical operation information from the first buffer and runs the first business according to the first historical operation information.

In a possible implementation of the second aspect, the historical operation information or the first operation information includes at least one of the following: branch address pair information, jump information, instruction trace, data trace, cache hot and cold information, scheduling recommendation information, page table information, hardware prefetching regularity information or difficult-to-predict address information.

In a possible implementation manner of the second aspect, the historical operation information or the first operation information further includes a branch block index, and the branch block index is used to index the at least one item.

In a possible implementation of the second aspect, the first processing core obtains first historical operation information in the historical operation information, including: a buffer of the first processing core obtains at least part of the first historical operation information from the global predictor and caches the at least part.

In a possible implementation manner of the second aspect, the first historical operation information is historical operation information of other services that are the same as or belong to the same type as the first service.

In a third aspect, an electronic device is provided, which includes a memory and a business processing device, the business processing device includes a global predictor and multiple processing cores, the memory is used to store computer instructions, and the business processing device is used to execute the computer instructions so that the electronic device implements the business processing method provided by the second aspect or any possible implementation of the second aspect.

In another aspect of the present application, a computer-readable storage medium is provided, in which a computer program or instruction is stored. When the computer program or instruction is executed, the business processing method provided by the second aspect or any possible implementation of the second aspect is implemented.

In another aspect of the present application, a computer program product is provided, which includes: a computer program (also referred to as code, or instruction), which, when executed, enables a computer to execute a business processing method provided in the second aspect or any possible implementation of the second aspect.

It can be understood that the beneficial effects that can be achieved by any of the business processing methods, electronic devices, computer-readable storage media and computer program products provided above can correspond to the beneficial effects in the business processing device provided above, and will not be repeated here.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of a multi-core system provided in an embodiment of the present application;

FIG2 is a schematic diagram of the structure of a service processing device provided in an embodiment of the present application;

FIG3 is a schematic diagram of the structure of a LBTB provided in an embodiment of the present application;

FIG4 is a schematic diagram of the structure of another LBTB provided in an embodiment of the present application;

FIG5 is a schematic diagram of a processing core acquiring historical operation information provided by an embodiment of the present application;

FIG6 is a schematic diagram of the structure of an sBTB provided in an embodiment of the present application;

FIG7 is a schematic diagram of a method of sharing global prediction among multiple processing cores provided in an embodiment of the present application;

FIG8 is a schematic diagram of configuring a global predictor provided in an embodiment of the present application;

FIG. 9 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

DETAILED DESCRIPTION

The following will discuss the making and use of each embodiment in detail. However, it should be understood that many applicable inventive concepts provided by this application can be implemented in a variety of specific environments. The specific embodiments discussed are only illustrative of the specific ways to implement and use this application and this technology, and do not limit the scope of this application.

Unless defined otherwise, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art.

Various circuits or other components may be described or referred to as being "configured to" perform one or more tasks. In this case, "configured to" is used to imply structure by indicating that the circuit/component includes structure (e.g., circuitry) that performs the one or more tasks during operation. Thus, even when the specified circuit/component is not currently operational (e.g., not turned on), the circuit/component may be referred to as being configured to perform the task. Circuits/components used with the phrase "configured to" include hardware, such as circuits that perform an operation, etc.

The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. In the present application, "at least one" means one or more, and "more" means two or more. "And/or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and/or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character "/" generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c, a, b and c; where a, b and c can be single or multiple.

The embodiments of the present application use words such as "first" and "second" to distinguish objects with similar names, functions or effects. Those skilled in the art will understand that words such as "first" and "second" do not limit the quantity and execution order. The term "coupled" is used to indicate electrical connection, including direct connection through wires or connection terminals or indirect connection through other devices. Therefore, "coupled" should be regarded as a broad electronic communication connection.

It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

At present, the central processing unit (CPU) subsystem usually has the problem of low efficiency when processing business. The specific manifestations of this problem are: high cache miss rate, low branch prediction accuracy, and low instruction number/clock cycle (instruction per clock, IPC). For example, the scale of instructions and data of the business running on the CPU subsystem is large, while the capacity of resources such as cache, branch target buffer (BTB) and branch direction predictor in the CPU subsystem is limited, which easily causes more cache misses. For another example, the software in the CPU subsystem does not perceive speculative means such as front-end prefetching and back-end prefetching, which makes the prefetching information unable to assist other predictions, resulting in information waste. For another example, the number of threads of an application running on the CPU subsystem is far greater than the number of processing cores (or kernels, also called processor cores) included in the CPU subsystem, which can easily cause a large number of thread switches (including switches within the same processing core and switches between different processing cores). When threads switch, the data stored in resources such as the cache, BTB, and branch direction predictor are not the data required by the current thread, resulting in a large number of cold miss problems for the current thread.

Based on this, an embodiment of the present application provides a business processing device, which includes a global predictor (GP) and multiple processing cores coupled to the global predictor. The global predictor can be used to cache historical operation information, and any one of the multiple processing cores can be used to obtain the required operation information in the historical operation information, and run the business according to the obtained operation information. The global predictor is also used to cache the operation information obtained by running the business. In this way, by caching the historical operation information and the operation information generated by any one of the processing cores running the business through the global predictor, the multiple processing cores obtain the required operation information from the global predictor when running the business, which can reduce the cache miss rate of the multiple processing cores when processing the business, improve the prediction accuracy and IPC (number of instructions/clock cycle), and thus improve the operation efficiency of the business.

The business processing device provided in the embodiment of the present application can be applied to a multi-core system, which can be called a processor subsystem (for example, a CPU subsystem). The structure of the multi-core system is introduced and described below.

FIG1 is a schematic diagram of the structure of a multi-core system provided in an embodiment of the present application. The multi-core system includes a global predictor and a plurality of processing cores coupled to the global predictor, and the plurality of processing cores can share the global predictor through software configuration. The plurality of processing cores can be used to deploy different services, the same services or partially the same services, and the partially the same services may refer to the existence of partially the same data and/or instructions that two services need to access during operation. In an embodiment of the present application, the plurality of processing cores can be used to perform services such as benchmark performance testing, service performance testing, similar service deployment or service suite deployment. Exemplarily, the service scenarios of the multi-core system include but are not limited to: server cluster benchmark performance testing, server cluster bidding service performance testing, server cluster similar service deployment (e.g., high performance computing (HPC)), server cluster service suite deployment, terminal field benchmark performance testing, service switching, service migration, etc.

The number of multiple processing cores included in the multi-core system can be configured according to actual needs. For example, the number of the multiple processing cores can be 2, 4, 6 or 8; in addition, the multiple processing cores can be a homogeneous structure (i.e., multiple processing cores included) or a heterogeneous structure (i.e., including different processing cores). In one example, as shown in (a) of FIG. 1 , the multi-core system includes: a global predictor, and 4 processing cores coupled to the global predictor, the 4 processing cores are respectively represented as core 0 to core 3, and the 4 processing cores are a homogeneous structure. In another example, as shown in (b) of FIG. 1 , the multi-core system includes: a global predictor, and 8 processing cores coupled to the global predictor, the 8 processing cores are respectively represented as core 0 to core 3, and the 8 processing cores are a homogeneous structure. In another example, as shown in (c) of Figure 1, the multi-core system includes: a global predictor, and 8 processing cores coupled to the global predictor, the 8 processing cores may be a heterogeneous structure, and the 8 processing cores may include super large core 0, large core 1 to large core 3, and small core 4 to small core 7.

In the multi-core system, the multiple processing cores may include multiple different processing cores of the same processor, or the multiple processing cores may include processing cores of multiple different processors, that is, the multiple processing cores may form one or more processors. The processors include, but are not limited to, CPU, general-purpose processor, graphic processing unit (GPU), image signal processor (ISP), digital signal processor (DSP), network processor (NPU), artificial intelligence (AI) processor, etc. Optionally, the structures of any two processing cores among the multiple processing cores and the sizes of their respective hardware resources (e.g., cache resources) may be the same or different, and the embodiments of the present application do not impose specific restrictions on this.

Further, the multi-core system may also include a memory coupled to a plurality of processing cores, the memory may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. Exemplarily, the RAM may be a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), and a double data rate synchronous dynamic random access memory (DDR SDRAM). The memory is not shown in the figure.

The multi-core system can be an electronic device, or a system on chip (SoC) or a chipset including multiple chips applied to an electronic device, or a module including the SoC or chipset. The electronic device can be used as a terminal device or a server. Optionally, the electronic device includes but is not limited to: mobile phones, tablet computers, laptop computers, desktop computers, PDAs, ultra-mobile personal computers (ultra-mobile personal computers, umPCs), mobile internet devices (mobile internet devices, MIDs), netbooks, cameras, cameras, wearable devices (such as smart watches and smart bracelets, etc.), vehicle-mounted devices (such as cars, bicycles, electric vehicles, airplanes, ships, trains, high-speed trains, etc.), virtual reality (VR) devices, augmented reality (AR) devices, industrial control (i The wireless terminals include wireless terminals in industrial control, smart home devices (e.g., refrigerators, TVs, air conditioners, electric meters, etc.), intelligent robots, workshop equipment, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, or wireless terminals in smart homes, and flying equipment (e.g., intelligent robots, hot air balloons, drones, airplanes), etc.

FIG2 is a schematic diagram of the structure of a service processing device provided by an embodiment of the present application, wherein the service processing device includes a global predictor 10 and a plurality of processing cores 20 coupled to the global predictor 10, wherein the plurality of processing cores 20 share the global predictor 10, for example, by configuring the plurality of processing cores 20 through software to share different resources of the global predictor 10. FIG2 is taken as an example in which the plurality of processing cores 20 include processing cores 21 to 2n, where n is an integer greater than 1.

The global predictor 10 is used to: cache historical operation information of at least one processing core among the multiple processing cores 20. The at least one processing core includes one or more processing cores. Wherein, when the at least one processing core includes multiple processing cores, the at least one processing core may be a part of the multiple processing cores 20, or may be all of the multiple processing cores 20. The historical operation information cached in the global predictor 10 may be obtained by the at least one processing core running a service. For example, each of the at least one processing core may run one or more services, and transmit the operation information obtained by the operation to the global predictor 10. The global predictor 10 caches the operation information transmitted by the at least one processing core as the historical operation information.

Any one of the multiple processing cores 20 (hereinafter referred to as the first processing core 21 for the convenience of description) is used to: obtain the first historical operation information in the historical operation information, and run the first business according to the first historical operation information to obtain the first operation information. The first historical operation information may be part or all of the historical operation information. Optionally, the first historical operation information is the historical operation information of other businesses that are the same as or belong to the same type as the first business. For example, the first historical operation information may be the historical operation information of the first business, that is, the operation information obtained by the previous operation of the first business; or, the first business and the second business are two businesses in the same high-performance computing, and the first historical operation information is the historical operation information of the second business. The following description takes the first historical operation information as the historical operation information of the first business as an example.

The global predictor 10 is also used to: cache the first operation information. For example, when the first processing core 21 obtains the first operation information, it transmits the first operation information to the global predictor 10, and the global predictor 10 receives and caches the first operation information. After the global predictor 10 caches the first operation information, when any processing core of the multiple processing cores 20 (for example, the first processing core 21 or other processing cores) obtains historical operation information from the global predictor 10, the historical operation information includes the first operation information. That is, the historical operation information is dynamically updated, and the global predictor 10 can dynamically update the historical operation information according to the operation information obtained by the multiple processing cores 20 running the business.

Optionally, the historical operation information or the first operation information includes at least one of the following: branch address pair information, jump information, instruction trace, data trace, cache hot and cold information, scheduling recommendation information, page table information, hardware prefetching regularity information or difficult-to-predict address information. Among them, the branch address pair information refers to the address of the executed branch in the memory, and the address includes a source address and a target address, and the source address and the target address form an address pair. The jump information may include a jump direction and a jump destination, and the jump direction is used to indicate the jump direction of the jump instruction (i.e., jump or not jump), and the jump destination refers to the destination address after the jump. The data trace is used to indicate the trace of the accessed data. The instruction trace is used to indicate the trace of the accessed instruction. The cache hot and cold information is used to indicate the hot and cold degree of data and/or instructions in the cache (e.g., the first, second and third level cache). The scheduling recommendation information is used to indicate the recommended information in the scheduling process, such as the scheduling policy recommended based on the quality of service (QoS). The page table information is used to indicate the correspondence between the virtual address and the physical address corresponding to the accessed data and/or instruction. The regularity information of hardware prefetching is used to indicate the regularity of hardware prefetching data and/or instructions, which may include front-end prefetching and/or back-end prefetching. The difficult-to-predict address information is used to indicate the address information that is difficult to predict for the hardware prefetcher (hardware prefetch, HWP). The memory targeted by the above address may be located on the same or different chip as the above one or more processing cores, and may be a volatile or non-volatile memory, which is not limited in this embodiment.

It can be understood that the above-mentioned historical operation information or first operation information, in addition to the above-mentioned information, may also include other information required in the business operation process (such as value prediction information, which may refer to the numerical value obtained by prediction when the memory access is not completed). The embodiment of the present application does not impose specific restrictions on this.

Optionally, the above historical operation information or the first operation information also includes a branch block index, and the branch block index is used to index at least one of the above information. At this time, when the branch block corresponding to the branch block index is accessed, the search of the global predictor 10 can be triggered. Among them, the branch block index can also be called a branch block program counter (program counter, PC) index (block PC index). For ease of understanding, the historical operation information is taken as an example below to explain the branch block index included in the historical operation information and the first operation information and at least one item corresponding to the branch block index.

In one example, assuming that the historical operation information includes historical operation information of multiple businesses, the historical operation information of each business may include at least one branch block index, and historical operation sub-information corresponding to each branch block index, and each historical operation sub-information may include at least one of the following: branch address pair information, jump information, instruction trace, data trace, cache hot and cold information, scheduling recommendation information, page table information, hardware prefetching regularity information or difficult-to-predict address information.

Each of the above-mentioned multiple businesses may include at least one branch block, and each branch block (or subroutine or program segment) in the at least one branch block may correspond to a branch block index, and the branch block may correspond to a historical operation sub-information after running, and the branch block index of a branch block may be used to index the historical operation sub-information obtained after the branch block runs. Optionally, the branch block index may be an instruction fetch address, and the instruction fetch address may be a source address corresponding to the branch block.

Exemplarily, the historical operation information may be shown in the following Table 1. In Table 1, it is assumed that the multiple services include M services, and the M services are represented as services 1 to M, at least one branch block index of service 1 is represented as ID1-1, ID1-2, ..., at least one branch block index of service 2 is represented as ID2-1, ID2-2, ..., and at least one branch block index of service M is represented as IDM-1, IDM-2, ...

Table 1

It can be understood that the above Table 1 uses the example that the information types included in the historical operation sub-information corresponding to different branch block indexes are the same. In actual applications, the information types included in the historical operation sub-information corresponding to different branch block indexes may also be different, and the embodiments of the present application do not impose specific restrictions on this.

In addition, the global predictor 10 may also include other information of each of the multiple services. For example, the other information may include a service identifier and/or a service context, etc. This embodiment of the present application does not impose any specific limitation on this.

Further, the global predictor 10 includes a plurality of buffers. The plurality of buffers are used to cache the historical operation information of the plurality of services respectively. Each of the plurality of buffers can be used to cache the historical operation information obtained by the operation of a processing core, that is, the historical operation information obtained by the operation of different processing cores can be cached in different buffers; or, to cache the historical operation information of a service, that is, the historical operation information of different services can be cached in different buffers.

Optionally, the multiple buffers include a first buffer, the first buffer is used to cache historical operation information of the first business, and the historical operation information of the first business may include first historical operation information. In a possible example, for any one of the multiple processing cores 20 except the first processing core 21 (referred to as the second processing core 22 herein), when the first business is switched from the first thread of the first processing core 21 to the second thread of the second processing core 22, the second processing core 22 can be used to obtain the first historical operation information from the first buffer, and run the first business according to the first historical operation information. In this example, when the first business is switched from the first processing core 21 to the second processing core 22, the second processing core 22 can still obtain the first historical operation information from the first buffer that caches the first business, thereby avoiding the problem of a large number of cold misses in the second processing core 22 when the first business is switched.

Optionally, the size (or dimension) of each buffer in the multiple buffers may be determined according to the business to which the historical operation information cached in the buffer belongs. Exemplarily, the size of the first buffer is determined according to the first business. That is, the size of the buffer used to cache the historical operation information of a business may be dynamically determined according to the size of the business. For example, in actual applications, the size of the corresponding buffer may be dynamically determined for each business by software (e.g., an operating system) running on the multiple processing cores 20, and the embodiments of the present application do not impose specific restrictions on this.

In a possible embodiment, the global predictor 10 includes a multi-way buffer, and each buffer in the above-mentioned multiple buffer areas may include at least one buffer in the multi-way buffer. Optionally, each buffer in the multi-way buffer can be used to cache historical operation information of a service, and historical operation information of different services is cached in different buffers. The historical operation information of the same service can occupy one or more buffers. In addition, the multi-way buffers are independent of each other, and each buffer can be accessed separately, and the access corresponding to the buffers of different ways does not affect each other. Exemplarily, the multi-way buffer includes a first buffer, and the first buffer is used to cache the historical operation information of the first service.

When the historical operation information of a certain service includes at least one of the above multiple information such as branch address pair information, jump information and instruction trace, for any one of the at least one item, each buffer in the global predictor 10 can be cached by the following structure. For the convenience of description, the following example is taken as an example that the first processing core 21 runs the first service, the first buffer is used to cache the historical operation information of the first service, and the historical operation information of the first service includes branch address pair information. Among them, the first buffer can also be called a link branch target buffer (LBTB).

In one example, as shown in Fig. 3, the LBTB may include: a history queue, a storage circuit, a search queue, and a fill queue. The history queue, the search queue, and the fill queue are all coupled to the storage circuit.

The history queue is used to obtain the correct branch address pair (i.e., including the source address and the target address) from the pipeline corresponding to the first business when a branch prediction target address fails (represented as a prediction failure in the figure, and the prediction failure may mean that the target address corresponding to the branch is not found in the cache of the first processing core 21 (e.g., the first buffer and the second buffer hereinafter)) during the operation of the first business, and output the branch address pair to the storage circuit. Optionally, in order to reduce the number of updates to the LBTB to reduce power consumption and access conflicts, the history queue can be used to output the preset number of branch address pairs as a group to the storage circuit in a certain storage format when a preset number of branch address pairs (e.g., 4 address pairs) are accumulated. In FIG3, the preset number of branch address pairs includes brn add0-tgt add0, brn add1-tgt add1, brn add2-tgt add2, brn add3-tgt add3, and the storage format also includes a link address link add as an example, and the link add is used to indicate the branch address pair of the next group.

The storage circuit is used to receive and cache the branch address pairs output by the history queue. When a group of branch address pairs are cached in the above storage format, the storage circuit can index the source address of the first branch address pair and write the group of branch addresses into the corresponding storage. Optionally, the storage circuit can include multi-way connected RAM, so that the search efficiency can be improved when searching the storage circuit.

The search queue is used to obtain the instruction fetch address of the branch block and output the instruction fetch address to the storage circuit. The search queue can receive and filter duplicate address information; in addition, the search queue can be a multi-input and one-output queue, so that the bandwidth difference between input and output can be balanced. Optionally, the search queue can obtain the instruction fetch address when the first processing core 21 meets certain conditions. For example, the conditions may include but are not limited to: querying and missing in the main branch target buffer (main branch target buffer, mBTB), or querying and hitting in the stream branch target buffer (stream branch target buffer, sBTB). For a detailed description of mBTB and sBTB, please refer to the description below, and the embodiments of the present application will not be repeated here.

The storage circuit is also used for: when receiving the instruction fetch address of the branch block of the first processing core 21, obtaining the corresponding branch address pair according to the instruction fetch address, and outputting the branch address pair to the backfill queue. Optionally, when a group of branch address pairs are cached in the above storage format, the storage circuit can disassemble the obtained group of branch addresses, and output a preset number of branch address pairs obtained by disassembly to the backfill queue, and output the link add in the group of branch address pairs to the search queue, so that the search queue performs the next search based on the link add.

The backfill queue is used to backfill the branch address pairs output by the storage circuit into the first processing core 21. Optionally, the backfill queue can backfill a preset number of branch address pairs output by the storage circuit into the buffer of the first processing core 21, for example, into the sBTB of the first processing core 21.

In another example, in combination with FIG. 3 , as shown in FIG. 4 , for each processing core in the multiple processing cores 20, the global predictor 10 may include a history queue, a storage circuit, a search queue, and a backfill queue corresponding to each processing core. Among them, the different storage circuits in the global predictor 10 may be integrated together as a storage module; or, the global predictor includes a storage module, the storage module includes a storage circuit corresponding to each processing core, and the storage circuit includes a multi-way cache. In FIG. 4 , the multiple processing cores 20 include 4 processing cores and are represented as cores 0 to 3, respectively, the history queue 0, search queue 0, backfill queue 0, and two-way caches w0 and w1 corresponding to core 0, the history queue 1, search queue 1, backfill queue 1, and two-way caches w2 and w3 corresponding to core 1, the history queue 2, search queue 2, backfill queue 2, and two-way caches w4 and w5 corresponding to core 2, and the history queue 3, search queue 3, backfill queue 3, and four-way caches w6 to w9 corresponding to core 3.

Furthermore, the following takes the example of the first processing core 21 acquiring the first historical operation information from the global predictor 10 to introduce and illustrate the relevant process of any processing core among the multiple processing cores 20 acquiring the historical operation information from the global predictor 10 .

In a possible embodiment, the first processing core 21 includes a first buffer, and the first buffer is used to obtain at least part of the first historical operation information from the global predictor 10 and cache the at least part. The first processing core 21 may also include a second buffer, and the second buffer is different from the first buffer. The second buffer may refer to a buffer set in the first processing core 21 for caching prefetch information, and the second buffer is not used to cache the historical operation information obtained from the global predictor 10. In the embodiment of the present application, the first buffer may also be referred to as a candidate buffer (e.g., sBTB), and the second buffer may be referred to as a primary buffer (e.g., mBTB).

Optionally, the first buffer can be specifically used to obtain at least part of the first historical operation information from the global predictor 10 and cache the at least part when certain conditions are met. For example, the condition may include: querying in the second buffer and not hitting (that is, the second buffer does not have the required information), or querying in the first buffer and hitting (the first buffer has the required information), etc., and the embodiment of the present application does not impose specific restrictions on this.

Among them, when the first historical operation information includes at least one of the above multiple information such as branch address pair information, jump information and instruction trace, the number of the first buffers of the first processing core 21 can be at least one, that is, the first processing core 21 includes at least one first buffer, and each first buffer of the at least one first buffer can be used to cache one of the above multiple historical operation information. For ease of description, the following is an example in which the first historical operation information includes branch address pair information, and the first processing core 21 includes a main branch target buffer mBTB (corresponding to the second buffer) and a streaming branch target buffer sBTB (corresponding to the first buffer).

Exemplarily, as shown in FIG5 , the first processing core 21 includes an mBTB and an sBTB, wherein the mBTB caches a first branch address pair set corresponding to a first service pre-fetched by the first processing core 21, and the sBTB caches a second branch address pair set obtained from the LBTB of the global predictor 10. In the process of the first processing core 21 running the first service, when the first processing core 21 obtains the instruction fetch address FIVA through instruction fetching, the first processing core 21 may first query whether the target branch address corresponding to the FIVA exists in the first branch address pair set cached in the mBTB; if so (i.e., a hit), the execution continues according to the target branch address; if not (i.e., a miss), the second branch address pair set cached in the sBTB is queried whether the target branch address corresponding to the FIVA exists, and if so (i.e., a hit), the execution continues according to the queried target branch address. In addition, when the query in the mBTB does not hit, or the query in the sBTB hits, it indicates that the historical operation information is accurate and available as pre-fetch information, and the sBTB can obtain more branch address pairs corresponding to the first business from the LBTB of the global predictor 10. For example, the sBTB sends the next instruction fetch address to the global predictor 10 to obtain the more branch address pairs through the next instruction fetch address for use when the first processing core 21 runs the first business. Optionally, when the first business ends, or when other businesses need to use the sBTB, the first processing core 21 can also clear (or flush) the sBTB. For example, the first processing core 21 can clear the sBTB through the valid bit.

It can be understood that the conditions for the sBTB to obtain the branch address pair from the LBTB of the global predictor 10 may also include other conditions, such as obtaining when a certain time is reached, or obtaining when all pipeline jumps of the first processing core 21 occur, etc. The embodiment of the present application does not impose specific restrictions on this.

In addition, FIG6 shows a possible structural diagram of the above-mentioned sBTB. As shown in FIG6, the sBTB may include a storage circuit and a valid bit array, the storage circuit may be used to cache historical operation information from the global predictor 10, and the valid bit array may be used to indicate the validity of the cached information in the storage circuit. Among them, the storage circuit may include a multi-way connected RAM, so that the search efficiency can be improved when searching the storage circuit. Optionally, the sBTB may also include a matching and selection circuit, which may be used to match the business to which the FIVA belongs with the business currently cached by the sBTB, and output when the target branch address hit by the sBTB is valid. In addition, the output end of the mBTB and the output end of the sBTB may also be coupled by a selector, which is used to select the output result of the mBTB when the mBTB hits, and select the output result of the sBTB when the sBTB hits.

Optionally, when the first processing core 21 queries the first buffer and hits, the first processing core 21 can reload the hit operation information as speculative information into the module or component that needs to be used by the pipeline. Exemplarily, the branch address pair is loaded back into the branch pipeline, the hot and cold and critical information of the instruction cache and the data cache is loaded back into the instruction prefetch and replacement component, the historical operation information of the page table is loaded back into the page table prefetch component, and the regular information and difficult-to-predict address information of the hardware prefetch are loaded back into the hardware prefetch component, etc.

Further, in a possible example, as shown in FIG7, when the historical operation information cached in the global predictor includes multiple information such as branch address pair information, jump information and instruction trace, the second buffer for caching the multiple information in any processing core (for example, core 0) among the multiple processing cores 21 (for example, core 0, core 1 and core 2) may include a branch target buffer (BTB), an instruction cache (Icache), a data cache (Dcache) and a page table cache (TLB); the processing core may also include other devices such as an execution pipeline. FIG7 is illustrated by taking the example that the processing core caches the multiple information obtained from the global predictor 10 through the first buffer, and the first buffer is a stream buffer.

Accordingly, in one example, as shown in FIG7 , the global predictor 10 includes multiple buffers (e.g., N buffers and represented as GP w0 to GP wN), each of which can be used to cache the historical operation information of a service, and the historical operation information of any service can include multiple branch block indexes, and the above-mentioned multiple information corresponding to each branch block index. The branch block index in the historical operation information of service 1 in FIG7 includes block-ID1 and block-ID2 as an example for explanation. When the same service switches between different processing cores, the processing core where the service is switched can share the historical operation information of the service in the global predictor 10.

After introducing the related structures of the global predictor 10 and the multiple processing cores 20 , the process of allocating resources in the global predictor 10 to any processing core among the multiple processing cores 20 is described in detail below.

Optionally, the resources in the global predictor 10 used by any of the multiple processing cores 20 can be obtained through configuration. When any of the multiple processing cores 20 needs to use the global predictor 10 to cache the historical operation information of a certain service, the global predictor 10 can be configured for the processing core, for example, a corresponding buffer is configured in the global predictor 10 for the processing core. In addition, the services that can use the global predictor 10 can also be configured for the multiple processing cores 20, that is, some key services can be configured for any of the multiple processing cores 20, and only the historical operation information of the configured key services can be cached in the global predictor. The process of configuring the global predictor is introduced and explained below by taking the first processing core 21 as an example.

In a possible embodiment, the first processing core 21 is also used to: obtain configuration information for the first service, the configuration information is used to indicate the first buffer; configure the first buffer for the first service according to the configuration information. Optionally, configuring the first buffer may include enabling, disabling or clearing the first buffer. Among them, the configuration information may be sent to the first processing core 21 by the software running on the multiple processing cores 20, or may be pre-configured in the first processing core 21, and the embodiments of the present application do not impose specific restrictions on this. The configuration information can be used to indicate the size of the first buffer, and/or to indicate the address space corresponding to the first buffer. Further, the configuration information can also be used to indicate the first service. For example, the configuration information may include a service identifier of the first service.

For ease of understanding, as shown in Figure 8, the following is an example of the process of enabling, disabling and clearing the global predictor 10 through configuration information when the first processing core 21 is core 0, core 1 and core 2. Figure 8 is an example of core 0, core 1 and core 2 all including HWP and SBTB.

In one example, assuming that the first processing core 21 is core 0, enabling the global predictor 10 through configuration information includes: S11. When it is necessary to run service a on core 0, the software running on the multiple processing cores 20 can send the first configuration information for the service a to core 0; S12. When core 0 receives the first configuration information, the HWP of core 0 enables the global predictor 10 according to the first configuration information, for example, sending service information and enable information to the global predictor 10 to enable the global predictor 10 to cache the historical operation information of service a; S13. Core 0 can also enable sBTB when the information currently cached in sBTB matches service a; S14. The global predictor 10 starts working.

In another example, assuming that the first processing core 21 is core 1, shutting down the global predictor 10 through configuration information includes: S21. When it is necessary to shut down the service b running on core 1 using the global predictor 10, the software running on the multiple processing cores 20 can send second configuration information for the service b to core 1; S22. When receiving the second configuration information, the HWP of core 1 shuts down the global predictor 10 according to the second configuration information, for example, sending service information and shutdown information to the global predictor 10; S23. The global predictor 10 stops providing services for the service b on core 1, that is, stops providing historical operation information of the service to core 1.

In another example, assuming that the first processing core 21 is core 2, clearing the global predictor 10 through configuration information includes: S31. When it is necessary to clear the global predictor 10 used by the business c running on core 2, the software running on the multiple processing cores 20 can send the third configuration information for the business c to core 2; S32. When receiving the third configuration information, the HWP of core 2 clears the global predictor 10 according to the third configuration information, for example, sending thread information and clearing information to the global predictor 10; S33. The global predictor 10 clears the information corresponding to the thread, that is, clears the historical running information of the business c. Optionally, the global predictor 10 can be cleared using a row-by-row clearing method.

In the embodiment of the present application, the global predictor 10 caches historical operation information and the operation information generated by any processing core running the business, so as to update the cached operation information for subsequent use. When running the business, the multiple processing cores 20 obtain the operation information they need from the global predictor 10. In this way, compared with expanding a larger capacity cache for the multiple processing cores, the cache miss rate of the multiple processing cores 20 when processing the business can be reduced, the prediction accuracy and IPC can be improved, and the operation efficiency of the business can be improved. For the business switching scenario, since the global predictor 10 can be shared by the multiple processing cores 20, when the business is switched from one processing core to another, the other processing core can still obtain the historical operation information of the business from the global predictor 10 for running the business, thereby avoiding the problem of a large number of cold misses in the other processing core. In addition, the resources in the global predictor 10 used by any processing core among the multiple processing cores 20 are obtained through software configuration, and the multiple processing cores 20 can also be configured with services that can use the global predictor 10, so as to avoid information overflow in the global predictor 10 causing security information leakage. At the same time, from the software perspective, key services can be identified and the resources in the global predictor 10 can be configured to the key services running on the processing core, thereby avoiding resource bottlenecks and further improving the operating efficiency of the services.

Based on this, an embodiment of the present application also provides a service processing method, which can be applied to a service processing device including a global predictor and multiple processing cores coupled to the global predictor. For a description of the service processing device, please refer to the above description. The method includes: the global predictor caches historical operation information of at least one processing core among the multiple processing cores; the first processing core among the multiple processing cores obtains the first historical operation information in the historical operation information, and runs the first service according to the first historical operation information to obtain the first operation information; the global predictor caches the first operation information.

Optionally, the historical operation information includes historical operation information of multiple businesses, and the historical operation information of the multiple businesses includes first historical operation information.

In a possible embodiment, the global predictor includes multiple buffers, and the multiple buffers cache the historical operation information of the multiple services respectively, wherein the first buffer of the multiple buffers caches the first historical operation information. Accordingly, the method may also include: the first processing core obtains configuration information for the first service, and the configuration information is used to indicate the first buffer; the first processing core configures the first buffer for the first service according to the configuration information. Configuring the first buffer includes enabling, disabling or clearing the first buffer.

It can be understood that all contents in the above-mentioned device embodiment can be referred to in the embodiment corresponding to the business processing method, and the embodiments of the present application will not be described in detail here.

In an embodiment of the present application, historical operation information and operation information generated by any processing core running a business are cached by a global predictor to update the cached operation information for subsequent use. Any processing core among the multiple processing cores can obtain the required operation information from the global predictor when running a business. In this way, compared with expanding a larger capacity cache for the multiple processing cores, this solution can reduce the cache miss rate when the multiple processing cores process the business, improve the prediction accuracy and IPC, and thus improve the operation efficiency of the business.

In another aspect of the present application, an electronic device is also provided, as shown in FIG9 , the electronic device includes a memory and a service processing device, the service processing device includes a global predictor and multiple processing cores, the memory is used to store computer instructions, and the service processing device is used to execute the computer instructions so that the electronic device implements any one of the service processing methods provided above. The specific introduction of the memory can be seen in the previous embodiment.

It can be understood that all relevant contents of each step involved in the above method embodiment can be referred to the embodiment of the business processing method and the embodiment of the electronic device, and the embodiments of the present application will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed.

The units described as separate components may or may not be physically separated, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium, which can include: a USB flash drive, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk, etc., which can store program codes. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product.

In another embodiment of the present application, a readable storage medium is also provided, in which computer execution instructions are stored. When a device (which may be a single-chip microcomputer, chip, etc.) or a processor executes the steps in the above method embodiment.

In another embodiment of the present application, a computer program product is also provided, which includes computer instructions stored in a readable storage medium; at least one processor of the device can read the computer instructions from the readable storage medium, and at least one processor executes the computer instructions so that the device performs the steps in the above method embodiment.

Finally, it should be noted that the above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims (20)

A service processing device, characterized in that it comprises: a global predictor, and a plurality of processing cores coupled to the global predictor; wherein: The global predictor is used to cache historical operation information of at least one processing core among the multiple processing cores; a first processing core among the multiple processing cores, configured to obtain first historical operation information among the historical operation information, and to run a first service according to the first historical operation information to obtain first operation information, wherein the first processing core is any processing core among the multiple processing cores; The global predictor is further used to cache the first operation information. The device according to claim 1, characterized in that the historical operation information includes historical operation information of multiple services, and the historical operation information of the multiple services includes the first historical operation information; The global predictor includes: a plurality of buffers, used to cache the historical operation information of the plurality of services respectively, wherein a first buffer among the plurality of buffers is used to cache the first historical operation information. The device according to claim 2, characterized in that the first processing core is further used to: Acquire configuration information for the first service, where the configuration information is used to indicate the first buffer; The first buffer is configured for the first service according to the configuration information, wherein configuring the first buffer includes enabling, disabling or clearing the first buffer. The device according to claim 3 is characterized in that the size of the first buffer is determined according to the first service. The device according to any one of claims 2 to 4, wherein the plurality of processing cores further comprises: The second processing core is used to obtain the first historical operation information from the first buffer and run the first service according to the first historical operation information when the first service is switched from the first processing core to the second processing core. The device according to any one of claims 1 to 5 is characterized in that the historical operation information or the first operation information includes at least one of the following: branch address pair information, jump information, instruction trace, data trace, cache hot and cold information, scheduling recommendation information, page table information, hardware prefetching regularity information or difficult-to-predict address information. The device according to claim 6 is characterized in that the historical operation information or the first operation information also includes a branch block index, and the branch block index is used to index the at least one item. The device according to any one of claims 1 to 7, wherein the first processing core comprises: A buffer is used to obtain at least part of the first historical operation information from the global predictor and cache the at least part. The device according to any one of claims 1 to 8 is characterized in that the first historical operation information is historical operation information of other services that are the same as or belong to the same type as the first service. A service processing method, characterized in that it is applied to a service processing device, wherein the device includes a global predictor and a plurality of processing cores coupled to the global predictor; the method includes: The global predictor caches historical operation information of at least one processing core among the plurality of processing cores; A first processing core among the multiple processing cores acquires first historical operation information among the historical operation information, and runs a first service according to the first historical operation information to obtain first operation information, wherein the first processing core is any processing core among the multiple processing cores; The global predictor caches the first running information. The method according to claim 10, characterized in that the historical operation information includes historical operation information of multiple services, and the historical operation information of the multiple services includes the first historical operation information; the global predictor caches the historical operation information of at least one processing core of the multiple processing cores, comprising: The multiple buffers of the global predictor cache the historical operation information of the multiple services respectively, wherein a first buffer among the multiple buffers is used to cache the first historical operation information. The method according to claim 11, characterized in that the method further comprises: The first processing core obtains configuration information for the first service, where the configuration information is used to indicate the first buffer; The first processing core configures the first buffer for the first service according to the configuration information, wherein configuring the first buffer includes enabling, disabling or clearing the first buffer. The method according to claim 12 is characterized in that the size of the first buffer is determined according to the first service. The method according to any one of claims 11 to 13, wherein the plurality of processing cores further include a second processing core, and the method further includes: When the first service is switched from the first processing core to the second processing core, the second processing core obtains the first historical operation information from the first buffer and runs the first service according to the first historical operation information. The method according to any one of claims 10-14 is characterized in that the historical operation information or the first operation information includes at least one of the following: branch address pair information, jump information, instruction trace, data trace, cache hot and cold information, scheduling recommendation information, page table information, hardware prefetching regularity information or difficult-to-predict address information. The method according to claim 15 is characterized in that the historical operation information or the first operation information also includes a branch block index, and the branch block index is used to index the at least one item. The method according to any one of claims 10 to 16, wherein the first processing core obtains the first historical operation information in the historical operation information, comprising: The buffer of the first processing core obtains at least part of the first historical operation information from the global predictor and caches the at least part. The method according to any one of claims 10-17 is characterized in that the first historical operation information is historical operation information of other services that are the same as or belong to the same type as the first service. An electronic device, characterized in that the electronic device includes a memory and a business processing device, the business processing device includes a global predictor and multiple processing cores, the memory is used to store computer instructions, and the business processing device is used to execute the computer instructions so that the electronic device implements the business processing method as described in any one of claims 10-18. A readable storage medium, characterized in that the readable storage medium stores computer instructions, and when the computer instructions are executed on a device, the device executes the business processing method according to any one of claims 10-18.