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WO2025128493A1 - Encapsulation structure for memory devices - Google Patents

Encapsulation structure for memory devices Download PDF

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Publication number
WO2025128493A1
WO2025128493A1 PCT/US2024/059232 US2024059232W WO2025128493A1 WO 2025128493 A1 WO2025128493 A1 WO 2025128493A1 US 2024059232 W US2024059232 W US 2024059232W WO 2025128493 A1 WO2025128493 A1 WO 2025128493A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
layer
dielectric
sidewall
encapsulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/US2024/059232
Other languages
French (fr)
Inventor
Neil Quinn Murray
Noriyuki Sato
Somilkumar J. RATHI
Niloy Mukherjee
Tanay GOSAVI
Amrita Mathuriya
Rajeev Kumar Dokania
Sasikanth Manipatruni
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kepler Computing Inc
Original Assignee
Kepler Computing Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kepler Computing Inc filed Critical Kepler Computing Inc
Publication of WO2025128493A1 publication Critical patent/WO2025128493A1/en
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers

Definitions

  • Figure 1A illustrates a cross-section of a device structure including a capacitor comprising a bottom electrode structure and an encapsulation structure on a sidewall of the bottom electrode structure, in at least one example.
  • Figure 1E illustrates a cross-section of a device structure including a capacitor comprising a bottom electrode structure and an encapsulation structure, where the Docket No.: KP12P064US-PCT encapsulation structure further comprises a portion that extends laterally on etch stop layer, in at least one example.
  • Figure 1F illustrates a cross-section of a device structure including a capacitor comprising a bottom electrode structure and an encapsulation structure on a sidewall of the bottom electrode structure, in at least one example.
  • Figure 1G illustrates a cross-section of a device structure including a capacitor comprising a bottom electrode structure and an encapsulation structure on a sidewall of the bottom electrode structure, in at least one example.
  • Figure 2A illustrates a cross-section of a device structure comprising a capacitor coupled with an electrode structure.
  • Figure 2B illustrates a cross-section of a device structure comprising a plurality of capacitors, where an individual capacitor is coupled with an individual electrode structure, in at least one example.
  • Figure 3A illustrates a cross-section of a cross-section of capacitor that includes a spacer between an encapsulation structure and sidewall of a portion of the capacitor.
  • Figure 3B illustrates a cross-section of device structure in Figure 3A, where different portions of encapsulation structure can have different thicknesses, and where a portion of the encapsulation structure adjacent to a bottom electrode structure does not include a cavity.
  • Figure 4A illustrates a cross-section of a device structure including a capacitor coupled with an electrode structure, where a first portion of an encapsulation structure is on a sidewall of the capacitor and a second portion is under a lowermost layer of the capacitor, in at least one example.
  • Figure 4B illustrates a cross-section of the device structure in Figure 4A where encapsulation structure further comprises a portion that extends laterally on an etch stop layer adjacent to the capacitor.
  • Figure 4C illustrates a cross-section of the device structure in Figure 4A where an insulator liner is on sidewalls of the electrode structure, in at least one example.
  • Figure 4D illustrates a cross-section of the device structure in Figure 4A where a lateral thickness of a portion of encapsulation structure adjacent to a sidewall of the electrode structure varies with height of electrode structure, in at least one example.
  • Figure 4E illustrates a cross-section of a device structure comprising a plurality of capacitors, where an individual capacitor is coupled with an individual electrode structure, in at least one example. Docket No.: KP12P064US-PCT
  • Figure 5 is an illustration of a flow for fabricating a device structure.
  • Figure 6A illustrates a cross-section of a fin structure formed on a substrate, in at least one example.
  • Figure 6B is an isometric illustration of structure in Figure 6A following process to form a dielectric adjacent to a portion of fin structure, in at least one example.
  • Figure 6C is an isometric illustration of structure in Figure 6B following formation of a dummy gate on fin, in at least one example.
  • Figure 6D is an isometric illustration of structure in Figure 6C following process to form an epitaxial source structure and an epitaxial drain structure, in at least one example.
  • Figure 6E is an isometric illustration of structure in Figure 6D following process to remove mask, dummy gate, and dummy gate dielectric to form a gate opening, in at least one example.
  • Figure 6F illustrates a cross-section of structure in Figure 6E following process to form a gate structure in gate opening, in at least one example.
  • Figure 7A illustrates a cross-section of structure in Figure 6F through a line A-A' following process to form a drain contact on a drain structure, in at least one example.
  • Figure 7B illustrates a cross-section of structure in Figure 7A, following process to form a conductive interconnect coupled with the drain contact, in at least one example.
  • Figure 8 illustrates a cross-section of structure in Figure 7B following process to deposit an etch stop layer to form an electrode structure, in at least one example.
  • Figure 9A is an enhanced cross-sectional illustration of a portion of structure in Figure 8 following process to etch an opening in etch stop layer, in at least one example.
  • Figure 9B illustrates a cross-section of structure in Figure 9A following process to deposit a liner layer within an opening, in at least one example.
  • Figure 9C illustrates a cross-section of structure in Figure 9B following process to form a spacer within the opening, in at least one example.
  • Figure 9D illustrates a cross-section of structure in Figure 9C following process to form a conductive hydrogen barrier layer adjacent to the spacer within the opening, and a conductive fill material on the conductive hydrogen barrier layer, in at least one example.
  • Figure 9E illustrates a cross-section of structure in Figure 9A following process to form an electrode structure where a conductive hydrogen barrier laterally surrounds a conductive fill material, and where a spacer is between conductive hydrogen barrier and etch stop layer, in at least one example.
  • Docket No.: KP12P064US-PCT [0034]
  • Figure 10A illustrates a cross-section of a structure in Figure 9A following process to deposit a conductive fill material within the opening, in at least one example.
  • Figure 10B illustrates a cross-section of a structure in Figure 10A following process to planarize and recess conductive fill material within opening, in at least one example.
  • Figure 10C illustrates a cross-section of structure in Figure 10B following process to form a conductive hydrogen barrier on conductive fill material, in at least one example.
  • Figure 11A illustrates a cross-section of structure in Figure 9A following process to form a conductive hydrogen barrier layer within opening, and a conductive fill material on conductive hydrogen barrier layer, in at least one example.
  • Figure 11B illustrates a cross-section of structure in Figure 11A following process to form an electrode structure where a conductive hydrogen barrier laterally surrounds a conductive fill material, in at least one example.
  • Figure 12A illustrates a cross-section of structure in Figure 11A following the process to deposit a multi-layer stack on an electrode structure, in at least one example.
  • Figure 12B illustrates a cross-section of structure in Figure 12A, following process to etch multi-layer stack to form a capacitor, in at least one example.
  • Figure 12C illustrates a cross-section of structure in Figure 12B following process to laterally recess a portion of a lowermost layer in capacitor, in at least one example.
  • Figure 12D illustrates a cross-section of structure in Figure 12C, following process to deposit an encapsulation layer on sidewalls of capacitor, in at least one example.
  • Figure 12E illustrates a cross-section of structure in Figure 12D, following process to etch encapsulation layer to form an encapsulation structure, in at least one example.
  • Figure 13A illustrates a cross-section of structure in Figure 11A following process to etch multi-layer stack to form a partially formed capacitor structure, in at least one example.
  • Figure 13B illustrates a cross-section of structure in Figure 13A following process to form a spacer adjacent to partially formed capacitor structure.
  • Figure 13C illustrates a cross-section of structure in Figure 13B following process to etch a lowermost layer in multi-layer stack and laterally recess a portion of lowermost layer to form a recessed portion, in at least one example.
  • Figure 13D illustrates a cross-section of structure in Figure 13C following process to deposit an encapsulation layer on spacer and adjacent to sidewall of recessed portion of lowermost layer, in at least one example.
  • Figure 13E illustrates a cross-section of structure in Figure 13D following process to etch encapsulation layer to form an encapsulation structure, in at least one example.
  • Figure 14A illustrates a cross-section of structure in Figure 13D following process to anisotropically etch lowermost conductive layer to form an electrode, in at least one example.
  • Figure 14B illustrates a cross-section of a portion of structure in Figure 14A following process to recess a portion of electrode to form a cavity.
  • Figure 15A illustrates a cross-section of structure in Figure 8 following process to deposit sacrificial layer and form an opening in the sacrificial layer and in the etch stop layer, in at least one example.
  • Figure 15B illustrates a cross-section of structure in Figure 15A following process to form an electrode structure in opening, in at least one example.
  • Figure 15C illustrates a cross-section of structure in Figure 15B following process to deposit a multi-layer stack to fabricate a capacitor, in at least one example.
  • Figure 15D illustrates a cross-section of structure in Figure 15C following process to etch multi-layer stack to form a capacitor, in at least one example.
  • Figure 15E illustrates a cross-section of structure in Figure 15D following process to remove sacrificial layer and expose a portion of sidewall of an electrode structure below capacitor, in at least one example.
  • Figure 15F illustrates a cross-section of structure in Figure 15E following process to deposit an encapsulation layer on sidewall of the capacitor and adjacent to the portion of sidewall of an electrode structure exposed by removing sacrificial layer, in at least one example.
  • Figure 15G illustrates a cross-section of structure in Figure 15F following process to etch the encapsulation layer to form an encapsulation structure, in at least one example.
  • Figure 16A illustrates a cross-section of structure in Figure 15D following process to deposit an encapsulation layer on sidewall of capacitor and on sacrificial layer, in at least one example. Docket No.: KP12P064US-PCT
  • Figure 16B illustrates a cross-section of structure in Figure 16A following process to etch encapsulation layer to form a spacer adjacent to capacitor sidewalls, in at least one example.
  • Figure 16C illustrates a cross-section of structure in Figure 16B following process to remove the sacrificial layer and expose a portion of sidewall of an electrode structure below the capacitor and expose a portion of a lowermost surface of capacitor, in at least one example.
  • Figure 16D illustrates a cross-section of structure in Figure 16C following process to deposit an encapsulation layer on sidewall of the spacer, on portion of lowermost surface of capacitor and on an etch stop layer adjacent to electrode structure, in at least one example.
  • Figure 16E illustrates a cross-section of structure in Figure 16D following process to etch encapsulation layer to form an encapsulation structure, in at least one example.
  • Figure 17A illustrates a cross-section of structure in Figure 16E following process to deposit a dielectric on capacitor, on encapsulation structure, and on etch stop layer, and planarize dielectric to expose an uppermost surface of a top electrode of capacitor, in at least one example.
  • Figure 17B illustrates a cross-section of structure in Figure 17A following process to form a via electrode on at least a portion of top electrode of capacitor after formation of an insulator layer comprising a hydrogen barrier material, in at least one example.
  • Figure 18 illustrates a cross-section of structure in Figure 15G following process to deposit a dielectric on capacitor and on encapsulation structure, and on etch stop layer, and planarize the dielectric to expose an uppermost surface of a top electrode of the capacitor, in at least one example.
  • Figure 19 illustrates a cross-section of structure in Figure 18 following process to form a via electrode on at least a portion of top electrode of capacitor after formation of an insulator layer comprising a hydrogen barrier material, in at least one example.
  • Figure 20A illustrates a cross-section of system comprising a device structure in a memory region and an interconnect structure in a logic region adjacent to the memory region, in at least one example.
  • Figure 20B illustrates a cross-section of system comprising a device structure in a memory region and an interconnect structure in a logic region adjacent to the memory region, in at least one example.
  • Figure 21 illustrates a cross-section of system comprising a device structure in a memory region and an interconnect structure in a logic region adjacent to the memory region, in at least one example.
  • Figure 22A illustrates a cross section of structure comprising a pair of stacked insulator layers above an electrode structure, in at least one example.
  • Figure 22B illustrates a cross-section of structure in Figure 22A, following process to form capacitors, in at least one example.
  • Figure 22C illustrates a cross-section of structure in Figure 22B, following process to form a capacitor above an individual electrode structure, in at least one example.
  • Figure 22D illustrates a cross-section of structure in Figure 22C, following process to form a first dielectric in the memory region, in at least one example.
  • Figure 22E illustrates a cross-section of structure in Figure 22D, following process to deposit a second dielectric on a lower insulator layer in logic region adjacent to the memory region, in at least one example.
  • Figure 22F illustrates a cross-section of structure in Figure 22E, following process to form an etch stop layer and a third dielectric on the etch stop layer, in at least one example.
  • Figure 22G illustrates a cross-section of structure in Figure 22F, following process to form opening above top electrode of capacitor in memory region.
  • Figure 22H illustrates a cross-section of structure in Figure 22G, following process to form via electrode in contact with top electrode.
  • Figure 22I illustrates a cross-section of structure in Figure 22H, following process to form etch second dielectric to form via opening in logic region, in at least one example.
  • Figure 22J illustrates a cross-section of in Figure 22I, following process to form via electrode and metal lines.
  • Figure 23A illustrates a cross-section of structure in Figure 22B, following process to etch and form capacitor, where etching recesses an upper insulator layer, in at least one example.
  • Figure 23B illustrates a cross-section of structure in Figure 23A, following process to laterally recess sidewall of a lower electrode of the capacitor, in at least one example.
  • Figure 23C illustrates a cross-section of structure in Figure 23B, following process to form an encapsulation structure adjacent to the capacitor, in at least one example.
  • Figure 24A illustrates a cross-section of structure in Figure 22B, following process to etch and form a capacitor, where etching recesses an upper insulator layer to form a concaved surface, in at least one example.
  • Figure 24B illustrates a cross-section of structure in Figure 24A, following process to laterally recess sidewall of a lowermost electrode in the capacitor.
  • Figure 24C illustrates a cross-section of structure in Figure 24B, following process to form an encapsulation structure adjacent to the capacitor, in at least one example.
  • Figure 25 illustrates a cross-section of structure in Figure 22C following process to mask and pattern an upper insulator layer laterally adjacent to an electrode structure coupled with a capacitor, in at least one example.
  • Figure 26A illustrates a cross-section of structure in Figure 22B following process to laterally recess electrode, deposit an encapsulation layer, deposit and planarize a first dielectric, followed by process to mask and etch a second dielectric, encapsulation layer, and an insulator layer, in at least one example.
  • Figure 26B illustrates a cross-section of structure in Figure 26A following process to form a second dielectric in an adjacent logic region, in at least one example.
  • Figure 26C illustrates a cross-section of structure in Figure 26B following process to form a via electrode coupled with a top electrode of a capacitor in a memory region, and following process to form a metal line, and electrode in an adjacent logic region.
  • Figure 27A illustrates a cross-section of structure in Figure 22A, where electrode structure is further laterally surrounded by a sacrificial insulator layer, formed above an insulator layer, in at least one example.
  • Figure 27B illustrates a cross-section of structure in Figure 27A following process to form capacitors, in at least one example.
  • Figure 27C illustrates a cross-section of structure in Figure 27B following process to remove the sacrificial insulator layer.
  • Figure 27D illustrates a cross-section of structure in Figure 27C following process to form encapsulation structure in contact with a capacitor, in at least one example.
  • Figure 27E illustrates a cross-section of structure in Figure 27D, following process to form a first dielectric in a memory region, in at least one example.
  • Figure 28 illustrates a cross-section of structure in Figure 27C following process to deposit an encapsulation layer, and deposit and pattern a first dielectric in a memory region, in at least one example.
  • Figure 29A illustrates a cross-section of structure in Figure 22A following process to pattern an upper insulator layer in a multi-layer insulator stack, in at least one example.
  • Figure 29B illustrates a cross-section of structure in Figure 29A, following process to form a portion of a multi-layer stack to form a capacitor, in at least one example.
  • Figure 29C illustrates a cross-section of structure in Figure 29B following process to pattern the multi-layer stack and form capacitors, in at least one example.
  • Figure 30A illustrates a cross-section of structure in Figure 27A following process to pattern a portion of multi-layer stack prior to forming capacitors, in at least one example.
  • Figure 30B illustrates a cross-section of structure in Figure 30A, following process to form capacitors, in at least one example.
  • Figure 30C illustrates a cross-section of structure in Figure 30B following process to remove a sacrificial layer from above an upper insulator layer in the multi-layer stack, in at least one example.
  • Figure 31 illustrates a computing architecture with a coherent cache or memory- side buffer chiplet that includes a memory controller, wherein the coherent cache or memory- side buffer chiplet is coupled to an accelerator, a processor, and a memory, in accordance with some examples.
  • Figure 32 illustrates an architecture of the coherent cache or memory-side buffer chiplet with multiple controllers and multiple cache banks, in accordance with some examples.
  • Figure 33 illustrates an apparatus comprising memory and corresponding logic, wherein the memory comprises ferroelectric (FE) memory bit-cells, in accordance with some examples.
  • Figure 34 illustrates a high-level architecture of an artificial intelligence (AI) machine comprising a compute die positioned on top of a memory die, in accordance with some examples.
  • Figure 35 illustrates a 3-input majority gate using non-linear input capacitors, in accordance with some examples. Docket No.: KP12P064US-PCT
  • Figure 36 illustrates a complex logic gate implemented using a 5-input majority gate, in accordance with some examples.
  • At least one example describes capacitors with encapsulation structures integrated with transistors. While at least one example is described with reference to FeRAM or paraelectric RAM, capacitive structures formed herein can be used for any application where a capacitor is desired. In at least one example, capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.
  • capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.
  • Coupled and “connected,” along with their derivatives, may be used to describe functional or structural relationships between components. These terms are not intended as synonyms for each other. Rather, in particular examples, “connected” may be Docket No.: KP12P064US-PCT used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. “Coupled” may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical, electrical, or magnetic contact with each other, and/or that two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship).
  • adjacent here generally refers to a position of a thing being next to (e.g., immediately next to or close to with one or more things between them) or adjoining another thing (e.g., abutting it).
  • signal may refer to current signal, voltage signal, magnetic signal, or data/clock signal.
  • device may generally refer to an apparatus according to context of usage of that term. For example, a device may refer to a stack of layers or structures, a single structure or layer, a connection of various structures having active and/or passive elements, etc.
  • a device is a three-dimensional structure with a plane along x-y direction and a height along z direction of an x-y-z Cartesian coordinate system.
  • plane of device may also be plane of an apparatus which comprises the device.
  • terms “substantially equal,” “about equal,” and “approximately equal” mean that there is no more than incidental variation between two things so described. Such variation is typically no more than +/-10% of a predetermined target value.
  • “left,” “right,” “front,” “back,” “top,” “bottom,” “over,” “under,” and similar terms are used for descriptive purposes and not necessarily for describing permanent relative positions.
  • terms “over,” “under,” “front side,” “back side,” “top,” “bottom,” “over,” “under,” and “on” as used herein refer to a relative position of one Docket No.: KP12P064US-PCT component, structure, or material with respect to other referenced components, structures, or materials within a device, where such physical relationships are noteworthy. These terms are employed herein for descriptive purposes only and predominantly within context of a device z-axis and therefore may be relative to an orientation of a device. Hence, a first material “over” a second material in context of a figure provided herein may also be “under” the second material if device is oriented upside-down relative to context of figure provided. Similar distinctions are to be made in context of component assemblies.
  • between may be employed in context of z-axis, x-axis or y-axis of a device.
  • a material that is between two other materials may be in contact with one or both of those materials.
  • a material that is between two or other materials may be separated from both of other two materials by one or more intervening materials.
  • a material “between” two other materials may therefore be in contact with either of other two materials.
  • a material “between” two other materials may be coupled to other two materials through an intervening material.
  • a device that is between two other devices may be directly connected to one or both of those devices.
  • a device that is between two other devices may be separated from both of other two devices by one or more intervening devices.
  • Capacitors with a wide variety of materials have been implemented for memory (random-access memory or RAM) applications.
  • Perovskite materials have been implemented in capacitors for high density FeRAM applications owing to their low power consumption and high on/off ratio.
  • Perovskite FeRAM devices may be useful over other forms of memory, such as magnetic tunnel junction (MTJ)-based devices, due to relatively low number of layers within a FeRAM device compared to MTJ-based devices.
  • MTJ magnetic tunnel junction
  • a typical FeRAM device may be fully operational with three layers, where a ferroelectric dielectric is contained between two electrode layers.
  • Electrode layers within FeRAM device may also include Perovskite materials to enable lattice matching and reduction in electrical resistance.
  • FeRAM capacitors including lead-free Perovskite materials
  • hydrogen can cause reduction when it reacts with one or more materials of a FeRAM capacitor, such as electrodes or ferroelectric material itself.
  • Docket No.: KP12P064US-PCT FeRAM capacitors can lose their polarization hysteresis characteristics as a result of hydrogen reduction.
  • sources of hydrogen may arise from anneal operations carried out to eliminate dangling bonds and may be unavoidable.
  • a multi-layer stack including at least 3 layers may be deposited for fabricating capacitors.
  • the deposition process can utilize high temperatures to achieve desired crystallinity.
  • patterning multi-layer stack to fabricate memory devices can roughen and damage sidewalls of memory devices causing charge leakage and memory loss during operation.
  • annealing memory devices can be useful.
  • annealing temperatures can exceed 1100 degrees Celsius depending on materials within multi-layer stack and annealing methods utilized.
  • annealing may be performed before or after stack patterning.
  • multi-layer stack can be patterned into capacitors.
  • capacitor devices have a planar structure where individual layers are sequentially layered, one on top of another, and patterned into cylindrical (circular or elliptical) or rectangular shapes.
  • solutions against hydrogen diffusion include forming an encapsulation layer that includes an insulating material, such as silicon nitride to protect capacitor sidewalls and top surfaces.
  • encapsulation layers can provide protection against hydrogen and oxygen diffusion into capacitor.
  • contact or via electrode may be formed at a top of FeRAM device by piercing through insulating barrier layer and exposing one or more top electrode materials.
  • barrier layer itself may be further surrounded by additional insulating material such as an interlayer dielectric (ILD).
  • ILD materials such as silicon oxide or silicon oxide doped with carbon in general may not act as a hydrogen diffusion barrier and are less useful when in contact with one or more layers of memory device.
  • an encapsulation layer comprising materials other than silicon nitride can be deposited to protect sidewalls of capacitors and can offer enhanced flexibility in material choices. Flexibility in material choices can be important when integration schemes can include operations where one layer is removed selectively to two or more exposed layers.
  • capacitors are coupled with a conductive electrode, a via, or a conductive interconnect from above and below. While the presence of encapsulation layer above the capacitor can be useful, further encapsulating at least a portion of a lower surface Docket No.: KP12P064US-PCT of the capacitor can be useful to prevent diffusion of hydrogen along interfaces between adjacent layers.
  • the encapsulation layer can further extend under a portion of the bottom electrode that is not in contact with a conductive electrode, via or a conductive interconnect. In at least one example, when at least a portion of encapsulation layer is contact with a lower surface of a lower electrode, a substantially full encapsulation may be accomplished.
  • substantially full encapsulation can create a hermetic seal.
  • a capacitor can include a bottom electrode structure comprising two conductive layers, a work function layer and a sacrificial conductor.
  • the sacrificial conductor can be recessed relative to the work function layer, such portions of the encapsulation layer can be present under the work function layer.
  • the sacrificial conductor can have a thickness that is dictated by electrical and physical considerations.
  • sacrificial conductor can have a thickness that is governed by conductivity of the sacrificial conductor and by deposition of a minimum thickness of encapsulation layer to be sufficiently hermetic.
  • the sacrificial conductor can have a minimum thickness that is equal to two times a minimum thickness of the encapsulation layer.
  • the capacitor comprises a single bottom electrode, instead of a bottom electrode structure, to avoid lattice mismatch during deposition or to enable a smoother single conductive film, prior to deposition of a dielectric layer of the capacitor.
  • a conductive electrode, a via, or a conductive interconnect that is in contact with the bottom electrode of the capacitor can be raised relative to an insulator laterally adjacent to it.
  • an uppermost surface of the conductive electrode, the via, or the conductive interconnect is raised relative to a surrounding insulator, a portion of an encapsulation layer can be inserted under the bottom electrode structure of the capacitor.
  • the uppermost surface can be raised by an amount useful to deposit the encapsulation layer.
  • the uppermost surface can be raised by a minimum height that is equal to two times a thickness of the encapsulation layer.
  • hydrogen can also diffuse from layers below a bottom electrode structure of the capacitor, such as through the conductive electrode, via or conductive interconnect.
  • the conductive electrode, the via or the conductive interconnect can be laterally surrounded by an etch stop layer that includes a hydrogen barrier material.
  • the etch stop layer includes silicon and nitrogen, or silicon, nitrogen, and carbon.
  • the liner comprises a material that is same or substantially same as the encapsulation layer, where both the encapsulation layer and the liner comprise materials that are different from the material of the etch stop layer.
  • the conductive electrode, via or conductive interconnect can include a conductive hydrogen barrier material.
  • FIG. 1A is an illustration of a cross-section of a device structure 100A.
  • device structure 100A comprises a capacitor 102 comprising a bottom electrode structure 104, dielectric 106, and top electrode 108 on dielectric 106.
  • Device structure 100A is further coupled with electrode structure 116.
  • bottom electrode structure 104 further comprises electrode 110 and electrode 112 on electrode 110.
  • electrode 110 comprises a lateral thickness WE1
  • electrode 112 comprises a lateral thickness W E2 , where lateral thickness W E2 is greater than lateral thickness WE1.
  • WE1 is at least 5 nm less than WE2.
  • a greater lateral thickness W E2 compared to lateral thickness W E1 is useful for encapsulating bottom electrode structure 104. [00129] It is useful to protect sidewalls, top, and bottom surfaces of capacitor 102 from reacting with hydrogen.
  • solutions against hydrogen diffusion include implementing an insulating barrier layer such as encapsulation structure 114 to protect sidewalls, top surface, and bottom surface of capacitor 102.
  • encapsulation structure 114 comprises one of: silicon nitride, carbon doped silicon nitride, Al x O y , HfO x , ZrO x , TaO x , TiO x , AlSiO x , HfSiO x , or TaSiO x , where ‘x’ and ‘y’ are integers (the integers may be the same or distinct).
  • encapsulation structure 114 can include a metal and nitrogen such as, but not limited to, AlN, ZrN, or HfN. In other examples, encapsulation structure 114 can include a metal, and both Si and O, such as AlSiOx, HfSiO x , or TaSiOx where ‘x’ is an integer. [00130] In at least one example, encapsulation structure 114 comprises portion 114A on a sidewall 110A of electrode 110 and adjacent to lowermost surface 112A.
  • encapsulation structure 114 further comprises portion 114B adjacent to a sidewall 112B of electrode 112, where portion 114A and portion 114B are contiguous. In at least one example, portion 114B is further adjacent to sidewall 106A and sidewall 108A. Encapsulation structure 114 is contiguous from top electrode 108 to electrode 110. [00131] Electrode 110 has a vertical thickness TE1, that is orthogonal to the lateral thickness W E1 . In at least one example, vertical thickness T E1 may be tuned depending on material of electrode 110, electrical conductivity of electrode 110, and to an extent, on a minimum lateral thickness TEC of encapsulation structure 114.
  • a minimum lateral thickness of encapsulation structure 114 can be at least 1 nm for a contiguous film that has no pores or defects that can allow hydrogen to diffuse into capacitor 102.
  • TEC can vary from top of top electrode 108 to bottom of electrode 110 and can depend on shape of capacitor 102 (for example, taper in sidewall).
  • shape of sidewall 102A of capacitor 102 is influenced by profile of individual sidewalls such as sidewall 108A, sidewall 106A, and sidewall 112B.
  • outer sidewall 114C of encapsulation structure 114 can be substantially vertical, with a curved top portion, as shown.
  • outer sidewall 114C of encapsulation structure 114 can be gradually tapered.
  • shape of portion 114A relative to sidewall 110A can vary along the z-direction, depending on vertical thickness TE1.
  • shape of portion 114A can depend on lateral thickness T ECM of portion 114A.
  • lateral thickness TEC of portion 114A can vary along the z-direction. Variation in lateral thickness T ECM of portion 114A along the z-direction can depend on various factors such as vertical thickness TE1, lateral thickness TEC, and on whether encapsulation structure 114 is etched.
  • variation in lateral thickness T ECM of portion 114A can be attributed to relative thickness between vertical thickness TE1 and half of a difference between WE2 and WE1 (or ⁇ W).
  • electrode 110 and electrode 112 are substantially symmetric above a vertical axis.
  • ⁇ W can be at least 2.0 nm or, sidewall 112B extends away from sidewall 110A by 2.0 nm.
  • ⁇ W is less than vertical thickness TE1 (as shown), and lateral thickness TEC of encapsulation structure 114 is less than half of vertical thickness TE1, and encapsulation structure 114 includes cavity 115.
  • lateral thickness TEC of encapsulation structure 114 is at least a quarter of vertical thickness TE1.
  • shape and size of cavity can vary with lateral thickness TECM, and with ⁇ W.
  • ⁇ W is greater than vertical thickness TE1
  • lateral thickness TEC of Docket No.: KP12P064US-PCT encapsulation structure 114 is less than half of vertical thickness TE1, as shown in device structure 100B of Figure 1B.
  • cavity 115 within portion 114A is more elongated compared to cavity 115 in Figure 1A.
  • cavity 115 can be reduced or eliminated entirely when lateral thickness TEC of encapsulation structure 114 approaches at least half of vertical thickness T E1 , as shown in device structure 100C of Figure 1C.
  • encapsulation structure 114 within portion 114A is merged as indicated by seams (dashed lines 117).
  • portion 114A comprises an outer sidewall 114D that is substantially co-linear with sidewall 114C.
  • lateral thickness TECM of portion 114A is substantially uniform along vertical thickness TE1 of electrode 110.
  • electrode structure 116 is laterally surrounded by etch stop layer 118.
  • electrode structure 116 is at a same level as 118//.
  • surface 116B is at least co-planar or substantially co-planar with surface 118A.
  • surface 118A can be recessed below surface 116B.
  • etch stop layer 118 includes one Si, Ni, and O, or Si and Ni, or Si Ni, and C, or Si, Ni, O, and C.
  • electrode structure 116 includes a material that is different from material of encapsulation structure 114. In at least one example, electrode structure 116 may also act as an oxygen diffusion barrier.
  • portion of electrode structure 116 may be in contact with encapsulation structure 114.
  • W ES is less than W E1 , and uppermost surface of electrode structure 116 is not in contact with portion 114A.
  • W ES is greater than W E1 (as indicated by dashed lines 123) and uppermost surface of electrode structure 116 is in contact with portion 114A.
  • electrode structure 116 includes a conductive hydrogen barrier 120 and a conductive fill 122.
  • conductive hydrogen barrier 120 and etch stop layer 118 form a dual hydrogen barrier below device structure 100A.
  • conductive hydrogen barrier 120 includes a material that is amorphous. In at least one example, amorphous materials lack defined grain boundaries that facilitate hydrogen diffusion and are thus useful.
  • Examples of conductive hydrogen barrier 120 include one of: TiAlN with >30 atomic percent AlN, TaN with >30 atomic percent N, TiSiN with >20 atomic percent SiN, Ta carbide (TaC), Ti carbide (TiC), tungsten carbide (WC), tungsten nitride (WN), carbonitrides of Ta, Ti, W, i.e., TaCN, TiCN, WCN, titanium monoxide (TiO), titanium oxide Ti 2 O, tungsten oxide (WO 3 ), tin oxide (SnO 2 ), indium tin oxide (ITO), iridium Docket No.: KP12P064US-PCT oxide, indium gallium zinc oxide (IGZO), zinc oxide, or METGLAS series of alloys, e.g., Fe 40 Ni 40
  • conductive hydrogen barrier 120 has a thickness of at least 2.0 nm.
  • conductive fill 122 may include a material such as tantalum, titanium, ruthenium, tungsten, molybdenum, or copper.
  • electrode structure 116 may not include a material such as copper to prevent sputtering of the copper during fabrication of the device structure 100A.
  • top electrode 108 is a conductive metal oxide that includes one of the conducting perovskite metallic oxides exemplified by: La-Sr-CoO 3 , SrRuO3, La-Sr-MnO3, YBa2Cu3O7, Bi2Sr2CaCu2O2, LaNiO3, and ReO3.
  • electrode 112 is a conductive metal oxide that includes one of the conducting perovskite metallic oxides exemplified by: La-Sr-CoO3, SrRuO3, La-Sr-MnO3, YBa2Cu3O7, Bi 2 Sr 2 CaCu 2 O 2 , LaNiO 3 , and ReO 3 .
  • top electrode 108 and electrode 112 include a same material. In at least one example, top electrode 108 and electrode 112 are asymmetric or comprise materials having different work functions.
  • dielectric 106 is of form ABO3, where A and B are two cations of different sizes and O is Oxygen.
  • A includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na; and “B” includes one of Ti, Mn, Fe, Ta, or Nb.
  • dielectric 106 can be doped, e.g., by one or more elements from lanthanide series of periodic table, or one or more elements of 3d, 4d, 5d, 6d, 4f, or 5f series of periodic table.
  • perovskites can be suitably doped to achieve a spontaneous distortion in a range of 0.3% to 2%.
  • concentration of these substitutes is such that it achieves spontaneous distortion in range of 0.3% to 2%.
  • lead-based Perovskite material includes lead zirconium titanate (PZT) or PZT with a first doping material, wherein doping material is one of La or Nb.
  • non-Pb perovskites can also be doped, e.g., by La or Lanthanides.
  • Non-Pb perovskite material can include one or more of La, Sr, Co, Cr, K, Nb, Na, Sr, Ru, Y, Fe, Ba, Hf, Zr, Cu, Ta, Bi, Ca, Ti, or Ni.
  • non-Pb Perovskite material includes one of: BaTiO 3 , KNbO 3 , or NaTaO 3 .
  • dielectric 106 includes a low voltage ferroelectric material.
  • Low voltage FE materials can be of form ABB'O 3 , where “A” includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na; Docket No.: KP12P064US-PCT “B” includes one of Mn, Fe, Ta, or Nb; and “B'” includes one of: Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, or Zn.
  • dielectric 106 has the form AA'BO3
  • A includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na
  • B includes one of Mn, Fe, Ta, or Nb
  • A' includes one of Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, or Lu.
  • A' comprises a valency of site A, but different ferroelectric polarizability from A.
  • dielectric 106 includes bismuth ferrite (BFO) with a second doping material, wherein the second doping material is one of lanthanum, elements from lanthanide series of a periodic table, or elements of 3d, 4d, 5d, 6d, 4f, or 5f series of periodic table.
  • BFO is doped with Mn or Sc, wherein Mn or Sc achieve a spontaneous distortion in BFO in a range of 0.3% to 2%.
  • dielectric 106 includes a relaxor ferroelectric material.
  • relaxor ferroelectric material is a BaTiO3 (BTO) based relaxor which includes one of: BaTiO3-Bi(Zn1/2Ti1/2)O3 (BTO-BZT), BaTiO3-BiScO3 (BTO-BS), BiScO3, Ba (1-x) Sr x TiO3 (BST), BaTiO3-Pb(Mg1/3Nb2/3)O3 (BTO-PMN), BaTi (1-x) Zr x O3 (BTZ), BaTiO3- Pb(Zn1/3Nb2/3)O3 (BTO-PZN), or BaTiO3-Pb(Sc1/2Nb1/2)O3 (BTO-PSN).
  • BTO BaTiO3 based relaxor which includes one of: BaTiO3-Bi(Zn1/2Ti1/2)O3 (BTO-BZT), BaTiO3-BiScO3 (BTO-BS), BiScO
  • relaxor ferroelectric material is a PZT based relaxor which includes one of: PZT-Pb(Mg1/3Nb2/3)O3 (PZT-PMN), PZT-Pb(Ni1/3Nb2/3)O3 (PZT- PNN), PZT-Pb(Zn1/3Nb2/3)O3 (PZT-PZN), PZT-Pb(Sc1/2Nb1/2)O3 (PZT-PSN), PZT- Pb(Fe1/2Nb1/2)O3 (PZT-PFN), PZT- PbxLa1-x(ZryTi1-y)O3 (PZT-PLZT), where 0 ⁇ x ⁇ 1 and where 0 ⁇ y ⁇ 1, or PZT-PbTi (1-x) Mn (x) O3 (PZT-PTM), where 0 ⁇ x ⁇ 1.
  • PZT-PbT-PMN PZT-Pb(
  • relaxor ferroelectric material is a SrBi2Ta2O9, (SBT) based relaxor which includes one of: paraelectric SBT-SrBi2[Nb (1-x) Ta (x) ]2O9 (SBT-SBNT), where 0 ⁇ x ⁇ 1, SBT doped with transition metals such as Mn, Fe, or Co; SBT doped with rare earth ions such as La, Ce, or Nd; or SBT doped with alkaline earth metals with Ba or Ca.
  • SBT-SBNT paraelectric SBT-SrBi2[Nb (1-x) Ta (x) ]2O9
  • relaxor ferroelectric material is based on lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or Barium titanium-barium strontium titanium (BT- BST).
  • PMN lead magnesium niobate
  • PMN-PT lead magnesium niobate-lead titanate
  • BT-BZNT barium titanium-bismuth zinc niobium tantalum
  • BT- BST Barium titanium-barium strontium titanium
  • dielectric 106 includes hexagonal ferroelectrics of a type h-RMnO 3 , where R is a rare earth element which includes one of: cerium (Ce), dysprosium Docket No.: KP12P064US-PCT (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y); hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides, or their alloyed oxides.
  • R is a rare earth element which includes one of: cerium (Ce), dysprosium Docket
  • dielectric 106 includes a hexagonal ferroelectric which includes one of: YMnO3 or LuFeO 3 .
  • dielectric 106 includes hafnium oxide of form Hf (1-x) E x O y , where 'x' and ‘y’ are fractions (the fractions can be equal or distinct) and where E includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y.
  • dielectric 106 includes Al (1-x) Sc x N, Ga (1-x) Sc x N, Al (1- x)Y(x)N where ‘x’ and ‘y’ are respective compositional fractions or Al(a)Mg(b)Nb(c)N, where a, b, and c are respective compositional fractions.
  • dielectric 106 includes one of: LiNbO3, LiTaO3, LiTaO2F2, or Sr( ⁇ )Ba(1-x)Nb2O6 where 0.32 ⁇ x ⁇ 0.8, or KSr 2 Nb 5 O 15 .
  • dielectric 106 comprises multiple layers, for example, alternating layers of [Bi 2 O 2 ]2+, and pseudo-perovskite blocks (Bi 4 Ti 3 O 12 and related Aurivillius phases), with perovskite layers that are ‘n’ octahedral layers.
  • examples of multiple layers include improper ferroelectric material.
  • An improper ferroelectric is a ferroelectric where primary order parameter is an order mechanism such as strain or buckling of atomic order.
  • improper ferroelectric material includes an epitaxial bilayer stack including one of: [barium titanate/strontium titanate]n or [lanthanum aluminate/ strontium titanate]n, wherein ‘n’ represents a number of bilayers, and wherein ‘n’ is between 1 and 100.
  • dielectric 106 includes LuFeO3 class of materials or super lattice of ferroelectric and paraelectric materials.
  • f-orbital materials e.g., lanthanides
  • dielectric 106 includes a paraelectric material.
  • paraelectric material is a BaTiO3 (BTO) based paraelectric which includes one of: BaTiO3-Bi(Zn1/2Ti1/2)O3 (BTO-BZT), BaTiO3-BiScO3 (BTO-BS): BiScO3, Ba 1-x Sr x TiO3 (BST), BaTiO3-Pb(Mg1/3Nb2/3)O3 (BTO-PMN), BaTi1-xZrxO3 (BTZ), BaTiO3- Pb(Zn1/3Nb2/3)O3 (BTO-PZN), BaTiO3-Pb(Sc1/2Nb1/2)O3 (BTO-PSN).
  • BTO BaTiO3
  • BTO-BS BaTiO3 based paraelectric which includes one of: BaTiO3-Bi(Zn1/2Ti1/2)O3 (BTO-BZT), BaTiO3-BiScO3 (BTO-BS)
  • paraelectric material is a PZT based paraelectric which includes one of: PZT-Pb(Mg1/3Nb2/3)O3 (PZT-PMN), PZT-Pb(Ni1/3Nb2/3)O3 (PZT-PNN), PZT-Pb(Zn1/3Nb2/3)O3 (PZT-PZN), PZT-Pb(Sc1/2Nb1/2)O3 (PZT-PSN), PZT-Pb(Fe1/2Nb1/2)O3 (PZT-PFN), PZT- Pb x La 1-x (Zr y Ti 1-y )O 3 (PZT-PLZT), where 0 ⁇ x ⁇ 1 and where 0 ⁇ y ⁇ 1, or PZT-PbTi(1-x)Mn(x)O3 (PZT-PTM), where 0 ⁇
  • paraelectric material is a SrBi2Ta2O9 (SBT) based paraelectric which includes one of: SBT-SrBi2[Nb(1-x)Ta(x)]2O9 (SBT-SBNT), where 0 ⁇ x ⁇ 1, SBT doped with transition metals such as Mn, Fe, Co; SBT doped with rare earth ions such as La, Ce, or Nd; or SBT doped with alkaline earth metals with Ba or Ca.
  • room temperature paraelectric materials include: SrTiO3, BaxSryTiO3, HfZrO2, or Hf-Si-O.
  • dielectric 106 includes an anti-ferroelectric material.
  • antiferroelectric material may include one of: an antiferroelectric material comprising one of: HfSiO2 doped with >30% Si or >30% Zr; HfZrO2 doped with >30% Si or >30% Zr; ZrO 2 or NaNbO 3 ; NaNbO 3 , PbZrO 3 , or PbZrO 3 doped with >5% K; a first solid solution including one of: PbTiO3, SrTiO3, PbHfO3, PbHfO3, Pb(Lu0.5Nb0.5)O3, Pb(Lu 0.5 Nb 0.5 )O 3 , Pb(Yb 0.5 Nb 0.5 )O 3 , AgNbO 3 or NaNbO 3 ; or a second solid solution including PbTiO3 and one of: SrTiO3, PbHfO3,
  • Figure 1D is an illustration of a cross-section of device structure 100D that has one or more properties of device structure 100A, such as capacitor 102 and electrode structure 116.
  • device structure 100D further comprises encapsulation structure 124, where 124 has one or more features such as, structure and material of encapsulation structure 114, ( Figure 1A).
  • encapsulation structure 124 comprises portion 124A adjacent to sidewall 110A and lowermost surface 112A, portion 124A adjacent to sidewall 102A of capacitor 102, where portion 124A comprises an outer sidewall 124C.
  • portions 124A and 124B have features of portions 114A and 114B ( Figure 1A).
  • encapsulation structure 124 further comprises portion 124D that extends laterally on etch stop layer 118. In at least one example, portion 124D laterally extends beyond outer sidewall 124C. In at least one example, portion 124D is contiguous with portion 124A. [00157] In at least one example, portion 124D has vertical thickness T ECV , where vertical thickness TECV can be the same as lateral thickness TEC of portion 124B. In at least one example, top surface 124E of portion 124B can be flat, as shown. A top surface 124E that is Docket No.: KP12P064US-PCT substantially planar may be indicative of a process operation utilized, such as for example a planarization process.
  • encapsulation structure 124 further includes portion 124F that is contiguous with portion 124B, where portion 124F is on a top surface of top electrode 108 and on top surface of portion 124B.
  • portion 124F has a vertical thickness TECV that is same or substantially same as vertical thickness TECV of portion 124D, lateral thickness T EC of portion 124B, or lateral thickness T ECM of portion 124A.
  • encapsulation structure 124 fully encapsulates capacitor 102.
  • device structure 100C can also include features of encapsulation structure 124 described in Figure 1D.
  • Figure 1E is an illustration of a cross- section of device structure 100E where, encapsulation structure 124 further comprises portion 124D that extends laterally on encapsulation structure 124.
  • portion 124D has a thickness TEC that is substantially the same as lateral thickness TEC of portion 124B.
  • top portion of encapsulation structure 124 has top surface 124E that is flat, as shown. A flat surface may be indicative of a process operation utilized, such as a planarization process.
  • encapsulation structure 124 further includes portion 124F that is contiguous with portion 124B, where portion 124F is on a top surface of top electrode 108.
  • portion 124F has a thickness TECF that is same or substantially same as lateral thickness T EC of portion 124B, and vertical thickness of portion 124D. In at least one example, portion 124F has a thickness TECF that is less than lateral thickness T EC of portion 124B, and less than vertical thickness T EC of portion 124D.
  • Figure 1F is an illustration of a cross-section of device structure 100F where electrode 112 ( Figure 1A) is replaced by a bilayer electrode 130, in at least one example. In at least one example, bilayer electrode 130 comprises electrode 131 and electrode 132 on electrode 131.
  • portion 114A of encapsulation structure 114 is in contact with a lowermost surface 131A of electrode 131.
  • portion 114B is adjacent to sidewall 131B and sidewall 132B.
  • electrode 131 comprises one of: Ir, Pt, Ru, IrOx, PtOx, RuOx, where ‘x’ is an integer, or conductive oxide metals that have self-limiting oxidation.
  • electrode 132 can include one of: La-Sr-CoO 3 , SrRuO 3 , La-Sr-MnO 3 , YBa2Cu3O7, Bi2Sr2CaCu2O2, LaNiO3, and ReO3.
  • electrode 110 includes one of: niobium, chromium, molybdenum, tantalum, tungsten, rhenium, titanium, nitrogen doped variants of niobium, chromium, molybdenum, tantalum, tungsten, rhenium, Docket No.: KP12P064US-PCT titanium, AlN doped variants and SiN doped variants having electrically conductive properties.
  • FIG. 1G is an illustration of a cross-section of device structure 100G where electrode 110 ( Figure 1A) is replaced by a bilayer electrode 140, in at least one example.
  • bilayer electrode 140 includes electrode 141 and electrode 142 on electrode 141.
  • bilayer electrode 140 is laterally surrounded by encapsulation structure 114.
  • portion 114A is in contact with sidewall 141B and sidewall 142B.
  • electrode 141 includes one of Ta, Ti, W, Cr, Nb, Mo, nitrogen doped variants, AlN doped variants, or doped variants having electrically conductive properties.
  • electrode 141 includes one of: Ir, Pt, Ru, IrOx, PtOx, RuOx, where ‘x’ is an integer, or conductive oxide metals that have self-limiting oxidation.
  • Figure 2A is an illustration of a cross-section of device structure 200A.
  • device structure 200A includes features of device structure 100A such as capacitor 102, encapsulation structure 114, and electrode structure 116.
  • device structure 200A further comprises liner 202 between etch stop layer 118 and electrode structure 116.
  • liner 202 comprises one of: silicon nitride, carbon doped silicon nitride, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx, or TaSiOx, where ‘x’ and ‘y’ are integers (where the integers can be same or distinct).
  • liner 202 comprises a same material as encapsulation structure 114, but different from material of etch stop layer 118. Inclusion of liner 202 provides flexibility in choice of material for etch stop layer 118 and liner 202, as will be discussed further below.
  • liner 202 can be in contact with at least a portion of encapsulation structure 114.
  • electrode 110 is confined within a planar cross-sectional area (on X-Y plane) or plan view perimeter of electrode structure 116.
  • WES is less than WES1 along the X-direction.
  • liner 202 is in contact with encapsulation structure 114, such as is shown.
  • liner 202 combined with encapsulation structure 114 form a diffusion barrier against hydrogen penetration.
  • encapsulation structure 114 extends on an uppermost surface of liner 202.
  • liner 202 has a planar top surface. In at least one example, liner 202 can have a tapered portion away from sidewall 116A (as indicated by dashed lines 203). A tapered portion is indicative of a process operation utilized to obtain liner 202. In at Docket No.: KP12P064US-PCT least one example, liner 202 can be implemented in device structure 100A and device structure 100C described in association with Figures 1A and 1C. [00167]
  • Figure 2B is an illustration of a cross-section of device structure 200B, that includes a plurality of capacitors 204. In at least one example, plurality of capacitors 204 include capacitor 206A and capacitor 206B.
  • capacitor 206A and capacitor 206B include features of capacitor 102 ( Figure 1A).
  • device structure 200B further includes encapsulation structure 124 that extends continuously between capacitor 206A and capacitor 206B.
  • capacitor 206A and capacitor 206B are separated by a minimum of 20 nm.
  • encapsulation structure 124 can also include portion 124F on top electrode 108.
  • top surface 124E of encapsulation structure 124 are coplanar or substantially coplanar with uppermost surface 108B.
  • Figure 3A is an illustration of a cross-section of device structure 300A, that includes spacer 302 between encapsulation structure 304 and sidewall 102A.
  • spacer 302 can be useful to protect dielectric 106.
  • spacer 302 can includes a material of encapsulation structure 114.
  • spacer 302 substantially follows a contour of sidewall 102A.
  • spacer 302 comprises sidewall 302A that is substantially vertical and sidewall 302B that is tapered.
  • spacer 302 has a lateral thickness T I that decreases from base of electrode 112 to top of top electrode 108.
  • lateral thickness TI of spacer 302 reaches a maximum value adjacent to lowermost surface 112A. In at least one example, when sidewall 102A is tapered, lateral thickness TI of spacer 302 can reach a maximum value adjacent to uppermost surface 108B. In at least one example, lowermost surface 302C of spacer 302 can extend below lowermost surface 112A as indicated by dashed lines 305. [00169] In at least one example, device structure 300A further comprises encapsulation structure 304. In at least one example, encapsulation structure 304 includes features such as portions of structure and material of encapsulation structure 114 ( Figure 1A).
  • encapsulation structure 304 comprises portion 304A and contiguous portion 304B under lowermost surface 112A.
  • portion 304A is adjacent to sidewall 302B of spacer 302 and portion 304B of encapsulation structure 304 is adjacent to sidewall 110A.
  • portion 304B is also in contact with lowermost surface 302C and in contact with portion of lowermost surface 112A.
  • portion 304B has Docket No.: KP12P064US-PCT one or more features of portion 114A as described in association with Figure 1A.
  • portion 304B comprises a minimum lateral thickness T MS that is less than half of vertical thickness TE1.
  • cavity 307 can extend under spacer 302.
  • portion 304B comprises a minimum lateral thickness T MS that is at least equal to half of vertical thickness TE1
  • size of cavity 307 can be reduced or eliminated.
  • sidewall 304C of encapsulation structure 304 may have a curvature that matches with curvature of sidewall 302B.
  • sidewall 302A is substantially tapered
  • sidewall 302B and sidewall 304C may be substantially vertical depending on lateral thickness T I and lateral thickness T M1 .
  • encapsulation structure 304 can include a material of spacer 302.
  • encapsulation structure 304 can include a material that is different from material of spacer 302.
  • Figure 3B is an illustration of a cross-section of device structure 300B, where portion 304B does not include a cavity 307 ( Figure 3A) and where different portions of encapsulation structure 304 can have different thicknesses.
  • portion 304A has a lateral thickness TM1 as measured from sidewall 302B, and portion 304A has a vertical thickness T ECV as measured from lowermost surface 112A to a mid-point of T E1 .
  • vertical thickness TECV can be greater than or less than lateral thickness T M1.
  • FIG. 4A is an illustration of a cross-section of device structure 400A.
  • device structure 400A includes features of device structure 100A, such as electrode 112, dielectric 106, and top electrode 108.
  • electrode 112, dielectric 106, and top electrode 108 are components of capacitor 402.
  • device structure 400A further comprises encapsulation structure 404.
  • encapsulation structure 404 comprises portion 404A where portion 404A is on sidewall 108A, on sidewall 106A, and on sidewall 112B.
  • encapsulation structure 404 further comprises portion 404B, where portion 404B is adjacent to at least a portion of a sidewall 116A and extends from uppermost surface 118A to lowermost surface 112A.
  • at least a lower portion of electrode structure 116 is laterally surrounded by etch stop layer 118.
  • uppermost surface 116B of electrode structure 116 is above uppermost surface 118A of etch stop layer 118.
  • sidewall 112B extends laterally beyond sidewall 116A.
  • a cavity bounded by sidewall 116A, lowermost surface 112A, and uppermost Docket No.: KP12P064US-PCT surface 118A is filled by portion 404B of encapsulation structure 404.
  • portion 404A and portion 404B are contiguous.
  • electrode 112 comprises a lateral thickness WE2
  • electrode structure 116 comprises a lateral thickness W ES where W E2 is greater than W ES .
  • WES is at least 5 nm less than WE2.
  • lowermost surface 112A is vertically separated from uppermost surface 118A of etch stop layer 118 by spacing T ES .
  • shape of portion 404B relative to sidewall 116A can vary along the z- direction.
  • lateral thickness TEC1 of portion 404B can vary along the z-direction, depending on spacing T ES on lateral thickness T EC of portion 404A and on whether encapsulation structure 404 is etched.
  • variation in lateral thickness T EC1 can depend on relative thickness between spacing T ES and half the difference between WE2 and WE1 or ⁇ W.
  • ⁇ W can be at least 2.0 nm.
  • electrode 112 and electrode structure 116 are substantially symmetric above a vertical axis.
  • sidewall 112B extends away from sidewall 116A by 2.0 nm.
  • portion 404B fills a space spanned between electrode 112 and uppermost surface 118A, such as is shown. In at least one example, spacing TES is sufficiently large for portion 404B to not fill space spanned by uppermost surface 118A and lowermost surface 112A.
  • portion 404B comprises features of portion 114A ( Figure 1A).
  • shape of portion 404A can change along the z-direction.
  • shape of portion 404A can depend on the shape of sidewall 402A of capacitor 402. In at least one example, curvature of outer sidewall 404C follows a contour of sidewall 402A. In at least one example, outer sidewall 404C of encapsulation structure 404 is substantially vertical, where sidewall 402A is substantially vertical, as shown. In at least one example, outer sidewall 404C can be tapered or curved. In at least one example, encapsulation structure 404 includes a material of encapsulation structure 114 ( Figure 1A).
  • Figure 4B is an illustration of a cross-section of device structure 400B where encapsulation structure 404 further comprises portion 404D that extends laterally on etch stop layer 118.
  • Portion 404D comprises a vertical thickness TEC2.
  • vertical thickness T EC2 and/or lateral thickness T EC can be independent of spacing T ES .
  • vertical thickness TEC2 can be substantially same as spacing TES.
  • T EC2 can be greater than or less than spacing T ES .
  • top surface 404E of portion 404A can be flat, as shown.
  • a flat surface may be indicative of a process operation utilized, such as a planarization process.
  • encapsulation structure 404 further includes portion 404F that is contiguous with portion 404A, where portion 404F is on a top surface of top electrode 108 and on top surface 404E.
  • Portion 404F has a vertical thickness TEC3.
  • vertical thickness TEC3 can be same or substantially same as vertical thickness TEC2 of portion 404D and lateral thickness T EC of portion 114B.
  • vertical thickness TEC3 can be less than vertical thickness TEC2 of portion 404D and lateral thickness TEC of portion 114B.
  • Figure 4C is an illustration of a cross-section of device structure 400C, where electrode structure 116 is laterally surrounded by liner 406, in at least one example.
  • liner 406 has one or more properties of liner 202 ( Figure 2A).
  • liner 406 comprises one of: silicon nitride, carbon doped silicon nitride, Al x O y , HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx, or TaSiOx.
  • liner 406 extends from level of a lowermost surface 116C to uppermost surface 116B and is in contact with lowermost surface 112A.
  • liner 406 is directly between sidewall 116A and portion 404B. In at least one example, liner 406 is also directly between sidewall 116A and etch stop layer 118. In at least one example, liner 406 comprises a same material as encapsulation structure 404 but is different from material of etch stop layer 118. Inclusion of liner 202 provides flexibility in choice of material for etch stop layer 118. In at least one example, where liner 406 is present, etch stop layer can include a material that includes oxygen. Liner 406 has a width WL. In at least one example, width WL can be less than spacing between sidewall 116A and sidewall 402A.
  • implementing liner 406 reduces lateral thickness TEC1. In at least one example, implementing liner 406 can increase ⁇ W. In at least one example, liner 406 may be implemented in device structure 300A ( Figure 3A), device structure 300B ( Figure 3B), or device structure 400B ( Figure 4B). In at least one embodiment, outer sidewall 408C is substantially vertical. In at least one embodiment, profile of outer sidewall 408C can be dependent on profile of sidewall 112B, sidewall 106A and sidewall 108A. [00179] Figure 4D illustrates a cross-section of device structure 400D.
  • device structure 400D includes one or more properties of device structure 400A Docket No.: KP12P064US-PCT illustrated in Figure 4A.Referring collectively to Figures 4A and 4D, in at least one example, device structure 400D includes encapsulation structure 408 adjacent to capacitor 402 and electrode structure 116. In at least one example, encapsulation structure 408 includes features and material of encapsulation structure 404. [00180] In at least one example, spacing TES is greater compared to spacing TES in structure 400A. In at least one example, spacing T ES is greater than a lateral thickness T ECM of portion 408A or lateral thickness TEC of portion 408B.
  • lateral thickness TECM of portion 408A varies with spacing TES.
  • lateral thickness T ECM is at least a quarter of spacing T ES adjacent to a portion of sidewall 116A.
  • portion 408A may include a cavity.
  • portion 408A when lateral thickness T EC or T ECM is at least a quarter of spacing T ES , portion 408A includes cavity 409.
  • Figure 4E is an illustration of a cross-section of device structure 400E, that includes a plurality of capacitors 410.
  • plurality of capacitors 410 include capacitor 412A and capacitor 412B.
  • capacitor 412A and capacitor 412B include features of capacitor 402 ( Figure 4A). In at least one example, capacitor 412A and capacitor 412B are separated by a minimum of 20 nm.
  • device structure 400E further includes encapsulation structure 404 that extends continuously between capacitor 412A and capacitor 412B. In at least one example, where encapsulation structure 124 extends continuously between capacitor 412A and capacitor 412B, encapsulation structure 404 includes portion 404D on top electrode 108. In at least one example, top surface 404E of encapsulation structure 404 are coplanar or substantially coplanar with uppermost surface 108B.
  • encapsulation structure 404 can include curved portions (indicated by dashed lines 411) adjacent to electrode 112.
  • Figure 5 is a flow diagram for method 500 to fabricate a device structure such as device structure 100A ( Figure 1A), in at least one example.
  • method 500 begins at operation 510 with forming of a transistor above a substrate.
  • method 500 continues at operation 520 with formation of an electrode structure above transistor, where the electrode structure is electrically coupled with the transistor.
  • method 500 continues at operation 530 with formation of a material layer stack, including a non-linear polar material, on the electrode structure.
  • method 500 continues at operation 540 by recessing a lower layer relative to an upper layer within a bottom electrode structure of the capacitor.
  • Docket No.: KP12P064US-PCT method 500 ends at operation 550 by forming a spacer adjacent to the bottom electrode structure, where the spacer is in contact with a lowermost surface of the upper layer.
  • Figure 6A illustrates a cross-section of structure 600A.
  • structure 600 is a cross sectional illustration of fin 601, formed on substrate 602.
  • mask 603 is formed on substrate 602.
  • mask 603 includes a dielectric material.
  • mask 603 may be formed by a lithographic pattern on dielectric material.
  • a plasma etch process is utilized to etch material of substrate 602 to form fin 601.
  • fin 601 may be substantially vertical as is shown.
  • substrate 602 includes silicon, silicon germanium, germanium, or a suitable material that can be utilized to pattern and dope to form source and drain structures applicable for a transistor.
  • Figure 6B illustrates an isometric view of structure 600B.
  • structure 600B is an isometric illustration of structure 600A in Figure 6A, following process to form dielectric 604 adjacent to a portion of fin 601.
  • dielectric 604 is blanket deposited on mask 603 (not shown), on sidewalls of fin 601, and on substrate 602.
  • dielectric 604 is planarized post deposition.
  • planarization process includes a chemical mechanical planarization process (CMP).
  • CMP process removes mask 603 from above fin 601.
  • dielectric 604 is then recessed to obtain a desired height of fin 601.
  • Dielectric 604 can provide electrical isolation for portions of a gate electrode to be formed.
  • a profile of dielectric 604 that is recessed relative to uppermost surface 601A of fin 601, is shown in enhanced cross sectional illustration 606. [00185]
  • Figure 6C illustrates an isometric view of structure 600C.
  • structure 600C is an isometric illustration of structure 600B in Figure 6B, following formation of dummy gate 605 on fin 601, in at least one example.
  • dummy gate dielectric layer 607 is deposited on fin 601 and on dielectric 604.
  • dummy gate dielectric layer 607 is grown by a plasma enhanced chemical vapor deposition (PECVD) process, chemical vapor deposition (CVD) or an atomic layer deposition (ALD) process.
  • PECVD plasma enhanced chemical vapor deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • dummy gate dielectric layer 607 includes a layer of silicon dioxide adjacent to fin 601. [00186]
  • a dummy gate material is blanket deposited on dummy gate dielectric layer 607.
  • dummy gate material includes a chemical vapor deposition process to deposit a material such as polysilicon, amorphous silicon, or silicon germanium.
  • deposition process can take place at temperatures Docket No.: KP12P064US-PCT of approximately 600 degrees Celsius or less.
  • a planarization process may be performed to planarize dummy gate material after deposition.
  • a mask material is deposited on dummy gate material.
  • mask material includes a silicon nitride or a silicon oxynitride.
  • mask material is patterned by a lithographic process and etched by a plasma etch process to form hardmask 608.
  • hardmask 608 is subsequently utilized to etch dummy gate material to form dummy gate 605.
  • dummy gate dielectric layer 607 is removed from surfaces of fin 601 after formation of dummy gate 605.
  • spacer 610 is formed on sidewalls of dummy gate 605.
  • an encapsulation layer is blanket deposited on fin 601, and on dummy gate 605.
  • encapsulation layer is then etched to form spacer 610 on sidewalls of dummy gate 605.
  • encapsulation layer may be removed from sidewalls of fin 601 by a masking and etching process so that spacer 610 is substantially formed on sidewalls of dummy gate 605 and on a portion of sidewalls of fin 601 adjacent to dummy gate 605.
  • Figure 6D illustrates an isometric view of structure 600D.
  • structure 600D is an isometric illustration of structure 600C in Figure 6C, following process to form source structure 612 and drain structure 614, in at least one example.
  • portions of fin 601 are etched and removed.
  • shape of fin 601 is indicated by dashed lines 609.
  • an epitaxial growth process is utilized to selectively grow source structure 612 and drain structure 614 on fin 601 as shown.
  • source structure 612 and drain structure 614 are grown to have faceted sidewalls by an epitaxial growth process.
  • dopants may be implanted during epitaxial growth process or implanted at a later operation.
  • spacer 610 and hardmask 608 can prevent epitaxial growth from taking place on dummy gate 605.
  • sidewall 605A of dummy gate 605 is exposed for illustrative purposes only, spacer 610 encapsulates all sidewalls 605A of dummy gate 605.
  • epitaxial growth process may be carried out at temperatures between 200 degrees Celsius and 700 degrees Celsius to grow source structure 612 and drain structure 614 doped with Si, amorphous silicon or SiGe. Docket No.: KP12P064US-PCT [00191]
  • Figure 6E illustrates an isometric view of structure 600E.
  • structure 600E is an isometric illustration of structure 600D in Figure 6D, following process to remove hardmask 608, dummy gate 605, and dummy gate dielectric layer 607, in at least one example.
  • dielectric 616 is blanket deposited on source structure 612 and drain structure 614, on dielectric 604, spacer 610 and hardmask 608 ( Figure 6D).
  • dielectric 616 can include silicon and one or more of oxygen, nitrogen, or carbon, and may be deposited by a chemical vapor deposition (CVD), or a plasma enhanced chemical vapor deposition (PECVD) process.
  • dielectric 616 is planarized by a CMP process.
  • CMP process may remove hardmask 608.
  • an etch process may be utilized to remove hardmask 608, and portions of dummy gate 605 after partial competition of CMP process.
  • a wet chemical process is utilized to selectively remove dummy gate 605, as well as dummy gate dielectric layer 607 selective to dielectric 604, spacer 610, fin 601, and dielectric 616.
  • process of removing dummy gate 605 forms an opening 611.
  • Figure 6F illustrates an isometric view of transistor 618.
  • transistor 618 is an isometric illustration of structure 600E in Figure 6E, following process to form gate structure 620 in opening 611, in accordance with at least one example.
  • a gate dielectric layer 622 is blanket deposited after a high temperature process to grow source structure 612 and drain structure 614.
  • an atomic deposition process is utilized to deposit a gate dielectric layer 622 on fin (not shown), on sidewalls of spacer 610 and on dielectric 604 in opening 611.
  • a PMOS or an NMOS material is deposited on gate dielectric layer 622 to form gate electrode 624.
  • deposition process may include a CVD, a physical vapor deposition (PVD), or an atomic layer deposition (ALD) method.
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • a planarization process can be performed to remove excess material of gate electrode 624 and gate dielectric layer 622 from above spacer 610 and dielectric 616.
  • FIG. 7A illustrates a cross-section of structure 700A.
  • structure 700A is a cross sectional illustration, through line A-A’, of transistor 618 in Figure 6F following process to deposit dielectric 702 on dielectric 616.
  • dielectric 702 is blanket deposited on dielectric 616, on spacer 610 and on gate structure 620.
  • dielectric 702 includes a material that is same or Docket No.: KP12P064US-PCT substantially same as material of dielectric 616.
  • dielectric 702 may be deposited by a PECVD or a CVD process. The illustration depicts a portion of gate electrode 624 on fin 601. In at least one example, lines 703 denote extensions of gate electrode 624 on dielectric 604, below dashed line 705.
  • drain contact 704A on drain structure 614, gate contact 704B on gate electrode 624 and source contact 704C on source structure 612 can be formed.
  • a mask is formed on dielectric 702, and an opening is formed in dielectric 702 and in dielectric 616 to expose drain structure 614.
  • a conductive material is deposited into opening and on uppermost surface 702A of dielectric 702.
  • conductive material is removed via planarization from uppermost surface 702A to fabricate drain contact 704A.
  • gate contact 704B can be formed on gate structure 620.
  • gate contact 704B can be formed by etching dielectric 702 and depositing materials that are same or substantially same as materials of drain contact 704A.
  • source contact 704C can be formed on source structure 612.
  • source contact 704C can be formed by etching dielectric 702 and depositing materials that are same or substantially same as materials of drain contact 704A.
  • transistor 618 is formed above substrate 602. In at least one example, a plurality of transistors that are identical or substantially identical to transistor 618 can be formed on a same level or plane of transistor 618 within substrate 602. [00196]
  • Figure 7B illustrates a cross-section of structure 700B.
  • structure 700A is a cross sectional illustration of structure 700A in Figure 7A following process to form conductive interconnect 708, in at least one example.
  • dielectric 706 is deposited on dielectric 616 and on drain contact 704A.
  • dielectric 706 includes a material that is same or substantially same as material of dielectric 706.
  • dielectric 706 is deposited by a PVD, PECVD, or an ALD deposition process.
  • opening is formed in dielectric 706 and one or more conductive materials are deposited into opening 707.
  • conductive materials are deposited in opening 707 and on drain contact 704A.
  • conductive material is planarized to form conductive interconnect 708. In at least one example, there can be more than one intervening layer between dielectric 616 and dielectric 706 and corresponding one or more conductive electrodes.
  • Figure 8 illustrates a cross-section of structure 800.
  • structure 800 is a cross sectional illustration of structure 700B in Figure 7B following Docket No.: KP12P064US-PCT process to deposit etch stop layer 118.
  • etch stop layer 118 is blanket deposited on dielectric 706 and on conductive interconnect 708. In at least one example, etch stop layer 118 is deposited on dielectric 706 by a PECVD, a PVD, or a CVD process.
  • etch stop layer 118 may be etched by a plasma etch process to form an opening above conductive interconnect 708 to form an electrode structure.
  • an opening can be formed in portion 803 (dashed lines).
  • an opening can be formed above gate structure 620.
  • Figure 9A illustrates a cross-section of structure 900A.
  • Structure 900A is an enhanced cross-sectional illustration of portion 803 in Figure 8 following process to etch opening 902 in etch stop layer 118, in at least one example.
  • mask 903 includes a photoresist material and is formed on etch stop layer 118 by a lithographic process.
  • etch stop layer 118 may be etched by a plasma etch process through an opening in mask 903.
  • opening 902 has a lateral thickness W O .
  • Lateral thickness WO may be narrower, equal to, or wider than lateral thickness WCI.
  • lateral thickness W O is greater than lateral thickness W CI .
  • shape of opening 902 may be circular or rectangular, and conductive interconnect 708 may be discrete islands or a line straddling a drain structure.
  • Figure 9B illustrates a cross-section of structure 900B.
  • Structure 900B illustrates a cross-section of structure 900A in Figure 9A, following process to deposit a liner layer 904 in opening 902, in at least one example.
  • liner layer 904 includes a material of liner 202 ( Figure 2A).
  • liner layer 904 can be blanket deposited in opening 902 on conductive interconnect 708, on sidewall 118B, and on top surface of etch stop layer 118.
  • liner layer 904 is also blanket deposited on a portion of dielectric 706, when lateral thickness WO is greater than lateral thickness W CI .
  • liner layer 904 is blanket deposited to a thickness W I.
  • Figure 9C illustrates a cross-section of structure 900C.
  • Structure 900C illustrates a cross-section of structure 900B in Figure 9B, following process to etch liner layer 904.
  • a plasma etch process is utilized to etch liner layer 904 to form liner 202.
  • the plasma etch process removes liner layer 904 from above etch stop layer 118 and from uppermost surface of conductive interconnect 708 to form liner 202 adjacent to sidewall 118B.
  • upper portions of liner 202 may be curved.
  • Figure 9D illustrates a cross-section of structure 900D.
  • Structure 900D illustrates a cross-section of structure 900C in Figure 9C, following process to deposit conductive Docket No.: KP12P064US-PCT hydrogen barrier layer 906 in opening 902 conductive fill material 908 on conductive hydrogen barrier layer 906.
  • a conductive hydrogen barrier layer 906 is blanket deposited in opening 902 on conductive interconnect 708, on liner 202, and on uppermost surface 118A of etch stop layer 118.
  • a conductive fill material 908 is blanket deposited on conductive hydrogen barrier layer 906.
  • conductive hydrogen barrier layer 906 includes a material of conductive hydrogen barrier 120
  • conductive fill material 908 includes a material of conductive fill 122 ( Figure 1A).
  • conductive hydrogen barrier layer 906 and conductive fill material 908 can be deposited by a CVD, a PVD, or an ALD process.
  • conductive hydrogen barrier layer 906 and conductive fill material 908 follow a contour of liner 202.
  • Figure 9E illustrates a cross-section of structure 900E.
  • Structure 900E illustrates a cross-section of structure 900D in Figure 9D following process to form electrode structure 116, in at least one example.
  • planarization process forms conductive hydrogen barrier 120 and conductive fill 122.
  • planarization also confines conductive fill material 908 within conductive hydrogen barrier layer 906.
  • planarization forms uppermost surface 118A and 116B that are co-planar or substantially co- planar.
  • upper portions of conductive hydrogen barrier 120 and conductive fill 122 comprise a contour or shape of upper portion of liner 202.
  • upper portions of conductive hydrogen barrier 120 and conductive fill 122 are curved away from a central axis of electrode structure 116.
  • planarization process recesses uppermost surface116B and uppermost surface 118A to level of dashed lines 909.
  • substantially curved portions of liner 202, conductive hydrogen barrier 120 and conductive fill 122 are removed.
  • surface 202A can also be made co-planar or substantially co-planar with uppermost surface 118A and uppermost surface 116B.
  • electrode structure 116 can be formed without a liner.
  • Figures 10B-10C are cross-sectional illustrations depicting a method to fabricate an Docket No.: KP12P064US-PCT electrode structure having a conductive hydrogen barrier above a fill metal, in accordance with at least one example.
  • Figure 10A illustrates a cross-section of structure 1000A.
  • Structure 1000A illustrates a cross-section of structure 900D in Figure 9A following process to remove mask 903 and deposit conductive fill material 1004 within opening 902, in at least one example.
  • conductive fill material 1004 is blanket deposited into opening 902, on conductive interconnect 708 and on sidewalls and uppermost surface 118A.
  • conductive fill material 1004 includes tantalum, titanium, ruthenium, or tungsten, and can be deposited by a PVD, a PECVD, or an ALD process. In at least one example, conductive fill material 1004 includes copper and can be deposited by an electroplating process.
  • Figure 10B illustrates a cross-section of structure 1000B. Structure 1000B illustrates a cross-section of structure 1000A in Figure 10A following process to recess conductive fill material 1004 within a portion of opening 902, in at least one example.
  • portions of conductive fill material 1004 deposited on uppermost surface 118A, in a prior operation, are removed by a planarization process.
  • planarization process forms conductive fill 1006 within opening 902.
  • surface 1006A of conductive fill 1006 is substantially planar with uppermost surface 118A.
  • surface 1006A can be dished as indicated by dashed lines 1007.
  • a wet chemical process is utilized to recess conductive fill 1006 below uppermost surface 118A.
  • level of recess of conductive fill 1006 relative to uppermost surface 118A will depend on thickness T L and on a desired thickness of a conductive hydrogen barrier to be formed.
  • conductive fill 1006 is recessed relative to uppermost surface 118A by up to half of thickness T L .
  • surface 1006A may be dished after recessing as indicated by dashed lines 1007.
  • Figure 10C illustrates a cross-section of structure 1000C. Structure 1000C illustrates a cross-section of structure 1000B in Figure 10B following process to form conductive hydrogen barrier 1008 on conductive fill 1006.
  • a conductive hydrogen barrier layer is blanket deposited on conductive fill 1006 and on etch stop layer 118.
  • a planarization process may be utilized to remove excess conductive hydrogen barrier material layer deposited on uppermost surface 118A.
  • planarization process includes a chemical mechanical polish (CMP) Docket No.: KP12P064US-PCT process.
  • CMP process forms conductive hydrogen barrier 1008.
  • conductive hydrogen barrier 1008 and conductive fill 1006 are components of electrode structure 1010.
  • Figures 11A-11B are cross-sectional illustrations depicting a method to fabricate an electrode structure having a conductive hydrogen barrier above a fill metal, in accordance with at least one example.
  • Figure 11A illustrates a cross-section of structure 1100A.
  • structure 1100A illustrates a cross-section of structure 900A in Figure 9A following process to deposit conductive hydrogen barrier layer 906 in opening 902, and conductive fill material 908 on conductive hydrogen barrier layer 906.
  • materials and processes utilized to deposit hydrogen barrier layer and conductive fill material 908 have been described in association with Figure 9D.
  • Figure 11B illustrates a cross-section of structure 1100B.
  • Structure 1100B illustrates a cross-section of structure 1100A in Figure 11A following process to form electrode structure 116, in at least one example.
  • excess portions of conductive fill material 908, and conductive hydrogen barrier layer 906 above etch stop layer 118 are removed by a planarization process.
  • planarization process forms conductive hydrogen barrier 120 and conductive fill 122.
  • planarization confines conductive fill 122 within conductive hydrogen barrier layer 906.
  • planarization forms uppermost surface 118A and uppermost surface 116B that are co-planar or substantially co- planar.
  • Figure 12A illustrates a cross-section of structure 1200A.
  • structure 1200A illustrates a cross-section of structure 1100B in Figure 11A following process to form a multi-layer stack 1201 on electrode structure 116 and on etch stop layer 118.
  • number of layers can depend on a type of memory device to be fabricated.
  • process to form multi-layer stack 1201 includes blanket deposition of at least three material layers, to form capacitor 402 ( Figure 4A).
  • process to form multi-layer stack 1201 includes blanket deposition of at least four layers to form capacitor 102 ( Figure 1A).
  • multi-layer stack 1201 includes deposition of layers for a ferroelectric memory device.
  • multi-layer stack 1201 includes deposition of layers for a paraelectric memory device. Docket No.: KP12P064US-PCT [00215]
  • individual layers of multi-layer stack 1201 are deposited in situ, i.e., without breaking vacuum.
  • Multi-layer stack 1201 may be deposited by an ALD, a PECVD, a CVD, a PVD process, or a combination thereof.
  • ALD process may be performed at a process temperature between 160 degrees Celsius and 400 degrees Celsius
  • PVD process may be performed at a process temperature between 23 degrees Celsius (room temperature) and 400 degrees Celsius
  • CVD process may be performed at a process temperature between 160 degrees Celsius and 800 degrees Celsius.
  • formation of multi-layer stack 1201 begins by blanket deposition of layer 1202 on etch stop layer 118 and on electrode structure 116.
  • deposition temperatures will depend on material of dielectric layer 1204.
  • dielectric layer 1204 comprises a conductive material that is designed to be laterally etched selectively to layers above, after formation of a capacitor.
  • lateral etching mechanism include plasma etching, wet chemical etching, or a combination thereof.
  • layer 1202 includes a material of electrode 110 ( Figure 1A).
  • layer 1202 includes, for example, a refractory or a nitride of a refractory metal that is useful for relative ease of patterning. In at least one example, layer 1202 has a thickness T1 that ranges between 5 nm and 30 nm. [00217] In at least one example, conductive layer 1203 is blanket deposited on layer 1202. In at least one example, conductive layer 1203 includes a conductive oxide.
  • conductive layer 1203 comprises one of: La (1-x) Sr (x) FeO 3 , La (1-x) Sr (x) CoO 3, La (1- x)Ca(x)MnO3, La(1-x)Sr(x)MnO3, Ba(1-x)Sr(x)RuO3, La(1-x)Sr(x)MnO3, wherein 0 ⁇ x ⁇ 1, SrRuO3, Sr 2 RuO 4 , SrMoO 3 , SrCoO 3 , SrCrO 3 , SrFeO 3 , SrVO 3 , CaMoO 3 , SrNbO 3 , LaNiO 3 , YBa2Cu3O7, Bi2Sr2CaCuO8, or CaRuO3.
  • conductive layer 1203 includes Ir, Ir 2 O y , Ru, RuO y , Mo, MoO y , W, or WO y , wherein ‘y’ is an integer.
  • conductive layer 1203 includes hexagonal compounds including one or more of PtCoO2, PdCoO2, delafossite structured hexagonal conductive oxides including Al-doped ZnO, spinels including one or more of Fe 3 O 4 , LiV 2 O 4 or cubic oxides including Indium tin oxide or Sn-doped In2O3.
  • conductive layer 1203 includes a material that is different from material of layer 1202.
  • conductive layer 1203 is deposited to thickness T2 that is suitable for minimizing electrical resistance as well as conducive to etch patterning to form memory devices.
  • conductive layer 1203 has a thickness T2 that Docket No.: KP12P064US-PCT ranges between 3 nm and 30 nm.
  • a thickness T2 of less than 30 nm can be useful to prevent significant tapering of sidewalls formed during patterning process.
  • deposition process is continued with deposition of dielectric layer 1204 on conductive layer 1203.
  • dielectric layer 1204 is blanket deposited on conductive layer 1203.
  • dielectric layer 1204 has a thickness T 3 between (and inclusive of) 1 nm and 30 nm. [00220] In at least one example, dielectric layer 1204 is the same or substantially the same as dielectric 106. [00221] In at least one example, process is continued with blanket deposition of conductive layer 1205 on dielectric layer 1204. In at least one example, conductive layer 1205 includes a conductive oxide.
  • conductive layer 1205 comprises one of: (La,Sr)FeO3, (La,Sr)CoO3, (La,Ca)MnO3, (La,Sr)MnO3, SrRuO3, Sr2RuO4, (Ba,Sr)RuO 3 , SrMoO 3 , (La,Sr)MnO 3 , SrCoO 3 , SrCrO 3 , SrFeO 3 , SrVO 3 , CaMoO 3 , SrNbO 3 , LaNiO3, YBa2Cu3O7, Bi2Sr2CaCuO8, or CaRuO3.
  • conductive layer 1203 includes Ir, Ir 2 O x , Ru, RuO x , Mo, MoO x , W, or WO x .
  • conductive layer 1205 includes a material that is same or substantially same as material of conductive layer 1203. In at least one example, when conductive layer 1203 and conductive layer 1205 include same material, multi-layer stack can be substantially symmetric in device voltage/current characteristics.
  • conductive layer 1205 is deposited to thickness T4. In at least one example, it is useful for conductive layer 1205 to be sufficiently thick for example, 25 nm or more to act as a hardmask during etching and for planarization margin.
  • thickness T4 can be between 3 nm and 50 nm.
  • conductive layer 1205 can have a different thickness than conductive layer 1203.
  • thickness T4 is substantially equal to thickness T2.
  • multi-layer stack 1201 can also include one or more sacrificial layers above conductive layer 1205. Sacrificial layers above conductive layer 1205 can be useful during a patterning process or during planarization process after formation of one or more capacitors.
  • mask 1207 is formed on multi-layer stack 1201. In at least one example, mask 1207 includes a photoresist or a hardmask that has been patterned by a photoresist.
  • mask 1207 can include a conductive material.
  • a conductive material such as Ta, TaN, TiN, or W can be patterned with photoresist and can offer protection against patterning multi-layer stack 1201. Docket No.: KP12P064US-PCT [00224]
  • Figure 12B illustrates a cross-section of structure 1200B.
  • structure 1200B illustrates a cross-section of structure 1200A in Figure 12A following process to pattern multi-layer stack 1201 to form one or more capacitors.
  • one capacitor, such as capacitor 1208, is shown.
  • a plasma etch process is utilized.
  • plasma etch process may include a discharge produced by a magnetic enhanced reactive ion etching mechanism, an electron cyclotron resonance discharge, or an inductively coupled plasma discharge.
  • plasma etch process etches conductive layer 1205 to form top electrode 108.
  • dielectric layer 1204 is etched to form a patterned dielectric layer or dielectric 106
  • conductive layer 1203 is etched to form electrode 112
  • layer 1202 is etched to form electrode 110, where electrode 112 and electrode 110 are collectively referred to as bottom electrode structure 104.
  • process utilized to etch conductive layer to form electrode 112 may be substantially same as etch process utilized to form top electrode 108.
  • sidewall 1208A of capacitor 1208 are substantially vertical with respect to uppermost surface 118A, as shown.
  • sidewalls 102A are tapered as indicated by dashed lines 1209.
  • top electrode 108 can have a curved upper surface, as indicated by dashed lines 1211.
  • an over etch can be performed during plasma etch process to expose etch stop layer 118.
  • plasma etch process utilized to form bottom electrode structure 104 may be selective to etch stop layer 118.
  • etch stop layer 118 may be un-etched. In at least one example, plasma etch process utilized to form bottom electrode structure 104 is not selective to etch stop layer 118. In at least one such example, portions of etch stop layer 118 may be recessed, as indicated by dashed lines 1213.
  • capacitor 1208 includes features of capacitor 102 such as top electrode 108, dielectric 106, electrode 112, and electrode 110. In at least one example, a further modification of electrode 110 can render capacitor 102 illustrated in Figure 1A. In at least one example, profile of sidewall 110A can influence shape of encapsulation structure to be formed.
  • the plasma etch process can be tailored to produce sidewall 110A having a substantially vertical profile.
  • a substantially vertical profile can provide a surface to form a substantially contiguous encapsulation layer.
  • Docket No.: KP12P064US-PCT [00229]
  • Figure 12C illustrates a cross-section of structure 1200C.
  • structure 1200C is a cross sectional illustration of structure 1200B in Figure 12B following process to laterally recess sidewall 110A relative to sidewall 112B.
  • a wet chemical etch is utilized to laterally recess sidewall 110A relative to dashed line 1213.
  • the wet chemical etch is selective to top electrode 108, dielectric 106, electrode 112, and etch stop layer 118.
  • sidewall 110A is substantially vertical.
  • sidewall 110A can have a granular structure that is representative of grains comprising electrode 110.
  • sidewall 110A can be concaved outward as indicated by dashed line 1215.
  • electrode 110 includes a material that is same or substantially same as material of the conductive hydrogen barrier 120.
  • wet etch process utilized is timed to prevent conductive hydrogen barrier 120 from being exposed.
  • Electrode 110, conductive hydrogen barrier 120, and conductive fill 122 include materials that can be selectively removed relative to one another, sidewall 116A, or uppermost surface 116B can also be exposed while laterally recessing sidewall 110A.
  • bulk electrical conductivity of electrode 110 may be determined by lateral thickness W E1 and vertical thickness T E1 , in addition to material of electrode 110.
  • Figure 12D illustrates a cross-section of structure 1200D.
  • structure 1200D is a cross sectional illustration of structure 1200C in Figure 12C following process to deposit encapsulation layer 1214.
  • encapsulation layer 1214 is blanket deposited on capacitor 102 and on etch stop layer 118.
  • process utilized to deposit encapsulation layer 1214 depends on material utilized, on the height of capacitor 102, and on the relative spacing between any two adjacent capacitors, such as capacitor 102.
  • the deposition process utilized to deposit encapsulation layer 1214 does not include hydrogen or ammonia containing chemicals to prevent hydrogen exposure to layers within capacitor 102.
  • some materials can be deposited by both a non-hydrogen or an ammonia containing chemicals. However, each deposition process can have different deposition rates and deposition conformality.
  • profile of encapsulation layer 1214 can be influenced by vertical thickness T E1 , lateral thickness W E1 , and by deposited thickness TECL of encapsulation layer 1214.
  • encapsulation layer 1214 is deposited to thickness T ECL that is less than half a vertical thickness TE1.
  • encapsulation layer 1214 is deposited on sidewall 116A, lowermost surface 112A, and on sidewall 102A.
  • cavity 1217 is formed between etch stop layer 118 and electrode 112.
  • an ALD process may be utilized to obtain deposition on lowermost surface 112A and on sidewall 110A.
  • encapsulation layer 1214 when deposited to a thickness of approximately 2 nm, may be sufficient to prevent hydrogen diffusion.
  • cavity 1217 can be substantially eliminated when encapsulation layer 1214 is deposited to thickness TECL that is at least half a vertical thickness T E1 , as indicated by dashed lines 1219.
  • encapsulation layer 1214 can be deposited on etch stop layer 118 to thickness TECL that is equal to or greater than vertical thickness T E1 .
  • encapsulation layer 1214 includes an insulator material.
  • the insulator material include a metal and oxygen, such as, but not limited to AlxOy, HfOx, AlSiOx, ZrOx, or TiOx, where ‘x’ and ‘y’ are integers (the integers may be the same or distinct).
  • encapsulation layer 1214 can include a metal and nitrogen such as, but not limited to, AlN, ZrN, or HfN.
  • encapsulation layer 1214 can include a metal, and both Si and O, such as AlSiOx, HfSiO x , or TaSiOx where ‘is an integer.
  • encapsulation layer 1214 can be deposited by an ALD process to a thickness in the range of 0.5 nm – 10 nm. In some examples, encapsulation layer 1214 may be deposited to a thickness of less than 5 nm.
  • An ALD process can provide a substantially conformal thickness on sidewall 108A and on uppermost surface 108B, as shown. In at least one example, a physical vapor deposition (PVD) process may be utilized.
  • PVD physical vapor deposition
  • Figure 12E illustrates a cross-section of structure 1200E.
  • structure 1200E is a cross sectional illustration of structure 1200D in Figure 12D following process to form encapsulation structure 114. Docket No.: KP12P064US-PCT
  • a plasma etch process is utilized to etch encapsulation layer 1214 from uppermost surface 118A, and from top surface of top electrode 108.
  • portions of etch stop layer 118 may be etched, where etch process can recess uppermost surface 118A relative to lowermost surface of electrode 110.
  • the etch process is substantially anisotropic, forming sidewall 114C that is substantially vertical.
  • the etch process can be isotropic where portion 114B may be formed with tapered sidewalls, and where lateral thickness TEC of 114B decreases from electrode 112 to top electrode 108 (+z-direction).
  • Figures 13A-13E are cross-sectional illustrations depicting a method to fabricate device structure 300A, illustrated in Figure 3A.
  • Figure 13A illustrates a cross-section of structure 1300A.
  • structure 1300A is a cross sectional illustration of structure 1200A in Figure 12A following process to etch conductive layer 1205, dielectric layer 1204, and conductive layer 1203.
  • the method to etch conductive layer 1205, dielectric layer 1204, and conductive layer 1203 and form top electrode 108, dielectric 106, and electrode 112 are described above ( Figure 12B).
  • a plasma etch process utilized is halted after layer 1202 is exposed and structure 1302 is formed.
  • the plasma etch process utilized is halted to form a spacer around top electrode 108, dielectric 106, and electrode 112.
  • FIG. 13B illustrates a cross-section of structure 1300B.
  • structure 1300B is a cross sectional illustration of structure 1300A in Figure 13A following process to form spacer 302 on sidewall 108A, sidewall 106A, and sidewall 112B of structure 1302.
  • an encapsulation layer is blanket deposited on top electrode 108, layer 1202, and sidewall 106A.
  • encapsulation layer includes a material that is same or substantially same as material of spacer 302.
  • the encapsulation layer is etched by a plasma etch process to form spacer 302.
  • an over etch process is utilized to clear the encapsulation layer from above surface 1202A.
  • an over etch process may comprise sufficiently low energy ions that favor isotropic etch, causing erosion of spacer 302 near Docket No.: KP12P064US-PCT vicinity of top electrode 108.
  • spacer 302 may have a portion 302D that extends below lowermost surface 112A. In at least one example, portion 302D can influence a shape of encapsulation structure to be formed.
  • Figure 13C illustrates a cross-section of structure 1300C. In at least one example, structure 1300C is a cross sectional illustration of structure 1300B in Figure 13B following process to form electrode 110.
  • a wet chemical etch process is utilized to recess and etch layer 1202 to form electrode 110.
  • forming electrode 110 completes formation of capacitor 102.
  • wet chemical etch process utilized also laterally etches layer 1202 relative to sidewall 302B of spacer 302.
  • sidewall 110A may be formed with a tapered profile as indicated by dashed lines 1301.
  • a tapered profile can result when wet chemical etchants vertically and laterally etch layer 1202 to create an undercut below spacer 302.
  • the profile of electrode 110 formed can also depend on grain boundaries within layer 1202.
  • etching of layer 1202 can take place along grain boundaries, where the grain sizes may be irregular or regular.
  • the lateral etch rate and vertical etch rate can be substantially same.
  • recess WR of sidewall 110A relative to sidewall 302B can be chosen depending on vertical thickness T E1 .
  • recess WR can be the same or different from vertical thickness TE1.
  • recess W R is substantially the same as vertical thickness T E1 to provide space for conformal deposition of an encapsulation layer in a downstream operation.
  • Figure 13D illustrates a cross-section of structure 1300D.
  • structure 1300D is a cross sectional illustration of structure 1300C in Figure 13C following process to form an encapsulation layer 1304.
  • the material and method utilized to deposit encapsulation layer 1304 can be the same as the material and methods utilized to deposit encapsulation layer 1214 ( Figure 12D).
  • encapsulation layer 1304 includes a same material as spacer 302.
  • encapsulation layer 1304 is conformally deposited on sidewall 302B, sidewall 110A, etch stop layer 118, and on top surface of top electrode 108.
  • an ALD deposition process can be utilized to conformally deposit encapsulation layer 1304.
  • a conformal deposition process is useful when encapsulation layer 1304 is deposited to a thickness that is less than half of vertical thickness T E1 .
  • encapsulation layer 1304 is contiguous and hermetically seals capacitor 102.
  • portion 1304A has one or more features of portion 304B ( Figure 3A).
  • Figure 13E illustrates a cross-section of structure 1300E.
  • structure 1300E is a cross sectional illustration of structure 1300D in Figure 13D following process to form encapsulation structure 304.
  • a plasma etch process is utilized to etch encapsulation layer 1304, selectively to etch stop layer 118 and top electrode 108 to form encapsulation structure 304.
  • the plasma etch process removes portions of encapsulation layer 1304 from uppermost surface 118A and uppermost surface 108B.
  • a combination of plasma etch and wet etch process may be utilized to etch layer 1202 as will be discussed below ( Figures 14A-14B).
  • FIG 14A illustrates a cross-section of structure 1400A.
  • structure 1400A is a cross sectional illustration of structure 1300B in Figure 13B following process to form electrode 110.
  • a plasma etch process is utilized to anisotropically etch layer 1202 to form electrode 110, where sidewall 110A of electrode 110 is substantially aligned with sidewall 302A.
  • spacer 302 acts as a mask while etching electrode 110.
  • the plasma etch process utilized is selective to material of top electrode 108.
  • top electrode 108 may be capped with material that is same or substantially same as layer 1202 prior to etching and forming structure 1302 (Figure 13A). In at least one example, capping with material that is same or substantially same as layer 1202 can help to preserve top electrode 108 during etching of layer 1202.
  • Figure 14B illustrates a cross-section of structure 1400B.
  • structure 1400B is a cross sectional illustration of structure 1400A in Figure 14A following process to recess sidewall 110A under electrode 112.
  • wet chemical etch laterally can recess a surface, such as sidewall 110A, in a lateral direction.
  • etching electrode 110 in one direction can be used to controllably recess sidewall 110A, as indicated by dashed lines 1401A and 1401B.
  • resulting sidewall 110A may be influenced by grains within electrode 110.
  • Docket No.: KP12P064US-PCT [00252]
  • Figure 15A illustrates a cross-section of structure 1500A.
  • structure 1500A is a cross sectional illustration of structure 800 in Figure 8, following process form opening 1503.
  • Transistor 618 ( Figure 8) is not illustrated for clarity.
  • sacrificial layer 1502 is blanket deposited on etch stop layer 118.
  • sacrificial layer 1502 comprises an insulator that includes a material which can be selectively removed relative to etch stop layer 118 and one or more layers in multi-layer stack to be deposited above.
  • sacrificial layer 1502 is blanket deposited on etch stop layer 118 by a PVD, CVD, PECVD, or an ALD process.
  • sacrificial layer 1502 is deposited to a thickness between 2 nm and 30 nm.
  • thickness of sacrificial layer 1502 may be determined by process utilized to form an electrode structure in a downstream operation.
  • mask 1505 is formed on sacrificial layer 1502.
  • mask 1505 includes a photoresist material and is formed on sacrificial layer 1502 by a lithographic process.
  • sacrificial layer 1502 and etch stop layer 118 may be etched by a plasma etch process through an opening in mask 1505 to form opening 1503.
  • opening 1503 exposes conductive interconnect 708.
  • Figure 15B illustrates a cross-section of structure 1500B.
  • structure 1500B is a cross sectional illustration of structure 1500A in Figure 15A following process to form electrode structure 116.
  • method to form electrode structure 116 is similar to method described above ( Figures 11B and 11B).
  • Figure 15C illustrates a cross-section of structure 1500C.
  • structure 1500C is a cross sectional illustration of structure 1500B in Figure 15B following process to deposit multi-layer stack 1506 to form capacitor 402 ( Figure 4A).
  • Conductive interconnect 708 is not illustrated for clarity.
  • conductive layer 1203 is blanket deposited on electrode structure 116 and on sacrificial layer 1502, dielectric layer 1204 is blanket deposited on conductive layer 1203 and conductive layer 1205 is blanket deposited on dielectric layer 1204.
  • materials and methods utilized to deposit conductive layer 1203, dielectric layer 1204, and conductive layer 1205 are described in Figure 12A.
  • Figure 15D illustrates a cross-section of structure 1500D.
  • structure 1500D is a cross sectional illustration of structure 1500C in Figure 15C following process to etch conductive layer 1205, dielectric layer 1204, and conductive layer 1203 to form capacitor 402.
  • a plasma etch process is utilized to etch Docket No.: KP12P064US-PCT conductive layer 1205, dielectric layer 1204, and conductive layer 1203 ( Figure 15C).
  • the plasma etch process is selective to sacrificial layer 1502, with little to no erosion of sacrificial layer 1502.
  • uppermost surface 1502A is not etched.
  • lateral thickness W C of capacitor 402 is greater than lateral thickness WES.
  • sacrificial layer 1502 can be etched after forming capacitor 402, as indicated by dashed lines 1509.
  • an anisotropic etch process is utilized to etch sacrificial layer 1502 to facilitate further removal of sacrificial layer 1502 at a downstream operation.
  • a portion of sacrificial layer 1502 remains under electrode 112 after etching sacrificial layer 1502.
  • Figure 15E illustrates a cross-section of structure 1500E.
  • structure 1500E is a cross sectional illustration of structure 1500D in Figure 15D following process to remove sacrificial layer 1502.
  • portion of sacrificial layer 1502 remaining under electrode 112 is removed by a wet chemical etch, where the wet chemical etch may be selective to top electrode 108, dielectric 106, electrode 112, conductive hydrogen barrier 120, and etch stop layer 118.
  • complete removal of sacrificial layer 1502 forms cavity 1511 between electrode 112, etch stop layer 118, and conductive hydrogen barrier 120.
  • lateral thickness of cavity 1511 depends on size of lateral thickness WC relative to lateral thickness WES, where WC is greater than W ES .
  • Figure 15F illustrates a cross-section of structure 1500F.
  • structure 1500F is a cross sectional illustration of structure 1500E in Figure 15E following process to deposit an encapsulation layer 1510 on capacitor 402, on sidewall 116A, on uppermost surface 118A, and adjacent to sidewall 116A.
  • encapsulation layer 1510 includes a material that is same or substantially same as material of encapsulation layer 1214.
  • method to deposit encapsulation layer 1510 has been described above.
  • encapsulation layer 1510 can be deposited to a thickness that does not produce a cavity under electrode 112.
  • encapsulation layer 1510 can be deposited to a thickness that can produce a cavity, for example, cavity 1217.
  • encapsulation layer 1510 can be etched and removed from above top electrode 108 and from above etch stop layer 118, such as is shown in cross-sectional illustration of structure 1500G in Figure 15G.
  • over etching can reduce lateral thickness TECM of portion 404A and lateral thickness TEC of portion 404B.
  • KP12P064US-PCT [00260]
  • an additional spacer can be formed on sidewall 402A prior to removing sacrificial layer 1502.
  • an additional spacer on sidewall 402A can provide protection to dielectric 106 during removal of sacrificial layer 1502.
  • wet chemical etchants utilized to remove sacrificial layer 1502 can damage some material choices of dielectric 106.
  • Figure 16A illustrates a cross-section of structure 1600A.
  • structure 1600A is a cross sectional illustration of structure 1500D in Figure 15D following process to form encapsulation layer 1602.
  • encapsulation layer 1602 includes a material that is same or substantially same as material of spacer 302 ( Figure 13B).
  • material of encapsulation layer 1602 is chosen to provide hermetic seal to dielectric 106 and be chemically resilient while etching sacrificial layer 1502.
  • encapsulation layer 1602 is blanket deposited on top electrode 108, on sidewall 402A, and on uppermost surface 1502A by an ALD, a PVD process, or a combination thereof.
  • encapsulation layer 1602 comprises a thickness of at least 2 nm to be continuous.
  • Figure 16B illustrates a cross-section of structure 1600B.
  • structure 1600B is a cross sectional illustration of structure 1600A in Figure 16A following process to form spacer 1604.
  • encapsulation layer 1602 ( Figure 16A) is etched by a plasma etch process to form spacer 1604.
  • sidewall 1604A of spacer 1604 is substantially vertical.
  • an over etch process is utilized to remove encapsulation layer 1602 and expose sacrificial layer 1502.
  • sidewall 1604A is tapered, as illustrated.
  • Figure 16C illustrates a cross-section of structure 1600C.
  • structure 1600C is a cross sectional illustration of structure 1600B in Figure 16B following process to etch and remove sacrificial layer 1502.
  • a combination of plasma etch and a wet etch process is utilized to remove sacrificial layer 1502.
  • a wet chemical etch process may be utilized to remove all of sacrificial layer 1502, where the wet chemical process is selective to etch stop layer 118, spacer 1604 and conductive hydrogen barrier 120.
  • the process of removing sacrificial layer 1502 forms cavity between electrode 112, spacer 1604, conductive hydrogen barrier 120, and etch stop layer 118 adjacent to conductive hydrogen barrier 120.
  • size of cavity 1605 depends on thickness of sacrificial layer 1502 removed and on lateral distance (along X-direction) between sidewall 116A and sidewall 1604A.
  • Docket No.: KP12P064US-PCT [00264]
  • Figure 16D illustrates a cross-section of structure 1600D.
  • structure 1600D is a cross sectional illustration of structure 1600C in Figure 16C following process to deposit encapsulation layer 1608.
  • encapsulation layer 1608 is blanket deposited on sidewall 1604A, on top electrode 108, on uppermost surface 118A.
  • encapsulation layer 1608 provides a seal at interface 1609 between spacer 1604 and capacitor 402. In at least one example, when encapsulation layer 1608 is deposited to a thickness that is at least half TES, cavity 1605 is filled.
  • Figure 16E illustrates a cross-section of structure 1600E. In at least one example, structure 1600E is a cross sectional illustration of structure 1600D in Figure 16D following process to etch encapsulation layer 1608 to form structure 1610. In at least one example, encapsulation layer 1608 ( Figure 16D) is removed by a plasma etch process selectively to etch stop layer 118, and top electrode 108.
  • the plasma etch process can expose and remove upper portions of spacer 1604, when encapsulation layer 1608 and structure 1610 include a same or substantially same material.
  • plasma etch process forms portion 1610A adjacent to sidewall 116A, under lowermost surface 1604B of spacer 1604, and lowermost surface 112A.
  • thickness of structure 1610 is such that portion 1610A fills cavity 1605 ( Figure 16C).
  • Figure 17A illustrates a cross-section of structure 1700A.
  • structure 1700A is a cross sectional illustration of structure 1200E in Figure 12E following process to deposit dielectric 1702.
  • dielectric 1702 is blanket deposited on etch stop layer 118 on encapsulation structure 114. In at least one example, when uppermost surface 108B is exposed, dielectric 1702 is also deposited on uppermost surface 108B. In at least one example, to provide a barrier against hydrogen diffusion directly into sidewalls of capacitor 102, dielectric 1702 can include a material that is amorphous, having a high film density (a film density above 90% of theoretical material density or film density), and is electrically insulating. [00267] In an example, a planarization process is performed to remove excess dielectric 1702. In at least one example, planarization process includes a chemical mechanical planarization process (CMP).
  • CMP chemical mechanical planarization process
  • CMP process removes dielectric 1702 and upper portions of encapsulation structure 114. In at least one example, CMP process removes an upper portion of top electrode 108. In at least one example, the CMP process forms planar uppermost surfaces 114E, 1702A, and 108B that are co-planar or substantially co-planar. In at least one example, where encapsulation structure 114 also includes portion Docket No.: KP12P064US-PCT 114F (denoted by dashed lines) above top electrode 108, the planarization process may be utilized to stop on portion 114F or planarize and remove portion 114F.
  • encapsulation structure 404 also includes portion 114G on etch stop layer 118.
  • Figure 17B illustrates a cross-section of structure 1700B.
  • structure 1700B is a cross sectional illustration of structure 1700A in Figure 17A following process to deposit insulator layer 1704 and form via electrode 1706 on a portion of top electrode 108.
  • insulator layer 1704 includes a material that is same or substantially same as etch stop layer 118.
  • insulator layer 1704 includes a material that is same or substantially same as dielectric 1702, where dielectric 1702 includes a material that is amorphous, having a high film density (a film density above 90% of theoretical material density or film density). In at least one such example, insulator layer 1704 includes a material that is different from encapsulation structure 114. In at least one example, an opening is formed in insulator layer 1704 above capacitor 102, where the opening exposes a portion of top electrode 108. In at least one example, a conductive hydrogen barrier layer is blanket deposited in the opening, on sidewalls of insulator layer 1704 and on a portion of top electrode 108.
  • a conductive fill material is blanket deposited on the conductive hydrogen barrier layer.
  • conductive fill material includes copper and may be deposited by an electroplating process.
  • a CMP process removes the conductive fill material and conductive hydrogen barrier material layer from above uppermost surface 1704A.
  • planarization process forms conductive hydrogen barrier 1708 and conductive fill 1710.
  • conductive hydrogen barrier 1708 and the conductive fill 1710 include a material that is same or substantially same as material of conductive hydrogen barrier 120 and conductive fill 122, respectively ( Figure 1A).
  • FIG. 18 illustrates a cross-section of structure 1800.
  • structure 1800 is a cross sectional illustration of structure 1500G in Figure 15G following process to deposit dielectric 1702.
  • dielectric 1702 is blanket deposited on etch stop layer 118, on encapsulation structure 404.
  • dielectric 1702 is also deposited on sidewall 108A.
  • dielectric 1702 when uppermost surface 108B is exposed, dielectric 1702 is also deposited on uppermost surface 108B.
  • dielectric 1702 can include a material that is amorphous, having a high film density (a film density above 90% of theoretical material density or film density) and is electrically insulating.
  • a planarization process is performed to remove excess dielectric 1702.
  • planarization process includes a chemical mechanical planarization process (CMP).
  • CMP process removes dielectric 1702 and upper portions of encapsulation structure 404.
  • CMP process removes an upper portion of top electrode 108.
  • the CMP process forms planar uppermost surfaces 1702A, 108B, and top surface 404E that are co-planar or substantially co-planar.
  • the planarization process may be utilized to stop on portion 404F or planarize and remove portion 404F.
  • encapsulation structure 404 also includes portion 404G on etch stop layer 118.
  • Figure 19 illustrates a cross-section of structure 1900.
  • structure 1900 is a cross sectional illustration of structure 1800 in Figure 18 following process to deposit insulator layer 1704 and form via electrode 1706 on a portion of top electrode 108.
  • insulator layer 1704 includes a material that is same or substantially same as etch stop layer 118.
  • insulator layer 1704 includes a material that is same or substantially same as dielectric 1702, where dielectric 1702 includes a material that is amorphous, having a high film density (a film density above 90% of theoretical material density or film density).
  • insulator layer 1704 includes a material that is different from encapsulation structure 114.
  • an opening is formed in insulator layer 1704 above capacitor 402, where the opening exposes a portion of top electrode 108.
  • a conductive hydrogen barrier layer is blanket deposited in the opening, on sidewalls of insulator layer 1704 and on a portion of top electrode 108.
  • a conductive fill material is blanket deposited on the conductive hydrogen barrier layer.
  • conductive fill material includes copper and may be deposited by an electroplating process.
  • a CMP process removes the conductive fill material and conductive hydrogen barrier material layer from above uppermost surface 1704A. The planarization process forms conductive hydrogen barrier 1708 and conductive fill 1710.
  • conductive hydrogen barrier 1708 and the conductive fill 1710 include a material that is same or substantially same as material of conductive hydrogen barrier 120 and conductive fill 122, respectively ( Figure 1A).
  • insulator layer Docket No.: KP12P064US-PCT 1704, conductive hydrogen barrier 1708, encapsulation structure 114, etch stop layer 118, and conductive hydrogen barrier 120 combine to provide a hermetic seal to capacitor 402.
  • structure 1700B ( Figure 17B) and device structure ( Figure 4A) can be elements of a memory region.
  • the memory region can be integrated a logic region adjacent to the memory region.
  • the logic region can include transistors that are same or different from transistors in the memory region. In at least one example, the transistors in the memory and logic regions can be on a same level.
  • etch stop layer 118 may be replaced by a dual layer barrier.
  • a dual layer barrier may be implemented for a variety of reasons such as to improve yield, provide a barrier against hydrogen, prevent film delamination due to increased thickness in a single film.
  • a dual layer barrier may comprise a lower insulator layer and an upper insulator having a different material from the upper insulator layer.
  • etch stop layer 118 may include silicon, nitrogen and carbon and have a thickness that is sufficient to act as an etch stop layer and advantageously provide high yield in a logic region.
  • etch stop layer 118 comprising silicon, nitrogen and carbon may be deposited to a thickness that relieves tensile stress. Excessive tensile stress can cause film delamination and present yield problems during fabrication.
  • etch stop layer 118 including silicon, nitrogen and carbon may not be adequate to act as a hydrogen diffusion barrier in an adjacent memory region.
  • hydrogen can diffuse into
  • the upper insulator layer comprises a material that can provide a barrier against hydrogen diffusion.
  • FIG. 20A illustrates a cross-section of system 2000A.
  • system 2000A includes device structure 2002 in memory region 2001A, and device structure 2004 in logic region 2001B.
  • device structure 2002 includes one or more elements of structure 1700B illustrated in Figure 17B, such as capacitor 102, encapsulation structure 114, electrode structure 116, conductive interconnect 708, dielectric 1702, and transistor 618.
  • device structure 2002 can include more than 64 device structures, such as structure 1700B in an array. Docket No.: KP12P064US-PCT [00278]
  • Device structure 2002 further includes a barrier structure 2006 between conductive interconnect 708 and capacitor 102, where barrier structure 2006 includes a step height.
  • the step height is at an interface between memory region 2001A and logic region 2001B.
  • the step height can be between 3 nm and 50 nm.
  • barrier structure 2006 can include a plurality of insulator layers.
  • barrier structure 2006 includes two insulator layers, such as insulator layer 2008 and insulator layer 2010.
  • insulator layer 2008 includes a material that is different from material of insulator layer 2010.
  • insulator layer 2008 includes one of: SiN (low H content), Al x O y , HfO x , ZrO x , TaOx, TiOx, AlSiOx, HfSiOx, TaSiOx, SiOx, SiN, SiON, AlzOy, AlN, ZrN, HfN, GaOx, where ‘x’, ‘y’ and ‘z’ are integers (where the integers can be same or distinct).
  • insulator layer 2010 includes one of: SiCN, SiON, SiC, SiN (high hydrogen content).
  • insulator layer 2008 includes a material that is different from material of encapsulation structure 114.
  • electrode structure 116 is embedded within insulator layer 2008 and insulator layer 2010.
  • encapsulation structure 114 is in contact with insulator layer 2008.
  • encapsulation structure 114 has one or more features described above in Figures 1B-1F.
  • electrode structure 116 spans a combined vertical thickness of insulator layer 2008 and insulator layer 2010.
  • logic region 2001B further includes conductive interconnect 2012 in level 2013 and transistor 2014 coupled below insulator layer 2010.
  • logic region 2001B includes via electrode 2016.
  • via electrode 2016 is laterally surrounded by insulator layer 2010 but not insulator layer 2008.
  • via electrode 2016 extends beyond a level of uppermost surface 116B of electrode structure 116.
  • electrode 2016 is further coupled with a metal line 2018, where metal line 2018 is within level 2019, but above electrode 2016.
  • metal line 2018 can extend along the y-direction in the Figure.
  • system 2000A includes a metal line 2020 adjacent to metal line 2018.
  • metal line 2020 may be coupled to a functional device on a plane in front/or behind plane of a plane of Figure 20A.
  • metal line 2020 may be a dummy metal line implemented for patterning fidelity.
  • Docket No.: KP12P064US-PCT [00282]
  • transistor 2014 is identical to transistor 618.
  • transistor 2014 may include features such as multiple fins to increase drive current in logic transistors.
  • conductive interconnect 2012 can be the same size as conductive interconnect 708. In at least one example, conductive interconnect 2012 can be wider than conductive interconnect 708.
  • electrode 2016 includes Cu, Cu/Al/Si compounds, Cu doped with Mn, W, Al, Ta(N), Ti(N), Mo, or Ru.
  • metal line 2018 and metal line 2020 include Cu, Cu/Al/Si compounds, Cu doped with Mn, W, Al, Ta(N), Ti(N), Mo, or Ru.
  • via electrode 2016 is also laterally surrounded by dielectric 2022 above insulator layer 2010.
  • dielectric 2022 can include a same material as dielectric 1702.
  • dielectric 2022 can include a material that has a lower dielectric constant than dielectric 1702.
  • electrode 1706, metal line 2018 and metal line 2020 have a same or substantially same height TM.
  • electrode 1706, metal line 2018, and metal line 2020 are laterally surrounded by dielectric 2024.
  • dielectric 2024 can include a bilayer stack, where a lower layer includes a material of insulator layer 2008, and an upper layer that includes a low K dielectric such as dielectric 2022.
  • Figure 20B illustrates a cross-section of system 2000B.
  • system 2000B includes device structure 2030 in memory region 2001A, and device structure 2004 in logic region 2001B.
  • device structure 2030 includes one or more elements of structure 1700B illustrated in Figure 17B, such as electrode 112, conductive interconnect 708, electrode structure 116, dielectric 1702, and transistor 618.
  • device structure 2030 includes capacitor 2032 and encapsulation layer 2034 adjacent to sidewall 2032A of capacitor 2032.
  • capacitor 2032 includes many features of capacitor 102, such as top electrode 108, dielectric 106, electrode 112, and electrode 110.
  • electrode 110 does not have recessed sidewalls as in capacitor 102.
  • encapsulation layer 2034 includes a same material as encapsulation structure 114. In at least one example, encapsulation layer 2034 is conformal to sidewall 2032A.
  • encapsulation layer 2034 when capacitor 2032 has a substantially vertical profile, encapsulation layer 2034 has a substantially uniform thickness on sidewall 2032A. In at least one example, when sidewall 2032A is tapered then encapsulation layer 2034 can have a variation in thickness along sidewall 2032A. In at least one such example, encapsulation layer 2034 may decrease in lateral thickness from top Docket No.: KP12P064US-PCT electrode 108 to electrode 110. In at least one example, encapsulation layer 2034 is in contact with insulator layer 2008 but not insulator layer 2010. In at least one example, encapsulation layer 2034 extends on insulator layer 2008 to an edge of insulator layer 2008 at interface between memory region 2001A and logic region 2001B.
  • electrode structure 116 comprises lateral thickness TES, where T ES can be greater than or less than lateral thickness W MD of capacitor 2032.
  • system 2000B includes logic region 2001B that includes features of logic region 2001B such as device structure 2004 described in association with Figure 20A.
  • Figure 21 illustrates a cross-section of system 2100.
  • system 2100 includes device structure 2101 in memory region 2001A, and device structure 2101 in logic region 2001B.
  • device structure 2101 includes one or more elements of structure 1900 illustrated in Figure 19, such as capacitor 402, encapsulation structure 404, electrode structure 116, conductive interconnect 708, dielectric 1702, and transistor 618.
  • system 2100 can include an array with more than 64 device structures such as structure 1900.
  • electrode structure 116 is embedded within insulator layer 2008 and insulator layer 2010. In at least one example, electrode structure 116 extends above surface 2008A of insulator layer 2008. In at least one example, encapsulation structure 114 is in contact with insulator layer 2008. In at least one example, encapsulation structure 114 has one or more features described above in Figures 4A, 4B and 4D. In at least one example, encapsulation structure 404 fills a space between surface 2008A and lowermost surface 112A.
  • system 2000B includes logic region 2001B that includes features of logic region 2001B such as device structure 2004 described in association with Figure 20A.
  • Figures 22A-22J illustrate process operations to fabricate system 2000A illustrated in Figure 20A, in at least one example.
  • Figure 22A illustrates a cross section of structure 2200A.
  • process to form 2200A comprises depositing a pair of insulator layers such as insulator layer 2202 and insulator layer 2204.
  • insulator layer 2202 is blanket deposited on dielectric 706, conductive interconnect 708, and conductive interconnect 2012.
  • electrode structure 116 is formed above individual conductive Docket No.: KP12P064US-PCT interconnect 708 in memory region 2201A. In at least one example, an electrode structure is not formed on conductive interconnect 2012 in logic region 2201B. In at least one example, method to form electrode structure 116 is substantially similar to methods described above. In at least one example, openings are formed by etching insulator layer 2202 and insulator layer 2204 through a mask. In at least one example, materials such as those described above ( Figures 10A-11B) are deposited into the openings and planarized. [00293] In at least one example, 2204 may be deposited to a greater thickness than a desired final thickness to anticipate losses during the planarization process.
  • insulator layer 2202 and insulator layer 2204 include a same material as insulator layer 2010 and insulator layer 2008, respectively.
  • Figure 22B illustrates a cross-section of structure 2200B.
  • structure 2200B is a cross sectional illustration of structure 2200A in Figure 22A, following process to form capacitors 2205.
  • capacitors 2205 include features of capacitor 102, such as top electrode 108, dielectric 106, electrode 112, and electrode 110.
  • method to form capacitors 2205 is similar to methods described above in Figures 12A-12C.
  • a multi-layer stack is deposited on insulator layer 2204 and on electrode structure 116.
  • the multi-layer stack is patterned as described above.
  • a further modification of electrode 110 can render capacitor 102 ( Figure 1A).
  • profile of sidewall 110A can dictate shape of encapsulation structure to be formed.
  • the plasma etch process can be tailored to produce sidewall 110A having a substantially vertical profile.
  • a wet etch process can controllably recede sidewall 110A relative to sidewall 112B in a downstream operation.
  • Figure 22C illustrates a cross-section of structure 2200C.
  • structure 2200C is a cross sectional illustration of structure 2200B in Figure 22B, following process to form capacitor 102 above an individual electrode structure 116.
  • method to recede sidewall 110A is described above in Figure 12C.
  • wet chemical etchant utilized to recede sidewall 110A is selective to insulator layer 2204, top electrode 108, dielectric 106 electrode 112, and electrode 110.
  • electrode structure 116 has a lateral thickness that is less than a lateral thickness of electrode 110 after recessing process.
  • electrode structure 116 may be laterally surrounded by a liner layer as discussed above ( Figure 2A). Docket No.: KP12P064US-PCT [00297]
  • encapsulation structure 114 is formed on capacitor 102. In at least one example, encapsulation structure 114 is formed around individual capacitors 102 and does not continuously extend from one capacitor 102 to another capacitor 102.
  • Figure 22D illustrates a cross-section of structure 2200D. In at least one example, structure 2200D is a cross sectional illustration of structure 2200C in Figure 22C, following process to form dielectric in memory region 2201A.
  • dielectric 2206 is blanket deposited on structure 2200C ( Figure 22C) by a PVD, CVD, PECVD, or an ALD process.
  • dielectric 2206 comprises silicon and one or more of carbon or oxygen.
  • dielectric 2206 is planarized. In at least one example, the planarization process removes a portion of top electrode 108 and upper portions of encapsulation structure 114 adjacent to top electrode 108, rendering uppermost surface 114E that is co-planar or substantially co-planar with uppermost surface 108B.
  • mask 2207 is formed on dielectric 2206, and on top electrode 108.
  • a plasma etch process is utilized to etch dielectric 2206 and insulator layer 2204 from logic region 2201B.
  • insulator layer 2204 can be removed selectively with little to no removal of insulator layer 2202.
  • sidewall 2206A of dielectric 2206 and insulator layer insulator layer 2204 are aligned after the etch process.
  • uppermost surface 2202A of insulator layer 2202 may be recessed in logic region 2201B by up to 2nm.
  • mask 2207 may be removed after the etch process.
  • dielectric 2206 is not planarized to expose top electrode 108.
  • a portion of dielectric 2206 remains above top electrode 108, and upper portions of encapsulation structure 114 remain, as illustrated in structure 2200C ( Figure 22C).
  • leaving portions of dielectric 2206 above top electrode 108 can be advantageous because it can be used for protecting top electrode 108 during a second planarization process utilized in a downstream operation.
  • the second planarization process may be implemented after depositing a dielectric in logic region 2201B and in memory region 2201A.
  • Figure 22E illustrates a cross-section of structure 2200E.
  • structure 2200E is a cross sectional illustration of structure 2200D in Figure 22D, following process to deposit dielectric 2208 on insulator layer 2202 in logic region 2201B and in memory region 2201A.
  • dielectric 2208 comprises a same material as dielectric 2206.
  • dielectric 2208 is blanket deposited on dielectric 2206, top Docket No.: KP12P064US-PCT electrode 108, encapsulation structure 114, and on sidewall of insulator layer 2204 in memory region 2201A.
  • dielectric 2208 includes a material that has a lower dielectric constant than dielectric 2206.
  • Figure 22F illustrates a cross-section of structure 2200F.
  • structure 2200F is a cross sectional illustration of structure 2200E in Figure 22E, following process to form etch stop layer 2210 on dielectric 2206, top electrode 108, encapsulation structure 114, and dielectric 2208.
  • a planarization process is performed to remove excess dielectric 2208 from above dielectric 2206.
  • planarization process can stop on top electrode 108 after removing excess dielectric 2208 in memory region 2201A.
  • planarization process forms uppermost surface 2206B and uppermost surface 2208A that are co-planar or substantially co-planar.
  • portions of uppermost surface 2206B may be recessed relative to uppermost surfaces 114E or uppermost surface 108B.
  • planarization process utilized to remove excess dielectric 2208 deposited above dielectric 2206 can be continued.
  • continuing planarization process can also remove excess dielectric 2206.
  • continuing planarization process can also remove portions of top electrode 108 and upper portions of encapsulation structure 114 to render structure illustrated in Figure 22F.
  • uppermost surface 2206B and uppermost surface 2208A can be coplanar or substantially coplanar.
  • etch stop layer 2210 is blanket deposited in memory region 2201A and logic region 2201B by a PVD, CVD, PECVD, or an ALD process. In at least one example, etch stop layer 2210 is deposited to a thickness of at least 5nm. In at least one example, etch stop layer 2210 includes a hydrogen barrier material. In at least one example, etch stop layer 2210 includes a same material as insulator layer 2204. In at least one example, dielectric 2212 is blanket deposited on etch stop layer 2210 by a PVD, CVD, PECVD, or an ALD process. In at least one example, etch stop layer 2210 includes a same material as dielectric 2208.
  • Figure 22G illustrates a cross-section of structure 2200G.
  • structure 2200G is a cross sectional illustration of structure 2200F in Figure 22F, following process to form opening 2213 above top electrode 108.
  • mask 2215 is Docket No.: KP12P064US-PCT formed on dielectric 2212 by a lithographic process.
  • a plasma etch process is utilized to form opening 2213 in dielectric 2212 and in etch stop layer 2210.
  • the plasma etch process exposes uppermost surface 108B.
  • opening 2213 has a lateral thickness that does not expose encapsulation structure 114 to prevent erosion of encapsulation structure 114 along sidewall 108A.
  • Figure 22H illustrates a cross-section of structure 2200H.
  • structure 2200H is a cross sectional illustration of structure 2200G in Figure 22G, following process to form via electrode 2214 in contact with top electrode 108.
  • one or more conductive materials are deposited into opening 2213 and on dielectric 2212.
  • a planarization process is utilized to remove excess one or more conductive materials from above 2212 to isolate the one or more conductive materials to form via electrode 2214.
  • FIG. 22I illustrates a cross-section of structure 2200I.
  • structure 2200I is a cross sectional illustration of structure 2200H in Figure 22H, following process to etch dielectric 2208 to form via opening 2221 within opening 2219 in logic region 2201B.
  • mask 2223 is formed, on dielectric 2212, on electrode 2214, in opening 2217 and in opening 2219, by a lithographic process and includes a photoresist material.
  • mask 2223 has an opening within opening 2219 that is designed to facilitate etching dielectric 2208 to form via opening 2221, as shown.
  • mask 2223 may not include an opening within opening 2217 in the plane of the Figure but may include an opening in a plane that is behind or in front.
  • a plasma etch process is utilized to form via opening 2221 by etching the dielectric 2208 and insulator layer 2202.
  • insulator layer 2202 is utilized as an etch stop.
  • a known thickness of insulator layer 2204 can be advantageous for targeting etch process implemented while exposing conductive interconnect 2012. In at least one example, a known thickness of insulator layer 2204 can enable minimal over etch of insulator layer 2202 across a substrate and can advantageously preserve die yield over an entire substrate.
  • Docket No.: KP12P064US-PCT [00309]
  • Figure 22J illustrates a cross-section of structure 2200J.
  • structure 2200J is a cross sectional illustration of structure 2200I in Figure 22I, following process to form via electrode 2224, metal line 2226, and metal line 2228.
  • mask 2223 utilized to form via opening 2221 is removed and a conductive material is deposited into opening 2219, opening 2221, and opening 2217.
  • the conductive material includes a material that is the same or substantially the same as the material of the via electrode 2214, including examples with or without one or more liner layers and fill metal.
  • a fill metal includes copper, tungsten, nickel, or cobalt, and a liner layer includes ruthenium or tantalum.
  • the liner layer is deposited on uppermost surface 2012A of the conductive interconnect 2012, on sidewall of insulator layer 2202, on sidewall of dielectric 2208, on sidewall of insulator layer 2010, sidewall of dielectric 2212, on uppermost dielectric surface 2212A, and on surfaces of via electrodes 2214.
  • a fill metal or a conductive material is directly deposited on uppermost surface 2012A of the conductive interconnect 2012, on sidewall of insulator layer 2202, on sidewall of dielectric 2208, on sidewall of insulator layer 2010, on sidewall of dielectric 2212, on uppermost dielectric surface 2212A, and on surfaces of via electrodes 2214.
  • a planarization process may be utilized to remove an excess conductive material deposited on dielectric 2212 and on via electrodes 2214.
  • the planarization process includes a chemical mechanical polish (CMP) process.
  • the CMP process isolates metal line 2228 from metal line 2226.
  • via electrode 2224 can be formed at the same time as metal line 2226.
  • uppermost surfaces 2214A of via electrode 2214, uppermost surface 2228A, and uppermost surface 2226A are co-planar or substantially co-planar after the CMP process.
  • via electrode 2214 may be fabricated before or after fabrication of via electrode 2224, metal line 2226, and metal line 2228.
  • Figure 23A illustrates a cross-section of structure 2300A.
  • structure 2300A is a cross sectional illustration of structure 2200B in Figure 22B, following process to etch and form capacitors 2205.
  • portion of insulator layer 2204 below lowermost surface 110B of structure 2302 is recessed.
  • structure 2302 includes top electrode 108, dielectric 106, and electrode 112.
  • the plasma etch forms surface 2204A, where surface 2204A is below uppermost surface 2204B and sidewall surface 2204C. In at least one example, lowermost surface 110B and uppermost surface 2204B are in contact with each other. In at least one example, the thickness of insulator layer 2204, as measured from lowermost surface 2204D to surface 2204A, is adequate for preventing hydrogen from diffusing from below insulator layer 2202. In at least one example, surface 2204A is substantially planar between two adjacent capacitors 102. In at least one example, structure 2302 comprises a same material as encapsulation structure 114 ( Figure 1A).
  • Figure 23B illustrates a cross-section of structure 2300B.
  • structure 2300B is a cross sectional illustration of structure 2300A in Figure 23A, following process to laterally recess sidewall 110A.
  • process utilized to recess sidewall 110A has been described above ( Figure 12C).
  • sidewall 2302A is substantially aligned with sidewall surface 2204C.
  • Figure 23C illustrates a cross-section of structure 2300C.
  • structure 2300C is a cross sectional illustration of structure 2300B in Figure 23B, following process to form encapsulation structure 2304.
  • encapsulation structure 2304 is formed by blanket depositing and etching an encapsulation layer, as described above ( Figure 12D). In at least one example, encapsulation structure 2304 comprises all the features of encapsulation structure 114 ( Figure 1A). In at least one example, encapsulation structure 2304 further comprises portion 2304A in contact with sidewall surface 2204C and surface 2204A. In at least one example, when an encapsulation layer, utilized to form encapsulation structure 2304, has a lateral thickness that is at least half a vertical thickness T E1 of electrode 110, then cavity 2305 may be eliminated. [00316] Figure 24A illustrates a cross-section of structure 2400A.
  • structure 2400A is a cross sectional illustration of structure 2200B in Figure 22B, following process to etch and form capacitors 2205.
  • portion of insulator layer 2204 below lowermost surface 110B of structure 2302 is recessed.
  • the plasma etch forms surface 2204A, where surface 2204A is gradually tapered below uppermost surface 2204B.
  • the thickness of insulator layer 2204 at a lowest point, as measured from lowermost surface 2204D to surface 2204A is adequate for preventing hydrogen from diffusing from 2202.
  • surface 2204A can have a variable height as measured relative to lowermost surface 2204D in region between two adjacent electrodes 110.
  • Figure 24B illustrates a cross-section of structure 2400B.
  • structure 2400B is a cross sectional illustration of structure 2400A in Figure 24A, following process to laterally recess sidewall 110A.
  • process utilized to recess sidewall 110A has been described above ( Figure 12C).
  • the process to recess sidewall 110A exposes portions of uppermost surface 2204B.
  • edge of uppermost surface 2204B is substantially aligned with sidewall 2302A.
  • Figure 24C illustrates a cross-section of structure 2400C.
  • structure 2400C is a cross sectional illustration of structure 2400B in Figure 24B, following process to form encapsulation structure 2402.
  • encapsulation structure 2402 is formed by blanket depositing and etching an encapsulation layer, as described above ( Figure 12D).
  • encapsulation structure 2402 comprises a same material as encapsulation structure 114 ( Figure 1A).
  • encapsulation structure 2402 comprises at least some of the features of encapsulation structure 114 ( Figure 1A).
  • encapsulation structure 2402 further comprises portion 2402A that follows a contour of surface 2204B.
  • Figure 25 illustrates a cross-section of structure 2500.
  • structure 2500 is a cross sectional illustration of structure 2200C in Figure 22C following process to mask and pattern insulator layer 2204.
  • mask 2501 is formed above capacitor 102, encapsulation structure 114, and insulator layer 2204.
  • mask 2501 has a lateral thickness that extends beyond encapsulation structure 114.
  • mask 2501 may be formed from a sacrificial material that can be removed after patterning insulator layer 2204.
  • insulator layer 2204 is patterned and removed from above insulator layer 2202 in memory region 2201A and logic region 2201B.
  • two capacitors 102 are shown, where individual capacitor 102 is separated from a nearest capacitor 102.
  • the patterning process forms an island of insulator layer 2204 around individual electrode structure 116.
  • island of insulator layer 2204 is sufficient to block hydrogen from reaching capacitor 102.
  • Figure 26A illustrates a cross-section of structure 2600A.
  • structure 2600A is a cross sectional illustration of structure 2200B in Figure 22B following process to laterally recess electrode 110, deposit encapsulation layer 1214, deposit and planarize dielectric 2206, followed by process to mask and etch dielectric 2206, Docket No.: KP12P064US-PCT encapsulation layer 1214, and insulator layer 2204.
  • process to form encapsulation layer 1214 is described above ( Figure 12D).
  • dielectric 2206 is deposited and planarized by process methodology described above ( Figure 22D).
  • the planarization process utilized to planarize dielectric 2206 and remove it from above encapsulation layer 1214 does not remove encapsulation layer 1214 from above top electrode 108.
  • mask 2601 is formed above dielectric 2206 and encapsulation layer 1214.
  • a plasma etch process is utilized to etch dielectric 2206, encapsulation layer 1214, and insulator layer 2204 from logic region 2201B.
  • Figure 26B illustrates a cross-section of structure 2600B.
  • structure 2600B is a cross sectional illustration of structure 2600A in Figure 26A following process to form dielectric 2208 in logic region 2201B.
  • the method of forming dielectric 2208 is substantially the same as method described above ( Figure 22F).
  • dielectric 2208 is deposited on portions of encapsulation layer 1214 above top electrode 108.
  • the CMP process utilized to planarize dielectric 2208 that is deposited in memory region 2201A does not remove encapsulation layer 1214 from above capacitor 102.
  • some dishing of dielectric 2206 adjacent to encapsulation layer 1214 may occur as a result of CMP process.
  • Figure 26C illustrates a cross-section of structure 2600C.
  • structure 2600C is a cross sectional illustration of structure 2600B in Figure 26B following process to form via electrode 2214 coupled with top electrode 108 in memory region 2201A, and form metal line 2228, metal line 2226, and electrode 2224 in logic region 2201B.
  • etch stop layer 2210 is blanket deposited on encapsulation layer 1214, dielectric 2206, and dielectric 2208, and dielectric is blanket deposited on etch stop layer 2210.
  • process utilized to form electrode 2214 is substantially similar to process described above ( Figures 22G-22H) with the exception that via opening formed in dielectric 2212 and in etch stop layer 2210 is extended through encapsulation layer 1214 to expose top electrode 108.
  • Figure 27A illustrates a cross-section of structure 2700A.
  • structure 2700A is a cross sectional illustration of structure 2200A in Figure 22A, where electrode structure 116 is further laterally surrounded by sacrificial layer 2702 which is Docket No.: KP12P064US-PCT formed above insulator layer 2204.
  • sacrificial layer 2702 is part of initial multi-layer stack 2703.
  • sacrificial layer 2702 includes a material of sacrificial layer 1502 ( Figure 15A).
  • Transistors 618 and transistor 2014 are not illustrated for clarity.
  • sacrificial layer 1502 is blanket deposited on insulator layer 2204.
  • sacrificial layer 2702 comprises an insulator that includes a material which can be selectively removed relative to insulator layer 2204 and one or more layers in multi- layer stack to be deposited above.
  • sacrificial layer 2702 is blanket deposited on etch stop layer 118 by a PVD, CVD, PECVD, or an ALD process.
  • sacrificial layer 2702 is deposited to a thickness between 2nm and 30nm.
  • thickness of sacrificial layer 2702 may be determined by process utilized to form electrode structure 116.
  • electrode structures 116 are formed within multi-layer stack 2701 by methods similar to methods described above ( Figure 15A- 15B), with the exception that opening is formed in a trilayer stack comprising sacrificial layer 2702, insulator layer 2204 and insulator layer 2202 as opposed to opening in a bilayer stack.
  • no electrode structure is formed in logic region 2201B.
  • Figure 27B illustrates a cross-section of structure 2700B.
  • structure 2700B is a cross sectional illustration of structure 2700A in Figure 27A, following process to form capacitors 402.
  • FIG. 10 illustrates a cross-section of structure 2700C.
  • structure 2700C is a cross sectional illustration of structure 2700B in Figure 27B, following process to remove sacrificial layer 2702.
  • sacrificial layer 2702 is removed by a wet chemical etch, where the wet chemical etch may be selective to top electrode 108, dielectric 106, electrode 112, and insulator layer 2204.
  • wet chemical etch may be used to effectively remove sacrificial layer 2702 under electrode 112.
  • complete removal of sacrificial layer 2702 forms cavity 2705 between electrode 112, insulator layer 2204, and electrode structure 116.
  • cavity 2705 exposes portions of sidewall Docket No.: KP12P064US-PCT 116A.
  • lateral thickness of cavity 2705 depends on size of lateral thickness W C relative to lateral thickness W ES , where W C is greater than W ES .
  • Figure 27D illustrates a cross-section of structure 2700D.
  • structure 2700D is a cross sectional illustration of structure 2700C in Figure 27C, following process to form encapsulation structure 404 on capacitor 402, on uppermost surface 118A, and adjacent to sidewall 116A.
  • encapsulation structure 404 has one or more features of encapsulation structure 404 ( Figure 4A).
  • method of forming encapsulation structure 404 is described above ( Figures 15F and 15G).
  • FIG. 27E illustrates a cross-section of structure 2700E.
  • structure 2700E is a cross sectional illustration of structure 2700D in Figure 27D, following process to form dielectric 2206 in memory region 2201A.
  • dielectric 2206 is blanket deposited on structure 2700D ( Figure 27D) by a PVD, CVD, PECVD, or an ALD process.
  • dielectric 2206 is planarized. In at least one example, the planarization process exposes a top surface of top electrode 108.
  • the planarization process removes a portion of top electrode 108 and upper portions of encapsulation structure 404 adjacent to top electrode 108, rendering a substantially planar top surface (not shown).
  • substantially planar top surface of encapsulation structure 404 is co-planar or substantially co-planar with uppermost surface 108B.
  • mask 2707 is formed on dielectric 2206, and on top electrode 108.
  • a plasma etch process is utilized to remove dielectric 2206 and insulator layer 2204 from logic region 2201B.
  • insulator layer 2204 can be removed selectively with little to no removal of insulator layer 2202.
  • uppermost surface 2202A of insulator layer 2202 may be recessed in logic region 2201B by up to 2 nm.
  • mask 2707 may be removed after etching dielectric 2206 and insulator layer 2204.
  • process operations described in association with Figures 22E-22J may be implemented on structure 2700E to form system 2100.
  • method to form encapsulation structure includes depositing an encapsulation layer but not etching the encapsulation layer.
  • Figure 28 illustrates a cross-section of structure 2800.
  • structure 2800 is a cross Docket No.: KP12P064US-PCT sectional illustration of structure 2700C in Figure 27C following process to deposit encapsulation layer 2802, and deposit and pattern dielectric 2206.
  • encapsulation layer 2802 includes a material that is the same or substantially the same as material of encapsulation structure 404.
  • a planarization process such as CMP is performed.
  • the CMP process removes excess dielectric 2206 from above encapsulation layer 2802.
  • encapsulation layer 2802 acts as a polish stop.
  • mask 2803 is formed on dielectric 2206.
  • a plasma etch process is utilized to etch dielectric 2206, encapsulation layer 2802, and insulator layer 2204 from logic region 2201B.
  • the fabrication process may be continued, and process operations described in association with Figures 26B and 26C may be utilized to form via electrodes coupled with individual capacitors 402 in 2201B, and form electrode 2224, and metal line 2226 in logic region 2201B of structure 2800.
  • barrier structure 2006 ( Figure 20A) may be formed prior to patterning a multi-layer stack and form one or more capacitors.
  • Figures 29A-29C illustrate a process flow for patterning and forming capacitors, in at least one example.
  • Figure 29A illustrates a cross-section of structure 2900A.
  • structure 2900A is a cross sectional illustration of structure 2200A in Figure 22A following process to pattern insulator layer 2204 from logic region 2201B.
  • 2901 is formed on insulator layer 2204 and on electrode structure 116.
  • a plasma etch process is utilized to etch insulator layer 2204 from unmasked portions in logic region 2201B.
  • the plasma etch process is substantially selective to insulator layer 2202.
  • insulator layer 2202 is deposited to a minimum thickness that can provide etch selectivity during etching of a dielectric to be formed in logic region 2201B in a downstream operation.
  • Figure 29B illustrates a cross-section of structure 2900B.
  • structure 2900B illustrates a cross-section of structure 2900A in Figure 29A, following process to form a portion of multi-layer stack 1201 on electrode structure 116 and on insulator layer 2204 in 2201A, and a portion of multi-layer stack 1201 on insulator layer 2202 in logic region 2201B.
  • number of layers in multi-layer stack 1201 can depend on a type of memory device to be fabricated.
  • process to form multi-layer stack 1201 includes blanket deposition of at least three material layers, to form capacitor 402 ( Figure 4A).
  • process to form multi-layer stack Docket No.: KP12P064US-PCT 1201 includes blanket deposition of at least four layers to form capacitor 102 ( Figure 1A).
  • multi-layer stack 1201 includes deposition of layers for a ferroelectric memory device.
  • multi-layer stack 1201 includes deposition of layers for a paraelectric memory device.
  • a transition region between memory region 2201A and logic region 2201B can produce a step height within layers in multi-layer stack 1201.
  • Figure 29C illustrates a cross-section of structure 2900C.
  • structure 2900C illustrates a cross-section of structure 2900B in Figure 29B following process to pattern multi-layer stack 1201 to form capacitors 2902.
  • a plasma etch process is utilized to etch multi-layer stack 1201.
  • plasma etch process may include a discharge produced by a magnetic enhanced reactive ion etching mechanism, an electron cyclotron resonance discharge or an inductively coupled plasma discharge.
  • residue 1201A of multi-layer stack 1201 may be formed on sidewall 2204E.
  • residue 1201A may include one or more layers of capacitor 2902.
  • an over etch may be performed to remove residue 1201A.
  • the fabrication process may be continued to completion.
  • electrode 110 may be laterally recessed and encapsulation layer may be deposited and etched to form encapsulation structure on capacitors 2902.
  • a portion of encapsulation layer utilized to form encapsulation structure may be formed on sides of residue 1201A.
  • Other operations such as formation of dielectrics in memory region 2201A and logic region 2201B and formation of electrodes coupled with capacitors and logic transistor may be carried out, in accordance with examples discussed above.
  • one or more layers in multi-layer stack 2703 in Figure 27A may be etched prior to forming capacitor above electrode structure 116.
  • Figure 30A illustrates a cross-section of structure 3000A.
  • structure 3000A illustrates a cross-section of structure 2700A in Figure 27A, following process to pattern a portion of multi-layer stack 2703 prior to forming capacitors.
  • mask 3001 is formed on multi-layer stack 2703, where mask 3001 includes a photoresist material.
  • a plasma etch process is utilized to etch multi-layer stack 2703 to form intermediate structure 3002.
  • plasma etch process may include a discharge produced by a magnetic Docket No.: KP12P064US-PCT enhanced reactive ion etching mechanism, an electron cyclotron resonance discharge or an inductively coupled plasma discharge.
  • sacrificial layer 2702 and insulator layer 2204 are etched from logic region 2201B to form intermediate structure 3002.
  • Figure 30B illustrates a cross-section of structure 3000B.
  • structure 3000B illustrates a cross-section of structure 3000A in Figure 30A, following process to form capacitor 402.
  • multi-layer stack 1506 is formed on structure 3000A after removal of mask 3001.
  • multi-layer stack 1506 may or may not include a layer to form electrode 110.
  • a plasma etch process is utilized to etch multi- layer stack 1506 to form capacitor 402 above an individual electrode structure 116.
  • residue 1506A of multi-layer stack 1506 may be formed on sidewall 2204E and sidewall 2702A.
  • residue 1506A may include one or more layers of capacitor 402.
  • an over etch may be performed to remove residue 1506A.
  • Figure 30C illustrates a cross-section of structure 3000C.
  • structure 3000C illustrates a cross-section of structure 3000B in Figure 30B following process to remove sacrificial layer 2702 from above insulator layer 2204 and from under electrode 112.
  • the process to remove sacrificial layer 2702 is described above ( Figure 27C).
  • residue 1506A formed adjacent to sidewall 2702A and sidewall 2204E may remain.
  • residue 1506A may extend above uppermost surface 2204B.
  • the fabrication process may be continued to laterally form encapsulation layer or etch the encapsulation layer to form encapsulation structure on capacitor 402.
  • encapsulation layer utilized to form encapsulation structure may be formed on residue 1506A, where portions of the encapsulation layer may extend on portions of uppermost surface 2204B, and on portion of uppermost surface 2202A in logic region 2201B.
  • the fabrication process may be continued to completion. For example, operations such as formation of dielectrics in memory region 2201A and logic region 2201B and formation of electrodes coupled with capacitors and logic transistor may be carried out, in accordance with examples discussed above.
  • Figure 31 illustrates computing architecture 3100 with a coherent cache or memory-side buffer chiplet that includes a memory controller, wherein the coherent cache or memory-side buffer chiplet is coupled to an accelerator, a processor, and a memory, in accordance with at least one example.
  • computing architecture 3100 Docket No.: KP12P064US-PCT comprises coherent cache or memory-side buffer chiplet 3101, accelerator 3102 (e.g., inference chip), processor (e.g., processor 3120), and memory die 3104.
  • coherent cache or memory-side buffer chiplet 3101 comprises at least two channels 3125 which are configured to connect with accelerator 3102 and processor 3120.
  • coherent cache or memory-side buffer chiplet 3101 comprises I/O and controller 3110 to manage data traffic with memory die 3104. By moving controller 3110 from processor 3120 to coherent cache or memory-side buffer chiplet 3101, cost in terms of power and die area for processor 3120 is reduced.
  • coherent cache or memory-side buffer chiplet 3101 is a cache memory that comprises ferroelectric memory cells.
  • coherent cache or memory-side buffer chiplet 3101 comprises one or more of: FE-SRAM, FE-DRAM, SRAM, MRAM, resistance RAM (Re-RAM), embedded DRAM (e.g., 1T-1C based memory), or a combination of them.
  • Figure 32 illustrates architecture 3200 of the coherent cache or memory-side buffer chiplet 3207 with multiple controllers and multiple cache banks, in accordance with at least one example.
  • architecture 3200 comprises channels (e.g., channel 3215-1, which can be ch0 and channel 3215-2, which can be ch1), cache banks 3201, cache controller 3202, non-volatile (NV) controller 3203, and reliability logic 3204.
  • cache controller 3202 is a local cache controller.
  • coherent cache or memory-side buffer chiplet 3207 may function as a cache or memory buffer.
  • cache lookups can map a large physical memory into a small physical cache using indirection via tags.
  • indirection refers to the use of tags to specify which address maps to which physical location.
  • a tag is used to figure out which address is currently mapped.
  • each cache bank 3201 includes data bank 3205 (e.g., comprising memory cells) and associated tags 3206.
  • data bank 3205 comprises ferroelectric memory cells.
  • data bank 3205 comprises one or more of: FE-SRAM, FE-DRAM, SRAM, MRAM, resistance RAM (Re-RAM), embedded DRAM (e.g., 1T-1C based memory), or a combination of them.
  • FE-SRAM FE-DRAM
  • SRAM SRAM
  • MRAM resistance RAM
  • Re-RAM resistance RAM
  • embedded DRAM e.g., 1T-1C based memory
  • data bank 3205 when data bank 3205 includes ferroelectric memory, it uses NV controller 3203 and a stronger reliability logic (e.g., error correction code) for security compared to non- ferroelectric memory for data bank 3205.
  • tags may be used to identify which addresses map to which physical locations in the bank.
  • cache may be set associative, in which a particular address can map to several physical locations. The specific physical location a newly allocated address is mapped to may be determined by a replacement algorithm, such as LRU (least recently used) or pseudo-LRU, or even random.
  • LRU least recently used
  • pseudo-LRU pseudo-LRU
  • tag 3206 may be coupled with a physical line.
  • Tag 3206 may comprise some address bits, sufficient to uniquely identify which address currently occupies the physical line coupled with the tag.
  • cache controller 3202 could be used to control state transitions used for cache look ups such as comparing requested addresses with tags stored in an array of tags 3206, and identifying a candidate for replacement (replacement algorithm) when a cache miss occurs.
  • cache controller could be tasked with initializing the cache when the cache power is on.
  • cache controller 3202 when FE memory of data bank 3205, which retains state across power cycles, is used, cache controller 3202 could write 0s to all memory locations to ensure that data associated with previously executed programs is erased, thus preventing any data leakage to subsequently executed programs, in at least one example.
  • non-volatile memory may also include an NV bit, which could indicate that cache data is meant to be non-volatile and remain across power cycles.
  • cache controller 3202 may skip locations marked thus when initializing memory.
  • reliability logic 3204 performs error correction to the data. Any suitable error correction scheme (e.g., with error correction code (ECC)) may be used by reliability logic 3204.
  • ECC error correction code
  • non-volatile (NV) controller 3203 is provided to explicitly clear the cache when using a non-volatile memory, such as FM memory for data bank 3205.
  • NV controller 3203 may include an NV bit which indicates cache lines that should not be cleared but are expected to retain their contents across power cycles.
  • functions of NV controller 3203 can be combined in cache controller 3202, or vice versa.
  • Figure 33 illustrates apparatus 3300 comprising an MxN memory array of bit- cells and corresponding periphery circuitry, in accordance with at least one example.
  • apparatus 3300 comprises MxN memory array 3301 of bit-cells, logic circuitry 3302 for address decoding, and logic circuitry 3303 for sense amplifier and BL driver, and logic circuitry 3304 for write drivers, and plate-line (PL) drivers.
  • plate-lines PL0, PL1 through PLN are parallel to word-lines WL0, WL1, through WLM while bit-lines BL0, BL1 through BLN are orthogonal to the plate-lines and the word- lines, where ‘N’ is a number greater than 1.
  • plate-lines PL0, PL1, through PLN are parallel to bit-lines BL0, BL1 through BLN, while word-lines WL0, WL1, through WLM are orthogonal to the plate-lines and the bit-lines, where ‘N’ is a number greater than 1.
  • individual memory bit-cells in memory array 3301 are organized in rows and columns.
  • memory bit-cells 33010,0 through 3301 M,N are organized in an array.
  • an individual memory bit-cell (e.g., 33010,0) is a 1TnC bit-cell.
  • an individual memory bit-cell (e.g., 3301 0,0 ) is a multi-element FE gain bit-cell.
  • An example of a 1TnC bit-cell is described with reference to Figures 32A-32B.
  • an individual memory bit-cell (e.g., 3301 0,0 ) is a multi-element FE gain bit-cell, where an individual capacitor of the bit-cell is connected to a transistor switch.
  • the access transistor when multiple capacitors are used per bit-cell, the access transistor may be made larger.
  • the access transistor is connected to the bit-line as the bit-line drives a gate terminal of the access transistor.
  • a larger access transistor can add capacitance to the bit-line.
  • one way to reduce the bit-line capacitance is to route the bit- line on higher level metal layers.
  • higher-level metal layers are usually occupied by ground and supply routes.
  • connecting the gate of the access transistor to higher-level metal layers to access the bit-line means traversing through contact regions and vias. Such signal path may increase resistance and capacitance on the bit-line.
  • memory array 3301 is split into two or more subarrays with bit-line multiplexers between the subarrays.
  • bit-line routes are split along the subarrays via a selection circuitry.
  • the selection circuitry decouples the bit-line into separate bit-line routes which allows the capacitance on the bit-line to reduce as parasitic capacitance from the bit- line route is reduced, and bit-line is not driving all the access transistors in a row of the array.
  • Docket No.: KP12P064US-PCT [00354]
  • wear-leveling logic 3306 provides one or more endurance mechanisms for the 1TnC memory bit-cells.
  • AI machine 3400 comprises computational block 3401 or processor having memory 3402 (e.g., random access memory (RAM)) and compute die 3403, RAM 3404 (e.g., static RAM (SRAM), ferroelectric or paraelectric RAM (FeRAM), ferroelectric or paraelectric static random-access memory (FeSRAM)), processor 3405, RAM 3406 (dynamic RAM (DRAM), FeRAM)), and solid-state memory or solid-state drive 3407.
  • RAM random access memory
  • RAM 3404 e.g., static RAM (SRAM), ferroelectric or paraelectric RAM (FeRAM), ferroelectric or paraelectric static random-access memory (FeSRAM)
  • processor 3405 RAM 3406 (dynamic RAM (DRAM), FeRAM)
  • DRAM dynamic RAM
  • FeRAM FeRAM
  • AI machine 3400 are packaged in a single package forming a system-on-chip (SoC).
  • SoC can be configured as a logic-on-logic configuration, which can be in a 3D configuration or a 2.5D configuration.
  • computational block 3401 is packaged in a single package and then coupled to processor 3405 and RAM 3404 and 3406, and solid-state drive 3407 on a printed circuit board (PCB).
  • PCB printed circuit board
  • computational block 3401 is configured as a logic-on-logic configuration, which can be in a 3D configuration or a 2.5D configuration.
  • computational block 3401 comprises special purpose compute die 3403 or microprocessor.
  • compute die 3403 is a compute chiplet that performs a function of an accelerator or inference.
  • memory 3402 is DRAM which forms a special memory/cache for the special purpose compute die 3403.
  • DRAM can be embedded DRAM (eDRAM) such as 1T-1C (one transistor and one capacitor) based memories.
  • eDRAM embedded DRAM
  • memory 3402 is ferroelectric or paraelectric RAM (Fe-RAM).
  • compute die 3403 is specialized for applications such as Artificial Intelligence, graph processing, and algorithms for data processing.
  • compute die 3403 further has logic computational blocks, for example, for multipliers and buffers, special data memory block (e.g., buffers) comprising DRAM, FeRAM, or a combination of them.
  • memory 3402 has weights and inputs stored in-order to improve the computational efficiency.
  • interconnects between processor 3405 (also referred to as special purpose processor), RAM 3404, and compute die 3403 are optimized for high bandwidth and low latency.
  • architecture of Figure 34 allows efficient packaging to lower the energy, Docket No.: KP12P064US-PCT power, or cost and provides for ultra-high bandwidth between memory 3402 and compute die 3403 of computational block 3401.
  • memory 3402 is partitioned to store input data (or data to be processed) 3402A and computed weights 3402B.
  • input data 3402A are stored in a separate memory (e.g., a separate memory die) and computed weights 3402B are stored in a separate memory (e.g., separate memory die).
  • compute die 3403 comprises matrix multiplier, adder, concatenation logic, buffers, and combinational logic.
  • compute die 3403 performs multiplication operation on input data 3402A and computed weights 3402B.
  • computed weights 3402B are fixed weights.
  • processor 3405 e.g., a graphics processor unit (GPU), field programmable grid array (FPGA) processor, application specific integrated circuit (ASIC) processor, digital signal processor (DSP), an AI processor, a central processing unit (CPU), or any other high-performance processor
  • GPU graphics processor unit
  • FPGA field programmable grid array
  • ASIC application specific integrated circuit
  • DSP digital signal processor
  • AI AI processor
  • CPU central processing unit
  • RAM 3404 is ferroelectric or paraelectric based SRAM.
  • solid-state drive 3407 comprises NAND flash cells.
  • solid-state drive 3407 comprises NOR flash cells.
  • solid-state drive 3407 comprises multi- threshold NAND flash cells.
  • non-volatility of FeRAM is used to introduce new features such as security, functional safety, and faster reboot time of AI machine 3400.
  • the non-volatile FeRAM is a low power RAM that provides fast access to data and weights.
  • RAM 3404 that is an FeRAM can also serve as a fast storage for computational block 3401 (or accelerator), which typically has low capacity and fast access requirements.
  • the FeRAM FeDRAM or FeSRAM
  • ferroelectric or paraelectric (FE) material may be in a transistor gate stack or in a capacitor of the memory.
  • ferroelectric material can be any suitable low voltage FE material that allows the FE material to switch its state by a low voltage (e.g., 3400 mV).
  • Docket No.: KP12P064US-PCT threshold in the FE material has a highly non-linear transfer function in the polarization vs. voltage response.
  • threshold is related to: a) non-linearity of switching transfer function, and b) to the squareness of the FE switching.
  • the non-linearity of switching transfer function is the width of the derivative of the polarization vs. voltage plot.
  • squareness is defined by the ratio of the remnant polarization to the saturation polarization; perfect squareness will show a value of 1. [00363]
  • squareness of the FE switching can be suitably manipulated with chemical substitution.
  • a P-E (polarization-electric field) square loop can be modified by La or Nb substitution to create an S-shaped loop.
  • shape can be systematically tuned to ultimately yield a non-linear dielectric.
  • the squareness of FE switching can also be changed by the granularity of FE layer.
  • a perfectly epitaxial, single crystalline FE layer will show higher squareness (e.g., ratio is closer to 1) compared to a polycrystalline FE.
  • this perfect epitaxial can be accomplished using lattice matched bottom and top electrodes.
  • BiFeO can be epitaxially synthesized using a lattice matched SrRuO3 bottom electrode yielding P-E loops that are square.
  • progressive doping with La will reduce the squareness.
  • FE material includes material of ferroelectric layer which are same as those described herein.
  • FE material is between two electrodes that comprise perovskite templated conductors.
  • a thin layer e.g., approximately 10 nm
  • a perovskite conductor such as SrRuO3
  • IrO2, RuO 2 , PdO 2 , or PtO 2 which have a non-perovskite structure but higher conductivity
  • Figure 35 illustrates 3-input majority gate 3500 using non-linear input capacitors, in accordance with at least one example.
  • 3-input majority gate 3500 comprises non-linear input capacitors C1nl, C2nl, and C3nl that receive digital signals a, b, and c, respectively.
  • signal names and node names are interchangeably used.
  • ‘a’ refers to node ‘a’ or signal ‘a’ depending on the context of the sentence.
  • one end or terminal of capacitor C1nl is coupled to node a while the other end of capacitor C1n1 is coupled to summing node Vs. The same is true for other non-linear capacitors C2n1 and C3nl, as shown.
  • 3-input majority gate 3500 comprises driver circuitry 3501.
  • driver circuitry Docket No.: KP12P064US-PCT 3501 is an inverter.
  • other types of driver circuitries can be used, such as NAND gate, NOR gate, multiplexer, buffer, or other logic gates.
  • majority function is performed at summing node Vs as Majority(a,b,c).
  • driver circuitry 3501 is an inverter, minority function is performed at output “out” as Minority(a,b,c).
  • an additional linear capacitor CL is coupled to summing node Vs and ground as shown.
  • linear capacitor CL is a non-ferroelectric capacitor.
  • the non-ferroelectric capacitor includes one of: dielectric capacitor, paraelectric capacitor, or non-linear dielectric capacitor.
  • a dielectric capacitor comprises a first metal plate and a second metal plate with a dielectric between them.
  • dielectric includes one or more of: HfOX, ABO3 perovskites, nitrides, oxy- fluorides, oxides, etc.
  • a paraelectric capacitor comprises a first metal plate and a second metal plate with paraelectric material between them.
  • f-orbital materials are doped to the ferroelectric materials to make paraelectric material.
  • room temperature paraelectric material include: SrTiO3, Ba(x)Sr(y)TiO 3 , HfZrO 2 , Hf-Si-O, La-substituted PbTiO 3 , or PMN-PT based relaxor ferroelectrics.
  • a dielectric capacitor comprises a first metal plate and a second metal plate with a non-linear dielectric capacitor between them. In at least one example, the range for dielectric constant is 1.2 to 10000.
  • capacitor CL can be implemented as MIM (metal-insulator-metal) capacitor technology, transistor gate capacitor, hybrid of metal capacitors, or transistor capacitor. In at least one example, capacitor CL can be implemented as MIM (metal-insulator-metal) capacitor technology, transistor gate capacitor, hybrid of metal capacitors, or transistor capacitor.
  • non-linear input capacitors C1nl, C2nl, and C3nl comprise non-linear polar material.
  • non-linear polar material includes one of: ferroelectric (FE) material, paraelectric material, relaxor ferroelectric, or non-linear dielectric.
  • paraelectric material is same as FE material, but with chemical doping of the active ferroelectric ion by an ion with no polar distortion.
  • non-polar ions are non-s orbital ions formed with p, d, or f external orbitals.
  • non-linear dielectric materials are same as paraelectric materials, relaxors, and dipolar glasses.
  • the FE material can be any suitable low voltage FE material that allows the FE material to switch its state by a low voltage (e.g., 100 mV).
  • threshold in the FE material has a highly non-linear transfer function in the polarization versus voltage response.
  • the threshold is related to: a) non-linearity of switching transfer function; and b) the squareness of the FE switching.
  • non-linearity of switching transfer function is the width of the derivative of the polarization versus voltage plot.
  • squareness is defined by the ratio of the remnant polarization to the saturation polarization; perfect squareness will show a value of 1.
  • squareness of FE switching can be suitably manipulated with chemical substitution.
  • a P-E (polarization-electric field) square loop in PbTiO 3 a P-E (polarization-electric field) square loop can be modified by La or Nb substitution to create an S-shaped loop.
  • the shape can be systematically tuned to ultimately yield a non-linear dielectric.
  • squareness of FE switching can also be changed by granularity of the FE layer.
  • a perfect epitaxial, single crystalline FE layer may show higher squareness (e.g., ratio is closer to 1) compared to polycrystalline FE.
  • a perfect epitaxial can be accomplished by use of lattice matched bottom and top electrodes.
  • BiFeO BFO
  • BFO BiFeO
  • the charge developed on node Vs produces a voltage and current that is the output of 3-input majority gate 3500.
  • any suitable driver circuitry 3501 can drive this output.
  • non-FE logic, FE logic, CMOS logic, BJT logic, etc. can be used to drive the output to a downstream logic.
  • drivers include one or more of inverters, buffers, NAND gates, NOR gates, XOR gates, amplifiers, comparators, digital-to-analog converters, analog-to-digital converters, multiplexers, etc.
  • the majority function is performed at the summing node Vs, and the resulting voltage is projected on to capacitance of driver circuitry 3501.
  • majority function of the currents (I a , I b , and I c ) on node Vs results in a resultant current that charges capacitor.
  • Table 1 illustrates the majority function f(Majority a, b, c).
  • any suitable driver circuitry 3501 can drive this output.
  • a non-FE logic, FE logic, CMOS logic, or BJT logic, etc. can be used to drive the output to a downstream logic.
  • drivers include inverters, buffers, NAND gates, NOR gates, XOR gates, amplifiers, comparators, digital-to-analog converters, analog-to-digital converters, or multiplexers, etc.
  • Figure 35 illustrates a 3-input majority gate
  • the same concept can be extended to more than 3 inputs to make an N-input majority gate, where N is greater than 2, in accordance with at least one example.
  • ‘N’ is an odd number.
  • 5-input majority gate is similar to a 3-input majority gate 3500 but for additional inputs ‘d’ and ‘e’.
  • inputs can come from the same drivers or from different drivers.
  • the 3-input majority gate can be configured as a fast inverter with a much faster propagation delay compared to a similar sized (in terms of area footprint) CMOS inverter. In at least one example, this may be useful when the inputs have a significantly slower slope compared to the propagation delay through the non-linear input capacitors.
  • third input is the driving input which is to be inverted. In at least one example, inversion will be at the Vs node.
  • N-input majority gate where ‘N’ is 1 or any other odd number.
  • N-input majority gate (N-1)/2 inputs are set to ‘1’ and (N-1)/2 inputs are set to ‘0’, and one input is used to decide the inversion function.
  • the various examples are described as a majority gate, the same concepts are applicable to a minority gate.
  • KP12P064US-PCT driving circuitry is an inverting circuitry coupled to the summing node Vs. The minority function is seen at the output of the inverting circuitry.
  • (2N-1) input majority gate can operate as an N-input AND gate where (N-1) inputs of the majority gate are set to zero.
  • AND function will be seen at the summing node Vs.
  • N-input NAND, OR, NOR gates can be realized.
  • summing node Vs is driven by a driver circuitry (e.g., inverter, buffer, NAND gate, AND gate, OR gate, NOR gate, or any other logic circuitry).
  • driver circuitry 3501 can be replaced with another majority or minority gate.
  • storage node Vs is directly coupled to a non-linear capacitor of another majority or minority gate.
  • any logic function f ⁇ x ⁇ , x ⁇ , ... x ⁇ can be represented by two levels of logic as given by the min-term expansion: f ⁇ x ⁇ , x ⁇ , ... x ⁇ ⁇ V ⁇ , ⁇ ,.... ⁇ f ⁇ x ⁇ , x ⁇ , ... x ⁇ ⁇ x ⁇ ⁇ ⁇ x ⁇ ⁇ ⁇ ... ⁇ x ⁇ ⁇ ⁇ where C ⁇ is either 0 or 1. When C ⁇ is 1, x ⁇ ⁇ ⁇ x ⁇ (the input is used in its original form). When C ⁇ is 0, x ⁇ ⁇ ⁇ x ⁇ (the input is used in its inverted form).
  • first level of logic is represented by at most 2 ⁇ AND gates ⁇ , one for each of the 2 ⁇ possible combinations of 0 and 1 for C ⁇ , C ⁇ , .... C ⁇ .
  • the second level of logic is represented by a single OR gate ( ⁇ ).
  • Each operand of the OR gate is a representation of a row in the truth table for f ⁇ x ⁇ , x ⁇ , ... x ⁇ .
  • a (2N-1)-input majority gate can represent an N-input AND gate, by tying (N-1) of the majority gate’s inputs to a ground level.
  • a (2N-1)- input majority gate can represent an N-input OR gate, by tying (N-1) of the majority gate’s inputs to a supply level (Vdd).
  • a majority gate can represent AND and OR gates, and the inputs to the AND and OR gates are either original or inverted forms of the input digital signals, any logic function can be represented by majority gates and inverters.
  • Figure 36 illustrates complex logic gate 3600 implemented using a 5-input majority gate, in accordance with at least one example.
  • an AOI (and- or-invert) logic comprises a 5-input majority gate.
  • 5-input majority gate includes non-linear capacitors C1n1, C2nl, C3nl, C4nl, and C5nl, and driving circuitry 3601 coupled as shown.
  • two of the non-linear capacitors receive the same input.
  • capacitors C3nl and C4nl receive input ‘c’.
  • C5nl is coupled to Vdd to produce an OR function at node Vs, where the OR function is Docket No.: KP12P064US-PCT OR(AND(a,b),c).
  • other logic gates can be realized by changing Vdd to ground for capacitor C5nl, and/or changing other inputs.
  • Example 1 is a device comprising: A device structure comprising: an electrode structure; a capacitor structure on the electrode structure, the capacitor structure comprising: a bottom electrode structure comprising: a first electrode comprising a first lateral thickness; and a second electrode on the first electrode, the second electrode comprising a second lateral thickness greater than the first lateral thickness; a dielectric comprising a non-linear polar material having a form ABB'O 3 , AA'B'O 3 , or ABO 3 , wherein A' is a first dopant for atomic site A, wherein B' is a second dopant for atomic site B, and wherein O is oxygen; and a third electrode on the dielectric; and an encapsulation structure comprising: a first portion adjacent to a first sidewall of the first electrode and adjacent to a lower surface of the second electrode; and a second portion adjacent to a second sidewall of the second electrode, a third sidewall of the dielectric, and a fourth sidewall of the third electrode.
  • Example 2 is a device structure according to any device structure described herein, in particular example 1, wherein the first lateral thickness is at least 2 nm less than the second lateral thickness.
  • Example 3 is a device structure according to any device structure described herein, in particular example 1, wherein the electrode structure comprises: a conductive hydrogen barrier layer comprising one of: TiAlN with greater than 30 atomic percent AlN, TaN with greater than 30 atomic percent nitrogen, TiSiN with greater than 20 atomic percent SiN, TaC, TiC, WC, WN, carbonitrides of Ta, Ti, W, TiO, Ti2O, WO3, SnO2, ITO, IGZO, zinc oxide or METGLAS series of alloys; and a fill metal within the conductive hydrogen barrier layer, wherein the fill metal comprises one of tantalum, titanium, ruthenium, tungsten, molybdenum or copper, wherein the second electrode comprises one of: a first non-Pb based metal oxide, such as but
  • Example 4 is a device structure according to any device structure described herein, in particular example 3, wherein the electrode structure comprises a third lateral thickness that is less than the first lateral thickness.
  • Example 5 is a device structure according to any device structure described herein, in particular example 1, wherein the first electrode has a vertical thickness orthogonal to the first lateral thickness, wherein the first portion has a fourth lateral thickness, and wherein the fourth lateral thickness is different from the vertical thickness.
  • Example 6 is a device structure according to any device structure described herein, in particular example 5, wherein the fourth lateral thickness varies with height, and wherein the fourth lateral thickness is at least equal to a quarter of the vertical thickness.
  • Example 7 is a device structure according to any device structure described herein, in particular example 6, wherein the first portion and the second portion are contiguous, and wherein the first portion further comprises a cavity.
  • Example 8 is a device structure according to any device structure described herein, in particular example 1, further comprising an insulator laterally adjacent to the electrode structure, wherein the second portion is in contact with the insulator.
  • Example 9 is a device structure according to any device structure described herein, in particular example 8, further comprising a liner between the insulator and the electrode structure, wherein the second portion further extends on the liner.
  • Example 10 is a device structure according to any device structure described herein, in particular example 9, wherein the encapsulation structure comprises one of: silicon nitride, carbon doped silicon nitride, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx, or TaSiOx, wherein ‘x’ and ‘y’ are first and second integers, respectively, wherein the liner comprises one of: silicon nitride, carbon doped silicon nitride, Al x O y , HfO x , ZrO x , TaO x , TiOx, AlSiOx, HfSiOx, or TaSiOx, wherein ‘x’ and ‘y’ are third and fourth integers, respectively, wherein the insulator comprises one of: silicon nitride, or carbon doped silicon nitride, and wherein the insulator and the encapsulation structure comprise
  • Example 11 is a device structure according to any device structure described herein, in particular example 8, wherein the encapsulation structure further comprising a third portion that extends laterally on the insulator beyond an outer sidewall of the second portion.
  • Example 12 is a device structure according to any device structure described herein, in particular example 11, wherein the encapsulation structure further comprising a fourth portion that extends on the second portion and on an uppermost surface of the third electrode.
  • Example 13 is a device structure according to any device structure described herein, in particular example 5, wherein the second portion comprises a fifth lateral thickness, and wherein a minimum value of the fourth lateral thickness is equal to the fifth lateral thickness.
  • Example 14 is a device structure according to any device structure described herein, in particular example 1, wherein the dielectric comprises: the form ABB'O 3 , wherein A includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na, wherein B includes one of Mn, Fe, Ta, or Nb, and wherein B' includes one of: Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, or Zn, the form ABO3, wherein A includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, G
  • Example 15 is a device structure comprising: a plurality of electrode structures; a plurality of capacitor structures, wherein individual ones of the plurality of capacitor structures are coupled with individual ones of the plurality of electrode structures, and wherein the individual ones of the plurality of capacitor structures comprise: a bottom electrode structure, comprising: a first electrode comprising a first lateral width; and a second electrode on the first electrode comprising a second lateral with greater than the first lateral width; a dielectric comprising a non-linear polar material; and a third electrode on the dielectric; and an encapsulation structure comprising: a first portion adjacent to a first sidewall of the first electrode and adjacent to a lower surface of the second electrode; and a second portion adjacent to a second sidewall of the second electrode, a third sidewall of the dielectric, and a fourth sidewall of the third electrode, wherein the first portion and the second portion are contiguous.
  • Example 16 is a device structure according to any device described herein, in particular example 15, wherein the encapsulation structure further comprises a third portion that is contiguous between a first capacitor and a second capacitor in the plurality of capacitor structures.
  • Example 17 is a device structure according to any device described herein, in particular example 15, wherein a top surface of the encapsulation structure is substantially planar or co-planar with an uppermost surface of the third electrode.
  • Example 18 is a device structure according to any device described herein, in particular example 15, wherein the dielectric comprises one of: a first form ABB’O 3 , wherein A includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na, wherein B includes one of Mn, Fe, Ta, or Nb, and wherein ‘B'’ includes one of: Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, or Zn; a second form AA'BO3, wherein A includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na, wherein B includes one of Mn, Fe, Ta, or Nb, wherein A' includes one
  • Example 19 is a system comprising: a transistor comprising: a source; a drain; and a gate; a capacitor coupled with the transistor, the capacitor comprising: a bottom electrode structure, comprising: a first electrode comprising a first lateral thickness; and a second electrode on the first electrode, the second electrode comprising a second lateral thickness greater than the first lateral thickness; a dielectric comprising a non-linear polar material having a form ABB'O3, AA'B'O3, or ABO3, wherein A' is a first dopant for atomic site A, wherein B' is a second dopant for atomic site B, and wherein O is oxygen; and a third Docket No.: KP12P064US-PCT electrode on the dielectric; an encapsulation structure comprising: a first portion adjacent to a first sidewall of the first electrode and adjacent to a lower surface of the second electrode; and a second portion adjacent to a second sidewall of the second electrode, a third
  • Example 20 is a system according to any system described herein, in particular example 19, wherein the electrode structure comprises: a conductive hydrogen barrier layer comprising one of: TiAlN with greater than 30 atomic percent AlN, TaN with greater than 30 atomic percent nitrogen, TiSiN with greater than 20 atomic percent SiN, TaC, TiC, WC, WN, carbonitrides of Ta, Ti, W, TiO, Ti 2 O, WO 3 , SnO 2 , ITO, IGZO, zinc oxide or METGLAS series of alloys; and a fill metal within the conductive hydrogen barrier layer, wherein the fill metal comprises one of tantalum, titanium, ruthenium, tungsten, molybdenum or copper, wherein the first electrode comprises one of: niobium, chromium, molybdenum, tantalum, tungsten, rhenium, titanium, nitrogen doped variants of niobium, chromium, molybdenum, tantalum,
  • Example 1A is a method of fabricating a device, the method comprising: forming an electrode structure within an insulator layer; forming a capacitor structure on the electrode structure, wherein forming the capacitor structure comprises: depositing a multilayer stack comprising a plurality of electrode layers and a dielectric layer comprising a non-linear polar material; and patterning the multilayer stack to form a top electrode, a dielectric comprising the non-linear polar material, and a bottom electrode structure comprising an upper electrode and a lower electrode; forming a recess by laterally etching a Docket No.: KP12P064US-PCT first sidewall of the lower electrode; and depositing an encapsulation layer comprising a first portion on a second sidewall of the upper electrode and a second portion on a third sidewall of the lower electrode, wherein the second portion is in contact with a lowermost surface of the upper electrode.
  • Example 2A is a method of fabricating a device according to any method described herein, in particular example 1A, wherein the encapsulation layer comprises one of: silicon nitride, carbon doped silicon nitride, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx or TaSiOx, wherein ‘x’ and ‘y’ are first and second integers, respectively, wherein the insulator layer comprises one of: silicon nitride, or carbon doped silicon nitride, and wherein the encapsulation layer comprises a different material than a material of the insulator layer.
  • Example 3A is a method of fabricating a device according to any method described herein, in particular example 1A further comprising planarizing the capacitor structure and the first portion, wherein uppermost surfaces of the first portion and the top electrode are substantially co-planar.
  • Example 4A is a method of fabricating a device according to any method described herein, in particular example 1A, wherein the encapsulation layer is deposited to a thickness that is at least equal to half vertical thickness of the lower electrode, and wherein the encapsulation layer fills the recess.
  • Example 5A is a method of fabricating a device according to any method described herein, in particular example 1A, wherein the lower electrode has a vertical thickness that is greater than a first lateral thickness of the first portion, and wherein the encapsulation layer does not fill the recess.
  • Example 6A is a method of fabricating a device according to any method described herein, in particular example 5A, wherein depositing the encapsulation layer forms the second portion comprising a variable lateral thickness, wherein the variable lateral thickness has a minimum thickness adjacent to a portion of the third sidewall, and wherein the minimum thickness is equal to the first lateral thickness.
  • Example 7A is a method of fabricating a device according to any method described herein, in particular example 6A, wherein depositing the encapsulation layer further comprises depositing on a top surface of the capacitor structure, on the third sidewall of the dielectric, on a fourth sidewall of the top electrode and on the insulator layer.
  • Example 8A is a method of fabricating a device according to any method described herein, in particular example 7A, wherein the method further comprises etching the encapsulation layer to form an encapsulation structure, wherein etching the encapsulation Docket No.: KP12P064US-PCT layer removes the encapsulation layer from the top surface of the capacitor structure and from a portion of an uppermost surface of the insulator layer, wherein the encapsulation structure comprises the first portion and the second portion, and wherein the first portion further extends on the third sidewall and on the fourth sidewall.
  • Example 9A is a method of fabricating a device according to any method described herein, in particular example 8A, wherein etching reduces the first lateral thickness but not the minimum thickness.
  • Example 10A is a method of fabricating a device according to any method described herein, in particular example 9A, wherein etching the encapsulation layer, changes the first lateral thickness to a second lateral thickness where the second lateral thickness varies from the top electrode to the lower electrode.
  • Example 11A is a method of fabricating a device according to any method described herein, in particular example 1A, wherein forming the recess comprises laterally recessing the first sidewall by at least 2nm compared to the second sidewall.
  • Example 12A is a method of fabricating a device according to any method described herein, in particular example 1A, wherein prior to forming the electrode structure within the insulator layer, the method further comprises forming a liner between the electrode structure and the insulator layer, and wherein the liner comprises a material of the encapsulation layer.
  • Example 13A is a method of fabricating a device according to any method described herein, in particular example 12A, wherein the encapsulation layer comprises one of: material described above in example 3.
  • Example 14A is a method of fabricating a device according to any method described herein, in particular example 1A, wherein depositing the multilayer stack comprises: depositing a material of the lower electrode, upper electrode, top electrode and the dielectric layer as described in examples 18 and 20.
  • Example 15A is a method of fabricating a device according to any method described herein, in particular example 1A further comprising: depositing an etch stop layer on the capacitor structure; forming an opening in the etch stop layer; and forming a via electrode in the opening, wherein the via electrode is in contact with the top electrode, and wherein the etch stop layer comprises a material of the insulator layer.
  • Example 16A is a method of fabricating a device, the method comprising: forming a capacitor by patterning a multilayer stack comprising a plurality of electrode layers and a dielectric layer comprising a non-linear polar material having a form ABB'O 3 , Docket No.: KP12P064US-PCT AA'B'O3, or ABO3, wherein patterning the multilayer stack forms a top electrode, a bottom electrode structure comprising an upper electrode and a lower electrode, and a dielectric comprising the non-linear polar material between the top electrode and the bottom electrode structure; laterally recessing a first sidewall of the lower electrode; and depositing an encapsulation layer adjacent to second sidewall of the capacitor and in contact with at least a second portion of a lowermost surface of the lower electrode.
  • Example 17A is a method of fabricating a device according to any method described herein, particular example 16A, wherein the method further comprises forming an electrode structure above a substrate and depositing the multilayer stack on the electrode structure prior to forming the capacitor.
  • Example 18A is a method of fabricating a device according to any method described herein, particular example 17A, wherein prior to forming the lower electrode and depositing the encapsulation layer, the method further comprises forming a spacer on sidewalls of the top electrode, the dielectric and the upper electrode, and wherein depositing the encapsulation layer further comprises depositing on an outer sidewall of the spacer.
  • Example 19A is a method of forming a system, the method comprising: forming a transistor above a substrate, the transistor comprising a source, a gate and a drain; and forming a device structure coupled with the gate or the drain of the transistor, wherein forming the device structure comprises: forming an electrode structure; forming a capacitor structure on the electrode structure, wherein forming the capacitor structure comprises: depositing a multilayer stack comprising a plurality of electrode layers and a dielectric layer comprising a non-linear polar material; and patterning the multilayer stack to form a top electrode, a dielectric comprising the non-linear polar material, a bottom electrode structure comprising an upper electrode and a lower electrode; forming a recess by laterally etching a first sidewall of the lower electrode; and depositing an encapsulation layer comprising a first portion on a second sidewall of the upper electrode and a second portion on a third sidewall of the lower electrode, wherein the second portion is in contact with
  • Example 20A is a method of forming a system according to any method described herein, particular example 19A, wherein forming the transistor comprises forming a non-planar transistor or a nano-wire transistor, and wherein forming the multilayer stack comprises: depositing a material of the lower electrode, upper electrode, top electrode and the dielectric layer as described in examples 18 and 20.
  • Example 1C is a device structure comprising: an electrode structure adjacent to an insulator, the electrode structure comprising a first lateral thickness; a capacitor in contact with the electrode structure, the capacitor comprising: a first electrode comprising a second lateral thickness, the second lateral thickness greater than the first lateral thickness; a dielectric comprising a non-linear polar material; and a second electrode on the dielectric; and an encapsulation structure comprising: a first portion adjacent to a first sidewall of the first electrode, a second sidewall of the dielectric, and a third sidewall of the second electrode; and a second portion adjacent to a lower surface of the first electrode, a portion of a fourth sidewall of the electrode structure, and an upper surface of the insulator, and wherein the first portion and the second portion are contiguous.
  • Example 2C is a device structure according to any device described herein, in particular example 1C, wherein the electrode structure comprises a material described above in example 3.
  • Example 3C is a device structure according to any device described herein, in particular example 1C, wherein the first electrode has a first vertical thickness, the first vertical thickness orthogonal to the first lateral thickness, wherein the second portion has a second vertical thickness, wherein the insulator has a third vertical thickness, and wherein the first vertical thickness is equal to a combined sum of the second vertical thickness and the third vertical thickness.
  • Example 4C is a device structure according to any device described herein, in particular example 3C, wherein the second portion has a third lateral thickness, and wherein the third lateral thickness is equal to at least a quarter of the second vertical thickness.
  • Example 5C is a device structure according to any device described herein, in particular example 4C, wherein the third lateral thickness varies with distance between the upper surface of the insulator and the lower surface of the first electrode.
  • Example 6C is a device structure according to any device described herein, in particular example 5C, wherein the second portion further comprises a cavity.
  • Example 7C is a device structure according to any device described herein, in particular example 1C, further comprising a liner between the insulator and the electrode structure, wherein the liner is further between the second portion and the electrode structure.
  • Example 8C is a device structure according to any device described herein, in particular example 7C, wherein the encapsulation structure comprises one of: silicon nitride, carbon doped silicon nitride, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx or TaSiOx, wherein ‘x’ and ‘y’ are first and second integers, respectively, wherein the liner comprises Docket No.: KP12P064US-PCT one of: silicon nitride, carbon doped silicon nitride, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiO x or
  • Example 9C is a device structure according to any device described herein, in particular example 1C, wherein the encapsulation structure further comprising a third portion extending laterally on the insulator beyond an outer sidewall of the first portion.
  • Example 10C is a device structure according to any device described herein, in particular example 9C, wherein the encapsulation structure further comprising a fourth portion extending on the first portion and on an upper surface of the second electrode.
  • Example 11C is a device structure according to any device described herein, in particular example 4C, wherein the encapsulation structure comprises a fourth lateral thickness that increases with distance from an uppermost surface of the insulator to a top surface of the second electrode.
  • Example 12C is a device structure according to any device described herein, in particular example 1C, wherein the dielectric comprises a material described in example 18.
  • Example 13C is a device structure according to any device described herein, in particular example 1C further comprising a spacer between the encapsulation structure and the second sidewall, wherein the spacer is above the second portion.
  • Example 14C is a device structure according to any device described herein, in particular example 13C, wherein the insulator comprises a first material that is different from a second material of the encapsulation structure or a third material of the spacer, wherein the encapsulation structure comprises one of: silicon nitride, carbon doped silicon nitride, Al x O y , HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx or TaSiOx, wherein ‘x’ and ‘y’ are first and second integers, respectively, wherein the spacer comprises one of: silicon nitride, carbon doped silicon nitride, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx or TaSiOx, wherein ‘x’ and ‘y’ are third and fourth integers, respectively, and wherein the insulator comprises one of: silicon nitride,
  • Example 15C is a device structure according to any device described herein, in particular example 1C, wherein the first lateral thickness is at least 2 nm less than the second lateral thickness.
  • Example 16C is a device structure comprising: an insulator layer; a plurality of electrode structures on a same level within the insulator layer, wherein individual ones of the plurality of electrode structures comprise a first lateral thickness and a first sidewall; a Docket No.: KP12P064US-PCT plurality of capacitor structures, wherein individual ones of the plurality of capacitor structures are coupled with the individual ones of the plurality of electrode structures, and wherein the individual ones of the plurality of capacitor structures comprise: a first electrode comprising a second lateral thickness, the second lateral thickness greater than the first lateral thickness; a dielectric comprising a non-linear polar material having a form ABB'O3, AA'B'O 3 , or ABO 3 , wherein A' is a first dopant
  • Example 17C is a device structure according to any device described herein, in particular example 16C, wherein the individual ones of the plurality of encapsulation structures further comprise a third portion that laterally extends on the insulator layer, and wherein the third portion is contiguous between the individual ones of the plurality of capacitor structures.
  • Example 18C is a device structure according to any device described herein, in particular example 16C, wherein a top surface of the individual ones of the plurality of encapsulation structures are substantially planar or co-planar with an upper surface of the second electrode.
  • Example 19C is a system, comprising: a transistor comprising: a source; a drain; and a gate; an electrode structure coupled with the drain, the electrode structure adjacent to an insulator on a same level as the electrode structure; a capacitor on the electrode structure, the capacitor comprising: a first electrode comprising a first sidewall, the first sidewall extending beyond a second sidewall of the electrode structure; a dielectric comprising a non-linear polar material having a form ABB'O 3 , AA'B'O 3 , or ABO 3 , wherein A' is a first dopant for atomic site A, wherein B' is a second dopant for atomic site B, and wherein O is oxygen; and a second electrode on the dielectric; and an encapsulation structure comprising: a first portion adjacent to the first sidewall and adjacent to a third sidewall of the dielectric; and a second portion that extends along a portion of the second sidewall from under a lower surface of the first
  • Example 20C is a system according to any system described herein, in particular example 19C, wherein the electrode structure comprises a material described in at least example 20, and wherein the transistor is one of: a planar, non-planar or a nano-wire transistor.
  • Example 1D is a method of fabricating a device, the method comprising: forming an electrode structure adjacent to an insulator layer; forming a capacitor on the electrode structure by patterning a multilayer stack comprising a plurality of electrode layers and a dielectric layer comprising a non-linear polar material , wherein patterning the multilayer stack forms a top electrode, a bottom electrode and a dielectric comprising the non-linear polar material between the top electrode and the bottom electrode; forming a recess under the bottom electrode adjacent the electrode structure; and depositing an encapsulation layer adjacent to a first sidewall of the capacitor and in contact with at least a portion of a lowermost surface of the bottom electrode.
  • Example 2D is a method of fabricating a device structure according to any method described herein, in particular example 1D, wherein forming the recess comprises etching and removing a sacrificial layer formed above the insulator layer, the insulator layer formed prior to forming the electrode structure.
  • Example 3D is a method of fabricating a device according to any method described herein, in particular example 1D, wherein the recess exposes a first portion of a second sidewall of the electrode structure, and wherein depositing the encapsulation layer further comprises depositing on the first portion of the second sidewall.
  • Example 4D is a method of fabricating a device according to any method described herein, in particular example 3D, wherein the encapsulation layer fills the recess, and wherein the encapsulation layer is further deposited on the insulator layer and on the top electrode.
  • Example 5D is a method of fabricating a device according to any method described herein, in particular example 4D, wherein the method further comprises etching the encapsulation layer from above the top electrode, and from above the insulator layer, and wherein etching the encapsulation layer forms an encapsulation structure having a second portion on the first sidewall and a third portion in contact the lowermost surface of the bottom electrode and in contact with the first portion of the second sidewall.
  • Example 6D is a method of fabricating a device according to any method described herein, in particular example 1D, wherein the encapsulation layer partially fills the recess. Docket No.: KP12P064US-PCT [00446]
  • Example 7D is a method of fabricating a device according to any method described herein, in particular example 3D, wherein a second portion of the encapsulation layer deposited on the first portion of the second sidewall comprises a first lateral thickness that varies with height of the second sidewall.
  • Example 8D is a method of fabricating a device according to any method described herein, in particular example 3D, wherein the encapsulation layer comprises one of: silicon nitride, carbon doped silicon nitride, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx or TaSiOx, wherein ‘x’ and ‘y’ are first and second integers, respectively, wherein the insulator layer comprises one of: silicon nitride, or carbon doped silicon nitride, and wherein the insulator layer and the encapsulation layer comprise a different material.
  • Example 9D is a method of fabricating a device according to any method described herein, in particular example 1D, wherein forming the multilayer stack comprises depositing a material of the bottom electrode, the dielectric layer and a material of the top electrode as described in at least example 14.
  • Example 10D is a method of fabricating a device, the method comprising: forming an electrode structure adjacent to a dual insulator stack; forming a capacitor structure on the electrode structure, wherein forming the capacitor structure comprises: depositing a multilayer stack comprising a plurality of electrode layers and a dielectric layer comprising a non-linear polar material; and patterning the multilayer stack to form a top electrode, a bottom electrode and a dielectric comprising the non-linear polar material between the top electrode and the bottom electrode; forming a recess by laterally etching an upper insulator layer in the dual insulator stack, wherein the recess exposes a first portion of a lower surface of the bottom electrode; and depositing an encapsulation layer adjacent to a first sidewall of the capacitor structure and within the recess, wherein the encapsulation layer comprises: a third portion adjacent to the first sidewall of the capacitor structure; and a fourth portion in contact with the lower surface of the bottom electrode.
  • Example 11D is a method of fabricating a device according to any method described herein, in particular example 10D, wherein forming the recess further comprises: exposing a fifth portion of a second sidewall of the electrode structure; and exposing a lower insulator layer, wherein the lower insulator layer is adjacent to the electrode structure, and wherein an upper surface of the electrode structure is above an upper surface of the lower insulator layer.
  • Example 12D is a method of fabricating a device according to any method described herein, in particular example 11D, wherein the recess has a vertical thickness that is Docket No.: KP12P064US-PCT greater than a lateral thickness of the encapsulation layer, wherein the fourth portion is further in contact with the fifth portion of the second sidewall, and wherein the fifth portion and the fourth portion are contiguous.
  • Example 13D is a method of fabricating a device according to any method described herein, in particular example 11D, wherein the encapsulation layer is deposited to a thickness that is at least equal to half vertical thickness of the recess, and wherein the encapsulation layer fills the recess.
  • Example 14D is a method of fabricating a device according to any method described herein, in particular example 12D, wherein depositing the encapsulation layer further comprises depositing on a top surface of the capacitor structure and on the lower insulator layer, and wherein the method further comprises etching the encapsulation layer to form an encapsulation structure within the recess, and wherein the encapsulation structure comprises: the third portion; and an eighth portion within the recess, wherein the eighth portion comprises a lateral recess, and wherein etching removes the encapsulation layer from the top surface of the capacitor structure and forms the third portion that is curved.
  • Example 15D is a method of fabricating a device according to any method described herein, in particular example 13D, wherein the recess is at least 1 nm wide as measured from the second sidewall and comprises a height of at least 2 nm from the upper surface of the lower insulator layer.
  • Example 17D is a method of fabricating a device according to any method described herein, in particular example 11D, wherein the encapsulation layer comprises one of: silicon nitride, carbon doped silicon nitride, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiO x or TaSiO x , wherein ‘x’ and ‘y’ are first and second integers, respectively, wherein the lower insulator layer comprises one of: silicon nitride, or carbon doped silicon nitride, and wherein the lower insulator layer and the encapsulation layer comprise a different material.
  • Example 18D is a method of fabricating a device according to any method described herein, in particular example 10D, wherein depositing the multilayer stack further comprises depositing a material of the bottom electrode, the dielectric layer and a material of the top electrode as described in at least example 9D.
  • Example 19D is a method of fabricating a system, the method comprising: forming a transistor above a substrate, the transistor comprising a source, a gate and a drain; and forming a device structure coupled with the gate or the drain of the transistor, wherein forming the device structure comprises: forming an electrode structure adjacent to a dual insulator layer; forming a capacitor on the electrode structure by patterning a multilayer Docket No.: KP12P064US-PCT stack, wherein patterning the multilayer stack forms a top electrode, a bottom electrode and a dielectric comprising a non-linear polar material between the top electrode and the bottom electrode; forming a recess under the bottom electrode and adjacent the electrode structure by removing an upper insulator layer in the dual insulator layer; and depositing an encapsulation layer adjacent to a first sidewall of the capacitor and on at least a portion of a lowermost surface of the bottom electrode.
  • Example 20D is a method of fabricating a system according to any method described herein, in particular example 19D, wherein forming the transistor comprises forming a non-planar transistor or a nano-wire transistor, and wherein depositing the encapsulation layer further comprises: depositing the encapsulation layer on a top surface of the capacitor, on a lower insulator layer that is exposed by removal of the upper insulator layer, and on a portion of a second sidewall of the electrode structure.
  • Example 1E is a device structure comprising: a first insulator layer and a second insulator layer on the first insulator layer; an electrode structure embedded within the first insulator layer and the second insulator layer; a capacitor coupled with the electrode structure, the capacitor comprising: a first electrode; a dielectric comprising a non-linear polar material; and a second electrode on the dielectric; an encapsulation layer on a sidewall of the capacitor and in contact with at least a portion of a lowermost surface of the first electrode, the encapsulation layer in contact with the second insulator layer; and a via electrode adjacent to the capacitor, the via electrode laterally surrounded by the first insulator layer but not the second insulator layer, wherein the via electrode extends beyond an uppermost surface of the electrode structure.
  • Example 2E is a device structure according to any device described herein, in particular example 1E further comprising a third electrode coupled between the electrode structure and the first electrode, wherein the first electrode comprises a first lateral thickness, and wherein the third electrode comprises a second lateral thickness, the first lateral thickness greater than the second lateral thickness.
  • Example 3E is a device structure according to any device described herein, in particular example 2E, wherein the sidewall is a first sidewall, and wherein the encapsulation layer is adjacent to a second sidewall of the third electrode.
  • Example 4E is a device structure according to any device described herein, in particular example 1E, wherein the first insulator layer comprises silicon, carbon and nitrogen, and wherein the second insulator layer comprises silicon and nitrogen, and wherein the encapsulation layer comprises one of: Al x O y , HfO x , ZrO x , TaO x , TiO x , AlSiO x , HfSiO x or Docket No.: KP12P064US-PCT TaSiOx, wherein ‘x’ and ‘y’ are first and second integers, respectively, and wherein the second insulator layer and the encapsulation layer comprise different materials.
  • Example 5E is a device structure according to any device described herein, in particular example 1E, wherein the first insulator layer comprises a first vertical thickness of at least 5 nm, and wherein the second insulator layer comprises a second vertical thickness of at least 5 nm.
  • Example 6E is a device structure according to any device described herein, in particular example 1E, wherein the capacitor is in a first region and the via electrode is in a second region, wherein the device structure further comprises: a first dielectric in the first region, the first dielectric on the second insulator layer and adjacent to the encapsulation layer; and a second dielectric in the second region, the second dielectric on the first insulator layer and adjacent to the via electrode.
  • Example 7E is a device structure according to any device described herein, in particular example 6E, wherein the first dielectric and the second dielectric comprise a same material.
  • Example 8E is a device structure according to any device described herein, in particular example 1E, wherein the encapsulation layer further extends to an edge of the second insulator layer.
  • Example 9E is a device structure according to any device described herein, in particular example 1E further comprising: a first conductive interconnect directly below and in contact with the electrode structure; and a second conductive interconnect directly below and in contact with the via electrode, wherein the second conductive interconnect and the second conductive interconnect are on a same level, wherein a lowermost surface of the via electrode is co-planar with a lowermost surface of the electrode structure.
  • Example 10E is a device structure according to any device described herein, in particular example 9E, wherein the first insulator layer extends on a portion of the first conductive interconnect and on a portion of the second conductive interconnect.
  • Example 11E is a device structure according to any device described herein, in particular example 1E, wherein the second insulator layer comprises a thickness of at least 3 nm.
  • Example 12E is a device structure according to any device described herein, in particular example 1E, wherein the electrode structure comprises materials described in at least example 3.
  • Example 13E is a device structure according to any device described herein, in particular example 1E, wherein the first electrode comprises one of: niobium, chromium, molybdenum, tantalum, tungsten, rhenium, titanium, nitrogen doped variants of niobium, chromium, molybdenum, tantalum, tungsten, rhenium, titanium, nitrides of tantalum, tungsten, titanium, conductive doped AlN, or conductive doped SiN.
  • the first electrode comprises one of: niobium, chromium, molybdenum, tantalum, tungsten, rhenium, titanium, nitrogen doped variants of niobium, chromium, molybdenum, tantalum, tungsten, rhenium, titanium, nitrides of tantalum, tungsten, titanium, conductive doped AlN, or conductive doped SiN.
  • Example 14E is a device structure according to any device described herein, in particular example 1E, wherein the dielectric comprises a material described in at least example 18.
  • Example 15E is a device structure comprising: a first insulator layer and a second insulator layer on the first insulator layer; an electrode structure embedded within the first insulator layer and the second insulator layer, wherein a first upper surface of the electrode structure extends above a second upper surface of the second insulator layer; a capacitor coupled with the electrode structure, the capacitor comprising: a first electrode; a dielectric layer comprising a non-linear polar material having a form ABB'O3, AA'B'O3, or ABO 3 , wherein A' is a first dopant for atomic site A, wherein B' is a second dopant for atomic site B, wherein O is oxygen; and a second electrode on the dielectric layer; an encapsulation layer on a sidewall of the capacitor and on at least a
  • Example 16E is a device structure according to any device described herein, in particular example 15E, wherein the first electrode comprises a first lateral thickness, and wherein the electrode structure comprises a second lateral thickness, the first lateral thickness greater than the second lateral thickness.
  • Example 17E is a device structure according to any device described herein, in particular example 15E, wherein the encapsulation layer comprises a third lateral thickness on the sidewall of the capacitor, and wherein the encapsulation layer comprises a fourth lateral thickness adjacent to a portion of the electrode structure, wherein the third lateral thickness is less than the fourth lateral thickness.
  • Example 18E is a system, comprising: a first transistor and a second transistor; a device structure coupled with a first drain of the first transistor, the device structure comprising: a first insulator layer and a second insulator layer on the first insulator layer; an electrode structure embedded within the first insulator layer and the second insulator layer; a Docket No.: KP12P064US-PCT capacitor coupled with the electrode structure, the capacitor comprising: a first electrode; a dielectric layer comprising a non-linear polar material; and a second electrode on the dielectric layer; and an encapsulation layer on a sidewall of the capacitor and in contact with at least a portion of a lowermost surface of the first electrode, the encapsulation layer in contact with the second insulator layer; and a via electrode coupled with a second drain of the second transistor, wherein the via electrode is adjacent to the capacitor, wherein the via electrode is laterally surrounded by the first insulator layer but not the second insulator layer
  • Example 19E is a system according to any system described herein, in particular example 18E, wherein an uppermost surface of the encapsulation layer is co-planar with an uppermost surface of the second electrode.
  • Example 20E is a system according to any system described herein, in particular example 18E, wherein the encapsulation layer laterally extends laterally under the first electrode by a distance of at least 2.5nm measured relative the sidewall.
  • Example 1F is a method of fabricating a device, the method comprising: forming an electrode structure within an opening in a stack of insulator layers; forming a capacitor on the electrode structure, wherein forming the capacitor comprises: depositing a multilayer stack comprising a plurality of electrode layers and a dielectric layer comprising a nonlinear polar material; patterning the multilayer stack to form a top electrode, a dielectric comprising the nonlinear polar material, and a bottom electrode structure comprising an upper electrode on a lower electrode; and forming a recess by laterally etching a first sidewall of the lower electrode; depositing an encapsulation layer on a second sidewall of the capacitor and on a portion of a lowermost surface of the upper electrode; patterning and removing an upper insulator layer in the stack of insulator layers in a region adjacent to the capacitor; and forming a via electrode in the region, wherein the via electrode is laterally surrounded by a lower insulator layer in the stack of
  • Example 2F is a method of fabricating a device according to any method described herein, in particular example 1F, wherein the upper insulator layer comprises silicon, carbon and nitrogen, wherein the lower insulator layer comprises silicon and nitrogen, wherein the encapsulation layer comprises one of: carbon-doped silicon nitride, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx or TaSiOx, and wherein the encapsulation layer comprises a different material from materials of the upper insulator layer and the lower insulator layer.
  • Example 3F is a method of fabricating a device according to any method described herein, in particular example 1F, wherein patterning and removing the upper insulator layer further comprises: depositing a dielectric on the capacitor and on the upper insulator layer; forming a mask on the dielectric; and etching the dielectric and the upper insulator layer from the region, wherein etching the upper insulator layer exposes the lower insulator layer in the region.
  • Example 4F is a method of fabricating a device according to any method described herein, in particular example 3F, wherein the dielectric is a first dielectric, and wherein forming the via electrode in the region comprises: depositing a second dielectric on the lower insulator layer in the region; planarizing the second dielectric; etching a via opening in the second dielectric and in the lower insulator layer to expose a conductive interconnect; and depositing at least one conductive material in the opening on the conductive interconnect.
  • Example 5F is a method of fabricating a device according to any method described herein, in particular example 1F, wherein the capacitor is formed prior to patterning the upper insulator layer.
  • Example 6F is a method of fabricating a device according to any method described herein, in particular example 1F, wherein the capacitor is formed after patterning the upper insulator layer, and wherein depositing the multilayer stack further comprises depositing on a third sidewall of the upper insulator layer at an edge of the region.
  • Example 7F is a method of fabricating a device according to any method described herein, in particular example 6F, wherein etching the multilayer stack further comprises forming a spacer comprising one or more layers of the multilayer stack on the third sidewall.
  • Example 8F is a method of fabricating a device according to any method described herein, in particular example 3F, wherein the encapsulation layer is further deposited on the upper insulator layer and on the top electrode prior to depositing the dielectric.
  • Example 9F is a method of fabricating a device according to any method described herein, in particular example 8F, wherein prior to forming the mask, the method further comprises: planarizing the dielectric; and planarizing and removing the encapsulation layer deposited on the top electrode, wherein the encapsulation layer formed on the second sidewall of the capacitor has a substantially flat uppermost surface.
  • Example 10F is a method of fabricating a device according to any method described herein, in particular example 8F, wherein after etching the dielectric, the method further comprises etching the encapsulation layer from the region prior to etching the upper insulator layer.
  • Example 11F is a method of fabricating a device according to any method described herein, in particular example 1F, wherein etching the multilayer stack further comprises recessing the upper insulator layer, and wherein depositing the encapsulation layer comprises following a contour of the recess.
  • Example 12F is a method of fabricating a device, the method comprising: forming a barrier structure with a step height, the step height formed by removing at least one layer within a stack of insulator layers in the barrier structure; forming an electrode structure within the barrier structure, wherein the electrode structure is laterally surrounded by the stack of insulator layers; forming a capacitor coupled with the electrode structure, the capacitor comprising a dielectric between a bottom electrode structure and a top electrode; depositing an encapsulation layer on the capacitor, wherein the encapsulation layer is deposited on a sidewall and on a portion of a lowermost surface of the capacitor; and forming a via structure in a region adjacent to the capacitor, the via structure laterally surrounded by one less layer in the stack of insulator layers than the electrode structure.
  • Example 13F is a method of fabricating a device according to any method described herein, in particular example 12F, wherein patterning and removing an upper insulator layer within the stack of insulator layers further comprises: forming a mask over the electrode structure; and etching the upper insulator layer from the region and exposing a lower insulator layer within the stack of insulator layers.
  • Example 14F is a method of fabricating a device according to any method described herein, in particular example 13F, wherein forming the via structure in the region comprises: blanket depositing a dielectric on the barrier structure, wherein the dielectric is further deposited on the capacitor and on portions of the encapsulation layer; planarizing the dielectric; etching an opening in the dielectric and in the lower insulator layer in the region, the opening exposing a conductive interconnect; and depositing at least one conductive material in the opening on the conductive interconnect.
  • Example 15F is a method of fabricating a device according to any method described herein, in particular example 14F, wherein planarizing the dielectric further comprises planarizing and removing the encapsulation layer from a top surface of the Docket No.: KP12P064US-PCT capacitor, and wherein uppermost surfaces of the top surface of the capacitor and the encapsulation layer are co-planar.
  • Example 16F is a method of fabricating a device according to any method described herein, in particular example 12F, wherein forming the capacitor further comprises laterally recessing a lowermost conductive electrode to form a recess, and wherein depositing the encapsulation layer further comprises filling the recess.
  • Example 17F is a method of fabricating a device according to any method described herein, in particular example 12F, wherein the bottom electrode structure further comprises a lower electrode and an upper electrode on the lower electrode, and wherein forming the capacitor further comprises depositing materials described in at least example 14A; etching the material of the top electrode to form the top electrode; etching the dielectric layer to form the dielectric; and etching the material of the upper electrode and the material of the lower electrode to form the bottom electrode structure.
  • Example 18 is a method of fabricating a system, the method comprising: forming a plurality of transistors above a substrate, wherein individual ones of the plurality of transistors comprise a source, a gate and a drain; forming a device structure coupled with the gate or the drain of a first transistor in the plurality of transistors, wherein forming the device structure comprises: forming an electrode structure within an opening in a stack of insulator layers; forming a capacitor on the electrode structure, wherein forming the capacitor comprises: depositing a multilayer stack comprising a plurality of electrode layers and a dielectric layer comprising a nonlinear polar material; patterning the multilayer stack to form a top electrode, a dielectric comprising the nonlinear polar material, a bottom electrode structure comprising an upper electrode and a lower electrode; and forming a recess by laterally etching a first sidewall of the lower electrode; and depositing an encapsulation layer on a second sidewall of the capacitor and on a portion
  • Example 19F is a method of fabricating a system according to any system described herein, in particular example 18F, further comprising forming a conductive interconnect between the electrode structure and the drain or the source of the first transistor, wherein the via electrode is coupled with the drain or the source of the second transistor.
  • Docket No.: KP12P064US-PCT KP12P064US-PCT
  • Example 20F is a method of fabricating a system according to any system described herein, in particular example 18F, wherein forming the plurality of transistors comprises forming non-planar transistors or nano-wire transistors, and wherein forming the multilayer stack comprises a method as described in at least example 17F.
  • Example 1G is a method of fabricating a device, the method comprising: forming an electrode structure within an opening in a stack of insulator layers; forming a capacitor on the electrode structure, wherein forming the capacitor comprises: depositing a multilayer stack comprising a plurality of electrode layers and a dielectric layer comprising a nonlinear polar material; and patterning the multilayer stack to form a top electrode, a dielectric comprising the nonlinear polar material, and a bottom electrode; forming a recess by laterally etching a first insulator layer in the stack of insulator layers; depositing an encapsulation layer on a sidewall of the capacitor and on a portion of a lowermost surface of the bottom electrode exposed by the recess; patterning and removing a second insulator layer in the stack of insulator layers in a region adjacent to the capacitor; and forming a via electrode in the region, wherein the via electrode is laterally surrounded by a third insulator layer, in the
  • Example 2G is a method of fabricating a device according to any method described herein, in particular example is a method of fabricating a device according to any method described herein, in particular example 1G, wherein the third insulator layer comprises silicon, carbon and nitrogen, and wherein the second insulator layer comprises silicon and nitrogen, and wherein the encapsulation layer comprises one of: carbon-doped silicon nitride, Al x O y , HfO x , ZrO x , TaO x , TiO x , AlSiO x , HfSiO x or TaSiO x , and wherein the encapsulation layer comprises a different material from materials of the second insulator layer and the third insulator layer.
  • Example 3G is a method of fabricating a device according to any method described herein, in particular example 1G, wherein patterning and removing the second insulator layer further comprises: depositing a dielectric on the capacitor and on the second insulator layer; and etching the dielectric and the second insulator layer from the region, wherein etching the second insulator layer exposes the third insulator layer in the region.
  • Example 4G is a method of fabricating a device according to any method described herein, in particular example 3G, wherein the dielectric is a first dielectric, wherein forming the via electrode in the region comprises: depositing a second dielectric on the third insulator layer in the region; etching a via opening in the second dielectric and in the third Docket No.: KP12P064US-PCT insulator layer to expose a conductive interconnect; and depositing at least one conductive material in the opening on the conductive interconnect.
  • Example 5G is a method of fabricating a device according to any method described herein, in particular example 1G, wherein the capacitor is formed prior to patterning the first insulator layer.
  • Example 6G is a method of fabricating a device according to any method described herein, in particular example 1G, wherein the sidewall is a first sidewall, and wherein forming the recess further comprises: exposing a third portion of a second sidewall of the electrode structure; and exposing the second insulator layer, wherein the second insulator layer is adjacent to the electrode structure, and wherein a first upper surface of the electrode structure is above a second upper surface of the second insulator layer.
  • Example 7G is a method of fabricating a device according to any method described herein, in particular example 1G, wherein the capacitor is formed after patterning the first insulator layer and the second insulator layer, wherein depositing the multilayer stack further comprises depositing on a third sidewall of the first insulator layer, and on a fourth sidewall of the second insulator layer at an edge of the region.
  • Example 8G is a method of fabricating a device according to any method described herein, in particular example 7G, wherein etching the multilayer stack further comprises forming a spacer comprising one or more layers of the multilayer stack on the third sidewall and on the fourth sidewall.
  • Example 9G is a method of fabricating a device according to any method described herein, in particular example 3G, wherein the encapsulation layer is further deposited on the first insulator layer and on the top electrode prior to depositing the dielectric.
  • Example 10G is a method of fabricating a device according to any method described herein, in particular example 9G, wherein the method further comprises: planarizing the dielectric; and planarizing and removing the encapsulation layer deposited on the top electrode, wherein the encapsulation layer formed on the sidewall of the capacitor has a substantially flat uppermost surface.
  • Example 11G is a method of fabricating a device according to any method described herein, in particular example 8G, further comprises etching the encapsulation layer from the region prior to etching the second insulator layer.
  • Example 12G is a method of fabricating a device, the method comprising: forming an electrode structure within a barrier structure, the barrier structure comprising a stack of insulator layers and a step height, the step height formed by removing at least one Docket No.: KP12P064US-PCT layer within the stack of insulator layers; forming a capacitor coupled with the electrode structure, the capacitor comprising a dielectric comprising a nonlinear polar material between a bottom electrode and a top electrode; forming a recess under the bottom electrode adjacent the electrode structure; depositing an encapsulation layer on the capacitor, wherein the encapsulation layer is deposited on a sidewall and on a portion of a lowermost surface of the capacitor; and forming a via structure in
  • Example 15G is a method of fabricating a device according to any method described herein, in particular example 13G, wherein patterning and removing the at least one layer within the stack of insulator layers further comprises: depositing a first dielectric on the upper insulator layer; forming a mask on the first dielectric and over the electrode structure; and etching the upper insulator layer from the region, wherein etching the upper insulator layer exposes a lower insulator layer within the stack of insulator layers in the region.
  • Example 16G is a method of fabricating a device according to any method described herein, in particular example 15G, wherein forming the via structure in the region comprises: blanket depositing a second dielectric on the lower insulator layer, wherein the second dielectric is further deposited above the capacitor; planarizing the second dielectric; etching an opening in the second dielectric and in the lower insulator layer in the region, the opening exposing a conductive interconnect; and depositing at least one conductive material in the opening on the conductive interconnect.
  • Example 17G is a method of fabricating a device according to any method described herein, in particular example 16G, wherein depositing the second dielectric comprises depositing above the encapsulation layer and wherein planarizing the second dielectric further comprises planarizing and removing the encapsulation layer from a top surface of the capacitor, and wherein planarizing forms top surfaces of the capacitor and the encapsulation layer that are co-planar. Docket No.: KP12P064US-PCT [00516]
  • Example 18G is a method of fabricating a device according to any method described herein, in particular example 12G, wherein forming the capacitor further comprises depositing materials described in at least example 9D.
  • Example 19G is a method of forming a system, the method comprising: forming a plurality of transistors above a substrate, wherein individual ones of the plurality of transistors comprise a source, a gate and a drain; forming a device structure coupled with the gate or the drain of a first transistor in the plurality of transistors, wherein forming the device structure comprises: forming an electrode structure within a barrier structure, the barrier structure comprising a step height, the step height formed by removing at least one layer within a stack of insulator layers in the barrier structure; forming a capacitor on the electrode structure by patterning a multilayer stack comprising a plurality of electrode layers and a nonlinear polar material having a form ABB'O3, AA'B'O3, or ABO3, wherein patterning the multilayer stack forms a top electrode, a bottom electrode and a dielectric layer between the top electrode and the bottom electrode; forming a recess under the bottom electrode adjacent the electrode structure; and depositing an encapsulation
  • Example 20G is a method of fabricating a system according to any method described herein, in particular example 19G, wherein forming the recess comprises removing a sacrificial layer within the stack of insulator layers, wherein the sacrificial layer is an uppermost layer within the stack of insulator layers, wherein removing the sacrificial layer exposes a portion of a sidewall of the electrode structure, and wherein depositing the encapsulation layer further comprises depositing on the portion of the sidewall.
  • Example 21G is a method of fabricating a system according to any method described herein, in particular example 19G, further comprising forming a conductive interconnect between the electrode structure and the drain or the source, wherein forming the plurality of transistors comprising forming non-planar transistors or nano-wire transistors, and wherein forming the multilayer stack by depositing layers described in at least example 18G.

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Abstract

A device structure comprises a capacitor on an electrode structure. The capacitor comprises a bottom electrode structure that includes at least two layers and a non-linear polar material. The device structure further includes an encapsulation layer that is adjacent to sidewalls of the capacitor including a lower surface of at least a portion of the bottom electrode structure and on a sidewall of the electrode structure.

Description

Docket No.: KP12P064US-PCT ENCAPSULATION STRUCTURE FOR MEMORY DEVICES BACKGROUND [0001] Integration of capacitors with transistors on can be challenging. As such, alternate methods to protect layers during fabrication are desirable to increase charge storage and facilitate operation of memory and logic devices based on capacitors. BRIEF DESCRIPTION OF DRAWINGS [0002] Material described herein is illustrated by way of example and not by way of limitation in accompanying figures. For simplicity and clarity of illustration, elements illustrated in figures are not necessarily drawn to scale. For example, dimensions of some elements may be exaggerated relative to other elements for clarity. Also, various physical features may be represented in their simplified “ideal” forms and geometries for clarity of discussion, but it is nevertheless to be understood that practical implementations may approximate illustrated ideals. For example, smooth surfaces and square intersections may be drawn in disregard of finite roughness, corner-rounding, and imperfect angular intersections characteristic of structures formed by nanofabrication techniques. Further, where considered appropriate, reference labels have been repeated among figures to indicate corresponding or analogous elements. [0003] Figure 1A illustrates a cross-section of a device structure including a capacitor comprising a bottom electrode structure and an encapsulation structure on a sidewall of the bottom electrode structure, in at least one example. [0004] Figure 1B is an enhanced cross-sectional illustration of a portion of a pair of conductive layers of the capacitor in Figure 1A, in at least one example. [0005] Figure 1C illustrates a cross-section of a device structure including a capacitor comprising a bottom electrode structure, and an encapsulation structure on a sidewall of the bottom electrode structure, in at least one example. [0006] Figure 1D illustrates a cross-section of a device structure including a capacitor comprising a bottom electrode structure and an encapsulation structure, where the encapsulation structure further comprises a portion that extends laterally on an etch stop layer adjacent to the electrode structure, in at least one example. [0007] Figure 1E illustrates a cross-section of a device structure including a capacitor comprising a bottom electrode structure and an encapsulation structure, where the Docket No.: KP12P064US-PCT encapsulation structure further comprises a portion that extends laterally on etch stop layer, in at least one example. [0008] Figure 1F illustrates a cross-section of a device structure including a capacitor comprising a bottom electrode structure and an encapsulation structure on a sidewall of the bottom electrode structure, in at least one example. [0009] Figure 1G illustrates a cross-section of a device structure including a capacitor comprising a bottom electrode structure and an encapsulation structure on a sidewall of the bottom electrode structure, in at least one example. [0010] Figure 2A illustrates a cross-section of a device structure comprising a capacitor coupled with an electrode structure. [0011] Figure 2B illustrates a cross-section of a device structure comprising a plurality of capacitors, where an individual capacitor is coupled with an individual electrode structure, in at least one example. [0012] Figure 3A illustrates a cross-section of a cross-section of capacitor that includes a spacer between an encapsulation structure and sidewall of a portion of the capacitor. [0013] Figure 3B illustrates a cross-section of device structure in Figure 3A, where different portions of encapsulation structure can have different thicknesses, and where a portion of the encapsulation structure adjacent to a bottom electrode structure does not include a cavity. [0014] Figure 4A illustrates a cross-section of a device structure including a capacitor coupled with an electrode structure, where a first portion of an encapsulation structure is on a sidewall of the capacitor and a second portion is under a lowermost layer of the capacitor, in at least one example. [0015] Figure 4B illustrates a cross-section of the device structure in Figure 4A where encapsulation structure further comprises a portion that extends laterally on an etch stop layer adjacent to the capacitor. [0016] Figure 4C illustrates a cross-section of the device structure in Figure 4A where an insulator liner is on sidewalls of the electrode structure, in at least one example. [0017] Figure 4D illustrates a cross-section of the device structure in Figure 4A where a lateral thickness of a portion of encapsulation structure adjacent to a sidewall of the electrode structure varies with height of electrode structure, in at least one example. [0018] Figure 4E illustrates a cross-section of a device structure comprising a plurality of capacitors, where an individual capacitor is coupled with an individual electrode structure, in at least one example. Docket No.: KP12P064US-PCT [0019] Figure 5 is an illustration of a flow for fabricating a device structure. [0020] Figure 6A illustrates a cross-section of a fin structure formed on a substrate, in at least one example. [0021] Figure 6B is an isometric illustration of structure in Figure 6A following process to form a dielectric adjacent to a portion of fin structure, in at least one example. [0022] Figure 6C is an isometric illustration of structure in Figure 6B following formation of a dummy gate on fin, in at least one example. [0023] Figure 6D is an isometric illustration of structure in Figure 6C following process to form an epitaxial source structure and an epitaxial drain structure, in at least one example. [0024] Figure 6E is an isometric illustration of structure in Figure 6D following process to remove mask, dummy gate, and dummy gate dielectric to form a gate opening, in at least one example. [0025] Figure 6F illustrates a cross-section of structure in Figure 6E following process to form a gate structure in gate opening, in at least one example. [0026] Figure 7A illustrates a cross-section of structure in Figure 6F through a line A-A' following process to form a drain contact on a drain structure, in at least one example. [0027] Figure 7B illustrates a cross-section of structure in Figure 7A, following process to form a conductive interconnect coupled with the drain contact, in at least one example. [0028] Figure 8 illustrates a cross-section of structure in Figure 7B following process to deposit an etch stop layer to form an electrode structure, in at least one example. [0029] Figure 9A is an enhanced cross-sectional illustration of a portion of structure in Figure 8 following process to etch an opening in etch stop layer, in at least one example. [0030] Figure 9B illustrates a cross-section of structure in Figure 9A following process to deposit a liner layer within an opening, in at least one example. [0031] Figure 9C illustrates a cross-section of structure in Figure 9B following process to form a spacer within the opening, in at least one example. [0032] Figure 9D illustrates a cross-section of structure in Figure 9C following process to form a conductive hydrogen barrier layer adjacent to the spacer within the opening, and a conductive fill material on the conductive hydrogen barrier layer, in at least one example. [0033] Figure 9E illustrates a cross-section of structure in Figure 9A following process to form an electrode structure where a conductive hydrogen barrier laterally surrounds a conductive fill material, and where a spacer is between conductive hydrogen barrier and etch stop layer, in at least one example. Docket No.: KP12P064US-PCT [0034] Figure 10A illustrates a cross-section of a structure in Figure 9A following process to deposit a conductive fill material within the opening, in at least one example. [0035] Figure 10B illustrates a cross-section of a structure in Figure 10A following process to planarize and recess conductive fill material within opening, in at least one example. [0036] Figure 10C illustrates a cross-section of structure in Figure 10B following process to form a conductive hydrogen barrier on conductive fill material, in at least one example. [0037] Figure 11A illustrates a cross-section of structure in Figure 9A following process to form a conductive hydrogen barrier layer within opening, and a conductive fill material on conductive hydrogen barrier layer, in at least one example. [0038] Figure 11B illustrates a cross-section of structure in Figure 11A following process to form an electrode structure where a conductive hydrogen barrier laterally surrounds a conductive fill material, in at least one example. [0039] Figure 12A illustrates a cross-section of structure in Figure 11A following the process to deposit a multi-layer stack on an electrode structure, in at least one example. [0040] Figure 12B illustrates a cross-section of structure in Figure 12A, following process to etch multi-layer stack to form a capacitor, in at least one example. [0041] Figure 12C illustrates a cross-section of structure in Figure 12B following process to laterally recess a portion of a lowermost layer in capacitor, in at least one example. [0042] Figure 12D illustrates a cross-section of structure in Figure 12C, following process to deposit an encapsulation layer on sidewalls of capacitor, in at least one example. [0043] Figure 12E illustrates a cross-section of structure in Figure 12D, following process to etch encapsulation layer to form an encapsulation structure, in at least one example. [0044] Figure 13A illustrates a cross-section of structure in Figure 11A following process to etch multi-layer stack to form a partially formed capacitor structure, in at least one example. [0045] Figure 13B illustrates a cross-section of structure in Figure 13A following process to form a spacer adjacent to partially formed capacitor structure. [0046] Figure 13C illustrates a cross-section of structure in Figure 13B following process to etch a lowermost layer in multi-layer stack and laterally recess a portion of lowermost layer to form a recessed portion, in at least one example. Docket No.: KP12P064US-PCT [0047] Figure 13D illustrates a cross-section of structure in Figure 13C following process to deposit an encapsulation layer on spacer and adjacent to sidewall of recessed portion of lowermost layer, in at least one example. [0048] Figure 13E illustrates a cross-section of structure in Figure 13D following process to etch encapsulation layer to form an encapsulation structure, in at least one example. [0049] Figure 14A illustrates a cross-section of structure in Figure 13D following process to anisotropically etch lowermost conductive layer to form an electrode, in at least one example. [0050] Figure 14B illustrates a cross-section of a portion of structure in Figure 14A following process to recess a portion of electrode to form a cavity. [0051] Figure 15A illustrates a cross-section of structure in Figure 8 following process to deposit sacrificial layer and form an opening in the sacrificial layer and in the etch stop layer, in at least one example. [0052] Figure 15B illustrates a cross-section of structure in Figure 15A following process to form an electrode structure in opening, in at least one example. [0053] Figure 15C illustrates a cross-section of structure in Figure 15B following process to deposit a multi-layer stack to fabricate a capacitor, in at least one example. [0054] Figure 15D illustrates a cross-section of structure in Figure 15C following process to etch multi-layer stack to form a capacitor, in at least one example. [0055] Figure 15E illustrates a cross-section of structure in Figure 15D following process to remove sacrificial layer and expose a portion of sidewall of an electrode structure below capacitor, in at least one example. [0056] Figure 15F illustrates a cross-section of structure in Figure 15E following process to deposit an encapsulation layer on sidewall of the capacitor and adjacent to the portion of sidewall of an electrode structure exposed by removing sacrificial layer, in at least one example. [0057] Figure 15G illustrates a cross-section of structure in Figure 15F following process to etch the encapsulation layer to form an encapsulation structure, in at least one example. [0058] Figure 16A illustrates a cross-section of structure in Figure 15D following process to deposit an encapsulation layer on sidewall of capacitor and on sacrificial layer, in at least one example. Docket No.: KP12P064US-PCT [0059] Figure 16B illustrates a cross-section of structure in Figure 16A following process to etch encapsulation layer to form a spacer adjacent to capacitor sidewalls, in at least one example. [0060] Figure 16C illustrates a cross-section of structure in Figure 16B following process to remove the sacrificial layer and expose a portion of sidewall of an electrode structure below the capacitor and expose a portion of a lowermost surface of capacitor, in at least one example. [0061] Figure 16D illustrates a cross-section of structure in Figure 16C following process to deposit an encapsulation layer on sidewall of the spacer, on portion of lowermost surface of capacitor and on an etch stop layer adjacent to electrode structure, in at least one example. [0062] Figure 16E illustrates a cross-section of structure in Figure 16D following process to etch encapsulation layer to form an encapsulation structure, in at least one example. [0063] Figure 17A illustrates a cross-section of structure in Figure 16E following process to deposit a dielectric on capacitor, on encapsulation structure, and on etch stop layer, and planarize dielectric to expose an uppermost surface of a top electrode of capacitor, in at least one example. [0064] Figure 17B illustrates a cross-section of structure in Figure 17A following process to form a via electrode on at least a portion of top electrode of capacitor after formation of an insulator layer comprising a hydrogen barrier material, in at least one example. [0065] Figure 18 illustrates a cross-section of structure in Figure 15G following process to deposit a dielectric on capacitor and on encapsulation structure, and on etch stop layer, and planarize the dielectric to expose an uppermost surface of a top electrode of the capacitor, in at least one example. [0066] Figure 19 illustrates a cross-section of structure in Figure 18 following process to form a via electrode on at least a portion of top electrode of capacitor after formation of an insulator layer comprising a hydrogen barrier material, in at least one example. [0067] Figure 20A illustrates a cross-section of system comprising a device structure in a memory region and an interconnect structure in a logic region adjacent to the memory region, in at least one example. Docket No.: KP12P064US-PCT [0068] Figure 20B illustrates a cross-section of system comprising a device structure in a memory region and an interconnect structure in a logic region adjacent to the memory region, in at least one example. [0069] Figure 21 illustrates a cross-section of system comprising a device structure in a memory region and an interconnect structure in a logic region adjacent to the memory region, in at least one example. [0070] Figure 22A illustrates a cross section of structure comprising a pair of stacked insulator layers above an electrode structure, in at least one example. [0071] Figure 22B illustrates a cross-section of structure in Figure 22A, following process to form capacitors, in at least one example. [0072] Figure 22C illustrates a cross-section of structure in Figure 22B, following process to form a capacitor above an individual electrode structure, in at least one example. [0073] Figure 22D illustrates a cross-section of structure in Figure 22C, following process to form a first dielectric in the memory region, in at least one example. [0074] Figure 22E illustrates a cross-section of structure in Figure 22D, following process to deposit a second dielectric on a lower insulator layer in logic region adjacent to the memory region, in at least one example. [0075] Figure 22F illustrates a cross-section of structure in Figure 22E, following process to form an etch stop layer and a third dielectric on the etch stop layer, in at least one example. [0076] Figure 22G illustrates a cross-section of structure in Figure 22F, following process to form opening above top electrode of capacitor in memory region. [0077] Figure 22H illustrates a cross-section of structure in Figure 22G, following process to form via electrode in contact with top electrode. [0078] Figure 22I illustrates a cross-section of structure in Figure 22H, following process to form etch second dielectric to form via opening in logic region, in at least one example. [0079] Figure 22J illustrates a cross-section of in Figure 22I, following process to form via electrode and metal lines. [0080] Figure 23A illustrates a cross-section of structure in Figure 22B, following process to etch and form capacitor, where etching recesses an upper insulator layer, in at least one example. Docket No.: KP12P064US-PCT [0081] Figure 23B illustrates a cross-section of structure in Figure 23A, following process to laterally recess sidewall of a lower electrode of the capacitor, in at least one example. [0082] Figure 23C illustrates a cross-section of structure in Figure 23B, following process to form an encapsulation structure adjacent to the capacitor, in at least one example. [0083] Figure 24A illustrates a cross-section of structure in Figure 22B, following process to etch and form a capacitor, where etching recesses an upper insulator layer to form a concaved surface, in at least one example. [0084] Figure 24B illustrates a cross-section of structure in Figure 24A, following process to laterally recess sidewall of a lowermost electrode in the capacitor. [0085] Figure 24C illustrates a cross-section of structure in Figure 24B, following process to form an encapsulation structure adjacent to the capacitor, in at least one example. [0086] Figure 25 illustrates a cross-section of structure in Figure 22C following process to mask and pattern an upper insulator layer laterally adjacent to an electrode structure coupled with a capacitor, in at least one example. [0087] Figure 26A illustrates a cross-section of structure in Figure 22B following process to laterally recess electrode, deposit an encapsulation layer, deposit and planarize a first dielectric, followed by process to mask and etch a second dielectric, encapsulation layer, and an insulator layer, in at least one example. [0088] Figure 26B illustrates a cross-section of structure in Figure 26A following process to form a second dielectric in an adjacent logic region, in at least one example. [0089] Figure 26C illustrates a cross-section of structure in Figure 26B following process to form a via electrode coupled with a top electrode of a capacitor in a memory region, and following process to form a metal line, and electrode in an adjacent logic region. [0090] Figure 27A illustrates a cross-section of structure in Figure 22A, where electrode structure is further laterally surrounded by a sacrificial insulator layer, formed above an insulator layer, in at least one example. [0091] Figure 27B illustrates a cross-section of structure in Figure 27A following process to form capacitors, in at least one example. [0092] Figure 27C illustrates a cross-section of structure in Figure 27B following process to remove the sacrificial insulator layer. [0093] Figure 27D illustrates a cross-section of structure in Figure 27C following process to form encapsulation structure in contact with a capacitor, in at least one example. Docket No.: KP12P064US-PCT [0094] Figure 27E illustrates a cross-section of structure in Figure 27D, following process to form a first dielectric in a memory region, in at least one example. [0095] Figure 28 illustrates a cross-section of structure in Figure 27C following process to deposit an encapsulation layer, and deposit and pattern a first dielectric in a memory region, in at least one example. [0096] Figure 29A illustrates a cross-section of structure in Figure 22A following process to pattern an upper insulator layer in a multi-layer insulator stack, in at least one example. [0097] Figure 29B illustrates a cross-section of structure in Figure 29A, following process to form a portion of a multi-layer stack to form a capacitor, in at least one example. [0098] Figure 29C illustrates a cross-section of structure in Figure 29B following process to pattern the multi-layer stack and form capacitors, in at least one example. [0099] Figure 30A illustrates a cross-section of structure in Figure 27A following process to pattern a portion of multi-layer stack prior to forming capacitors, in at least one example. [00100] Figure 30B illustrates a cross-section of structure in Figure 30A, following process to form capacitors, in at least one example. [00101] Figure 30C illustrates a cross-section of structure in Figure 30B following process to remove a sacrificial layer from above an upper insulator layer in the multi-layer stack, in at least one example. [00102] Figure 31 illustrates a computing architecture with a coherent cache or memory- side buffer chiplet that includes a memory controller, wherein the coherent cache or memory- side buffer chiplet is coupled to an accelerator, a processor, and a memory, in accordance with some examples. [00103] Figure 32 illustrates an architecture of the coherent cache or memory-side buffer chiplet with multiple controllers and multiple cache banks, in accordance with some examples. [00104] Figure 33 illustrates an apparatus comprising memory and corresponding logic, wherein the memory comprises ferroelectric (FE) memory bit-cells, in accordance with some examples. [00105] Figure 34 illustrates a high-level architecture of an artificial intelligence (AI) machine comprising a compute die positioned on top of a memory die, in accordance with some examples. [00106] Figure 35 illustrates a 3-input majority gate using non-linear input capacitors, in accordance with some examples. Docket No.: KP12P064US-PCT [00107] Figure 36 illustrates a complex logic gate implemented using a 5-input majority gate, in accordance with some examples. DETAILED DESCRIPTION [00108] At least one example describes capacitors with encapsulation structures integrated with transistors. While at least one example is described with reference to FeRAM or paraelectric RAM, capacitive structures formed herein can be used for any application where a capacitor is desired. In at least one example, capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate. Here, numerous specific details are set forth, such as structural schemes and detailed fabrication methods to provide a thorough understanding of examples of present disclosure. It will be apparent to one skilled in art that examples of present disclosure may be practiced without these specific details. In other instances, well-known features, such as process equipment and device operations, are described in lesser detail to not unnecessarily obscure examples of present disclosure. Furthermore, it is to be understood that examples shown in Figures are illustrative representations and are not necessarily drawn to scale. [00109] In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring at least one example. Reference throughout this specification to “an example,” “one example,” “in at least one example,” or “some examples” means that a particular feature, structure, function, or characteristic described in connection with example is included in at least one example. Thus, appearances of the phrase “in an example,” “in at least one example,” or “in one example” or “some examples” in various places throughout this specification are not necessarily referring to same example of disclosure. Furthermore, particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more examples. For example, a first example may be combined with a second example anywhere particular features, structures, functions, or characteristics associated with two examples are not mutually exclusive. [00110] As used in herein, singular forms “a,” “an,” and “the” are intended to include plural forms as well, unless context clearly indicates otherwise. It will also be understood that term “and/or” as used herein refers to and encompasses all possible combinations of one or more of associated listed items. [00111] Here, “coupled” and “connected,” along with their derivatives, may be used to describe functional or structural relationships between components. These terms are not intended as synonyms for each other. Rather, in particular examples, “connected” may be Docket No.: KP12P064US-PCT used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. “Coupled” may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical, electrical, or magnetic contact with each other, and/or that two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship). [00112] Here, “over,” “under,” “between,” and “on” refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example, in context of materials, one material or material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials may be directly in contact with two layers or may have one or more intervening layers. In contrast, a first material “on” a second material is in direct contact with that second material/material. Similar distinctions are to be made in context of component assemblies. As used throughout this description, and in claims, a list of items joined by term “at least one of” or “one or more of” can mean any combination of listed terms. [00113] Here, “adjacent” here generally refers to a position of a thing being next to (e.g., immediately next to or close to with one or more things between them) or adjoining another thing (e.g., abutting it). [00114] Here, “signal” may refer to current signal, voltage signal, magnetic signal, or data/clock signal. [00115] Here, “device” may generally refer to an apparatus according to context of usage of that term. For example, a device may refer to a stack of layers or structures, a single structure or layer, a connection of various structures having active and/or passive elements, etc. Generally, a device is a three-dimensional structure with a plane along x-y direction and a height along z direction of an x-y-z Cartesian coordinate system. In at least one example, plane of device may also be plane of an apparatus which comprises the device. [00116] Unless otherwise specified in explicit context of their use, terms “substantially equal,” “about equal,” and “approximately equal” mean that there is no more than incidental variation between two things so described. Such variation is typically no more than +/-10% of a predetermined target value. [00117] Here, “left,” “right,” “front,” “back,” “top,” “bottom,” “over,” “under,” and similar terms are used for descriptive purposes and not necessarily for describing permanent relative positions. For example, terms “over,” “under,” “front side,” “back side,” “top,” “bottom,” “over,” “under,” and “on” as used herein refer to a relative position of one Docket No.: KP12P064US-PCT component, structure, or material with respect to other referenced components, structures, or materials within a device, where such physical relationships are noteworthy. These terms are employed herein for descriptive purposes only and predominantly within context of a device z-axis and therefore may be relative to an orientation of a device. Hence, a first material “over” a second material in context of a figure provided herein may also be “under” the second material if device is oriented upside-down relative to context of figure provided. Similar distinctions are to be made in context of component assemblies. [00118] Here, “between” may be employed in context of z-axis, x-axis or y-axis of a device. A material that is between two other materials may be in contact with one or both of those materials. In another example, a material that is between two or other materials may be separated from both of other two materials by one or more intervening materials. A material “between” two other materials may therefore be in contact with either of other two materials. In another example, a material “between” two other materials may be coupled to other two materials through an intervening material. A device that is between two other devices may be directly connected to one or both of those devices. In another example, a device that is between two other devices may be separated from both of other two devices by one or more intervening devices. [00119] Capacitors with a wide variety of materials have been implemented for memory (random-access memory or RAM) applications. Perovskite materials have been implemented in capacitors for high density FeRAM applications owing to their low power consumption and high on/off ratio. Perovskite FeRAM devices (herein FeRAM devices) may be useful over other forms of memory, such as magnetic tunnel junction (MTJ)-based devices, due to relatively low number of layers within a FeRAM device compared to MTJ-based devices. A typical FeRAM device may be fully operational with three layers, where a ferroelectric dielectric is contained between two electrode layers. Electrode layers within FeRAM device may also include Perovskite materials to enable lattice matching and reduction in electrical resistance. Introduction of lead-free Perovskite materials may offer additional environmental benefits without sacrificing device performance. [00120] In at least one example, FeRAM capacitors, including lead-free Perovskite materials, can be prone to damage from reaction with hydrogen during processing. Specifically, damage may be a result of hydrogen atoms traveling along grain boundaries between or along electrodes coupled with two terminals of a FeRAM capacitor. In at least one example, hydrogen can cause reduction when it reacts with one or more materials of a FeRAM capacitor, such as electrodes or ferroelectric material itself. In at least one example, Docket No.: KP12P064US-PCT FeRAM capacitors can lose their polarization hysteresis characteristics as a result of hydrogen reduction. During fabrication, sources of hydrogen may arise from anneal operations carried out to eliminate dangling bonds and may be unavoidable. [00121] In at least one example, a multi-layer stack including at least 3 layers may be deposited for fabricating capacitors. In at least one example, the deposition process can utilize high temperatures to achieve desired crystallinity. In at least one example, patterning multi-layer stack to fabricate memory devices can roughen and damage sidewalls of memory devices causing charge leakage and memory loss during operation. In at least one example, annealing memory devices can be useful. In at least one example, annealing temperatures can exceed 1100 degrees Celsius depending on materials within multi-layer stack and annealing methods utilized. In at least one example, annealing may be performed before or after stack patterning. [00122] In at least one such example, multi-layer stack can be patterned into capacitors. In at least one example, capacitor devices have a planar structure where individual layers are sequentially layered, one on top of another, and patterned into cylindrical (circular or elliptical) or rectangular shapes. In at least one example, it is useful to protect capacitor sidewalls, top, and bottom surfaces from reacting with hydrogen. In at least one example, solutions against hydrogen diffusion include forming an encapsulation layer that includes an insulating material, such as silicon nitride to protect capacitor sidewalls and top surfaces. In at least one example, encapsulation layers can provide protection against hydrogen and oxygen diffusion into capacitor. In at least one example, contact or via electrode may be formed at a top of FeRAM device by piercing through insulating barrier layer and exposing one or more top electrode materials. In at least one example, barrier layer itself may be further surrounded by additional insulating material such as an interlayer dielectric (ILD). ILD materials such as silicon oxide or silicon oxide doped with carbon in general may not act as a hydrogen diffusion barrier and are less useful when in contact with one or more layers of memory device. [00123] In at least one example, an encapsulation layer comprising materials other than silicon nitride can be deposited to protect sidewalls of capacitors and can offer enhanced flexibility in material choices. Flexibility in material choices can be important when integration schemes can include operations where one layer is removed selectively to two or more exposed layers. Typically, capacitors are coupled with a conductive electrode, a via, or a conductive interconnect from above and below. While the presence of encapsulation layer above the capacitor can be useful, further encapsulating at least a portion of a lower surface Docket No.: KP12P064US-PCT of the capacitor can be useful to prevent diffusion of hydrogen along interfaces between adjacent layers. In at least one example, the encapsulation layer can further extend under a portion of the bottom electrode that is not in contact with a conductive electrode, via or a conductive interconnect. In at least one example, when at least a portion of encapsulation layer is contact with a lower surface of a lower electrode, a substantially full encapsulation may be accomplished. In at least one example, substantially full encapsulation can create a hermetic seal. [00124] In at least one example, a capacitor can include a bottom electrode structure comprising two conductive layers, a work function layer and a sacrificial conductor. In at least one example, the sacrificial conductor can be recessed relative to the work function layer, such portions of the encapsulation layer can be present under the work function layer. In at least one example, the sacrificial conductor can have a thickness that is dictated by electrical and physical considerations. For example, sacrificial conductor can have a thickness that is governed by conductivity of the sacrificial conductor and by deposition of a minimum thickness of encapsulation layer to be sufficiently hermetic. In at least one example, the sacrificial conductor can have a minimum thickness that is equal to two times a minimum thickness of the encapsulation layer. [00125] In at least one example, the capacitor comprises a single bottom electrode, instead of a bottom electrode structure, to avoid lattice mismatch during deposition or to enable a smoother single conductive film, prior to deposition of a dielectric layer of the capacitor. In at least one such example, a conductive electrode, a via, or a conductive interconnect that is in contact with the bottom electrode of the capacitor can be raised relative to an insulator laterally adjacent to it. When an uppermost surface of the conductive electrode, the via, or the conductive interconnect is raised relative to a surrounding insulator, a portion of an encapsulation layer can be inserted under the bottom electrode structure of the capacitor. In at least one example, the uppermost surface can be raised by an amount useful to deposit the encapsulation layer. In at least one example, the uppermost surface can be raised by a minimum height that is equal to two times a thickness of the encapsulation layer. [00126] In at least one example, hydrogen can also diffuse from layers below a bottom electrode structure of the capacitor, such as through the conductive electrode, via or conductive interconnect. In at least one example, the conductive electrode, the via or the conductive interconnect can be laterally surrounded by an etch stop layer that includes a hydrogen barrier material. In at least one example, the etch stop layer includes silicon and nitrogen, or silicon, nitrogen, and carbon. In some examples, it is useful to laterally surround Docket No.: KP12P064US-PCT the conductive electrode, via or conductive interconnect with a liner for enhanced flexibility. In at least one example, the liner comprises a material that is same or substantially same as the encapsulation layer, where both the encapsulation layer and the liner comprise materials that are different from the material of the etch stop layer. In at least one example, the conductive electrode, via or conductive interconnect can include a conductive hydrogen barrier material. [00127] In other examples, hydrogen may diffuse through one or more materials of contact electrode towards FeRAM device stack through a top electrode. To protect against hydrogen diffusion through a top surface of top electrode, noble metals can be implemented as part of contact electrode structure. In at least one example, noble metals can have crystalline structures due to strong metallic bonding, and their amorphous phase is thermodynamically unstable favoring transformation into a crystalline phase. [00128] Figure 1A is an illustration of a cross-section of a device structure 100A. In at least one example, device structure 100A comprises a capacitor 102 comprising a bottom electrode structure 104, dielectric 106, and top electrode 108 on dielectric 106. Device structure 100A is further coupled with electrode structure 116. In at least one example, bottom electrode structure 104 further comprises electrode 110 and electrode 112 on electrode 110. In at least one example, electrode 110 comprises a lateral thickness WE1, and electrode 112 comprises a lateral thickness WE2, where lateral thickness WE2 is greater than lateral thickness WE1. In at least one example, WE1 is at least 5 nm less than WE2. In at least one example, a greater lateral thickness WE2 compared to lateral thickness WE1 is useful for encapsulating bottom electrode structure 104. [00129] It is useful to protect sidewalls, top, and bottom surfaces of capacitor 102 from reacting with hydrogen. In at least one example, solutions against hydrogen diffusion include implementing an insulating barrier layer such as encapsulation structure 114 to protect sidewalls, top surface, and bottom surface of capacitor 102. In at least one example, encapsulation structure 114 comprises one of: silicon nitride, carbon doped silicon nitride, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx, or TaSiOx, where ‘x’ and ‘y’ are integers (the integers may be the same or distinct). In some examples, encapsulation structure 114 can include a metal and nitrogen such as, but not limited to, AlN, ZrN, or HfN. In other examples, encapsulation structure 114 can include a metal, and both Si and O, such as AlSiOx, HfSiOx, or TaSiOx where ‘x’ is an integer. [00130] In at least one example, encapsulation structure 114 comprises portion 114A on a sidewall 110A of electrode 110 and adjacent to lowermost surface 112A. In at least one Docket No.: KP12P064US-PCT example, encapsulation structure 114 further comprises portion 114B adjacent to a sidewall 112B of electrode 112, where portion 114A and portion 114B are contiguous. In at least one example, portion 114B is further adjacent to sidewall 106A and sidewall 108A. Encapsulation structure 114 is contiguous from top electrode 108 to electrode 110. [00131] Electrode 110 has a vertical thickness TE1, that is orthogonal to the lateral thickness WE1. In at least one example, vertical thickness TE1 may be tuned depending on material of electrode 110, electrical conductivity of electrode 110, and to an extent, on a minimum lateral thickness TEC of encapsulation structure 114. A minimum lateral thickness of encapsulation structure 114 can be at least 1 nm for a contiguous film that has no pores or defects that can allow hydrogen to diffuse into capacitor 102. In at least one example, TEC can vary from top of top electrode 108 to bottom of electrode 110 and can depend on shape of capacitor 102 (for example, taper in sidewall). In general, shape of sidewall 102A of capacitor 102 is influenced by profile of individual sidewalls such as sidewall 108A, sidewall 106A, and sidewall 112B. In at least one example, outer sidewall 114C of encapsulation structure 114 can be substantially vertical, with a curved top portion, as shown. In at least one example, outer sidewall 114C of encapsulation structure 114 can be gradually tapered. [00132] In at least one example, shape of portion 114A relative to sidewall 110A can vary along the z-direction, depending on vertical thickness TE1. In at least one example, shape of portion 114A can depend on lateral thickness TECM of portion 114A. In at least one example, lateral thickness TEC of portion 114A can vary along the z-direction. Variation in lateral thickness TECM of portion 114A along the z-direction can depend on various factors such as vertical thickness TE1, lateral thickness TEC, and on whether encapsulation structure 114 is etched. In at least one example, variation in lateral thickness TECM of portion 114A can be attributed to relative thickness between vertical thickness TE1 and half of a difference between WE2 and WE1 (or ^W). In at least one example, electrode 110 and electrode 112 are substantially symmetric above a vertical axis. In at least one such example, ^W can be at least 2.0 nm or, sidewall 112B extends away from sidewall 110A by 2.0 nm. [00133] In at least one example, ^W is less than vertical thickness TE1 (as shown), and lateral thickness TEC of encapsulation structure 114 is less than half of vertical thickness TE1, and encapsulation structure 114 includes cavity 115. In at least one example, lateral thickness TEC of encapsulation structure 114 is at least a quarter of vertical thickness TE1. In at least one example, shape and size of cavity can vary with lateral thickness TECM, and with ^W. In at least one example, ^W is greater than vertical thickness TE1, and lateral thickness TEC of Docket No.: KP12P064US-PCT encapsulation structure 114 is less than half of vertical thickness TE1, as shown in device structure 100B of Figure 1B. In at least one such example, cavity 115 within portion 114A is more elongated compared to cavity 115 in Figure 1A. [00134] In at least one example, cavity 115 can be reduced or eliminated entirely when lateral thickness TEC of encapsulation structure 114 approaches at least half of vertical thickness TE1, as shown in device structure 100C of Figure 1C. In at least one such example, encapsulation structure 114 within portion 114A is merged as indicated by seams (dashed lines 117). In at least one example, portion 114A comprises an outer sidewall 114D that is substantially co-linear with sidewall 114C. In at least one such example, lateral thickness TECM of portion 114A is substantially uniform along vertical thickness TE1 of electrode 110. [00135] Referring again to Figure 1A, in at least one example, electrode structure 116 is laterally surrounded by etch stop layer 118. In at least one example, electrode structure 116 is at a same level as 118//. In at least one example, surface 116B is at least co-planar or substantially co-planar with surface 118A. In at least one example, surface 118A can be recessed below surface 116B. In at least one example, etch stop layer 118 includes one Si, Ni, and O, or Si and Ni, or Si Ni, and C, or Si, Ni, O, and C. In at least one example, electrode structure 116 includes a material that is different from material of encapsulation structure 114. In at least one example, electrode structure 116 may also act as an oxygen diffusion barrier. Depending on magnitude of lateral thickness WES of electrode structure 116 relative to lateral thickness WE1, portion of electrode structure 116 may be in contact with encapsulation structure 114. In at least one example, WES is less than WE1, and uppermost surface of electrode structure 116 is not in contact with portion 114A. In at least one example, WES is greater than WE1 (as indicated by dashed lines 123) and uppermost surface of electrode structure 116 is in contact with portion 114A. [00136] In at least one example, electrode structure 116 includes a conductive hydrogen barrier 120 and a conductive fill 122. In at least one example, conductive hydrogen barrier 120 and etch stop layer 118 form a dual hydrogen barrier below device structure 100A. In at least one example, conductive hydrogen barrier 120 includes a material that is amorphous. In at least one example, amorphous materials lack defined grain boundaries that facilitate hydrogen diffusion and are thus useful. Examples of conductive hydrogen barrier 120 include one of: TiAlN with >30 atomic percent AlN, TaN with >30 atomic percent N, TiSiN with >20 atomic percent SiN, Ta carbide (TaC), Ti carbide (TiC), tungsten carbide (WC), tungsten nitride (WN), carbonitrides of Ta, Ti, W, i.e., TaCN, TiCN, WCN, titanium monoxide (TiO), titanium oxide Ti2O, tungsten oxide (WO3), tin oxide (SnO2), indium tin oxide (ITO), iridium Docket No.: KP12P064US-PCT oxide, indium gallium zinc oxide (IGZO), zinc oxide, or METGLAS series of alloys, e.g., Fe40Ni40P14B6 (METGLAS is a Honeywell TM). In at least one example, conductive hydrogen barrier 120 has a thickness of at least 2.0 nm. [00137] In at least one example, conductive fill 122 may include a material such as tantalum, titanium, ruthenium, tungsten, molybdenum, or copper. In some examples, when WES is greater than WES1, electrode structure 116 may not include a material such as copper to prevent sputtering of the copper during fabrication of the device structure 100A. [00138] In at least one example, top electrode 108 is a conductive metal oxide that includes one of the conducting perovskite metallic oxides exemplified by: La-Sr-CoO3, SrRuO3, La-Sr-MnO3, YBa2Cu3O7, Bi2Sr2CaCu2O2, LaNiO3, and ReO3. In at least one example, electrode 112 is a conductive metal oxide that includes one of the conducting perovskite metallic oxides exemplified by: La-Sr-CoO3, SrRuO3, La-Sr-MnO3, YBa2Cu3O7, Bi2Sr2CaCu2O2, LaNiO3, and ReO3. In at least one example, top electrode 108 and electrode 112 include a same material. In at least one example, top electrode 108 and electrode 112 are asymmetric or comprise materials having different work functions. [00139] In at least one example, dielectric 106 is of form ABO3, where A and B are two cations of different sizes and O is Oxygen. In at least one such example, “A” includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na; and “B” includes one of Ti, Mn, Fe, Ta, or Nb. In at least one example, dielectric 106 can be doped, e.g., by one or more elements from lanthanide series of periodic table, or one or more elements of 3d, 4d, 5d, 6d, 4f, or 5f series of periodic table. In at least one example, perovskites can be suitably doped to achieve a spontaneous distortion in a range of 0.3% to 2%. In at least one example, in chemically substituted lead titanate such as Zr in Ti site or La, Nb in Ti site, concentration of these substitutes is such that it achieves spontaneous distortion in range of 0.3% to 2%. In at least one example, lead-based Perovskite material includes lead zirconium titanate (PZT) or PZT with a first doping material, wherein doping material is one of La or Nb. In at least one example, non-Pb perovskites can also be doped, e.g., by La or Lanthanides. Non-Pb perovskite material can include one or more of La, Sr, Co, Cr, K, Nb, Na, Sr, Ru, Y, Fe, Ba, Hf, Zr, Cu, Ta, Bi, Ca, Ti, or Ni. In at least one example, non-Pb Perovskite material includes one of: BaTiO3, KNbO3, or NaTaO3. [00140] In at least one example, dielectric 106 includes a low voltage ferroelectric material. Low voltage FE materials can be of form ABB'O3, where “A” includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na; Docket No.: KP12P064US-PCT “B” includes one of Mn, Fe, Ta, or Nb; and “B'” includes one of: Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, or Zn. [00141] In at least one example, where dielectric 106 has the form AA'BO3, “A” includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na; “B” includes one of Mn, Fe, Ta, or Nb; “A'” includes one of Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, or Lu. In at least one example, A' comprises a valency of site A, but different ferroelectric polarizability from A. Voltage below 3 volts is sufficiently low to be characterized as low voltage. [00142] In at least one example, dielectric 106 includes bismuth ferrite (BFO) with a second doping material, wherein the second doping material is one of lanthanum, elements from lanthanide series of a periodic table, or elements of 3d, 4d, 5d, 6d, 4f, or 5f series of periodic table. In at least one example, BFO is doped with Mn or Sc, wherein Mn or Sc achieve a spontaneous distortion in BFO in a range of 0.3% to 2%. [00143] In at least one example, dielectric 106 includes a relaxor ferroelectric material. In at least one example, relaxor ferroelectric material is a BaTiO₃ (BTO) based relaxor which includes one of: BaTiO₃-Bi(Zn₁/₂Ti₁/₂)O₃ (BTO-BZT), BaTiO₃-BiScO₃ (BTO-BS), BiScO₃, Ba(₁-x)SrxTiO₃ (BST), BaTiO₃-Pb(Mg₁/₃Nb₂/₃)O₃ (BTO-PMN), BaTi(1-x)ZrxO₃ (BTZ), BaTiO₃- Pb(Zn₁/₃Nb₂/₃)O₃ (BTO-PZN), or BaTiO₃-Pb(Sc₁/₂Nb₁/₂)O₃ (BTO-PSN). [00144] In at least one example, relaxor ferroelectric material is a PZT based relaxor which includes one of: PZT-Pb(Mg₁/₃Nb₂/₃)O₃ (PZT-PMN), PZT-Pb(Ni₁/₃Nb₂/₃)O₃ (PZT- PNN), PZT-Pb(Zn₁/₃Nb₂/₃)O₃ (PZT-PZN), PZT-Pb(Sc₁/₂Nb₁/₂)O₃ (PZT-PSN), PZT- Pb(Fe₁/₂Nb₁/₂)O₃ (PZT-PFN), PZT- PbxLa1-x(ZryTi1-y)O3 (PZT-PLZT), where 0 ≤ x ≤ 1 and where 0 ≤ y ≤ 1, or PZT-PbTi(1-x)Mn(x)O₃ (PZT-PTM), where 0 ≤ x ≤ 1. [00145] In at least one example, relaxor ferroelectric material is a SrBi₂Ta₂O₉, (SBT) based relaxor which includes one of: paraelectric SBT-SrBi₂[Nb(1-x)Ta(x)]₂O₉ (SBT-SBNT), where 0 ≤ x ≤ 1, SBT doped with transition metals such as Mn, Fe, or Co; SBT doped with rare earth ions such as La, Ce, or Nd; or SBT doped with alkaline earth metals with Ba or Ca. [00146] In at least one example, relaxor ferroelectric material is based on lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or Barium titanium-barium strontium titanium (BT- BST). [00147] In at least one example, dielectric 106 includes hexagonal ferroelectrics of a type h-RMnO3, where R is a rare earth element which includes one of: cerium (Ce), dysprosium Docket No.: KP12P064US-PCT (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y); hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides, or their alloyed oxides. In at least one example, dielectric 106 includes a hexagonal ferroelectric which includes one of: YMnO3 or LuFeO3. In at least one example, dielectric 106 includes hafnium oxide of form Hf(1-x)ExOy, where 'x' and ‘y’ are fractions (the fractions can be equal or distinct) and where E includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y. [00148] In at least one example, dielectric 106 includes Al(1-x)ScxN, Ga(1-x)ScxN, Al(1- x)Y(x)N where ‘x’ and ‘y’ are respective compositional fractions or Al(a)Mg(b)Nb(c)N, where a, b, and c are respective compositional fractions. In at least one example, dielectric 106 includes one of: LiNbO3, LiTaO3, LiTaO2F2, or Sr(^)Ba(1-x)Nb₂O₆ where 0.32≤x≤0.8, or KSr2Nb5O15. [00149] In at least one example, dielectric 106 comprises multiple layers, for example, alternating layers of [Bi2O2]2+, and pseudo-perovskite blocks (Bi4Ti3O12 and related Aurivillius phases), with perovskite layers that are ‘n’ octahedral layers. In at least one example, examples of multiple layers include improper ferroelectric material. An improper ferroelectric is a ferroelectric where primary order parameter is an order mechanism such as strain or buckling of atomic order. In at least one example, improper ferroelectric material includes an epitaxial bilayer stack including one of: [barium titanate/strontium titanate]n or [lanthanum aluminate/ strontium titanate]n, wherein ‘n’ represents a number of bilayers, and wherein ‘n’ is between 1 and 100. [00150] While various examples here are described with reference to ferroelectric material for storing charge state, at least one example may also be applicable for paraelectric material, anti-ferroelectric material, or a combination of them. [00151] In at least one example, dielectric 106 includes LuFeO3 class of materials or super lattice of ferroelectric and paraelectric materials. In at least one example, f-orbital materials (e.g., lanthanides) are doped to ferroelectric material of dielectric 106 to make a paraelectric material. [00152] In at least one example, dielectric 106 includes a paraelectric material. In at least one example, paraelectric material is a BaTiO₃ (BTO) based paraelectric which includes one of: BaTiO₃-Bi(Zn₁/₂Ti₁/₂)O₃ (BTO-BZT), BaTiO₃-BiScO₃ (BTO-BS): BiScO₃, Ba1-xSrxTiO₃ (BST), BaTiO₃-Pb(Mg₁/₃Nb₂/₃)O₃ (BTO-PMN), BaTi1-xZrxO₃ (BTZ), BaTiO₃- Pb(Zn₁/₃Nb₂/₃)O₃ (BTO-PZN), BaTiO₃-Pb(Sc₁/₂Nb₁/₂)O₃ (BTO-PSN). Docket No.: KP12P064US-PCT [00153] In at least one example, paraelectric material is a PZT based paraelectric which includes one of: PZT-Pb(Mg₁/₃Nb₂/₃)O₃ (PZT-PMN), PZT-Pb(Ni₁/₃Nb₂/₃)O₃ (PZT-PNN), PZT-Pb(Zn₁/₃Nb₂/₃)O₃ (PZT-PZN), PZT-Pb(Sc₁/₂Nb₁/₂)O₃ (PZT-PSN), PZT-Pb(Fe₁/₂Nb₁/₂)O₃ (PZT-PFN), PZT- PbxLa1-x(ZryTi1-y)O3 (PZT-PLZT), where 0 ≤ x ≤ 1 and where 0 ≤ y ≤ 1, or PZT-PbTi(1-x)Mn(x)O₃ (PZT-PTM), where 0 ≤ x ≤ 1. [00154] In at least one example, paraelectric material is a SrBi₂Ta₂O₉ (SBT) based paraelectric which includes one of: SBT-SrBi₂[Nb(1-x)Ta(x)]₂O₉ (SBT-SBNT), where 0 ≤ x ≤ 1, SBT doped with transition metals such as Mn, Fe, Co; SBT doped with rare earth ions such as La, Ce, or Nd; or SBT doped with alkaline earth metals with Ba or Ca. In at least one example, room temperature paraelectric materials include: SrTiO3, BaxSryTiO3, HfZrO2, or Hf-Si-O. [00155] In at least one example, dielectric 106 includes an anti-ferroelectric material. In at least one example, antiferroelectric material may include one of: an antiferroelectric material comprising one of: HfSiO2 doped with >30% Si or >30% Zr; HfZrO2 doped with >30% Si or >30% Zr; ZrO2 or NaNbO3; NaNbO3, PbZrO3, or PbZrO3 doped with >5% K; a first solid solution including one of: PbTiO3, SrTiO3, PbHfO3, PbHfO3, Pb(Lu0.5Nb0.5)O3, Pb(Lu0.5Nb0.5)O3, Pb(Yb0.5Nb0.5)O3, AgNbO3 or NaNbO3; or a second solid solution including PbTiO3 and one of: SrTiO3, PbHfO3, PbHfO3, Pb(Lu0.5Nb0.5)O3, Pb(Lu0.5Nb0.5)O3, Pb(Yb0.5Nb0.5)O3, AgNbO3 or NaNbO3. [00156] Figure 1D is an illustration of a cross-section of device structure 100D that has one or more properties of device structure 100A, such as capacitor 102 and electrode structure 116. In at least one example, device structure 100D further comprises encapsulation structure 124, where 124 has one or more features such as, structure and material of encapsulation structure 114, (Figure 1A). In at least one example, encapsulation structure 124 comprises portion 124A adjacent to sidewall 110A and lowermost surface 112A, portion 124A adjacent to sidewall 102A of capacitor 102, where portion 124A comprises an outer sidewall 124C. In at least one example, portions 124A and 124B have features of portions 114A and 114B (Figure 1A). In at least one example, encapsulation structure 124 further comprises portion 124D that extends laterally on etch stop layer 118. In at least one example, portion 124D laterally extends beyond outer sidewall 124C. In at least one example, portion 124D is contiguous with portion 124A. [00157] In at least one example, portion 124D has vertical thickness TECV, where vertical thickness TECV can be the same as lateral thickness TEC of portion 124B. In at least one example, top surface 124E of portion 124B can be flat, as shown. A top surface 124E that is Docket No.: KP12P064US-PCT substantially planar may be indicative of a process operation utilized, such as for example a planarization process. In at least one example, encapsulation structure 124 further includes portion 124F that is contiguous with portion 124B, where portion 124F is on a top surface of top electrode 108 and on top surface of portion 124B. In at least one example, portion 124F has a vertical thickness TECV that is same or substantially same as vertical thickness TECV of portion 124D, lateral thickness TEC of portion 124B, or lateral thickness TECM of portion 124A. In at least one example, encapsulation structure 124 fully encapsulates capacitor 102. [00158] In at least one example, device structure 100C can also include features of encapsulation structure 124 described in Figure 1D. Figure 1E is an illustration of a cross- section of device structure 100E where, encapsulation structure 124 further comprises portion 124D that extends laterally on encapsulation structure 124. In at least one example, portion 124D has a thickness TEC that is substantially the same as lateral thickness TEC of portion 124B. [00159] In at least one example, top portion of encapsulation structure 124 has top surface 124E that is flat, as shown. A flat surface may be indicative of a process operation utilized, such as a planarization process. In at least one example, encapsulation structure 124 further includes portion 124F that is contiguous with portion 124B, where portion 124F is on a top surface of top electrode 108. In at least one example, portion 124F has a thickness TECF that is same or substantially same as lateral thickness TEC of portion 124B, and vertical thickness of portion 124D. In at least one example, portion 124F has a thickness TECF that is less than lateral thickness TEC of portion 124B, and less than vertical thickness TEC of portion 124D. [00160] Figure 1F is an illustration of a cross-section of device structure 100F where electrode 112 (Figure 1A) is replaced by a bilayer electrode 130, in at least one example. In at least one example, bilayer electrode 130 comprises electrode 131 and electrode 132 on electrode 131. In at least one example, portion 114A of encapsulation structure 114 is in contact with a lowermost surface 131A of electrode 131. In at least one example, portion 114B is adjacent to sidewall 131B and sidewall 132B. [00161] In at least one example, electrode 131 comprises one of: Ir, Pt, Ru, IrOx, PtOx, RuOx, where ‘x’ is an integer, or conductive oxide metals that have self-limiting oxidation. In at least one example, electrode 132 can include one of: La-Sr-CoO3, SrRuO3, La-Sr-MnO3, YBa2Cu3O7, Bi2Sr2CaCu2O2, LaNiO3, and ReO3. In at least one example, electrode 110 includes one of: niobium, chromium, molybdenum, tantalum, tungsten, rhenium, titanium, nitrogen doped variants of niobium, chromium, molybdenum, tantalum, tungsten, rhenium, Docket No.: KP12P064US-PCT titanium, AlN doped variants and SiN doped variants having electrically conductive properties. [00162] Figure 1G is an illustration of a cross-section of device structure 100G where electrode 110 (Figure 1A) is replaced by a bilayer electrode 140, in at least one example. In at least one example, bilayer electrode 140 includes electrode 141 and electrode 142 on electrode 141. In at least one example, bilayer electrode 140 is laterally surrounded by encapsulation structure 114. In at least one example, portion 114A is in contact with sidewall 141B and sidewall 142B. [00163] In at least one example, electrode 141 includes one of Ta, Ti, W, Cr, Nb, Mo, nitrogen doped variants, AlN doped variants, or doped variants having electrically conductive properties. In at least one example, electrode 141 includes one of: Ir, Pt, Ru, IrOx, PtOx, RuOx, where ‘x’ is an integer, or conductive oxide metals that have self-limiting oxidation. [00164] Figure 2A is an illustration of a cross-section of device structure 200A. In at least one example, device structure 200A includes features of device structure 100A such as capacitor 102, encapsulation structure 114, and electrode structure 116. In at least one example, device structure 200A further comprises liner 202 between etch stop layer 118 and electrode structure 116. In at least one example, liner 202 comprises one of: silicon nitride, carbon doped silicon nitride, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx, or TaSiOx, where ‘x’ and ‘y’ are integers (where the integers can be same or distinct). In at least one example, liner 202 comprises a same material as encapsulation structure 114, but different from material of etch stop layer 118. Inclusion of liner 202 provides flexibility in choice of material for etch stop layer 118 and liner 202, as will be discussed further below. [00165] In at least one example, depending on relative size of electrode 110 and electrode structure 116, liner 202 can be in contact with at least a portion of encapsulation structure 114. In at least one example, electrode 110 is confined within a planar cross-sectional area (on X-Y plane) or plan view perimeter of electrode structure 116. In at least one example, WES is less than WES1 along the X-direction. In at least one such example, liner 202 is in contact with encapsulation structure 114, such as is shown. In at least one example, liner 202 combined with encapsulation structure 114 form a diffusion barrier against hydrogen penetration. In at least one example, encapsulation structure 114 extends on an uppermost surface of liner 202. [00166] In at least one example, liner 202 has a planar top surface. In at least one example, liner 202 can have a tapered portion away from sidewall 116A (as indicated by dashed lines 203). A tapered portion is indicative of a process operation utilized to obtain liner 202. In at Docket No.: KP12P064US-PCT least one example, liner 202 can be implemented in device structure 100A and device structure 100C described in association with Figures 1A and 1C. [00167] Figure 2B is an illustration of a cross-section of device structure 200B, that includes a plurality of capacitors 204. In at least one example, plurality of capacitors 204 include capacitor 206A and capacitor 206B. In at least one example, capacitor 206A and capacitor 206B include features of capacitor 102 (Figure 1A). In at least one example, device structure 200B further includes encapsulation structure 124 that extends continuously between capacitor 206A and capacitor 206B. In at least one example, capacitor 206A and capacitor 206B are separated by a minimum of 20 nm. In at least one example, where encapsulation structure 124 extends continuously between capacitor 206A and capacitor 206B, encapsulation structure 124 can also include portion 124F on top electrode 108. In at least one example, top surface 124E of encapsulation structure 124 are coplanar or substantially coplanar with uppermost surface 108B. [00168] Figure 3A is an illustration of a cross-section of device structure 300A, that includes spacer 302 between encapsulation structure 304 and sidewall 102A. In at least one example, implementation of spacer 302 can be useful to protect dielectric 106. In at least one example, spacer 302 can includes a material of encapsulation structure 114. In at least one example, spacer 302 substantially follows a contour of sidewall 102A. In at least one example, where sidewall 102A is substantially vertical, spacer 302 comprises sidewall 302A that is substantially vertical and sidewall 302B that is tapered. In at least one such example, spacer 302 has a lateral thickness TI that decreases from base of electrode 112 to top of top electrode 108. In at least one example, lateral thickness TI of spacer 302 reaches a maximum value adjacent to lowermost surface 112A. In at least one example, when sidewall 102A is tapered, lateral thickness TI of spacer 302 can reach a maximum value adjacent to uppermost surface 108B. In at least one example, lowermost surface 302C of spacer 302 can extend below lowermost surface 112A as indicated by dashed lines 305. [00169] In at least one example, device structure 300A further comprises encapsulation structure 304. In at least one example, encapsulation structure 304 includes features such as portions of structure and material of encapsulation structure 114 (Figure 1A). For example, encapsulation structure 304 comprises portion 304A and contiguous portion 304B under lowermost surface 112A. In at least one example, portion 304A is adjacent to sidewall 302B of spacer 302 and portion 304B of encapsulation structure 304 is adjacent to sidewall 110A. In at least one example, portion 304B is also in contact with lowermost surface 302C and in contact with portion of lowermost surface 112A. In at least one example, portion 304B has Docket No.: KP12P064US-PCT one or more features of portion 114A as described in association with Figure 1A. In at least one example, portion 304B comprises a minimum lateral thickness TMS that is less than half of vertical thickness TE1. In at least one such example, cavity 307 can extend under spacer 302. In at least one example, when portion 304B comprises a minimum lateral thickness TMS that is at least equal to half of vertical thickness TE1, size of cavity 307 can be reduced or eliminated. In at least one example, sidewall 304C of encapsulation structure 304 may have a curvature that matches with curvature of sidewall 302B. In at least one example, where sidewall 302A is substantially tapered, sidewall 302B and sidewall 304C may be substantially vertical depending on lateral thickness TI and lateral thickness TM1. In at least one example, encapsulation structure 304 can include a material of spacer 302. In at least one example, encapsulation structure 304 can include a material that is different from material of spacer 302. [00170] Figure 3B is an illustration of a cross-section of device structure 300B, where portion 304B does not include a cavity 307 (Figure 3A) and where different portions of encapsulation structure 304 can have different thicknesses. In at least one example, portion 304A has a lateral thickness TM1 as measured from sidewall 302B, and portion 304A has a vertical thickness TECV as measured from lowermost surface 112A to a mid-point of TE1. In at least one example, vertical thickness TECV can be greater than or less than lateral thickness TM1. In at least one example, vertical thickness TECV can be equal to lateral thickness TM1. [00171] Figure 4A is an illustration of a cross-section of device structure 400A. In at least one example, device structure 400A includes features of device structure 100A, such as electrode 112, dielectric 106, and top electrode 108. In at least one example, electrode 112, dielectric 106, and top electrode 108 are components of capacitor 402. In at least one example, device structure 400A further comprises encapsulation structure 404. In at least one example, encapsulation structure 404 comprises portion 404A where portion 404A is on sidewall 108A, on sidewall 106A, and on sidewall 112B. In at least one example, encapsulation structure 404 further comprises portion 404B, where portion 404B is adjacent to at least a portion of a sidewall 116A and extends from uppermost surface 118A to lowermost surface 112A. [00172] In at least one example, at least a lower portion of electrode structure 116 is laterally surrounded by etch stop layer 118. In at least one such example, uppermost surface 116B of electrode structure 116 is above uppermost surface 118A of etch stop layer 118. In at least one example, sidewall 112B extends laterally beyond sidewall 116A. In at least one example, a cavity bounded by sidewall 116A, lowermost surface 112A, and uppermost Docket No.: KP12P064US-PCT surface 118A is filled by portion 404B of encapsulation structure 404. In at least one example, portion 404A and portion 404B are contiguous. [00173] In at least one example, electrode 112 comprises a lateral thickness WE2, and electrode structure 116 comprises a lateral thickness WES where WE2 is greater than WES. In at least one example, WES is at least 5 nm less than WE2. As shown, lowermost surface 112A is vertically separated from uppermost surface 118A of etch stop layer 118 by spacing TES. In at least one example, shape of portion 404B relative to sidewall 116A can vary along the z- direction. For example, lateral thickness TEC1 of portion 404B can vary along the z-direction, depending on spacing TES on lateral thickness TEC of portion 404A and on whether encapsulation structure 404 is etched. In at least one example, variation in lateral thickness TEC1 can depend on relative thickness between spacing TES and half the difference between WE2 and WE1 or ^W. In at least one example, ^W can be at least 2.0 nm. In at least one example, electrode 112 and electrode structure 116 are substantially symmetric above a vertical axis. In at least one such example, sidewall 112B extends away from sidewall 116A by 2.0 nm. [00174] In at least one example, where spacing TES is approximately equal to two times lateral thickness TEC of portion 404A, portion 404B fills a space spanned between electrode 112 and uppermost surface 118A, such as is shown. In at least one example, spacing TES is sufficiently large for portion 404B to not fill space spanned by uppermost surface 118A and lowermost surface 112A. In at least one such example, portion 404B comprises features of portion 114A (Figure 1A). [00175] In at least one example, shape of portion 404A can change along the z-direction. In at least one example, shape of portion 404A, for example, curvature of outer sidewall 404C, can depend on the shape of sidewall 402A of capacitor 402. In at least one example, curvature of outer sidewall 404C follows a contour of sidewall 402A. In at least one example, outer sidewall 404C of encapsulation structure 404 is substantially vertical, where sidewall 402A is substantially vertical, as shown. In at least one example, outer sidewall 404C can be tapered or curved. In at least one example, encapsulation structure 404 includes a material of encapsulation structure 114 (Figure 1A). [00176] Figure 4B is an illustration of a cross-section of device structure 400B where encapsulation structure 404 further comprises portion 404D that extends laterally on etch stop layer 118. Portion 404D comprises a vertical thickness TEC2. In at least one example, vertical thickness TEC2 and/or lateral thickness TEC can be independent of spacing TES. In at least one Docket No.: KP12P064US-PCT example, vertical thickness TEC2 can be substantially same as spacing TES. In at least one example, TEC2 can be greater than or less than spacing TES. [00177] In at least one example, top surface 404E of portion 404A can be flat, as shown. A flat surface may be indicative of a process operation utilized, such as a planarization process. In at least one example, encapsulation structure 404 further includes portion 404F that is contiguous with portion 404A, where portion 404F is on a top surface of top electrode 108 and on top surface 404E. Portion 404F has a vertical thickness TEC3. In at least one example, vertical thickness TEC3, can be same or substantially same as vertical thickness TEC2 of portion 404D and lateral thickness TEC of portion 114B. In at least one example, vertical thickness TEC3 can be less than vertical thickness TEC2 of portion 404D and lateral thickness TEC of portion 114B. [00178] Figure 4C is an illustration of a cross-section of device structure 400C, where electrode structure 116 is laterally surrounded by liner 406, in at least one example. In at least one example, liner 406 has one or more properties of liner 202 (Figure 2A). In at least one example, liner 406 comprises one of: silicon nitride, carbon doped silicon nitride, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx, or TaSiOx. In at least one example, liner 406 extends from level of a lowermost surface 116C to uppermost surface 116B and is in contact with lowermost surface 112A. In at least one example, liner 406 is directly between sidewall 116A and portion 404B. In at least one example, liner 406 is also directly between sidewall 116A and etch stop layer 118. In at least one example, liner 406 comprises a same material as encapsulation structure 404 but is different from material of etch stop layer 118. Inclusion of liner 202 provides flexibility in choice of material for etch stop layer 118. In at least one example, where liner 406 is present, etch stop layer can include a material that includes oxygen. Liner 406 has a width WL. In at least one example, width WL can be less than spacing between sidewall 116A and sidewall 402A. In at least one example, implementing liner 406 reduces lateral thickness TEC1. In at least one example, implementing liner 406 can increase ^W. In at least one example, liner 406 may be implemented in device structure 300A (Figure 3A), device structure 300B (Figure 3B), or device structure 400B (Figure 4B). In at least one embodiment, outer sidewall 408C is substantially vertical. In at least one embodiment, profile of outer sidewall 408C can be dependent on profile of sidewall 112B, sidewall 106A and sidewall 108A. [00179] Figure 4D illustrates a cross-section of device structure 400D. In at least one example, device structure 400D includes one or more properties of device structure 400A Docket No.: KP12P064US-PCT illustrated in Figure 4A.Referring collectively to Figures 4A and 4D, in at least one example, device structure 400D includes encapsulation structure 408 adjacent to capacitor 402 and electrode structure 116. In at least one example, encapsulation structure 408 includes features and material of encapsulation structure 404. [00180] In at least one example, spacing TES is greater compared to spacing TES in structure 400A. In at least one example, spacing TES is greater than a lateral thickness TECM of portion 408A or lateral thickness TEC of portion 408B. In at least one example, lateral thickness TECM of portion 408A varies with spacing TES. In at least one example, lateral thickness TECM is at least a quarter of spacing TES adjacent to a portion of sidewall 116A. In at least one example, depending on lateral thickness TECM, portion 408A may include a cavity. In at least one example, when lateral thickness TEC or TECM is at least a quarter of spacing TES, portion 408A includes cavity 409. [00181] Figure 4E is an illustration of a cross-section of device structure 400E, that includes a plurality of capacitors 410. In at least one example, plurality of capacitors 410 include capacitor 412A and capacitor 412B. In at least one example, capacitor 412A and capacitor 412B include features of capacitor 402 (Figure 4A). In at least one example, capacitor 412A and capacitor 412B are separated by a minimum of 20 nm. In at least one example, device structure 400E further includes encapsulation structure 404 that extends continuously between capacitor 412A and capacitor 412B. In at least one example, where encapsulation structure 124 extends continuously between capacitor 412A and capacitor 412B, encapsulation structure 404 includes portion 404D on top electrode 108. In at least one example, top surface 404E of encapsulation structure 404 are coplanar or substantially coplanar with uppermost surface 108B. In at least one example, depending on thickness TEC, encapsulation structure 404 can include curved portions (indicated by dashed lines 411) adjacent to electrode 112. [00182] Figure 5 is a flow diagram for method 500 to fabricate a device structure such as device structure 100A (Figure 1A), in at least one example. In at least one example, method 500 begins at operation 510 with forming of a transistor above a substrate. In at least one example, method 500 continues at operation 520 with formation of an electrode structure above transistor, where the electrode structure is electrically coupled with the transistor. In at least one example, method 500 continues at operation 530 with formation of a material layer stack, including a non-linear polar material, on the electrode structure. In at least one example, method 500 continues at operation 540 by recessing a lower layer relative to an upper layer within a bottom electrode structure of the capacitor. In at least one example, Docket No.: KP12P064US-PCT method 500 ends at operation 550 by forming a spacer adjacent to the bottom electrode structure, where the spacer is in contact with a lowermost surface of the upper layer. [00183] Figure 6A illustrates a cross-section of structure 600A. In at least one example, structure 600 is a cross sectional illustration of fin 601, formed on substrate 602. In at least one example, mask 603 is formed on substrate 602. In at least one example, mask 603 includes a dielectric material. In at least one example, mask 603 may be formed by a lithographic pattern on dielectric material. In at least one example, a plasma etch process is utilized to etch material of substrate 602 to form fin 601. In at least one example, fin 601 may be substantially vertical as is shown. In at least one example, substrate 602 includes silicon, silicon germanium, germanium, or a suitable material that can be utilized to pattern and dope to form source and drain structures applicable for a transistor. [00184] Figure 6B illustrates an isometric view of structure 600B. In at least one example, structure 600B is an isometric illustration of structure 600A in Figure 6A, following process to form dielectric 604 adjacent to a portion of fin 601. In at least one example, dielectric 604 is blanket deposited on mask 603 (not shown), on sidewalls of fin 601, and on substrate 602. In at least one example, dielectric 604 is planarized post deposition. In at least one example, planarization process includes a chemical mechanical planarization process (CMP). In at least one example, CMP process removes mask 603 from above fin 601. In at least one example, dielectric 604 is then recessed to obtain a desired height of fin 601. Dielectric 604 can provide electrical isolation for portions of a gate electrode to be formed. A profile of dielectric 604 that is recessed relative to uppermost surface 601A of fin 601, is shown in enhanced cross sectional illustration 606. [00185] Figure 6C illustrates an isometric view of structure 600C. In at least one example, structure 600C is an isometric illustration of structure 600B in Figure 6B, following formation of dummy gate 605 on fin 601, in at least one example. In at least one example, dummy gate dielectric layer 607 is deposited on fin 601 and on dielectric 604. In at least one example, dummy gate dielectric layer 607 is grown by a plasma enhanced chemical vapor deposition (PECVD) process, chemical vapor deposition (CVD) or an atomic layer deposition (ALD) process. In at least one example, dummy gate dielectric layer 607 includes a layer of silicon dioxide adjacent to fin 601. [00186] In at least one example, a dummy gate material is blanket deposited on dummy gate dielectric layer 607. In at least one example, dummy gate material includes a chemical vapor deposition process to deposit a material such as polysilicon, amorphous silicon, or silicon germanium. In at least one example, deposition process can take place at temperatures Docket No.: KP12P064US-PCT of approximately 600 degrees Celsius or less. In at least one example, such as is shown, a planarization process may be performed to planarize dummy gate material after deposition. [00187] In at least one example, a mask material is deposited on dummy gate material. In at least one example, mask material includes a silicon nitride or a silicon oxynitride. In at least one example, mask material is patterned by a lithographic process and etched by a plasma etch process to form hardmask 608. In at least one example, hardmask 608 is subsequently utilized to etch dummy gate material to form dummy gate 605. In at least one example, dummy gate dielectric layer 607 is removed from surfaces of fin 601 after formation of dummy gate 605. [00188] In at least one example, after formation of dummy gate 605, spacer 610 is formed on sidewalls of dummy gate 605. In at least one example, an encapsulation layer is blanket deposited on fin 601, and on dummy gate 605. In at least one example, encapsulation layer is then etched to form spacer 610 on sidewalls of dummy gate 605. In at least one example, encapsulation layer may be removed from sidewalls of fin 601 by a masking and etching process so that spacer 610 is substantially formed on sidewalls of dummy gate 605 and on a portion of sidewalls of fin 601 adjacent to dummy gate 605. In at least one example, it is useful to remove encapsulation layer from sidewalls 601B of fin 601 to provide effective growth of epitaxial source and drain material in a downstream operation. [00189] Figure 6D illustrates an isometric view of structure 600D. In at least one example, structure 600D is an isometric illustration of structure 600C in Figure 6C, following process to form source structure 612 and drain structure 614, in at least one example. In at least one example, portions of fin 601 are etched and removed. In at least one example, shape of fin 601 is indicated by dashed lines 609. [00190] In at least one example, an epitaxial growth process is utilized to selectively grow source structure 612 and drain structure 614 on fin 601 as shown. In at least one example, source structure 612 and drain structure 614 are grown to have faceted sidewalls by an epitaxial growth process. In at least one example, dopants may be implanted during epitaxial growth process or implanted at a later operation. In at least one example, spacer 610 and hardmask 608 can prevent epitaxial growth from taking place on dummy gate 605. In at least one example, sidewall 605A of dummy gate 605 is exposed for illustrative purposes only, spacer 610 encapsulates all sidewalls 605A of dummy gate 605. In at least one example, epitaxial growth process may be carried out at temperatures between 200 degrees Celsius and 700 degrees Celsius to grow source structure 612 and drain structure 614 doped with Si, amorphous silicon or SiGe. Docket No.: KP12P064US-PCT [00191] Figure 6E illustrates an isometric view of structure 600E. In at least one example, structure 600E is an isometric illustration of structure 600D in Figure 6D, following process to remove hardmask 608, dummy gate 605, and dummy gate dielectric layer 607, in at least one example. In at least one example, dielectric 616 is blanket deposited on source structure 612 and drain structure 614, on dielectric 604, spacer 610 and hardmask 608 (Figure 6D). In at least one example, dielectric 616 can include silicon and one or more of oxygen, nitrogen, or carbon, and may be deposited by a chemical vapor deposition (CVD), or a plasma enhanced chemical vapor deposition (PECVD) process. In at least one example, dielectric 616 is planarized by a CMP process. In at least one example, CMP process may remove hardmask 608. In at least one example, an etch process may be utilized to remove hardmask 608, and portions of dummy gate 605 after partial competition of CMP process. In at least one example, a wet chemical process is utilized to selectively remove dummy gate 605, as well as dummy gate dielectric layer 607 selective to dielectric 604, spacer 610, fin 601, and dielectric 616. In at least one example, process of removing dummy gate 605 forms an opening 611. [00192] Figure 6F illustrates an isometric view of transistor 618. In at least one example, transistor 618 is an isometric illustration of structure 600E in Figure 6E, following process to form gate structure 620 in opening 611, in accordance with at least one example. In at least one example, a gate dielectric layer 622 is blanket deposited after a high temperature process to grow source structure 612 and drain structure 614. In at least one example, an atomic deposition process is utilized to deposit a gate dielectric layer 622 on fin (not shown), on sidewalls of spacer 610 and on dielectric 604 in opening 611. Depending on an MOS characteristic, in at least one example, a PMOS or an NMOS material is deposited on gate dielectric layer 622 to form gate electrode 624. Depending on material, and desired size of transistor gates, a range of deposition processes can be utilized. In at least one example, deposition process may include a CVD, a physical vapor deposition (PVD), or an atomic layer deposition (ALD) method. In at least one example, after deposition, a planarization process can be performed to remove excess material of gate electrode 624 and gate dielectric layer 622 from above spacer 610 and dielectric 616. [00193] Figure 7A illustrates a cross-section of structure 700A. In at least one example, structure 700A is a cross sectional illustration, through line A-A’, of transistor 618 in Figure 6F following process to deposit dielectric 702 on dielectric 616. In at least one example, dielectric 702 is blanket deposited on dielectric 616, on spacer 610 and on gate structure 620. In at least one example, dielectric 702 includes a material that is same or Docket No.: KP12P064US-PCT substantially same as material of dielectric 616. In at least one example, dielectric 702 may be deposited by a PECVD or a CVD process. The illustration depicts a portion of gate electrode 624 on fin 601. In at least one example, lines 703 denote extensions of gate electrode 624 on dielectric 604, below dashed line 705. [00194] In at least one example, drain contact 704A on drain structure 614, gate contact 704B on gate electrode 624 and source contact 704C on source structure 612 can be formed. In at least one example, a mask is formed on dielectric 702, and an opening is formed in dielectric 702 and in dielectric 616 to expose drain structure 614. In at least one example, a conductive material is deposited into opening and on uppermost surface 702A of dielectric 702. In at least one example, conductive material is removed via planarization from uppermost surface 702A to fabricate drain contact 704A. [00195] In at least one example, gate contact 704B can be formed on gate structure 620. In at least one example, gate contact 704B can be formed by etching dielectric 702 and depositing materials that are same or substantially same as materials of drain contact 704A. In at least one example, source contact 704C can be formed on source structure 612. In at least one example, source contact 704C can be formed by etching dielectric 702 and depositing materials that are same or substantially same as materials of drain contact 704A. In at least one example, transistor 618 is formed above substrate 602. In at least one example, a plurality of transistors that are identical or substantially identical to transistor 618 can be formed on a same level or plane of transistor 618 within substrate 602. [00196] Figure 7B illustrates a cross-section of structure 700B. In at least one example, structure 700A is a cross sectional illustration of structure 700A in Figure 7A following process to form conductive interconnect 708, in at least one example. In at least one example, dielectric 706 is deposited on dielectric 616 and on drain contact 704A. In at least one example, dielectric 706 includes a material that is same or substantially same as material of dielectric 706. In at least one example, dielectric 706 is deposited by a PVD, PECVD, or an ALD deposition process. In at least one example, opening is formed in dielectric 706 and one or more conductive materials are deposited into opening 707. In at least one example, conductive materials are deposited in opening 707 and on drain contact 704A. In at least one example, conductive material is planarized to form conductive interconnect 708. In at least one example, there can be more than one intervening layer between dielectric 616 and dielectric 706 and corresponding one or more conductive electrodes. [00197] Figure 8 illustrates a cross-section of structure 800. In at least one example, structure 800 is a cross sectional illustration of structure 700B in Figure 7B following Docket No.: KP12P064US-PCT process to deposit etch stop layer 118. In at least one example, etch stop layer 118 is blanket deposited on dielectric 706 and on conductive interconnect 708. In at least one example, etch stop layer 118 is deposited on dielectric 706 by a PECVD, a PVD, or a CVD process. In at least one example, etch stop layer 118 may be etched by a plasma etch process to form an opening above conductive interconnect 708 to form an electrode structure. In at least one example, an opening can be formed in portion 803 (dashed lines). In at least one example, an opening can be formed above gate structure 620. [00198] Figure 9A illustrates a cross-section of structure 900A. Structure 900A is an enhanced cross-sectional illustration of portion 803 in Figure 8 following process to etch opening 902 in etch stop layer 118, in at least one example. In at least one example, mask 903 includes a photoresist material and is formed on etch stop layer 118 by a lithographic process. In at least one example, etch stop layer 118 may be etched by a plasma etch process through an opening in mask 903. In at least one example, opening 902 has a lateral thickness WO. Lateral thickness WO may be narrower, equal to, or wider than lateral thickness WCI. In at least one example, lateral thickness WO is greater than lateral thickness WCI. In at least one example, shape of opening 902 may be circular or rectangular, and conductive interconnect 708 may be discrete islands or a line straddling a drain structure. [00199] Figure 9B illustrates a cross-section of structure 900B. Structure 900B illustrates a cross-section of structure 900A in Figure 9A, following process to deposit a liner layer 904 in opening 902, in at least one example. In at least one example, liner layer 904 includes a material of liner 202 (Figure 2A). In at least one example, liner layer 904 can be blanket deposited in opening 902 on conductive interconnect 708, on sidewall 118B, and on top surface of etch stop layer 118. In at least one example, liner layer 904 is also blanket deposited on a portion of dielectric 706, when lateral thickness WO is greater than lateral thickness WCI. In at least one example, liner layer 904 is blanket deposited to a thickness WI. [00200] Figure 9C illustrates a cross-section of structure 900C. Structure 900C illustrates a cross-section of structure 900B in Figure 9B, following process to etch liner layer 904. In at least one example, a plasma etch process is utilized to etch liner layer 904 to form liner 202. In at least one example, the plasma etch process removes liner layer 904 from above etch stop layer 118 and from uppermost surface of conductive interconnect 708 to form liner 202 adjacent to sidewall 118B. In at least one example, upper portions of liner 202 may be curved. [00201] Figure 9D illustrates a cross-section of structure 900D. Structure 900D illustrates a cross-section of structure 900C in Figure 9C, following process to deposit conductive Docket No.: KP12P064US-PCT hydrogen barrier layer 906 in opening 902 conductive fill material 908 on conductive hydrogen barrier layer 906. [00202] Collectively referring to Figures 9C and 9D, in at least one example, a conductive hydrogen barrier layer 906 is blanket deposited in opening 902 on conductive interconnect 708, on liner 202, and on uppermost surface 118A of etch stop layer 118. In at least one example, a conductive fill material 908 is blanket deposited on conductive hydrogen barrier layer 906. In at least one example, conductive hydrogen barrier layer 906 includes a material of conductive hydrogen barrier 120, and conductive fill material 908 includes a material of conductive fill 122 (Figure 1A). In at least one example, conductive hydrogen barrier layer 906 and conductive fill material 908 can be deposited by a CVD, a PVD, or an ALD process. In at least one example, conductive hydrogen barrier layer 906 and conductive fill material 908 follow a contour of liner 202. [00203] Figure 9E illustrates a cross-section of structure 900E. Structure 900E illustrates a cross-section of structure 900D in Figure 9D following process to form electrode structure 116, in at least one example. Collectively referring to Figures 9D and 9E, in at least one example, excess portions of conductive fill material 908, and conductive hydrogen barrier layer 906 deposited above etch stop layer 118 are removed by a planarization process. In at least one example, planarization process forms conductive hydrogen barrier 120 and conductive fill 122. In at least one example, planarization also confines conductive fill material 908 within conductive hydrogen barrier layer 906. In at least one example, planarization forms uppermost surface 118A and 116B that are co-planar or substantially co- planar. [00204] In at least one example, depending on the level of planarization performed, upper portions of conductive hydrogen barrier 120 and conductive fill 122 comprise a contour or shape of upper portion of liner 202. In at least one example, upper portions of conductive hydrogen barrier 120 and conductive fill 122 are curved away from a central axis of electrode structure 116. In at least one example, planarization process recesses uppermost surface116B and uppermost surface 118A to level of dashed lines 909. In at least one such example, substantially curved portions of liner 202, conductive hydrogen barrier 120 and conductive fill 122 are removed. In at least one example, surface 202A can also be made co-planar or substantially co-planar with uppermost surface 118A and uppermost surface 116B. [00205] In at least one example, electrode structure 116 can be formed without a liner. Figures 10B-10C are cross-sectional illustrations depicting a method to fabricate an Docket No.: KP12P064US-PCT electrode structure having a conductive hydrogen barrier above a fill metal, in accordance with at least one example. [00206] Figure 10A illustrates a cross-section of structure 1000A. Structure 1000A illustrates a cross-section of structure 900D in Figure 9A following process to remove mask 903 and deposit conductive fill material 1004 within opening 902, in at least one example. In at least one example, conductive fill material 1004 is blanket deposited into opening 902, on conductive interconnect 708 and on sidewalls and uppermost surface 118A. In at least one example, conductive fill material 1004 includes tantalum, titanium, ruthenium, or tungsten, and can be deposited by a PVD, a PECVD, or an ALD process. In at least one example, conductive fill material 1004 includes copper and can be deposited by an electroplating process. [00207] Figure 10B illustrates a cross-section of structure 1000B. Structure 1000B illustrates a cross-section of structure 1000A in Figure 10A following process to recess conductive fill material 1004 within a portion of opening 902, in at least one example. Referring collectively to Figures 10A and 10B, in at least one example, portions of conductive fill material 1004 deposited on uppermost surface 118A, in a prior operation, are removed by a planarization process. In at least one example, planarization process forms conductive fill 1006 within opening 902. In at least one example, surface 1006A of conductive fill 1006 is substantially planar with uppermost surface 118A. In at least one example, surface 1006A can be dished as indicated by dashed lines 1007. [00208] In at least one example, a wet chemical process is utilized to recess conductive fill 1006 below uppermost surface 118A. In at least one example, level of recess of conductive fill 1006 relative to uppermost surface 118A will depend on thickness TL and on a desired thickness of a conductive hydrogen barrier to be formed. In at least one example, conductive fill 1006 is recessed relative to uppermost surface 118A by up to half of thickness TL. In at least one example, surface 1006A may be dished after recessing as indicated by dashed lines 1007. [00209] Figure 10C illustrates a cross-section of structure 1000C. Structure 1000C illustrates a cross-section of structure 1000B in Figure 10B following process to form conductive hydrogen barrier 1008 on conductive fill 1006. In at least one example, a conductive hydrogen barrier layer is blanket deposited on conductive fill 1006 and on etch stop layer 118. In at least one example, a planarization process may be utilized to remove excess conductive hydrogen barrier material layer deposited on uppermost surface 118A. In at least one example, planarization process includes a chemical mechanical polish (CMP) Docket No.: KP12P064US-PCT process. In at least one example, CMP process forms conductive hydrogen barrier 1008. In at least one example, conductive hydrogen barrier 1008 and conductive fill 1006 are components of electrode structure 1010. [00210] Figures 11A-11B are cross-sectional illustrations depicting a method to fabricate an electrode structure having a conductive hydrogen barrier above a fill metal, in accordance with at least one example. [00211] Figure 11A illustrates a cross-section of structure 1100A. In at least one example, structure 1100A illustrates a cross-section of structure 900A in Figure 9A following process to deposit conductive hydrogen barrier layer 906 in opening 902, and conductive fill material 908 on conductive hydrogen barrier layer 906. In at least one example, materials and processes utilized to deposit hydrogen barrier layer and conductive fill material 908 have been described in association with Figure 9D. [00212] Figure 11B illustrates a cross-section of structure 1100B. Structure 1100B illustrates a cross-section of structure 1100A in Figure 11A following process to form electrode structure 116, in at least one example. Collectively referring to Figures 11A and 11B, in at least one example, excess portions of conductive fill material 908, and conductive hydrogen barrier layer 906 above etch stop layer 118 are removed by a planarization process. In at least one example, planarization process forms conductive hydrogen barrier 120 and conductive fill 122. In at least one example, planarization confines conductive fill 122 within conductive hydrogen barrier layer 906. In at least one example, planarization forms uppermost surface 118A and uppermost surface 116B that are co-planar or substantially co- planar. [00213] Figure 12A illustrates a cross-section of structure 1200A. In at least one example, structure 1200A illustrates a cross-section of structure 1100B in Figure 11A following process to form a multi-layer stack 1201 on electrode structure 116 and on etch stop layer 118. [00214] In at least one example, number of layers can depend on a type of memory device to be fabricated. In at least one example, process to form multi-layer stack 1201 includes blanket deposition of at least three material layers, to form capacitor 402 (Figure 4A). In at least one example, process to form multi-layer stack 1201 includes blanket deposition of at least four layers to form capacitor 102 (Figure 1A). In at least one example, multi-layer stack 1201 includes deposition of layers for a ferroelectric memory device. In at least one example, multi-layer stack 1201 includes deposition of layers for a paraelectric memory device. Docket No.: KP12P064US-PCT [00215] In an example, individual layers of multi-layer stack 1201 (for a ferroelectric memory device) are deposited in situ, i.e., without breaking vacuum. Multi-layer stack 1201 may be deposited by an ALD, a PECVD, a CVD, a PVD process, or a combination thereof. In examples, ALD process may be performed at a process temperature between 160 degrees Celsius and 400 degrees Celsius, PVD process may be performed at a process temperature between 23 degrees Celsius (room temperature) and 400 degrees Celsius, and CVD process may be performed at a process temperature between 160 degrees Celsius and 800 degrees Celsius. [00216] In at least one example, formation of multi-layer stack 1201 begins by blanket deposition of layer 1202 on etch stop layer 118 and on electrode structure 116. In at least one example, deposition temperatures will depend on material of dielectric layer 1204. In at least one example, dielectric layer 1204 comprises a conductive material that is designed to be laterally etched selectively to layers above, after formation of a capacitor. In at least one example, lateral etching mechanism include plasma etching, wet chemical etching, or a combination thereof. In at least one example, layer 1202 includes a material of electrode 110 (Figure 1A). In at least one example, layer 1202 includes, for example, a refractory or a nitride of a refractory metal that is useful for relative ease of patterning. In at least one example, layer 1202 has a thickness T1 that ranges between 5 nm and 30 nm. [00217] In at least one example, conductive layer 1203 is blanket deposited on layer 1202. In at least one example, conductive layer 1203 includes a conductive oxide. In at least one example, conductive layer 1203 comprises one of: La(1-x)Sr(x)FeO3, La(1-x)Sr(x)CoO3, La(1- x)Ca(x)MnO3, La(1-x)Sr(x)MnO3, Ba(1-x)Sr(x)RuO3, La(1-x)Sr(x)MnO3, wherein 0 ≤ x ≤ 1, SrRuO3, Sr2RuO4, SrMoO3, SrCoO3, SrCrO3, SrFeO3, SrVO3, CaMoO3, SrNbO3, LaNiO3, YBa2Cu3O7, Bi2Sr2CaCuO8, or CaRuO3. In at least one example, conductive layer 1203 includes Ir, Ir2Oy, Ru, RuOy, Mo, MoOy, W, or WOy, wherein ‘y’ is an integer. In at least one example, conductive layer 1203 includes hexagonal compounds including one or more of PtCoO2, PdCoO2, delafossite structured hexagonal conductive oxides including Al-doped ZnO, spinels including one or more of Fe3O4, LiV2O4 or cubic oxides including Indium tin oxide or Sn-doped In2O3. In at least one example, conductive layer 1203 includes a material that is different from material of layer 1202. [00218] In at least one example, conductive layer 1203 is deposited to thickness T2 that is suitable for minimizing electrical resistance as well as conducive to etch patterning to form memory devices. In at least one example, conductive layer 1203 has a thickness T2 that Docket No.: KP12P064US-PCT ranges between 3 nm and 30 nm. In at least one example, a thickness T2 of less than 30 nm can be useful to prevent significant tapering of sidewalls formed during patterning process. [00219] In at least one example, deposition process is continued with deposition of dielectric layer 1204 on conductive layer 1203. In at least one example, dielectric layer 1204 is blanket deposited on conductive layer 1203. In at least one example, dielectric layer 1204 has a thickness T3 between (and inclusive of) 1 nm and 30 nm. [00220] In at least one example, dielectric layer 1204 is the same or substantially the same as dielectric 106. [00221] In at least one example, process is continued with blanket deposition of conductive layer 1205 on dielectric layer 1204. In at least one example, conductive layer 1205 includes a conductive oxide. In at least one example, conductive layer 1205 comprises one of: (La,Sr)FeO3, (La,Sr)CoO3, (La,Ca)MnO3, (La,Sr)MnO3, SrRuO3, Sr2RuO4, (Ba,Sr)RuO3, SrMoO3, (La,Sr)MnO3, SrCoO3, SrCrO3, SrFeO3, SrVO3, CaMoO3, SrNbO3, LaNiO3, YBa2Cu3O7, Bi2Sr2CaCuO8, or CaRuO3. In at least one example, conductive layer 1203 includes Ir, Ir2Ox, Ru, RuOx, Mo, MoOx, W, or WOx. In at least one example, conductive layer 1205 includes a material that is same or substantially same as material of conductive layer 1203. In at least one example, when conductive layer 1203 and conductive layer 1205 include same material, multi-layer stack can be substantially symmetric in device voltage/current characteristics. In at least one example, conductive layer 1205 is deposited to thickness T4. In at least one example, it is useful for conductive layer 1205 to be sufficiently thick for example, 25 nm or more to act as a hardmask during etching and for planarization margin. In at least one example, thickness T4 can be between 3 nm and 50 nm. In at least one example, conductive layer 1205 can have a different thickness than conductive layer 1203. In at least one example, thickness T4 is substantially equal to thickness T2. [00222] In at least one example, multi-layer stack 1201 can also include one or more sacrificial layers above conductive layer 1205. Sacrificial layers above conductive layer 1205 can be useful during a patterning process or during planarization process after formation of one or more capacitors. [00223] In at least one example, mask 1207 is formed on multi-layer stack 1201. In at least one example, mask 1207 includes a photoresist or a hardmask that has been patterned by a photoresist. In at least one example, mask 1207 can include a conductive material. A conductive material such as Ta, TaN, TiN, or W can be patterned with photoresist and can offer protection against patterning multi-layer stack 1201. Docket No.: KP12P064US-PCT [00224] Figure 12B illustrates a cross-section of structure 1200B. In at least one example, structure 1200B illustrates a cross-section of structure 1200A in Figure 12A following process to pattern multi-layer stack 1201 to form one or more capacitors. In at least one example, one capacitor, such as capacitor 1208, is shown. In at least one example, a plasma etch process is utilized. In at least one example, plasma etch process may include a discharge produced by a magnetic enhanced reactive ion etching mechanism, an electron cyclotron resonance discharge, or an inductively coupled plasma discharge. [00225] Referring collectively to Figures 12A and 12B, in at least one example, plasma etch process etches conductive layer 1205 to form top electrode 108. In at least one example, dielectric layer 1204 is etched to form a patterned dielectric layer or dielectric 106, conductive layer 1203 is etched to form electrode 112, and layer 1202 is etched to form electrode 110, where electrode 112 and electrode 110 are collectively referred to as bottom electrode structure 104. [00226] In at least one example, process utilized to etch conductive layer to form electrode 112 may be substantially same as etch process utilized to form top electrode 108. In at least one example, sidewall 1208A of capacitor 1208 are substantially vertical with respect to uppermost surface 118A, as shown. In at least one example, sidewalls 102A are tapered as indicated by dashed lines 1209. In at least one example, top electrode 108 can have a curved upper surface, as indicated by dashed lines 1211. [00227] In at least one example, an over etch can be performed during plasma etch process to expose etch stop layer 118. In at least one example, plasma etch process utilized to form bottom electrode structure 104 may be selective to etch stop layer 118. In at least one such example, etch stop layer 118 may be un-etched. In at least one example, plasma etch process utilized to form bottom electrode structure 104 is not selective to etch stop layer 118. In at least one such example, portions of etch stop layer 118 may be recessed, as indicated by dashed lines 1213. [00228] In at least one example, capacitor 1208 includes features of capacitor 102 such as top electrode 108, dielectric 106, electrode 112, and electrode 110. In at least one example, a further modification of electrode 110 can render capacitor 102 illustrated in Figure 1A. In at least one example, profile of sidewall 110A can influence shape of encapsulation structure to be formed. In at least one example, the plasma etch process can be tailored to produce sidewall 110A having a substantially vertical profile. In at least one example, a substantially vertical profile can provide a surface to form a substantially contiguous encapsulation layer. Docket No.: KP12P064US-PCT [00229] Figure 12C illustrates a cross-section of structure 1200C. In at least one example, structure 1200C is a cross sectional illustration of structure 1200B in Figure 12B following process to laterally recess sidewall 110A relative to sidewall 112B. In at least one example, a wet chemical etch is utilized to laterally recess sidewall 110A relative to dashed line 1213. In at least one example, the wet chemical etch is selective to top electrode 108, dielectric 106, electrode 112, and etch stop layer 118. In at least one example, sidewall 110A is substantially vertical. In at least one example, sidewall 110A can have a granular structure that is representative of grains comprising electrode 110. In at least one example, sidewall 110A can be concaved outward as indicated by dashed line 1215. [00230] In at least one example, electrode 110 includes a material that is same or substantially same as material of the conductive hydrogen barrier 120. In at least one example, while recessing sidewall 110A to prevent conductive hydrogen barrier 120 from being etched, wet etch process utilized is timed to prevent conductive hydrogen barrier 120 from being exposed. [00231] In at least one example, where electrode 110, conductive hydrogen barrier 120, and conductive fill 122 include materials that can be selectively removed relative to one another, sidewall 116A, or uppermost surface 116B can also be exposed while laterally recessing sidewall 110A. In at least one example, bulk electrical conductivity of electrode 110 may be determined by lateral thickness WE1 and vertical thickness TE1, in addition to material of electrode 110. [00232] Figure 12D illustrates a cross-section of structure 1200D. In at least one example, structure 1200D is a cross sectional illustration of structure 1200C in Figure 12C following process to deposit encapsulation layer 1214. In at least one example, encapsulation layer 1214 is blanket deposited on capacitor 102 and on etch stop layer 118. In at least one example, process utilized to deposit encapsulation layer 1214 depends on material utilized, on the height of capacitor 102, and on the relative spacing between any two adjacent capacitors, such as capacitor 102. In exemplary examples, the deposition process utilized to deposit encapsulation layer 1214 does not include hydrogen or ammonia containing chemicals to prevent hydrogen exposure to layers within capacitor 102. In at least one example, depending on a deposition process, some materials can be deposited by both a non-hydrogen or an ammonia containing chemicals. However, each deposition process can have different deposition rates and deposition conformality. In general, a combination of ALD, PVD, and CVD processes may be utilized. Docket No.: KP12P064US-PCT [00233] Collectively referring to Figures 12C and 12D, in at least one example, profile of encapsulation layer 1214 can be influenced by vertical thickness TE1, lateral thickness WE1, and by deposited thickness TECL of encapsulation layer 1214. In at least one example, encapsulation layer 1214 is deposited to thickness TECL that is less than half a vertical thickness TE1. In at least one example, encapsulation layer 1214 is deposited on sidewall 116A, lowermost surface 112A, and on sidewall 102A. In at least one such example, cavity 1217 is formed between etch stop layer 118 and electrode 112. In at least one example, an ALD process may be utilized to obtain deposition on lowermost surface 112A and on sidewall 110A. In at least one example, encapsulation layer 1214, when deposited to a thickness of approximately 2 nm, may be sufficient to prevent hydrogen diffusion. [00234] In at least one example, cavity 1217 can be substantially eliminated when encapsulation layer 1214 is deposited to thickness TECL that is at least half a vertical thickness TE1, as indicated by dashed lines 1219. In at least one example, encapsulation layer 1214 can be deposited on etch stop layer 118 to thickness TECL that is equal to or greater than vertical thickness TE1. [00235] In an example, encapsulation layer 1214 includes an insulator material. Some examples of the insulator material include a metal and oxygen, such as, but not limited to AlxOy, HfOx, AlSiOx, ZrOx, or TiOx, where ‘x’ and ‘y’ are integers (the integers may be the same or distinct). In some examples, encapsulation layer 1214 can include a metal and nitrogen such as, but not limited to, AlN, ZrN, or HfN. In other examples, encapsulation layer 1214 can include a metal, and both Si and O, such as AlSiOx, HfSiOx, or TaSiOx where ‘is an integer. [00236] Materials such as AlxOy, HfOx, AlSiOx, ZrOx, or TiOx can be deposited without a hydrogen or an ammonia containing chemical precursor in an ALD process. In some examples, encapsulation layer 1214 can be deposited by an ALD process to a thickness in the range of 0.5 nm – 10 nm. In some examples, encapsulation layer 1214 may be deposited to a thickness of less than 5 nm. An ALD process can provide a substantially conformal thickness on sidewall 108A and on uppermost surface 108B, as shown. In at least one example, a physical vapor deposition (PVD) process may be utilized. In at least one example, a combination of ALD and PVD process may be utilized. [00237] Figure 12E illustrates a cross-section of structure 1200E. In at least one example, structure 1200E is a cross sectional illustration of structure 1200D in Figure 12D following process to form encapsulation structure 114. Docket No.: KP12P064US-PCT [00238] Collectively referring to Figures 12D and 12E, in at least one example, a plasma etch process is utilized to etch encapsulation layer 1214 from uppermost surface 118A, and from top surface of top electrode 108. In at least one example, portions of etch stop layer 118 may be etched, where etch process can recess uppermost surface 118A relative to lowermost surface of electrode 110. In at least one example, the etch process is substantially anisotropic, forming sidewall 114C that is substantially vertical. In at least one example, the etch process can be isotropic where portion 114B may be formed with tapered sidewalls, and where lateral thickness TEC of 114B decreases from electrode 112 to top electrode 108 (+z-direction). [00239] Figures 13A-13E are cross-sectional illustrations depicting a method to fabricate device structure 300A, illustrated in Figure 3A. [00240] Figure 13A illustrates a cross-section of structure 1300A. In at least one example, structure 1300A is a cross sectional illustration of structure 1200A in Figure 12A following process to etch conductive layer 1205, dielectric layer 1204, and conductive layer 1203. In at least one example, the method to etch conductive layer 1205, dielectric layer 1204, and conductive layer 1203 and form top electrode 108, dielectric 106, and electrode 112 are described above (Figure 12B). In at least one example, a plasma etch process utilized is halted after layer 1202 is exposed and structure 1302 is formed. In at least one example, the plasma etch process utilized is halted to form a spacer around top electrode 108, dielectric 106, and electrode 112. In at least one example, when dielectric 106 includes materials that are susceptible to damage from wet chemical process utilized to laterally recess electrode 110, spacer may be implemented to protect dielectric 106. In at least one example, the plasma etch process may include an over etch operation that can recess surface 1202A (away from sidewall 112B) relative to lowermost surface 112A. [00241] Figure 13B illustrates a cross-section of structure 1300B. In at least one example, structure 1300B is a cross sectional illustration of structure 1300A in Figure 13A following process to form spacer 302 on sidewall 108A, sidewall 106A, and sidewall 112B of structure 1302. [00242] In at least one example, an encapsulation layer is blanket deposited on top electrode 108, layer 1202, and sidewall 106A. In at least one example, encapsulation layer includes a material that is same or substantially same as material of spacer 302. In at least one example, after deposition, the encapsulation layer is etched by a plasma etch process to form spacer 302. In at least one example, an over etch process is utilized to clear the encapsulation layer from above surface 1202A. In at least one example, an over etch process may comprise sufficiently low energy ions that favor isotropic etch, causing erosion of spacer 302 near Docket No.: KP12P064US-PCT vicinity of top electrode 108. In at least one example, when surface 1202A is recessed below an interface between electrode 112 and layer 1202, spacer 302 may have a portion 302D that extends below lowermost surface 112A. In at least one example, portion 302D can influence a shape of encapsulation structure to be formed. [00243] Figure 13C illustrates a cross-section of structure 1300C. In at least one example, structure 1300C is a cross sectional illustration of structure 1300B in Figure 13B following process to form electrode 110. [00244] Referring collectively to Figures 13B and 13C, in at least one example, a wet chemical etch process is utilized to recess and etch layer 1202 to form electrode 110. In at least one example, forming electrode 110 completes formation of capacitor 102. In at least one such example, in addition to vertically etching layer 1202 wet chemical etch process utilized also laterally etches layer 1202 relative to sidewall 302B of spacer 302. In at least one example, sidewall 110A may be formed with a tapered profile as indicated by dashed lines 1301. A tapered profile can result when wet chemical etchants vertically and laterally etch layer 1202 to create an undercut below spacer 302. In at least one example, as the wet chemical etch progresses, chemical etchants vertically and laterally etch portions of layer 1202 at approximately equal rates forming a tapered profile. In at least one example, the profile of electrode 110 formed can also depend on grain boundaries within layer 1202. In at least one example, etching of layer 1202 can take place along grain boundaries, where the grain sizes may be irregular or regular. [00245] In at least one example, the lateral etch rate and vertical etch rate can be substantially same. In at least one such example, recess WR of sidewall 110A relative to sidewall 302B can be chosen depending on vertical thickness TE1. In at least one example, recess WR can be the same or different from vertical thickness TE1. In at least one example, recess WR is substantially the same as vertical thickness TE1 to provide space for conformal deposition of an encapsulation layer in a downstream operation. [00246] Figure 13D illustrates a cross-section of structure 1300D. In at least one example, structure 1300D is a cross sectional illustration of structure 1300C in Figure 13C following process to form an encapsulation layer 1304. In at least one example, the material and method utilized to deposit encapsulation layer 1304 can be the same as the material and methods utilized to deposit encapsulation layer 1214 (Figure 12D). [00247] In at least one example, encapsulation layer 1304 includes a same material as spacer 302. In at least one example, encapsulation layer 1304 is conformally deposited on sidewall 302B, sidewall 110A, etch stop layer 118, and on top surface of top electrode 108. In Docket No.: KP12P064US-PCT at least one example, an ALD deposition process can be utilized to conformally deposit encapsulation layer 1304. In at least one example, a conformal deposition process is useful when encapsulation layer 1304 is deposited to a thickness that is less than half of vertical thickness TE1. In at least one example, encapsulation layer 1304 is contiguous and hermetically seals capacitor 102. In at least one example, portion 1304A has one or more features of portion 304B (Figure 3A). [00248] Figure 13E illustrates a cross-section of structure 1300E. In at least one example, structure 1300E is a cross sectional illustration of structure 1300D in Figure 13D following process to form encapsulation structure 304. Referring collectively to Figures 13D and 13E, in at least one example, a plasma etch process is utilized to etch encapsulation layer 1304, selectively to etch stop layer 118 and top electrode 108 to form encapsulation structure 304. In at least one example, the plasma etch process removes portions of encapsulation layer 1304 from uppermost surface 118A and uppermost surface 108B. [00249] In at least one example, a combination of plasma etch and wet etch process may be utilized to etch layer 1202 as will be discussed below (Figures 14A-14B). [00250] Figure 14A illustrates a cross-section of structure 1400A. In at least one example, structure 1400A is a cross sectional illustration of structure 1300B in Figure 13B following process to form electrode 110. Referring collectively to Figures 13B and 14A, in at least one example, a plasma etch process is utilized to anisotropically etch layer 1202 to form electrode 110, where sidewall 110A of electrode 110 is substantially aligned with sidewall 302A. In at least one example, spacer 302 acts as a mask while etching electrode 110. In at least one example, the plasma etch process utilized is selective to material of top electrode 108. In at least one example, top electrode 108 may be capped with material that is same or substantially same as layer 1202 prior to etching and forming structure 1302 (Figure 13A). In at least one example, capping with material that is same or substantially same as layer 1202 can help to preserve top electrode 108 during etching of layer 1202. [00251] Figure 14B illustrates a cross-section of structure 1400B. In at least one example, structure 1400B is a cross sectional illustration of structure 1400A in Figure 14A following process to recess sidewall 110A under electrode 112. In at least one example, wet chemical etch laterally can recess a surface, such as sidewall 110A, in a lateral direction. In at least one example, etching electrode 110 in one direction (along x-axis) can be used to controllably recess sidewall 110A, as indicated by dashed lines 1401A and 1401B. In at least one example, resulting sidewall 110A may be influenced by grains within electrode 110. Docket No.: KP12P064US-PCT [00252] Figure 15A illustrates a cross-section of structure 1500A. In at least one example, structure 1500A is a cross sectional illustration of structure 800 in Figure 8, following process form opening 1503. Transistor 618 (Figure 8) is not illustrated for clarity. In at least one example, sacrificial layer 1502 is blanket deposited on etch stop layer 118. In at least one example, sacrificial layer 1502 comprises an insulator that includes a material which can be selectively removed relative to etch stop layer 118 and one or more layers in multi-layer stack to be deposited above. In at least one example, sacrificial layer 1502 is blanket deposited on etch stop layer 118 by a PVD, CVD, PECVD, or an ALD process. In at least one example, sacrificial layer 1502 is deposited to a thickness between 2 nm and 30 nm. In at least one example, thickness of sacrificial layer 1502 may be determined by process utilized to form an electrode structure in a downstream operation. [00253] In at least one example, mask 1505 is formed on sacrificial layer 1502. In at least one example, mask 1505 includes a photoresist material and is formed on sacrificial layer 1502 by a lithographic process. In at least one example, sacrificial layer 1502 and etch stop layer 118 may be etched by a plasma etch process through an opening in mask 1505 to form opening 1503. In at least one example, opening 1503 exposes conductive interconnect 708. [00254] Figure 15B illustrates a cross-section of structure 1500B. In at least one example, structure 1500B is a cross sectional illustration of structure 1500A in Figure 15A following process to form electrode structure 116. In at least one example, method to form electrode structure 116 is similar to method described above (Figures 11B and 11B). [00255] Figure 15C illustrates a cross-section of structure 1500C. In at least one example, structure 1500C is a cross sectional illustration of structure 1500B in Figure 15B following process to deposit multi-layer stack 1506 to form capacitor 402 (Figure 4A). Conductive interconnect 708 is not illustrated for clarity. In at least one example, conductive layer 1203 is blanket deposited on electrode structure 116 and on sacrificial layer 1502, dielectric layer 1204 is blanket deposited on conductive layer 1203 and conductive layer 1205 is blanket deposited on dielectric layer 1204. In at least one example, materials and methods utilized to deposit conductive layer 1203, dielectric layer 1204, and conductive layer 1205 are described in Figure 12A. In at least one example, mask 1507 is formed on conductive layer 1205 to pattern multi-layer stack 1506. [00256] Figure 15D illustrates a cross-section of structure 1500D. In at least one example, structure 1500D is a cross sectional illustration of structure 1500C in Figure 15C following process to etch conductive layer 1205, dielectric layer 1204, and conductive layer 1203 to form capacitor 402. In at least one example, a plasma etch process is utilized to etch Docket No.: KP12P064US-PCT conductive layer 1205, dielectric layer 1204, and conductive layer 1203 (Figure 15C). In at least one example, the plasma etch process is selective to sacrificial layer 1502, with little to no erosion of sacrificial layer 1502. For example, uppermost surface 1502A is not etched. [00257] In at least one example, lateral thickness WC of capacitor 402 is greater than lateral thickness WES. In at least one example, sacrificial layer 1502 can be etched after forming capacitor 402, as indicated by dashed lines 1509. In at least one example, an anisotropic etch process is utilized to etch sacrificial layer 1502 to facilitate further removal of sacrificial layer 1502 at a downstream operation. In at least one such example, a portion of sacrificial layer 1502 remains under electrode 112 after etching sacrificial layer 1502. [00258] Figure 15E illustrates a cross-section of structure 1500E. In at least one example, structure 1500E is a cross sectional illustration of structure 1500D in Figure 15D following process to remove sacrificial layer 1502. In at least one example, portion of sacrificial layer 1502 remaining under electrode 112 is removed by a wet chemical etch, where the wet chemical etch may be selective to top electrode 108, dielectric 106, electrode 112, conductive hydrogen barrier 120, and etch stop layer 118. In at least one example, complete removal of sacrificial layer 1502 forms cavity 1511 between electrode 112, etch stop layer 118, and conductive hydrogen barrier 120. In at least one example, lateral thickness of cavity 1511 depends on size of lateral thickness WC relative to lateral thickness WES, where WC is greater than WES. [00259] Figure 15F illustrates a cross-section of structure 1500F. In at least one example, structure 1500F is a cross sectional illustration of structure 1500E in Figure 15E following process to deposit an encapsulation layer 1510 on capacitor 402, on sidewall 116A, on uppermost surface 118A, and adjacent to sidewall 116A. Referring collectively to Figures 15F and 12D, in at least one example, encapsulation layer 1510 includes a material that is same or substantially same as material of encapsulation layer 1214. In at least one example, method to deposit encapsulation layer 1510 has been described above. In at least one example, encapsulation layer 1510 can be deposited to a thickness that does not produce a cavity under electrode 112. In at least one example, encapsulation layer 1510 can be deposited to a thickness that can produce a cavity, for example, cavity 1217. In at least one example, encapsulation layer 1510 can be etched and removed from above top electrode 108 and from above etch stop layer 118, such as is shown in cross-sectional illustration of structure 1500G in Figure 15G. In at least one example, over etching can reduce lateral thickness TECM of portion 404A and lateral thickness TEC of portion 404B. Docket No.: KP12P064US-PCT [00260] Referring again to Figure 15D, in at least one example, an additional spacer can be formed on sidewall 402A prior to removing sacrificial layer 1502. In at least one example, an additional spacer on sidewall 402A can provide protection to dielectric 106 during removal of sacrificial layer 1502. In at least one example, wet chemical etchants utilized to remove sacrificial layer 1502 can damage some material choices of dielectric 106. [00261] Figure 16A illustrates a cross-section of structure 1600A. In at least one example, structure 1600A is a cross sectional illustration of structure 1500D in Figure 15D following process to form encapsulation layer 1602. In at least one example, encapsulation layer 1602 includes a material that is same or substantially same as material of spacer 302 (Figure 13B). In at least one example, material of encapsulation layer 1602 is chosen to provide hermetic seal to dielectric 106 and be chemically resilient while etching sacrificial layer 1502. In at least one example, encapsulation layer 1602 is blanket deposited on top electrode 108, on sidewall 402A, and on uppermost surface 1502A by an ALD, a PVD process, or a combination thereof. In at least one example, encapsulation layer 1602 comprises a thickness of at least 2 nm to be continuous. [00262] Figure 16B illustrates a cross-section of structure 1600B. In at least one example, structure 1600B is a cross sectional illustration of structure 1600A in Figure 16A following process to form spacer 1604. In at least one example, encapsulation layer 1602 (Figure 16A) is etched by a plasma etch process to form spacer 1604. In at least one example, sidewall 1604A of spacer 1604 is substantially vertical. In at least one example, an over etch process is utilized to remove encapsulation layer 1602 and expose sacrificial layer 1502. In at least one example, sidewall 1604A is tapered, as illustrated. [00263] Figure 16C illustrates a cross-section of structure 1600C. In at least one example, structure 1600C is a cross sectional illustration of structure 1600B in Figure 16B following process to etch and remove sacrificial layer 1502. Referring collectively to Figures 16B and 16C, in at least one example, a combination of plasma etch and a wet etch process is utilized to remove sacrificial layer 1502. In at least one example, a wet chemical etch process may be utilized to remove all of sacrificial layer 1502, where the wet chemical process is selective to etch stop layer 118, spacer 1604 and conductive hydrogen barrier 120. In at least one example, the process of removing sacrificial layer 1502 forms cavity between electrode 112, spacer 1604, conductive hydrogen barrier 120, and etch stop layer 118 adjacent to conductive hydrogen barrier 120. In at least one example, size of cavity 1605 depends on thickness of sacrificial layer 1502 removed and on lateral distance (along X-direction) between sidewall 116A and sidewall 1604A. Docket No.: KP12P064US-PCT [00264] Figure 16D illustrates a cross-section of structure 1600D. In at least one example, structure 1600D is a cross sectional illustration of structure 1600C in Figure 16C following process to deposit encapsulation layer 1608. Referring collectively to Figures 16C and 16D, in at least one example, encapsulation layer 1608 is blanket deposited on sidewall 1604A, on top electrode 108, on uppermost surface 118A. In at least one example, encapsulation layer 1608 provides a seal at interface 1609 between spacer 1604 and capacitor 402. In at least one example, when encapsulation layer 1608 is deposited to a thickness that is at least half TES, cavity 1605 is filled. [00265] Figure 16E illustrates a cross-section of structure 1600E. In at least one example, structure 1600E is a cross sectional illustration of structure 1600D in Figure 16D following process to etch encapsulation layer 1608 to form structure 1610. In at least one example, encapsulation layer 1608 (Figure 16D) is removed by a plasma etch process selectively to etch stop layer 118, and top electrode 108. In at least one example, the plasma etch process can expose and remove upper portions of spacer 1604, when encapsulation layer 1608 and structure 1610 include a same or substantially same material. In at least one example, plasma etch process forms portion 1610A adjacent to sidewall 116A, under lowermost surface 1604B of spacer 1604, and lowermost surface 112A. In at least one example, thickness of structure 1610 is such that portion 1610A fills cavity 1605 (Figure 16C). [00266] Figure 17A illustrates a cross-section of structure 1700A. In at least one example, structure 1700A is a cross sectional illustration of structure 1200E in Figure 12E following process to deposit dielectric 1702. In at least one example, dielectric 1702 is blanket deposited on etch stop layer 118 on encapsulation structure 114. In at least one example, when uppermost surface 108B is exposed, dielectric 1702 is also deposited on uppermost surface 108B. In at least one example, to provide a barrier against hydrogen diffusion directly into sidewalls of capacitor 102, dielectric 1702 can include a material that is amorphous, having a high film density (a film density above 90% of theoretical material density or film density), and is electrically insulating. [00267] In an example, a planarization process is performed to remove excess dielectric 1702. In at least one example, planarization process includes a chemical mechanical planarization process (CMP). In at least one example, CMP process removes dielectric 1702 and upper portions of encapsulation structure 114. In at least one example, CMP process removes an upper portion of top electrode 108. In at least one example, the CMP process forms planar uppermost surfaces 114E, 1702A, and 108B that are co-planar or substantially co-planar. In at least one example, where encapsulation structure 114 also includes portion Docket No.: KP12P064US-PCT 114F (denoted by dashed lines) above top electrode 108, the planarization process may be utilized to stop on portion 114F or planarize and remove portion 114F. In at least one such example, encapsulation structure 404 also includes portion 114G on etch stop layer 118. [00268] Figure 17B illustrates a cross-section of structure 1700B. In at least one example, structure 1700B is a cross sectional illustration of structure 1700A in Figure 17A following process to deposit insulator layer 1704 and form via electrode 1706 on a portion of top electrode 108. In at least one example, insulator layer 1704 includes a material that is same or substantially same as etch stop layer 118. In at least one example, insulator layer 1704 includes a material that is same or substantially same as dielectric 1702, where dielectric 1702 includes a material that is amorphous, having a high film density (a film density above 90% of theoretical material density or film density). In at least one such example, insulator layer 1704 includes a material that is different from encapsulation structure 114. In at least one example, an opening is formed in insulator layer 1704 above capacitor 102, where the opening exposes a portion of top electrode 108. In at least one example, a conductive hydrogen barrier layer is blanket deposited in the opening, on sidewalls of insulator layer 1704 and on a portion of top electrode 108. In at least one example, a conductive fill material is blanket deposited on the conductive hydrogen barrier layer. In at least one example, conductive fill material includes copper and may be deposited by an electroplating process. [00269] In an example, a CMP process removes the conductive fill material and conductive hydrogen barrier material layer from above uppermost surface 1704A. In at least one example, planarization process forms conductive hydrogen barrier 1708 and conductive fill 1710. In at least one example, conductive hydrogen barrier 1708 and the conductive fill 1710 include a material that is same or substantially same as material of conductive hydrogen barrier 120 and conductive fill 122, respectively (Figure 1A). In at least one example, insulator layer 1704, conductive hydrogen barrier 1708, encapsulation structure 114, etch stop layer 118 and conductive hydrogen barrier 120 combine to provide a hermetic seal to capacitor 102. [00270] Figure 18 illustrates a cross-section of structure 1800. In at least one example, structure 1800 is a cross sectional illustration of structure 1500G in Figure 15G following process to deposit dielectric 1702. In at least one example, dielectric 1702 is blanket deposited on etch stop layer 118, on encapsulation structure 404. In at least one example, when uppermost surface 108B is exposed, dielectric 1702 is also deposited on sidewall 108A. In at least one example, when uppermost surface 108B is exposed, dielectric 1702 is also deposited on uppermost surface 108B. In at least one example, to provide a barrier against Docket No.: KP12P064US-PCT hydrogen diffusion directly into sidewalls of capacitor 102, dielectric 1702 can include a material that is amorphous, having a high film density (a film density above 90% of theoretical material density or film density) and is electrically insulating. [00271] In an example, a planarization process is performed to remove excess dielectric 1702. In at least one example, planarization process includes a chemical mechanical planarization process (CMP). In at least one example, CMP process removes dielectric 1702 and upper portions of encapsulation structure 404. In at least one example, CMP process removes an upper portion of top electrode 108. In at least one example, the CMP process forms planar uppermost surfaces 1702A, 108B, and top surface 404E that are co-planar or substantially co-planar. In at least one example, where encapsulation structure 404 also includes portion 404F above top electrode 108, the planarization process may be utilized to stop on portion 404F or planarize and remove portion 404F. In at least one such example, encapsulation structure 404 also includes portion 404G on etch stop layer 118. [00272] Figure 19 illustrates a cross-section of structure 1900. In at least one example, structure 1900 is a cross sectional illustration of structure 1800 in Figure 18 following process to deposit insulator layer 1704 and form via electrode 1706 on a portion of top electrode 108. In at least one example, insulator layer 1704 includes a material that is same or substantially same as etch stop layer 118. In at least one example, insulator layer 1704 includes a material that is same or substantially same as dielectric 1702, where dielectric 1702 includes a material that is amorphous, having a high film density (a film density above 90% of theoretical material density or film density). In at least one such example, insulator layer 1704 includes a material that is different from encapsulation structure 114. In at least one example, an opening is formed in insulator layer 1704 above capacitor 402, where the opening exposes a portion of top electrode 108. In at least one example, a conductive hydrogen barrier layer is blanket deposited in the opening, on sidewalls of insulator layer 1704 and on a portion of top electrode 108. In at least one example, a conductive fill material is blanket deposited on the conductive hydrogen barrier layer. In at least one example, conductive fill material includes copper and may be deposited by an electroplating process. [00273] In an example, a CMP process removes the conductive fill material and conductive hydrogen barrier material layer from above uppermost surface 1704A. The planarization process forms conductive hydrogen barrier 1708 and conductive fill 1710. In at least one example, conductive hydrogen barrier 1708 and the conductive fill 1710 include a material that is same or substantially same as material of conductive hydrogen barrier 120 and conductive fill 122, respectively (Figure 1A). In at least one example, insulator layer Docket No.: KP12P064US-PCT 1704, conductive hydrogen barrier 1708, encapsulation structure 114, etch stop layer 118, and conductive hydrogen barrier 120 combine to provide a hermetic seal to capacitor 402. [00274] In at least one example, structure 1700B (Figure 17B) and device structure (Figure 4A) can be elements of a memory region. In at least one example, the memory region can be integrated a logic region adjacent to the memory region. In at least one example, the logic region can include transistors that are same or different from transistors in the memory region. In at least one example, the transistors in the memory and logic regions can be on a same level. [00275] In at least one example, etch stop layer 118 may be replaced by a dual layer barrier. A dual layer barrier may be implemented for a variety of reasons such as to improve yield, provide a barrier against hydrogen, prevent film delamination due to increased thickness in a single film. In at least one example, a dual layer barrier may comprise a lower insulator layer and an upper insulator having a different material from the upper insulator layer. In at least one example, etch stop layer 118 may include silicon, nitrogen and carbon and have a thickness that is sufficient to act as an etch stop layer and advantageously provide high yield in a logic region. In at least one example, etch stop layer 118 comprising silicon, nitrogen and carbon may be deposited to a thickness that relieves tensile stress. Excessive tensile stress can cause film delamination and present yield problems during fabrication. In at least one such example, etch stop layer 118 including silicon, nitrogen and carbon may not be adequate to act as a hydrogen diffusion barrier in an adjacent memory region. In at least one example, hydrogen can diffuse into In at least one example, the upper insulator layer comprises a material that can provide a barrier against hydrogen diffusion. [00276] In at least one such example, hydrogen can diffuse from below electrode structure 116 towards capacitor 102. In at least one example, the upper insulator layer can be removed selectively from the logic region, before or after forming the capacitor devices. In at least one example, the lower insulator layer may advantageously preserve yield in the logic region. [00277] Figure 20A illustrates a cross-section of system 2000A. In at least one example, system 2000A includes device structure 2002 in memory region 2001A, and device structure 2004 in logic region 2001B. In at least one example, device structure 2002 includes one or more elements of structure 1700B illustrated in Figure 17B, such as capacitor 102, encapsulation structure 114, electrode structure 116, conductive interconnect 708, dielectric 1702, and transistor 618. In at least one example, two device structures, such as structure 1700B are shown. In at least one example, device structure 2002 can include more than 64 device structures, such as structure 1700B in an array. Docket No.: KP12P064US-PCT [00278] Device structure 2002 further includes a barrier structure 2006 between conductive interconnect 708 and capacitor 102, where barrier structure 2006 includes a step height. In at least one example, the step height is at an interface between memory region 2001A and logic region 2001B. In at least one example, the step height can be between 3 nm and 50 nm. In at least one example, barrier structure 2006 can include a plurality of insulator layers. In at least one example, barrier structure 2006 includes two insulator layers, such as insulator layer 2008 and insulator layer 2010. In at least one example, insulator layer 2008 includes a material that is different from material of insulator layer 2010. In at least one example, insulator layer 2008 includes one of: SiN (low H content), AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx, TaSiOx, SiOx, SiN, SiON, AlzOy, AlN, ZrN, HfN, GaOx, where ‘x’, ‘y’ and ‘z’ are integers (where the integers can be same or distinct). In at least one example, insulator layer 2010 includes one of: SiCN, SiON, SiC, SiN (high hydrogen content). In at least one example, insulator layer 2008 includes a material that is different from material of encapsulation structure 114. [00279] In at least one example, electrode structure 116 is embedded within insulator layer 2008 and insulator layer 2010. In at least one example, encapsulation structure 114 is in contact with insulator layer 2008. In at least one example, encapsulation structure 114 has one or more features described above in Figures 1B-1F. In at least one example, electrode structure 116 spans a combined vertical thickness of insulator layer 2008 and insulator layer 2010. [00280] In at least one example, logic region 2001B further includes conductive interconnect 2012 in level 2013 and transistor 2014 coupled below insulator layer 2010. In at least one example, logic region 2001B includes via electrode 2016. In at least one example, via electrode 2016 is laterally surrounded by insulator layer 2010 but not insulator layer 2008. In at least one example, via electrode 2016 extends beyond a level of uppermost surface 116B of electrode structure 116. [00281] In at least one example, electrode 2016 is further coupled with a metal line 2018, where metal line 2018 is within level 2019, but above electrode 2016. In at least one example, metal line 2018 can extend along the y-direction in the Figure. In at least one example, system 2000A includes a metal line 2020 adjacent to metal line 2018. In at least one example, metal line 2020 may be coupled to a functional device on a plane in front/or behind plane of a plane of Figure 20A. In at least one example, metal line 2020 may be a dummy metal line implemented for patterning fidelity. Docket No.: KP12P064US-PCT [00282] In at least one example, transistor 2014 is identical to transistor 618. In other examples, transistor 2014 may include features such as multiple fins to increase drive current in logic transistors. In at least one example, conductive interconnect 2012 can be the same size as conductive interconnect 708. In at least one example, conductive interconnect 2012 can be wider than conductive interconnect 708. In at least one example, electrode 2016 includes Cu, Cu/Al/Si compounds, Cu doped with Mn, W, Al, Ta(N), Ti(N), Mo, or Ru. In at least one example, metal line 2018 and metal line 2020 include Cu, Cu/Al/Si compounds, Cu doped with Mn, W, Al, Ta(N), Ti(N), Mo, or Ru. [00283] In at least one example, via electrode 2016 is also laterally surrounded by dielectric 2022 above insulator layer 2010. In at least one example, dielectric 2022 can include a same material as dielectric 1702. In at least one example, dielectric 2022 can include a material that has a lower dielectric constant than dielectric 1702. [00284] In at least one example, electrode 1706, metal line 2018 and metal line 2020 have a same or substantially same height TM. In at least one example, electrode 1706, metal line 2018, and metal line 2020 are laterally surrounded by dielectric 2024. In at least one example, dielectric 2024 can include a bilayer stack, where a lower layer includes a material of insulator layer 2008, and an upper layer that includes a low K dielectric such as dielectric 2022. [00285] Figure 20B illustrates a cross-section of system 2000B. In at least one example, system 2000B includes device structure 2030 in memory region 2001A, and device structure 2004 in logic region 2001B. In at least one example, device structure 2030 includes one or more elements of structure 1700B illustrated in Figure 17B, such as electrode 112, conductive interconnect 708, electrode structure 116, dielectric 1702, and transistor 618. In at least one example, device structure 2030 includes capacitor 2032 and encapsulation layer 2034 adjacent to sidewall 2032A of capacitor 2032. In at least one example, capacitor 2032 includes many features of capacitor 102, such as top electrode 108, dielectric 106, electrode 112, and electrode 110. In at least one example, electrode 110 does not have recessed sidewalls as in capacitor 102. In at least one example, encapsulation layer 2034 includes a same material as encapsulation structure 114. In at least one example, encapsulation layer 2034 is conformal to sidewall 2032A. In at least one example, when capacitor 2032 has a substantially vertical profile, encapsulation layer 2034 has a substantially uniform thickness on sidewall 2032A. In at least one example, when sidewall 2032A is tapered then encapsulation layer 2034 can have a variation in thickness along sidewall 2032A. In at least one such example, encapsulation layer 2034 may decrease in lateral thickness from top Docket No.: KP12P064US-PCT electrode 108 to electrode 110. In at least one example, encapsulation layer 2034 is in contact with insulator layer 2008 but not insulator layer 2010. In at least one example, encapsulation layer 2034 extends on insulator layer 2008 to an edge of insulator layer 2008 at interface between memory region 2001A and logic region 2001B. [00286] In at least one example, electrode structure 116 comprises lateral thickness TES, where TES can be greater than or less than lateral thickness WMD of capacitor 2032. [00287] In at least one example, system 2000B includes logic region 2001B that includes features of logic region 2001B such as device structure 2004 described in association with Figure 20A. [00288] Figure 21 illustrates a cross-section of system 2100. In at least one example, system 2100 includes device structure 2101 in memory region 2001A, and device structure 2101 in logic region 2001B. In at least one example, device structure 2101 includes one or more elements of structure 1900 illustrated in Figure 19, such as capacitor 402, encapsulation structure 404, electrode structure 116, conductive interconnect 708, dielectric 1702, and transistor 618. In at least one example, two device structures such as structure 1900 are shown. In at least one example, system 2100 can include an array with more than 64 device structures such as structure 1900. [00289] In at least one example, electrode structure 116 is embedded within insulator layer 2008 and insulator layer 2010. In at least one example, electrode structure 116 extends above surface 2008A of insulator layer 2008. In at least one example, encapsulation structure 114 is in contact with insulator layer 2008. In at least one example, encapsulation structure 114 has one or more features described above in Figures 4A, 4B and 4D. In at least one example, encapsulation structure 404 fills a space between surface 2008A and lowermost surface 112A. [00290] In at least one example, system 2000B includes logic region 2001B that includes features of logic region 2001B such as device structure 2004 described in association with Figure 20A. [00291] Figures 22A-22J illustrate process operations to fabricate system 2000A illustrated in Figure 20A, in at least one example. [00292] Figure 22A illustrates a cross section of structure 2200A. In at least one example, process to form 2200A comprises depositing a pair of insulator layers such as insulator layer 2202 and insulator layer 2204. In at least one example, insulator layer 2202 is blanket deposited on dielectric 706, conductive interconnect 708, and conductive interconnect 2012. In at least one example, electrode structure 116 is formed above individual conductive Docket No.: KP12P064US-PCT interconnect 708 in memory region 2201A. In at least one example, an electrode structure is not formed on conductive interconnect 2012 in logic region 2201B. In at least one example, method to form electrode structure 116 is substantially similar to methods described above. In at least one example, openings are formed by etching insulator layer 2202 and insulator layer 2204 through a mask. In at least one example, materials such as those described above (Figures 10A-11B) are deposited into the openings and planarized. [00293] In at least one example, 2204 may be deposited to a greater thickness than a desired final thickness to anticipate losses during the planarization process. In at least one example, insulator layer 2202 and insulator layer 2204 include a same material as insulator layer 2010 and insulator layer 2008, respectively. [00294] Figure 22B illustrates a cross-section of structure 2200B. In at least one example, structure 2200B is a cross sectional illustration of structure 2200A in Figure 22A, following process to form capacitors 2205. In at least one example, capacitors 2205 include features of capacitor 102, such as top electrode 108, dielectric 106, electrode 112, and electrode 110. In at least one example, method to form capacitors 2205 is similar to methods described above in Figures 12A-12C. [00295] Referring again to Figure 22B, in at least one example, a multi-layer stack is deposited on insulator layer 2204 and on electrode structure 116. In at least one example, the multi-layer stack is patterned as described above. In at least one example, a further modification of electrode 110 can render capacitor 102 (Figure 1A). In at least one example, profile of sidewall 110A can dictate shape of encapsulation structure to be formed. In at least one example, the plasma etch process can be tailored to produce sidewall 110A having a substantially vertical profile. In at least one example, when sidewall 110A has a substantially vertical profile, a wet etch process can controllably recede sidewall 110A relative to sidewall 112B in a downstream operation. [00296] Figure 22C illustrates a cross-section of structure 2200C. In at least one example, structure 2200C is a cross sectional illustration of structure 2200B in Figure 22B, following process to form capacitor 102 above an individual electrode structure 116. In at least one example, method to recede sidewall 110A is described above in Figure 12C. In at least one example, wet chemical etchant utilized to recede sidewall 110A is selective to insulator layer 2204, top electrode 108, dielectric 106 electrode 112, and electrode 110. In at least one example, electrode structure 116 has a lateral thickness that is less than a lateral thickness of electrode 110 after recessing process. In at least one example, electrode structure 116 may be laterally surrounded by a liner layer as discussed above (Figure 2A). Docket No.: KP12P064US-PCT [00297] In at least one example, encapsulation structure 114 is formed on capacitor 102. In at least one example, encapsulation structure 114 is formed around individual capacitors 102 and does not continuously extend from one capacitor 102 to another capacitor 102. [00298] Figure 22D illustrates a cross-section of structure 2200D. In at least one example, structure 2200D is a cross sectional illustration of structure 2200C in Figure 22C, following process to form dielectric in memory region 2201A. In at least one example, dielectric 2206 is blanket deposited on structure 2200C (Figure 22C) by a PVD, CVD, PECVD, or an ALD process. In at least one example, dielectric 2206 comprises silicon and one or more of carbon or oxygen. In at least one example, dielectric 2206 is planarized. In at least one example, the planarization process removes a portion of top electrode 108 and upper portions of encapsulation structure 114 adjacent to top electrode 108, rendering uppermost surface 114E that is co-planar or substantially co-planar with uppermost surface 108B. [00299] In at least one example, mask 2207 is formed on dielectric 2206, and on top electrode 108. In at least one example, a plasma etch process is utilized to etch dielectric 2206 and insulator layer 2204 from logic region 2201B. In at least one example, because of differences in etch rate between insulator layer 2204 and insulator layer 2202, insulator layer 2204 can be removed selectively with little to no removal of insulator layer 2202. In at least one example, sidewall 2206A of dielectric 2206 and insulator layer insulator layer 2204 are aligned after the etch process. In at least one example, uppermost surface 2202A of insulator layer 2202 may be recessed in logic region 2201B by up to 2nm. In at least one example, mask 2207 may be removed after the etch process. [00300] In at least one example, dielectric 2206 is not planarized to expose top electrode 108. In at least one such example, a portion of dielectric 2206 remains above top electrode 108, and upper portions of encapsulation structure 114 remain, as illustrated in structure 2200C (Figure 22C). In at least one example, leaving portions of dielectric 2206 above top electrode 108 can be advantageous because it can be used for protecting top electrode 108 during a second planarization process utilized in a downstream operation. The second planarization process may be implemented after depositing a dielectric in logic region 2201B and in memory region 2201A. [00301] Figure 22E illustrates a cross-section of structure 2200E. In at least one example, structure 2200E is a cross sectional illustration of structure 2200D in Figure 22D, following process to deposit dielectric 2208 on insulator layer 2202 in logic region 2201B and in memory region 2201A. In at least one example, dielectric 2208 comprises a same material as dielectric 2206. In an example, dielectric 2208 is blanket deposited on dielectric 2206, top Docket No.: KP12P064US-PCT electrode 108, encapsulation structure 114, and on sidewall of insulator layer 2204 in memory region 2201A. In at least one example, dielectric 2208 includes a material that has a lower dielectric constant than dielectric 2206. [00302] Figure 22F illustrates a cross-section of structure 2200F. In at least one example, structure 2200F is a cross sectional illustration of structure 2200E in Figure 22E, following process to form etch stop layer 2210 on dielectric 2206, top electrode 108, encapsulation structure 114, and dielectric 2208. Referring collectively to Figures 22E and 22F, in at least one example, a planarization process is performed to remove excess dielectric 2208 from above dielectric 2206. In at least one example, where no excess dielectric 2206 remains above top electrode 108, planarization process can stop on top electrode 108 after removing excess dielectric 2208 in memory region 2201A. In at least one example, planarization process forms uppermost surface 2206B and uppermost surface 2208A that are co-planar or substantially co-planar. In at least one example, portions of uppermost surface 2206B may be recessed relative to uppermost surfaces 114E or uppermost surface 108B. [00303] In at least one example, when there are portions of dielectric 2206 remaining above top electrode 108, planarization process utilized to remove excess dielectric 2208 deposited above dielectric 2206 can be continued. In at least one example, continuing planarization process can also remove excess dielectric 2206. In at least one example, continuing planarization process can also remove portions of top electrode 108 and upper portions of encapsulation structure 114 to render structure illustrated in Figure 22F. In at least one example, when dielectric 2208 and dielectric 2206 include a same or substantially same material, uppermost surface 2206B and uppermost surface 2208A can be coplanar or substantially coplanar. [00304] In an example, etch stop layer 2210 is blanket deposited in memory region 2201A and logic region 2201B by a PVD, CVD, PECVD, or an ALD process. In at least one example, etch stop layer 2210 is deposited to a thickness of at least 5nm. In at least one example, etch stop layer 2210 includes a hydrogen barrier material. In at least one example, etch stop layer 2210 includes a same material as insulator layer 2204. In at least one example, dielectric 2212 is blanket deposited on etch stop layer 2210 by a PVD, CVD, PECVD, or an ALD process. In at least one example, etch stop layer 2210 includes a same material as dielectric 2208. [00305] Figure 22G illustrates a cross-section of structure 2200G. In at least one example, structure 2200G is a cross sectional illustration of structure 2200F in Figure 22F, following process to form opening 2213 above top electrode 108. In at least one example, mask 2215 is Docket No.: KP12P064US-PCT formed on dielectric 2212 by a lithographic process. In at least one example, a plasma etch process is utilized to form opening 2213 in dielectric 2212 and in etch stop layer 2210. In at least one example, the plasma etch process exposes uppermost surface 108B. In at least one example, opening 2213 has a lateral thickness that does not expose encapsulation structure 114 to prevent erosion of encapsulation structure 114 along sidewall 108A. [00306] Figure 22H illustrates a cross-section of structure 2200H. In at least one example, structure 2200H is a cross sectional illustration of structure 2200G in Figure 22G, following process to form via electrode 2214 in contact with top electrode 108. In at least one example, one or more conductive materials are deposited into opening 2213 and on dielectric 2212. In at least one example, a planarization process is utilized to remove excess one or more conductive materials from above 2212 to isolate the one or more conductive materials to form via electrode 2214. [00307] In at least one example, after formation of electrode 2214, opening 2217 and opening 2219 are formed in dielectric 2212, and etch stop layer 2210 is formed in logic region 2201B. In an example, methods to form mask 2215 and opening 2217 are substantially the same as methods utilized to form mask 2215 and form opening 2213 (Figure 22G). [00308] Figure 22I illustrates a cross-section of structure 2200I. In at least one example, structure 2200I is a cross sectional illustration of structure 2200H in Figure 22H, following process to etch dielectric 2208 to form via opening 2221 within opening 2219 in logic region 2201B. In at least one example, mask 2223 is formed, on dielectric 2212, on electrode 2214, in opening 2217 and in opening 2219, by a lithographic process and includes a photoresist material. In at least one example, mask 2223 has an opening within opening 2219 that is designed to facilitate etching dielectric 2208 to form via opening 2221, as shown. In at least one example, mask 2223 may not include an opening within opening 2217 in the plane of the Figure but may include an opening in a plane that is behind or in front. In an example, a plasma etch process is utilized to form via opening 2221 by etching the dielectric 2208 and insulator layer 2202. In at least one example, insulator layer 2202 is utilized as an etch stop. In at least one example, a known thickness of insulator layer 2204 can be advantageous for targeting etch process implemented while exposing conductive interconnect 2012. In at least one example, a known thickness of insulator layer 2204 can enable minimal over etch of insulator layer 2202 across a substrate and can advantageously preserve die yield over an entire substrate. Docket No.: KP12P064US-PCT [00309] Figure 22J illustrates a cross-section of structure 2200J. In at least one example, structure 2200J is a cross sectional illustration of structure 2200I in Figure 22I, following process to form via electrode 2224, metal line 2226, and metal line 2228. [00310] Referring collectively to Figures 22I and 22J, in at least one example, mask 2223 utilized to form via opening 2221 is removed and a conductive material is deposited into opening 2219, opening 2221, and opening 2217. In an example, the conductive material includes a material that is the same or substantially the same as the material of the via electrode 2214, including examples with or without one or more liner layers and fill metal. In some examples, a fill metal includes copper, tungsten, nickel, or cobalt, and a liner layer includes ruthenium or tantalum. In some such examples, the liner layer is deposited on uppermost surface 2012A of the conductive interconnect 2012, on sidewall of insulator layer 2202, on sidewall of dielectric 2208, on sidewall of insulator layer 2010, sidewall of dielectric 2212, on uppermost dielectric surface 2212A, and on surfaces of via electrodes 2214. In other examples where no liner is implemented, a fill metal or a conductive material is directly deposited on uppermost surface 2012A of the conductive interconnect 2012, on sidewall of insulator layer 2202, on sidewall of dielectric 2208, on sidewall of insulator layer 2010, on sidewall of dielectric 2212, on uppermost dielectric surface 2212A, and on surfaces of via electrodes 2214. [00311] A planarization process may be utilized to remove an excess conductive material deposited on dielectric 2212 and on via electrodes 2214. In an example, the planarization process includes a chemical mechanical polish (CMP) process. The CMP process isolates metal line 2228 from metal line 2226. In at least one example, via electrode 2224 can be formed at the same time as metal line 2226. In at least one example, uppermost surfaces 2214A of via electrode 2214, uppermost surface 2228A, and uppermost surface 2226A are co-planar or substantially co-planar after the CMP process. [00312] In general, via electrode 2214 may be fabricated before or after fabrication of via electrode 2224, metal line 2226, and metal line 2228. The method described in association with Figures 22A-22J can be performed so as to fabricate via electrode 2224, metal line 2226, and metal line 2228 prior to fabrication of via electrode 2214. [00313] Figure 23A illustrates a cross-section of structure 2300A. In at least one example, structure 2300A is a cross sectional illustration of structure 2200B in Figure 22B, following process to etch and form capacitors 2205. In at least one example, portion of insulator layer 2204 below lowermost surface 110B of structure 2302 is recessed. In at least one example, structure 2302 includes top electrode 108, dielectric 106, and electrode 112. In at least one Docket No.: KP12P064US-PCT example, the plasma etch forms surface 2204A, where surface 2204A is below uppermost surface 2204B and sidewall surface 2204C. In at least one example, lowermost surface 110B and uppermost surface 2204B are in contact with each other. In at least one example, the thickness of insulator layer 2204, as measured from lowermost surface 2204D to surface 2204A, is adequate for preventing hydrogen from diffusing from below insulator layer 2202. In at least one example, surface 2204A is substantially planar between two adjacent capacitors 102. In at least one example, structure 2302 comprises a same material as encapsulation structure 114 (Figure 1A). [00314] Figure 23B illustrates a cross-section of structure 2300B. In at least one example, structure 2300B is a cross sectional illustration of structure 2300A in Figure 23A, following process to laterally recess sidewall 110A. In at least one example, process utilized to recess sidewall 110A has been described above (Figure 12C). In at least one example, sidewall 2302A is substantially aligned with sidewall surface 2204C. [00315] Figure 23C illustrates a cross-section of structure 2300C. In at least one example, structure 2300C is a cross sectional illustration of structure 2300B in Figure 23B, following process to form encapsulation structure 2304. In at least one example, encapsulation structure 2304 is formed by blanket depositing and etching an encapsulation layer, as described above (Figure 12D). In at least one example, encapsulation structure 2304 comprises all the features of encapsulation structure 114 (Figure 1A). In at least one example, encapsulation structure 2304 further comprises portion 2304A in contact with sidewall surface 2204C and surface 2204A. In at least one example, when an encapsulation layer, utilized to form encapsulation structure 2304, has a lateral thickness that is at least half a vertical thickness TE1 of electrode 110, then cavity 2305 may be eliminated. [00316] Figure 24A illustrates a cross-section of structure 2400A. In at least one example, structure 2400A is a cross sectional illustration of structure 2200B in Figure 22B, following process to etch and form capacitors 2205. In at least one example, portion of insulator layer 2204 below lowermost surface 110B of structure 2302 is recessed. In at least one example, the plasma etch forms surface 2204A, where surface 2204A is gradually tapered below uppermost surface 2204B. In at least one example, the thickness of insulator layer 2204 at a lowest point, as measured from lowermost surface 2204D to surface 2204A, is adequate for preventing hydrogen from diffusing from 2202. In at least one example, surface 2204A can have a variable height as measured relative to lowermost surface 2204D in region between two adjacent electrodes 110. Docket No.: KP12P064US-PCT [00317] Figure 24B illustrates a cross-section of structure 2400B. In at least one example, structure 2400B is a cross sectional illustration of structure 2400A in Figure 24A, following process to laterally recess sidewall 110A. In at least one example, process utilized to recess sidewall 110A has been described above (Figure 12C). In at least one example, the process to recess sidewall 110A, exposes portions of uppermost surface 2204B. In at least one example, edge of uppermost surface 2204B is substantially aligned with sidewall 2302A. [00318] Figure 24C illustrates a cross-section of structure 2400C. In at least one example, structure 2400C is a cross sectional illustration of structure 2400B in Figure 24B, following process to form encapsulation structure 2402. In at least one example, encapsulation structure 2402 is formed by blanket depositing and etching an encapsulation layer, as described above (Figure 12D). In at least one example, encapsulation structure 2402 comprises a same material as encapsulation structure 114 (Figure 1A). In at least one example, encapsulation structure 2402 comprises at least some of the features of encapsulation structure 114 (Figure 1A). In at least one example, encapsulation structure 2402 further comprises portion 2402A that follows a contour of surface 2204B. In at least one example, when encapsulation layer utilized to form encapsulation structure 2402, has a lateral thickness that is at least half a vertical thickness TE1 of electrode 110, then cavity 2403 may be eliminated. [00319] Figure 25 illustrates a cross-section of structure 2500. In at least one example, structure 2500 is a cross sectional illustration of structure 2200C in Figure 22C following process to mask and pattern insulator layer 2204. In at least one example, mask 2501 is formed above capacitor 102, encapsulation structure 114, and insulator layer 2204. In at least one example, mask 2501 has a lateral thickness that extends beyond encapsulation structure 114. In at least one example, mask 2501 may be formed from a sacrificial material that can be removed after patterning insulator layer 2204. In at least one example, after forming mask 2501, insulator layer 2204 is patterned and removed from above insulator layer 2202 in memory region 2201A and logic region 2201B. In at least one example, two capacitors 102 are shown, where individual capacitor 102 is separated from a nearest capacitor 102. The patterning process forms an island of insulator layer 2204 around individual electrode structure 116. In at least one example, island of insulator layer 2204 is sufficient to block hydrogen from reaching capacitor 102. [00320] Figure 26A illustrates a cross-section of structure 2600A. In at least one example, structure 2600A is a cross sectional illustration of structure 2200B in Figure 22B following process to laterally recess electrode 110, deposit encapsulation layer 1214, deposit and planarize dielectric 2206, followed by process to mask and etch dielectric 2206, Docket No.: KP12P064US-PCT encapsulation layer 1214, and insulator layer 2204. In at least one example, process to form encapsulation layer 1214 is described above (Figure 12D). [00321] In at least one example, dielectric 2206 is deposited and planarized by process methodology described above (Figure 22D). In at least one example, the planarization process utilized to planarize dielectric 2206 and remove it from above encapsulation layer 1214, does not remove encapsulation layer 1214 from above top electrode 108. In at least one example, mask 2601 is formed above dielectric 2206 and encapsulation layer 1214. In at least one example, a plasma etch process is utilized to etch dielectric 2206, encapsulation layer 1214, and insulator layer 2204 from logic region 2201B. [00322] Figure 26B illustrates a cross-section of structure 2600B. In at least one example, structure 2600B is a cross sectional illustration of structure 2600A in Figure 26A following process to form dielectric 2208 in logic region 2201B. In at least one example, the method of forming dielectric 2208 is substantially the same as method described above (Figure 22F). In at least one example, dielectric 2208 is deposited on portions of encapsulation layer 1214 above top electrode 108. In at least one example, the CMP process utilized to planarize dielectric 2208 that is deposited in memory region 2201A, does not remove encapsulation layer 1214 from above capacitor 102. In at least one example, some dishing of dielectric 2206 adjacent to encapsulation layer 1214 may occur as a result of CMP process. [00323] Figure 26C illustrates a cross-section of structure 2600C. In at least one example, structure 2600C is a cross sectional illustration of structure 2600B in Figure 26B following process to form via electrode 2214 coupled with top electrode 108 in memory region 2201A, and form metal line 2228, metal line 2226, and electrode 2224 in logic region 2201B. In at least one example, etch stop layer 2210 is blanket deposited on encapsulation layer 1214, dielectric 2206, and dielectric 2208, and dielectric is blanket deposited on etch stop layer 2210. [00324] In at least one example, process utilized to form electrode 2214 is substantially similar to process described above (Figures 22G-22H) with the exception that via opening formed in dielectric 2212 and in etch stop layer 2210 is extended through encapsulation layer 1214 to expose top electrode 108. In at least one example, process utilized to form metal line 2228, metal line 2226, and electrode 2224 is same or substantially the same as process described above (Figures 22G-22H). [00325] Figure 27A illustrates a cross-section of structure 2700A. In at least one example, structure 2700A is a cross sectional illustration of structure 2200A in Figure 22A, where electrode structure 116 is further laterally surrounded by sacrificial layer 2702 which is Docket No.: KP12P064US-PCT formed above insulator layer 2204. In at least one example, sacrificial layer 2702 is part of initial multi-layer stack 2703. In at least one example, sacrificial layer 2702 includes a material of sacrificial layer 1502 (Figure 15A). [00326] Transistors 618 and transistor 2014 (Figure 21) are not illustrated for clarity. In at least one example, sacrificial layer 1502 is blanket deposited on insulator layer 2204. In at least one example, sacrificial layer 2702 comprises an insulator that includes a material which can be selectively removed relative to insulator layer 2204 and one or more layers in multi- layer stack to be deposited above. In at least one example, sacrificial layer 2702 is blanket deposited on etch stop layer 118 by a PVD, CVD, PECVD, or an ALD process. In at least one example, sacrificial layer 2702 is deposited to a thickness between 2nm and 30nm. In at least one example, thickness of sacrificial layer 2702 may be determined by process utilized to form electrode structure 116. In at least one example, electrode structures 116 are formed within multi-layer stack 2701 by methods similar to methods described above (Figure 15A- 15B), with the exception that opening is formed in a trilayer stack comprising sacrificial layer 2702, insulator layer 2204 and insulator layer 2202 as opposed to opening in a bilayer stack. In at least one example, no electrode structure is formed in logic region 2201B. [00327] Figure 27B illustrates a cross-section of structure 2700B. In at least one example, structure 2700B is a cross sectional illustration of structure 2700A in Figure 27A, following process to form capacitors 402. In at least one example, two capacitors are shown in the Figure. In at least one example, the method utilized to form capacitors 402 is the same as methods described above (Figures 15C-15D). In at least one example, plasma etch process utilized to form capacitors 402 is selective to sacrificial layer 2702. In at least one example, some portions of sacrificial layer 2702 may be removed by over etching to form electrode 112. [00328] Figure 27C illustrates a cross-section of structure 2700C. In at least one example, structure 2700C is a cross sectional illustration of structure 2700B in Figure 27B, following process to remove sacrificial layer 2702. Referring collectively to Figures 27B and 27C, in at least one example, sacrificial layer 2702 is removed by a wet chemical etch, where the wet chemical etch may be selective to top electrode 108, dielectric 106, electrode 112, and insulator layer 2204. In at least one example, wet chemical etch may be used to effectively remove sacrificial layer 2702 under electrode 112. In at least one example, complete removal of sacrificial layer 2702 forms cavity 2705 between electrode 112, insulator layer 2204, and electrode structure 116. In at least one example, cavity 2705 exposes portions of sidewall Docket No.: KP12P064US-PCT 116A. In at least one example, lateral thickness of cavity 2705 depends on size of lateral thickness WC relative to lateral thickness WES, where WC is greater than WES. [00329] Figure 27D illustrates a cross-section of structure 2700D. In at least one example, structure 2700D is a cross sectional illustration of structure 2700C in Figure 27C, following process to form encapsulation structure 404 on capacitor 402, on uppermost surface 118A, and adjacent to sidewall 116A. In at least one example, encapsulation structure 404 has one or more features of encapsulation structure 404 (Figure 4A). In at least one example, method of forming encapsulation structure 404 is described above (Figures 15F and 15G). In at least one example, material of encapsulation structure 404 does not extend on insulator layer 2204 between two capacitors 402. [00330] Figure 27E illustrates a cross-section of structure 2700E. In at least one example, structure 2700E is a cross sectional illustration of structure 2700D in Figure 27D, following process to form dielectric 2206 in memory region 2201A. In at least one example, dielectric 2206 is blanket deposited on structure 2700D (Figure 27D) by a PVD, CVD, PECVD, or an ALD process. In at least one example, dielectric 2206 is planarized. In at least one example, the planarization process exposes a top surface of top electrode 108. [00331] In at least one example, the planarization process removes a portion of top electrode 108 and upper portions of encapsulation structure 404 adjacent to top electrode 108, rendering a substantially planar top surface (not shown). In at least one example, substantially planar top surface of encapsulation structure 404 is co-planar or substantially co-planar with uppermost surface 108B. [00332] In at least one example, mask 2707 is formed on dielectric 2206, and on top electrode 108. In at least one example, a plasma etch process is utilized to remove dielectric 2206 and insulator layer 2204 from logic region 2201B. In at least one example, because of differences in etch rate between insulator layer 2204 and insulator layer 2202, insulator layer 2204 can be removed selectively with little to no removal of insulator layer 2202. In at least one example, uppermost surface 2202A of insulator layer 2202 may be recessed in logic region 2201B by up to 2 nm. In at least one example, mask 2707 may be removed after etching dielectric 2206 and insulator layer 2204. In at least one example, process operations described in association with Figures 22E-22J may be implemented on structure 2700E to form system 2100. [00333] In at least one example, method to form encapsulation structure includes depositing an encapsulation layer but not etching the encapsulation layer. Figure 28 illustrates a cross-section of structure 2800. In at least one example, structure 2800 is a cross Docket No.: KP12P064US-PCT sectional illustration of structure 2700C in Figure 27C following process to deposit encapsulation layer 2802, and deposit and pattern dielectric 2206. In at least one example, encapsulation layer 2802 includes a material that is the same or substantially the same as material of encapsulation structure 404. In at least one example, after blanket deposition of 2206, a planarization process such as CMP is performed. In at least one example, the CMP process removes excess dielectric 2206 from above encapsulation layer 2802. In at least one example, encapsulation layer 2802 acts as a polish stop. [00334] In at least one example, mask 2803 is formed on dielectric 2206. In at least one example, a plasma etch process is utilized to etch dielectric 2206, encapsulation layer 2802, and insulator layer 2204 from logic region 2201B. In at least one example, the fabrication process may be continued, and process operations described in association with Figures 26B and 26C may be utilized to form via electrodes coupled with individual capacitors 402 in 2201B, and form electrode 2224, and metal line 2226 in logic region 2201B of structure 2800. [00335] In at least one example, barrier structure 2006 (Figure 20A) may be formed prior to patterning a multi-layer stack and form one or more capacitors. Figures 29A-29C illustrate a process flow for patterning and forming capacitors, in at least one example. [00336] Figure 29A illustrates a cross-section of structure 2900A. In at least one example, structure 2900A is a cross sectional illustration of structure 2200A in Figure 22A following process to pattern insulator layer 2204 from logic region 2201B. In at least one example, 2901 is formed on insulator layer 2204 and on electrode structure 116. In at least one example, a plasma etch process is utilized to etch insulator layer 2204 from unmasked portions in logic region 2201B. In at least one example, the plasma etch process is substantially selective to insulator layer 2202. In at least one example, insulator layer 2202 is deposited to a minimum thickness that can provide etch selectivity during etching of a dielectric to be formed in logic region 2201B in a downstream operation. [00337] Figure 29B illustrates a cross-section of structure 2900B. In at least one example, structure 2900B illustrates a cross-section of structure 2900A in Figure 29A, following process to form a portion of multi-layer stack 1201 on electrode structure 116 and on insulator layer 2204 in 2201A, and a portion of multi-layer stack 1201 on insulator layer 2202 in logic region 2201B. In at least one example, number of layers in multi-layer stack 1201 can depend on a type of memory device to be fabricated. In at least one example, process to form multi-layer stack 1201 includes blanket deposition of at least three material layers, to form capacitor 402 (Figure 4A). In at least one example, process to form multi-layer stack Docket No.: KP12P064US-PCT 1201 includes blanket deposition of at least four layers to form capacitor 102 (Figure 1A). In at least one example, multi-layer stack 1201 includes deposition of layers for a ferroelectric memory device. In at least one example, multi-layer stack 1201 includes deposition of layers for a paraelectric memory device. In at least one example, a transition region between memory region 2201A and logic region 2201B can produce a step height within layers in multi-layer stack 1201. In at least one example, the step height can be between 3 nm and 50 nm. [00338] Figure 29C illustrates a cross-section of structure 2900C. In at least one example, structure 2900C illustrates a cross-section of structure 2900B in Figure 29B following process to pattern multi-layer stack 1201 to form capacitors 2902. Referring collectively to Figures 29A and 29B, a plasma etch process is utilized to etch multi-layer stack 1201. In at least one example, plasma etch process may include a discharge produced by a magnetic enhanced reactive ion etching mechanism, an electron cyclotron resonance discharge or an inductively coupled plasma discharge. In at least one example, residue 1201A of multi-layer stack 1201 may be formed on sidewall 2204E. In at least one example, residue 1201A may include one or more layers of capacitor 2902. In an example, an over etch may be performed to remove residue 1201A. [00339] In at least one example, the fabrication process may be continued to completion. For example, electrode 110 may be laterally recessed and encapsulation layer may be deposited and etched to form encapsulation structure on capacitors 2902. In at least one example, a portion of encapsulation layer utilized to form encapsulation structure may be formed on sides of residue 1201A. Other operations such as formation of dielectrics in memory region 2201A and logic region 2201B and formation of electrodes coupled with capacitors and logic transistor may be carried out, in accordance with examples discussed above. [00340] In at least one example, one or more layers in multi-layer stack 2703 in Figure 27A, may be etched prior to forming capacitor above electrode structure 116. Figure 30A illustrates a cross-section of structure 3000A. In at least one example, structure 3000A illustrates a cross-section of structure 2700A in Figure 27A, following process to pattern a portion of multi-layer stack 2703 prior to forming capacitors. Referring collectively to Figures 27A and 30A, in at least one example, mask 3001 is formed on multi-layer stack 2703, where mask 3001 includes a photoresist material. In at least one example, a plasma etch process is utilized to etch multi-layer stack 2703 to form intermediate structure 3002. In at least one example, plasma etch process may include a discharge produced by a magnetic Docket No.: KP12P064US-PCT enhanced reactive ion etching mechanism, an electron cyclotron resonance discharge or an inductively coupled plasma discharge. In at least one example, sacrificial layer 2702 and insulator layer 2204 are etched from logic region 2201B to form intermediate structure 3002. [00341] Figure 30B illustrates a cross-section of structure 3000B. In at least one example, structure 3000B illustrates a cross-section of structure 3000A in Figure 30A, following process to form capacitor 402. Referring collectively to Figures 15C, 30A, and 30B, in at least one example, multi-layer stack 1506 is formed on structure 3000A after removal of mask 3001. In at least one example, multi-layer stack 1506 may or may not include a layer to form electrode 110. In at least one example, a plasma etch process is utilized to etch multi- layer stack 1506 to form capacitor 402 above an individual electrode structure 116. In at least one example, residue 1506A of multi-layer stack 1506 may be formed on sidewall 2204E and sidewall 2702A. In at least one example, residue 1506A may include one or more layers of capacitor 402. In an example, an over etch may be performed to remove residue 1506A. [00342] Figure 30C illustrates a cross-section of structure 3000C. In at least one example, structure 3000C illustrates a cross-section of structure 3000B in Figure 30B following process to remove sacrificial layer 2702 from above insulator layer 2204 and from under electrode 112. Referring collectively to Figures 30B and 30C, in at least one example, the process to remove sacrificial layer 2702 is described above (Figure 27C). In at least one example, residue 1506A formed adjacent to sidewall 2702A and sidewall 2204E may remain. In at least one example, residue 1506A may extend above uppermost surface 2204B. [00343] In at least one example, the fabrication process may be continued to laterally form encapsulation layer or etch the encapsulation layer to form encapsulation structure on capacitor 402. In at least one example, encapsulation layer utilized to form encapsulation structure may be formed on residue 1506A, where portions of the encapsulation layer may extend on portions of uppermost surface 2204B, and on portion of uppermost surface 2202A in logic region 2201B. [00344] In at least one example, the fabrication process may be continued to completion. For example, operations such as formation of dielectrics in memory region 2201A and logic region 2201B and formation of electrodes coupled with capacitors and logic transistor may be carried out, in accordance with examples discussed above. [00345] Figure 31 illustrates computing architecture 3100 with a coherent cache or memory-side buffer chiplet that includes a memory controller, wherein the coherent cache or memory-side buffer chiplet is coupled to an accelerator, a processor, and a memory, in accordance with at least one example. In at least one example, computing architecture 3100 Docket No.: KP12P064US-PCT comprises coherent cache or memory-side buffer chiplet 3101, accelerator 3102 (e.g., inference chip), processor (e.g., processor 3120), and memory die 3104. In at least one example, coherent cache or memory-side buffer chiplet 3101 comprises at least two channels 3125 which are configured to connect with accelerator 3102 and processor 3120. In at least one example, coherent cache or memory-side buffer chiplet 3101 comprises I/O and controller 3110 to manage data traffic with memory die 3104. By moving controller 3110 from processor 3120 to coherent cache or memory-side buffer chiplet 3101, cost in terms of power and die area for processor 3120 is reduced. In at least one example, coherent cache or memory-side buffer chiplet 3101 is a cache memory that comprises ferroelectric memory cells. For example, coherent cache or memory-side buffer chiplet 3101 comprises one or more of: FE-SRAM, FE-DRAM, SRAM, MRAM, resistance RAM (Re-RAM), embedded DRAM (e.g., 1T-1C based memory), or a combination of them. Using FE-SRAM, MRAM, or Re-RAM allows for low power and high-speed memory operation. [00346] Figure 32 illustrates architecture 3200 of the coherent cache or memory-side buffer chiplet 3207 with multiple controllers and multiple cache banks, in accordance with at least one example. In at least one example, architecture 3200 comprises channels (e.g., channel 3215-1, which can be ch0 and channel 3215-2, which can be ch1), cache banks 3201, cache controller 3202, non-volatile (NV) controller 3203, and reliability logic 3204. In at least one example, cache controller 3202 is a local cache controller. In at least one example, coherent cache or memory-side buffer chiplet 3207 may function as a cache or memory buffer. In at least one example, cache lookups can map a large physical memory into a small physical cache using indirection via tags. Here, indirection refers to the use of tags to specify which address maps to which physical location. In at least one example, if multiple addresses can map to a single physical location, a tag is used to figure out which address is currently mapped. [00347] In at least one example, each cache bank 3201 includes data bank 3205 (e.g., comprising memory cells) and associated tags 3206. In at least one example, data bank 3205 comprises ferroelectric memory cells. In at least one example, data bank 3205 comprises one or more of: FE-SRAM, FE-DRAM, SRAM, MRAM, resistance RAM (Re-RAM), embedded DRAM (e.g., 1T-1C based memory), or a combination of them. Using FE-SRAM, MRAM, or Re-RAM allows for low power and high-speed memory operation. In at least one example, when data bank 3205 includes ferroelectric memory, it uses NV controller 3203 and a stronger reliability logic (e.g., error correction code) for security compared to non- ferroelectric memory for data bank 3205. Docket No.: KP12P064US-PCT [00348] In at least one example, when data bank 3205 is used to implement a cache, tags may be used to identify which addresses map to which physical locations in the bank. In at least one example, cache may be set associative, in which a particular address can map to several physical locations. The specific physical location a newly allocated address is mapped to may be determined by a replacement algorithm, such as LRU (least recently used) or pseudo-LRU, or even random. On the other hand, the cache might be direct mapped, with each address mapping to merely a single physical cache line. In at least one example, in both set associative and direct mapped caches, several addresses map to a single physical cache line. In at least one example, to identify the address currently occupying the physical cache line, tag 3206 may be coupled with a physical line. Tag 3206 may comprise some address bits, sufficient to uniquely identify which address currently occupies the physical line coupled with the tag. [00349] In at least one example, cache controller 3202 could be used to control state transitions used for cache look ups such as comparing requested addresses with tags stored in an array of tags 3206, and identifying a candidate for replacement (replacement algorithm) when a cache miss occurs. In at least one example, cache controller could be tasked with initializing the cache when the cache power is on. In at least one example, when FE memory of data bank 3205, which retains state across power cycles, is used, cache controller 3202 could write 0s to all memory locations to ensure that data associated with previously executed programs is erased, thus preventing any data leakage to subsequently executed programs, in at least one example. In at least one example, non-volatile memory may also include an NV bit, which could indicate that cache data is meant to be non-volatile and remain across power cycles. In at least one example, cache controller 3202 may skip locations marked thus when initializing memory. [00350] In at least one example, reliability logic 3204 performs error correction to the data. Any suitable error correction scheme (e.g., with error correction code (ECC)) may be used by reliability logic 3204. In at least one example, non-volatile (NV) controller 3203 is provided to explicitly clear the cache when using a non-volatile memory, such as FM memory for data bank 3205. In at least one example, NV controller 3203 may include an NV bit which indicates cache lines that should not be cleared but are expected to retain their contents across power cycles. In at least one example, functions of NV controller 3203 can be combined in cache controller 3202, or vice versa. [00351] Figure 33 illustrates apparatus 3300 comprising an MxN memory array of bit- cells and corresponding periphery circuitry, in accordance with at least one example. In at Docket No.: KP12P064US-PCT least one example, apparatus 3300 comprises MxN memory array 3301 of bit-cells, logic circuitry 3302 for address decoding, and logic circuitry 3303 for sense amplifier and BL driver, and logic circuitry 3304 for write drivers, and plate-line (PL) drivers. In at least one example, plate-lines PL0, PL1 through PLN are parallel to word-lines WL0, WL1, through WLM while bit-lines BL0, BL1 through BLN are orthogonal to the plate-lines and the word- lines, where ‘N’ is a number greater than 1. In at least one example, plate-lines PL0, PL1, through PLN are parallel to bit-lines BL0, BL1 through BLN, while word-lines WL0, WL1, through WLM are orthogonal to the plate-lines and the bit-lines, where ‘N’ is a number greater than 1. In at least one example, individual memory bit-cells in memory array 3301 are organized in rows and columns. In at least one example, memory bit-cells 33010,0 through 3301M,N are organized in an array. [00352] In at least one example, an individual memory bit-cell (e.g., 33010,0) is a 1TnC bit-cell. An example of a 1TnC bit-cell is described with reference to Figures 31A-31B. Referring again to Figure 33, in at least one example, an individual memory bit-cell (e.g., 33010,0) is a multi-element FE gain bit-cell. An example of a 1TnC bit-cell is described with reference to Figures 32A-32B. Referring again to Figure 33, in at least one example, an individual memory bit-cell (e.g., 33010,0) is a multi-element FE gain bit-cell, where an individual capacitor of the bit-cell is connected to a transistor switch. [00353] Referring again to Figure 33, in at least one example, when multiple capacitors are used per bit-cell, the access transistor may be made larger. In at least one example, the access transistor is connected to the bit-line as the bit-line drives a gate terminal of the access transistor. In an example, a larger access transistor can add capacitance to the bit-line. In at least one example, one way to reduce the bit-line capacitance is to route the bit- line on higher level metal layers. In at least one example, higher-level metal layers are usually occupied by ground and supply routes. In at least one example, connecting the gate of the access transistor to higher-level metal layers to access the bit-line means traversing through contact regions and vias. Such signal path may increase resistance and capacitance on the bit-line. In at least one example, memory array 3301 is split into two or more subarrays with bit-line multiplexers between the subarrays. In at least one example, by splitting the array, bit-line routes are split along the subarrays via a selection circuitry. In at least one example, the selection circuitry decouples the bit-line into separate bit-line routes which allows the capacitance on the bit-line to reduce as parasitic capacitance from the bit- line route is reduced, and bit-line is not driving all the access transistors in a row of the array. Docket No.: KP12P064US-PCT [00354] In at least one example, wear-leveling logic 3306 provides one or more endurance mechanisms for the 1TnC memory bit-cells. In at least one example, one of the endurance mechanisms involves refreshing of the data content in the capacitor(s). [00355] Figure 34 illustrates a high-level architecture of artificial intelligence (AI) machine 3400 comprising a compute die positioned on top of a memory die, in accordance with at least one example. In at least one example, AI machine 3400 comprises computational block 3401 or processor having memory 3402 (e.g., random access memory (RAM)) and compute die 3403, RAM 3404 (e.g., static RAM (SRAM), ferroelectric or paraelectric RAM (FeRAM), ferroelectric or paraelectric static random-access memory (FeSRAM)), processor 3405, RAM 3406 (dynamic RAM (DRAM), FeRAM)), and solid-state memory or solid-state drive 3407. In at least one example, some or all components of AI machine 3400 are packaged in a single package forming a system-on-chip (SoC). In at least one example, SoC can be configured as a logic-on-logic configuration, which can be in a 3D configuration or a 2.5D configuration. [00356] In at least one example, computational block 3401 is packaged in a single package and then coupled to processor 3405 and RAM 3404 and 3406, and solid-state drive 3407 on a printed circuit board (PCB). In at least one example, computational block 3401 is configured as a logic-on-logic configuration, which can be in a 3D configuration or a 2.5D configuration. In at least one example, computational block 3401 comprises special purpose compute die 3403 or microprocessor. In at least one example, compute die 3403 is a compute chiplet that performs a function of an accelerator or inference. In at least one example, memory 3402 is DRAM which forms a special memory/cache for the special purpose compute die 3403. In at least one example, DRAM can be embedded DRAM (eDRAM) such as 1T-1C (one transistor and one capacitor) based memories. In at least one example, memory 3402 is ferroelectric or paraelectric RAM (Fe-RAM). [00357] In at least one example, compute die 3403 is specialized for applications such as Artificial Intelligence, graph processing, and algorithms for data processing. In at least one example, compute die 3403 further has logic computational blocks, for example, for multipliers and buffers, special data memory block (e.g., buffers) comprising DRAM, FeRAM, or a combination of them. In at least one example, memory 3402 has weights and inputs stored in-order to improve the computational efficiency. In at least one example, interconnects between processor 3405 (also referred to as special purpose processor), RAM 3404, and compute die 3403 are optimized for high bandwidth and low latency. In at least one example, architecture of Figure 34 allows efficient packaging to lower the energy, Docket No.: KP12P064US-PCT power, or cost and provides for ultra-high bandwidth between memory 3402 and compute die 3403 of computational block 3401. [00358] In at least one example, memory 3402 is partitioned to store input data (or data to be processed) 3402A and computed weights 3402B. In at least one example, input data 3402A are stored in a separate memory (e.g., a separate memory die) and computed weights 3402B are stored in a separate memory (e.g., separate memory die). [00359] In at least one example, compute die 3403 comprises matrix multiplier, adder, concatenation logic, buffers, and combinational logic. In at least one example, compute die 3403 performs multiplication operation on input data 3402A and computed weights 3402B. In at least one example, computed weights 3402B are fixed weights. For example, processor 3405 (e.g., a graphics processor unit (GPU), field programmable grid array (FPGA) processor, application specific integrated circuit (ASIC) processor, digital signal processor (DSP), an AI processor, a central processing unit (CPU), or any other high-performance processor) computes the weights for a training model. Once the weights are computed, they are stored in memory 3402. In at least one example, input data, that is to be analyzed using a trained model, is processed by computational block 3401 with computed weights 3402B to generate an output (e.g., a classification result). [00360] In at least one example, RAM 3404 is ferroelectric or paraelectric based SRAM. For example, six transistor (6T) SRAM bit-cells having ferroelectric or paraelectric transistors are used to implement non-volatile FeSRAM. In at least one example, solid-state drive 3407 comprises NAND flash cells. In at least one example, solid-state drive 3407 comprises NOR flash cells. In at least one example, solid-state drive 3407 comprises multi- threshold NAND flash cells. [00361] In at least one example, non-volatility of FeRAM is used to introduce new features such as security, functional safety, and faster reboot time of AI machine 3400. The non-volatile FeRAM is a low power RAM that provides fast access to data and weights. In at least one example, RAM 3404 that is an FeRAM can also serve as a fast storage for computational block 3401 (or accelerator), which typically has low capacity and fast access requirements. [00362] At least one example, the FeRAM (FeDRAM or FeSRAM) includes ferroelectric or paraelectric material. In at least one example, ferroelectric or paraelectric (FE) material may be in a transistor gate stack or in a capacitor of the memory. In at least one example, ferroelectric material can be any suitable low voltage FE material that allows the FE material to switch its state by a low voltage (e.g., 3400 mV). In at least one example, Docket No.: KP12P064US-PCT threshold in the FE material has a highly non-linear transfer function in the polarization vs. voltage response. In at least one example, threshold is related to: a) non-linearity of switching transfer function, and b) to the squareness of the FE switching. The non-linearity of switching transfer function is the width of the derivative of the polarization vs. voltage plot. In at least one example, squareness is defined by the ratio of the remnant polarization to the saturation polarization; perfect squareness will show a value of 1. [00363] In at least one example, squareness of the FE switching can be suitably manipulated with chemical substitution. For example, in PbTiO3 a P-E (polarization-electric field) square loop can be modified by La or Nb substitution to create an S-shaped loop. In at least one example, shape can be systematically tuned to ultimately yield a non-linear dielectric. The squareness of FE switching can also be changed by the granularity of FE layer. In at least one example, a perfectly epitaxial, single crystalline FE layer will show higher squareness (e.g., ratio is closer to 1) compared to a polycrystalline FE. In at least one example, this perfect epitaxial can be accomplished using lattice matched bottom and top electrodes. In one example, BiFeO (BFO) can be epitaxially synthesized using a lattice matched SrRuO3 bottom electrode yielding P-E loops that are square. In at least one example, progressive doping with La will reduce the squareness. [00364] In at least one example, FE material includes material of ferroelectric layer which are same as those described herein. [00365] In at least one example, FE material is between two electrodes that comprise perovskite templated conductors. In such a templated structure, a thin layer (e.g., approximately 10 nm) of a perovskite conductor (such as SrRuO3) is coated on top of IrO2, RuO2, PdO2, or PtO2 (which have a non-perovskite structure but higher conductivity) to provide a seed or template for the growth of pure perovskite ferroelectric material at low temperatures. [00366] Figure 35 illustrates 3-input majority gate 3500 using non-linear input capacitors, in accordance with at least one example. In at least one example, 3-input majority gate 3500 comprises non-linear input capacitors C1nl, C2nl, and C3nl that receive digital signals a, b, and c, respectively. Here, signal names and node names are interchangeably used. For example, ‘a’ refers to node ‘a’ or signal ‘a’ depending on the context of the sentence. In at least one example, one end or terminal of capacitor C1nl is coupled to node a while the other end of capacitor C1n1 is coupled to summing node Vs. The same is true for other non-linear capacitors C2n1 and C3nl, as shown. In at least one example, 3-input majority gate 3500 comprises driver circuitry 3501. In at least one example, driver circuitry Docket No.: KP12P064US-PCT 3501 is an inverter. In at least one example, other types of driver circuitries can be used, such as NAND gate, NOR gate, multiplexer, buffer, or other logic gates. In at least one example, majority function is performed at summing node Vs as Majority(a,b,c). In at least one example, driver circuitry 3501 is an inverter, minority function is performed at output “out” as Minority(a,b,c). [00367] In at least one example, in addition to the gate capacitance of driver circuitry 3501, an additional linear capacitor CL is coupled to summing node Vs and ground as shown. In at least one example, linear capacitor CL is a non-ferroelectric capacitor. In at least one example, the non-ferroelectric capacitor includes one of: dielectric capacitor, paraelectric capacitor, or non-linear dielectric capacitor. In at least one example, a dielectric capacitor comprises a first metal plate and a second metal plate with a dielectric between them. In at least one example, dielectric includes one or more of: HfOX, ABO3 perovskites, nitrides, oxy- fluorides, oxides, etc. In at least one example, a paraelectric capacitor comprises a first metal plate and a second metal plate with paraelectric material between them. In at least one example, f-orbital materials (e.g., lanthanides) are doped to the ferroelectric materials to make paraelectric material. Examples of room temperature paraelectric material include: SrTiO3, Ba(x)Sr(y)TiO3, HfZrO2, Hf-Si-O, La-substituted PbTiO3, or PMN-PT based relaxor ferroelectrics. In at least one example, a dielectric capacitor comprises a first metal plate and a second metal plate with a non-linear dielectric capacitor between them. In at least one example, the range for dielectric constant is 1.2 to 10000. In at least one example, capacitor CL can be implemented as MIM (metal-insulator-metal) capacitor technology, transistor gate capacitor, hybrid of metal capacitors, or transistor capacitor. In at least one example, capacitor CL can be implemented as MIM (metal-insulator-metal) capacitor technology, transistor gate capacitor, hybrid of metal capacitors, or transistor capacitor. [00368] In at least one example, non-linear input capacitors C1nl, C2nl, and C3nl comprise non-linear polar material. In at least one example, non-linear polar material includes one of: ferroelectric (FE) material, paraelectric material, relaxor ferroelectric, or non-linear dielectric. In at least one example, paraelectric material is same as FE material, but with chemical doping of the active ferroelectric ion by an ion with no polar distortion. In at least one example, non-polar ions are non-s orbital ions formed with p, d, or f external orbitals. In at least one example, non-linear dielectric materials are same as paraelectric materials, relaxors, and dipolar glasses. [00369] In at least one example, the FE material can be any suitable low voltage FE material that allows the FE material to switch its state by a low voltage (e.g., 100 mV). In at Docket No.: KP12P064US-PCT least one example, threshold in the FE material has a highly non-linear transfer function in the polarization versus voltage response. The threshold is related to: a) non-linearity of switching transfer function; and b) the squareness of the FE switching. In at least one example, non-linearity of switching transfer function is the width of the derivative of the polarization versus voltage plot. In at least one example, squareness is defined by the ratio of the remnant polarization to the saturation polarization; perfect squareness will show a value of 1. [00370] In at least one example, squareness of FE switching can be suitably manipulated with chemical substitution. In at least one example, in PbTiO3 a P-E (polarization-electric field) square loop can be modified by La or Nb substitution to create an S-shaped loop. The shape can be systematically tuned to ultimately yield a non-linear dielectric. In at least one example, squareness of FE switching can also be changed by granularity of the FE layer. In at least one example, a perfect epitaxial, single crystalline FE layer may show higher squareness (e.g., ratio is closer to 1) compared to polycrystalline FE. In at least one example, a perfect epitaxial can be accomplished by use of lattice matched bottom and top electrodes. In at least one example, BiFeO (BFO) can be epitaxially synthesized using lattice matched SrRuO3 bottom electrode yielding P-E loops that are square. In at least one example, progressive doping with La may reduce squareness. [00371] In at least one example, the charge developed on node Vs produces a voltage and current that is the output of 3-input majority gate 3500. In at least one example, any suitable driver circuitry 3501 can drive this output. In at least one example, non-FE logic, FE logic, CMOS logic, BJT logic, etc. can be used to drive the output to a downstream logic. In at least one example, drivers include one or more of inverters, buffers, NAND gates, NOR gates, XOR gates, amplifiers, comparators, digital-to-analog converters, analog-to-digital converters, multiplexers, etc. [00372] In at least one example, the majority function is performed at the summing node Vs, and the resulting voltage is projected on to capacitance of driver circuitry 3501. In at least one example, majority function of the currents (Ia, Ib, and Ic) on node Vs results in a resultant current that charges capacitor. Table 1 illustrates the majority function f(Majority a, b, c). Table 1 a b c Vs (f(Majority a, b, c))
Figure imgf000077_0001
Docket No.: KP12P064US-PCT 0 0 1 0 0 1 0 0 [00373]
Figure imgf000078_0001
ltage and current that is the output of 3-input majority gate 3500. In at least one example, any suitable driver circuitry 3501 can drive this output. For example, a non-FE logic, FE logic, CMOS logic, or BJT logic, etc. can be used to drive the output to a downstream logic. In at least one example, drivers include inverters, buffers, NAND gates, NOR gates, XOR gates, amplifiers, comparators, digital-to-analog converters, analog-to-digital converters, or multiplexers, etc. [00374] While Figure 35 illustrates a 3-input majority gate, the same concept can be extended to more than 3 inputs to make an N-input majority gate, where N is greater than 2, in accordance with at least one example. In at least one example, ‘N’ is an odd number. In at least one example, 5-input majority gate is similar to a 3-input majority gate 3500 but for additional inputs ‘d’ and ‘e’. In at least one example, inputs can come from the same drivers or from different drivers. [00375] In at least one example, the 3-input majority gate can be configured as a fast inverter with a much faster propagation delay compared to a similar sized (in terms of area footprint) CMOS inverter. In at least one example, this may be useful when the inputs have a significantly slower slope compared to the propagation delay through the non-linear input capacitors. In at least one example, one way to configurate the 3-input majority gate as an inverter is to set one input to a logic high (e.g., b=1) and set another input to a logic low (e.g., b=0). In at least one example, third input is the driving input which is to be inverted. In at least one example, inversion will be at the Vs node. The same technique can also be applied to N-input majority gate, where ‘N’ is 1 or any other odd number. In at least one example, in an N-input majority gate, (N-1)/2 inputs are set to ‘1’ and (N-1)/2 inputs are set to ‘0’, and one input is used to decide the inversion function. The various examples are described as a majority gate, the same concepts are applicable to a minority gate. In a minority gate the Docket No.: KP12P064US-PCT driving circuitry is an inverting circuitry coupled to the summing node Vs. The minority function is seen at the output of the inverting circuitry. [00376] In at least one example, (2N-1) input majority gate can operate as an N-input AND gate where (N-1) inputs of the majority gate are set to zero. In at least one example, AND function will be seen at the summing node Vs. In at least one example, N-input NAND, OR, NOR gates can be realized. In at least one example, summing node Vs is driven by a driver circuitry (e.g., inverter, buffer, NAND gate, AND gate, OR gate, NOR gate, or any other logic circuitry). In at least one example, driver circuitry 3501 can be replaced with another majority or minority gate. In at least one example, storage node Vs is directly coupled to a non-linear capacitor of another majority or minority gate. [00377] In at least one example, any logic function f^x^, xଶ, ... x୬^can be represented by two levels of logic as given by the min-term expansion: f^x^, xଶ, ... x୬^ ൌ Vେభ,େమ,....େ^ f^x^, xଶ, ... x୬^ ∧ xେభ ^ ∧ xେమ ଶ ∧ xେయ ଷ ...∧ x େ ୬^ where C୧ is either 0 or 1. When C୧ is 1, xେ^ ୧ ൌ x୧ (the input is used in its original form). When C୧ is 0, xେ^ ୧ ൌ x୧ (the input is used in its inverted form). In at least one example, first level of logic is represented by at most 2୬ AND gates ^∆^, one for each of the 2୬ possible combinations of 0 and 1 for C^, Cଶ, .... C୬. The second level of logic is represented by a single OR gate (⋁). Each operand of the OR gate is a representation of a row in the truth table for f^x^, xଶ, ... x୬^. [00378] In at least one example, a (2N-1)-input majority gate can represent an N-input AND gate, by tying (N-1) of the majority gate’s inputs to a ground level. Similarly, a (2N-1)- input majority gate can represent an N-input OR gate, by tying (N-1) of the majority gate’s inputs to a supply level (Vdd). In at least one example, since a majority gate can represent AND and OR gates, and the inputs to the AND and OR gates are either original or inverted forms of the input digital signals, any logic function can be represented by majority gates and inverters. [00379] Figure 36 illustrates complex logic gate 3600 implemented using a 5-input majority gate, in accordance with at least one example. In at least one example, an AOI (and- or-invert) logic comprises a 5-input majority gate. In at least one example, 5-input majority gate includes non-linear capacitors C1n1, C2nl, C3nl, C4nl, and C5nl, and driving circuitry 3601 coupled as shown. In at least one example, two of the non-linear capacitors receive the same input. Here, capacitors C3nl and C4nl receive input ‘c’. In at least one example, C5nl is coupled to Vdd to produce an OR function at node Vs, where the OR function is Docket No.: KP12P064US-PCT OR(AND(a,b),c). In at least one example, other logic gates can be realized by changing Vdd to ground for capacitor C5nl, and/or changing other inputs. [00380] Example 1 is a device comprising: A device structure comprising: an electrode structure; a capacitor structure on the electrode structure, the capacitor structure comprising: a bottom electrode structure comprising: a first electrode comprising a first lateral thickness; and a second electrode on the first electrode, the second electrode comprising a second lateral thickness greater than the first lateral thickness; a dielectric comprising a non-linear polar material having a form ABB'O3, AA'B'O3, or ABO3, wherein A' is a first dopant for atomic site A, wherein B' is a second dopant for atomic site B, and wherein O is oxygen; and a third electrode on the dielectric; and an encapsulation structure comprising: a first portion adjacent to a first sidewall of the first electrode and adjacent to a lower surface of the second electrode; and a second portion adjacent to a second sidewall of the second electrode, a third sidewall of the dielectric, and a fourth sidewall of the third electrode. [00381] Example 2 is a device structure according to any device structure described herein, in particular example 1, wherein the first lateral thickness is at least 2 nm less than the second lateral thickness. [00382] Example 3 is a device structure according to any device structure described herein, in particular example 1, wherein the electrode structure comprises: a conductive hydrogen barrier layer comprising one of: TiAlN with greater than 30 atomic percent AlN, TaN with greater than 30 atomic percent nitrogen, TiSiN with greater than 20 atomic percent SiN, TaC, TiC, WC, WN, carbonitrides of Ta, Ti, W, TiO, Ti2O, WO3, SnO2, ITO, IGZO, zinc oxide or METGLAS series of alloys; and a fill metal within the conductive hydrogen barrier layer, wherein the fill metal comprises one of tantalum, titanium, ruthenium, tungsten, molybdenum or copper, wherein the second electrode comprises one of: a first non-Pb based metal oxide, such as but not limited to, La(1-x)Sr(x)FeO3, La(1-x)Sr(x)CoO3, La(1-x)Ca(x)MnO3, La(1-x)Sr(x)MnO3, Ba(1-x)Sr(x)RuO3, La(1-x)Sr(x)MnO3, wherein 0 ≤ x ≤ 1, SrRuO3, Sr2RuO4, SrMoO3, SrCoO3, SrCrO3, SrFeO3, SrVO3, CaMoO3, SrNbO3, LaNiO3, YBa2Cu3O7, Bi2Sr2CaCuO8, CaRuO3, Ir, Ir2Oy, Ru, RuOy, Mo, MoOy, W, or WOy, wherein ‘y’ is an integer, wherein the third electrode comprises one of: a second non-Pb metal oxide, such as but not limited to, La(1-x)Sr(x)FeO3, La(1-x)Sr(x)CoO3, La(1-x)Ca(x)MnO3, La(1-x)Sr(x)MnO3, Ba(1- x)Sr(x)RuO3, La(1-x)Sr(x)MnO3, wherein 0 ≤ x ≤ 1, SrRuO3, Sr2RuO4, SrMoO3, SrCoO3, SrCrO3, SrFeO3, SrVO3, CaMoO3, SrNbO3, LaNiO3, YBa2Cu3O7, Bi2Sr2CaCuO8, CaRuO3, Ir, Ir2Oy, Ru, RuOy, Mo, MoOy, W, or WOy, wherein ‘y’ is an integer, and wherein the first Docket No.: KP12P064US-PCT electrode comprises one of: niobium, chromium, molybdenum, tantalum, tungsten, rhenium, titanium, nitrogen doped variants of niobium, chromium, molybdenum, tantalum, tungsten, rhenium, titanium, nitrides of tantalum, tungsten, titanium, conductive doped AlN, or conductive doped SiN. [00383] Example 4 is a device structure according to any device structure described herein, in particular example 3, wherein the electrode structure comprises a third lateral thickness that is less than the first lateral thickness. [00384] Example 5 is a device structure according to any device structure described herein, in particular example 1, wherein the first electrode has a vertical thickness orthogonal to the first lateral thickness, wherein the first portion has a fourth lateral thickness, and wherein the fourth lateral thickness is different from the vertical thickness. [00385] Example 6 is a device structure according to any device structure described herein, in particular example 5, wherein the fourth lateral thickness varies with height, and wherein the fourth lateral thickness is at least equal to a quarter of the vertical thickness. [00386] Example 7 is a device structure according to any device structure described herein, in particular example 6, wherein the first portion and the second portion are contiguous, and wherein the first portion further comprises a cavity. [00387] Example 8 is a device structure according to any device structure described herein, in particular example 1, further comprising an insulator laterally adjacent to the electrode structure, wherein the second portion is in contact with the insulator. [00388] Example 9 is a device structure according to any device structure described herein, in particular example 8, further comprising a liner between the insulator and the electrode structure, wherein the second portion further extends on the liner. [00389] Example 10 is a device structure according to any device structure described herein, in particular example 9, wherein the encapsulation structure comprises one of: silicon nitride, carbon doped silicon nitride, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx, or TaSiOx, wherein ‘x’ and ‘y’ are first and second integers, respectively, wherein the liner comprises one of: silicon nitride, carbon doped silicon nitride, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx, or TaSiOx, wherein ‘x’ and ‘y’ are third and fourth integers, respectively, wherein the insulator comprises one of: silicon nitride, or carbon doped silicon nitride, and wherein the insulator and the encapsulation structure comprise a different material. Docket No.: KP12P064US-PCT [00390] Example 11 is a device structure according to any device structure described herein, in particular example 8, wherein the encapsulation structure further comprising a third portion that extends laterally on the insulator beyond an outer sidewall of the second portion. [00391] Example 12 is a device structure according to any device structure described herein, in particular example 11, wherein the encapsulation structure further comprising a fourth portion that extends on the second portion and on an uppermost surface of the third electrode. [00392] Example 13 is a device structure according to any device structure described herein, in particular example 5, wherein the second portion comprises a fifth lateral thickness, and wherein a minimum value of the fourth lateral thickness is equal to the fifth lateral thickness. [00393] Example 14 is a device structure according to any device structure described herein, in particular example 1, wherein the dielectric comprises: the form ABB'O3, wherein A includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na, wherein B includes one of Mn, Fe, Ta, or Nb, and wherein B' includes one of: Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, or Zn, the form ABO3, wherein A includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na, and wherein B includes one of Mn, Fe, Ta, or Nb; or the form AA'BO3, wherein A includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na, wherein B includes one of Mn, Fe, Ta, or Nb, and wherein A' includes one of Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, or Lu. [00394] Example 15 is a device structure comprising: a plurality of electrode structures; a plurality of capacitor structures, wherein individual ones of the plurality of capacitor structures are coupled with individual ones of the plurality of electrode structures, and wherein the individual ones of the plurality of capacitor structures comprise: a bottom electrode structure, comprising: a first electrode comprising a first lateral width; and a second electrode on the first electrode comprising a second lateral with greater than the first lateral width; a dielectric comprising a non-linear polar material; and a third electrode on the dielectric; and an encapsulation structure comprising: a first portion adjacent to a first sidewall of the first electrode and adjacent to a lower surface of the second electrode; and a second portion adjacent to a second sidewall of the second electrode, a third sidewall of the dielectric, and a fourth sidewall of the third electrode, wherein the first portion and the second portion are contiguous. Docket No.: KP12P064US-PCT [00395] Example 16 is a device structure according to any device described herein, in particular example 15, wherein the encapsulation structure further comprises a third portion that is contiguous between a first capacitor and a second capacitor in the plurality of capacitor structures. [00396] Example 17 is a device structure according to any device described herein, in particular example 15, wherein a top surface of the encapsulation structure is substantially planar or co-planar with an uppermost surface of the third electrode. [00397] Example 18 is a device structure according to any device described herein, in particular example 15, wherein the dielectric comprises one of: a first form ABB’O3, wherein A includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na, wherein B includes one of Mn, Fe, Ta, or Nb, and wherein ‘B'’ includes one of: Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, or Zn; a second form AA'BO3, wherein A includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na, wherein B includes one of Mn, Fe, Ta, or Nb, wherein A' includes one of Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, and wherein A' comprises a valency of site A, but different ferroelectric polarizability from A; a third form ABO3, wherein A includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na, and wherein B includes one of Mn, Fe, Ta, or Nb; bismuth ferrite (BFO), or BFO with a first doping material, wherein the first doping material is one of lanthanum, elements from lanthanide series of a periodic table, or elements of 3d, 4d, 5d, 6d, 4f, or 5f series of periodic table; lead zirconium titanate (PZT) or PZT with a second doping material, wherein the second doping material is one of La or Nb; a perovskite comprising one of: BaTiO3, KNbO3, PbTiO3, or NaTaO3; BaTiO3, KNbO3, or NaTaO3 doped with La or Lanthanides; or PbTiO3 substitutionally doped with Zr, La, or Nb; a relaxor ferroelectric material which includes one of: lead magnesium niobate (PMN), lead magnesium niobate- lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or barium titanium- barium strontium titanium (BT-BST); a BaTiO₃ (BTO) based relaxor which includes one of: BaTiO₃-Bi(Zn₁/₂Ti₁/₂)O₃ (BTO-BZT), BaTiO₃-BiScO₃ (BTO-BS): BiScO₃, Ba(₁-x)SrxTiO₃ (BST), BaTiO₃-Pb(Mg₁/₃Nb₂/₃)O₃ (BTO-PMN), BaTi(1-x)ZrxO₃ (BTZ), BaTiO₃- Pb(Zn₁/₃Nb₂/₃)O₃ (BTO-PZN), BaTiO₃-Pb(Sc₁/₂Nb₁/₂)O₃ (BTO-PSN), where 0 < x < 1; a PZT based relaxor which includes one of: PZT-Pb(Mg₁/₃Nb₂/₃)O₃ (PZT-PMN), PZT- Pb(Ni₁/₃Nb₂/₃)O₃ (PZT-PNN), PZT-Pb(Zn₁/₃Nb₂/₃)O₃ (PZT-PZN), PZT-Pb(Sc₁/₂Nb₁/₂)O₃ (PZT-PSN), PZT-Pb(Fe₁/₂Nb₁/₂)O₃ (PZT-PFN), PZT- PbxLa1-x(ZryTi1-y)O3 (PZT-PLZT), Docket No.: KP12P064US-PCT where 0 ≤ x ≤ 1 and where 0 ≤ y ≤ 1, or PZT-PbTi(1-x)Mn(x)O₃ (PZT-PTM), where 0 ≤ x ≤ 1; a SrBi₂Ta₂O₉ (SBT) based relaxor which includes one of: paraelectric SBT-SrBi₂[Nb(1- x)Ta(x)]₂O₉ (SBT-SBNT), where 0 ≤ x ≤ 1, or SBT doped with one of: Mn, Fe, Co, La, Ce or Nd, Ba or Ca; a first hexagonal ferroelectric which includes one of: YMnO3 or LuFeO3; a second hexagonal ferroelectric of a type RMnO3, where R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y); lithium niobate, lithium tantalate, lithium iron tantalum oxy fluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate; an improper ferroelectric material which includes one of: [PTO/STO]n or [LAO/STO]n, wherein ‘n’ is between 1 and 100; hafnium (Hf), Zirconium (Zr), Aluminum (Al), Silicon (Si), an oxide of hafnium (Hf), Zirconium (Zr), Aluminum (Al), or Silicon (Si), or an alloyed oxide of hafnium (Hf), Zirconium (Zr), Aluminum (Al), or Silicon (Si); hafnium oxide of a form Hf(1-x)ExOy, where E includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y, wherein ‘x’ and ‘y’ are first and second fractions, respectively; HfO2 doped with one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y; Al(1-x)Sc(x)N, Ga(1-x)Sc(x)N, Al(1-x)Y(x)Nor Al(1-x-y)Mg(x)Nb(y)N, wherein ‘x’ and ‘y’ are third and fourth fractions, respectively; LiNbO3, LiTaO3, LiTaO2F2, Sr(^)Ba(1-x)Nb₂O₆ where 0.32 ≤ x ≤ 0.8, or KSr2Nb5O15; a paraelectric material comprising SrTiO3, Ba(x)Sr(y)TiO3, where 0 < x < 1 and where 0 < y < 1 HfZrO2, Hf- Si-O, or La-substituted PbTiO3; or an antiferroelectric material comprising one of: HfSiO2 doped with >30% Si or >30% Zr; HfZrO2 doped with >30% Si or >30% Zr; ZrO2 or NaNbO3; NaNbO3, PbZrO3, or PbZrO3 doped with >5% K; a first solid solution including one of: PbTiO3, SrTiO3, PbHfO3, PbHfO3, Pb(Lu0.5Nb0.5)O3, Pb(Lu0.5Nb0.5)O3, Pb(Yb0.5Nb0.5)O3, AgNbO3 or NaNbO3; or a second solid solution including PbTiO3 and one of: SrTiO3, PbHfO3, PbHfO3, Pb(Lu0.5Nb0.5)O3, Pb(Lu0.5Nb0.5)O3, Pb(Yb0.5Nb0.5)O3, AgNbO3 or NaNbO3. [00398] Example 19 is a system comprising: a transistor comprising: a source; a drain; and a gate; a capacitor coupled with the transistor, the capacitor comprising: a bottom electrode structure, comprising: a first electrode comprising a first lateral thickness; and a second electrode on the first electrode, the second electrode comprising a second lateral thickness greater than the first lateral thickness; a dielectric comprising a non-linear polar material having a form ABB'O3, AA'B'O3, or ABO3, wherein A' is a first dopant for atomic site A, wherein B' is a second dopant for atomic site B, and wherein O is oxygen; and a third Docket No.: KP12P064US-PCT electrode on the dielectric; an encapsulation structure comprising: a first portion adjacent to a first sidewall of the first electrode and adjacent to a lower surface of the second electrode; and a second portion adjacent to a second sidewall of the second electrode, a third sidewall of the dielectric, and a fourth sidewall of the third electrode, wherein the first portion and the second portion are contiguous; and an electrode structure coupled between the drain and the capacitor. [00399] Example 20 is a system according to any system described herein, in particular example 19, wherein the electrode structure comprises: a conductive hydrogen barrier layer comprising one of: TiAlN with greater than 30 atomic percent AlN, TaN with greater than 30 atomic percent nitrogen, TiSiN with greater than 20 atomic percent SiN, TaC, TiC, WC, WN, carbonitrides of Ta, Ti, W, TiO, Ti2O, WO3, SnO2, ITO, IGZO, zinc oxide or METGLAS series of alloys; and a fill metal within the conductive hydrogen barrier layer, wherein the fill metal comprises one of tantalum, titanium, ruthenium, tungsten, molybdenum or copper, wherein the first electrode comprises one of: niobium, chromium, molybdenum, tantalum, tungsten, rhenium, titanium, nitrogen doped variants of niobium, chromium, molybdenum, tantalum, tungsten, rhenium, titanium, conductive doped AlN, or conductive doped SiN, wherein the second electrode comprises one of: a first non-Pb based metal oxide, such as but not limited to La(1-x)Sr(x)FeO3, La(1-x)Sr(x)CoO3, La(1-x)Ca(x)MnO3, La(1-x)Sr(x)MnO3, Ba(1- x)Sr(x)RuO3, La(1-x)Sr(x)MnO3, wherein 0 ≤ x ≤ 1, SrRuO3, Sr2RuO4, SrMoO3, SrCoO3, SrCrO3, SrFeO3, SrVO3, CaMoO3, SrNbO3, LaNiO3, YBa2Cu3O7, Bi2Sr2CaCuO8, CaRuO3, Ir, Ir2Oy, Ru, RuOy, Mo, MoOy, W, or WOy, wherein ‘y’ is an integer, wherein the third electrode comprises one of: a second non-Pb metal oxide, such as but not limited to, La(1- x)Sr(x)FeO3, La(1-x)Sr(x)CoO3, La(1-x)Ca(x)MnO3, La(1-x)Sr(x)MnO3, Ba(1-x)Sr(x)RuO3, La(1- x)Sr(x)MnO3, wherein 0 ≤ x ≤ 1, SrRuO3, Sr2RuO4, SrMoO3, SrCoO3, SrCrO3, SrFeO3, SrVO3, CaMoO3, SrNbO3, LaNiO3, YBa2Cu3O7, Bi2Sr2CaCuO8, CaRuO3, Ir, Ir2Oy, Ru, RuOy, Mo, MoOy, W, or WOy, wherein ‘y’ is an integer, and wherein the transistor is one of: a planar, non-planar or a nano-wire transistor. [00400] Example 1A is a method of fabricating a device, the method comprising: forming an electrode structure within an insulator layer; forming a capacitor structure on the electrode structure, wherein forming the capacitor structure comprises: depositing a multilayer stack comprising a plurality of electrode layers and a dielectric layer comprising a non-linear polar material; and patterning the multilayer stack to form a top electrode, a dielectric comprising the non-linear polar material, and a bottom electrode structure comprising an upper electrode and a lower electrode; forming a recess by laterally etching a Docket No.: KP12P064US-PCT first sidewall of the lower electrode; and depositing an encapsulation layer comprising a first portion on a second sidewall of the upper electrode and a second portion on a third sidewall of the lower electrode, wherein the second portion is in contact with a lowermost surface of the upper electrode. [00401] Example 2A is a method of fabricating a device according to any method described herein, in particular example 1A, wherein the encapsulation layer comprises one of: silicon nitride, carbon doped silicon nitride, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx or TaSiOx, wherein ‘x’ and ‘y’ are first and second integers, respectively, wherein the insulator layer comprises one of: silicon nitride, or carbon doped silicon nitride, and wherein the encapsulation layer comprises a different material than a material of the insulator layer. [00402] Example 3A is a method of fabricating a device according to any method described herein, in particular example 1A further comprising planarizing the capacitor structure and the first portion, wherein uppermost surfaces of the first portion and the top electrode are substantially co-planar. [00403] Example 4A is a method of fabricating a device according to any method described herein, in particular example 1A, wherein the encapsulation layer is deposited to a thickness that is at least equal to half vertical thickness of the lower electrode, and wherein the encapsulation layer fills the recess. [00404] Example 5A is a method of fabricating a device according to any method described herein, in particular example 1A, wherein the lower electrode has a vertical thickness that is greater than a first lateral thickness of the first portion, and wherein the encapsulation layer does not fill the recess. [00405] Example 6A is a method of fabricating a device according to any method described herein, in particular example 5A, wherein depositing the encapsulation layer forms the second portion comprising a variable lateral thickness, wherein the variable lateral thickness has a minimum thickness adjacent to a portion of the third sidewall, and wherein the minimum thickness is equal to the first lateral thickness. [00406] Example 7A is a method of fabricating a device according to any method described herein, in particular example 6A, wherein depositing the encapsulation layer further comprises depositing on a top surface of the capacitor structure, on the third sidewall of the dielectric, on a fourth sidewall of the top electrode and on the insulator layer. [00407] Example 8A is a method of fabricating a device according to any method described herein, in particular example 7A, wherein the method further comprises etching the encapsulation layer to form an encapsulation structure, wherein etching the encapsulation Docket No.: KP12P064US-PCT layer removes the encapsulation layer from the top surface of the capacitor structure and from a portion of an uppermost surface of the insulator layer, wherein the encapsulation structure comprises the first portion and the second portion, and wherein the first portion further extends on the third sidewall and on the fourth sidewall. [00408] Example 9A is a method of fabricating a device according to any method described herein, in particular example 8A, wherein etching reduces the first lateral thickness but not the minimum thickness. [00409] Example 10A is a method of fabricating a device according to any method described herein, in particular example 9A, wherein etching the encapsulation layer, changes the first lateral thickness to a second lateral thickness where the second lateral thickness varies from the top electrode to the lower electrode. [00410] Example 11A is a method of fabricating a device according to any method described herein, in particular example 1A, wherein forming the recess comprises laterally recessing the first sidewall by at least 2nm compared to the second sidewall. [00411] Example 12A is a method of fabricating a device according to any method described herein, in particular example 1A, wherein prior to forming the electrode structure within the insulator layer, the method further comprises forming a liner between the electrode structure and the insulator layer, and wherein the liner comprises a material of the encapsulation layer. [00412] Example 13A is a method of fabricating a device according to any method described herein, in particular example 12A, wherein the encapsulation layer comprises one of: material described above in example 3. [00413] Example 14A is a method of fabricating a device according to any method described herein, in particular example 1A, wherein depositing the multilayer stack comprises: depositing a material of the lower electrode, upper electrode, top electrode and the dielectric layer as described in examples 18 and 20. [00414] Example 15A is a method of fabricating a device according to any method described herein, in particular example 1A further comprising: depositing an etch stop layer on the capacitor structure; forming an opening in the etch stop layer; and forming a via electrode in the opening, wherein the via electrode is in contact with the top electrode, and wherein the etch stop layer comprises a material of the insulator layer. [00415] Example 16A is a method of fabricating a device, the method comprising: forming a capacitor by patterning a multilayer stack comprising a plurality of electrode layers and a dielectric layer comprising a non-linear polar material having a form ABB'O3, Docket No.: KP12P064US-PCT AA'B'O3, or ABO3, wherein patterning the multilayer stack forms a top electrode, a bottom electrode structure comprising an upper electrode and a lower electrode, and a dielectric comprising the non-linear polar material between the top electrode and the bottom electrode structure; laterally recessing a first sidewall of the lower electrode; and depositing an encapsulation layer adjacent to second sidewall of the capacitor and in contact with at least a second portion of a lowermost surface of the lower electrode. [00416] Example 17A is a method of fabricating a device according to any method described herein, particular example 16A, wherein the method further comprises forming an electrode structure above a substrate and depositing the multilayer stack on the electrode structure prior to forming the capacitor. [00417] Example 18A is a method of fabricating a device according to any method described herein, particular example 17A, wherein prior to forming the lower electrode and depositing the encapsulation layer, the method further comprises forming a spacer on sidewalls of the top electrode, the dielectric and the upper electrode, and wherein depositing the encapsulation layer further comprises depositing on an outer sidewall of the spacer. [00418] Example 19A is a method of forming a system, the method comprising: forming a transistor above a substrate, the transistor comprising a source, a gate and a drain; and forming a device structure coupled with the gate or the drain of the transistor, wherein forming the device structure comprises: forming an electrode structure; forming a capacitor structure on the electrode structure, wherein forming the capacitor structure comprises: depositing a multilayer stack comprising a plurality of electrode layers and a dielectric layer comprising a non-linear polar material; and patterning the multilayer stack to form a top electrode, a dielectric comprising the non-linear polar material, a bottom electrode structure comprising an upper electrode and a lower electrode; forming a recess by laterally etching a first sidewall of the lower electrode; and depositing an encapsulation layer comprising a first portion on a second sidewall of the upper electrode and a second portion on a third sidewall of the lower electrode, wherein the second portion is in contact with a lowermost surface of the upper electrode. [00419] Example 20A is a method of forming a system according to any method described herein, particular example 19A, wherein forming the transistor comprises forming a non-planar transistor or a nano-wire transistor, and wherein forming the multilayer stack comprises: depositing a material of the lower electrode, upper electrode, top electrode and the dielectric layer as described in examples 18 and 20. Docket No.: KP12P064US-PCT [00420] Example 1C is a device structure comprising: an electrode structure adjacent to an insulator, the electrode structure comprising a first lateral thickness; a capacitor in contact with the electrode structure, the capacitor comprising: a first electrode comprising a second lateral thickness, the second lateral thickness greater than the first lateral thickness; a dielectric comprising a non-linear polar material; and a second electrode on the dielectric; and an encapsulation structure comprising: a first portion adjacent to a first sidewall of the first electrode, a second sidewall of the dielectric, and a third sidewall of the second electrode; and a second portion adjacent to a lower surface of the first electrode, a portion of a fourth sidewall of the electrode structure, and an upper surface of the insulator, and wherein the first portion and the second portion are contiguous. [00421] Example 2C is a device structure according to any device described herein, in particular example 1C, wherein the electrode structure comprises a material described above in example 3. [00422] Example 3C is a device structure according to any device described herein, in particular example 1C, wherein the first electrode has a first vertical thickness, the first vertical thickness orthogonal to the first lateral thickness, wherein the second portion has a second vertical thickness, wherein the insulator has a third vertical thickness, and wherein the first vertical thickness is equal to a combined sum of the second vertical thickness and the third vertical thickness. [00423] Example 4C is a device structure according to any device described herein, in particular example 3C, wherein the second portion has a third lateral thickness, and wherein the third lateral thickness is equal to at least a quarter of the second vertical thickness. [00424] Example 5C is a device structure according to any device described herein, in particular example 4C, wherein the third lateral thickness varies with distance between the upper surface of the insulator and the lower surface of the first electrode. [00425] Example 6C is a device structure according to any device described herein, in particular example 5C, wherein the second portion further comprises a cavity. [00426] Example 7C is a device structure according to any device described herein, in particular example 1C, further comprising a liner between the insulator and the electrode structure, wherein the liner is further between the second portion and the electrode structure. [00427] Example 8C is a device structure according to any device described herein, in particular example 7C, wherein the encapsulation structure comprises one of: silicon nitride, carbon doped silicon nitride, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx or TaSiOx, wherein ‘x’ and ‘y’ are first and second integers, respectively, wherein the liner comprises Docket No.: KP12P064US-PCT one of: silicon nitride, carbon doped silicon nitride, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx or TaSiOx, wherein ‘x’ and ‘y’ are third and fourth integers, respectively, wherein the insulator comprises one of: silicon nitride, or carbon doped silicon nitride, and wherein the insulator and the encapsulation structure comprise a different material. [00428] Example 9C is a device structure according to any device described herein, in particular example 1C, wherein the encapsulation structure further comprising a third portion extending laterally on the insulator beyond an outer sidewall of the first portion. [00429] Example 10C is a device structure according to any device described herein, in particular example 9C, wherein the encapsulation structure further comprising a fourth portion extending on the first portion and on an upper surface of the second electrode. [00430] Example 11C is a device structure according to any device described herein, in particular example 4C, wherein the encapsulation structure comprises a fourth lateral thickness that increases with distance from an uppermost surface of the insulator to a top surface of the second electrode. [00431] Example 12C is a device structure according to any device described herein, in particular example 1C, wherein the dielectric comprises a material described in example 18. [00432] Example 13C is a device structure according to any device described herein, in particular example 1C further comprising a spacer between the encapsulation structure and the second sidewall, wherein the spacer is above the second portion. [00433] Example 14C is a device structure according to any device described herein, in particular example 13C, wherein the insulator comprises a first material that is different from a second material of the encapsulation structure or a third material of the spacer, wherein the encapsulation structure comprises one of: silicon nitride, carbon doped silicon nitride, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx or TaSiOx, wherein ‘x’ and ‘y’ are first and second integers, respectively, wherein the spacer comprises one of: silicon nitride, carbon doped silicon nitride, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx or TaSiOx, wherein ‘x’ and ‘y’ are third and fourth integers, respectively, and wherein the insulator comprises one of: silicon nitride, or carbon doped silicon nitride. [00434] Example 15C is a device structure according to any device described herein, in particular example 1C, wherein the first lateral thickness is at least 2 nm less than the second lateral thickness. [00435] Example 16C is a device structure comprising: an insulator layer; a plurality of electrode structures on a same level within the insulator layer, wherein individual ones of the plurality of electrode structures comprise a first lateral thickness and a first sidewall; a Docket No.: KP12P064US-PCT plurality of capacitor structures, wherein individual ones of the plurality of capacitor structures are coupled with the individual ones of the plurality of electrode structures, and wherein the individual ones of the plurality of capacitor structures comprise: a first electrode comprising a second lateral thickness, the second lateral thickness greater than the first lateral thickness; a dielectric comprising a non-linear polar material having a form ABB'O3, AA'B'O3, or ABO3, wherein A' is a first dopant for atomic site A, wherein B' is a second dopant for atomic site B, and wherein O is oxygen; and a second electrode on the dielectric; and a plurality of encapsulation structures, where individual ones of the plurality of encapsulation structures comprise: a first portion adjacent to a second sidewall of the first electrode, a third sidewall of the dielectric, and a fourth sidewall of the second electrode; and a second portion adjacent to a lower surface of the first electrode, a portion of the first sidewall, and an upper surface of the insulator layer, wherein the first portion and the second portion are contiguous. [00436] Example 17C is a device structure according to any device described herein, in particular example 16C, wherein the individual ones of the plurality of encapsulation structures further comprise a third portion that laterally extends on the insulator layer, and wherein the third portion is contiguous between the individual ones of the plurality of capacitor structures. [00437] Example 18C is a device structure according to any device described herein, in particular example 16C, wherein a top surface of the individual ones of the plurality of encapsulation structures are substantially planar or co-planar with an upper surface of the second electrode. [00438] Example 19C is a system, comprising: a transistor comprising: a source; a drain; and a gate; an electrode structure coupled with the drain, the electrode structure adjacent to an insulator on a same level as the electrode structure; a capacitor on the electrode structure, the capacitor comprising: a first electrode comprising a first sidewall, the first sidewall extending beyond a second sidewall of the electrode structure; a dielectric comprising a non-linear polar material having a form ABB'O3, AA'B'O3, or ABO3, wherein A' is a first dopant for atomic site A, wherein B' is a second dopant for atomic site B, and wherein O is oxygen; and a second electrode on the dielectric; and an encapsulation structure comprising: a first portion adjacent to the first sidewall and adjacent to a third sidewall of the dielectric; and a second portion that extends along a portion of the second sidewall from under a lower surface of the first electrode to an upper surface of the insulator, wherein the first portion and the second portion are contiguous. Docket No.: KP12P064US-PCT [00439] Example 20C is a system according to any system described herein, in particular example 19C, wherein the electrode structure comprises a material described in at least example 20, and wherein the transistor is one of: a planar, non-planar or a nano-wire transistor. [00440] Example 1D is a method of fabricating a device, the method comprising: forming an electrode structure adjacent to an insulator layer; forming a capacitor on the electrode structure by patterning a multilayer stack comprising a plurality of electrode layers and a dielectric layer comprising a non-linear polar material , wherein patterning the multilayer stack forms a top electrode, a bottom electrode and a dielectric comprising the non-linear polar material between the top electrode and the bottom electrode; forming a recess under the bottom electrode adjacent the electrode structure; and depositing an encapsulation layer adjacent to a first sidewall of the capacitor and in contact with at least a portion of a lowermost surface of the bottom electrode. [00441] Example 2D is a method of fabricating a device structure according to any method described herein, in particular example 1D, wherein forming the recess comprises etching and removing a sacrificial layer formed above the insulator layer, the insulator layer formed prior to forming the electrode structure. [00442] Example 3D is a method of fabricating a device according to any method described herein, in particular example 1D, wherein the recess exposes a first portion of a second sidewall of the electrode structure, and wherein depositing the encapsulation layer further comprises depositing on the first portion of the second sidewall. [00443] Example 4D is a method of fabricating a device according to any method described herein, in particular example 3D, wherein the encapsulation layer fills the recess, and wherein the encapsulation layer is further deposited on the insulator layer and on the top electrode. [00444] Example 5D is a method of fabricating a device according to any method described herein, in particular example 4D, wherein the method further comprises etching the encapsulation layer from above the top electrode, and from above the insulator layer, and wherein etching the encapsulation layer forms an encapsulation structure having a second portion on the first sidewall and a third portion in contact the lowermost surface of the bottom electrode and in contact with the first portion of the second sidewall. [00445] Example 6D is a method of fabricating a device according to any method described herein, in particular example 1D, wherein the encapsulation layer partially fills the recess. Docket No.: KP12P064US-PCT [00446] Example 7D is a method of fabricating a device according to any method described herein, in particular example 3D, wherein a second portion of the encapsulation layer deposited on the first portion of the second sidewall comprises a first lateral thickness that varies with height of the second sidewall. [00447] Example 8D is a method of fabricating a device according to any method described herein, in particular example 3D, wherein the encapsulation layer comprises one of: silicon nitride, carbon doped silicon nitride, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx or TaSiOx, wherein ‘x’ and ‘y’ are first and second integers, respectively, wherein the insulator layer comprises one of: silicon nitride, or carbon doped silicon nitride, and wherein the insulator layer and the encapsulation layer comprise a different material. [00448] Example 9D is a method of fabricating a device according to any method described herein, in particular example 1D, wherein forming the multilayer stack comprises depositing a material of the bottom electrode, the dielectric layer and a material of the top electrode as described in at least example 14. [00449] Example 10D is a method of fabricating a device, the method comprising: forming an electrode structure adjacent to a dual insulator stack; forming a capacitor structure on the electrode structure, wherein forming the capacitor structure comprises: depositing a multilayer stack comprising a plurality of electrode layers and a dielectric layer comprising a non-linear polar material; and patterning the multilayer stack to form a top electrode, a bottom electrode and a dielectric comprising the non-linear polar material between the top electrode and the bottom electrode; forming a recess by laterally etching an upper insulator layer in the dual insulator stack, wherein the recess exposes a first portion of a lower surface of the bottom electrode; and depositing an encapsulation layer adjacent to a first sidewall of the capacitor structure and within the recess, wherein the encapsulation layer comprises: a third portion adjacent to the first sidewall of the capacitor structure; and a fourth portion in contact with the lower surface of the bottom electrode. [00450] Example 11D is a method of fabricating a device according to any method described herein, in particular example 10D, wherein forming the recess further comprises: exposing a fifth portion of a second sidewall of the electrode structure; and exposing a lower insulator layer, wherein the lower insulator layer is adjacent to the electrode structure, and wherein an upper surface of the electrode structure is above an upper surface of the lower insulator layer. [00451] Example 12D is a method of fabricating a device according to any method described herein, in particular example 11D, wherein the recess has a vertical thickness that is Docket No.: KP12P064US-PCT greater than a lateral thickness of the encapsulation layer, wherein the fourth portion is further in contact with the fifth portion of the second sidewall, and wherein the fifth portion and the fourth portion are contiguous. [00452] Example 13D is a method of fabricating a device according to any method described herein, in particular example 11D, wherein the encapsulation layer is deposited to a thickness that is at least equal to half vertical thickness of the recess, and wherein the encapsulation layer fills the recess. [00453] Example 14D is a method of fabricating a device according to any method described herein, in particular example 12D, wherein depositing the encapsulation layer further comprises depositing on a top surface of the capacitor structure and on the lower insulator layer, and wherein the method further comprises etching the encapsulation layer to form an encapsulation structure within the recess, and wherein the encapsulation structure comprises: the third portion; and an eighth portion within the recess, wherein the eighth portion comprises a lateral recess, and wherein etching removes the encapsulation layer from the top surface of the capacitor structure and forms the third portion that is curved. [00454] Example 15D is a method of fabricating a device according to any method described herein, in particular example 13D, wherein the recess is at least 1 nm wide as measured from the second sidewall and comprises a height of at least 2 nm from the upper surface of the lower insulator layer. [00455] Example 17D is a method of fabricating a device according to any method described herein, in particular example 11D, wherein the encapsulation layer comprises one of: silicon nitride, carbon doped silicon nitride, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx or TaSiOx, wherein ‘x’ and ‘y’ are first and second integers, respectively, wherein the lower insulator layer comprises one of: silicon nitride, or carbon doped silicon nitride, and wherein the lower insulator layer and the encapsulation layer comprise a different material. [00456] Example 18D is a method of fabricating a device according to any method described herein, in particular example 10D, wherein depositing the multilayer stack further comprises depositing a material of the bottom electrode, the dielectric layer and a material of the top electrode as described in at least example 9D. [00457] Example 19D is a method of fabricating a system, the method comprising: forming a transistor above a substrate, the transistor comprising a source, a gate and a drain; and forming a device structure coupled with the gate or the drain of the transistor, wherein forming the device structure comprises: forming an electrode structure adjacent to a dual insulator layer; forming a capacitor on the electrode structure by patterning a multilayer Docket No.: KP12P064US-PCT stack, wherein patterning the multilayer stack forms a top electrode, a bottom electrode and a dielectric comprising a non-linear polar material between the top electrode and the bottom electrode; forming a recess under the bottom electrode and adjacent the electrode structure by removing an upper insulator layer in the dual insulator layer; and depositing an encapsulation layer adjacent to a first sidewall of the capacitor and on at least a portion of a lowermost surface of the bottom electrode. [00458] Example 20D is a method of fabricating a system according to any method described herein, in particular example 19D, wherein forming the transistor comprises forming a non-planar transistor or a nano-wire transistor, and wherein depositing the encapsulation layer further comprises: depositing the encapsulation layer on a top surface of the capacitor, on a lower insulator layer that is exposed by removal of the upper insulator layer, and on a portion of a second sidewall of the electrode structure. [00459] Example 1E is a device structure comprising: a first insulator layer and a second insulator layer on the first insulator layer; an electrode structure embedded within the first insulator layer and the second insulator layer; a capacitor coupled with the electrode structure, the capacitor comprising: a first electrode; a dielectric comprising a non-linear polar material; and a second electrode on the dielectric; an encapsulation layer on a sidewall of the capacitor and in contact with at least a portion of a lowermost surface of the first electrode, the encapsulation layer in contact with the second insulator layer; and a via electrode adjacent to the capacitor, the via electrode laterally surrounded by the first insulator layer but not the second insulator layer, wherein the via electrode extends beyond an uppermost surface of the electrode structure. [00460] Example 2E is a device structure according to any device described herein, in particular example 1E further comprising a third electrode coupled between the electrode structure and the first electrode, wherein the first electrode comprises a first lateral thickness, and wherein the third electrode comprises a second lateral thickness, the first lateral thickness greater than the second lateral thickness. [00461] Example 3E is a device structure according to any device described herein, in particular example 2E, wherein the sidewall is a first sidewall, and wherein the encapsulation layer is adjacent to a second sidewall of the third electrode. [00462] Example 4E is a device structure according to any device described herein, in particular example 1E, wherein the first insulator layer comprises silicon, carbon and nitrogen, and wherein the second insulator layer comprises silicon and nitrogen, and wherein the encapsulation layer comprises one of: AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx or Docket No.: KP12P064US-PCT TaSiOx, wherein ‘x’ and ‘y’ are first and second integers, respectively, and wherein the second insulator layer and the encapsulation layer comprise different materials. [00463] Example 5E is a device structure according to any device described herein, in particular example 1E, wherein the first insulator layer comprises a first vertical thickness of at least 5 nm, and wherein the second insulator layer comprises a second vertical thickness of at least 5 nm. [00464] Example 6E is a device structure according to any device described herein, in particular example 1E, wherein the capacitor is in a first region and the via electrode is in a second region, wherein the device structure further comprises: a first dielectric in the first region, the first dielectric on the second insulator layer and adjacent to the encapsulation layer; and a second dielectric in the second region, the second dielectric on the first insulator layer and adjacent to the via electrode. [00465] Example 7E is a device structure according to any device described herein, in particular example 6E, wherein the first dielectric and the second dielectric comprise a same material. [00466] Example 8E is a device structure according to any device described herein, in particular example 1E, wherein the encapsulation layer further extends to an edge of the second insulator layer. [00467] Example 9E is a device structure according to any device described herein, in particular example 1E further comprising: a first conductive interconnect directly below and in contact with the electrode structure; and a second conductive interconnect directly below and in contact with the via electrode, wherein the second conductive interconnect and the second conductive interconnect are on a same level, wherein a lowermost surface of the via electrode is co-planar with a lowermost surface of the electrode structure. [00468] Example 10E is a device structure according to any device described herein, in particular example 9E, wherein the first insulator layer extends on a portion of the first conductive interconnect and on a portion of the second conductive interconnect. [00469] Example 11E is a device structure according to any device described herein, in particular example 1E, wherein the second insulator layer comprises a thickness of at least 3 nm. [00470] Example 12E is a device structure according to any device described herein, in particular example 1E, wherein the electrode structure comprises materials described in at least example 3. Docket No.: KP12P064US-PCT [00471] Example 13E is a device structure according to any device described herein, in particular example 1E, wherein the first electrode comprises one of: niobium, chromium, molybdenum, tantalum, tungsten, rhenium, titanium, nitrogen doped variants of niobium, chromium, molybdenum, tantalum, tungsten, rhenium, titanium, nitrides of tantalum, tungsten, titanium, conductive doped AlN, or conductive doped SiN. [00472] Example 14E is a device structure according to any device described herein, in particular example 1E, wherein the dielectric comprises a material described in at least example 18. [00473] Example 15E is a device structure comprising: a first insulator layer and a second insulator layer on the first insulator layer; an electrode structure embedded within the first insulator layer and the second insulator layer, wherein a first upper surface of the electrode structure extends above a second upper surface of the second insulator layer; a capacitor coupled with the electrode structure, the capacitor comprising: a first electrode; a dielectric layer comprising a non-linear polar material having a form ABB'O3, AA'B'O3, or ABO3, wherein A' is a first dopant for atomic site A, wherein B' is a second dopant for atomic site B, wherein O is oxygen; and a second electrode on the dielectric layer; an encapsulation layer on a sidewall of the capacitor and on at least a portion of a lowermost surface of the first electrode, the encapsulation layer in contact with the second insulator layer; and a via electrode adjacent to the capacitor, the via electrode laterally surrounded by the first insulator layer but not the second insulator layer, wherein the via electrode extends beyond an uppermost surface of the electrode structure. [00474] Example 16E is a device structure according to any device described herein, in particular example 15E, wherein the first electrode comprises a first lateral thickness, and wherein the electrode structure comprises a second lateral thickness, the first lateral thickness greater than the second lateral thickness. [00475] Example 17E is a device structure according to any device described herein, in particular example 15E, wherein the encapsulation layer comprises a third lateral thickness on the sidewall of the capacitor, and wherein the encapsulation layer comprises a fourth lateral thickness adjacent to a portion of the electrode structure, wherein the third lateral thickness is less than the fourth lateral thickness. [00476] Example 18E is a system, comprising: a first transistor and a second transistor; a device structure coupled with a first drain of the first transistor, the device structure comprising: a first insulator layer and a second insulator layer on the first insulator layer; an electrode structure embedded within the first insulator layer and the second insulator layer; a Docket No.: KP12P064US-PCT capacitor coupled with the electrode structure, the capacitor comprising: a first electrode; a dielectric layer comprising a non-linear polar material; and a second electrode on the dielectric layer; and an encapsulation layer on a sidewall of the capacitor and in contact with at least a portion of a lowermost surface of the first electrode, the encapsulation layer in contact with the second insulator layer; and a via electrode coupled with a second drain of the second transistor, wherein the via electrode is adjacent to the capacitor, wherein the via electrode is laterally surrounded by the first insulator layer but not the second insulator layer, and wherein the via electrode extends beyond an uppermost surface of the electrode structure. [00477] Example 19E is a system according to any system described herein, in particular example 18E, wherein an uppermost surface of the encapsulation layer is co-planar with an uppermost surface of the second electrode. [00478] Example 20E is a system according to any system described herein, in particular example 18E, wherein the encapsulation layer laterally extends laterally under the first electrode by a distance of at least 2.5nm measured relative the sidewall. [00479] Example 1F is a method of fabricating a device, the method comprising: forming an electrode structure within an opening in a stack of insulator layers; forming a capacitor on the electrode structure, wherein forming the capacitor comprises: depositing a multilayer stack comprising a plurality of electrode layers and a dielectric layer comprising a nonlinear polar material; patterning the multilayer stack to form a top electrode, a dielectric comprising the nonlinear polar material, and a bottom electrode structure comprising an upper electrode on a lower electrode; and forming a recess by laterally etching a first sidewall of the lower electrode; depositing an encapsulation layer on a second sidewall of the capacitor and on a portion of a lowermost surface of the upper electrode; patterning and removing an upper insulator layer in the stack of insulator layers in a region adjacent to the capacitor; and forming a via electrode in the region, wherein the via electrode is laterally surrounded by a lower insulator layer in the stack of insulator layers. [00480] Example 2F is a method of fabricating a device according to any method described herein, in particular example 1F, wherein the upper insulator layer comprises silicon, carbon and nitrogen, wherein the lower insulator layer comprises silicon and nitrogen, wherein the encapsulation layer comprises one of: carbon-doped silicon nitride, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx or TaSiOx, and wherein the encapsulation layer comprises a different material from materials of the upper insulator layer and the lower insulator layer. Docket No.: KP12P064US-PCT [00481] Example 3F is a method of fabricating a device according to any method described herein, in particular example 1F, wherein patterning and removing the upper insulator layer further comprises: depositing a dielectric on the capacitor and on the upper insulator layer; forming a mask on the dielectric; and etching the dielectric and the upper insulator layer from the region, wherein etching the upper insulator layer exposes the lower insulator layer in the region. [00482] Example 4F is a method of fabricating a device according to any method described herein, in particular example 3F, wherein the dielectric is a first dielectric, and wherein forming the via electrode in the region comprises: depositing a second dielectric on the lower insulator layer in the region; planarizing the second dielectric; etching a via opening in the second dielectric and in the lower insulator layer to expose a conductive interconnect; and depositing at least one conductive material in the opening on the conductive interconnect. [00483] Example 5F is a method of fabricating a device according to any method described herein, in particular example 1F, wherein the capacitor is formed prior to patterning the upper insulator layer. [00484] Example 6F is a method of fabricating a device according to any method described herein, in particular example 1F, wherein the capacitor is formed after patterning the upper insulator layer, and wherein depositing the multilayer stack further comprises depositing on a third sidewall of the upper insulator layer at an edge of the region. [00485] Example 7F is a method of fabricating a device according to any method described herein, in particular example 6F, wherein etching the multilayer stack further comprises forming a spacer comprising one or more layers of the multilayer stack on the third sidewall. [00486] Example 8F is a method of fabricating a device according to any method described herein, in particular example 3F, wherein the encapsulation layer is further deposited on the upper insulator layer and on the top electrode prior to depositing the dielectric. [00487] Example 9F is a method of fabricating a device according to any method described herein, in particular example 8F, wherein prior to forming the mask, the method further comprises: planarizing the dielectric; and planarizing and removing the encapsulation layer deposited on the top electrode, wherein the encapsulation layer formed on the second sidewall of the capacitor has a substantially flat uppermost surface. Docket No.: KP12P064US-PCT [00488] Example 10F is a method of fabricating a device according to any method described herein, in particular example 8F, wherein after etching the dielectric, the method further comprises etching the encapsulation layer from the region prior to etching the upper insulator layer. [00489] Example 11F is a method of fabricating a device according to any method described herein, in particular example 1F, wherein etching the multilayer stack further comprises recessing the upper insulator layer, and wherein depositing the encapsulation layer comprises following a contour of the recess. [00490] Example 12F is a method of fabricating a device, the method comprising: forming a barrier structure with a step height, the step height formed by removing at least one layer within a stack of insulator layers in the barrier structure; forming an electrode structure within the barrier structure, wherein the electrode structure is laterally surrounded by the stack of insulator layers; forming a capacitor coupled with the electrode structure, the capacitor comprising a dielectric between a bottom electrode structure and a top electrode; depositing an encapsulation layer on the capacitor, wherein the encapsulation layer is deposited on a sidewall and on a portion of a lowermost surface of the capacitor; and forming a via structure in a region adjacent to the capacitor, the via structure laterally surrounded by one less layer in the stack of insulator layers than the electrode structure. [00491] Example 13F is a method of fabricating a device according to any method described herein, in particular example 12F, wherein patterning and removing an upper insulator layer within the stack of insulator layers further comprises: forming a mask over the electrode structure; and etching the upper insulator layer from the region and exposing a lower insulator layer within the stack of insulator layers. [00492] Example 14F is a method of fabricating a device according to any method described herein, in particular example 13F, wherein forming the via structure in the region comprises: blanket depositing a dielectric on the barrier structure, wherein the dielectric is further deposited on the capacitor and on portions of the encapsulation layer; planarizing the dielectric; etching an opening in the dielectric and in the lower insulator layer in the region, the opening exposing a conductive interconnect; and depositing at least one conductive material in the opening on the conductive interconnect. [00493] Example 15F is a method of fabricating a device according to any method described herein, in particular example 14F, wherein planarizing the dielectric further comprises planarizing and removing the encapsulation layer from a top surface of the Docket No.: KP12P064US-PCT capacitor, and wherein uppermost surfaces of the top surface of the capacitor and the encapsulation layer are co-planar. [00494] Example 16F is a method of fabricating a device according to any method described herein, in particular example 12F, wherein forming the capacitor further comprises laterally recessing a lowermost conductive electrode to form a recess, and wherein depositing the encapsulation layer further comprises filling the recess. [00495] Example 17F is a method of fabricating a device according to any method described herein, in particular example 12F, wherein the bottom electrode structure further comprises a lower electrode and an upper electrode on the lower electrode, and wherein forming the capacitor further comprises depositing materials described in at least example 14A; etching the material of the top electrode to form the top electrode; etching the dielectric layer to form the dielectric; and etching the material of the upper electrode and the material of the lower electrode to form the bottom electrode structure. [00496] Example 18 is a method of fabricating a system, the method comprising: forming a plurality of transistors above a substrate, wherein individual ones of the plurality of transistors comprise a source, a gate and a drain; forming a device structure coupled with the gate or the drain of a first transistor in the plurality of transistors, wherein forming the device structure comprises: forming an electrode structure within an opening in a stack of insulator layers; forming a capacitor on the electrode structure, wherein forming the capacitor comprises: depositing a multilayer stack comprising a plurality of electrode layers and a dielectric layer comprising a nonlinear polar material; patterning the multilayer stack to form a top electrode, a dielectric comprising the nonlinear polar material, a bottom electrode structure comprising an upper electrode and a lower electrode; and forming a recess by laterally etching a first sidewall of the lower electrode; and depositing an encapsulation layer on a second sidewall of the capacitor and on a portion of a lowermost surface of the upper electrode in the recess; patterning and removing an upper insulator layer in the stack of insulator layers in a region adjacent to the capacitor; and forming a via electrode in the region, wherein the via electrode is laterally surrounded by a lower insulator layer in the stack of insulator layers, and wherein the via electrode is above a second transistor in the plurality of transistors. [00497] Example 19F is a method of fabricating a system according to any system described herein, in particular example 18F, further comprising forming a conductive interconnect between the electrode structure and the drain or the source of the first transistor, wherein the via electrode is coupled with the drain or the source of the second transistor. Docket No.: KP12P064US-PCT [00498] Example 20F is a method of fabricating a system according to any system described herein, in particular example 18F, wherein forming the plurality of transistors comprises forming non-planar transistors or nano-wire transistors, and wherein forming the multilayer stack comprises a method as described in at least example 17F. [00499] Example 1G is a method of fabricating a device, the method comprising: forming an electrode structure within an opening in a stack of insulator layers; forming a capacitor on the electrode structure, wherein forming the capacitor comprises: depositing a multilayer stack comprising a plurality of electrode layers and a dielectric layer comprising a nonlinear polar material; and patterning the multilayer stack to form a top electrode, a dielectric comprising the nonlinear polar material, and a bottom electrode; forming a recess by laterally etching a first insulator layer in the stack of insulator layers; depositing an encapsulation layer on a sidewall of the capacitor and on a portion of a lowermost surface of the bottom electrode exposed by the recess; patterning and removing a second insulator layer in the stack of insulator layers in a region adjacent to the capacitor; and forming a via electrode in the region, wherein the via electrode is laterally surrounded by a third insulator layer, in the stack of insulator layers, wherein the third insulator layer is below the second insulator layer. [00500] Example 2G is a method of fabricating a device according to any method described herein, in particular example is a method of fabricating a device according to any method described herein, in particular example 1G, wherein the third insulator layer comprises silicon, carbon and nitrogen, and wherein the second insulator layer comprises silicon and nitrogen, and wherein the encapsulation layer comprises one of: carbon-doped silicon nitride, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx or TaSiOx, and wherein the encapsulation layer comprises a different material from materials of the second insulator layer and the third insulator layer. [00501] Example 3G is a method of fabricating a device according to any method described herein, in particular example 1G, wherein patterning and removing the second insulator layer further comprises: depositing a dielectric on the capacitor and on the second insulator layer; and etching the dielectric and the second insulator layer from the region, wherein etching the second insulator layer exposes the third insulator layer in the region. [00502] Example 4G is a method of fabricating a device according to any method described herein, in particular example 3G, wherein the dielectric is a first dielectric, wherein forming the via electrode in the region comprises: depositing a second dielectric on the third insulator layer in the region; etching a via opening in the second dielectric and in the third Docket No.: KP12P064US-PCT insulator layer to expose a conductive interconnect; and depositing at least one conductive material in the opening on the conductive interconnect. [00503] Example 5G is a method of fabricating a device according to any method described herein, in particular example 1G, wherein the capacitor is formed prior to patterning the first insulator layer. [00504] Example 6G is a method of fabricating a device according to any method described herein, in particular example 1G, wherein the sidewall is a first sidewall, and wherein forming the recess further comprises: exposing a third portion of a second sidewall of the electrode structure; and exposing the second insulator layer, wherein the second insulator layer is adjacent to the electrode structure, and wherein a first upper surface of the electrode structure is above a second upper surface of the second insulator layer. [00505] Example 7G is a method of fabricating a device according to any method described herein, in particular example 1G, wherein the capacitor is formed after patterning the first insulator layer and the second insulator layer, wherein depositing the multilayer stack further comprises depositing on a third sidewall of the first insulator layer, and on a fourth sidewall of the second insulator layer at an edge of the region. [00506] Example 8G is a method of fabricating a device according to any method described herein, in particular example 7G, wherein etching the multilayer stack further comprises forming a spacer comprising one or more layers of the multilayer stack on the third sidewall and on the fourth sidewall. [00507] Example 9G is a method of fabricating a device according to any method described herein, in particular example 3G, wherein the encapsulation layer is further deposited on the first insulator layer and on the top electrode prior to depositing the dielectric. [00508] Example 10G is a method of fabricating a device according to any method described herein, in particular example 9G, wherein the method further comprises: planarizing the dielectric; and planarizing and removing the encapsulation layer deposited on the top electrode, wherein the encapsulation layer formed on the sidewall of the capacitor has a substantially flat uppermost surface. [00509] Example 11G is a method of fabricating a device according to any method described herein, in particular example 8G, further comprises etching the encapsulation layer from the region prior to etching the second insulator layer. [00510] Example 12G is a method of fabricating a device, the method comprising: forming an electrode structure within a barrier structure, the barrier structure comprising a stack of insulator layers and a step height, the step height formed by removing at least one Docket No.: KP12P064US-PCT layer within the stack of insulator layers; forming a capacitor coupled with the electrode structure, the capacitor comprising a dielectric comprising a nonlinear polar material between a bottom electrode and a top electrode; forming a recess under the bottom electrode adjacent the electrode structure; depositing an encapsulation layer on the capacitor, wherein the encapsulation layer is deposited on a sidewall and on a portion of a lowermost surface of the capacitor; and forming a via structure in a region adjacent to the capacitor, the via structure laterally surrounded by one less layer in the stack of insulator layers than the electrode structure. [00511] Example 13G is a method of fabricating a device according to any method described herein, in particular example 12G, wherein forming the recess comprises etching and removing a sacrificial layer within the stack of insulator layers, wherein removing the sacrificial layer exposes an upper insulator layer. [00512] Example 14G is a method of fabricating a device according to any method described herein, in particular example 12G, wherein the encapsulation layer partially fills the recess. [00513] Example 15G is a method of fabricating a device according to any method described herein, in particular example 13G, wherein patterning and removing the at least one layer within the stack of insulator layers further comprises: depositing a first dielectric on the upper insulator layer; forming a mask on the first dielectric and over the electrode structure; and etching the upper insulator layer from the region, wherein etching the upper insulator layer exposes a lower insulator layer within the stack of insulator layers in the region. [00514] Example 16G is a method of fabricating a device according to any method described herein, in particular example 15G, wherein forming the via structure in the region comprises: blanket depositing a second dielectric on the lower insulator layer, wherein the second dielectric is further deposited above the capacitor; planarizing the second dielectric; etching an opening in the second dielectric and in the lower insulator layer in the region, the opening exposing a conductive interconnect; and depositing at least one conductive material in the opening on the conductive interconnect. [00515] Example 17G is a method of fabricating a device according to any method described herein, in particular example 16G, wherein depositing the second dielectric comprises depositing above the encapsulation layer and wherein planarizing the second dielectric further comprises planarizing and removing the encapsulation layer from a top surface of the capacitor, and wherein planarizing forms top surfaces of the capacitor and the encapsulation layer that are co-planar. Docket No.: KP12P064US-PCT [00516] Example 18G is a method of fabricating a device according to any method described herein, in particular example 12G, wherein forming the capacitor further comprises depositing materials described in at least example 9D. [00517] Example 19G is a method of forming a system, the method comprising: forming a plurality of transistors above a substrate, wherein individual ones of the plurality of transistors comprise a source, a gate and a drain; forming a device structure coupled with the gate or the drain of a first transistor in the plurality of transistors, wherein forming the device structure comprises: forming an electrode structure within a barrier structure, the barrier structure comprising a step height, the step height formed by removing at least one layer within a stack of insulator layers in the barrier structure; forming a capacitor on the electrode structure by patterning a multilayer stack comprising a plurality of electrode layers and a nonlinear polar material having a form ABB'O3, AA'B'O3, or ABO3, wherein patterning the multilayer stack forms a top electrode, a bottom electrode and a dielectric layer between the top electrode and the bottom electrode; forming a recess under the bottom electrode adjacent the electrode structure; and depositing an encapsulation layer adjacent to sidewall of the capacitor and in contact with at least a portion of a lowermost surface of the bottom electrode; and forming a via structure in a region adjacent to the capacitor, the via structure laterally surrounded by one less layer in the stack of insulator layers than the electrode structure. [00518] Example 20G is a method of fabricating a system according to any method described herein, in particular example 19G, wherein forming the recess comprises removing a sacrificial layer within the stack of insulator layers, wherein the sacrificial layer is an uppermost layer within the stack of insulator layers, wherein removing the sacrificial layer exposes a portion of a sidewall of the electrode structure, and wherein depositing the encapsulation layer further comprises depositing on the portion of the sidewall. [00519] Example 21G is a method of fabricating a system according to any method described herein, in particular example 19G, further comprising forming a conductive interconnect between the electrode structure and the drain or the source, wherein forming the plurality of transistors comprising forming non-planar transistors or nano-wire transistors, and wherein forming the multilayer stack by depositing layers described in at least example 18G.

Claims

Docket No.: KP12P064US-PCT CLAIMS What is claimed is: 1. A device structure comprising: an electrode structure; a capacitor structure on the electrode structure, the capacitor structure comprising: a bottom electrode structure comprising: a first electrode comprising a first lateral thickness; and a second electrode on the first electrode, the second electrode comprising a second lateral thickness greater than the first lateral thickness; a dielectric comprising a non-linear polar material having a form ABB'O3, AA'B'O3, or ABO3, wherein A' is a first dopant for atomic site A, wherein B' is a second dopant for atomic site B, and wherein O is oxygen; and a third electrode on the dielectric; and an encapsulation structure comprising: a first portion adjacent to a first sidewall of the first electrode and adjacent to a lower surface of the second electrode; and a second portion adjacent to a second sidewall of the second electrode, a third sidewall of the dielectric, and a fourth sidewall of the third electrode. 2. The device structure of claim 1, wherein the first lateral thickness is at least 2 nm less than the second lateral thickness. 3. The device structure of claim 1, wherein the electrode structure comprises: a conductive hydrogen barrier layer comprising one of: TiAlN with greater than 30 atomic percent AlN, TaN with greater than 30 atomic percent nitrogen, TiSiN with greater than 20 atomic percent SiN, TaC, TiC, WC, WN, carbonitrides of Ta, Ti, W, TiO, Ti2O, WO3, SnO2, ITO, IGZO, zinc oxide or METGLAS series of alloys; and a fill metal within the conductive hydrogen barrier layer, wherein the fill metal comprises one of tantalum, titanium, ruthenium, tungsten, molybdenum or copper, Docket No.: KP12P064US-PCT wherein the second electrode comprises one of: a first non-Pb based metal oxide, such as but not limited to, La(1-x)Sr(x)FeO3, La(1-x)Sr(x)CoO3, La(1-x)Ca(x)MnO3, La(1-x)Sr(x)MnO3, Ba(1-x)Sr(x)RuO3, La(1-x)Sr(x)MnO3, wherein 0 ≤ x ≤ 1, SrRuO3, Sr2RuO4, SrMoO3, SrCoO3, SrCrO3, SrFeO3, SrVO3, CaMoO3, SrNbO3, LaNiO3, YBa2Cu3O7, Bi2Sr2CaCuO8, CaRuO3, Ir, Ir2Oy, Ru, RuOy, Mo, MoOy, W, or WOy, wherein ‘y’ is an integer, wherein the third electrode comprises one of: a second non-Pb metal oxide, such as but not limited to, La(1-x)Sr(x)FeO3, La(1-x)Sr(x)CoO3, La(1-x)Ca(x)MnO3, La(1- x)Sr(x)MnO3, Ba(1-x)Sr(x)RuO3, La(1-x)Sr(x)MnO3, wherein 0 ≤ x ≤ 1, SrRuO3, Sr2RuO4, SrMoO3, SrCoO3, SrCrO3, SrFeO3, SrVO3, CaMoO3, SrNbO3, LaNiO3, YBa2Cu3O7, Bi2Sr2CaCuO8, CaRuO3, Ir, Ir2Oy, Ru, RuOy, Mo, MoOy, W, or WOy, wherein ‘y’ is an integer, and wherein the first electrode comprises one of: niobium, chromium, molybdenum, tantalum, tungsten, rhenium, titanium, nitrogen doped variants of niobium, chromium, molybdenum, tantalum, tungsten, rhenium, titanium, nitrides of tantalum, tungsten, titanium, conductive doped AlN, or conductive doped SiN. 4. The device structure of claim 3, wherein the electrode structure comprises a third lateral thickness that is less than the first lateral thickness. 5. The device structure of claim 1, wherein the first electrode has a vertical thickness orthogonal to the first lateral thickness, wherein the first portion has a fourth lateral thickness, and wherein the fourth lateral thickness is different from the vertical thickness. 6. The device structure of claim 5, wherein the fourth lateral thickness varies with height, and wherein the fourth lateral thickness is at least equal to a quarter of the vertical thickness. 7. The device structure of claim 6, wherein the first portion and the second portion are contiguous, and wherein the first portion further comprises a cavity. 8. The device structure of claim 1, further comprising an insulator laterally adjacent to the electrode structure, wherein the second portion is in contact with the insulator. Docket No.: KP12P064US-PCT 9. The device structure of claim 8, further comprising a liner between the insulator and the electrode structure, wherein the second portion further extends on the liner. 10. The device structure of claim 9, wherein the encapsulation structure comprises one of: silicon nitride, carbon doped silicon nitride, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx, or TaSiOx, wherein ‘x’ and ‘y’ are first and second integers, respectively, wherein the liner comprises one of: silicon nitride, carbon doped silicon nitride, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx, or TaSiOx, wherein ‘x’ and ‘y’ are third and fourth integers, respectively, wherein the insulator comprises one of: silicon nitride, or carbon doped silicon nitride, and wherein the insulator and the encapsulation structure comprise a different material. 11. The device structure of claim 8, wherein the encapsulation structure further comprising a third portion that extends laterally on the insulator beyond an outer sidewall of the second portion. 12. The device structure of claim 11, wherein the encapsulation structure further comprising a fourth portion that extends on the second portion and on an uppermost surface of the third electrode. 13. The device structure of claim 5, wherein the second portion comprises a fifth lateral thickness, and wherein a minimum value of the fourth lateral thickness is equal to the fifth lateral thickness. 14. The device structure of claim 1, wherein the dielectric comprises: the form ABB'O3, wherein A includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na, wherein B includes one of Mn, Fe, Ta, or Nb, and wherein B' includes one of: Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, or Zn; the form ABO3, wherein A includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na, and wherein B includes one of Mn, Fe, Ta, or Nb; or the form AA'BO3, wherein A includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na, wherein B includes one Docket No.: KP12P064US-PCT of Mn, Fe, Ta, or Nb, and wherein A' includes one of Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, or Lu. 15. A device structure comprising: a plurality of electrode structures; a plurality of capacitor structures, wherein individual ones of the plurality of capacitor structures are coupled with individual ones of the plurality of electrode structures, and wherein the individual ones of the plurality of capacitor structures comprise: a bottom electrode structure, comprising: a first electrode comprising a first lateral width; and a second electrode on the first electrode comprising a second lateral with greater than the first lateral width; a dielectric comprising a non-linear polar material; and a third electrode on the dielectric; and an encapsulation structure comprising: a first portion adjacent to a first sidewall of the first electrode and adjacent to a lower surface of the second electrode; and a second portion adjacent to a second sidewall of the second electrode, a third sidewall of the dielectric, and a fourth sidewall of the third electrode, wherein the first portion and the second portion are contiguous. 16. The device structure of claim 15, wherein the encapsulation structure further comprises a third portion that is contiguous between a first capacitor and a second capacitor in the plurality of capacitor structures. 17. The device structure of claim 15, wherein a top surface of the encapsulation structure is substantially planar or co-planar with an uppermost surface of the third electrode. 18. The device structure of claim 15, wherein the dielectric comprises one of: a first form ABB’O3, wherein A includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na, wherein B includes Docket No.: KP12P064US-PCT one of Mn, Fe, Ta, or Nb, and wherein ‘B'’ includes one of: Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, or Zn; a second form AA'BO3, wherein A includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na, wherein B includes one of Mn, Fe, Ta, or Nb, wherein A' includes one of Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, or Lu; a third form ABO3, wherein A includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na, and wherein B includes one of Mn, Fe, Ta, or Nb; bismuth ferrite (BFO), or BFO with a first doping material, wherein the first doping material is one of lanthanum, elements from lanthanide series of a periodic table, or elements of 3d, 4d, 5d, 6d, 4f, or 5f series of periodic table; lead zirconium titanate (PZT) or PZT with a second doping material, wherein the second doping material is one of La or Nb; a perovskite comprising one of: BaTiO3, KNbO3, PbTiO3, or NaTaO3; BaTiO3, KNbO3, or NaTaO3 doped with La or Lanthanides; or PbTiO3 substitutionally doped with Zr, La, or Nb; a relaxor ferroelectric material which includes one of: lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or barium titanium-barium strontium titanium (BT- BST); a BaTiO₃ (BTO) based relaxor which includes one of: BaTiO₃-Bi(Zn₁/₂Ti₁/₂)O₃ (BTO-BZT), BaTiO₃-BiScO₃ (BTO-BS): BiScO₃, Ba(₁-x)SrxTiO₃ (BST), BaTiO₃- Pb(Mg₁/₃Nb₂/₃)O₃ (BTO-PMN), BaTi(1-x)ZrxO₃ (BTZ), BaTiO₃-Pb(Zn₁/₃Nb₂/₃)O₃ (BTO-PZN), BaTiO₃-Pb(Sc₁/₂Nb₁/₂)O₃ (BTO-PSN), where 0 < x < 1; a PZT based relaxor which includes one of: PZT-Pb(Mg₁/₃Nb₂/₃)O₃ (PZT-PMN), PZT-Pb(Ni₁/₃Nb₂/₃)O₃ (PZT-PNN), PZT-Pb(Zn₁/₃Nb₂/₃)O₃ (PZT-PZN), PZT- Pb(Sc₁/₂Nb₁/₂)O₃ (PZT-PSN), PZT-Pb(Fe₁/₂Nb₁/₂)O₃ (PZT-PFN), PZT- PbxLa1- x(ZryTi1-y)O3 (PZT-PLZT), where 0 ≤ x ≤ 1 and where 0 ≤ y ≤ 1, or PZT-PbTi(1- x)Mn(x)O₃ (PZT-PTM), where 0 ≤ x ≤ 1; Docket No.: KP12P064US-PCT a SrBi₂Ta₂O₉ (SBT) based relaxor which includes one of: paraelectric SBT- SrBi₂[Nb(1-x)Ta(x)]₂O₉ (SBT-SBNT), where 0 ≤ x ≤ 1, or SBT doped with one of: Mn, Fe, Co, La, Ce or Nd, Ba or Ca; a first hexagonal ferroelectric which includes one of: YMnO3 or LuFeO3; a second hexagonal ferroelectric of a type RMnO3, where R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y); lithium niobate, lithium tantalate, lithium iron tantalum oxy fluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate; an improper ferroelectric material which includes one of: [PTO/STO]n or [LAO/STO]n, wherein ‘n’ is between 1 and 100; hafnium (Hf), Zirconium (Zr), Aluminum (Al), Silicon (Si), an oxide of hafnium (Hf), Zirconium (Zr), Aluminum (Al), or Silicon (Si), or an alloyed oxide of hafnium (Hf), Zirconium (Zr), Aluminum (Al), or Silicon (Si); hafnium oxide of a form Hf(1-x)ExOy, where E includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y, wherein ‘x’ and ‘y’ are first and second fractions, respectively; HfO2 doped with one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y; Al(1-x)Sc(x)N, Ga(1-x)Sc(x)N, Al(1-x)Y(x)Nor Al(1-x-y)Mg(x)Nb(y)N, wherein ‘x’ and ‘y’ are third and fourth fractions, respectively; LiNbO3, LiTaO3, LiTaO2F2, Sr(^)Ba(1-x)Nb₂O₆ where 0.32 ≤ x ≤ 0.8, or KSr2Nb5O15; a paraelectric material comprising SrTiO3, Ba(x)Sr(y)TiO3, where 0 < x < 1 and where 0 < y < 1 HfZrO2, Hf-Si-O, or La-substituted PbTiO3; or an antiferroelectric material comprising one of: HfSiO2 doped with >30% Si or >30% Zr; HfZrO2 doped with >30% Si or >30% Zr; ZrO2 or NaNbO3; NaNbO3, PbZrO3, or PbZrO3 doped with >5% K; a first solid solution including one of: PbTiO3, SrTiO3, PbHfO3, PbHfO3, Pb(Lu0.5Nb0.5)O3, Pb(Lu0.5Nb0.5)O3, Pb(Yb0.5Nb0.5)O3, AgNbO3 or NaNbO3; or Docket No.: KP12P064US-PCT a second solid solution including PbTiO3 and one of: SrTiO3, PbHfO3, PbHfO3, Pb(Lu0.5Nb0.5)O3, Pb(Lu0.5Nb0.5)O3, Pb(Yb0.5Nb0.5)O3, AgNbO3 or NaNbO3. 19. A system, comprising: a transistor comprising: a source; a drain; and a gate; a capacitor coupled with the transistor, the capacitor comprising: a bottom electrode structure, comprising: a first electrode comprising a first lateral thickness; and a second electrode on the first electrode, the second electrode comprising a second lateral thickness greater than the first lateral thickness; a dielectric comprising a non-linear polar material having a form ABB'O3, AA'B'O3, or ABO3, wherein A' is a first dopant for atomic site A, wherein B' is a second dopant for atomic site B, and wherein O is oxygen; and a third electrode on the dielectric; an encapsulation structure comprising: a first portion adjacent to a first sidewall of the first electrode and adjacent to a lower surface of the second electrode; and a second portion adjacent to a second sidewall of the second electrode, a third sidewall of the dielectric, and a fourth sidewall of the third electrode, wherein the first portion and the second portion are contiguous; and an electrode structure coupled between the drain and the capacitor. 20. The system of claim 19, wherein the electrode structure comprises: a conductive hydrogen barrier layer comprising one of: TiAlN with greater than 30 atomic percent AlN, TaN with greater than 30 atomic percent nitrogen, TiSiN with greater than 20 atomic percent SiN, TaC, TiC, WC, WN, carbonitrides of Ta, Ti, W, TiO, Ti2O, WO3, SnO2, ITO, IGZO, zinc oxide or METGLAS series of alloys; and a fill metal within the conductive hydrogen barrier layer, wherein the fill metal comprises one of tantalum, titanium, ruthenium, tungsten, molybdenum or copper, wherein the first electrode comprises one of: niobium, chromium, molybdenum, tantalum, tungsten, rhenium, titanium, nitrogen doped variants of niobium, chromium, molybdenum, tantalum, tungsten, rhenium, titanium, conductive doped AIN, or conductive doped SiN, wherein the second electrode comprises one of: a first non-Pb based metal oxide, such as but not limited to Lap-xjSr^FeOs, La<i.X)Sr(X)CoO3, La<i-x)Ca(x)MnO3, La<i-x)Sr(x)MnO3, Bao.X)Sr(X)RuO3, La<i.x)Sr(x)MnO3, wherein 0 < x < 1, SrRuOs, Sr2RuO4, SrMoO3, SrCoO3, SrCrO3, SrFeO3, SrVO3, CaMoO3, SrNbO3, LaNiO3, YBa2Cu3O?, Bi2Sr2CaCuOs, CaRuO3, Ir, Ir2Oy, Ru, RuOy, Mo. MoOy, W, or WOy, wherein ‘y’ is an integer, wherein the third electrode comprises one of: a second non-Pb metal oxide, such as but not limited to, La<i-X)Sr(x)FeO3, La<i-x)Sr(X)CoO3, La<i-x)Ca(x)MnO3, La<i- x)Sr(X)MnO3, Ba<i-x)Sr(x)RuO3, La<i-x)Sr x)MnO3, wherein 0 < x < 1, SrRuO3, Sr2RuO4, SrMoO3, SrCoO3, SrCrO3, SrFeO3, SrVO3, CaMoO3, SrNbO3, LaNiO3, YBa2Cu3O7. Bi2Sr2CaCuOs, CaRuO3, Ir, Ir2Oy. Ru, RuOy, Mo. MoOy, W, or WOy, wherein ‘y’ is an integer, and wherein the transistor is one of: a planar, non-planar or a nano-wire transistor.
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