WO2025118429A1

WO2025118429A1 - Method, apparatus, and system for blockwise channel interleaving for error correction coding

Info

Publication number: WO2025118429A1
Application number: PCT/CN2024/081456
Authority: WO
Inventors: Huazi ZHANG; Jianglei Ma; Wen Tong
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2023-12-04
Filing date: 2024-03-13
Publication date: 2025-06-12
Anticipated expiration: 2026-06-04

Abstract

Provided are a communication method, apparatus, and system. An apparatus such as a channel interleaver could obtain a first code bit sequence, where the first code bit sequence is obtained after rate matching a second code bit sequence, divide the first code bit sequence into blocks, and channel interleave the blocks according to a pre-defined order, where the channel interleaving is applied to the first code bit sequence before modulation and transmission to a channel. Because the first code bit sequence could be divided into blocks for channel interleaving, the blockwise interleaving with higher parallelism could be implemented, and thus, the flexibility, simplicity, and higher throughput can be achieved while stable or superior performance could be provided under high-order modulation or in a fading channel.

Description

METHOD, APPARATUS, AND SYSTEM FOR BLOCKWISE CHANNEL INTERLEAVING FOR ERROR CORRECTION CODING

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to US provisional patent application No. 63/605, 673, filed on December 04, 2023, which is hereby incorporated by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates generally to the field of wireless communications technologies and, in particular, to a communication method, apparatus, and system.

BACKGROUND

In wireless communications, channel quality is constantly changing due to the fading effects at both fast and slow scale. Accordingly, channel coding has always been designed to adapt to the channel states. Modulation coding scheme (MCS) adaptation is a powerful method to combat varying channel states, in which the modulation order and code length and coding rate can be changed in real time. Therefore, it requires that a channel coding scheme can flexibly change the code length and code rate in a fine-grained way, and at the same time achieve good error correction performance in all possible configurations. This fine-grained flexibility of channel codes is one of the most challenging problem for engineers in this domain.

At the same time, the complexity of both encoding and decoding algorithms need to be sufficiently low. In hardware, complexity can be evaluated through measuring chip area and energy efficiency. They are related to algorithmic complexity, but are more closely related to hardware cost and battery life. Therefore, there exists a desire to reduce implementation complexity when designing coding schemes.

Future communication systems, such as so-called sixth-generation (6G) systems, may aim to support several challenging scenarios, including for example immersive communication, massive communication, and hyper reliable and low-latency communication. The KPIs that are related to channel coding include coding gain, reliability, throughput, latency and their tradeoffs. For example, the throughput target of 6G may reach above 1 Tbps, and the energy efficiency target may decrease to 1 pJ/bit. Meanwhile, a coding scheme supporting flexible rate matching and IR-HARQ schemes is also beneficial. Accordingly, it is desirable yet challenging to design a code ensemble to fulfill all these KPIs and capabilities.

This background information is provided to reveal information believed by the applicant to be of possible relevance to the present disclosure. No admission is necessarily intended, nor should be construed, that any of the preceding information constitutes prior art against the present disclosure.

SUMMARY

In a first aspect, the present disclosure provides a communication method, including:

obtaining a first code bit sequence, where the first code bit sequence is obtained after rate matching a second code bit sequence;

dividing the first code bit sequence into blocks; and

channel interleaving the blocks according to a pre-defined order, where the channel interleaving is applied to the first code bit sequence before modulation and transmission to a channel.

Because the first code bit sequence could be divided into blocks for channel interleaving, the blockwise interleaving with higher parallelism could be implemented, and thus, the flexibility, simplicity, and higher throughput can be achieved while stable or superior performance could be provided under high-order modulation or in a fading channel.

In a possible implementation of the first aspect, the pre-defined order is stored in a table or indicated by a sequence.

Because the pre-defined order could be stored in the table or indicated by the sequence, the order could be changed as required, thereby improving the flexibility of channel interleaving of the blocks.

In a possible implementation of the first aspect, the pre-defined order is a reverse order of the blocks.

Because the simple rule could be used to interleave the blocks, such as the reverse order of the blocks, the interleaving of the blocks could be implemented simply, thereby the complexity of interleaving could be reduced.

In a possible implementation of the first aspect, the order of bits in each of the blocks is unchanged before and after the interleaving.

Because the order of bits in each of the blocks is unchanged before and after the interleaving, the code bit sequence could be processed in a unit of block, and thus the block-wise interleaving with higher parallelism could be achieved and throughput could be improved while stable or superior performance could be provided under high-order modulation or in a fading channel.

In a possible implementation of the first aspect, the dividing the first code bit sequence into blocks is performed independent of a modulation order.

Because the division of the first code bit sequence is independent of the modulation order, a modulation-independent interleaver may be implemented. The interleaver may have a deterministic structure, and thus is simple to be implemented. The interleaver, although having a deterministic structure, serves as a pseudo-random interleaver for blockwise channel interleaving, thereby providing higher throughput as well as stable or superior performance under high-order modulation or in a fading channel.

In a possible implementation of the first aspect, where a block size is predefined in a protocol.

In a possible implementation of the first aspect, a block size is a power-of-2 number.

In a possible implementation of the first aspect, the block size is 8, 16, 32, 64, or 128.

In a possible implementation of the first aspect, a block size is a prime number.

In a possible implementation of the first aspect, the block size is 5, 7, 11, 13, 17, or 19.

Because the block size could be predefined in a protocol and could be set as different kinds of numbers according to actual demands, various application scenario could be adapted to, thereby improving the flexibility and universality of the interleaving.

In a possible implementation of the first aspect, the channel interleaving the blocks according to the pre-defined order includes:

writing the blocks block-by-block into a buffer of a given shape according to the predefined order; and

reading the blocks block-by-block from the buffer of the given shape according to a different predefined order to obtain an output sequence.

Because the code bit sequence could be written into and read from the buffer block-by-block, the throughput could be greatly improved compared with the bit-by-bit serial operation.

In a possible implementation of the first aspect, the given shape is a square, a rectangle, a triangle, or a trapezoid.

Because the buffer could have various shapes such as a square, a rectangle, a triangle, or a trapezoid, different application scenario could be adapted to, thereby the flexibility of interleaving could be implemented.

In a possible implementation of the first aspect, the method further includes:

sequentially feeding the output sequence to a modulator, where consecutive bits in each of blocks of the output sequence are mapped to one symbol.

Because the output sequence in the form of block could be sequentially fed to the modulator, consecutive bits of each block could be mapped to one symbol, the modulation could be implemented with high efficiency.

In a possible implementation of the first aspect, the dividing the first code bit sequence into blocks is performed dependent of a modulation order.

Because the division of the first code bit sequence is dependent of the modulation order, modulation-specific blockwise interleaver could be implemented. Joint design could be favored to optimize the interleaver given a specific modulation order, thereby polarization could be increased and performance could be improved.

In a possible implementation of the first aspect, where a block size based on the modulation order.

Because the interleaving may use parameter (s) which depend on the modulation order, joint design could be achieved, which is favored to optimize the interleaver given a specific modulation order.

In a possible implementation of the first aspect, the block size is a divisor of the modulation order and a positive even integer.

In a possible implementation of the first aspect, the positive even integer is a fixed value.

In a possible implementation of the first aspect, the positive even integer is 2 4 6 8, or 10.

Because the block size depending on the modulation order could be predefined in a protocol and could be set to different numbers obtained based on the modulation order, the interleaving could adapt to different application scenarios, thereby improving the flexibility of interleaving.

In a possible implementation of the first aspect, the blocks are grouped into multiple groups of blocks, and a number of blocks in each of the multiple groups is equal to the positive even integer.

writing the blocks in each of the multiple groups block-by-block according to the predefined order.

Because the blocks are further grouped into multiple groups, the blockwise interleaving with higher parallelism could be implemented further based on group, and the code bits that will be mapped to one symbol could be grouped together, which could facilitate subsequent modulation and thus improve processing efficiency, thereby further improving the throughput of interleaver.

In a possible implementation of the first aspect, each of multiple groups of blocks is written block-by-block into a rectangle-shaped buffer row-by-row in either left-to-right order or right-to-left order, where a number of rows of the rectangle-shaped buffer is equal to the positive even integer; and the blocks are read block-by-block from the rectangle-shaped buffer column-by-column in either top-down order or bottom-up order to obtain an output sequence, where each of columns includes a respective group of multiple groups.

Because the code bit sequence could be written into and read out from the rectangle-shaped buffer block-by-block based on group, processing overhead could be reduced and the throughput could be greatly improved compared with interleaving with a triangle-shaped buffer.

In a possible implementation of the first aspect, the method further includes:

sequentially feeding an output sequence to a modulator, where consecutive bits of each of the multiple groups of block are mapped to one modulated symbol.

Because the output sequence is obtained by blockwise interleaving based on group, and the output sequence is sequentially fed into the modulator, code bits of each group could be consecutively fed into the modulator and then be mapped to a respective symbol, the efficiency of the modulation with could be further improved.

In a possible implementation of the first aspect, the dividing the first code bit sequence into blocks includes:

dividing the first code bit sequence into systematic blocks and parity blocks for systematic code, where the systematic blocks are blocks including systematic bits, and the parity blocks are blocks including parity bits.

Because the first code bit sequence could be divided into systematic blocks and parity blocks for channel interleaving of systematic code, the blockwise interleaving with higher parallelism could be implemented for systematic code, which could improve the flexibility, simplicity, and throughput for systematic code.

In a possible implementation of the first aspect, the systematic blocks and the parity blocks for the systematic code are grouped into multiple groups of blocks, where each of multiple groups includes at least one systematic block and at least one parity block.

Because the systematic blocks and parity blocks are further grouped into multiple groups, the blockwise interleaving with higher parallelism could be implemented for systematic code based on group, which could improve the throughput of the interleaver for systematic code. Since each group could include at least one systematic block and at least one parity block, the code bits of each group could include both systematic bits and parity bits, which can meet the requirement of modulation for systematic code, thereby facilitating the subsequent modulation for systematic code, as well as modulation efficiency enhancement and further throughput improvement.

In a possible implementation of the first aspect, the systematic blocks are written row-by-row in left-to-right order and the parity blocks are written row-by-row in right-to-left order, or the systematic blocks are written row-by-row in right-to-left order and the parity blocks are written row-by-row in left-to-right order, or the systematic blocks and the parity blocks are written in zigzag order.

In a possible implementation of the first aspect, the systematic blocks are read column-by-column in top-down order and the parity blocks are read column-by-column in bottom-up order, or the systematic blocks are read column-by-column in bottom-up order and the parity blocks are read column-by-column in top-down order, or the systematic blocks and the parity blocks are read in zigzag order.

Because the code bit sequence could be written into and read out from the rectangle-shaped buffer block-by-block based on group in several different kinds of orders, different application scenario for systematic code could be adapted to, thereby improving the flexibility of interleaving for systematic code.

In a possible implementation of the first aspect, consecutive bits in the at least one systematic block in each of multiple groups of blocks are mapped to high-energy bits, and consecutive bits in the at least one parity block in each of multiple groups of blocks are mapped to low-energy bits.

Because systematic bits are mapped to high-energy bits and parity bits are mapped to low-energy bits, the systematic bits could be mapped to more reliable bits, which could improve the performance of systematic code.

dividing the first code bit sequence into first blocks and second blocks for non-systematic code, where the first blocks includes bits from a first half of the second code bit sequence and the second blocks includes bits from a second half of the second code bit sequence.

Because the first code bit sequence could be divided into blocks for channel interleaving of non-systematic code, the blockwise interleaving with higher parallelism could be implemented for non-systematic code, which could improve the flexibility, simplicity, and throughput for non-systematic code.

In a possible implementation of the first aspect, the first blocks and the second blocks for the non-systematic code are grouped into multiple groups of blocks.

Because the first blocks and second blocks are further grouped into multiple groups, the blockwise interleaving with higher parallelism could be implemented for non-systematic code based on group, which could improve the throughput of the interleaver for non-systematic code. The code bits that will be mapped to one symbol are grouped together, thereby facilitating the subsequent modulation for non-systematic code, as well as modulation efficiency enhancement and further throughput improvement.

In a possible implementation of the first aspect, the first blocks are written row-by-row in left-to-right order and the second blocks are written row-by-row in right-to-left order, or the first blocks are written row-by-row in right-to-left order and the second blocks are written row-by-row in left-to-right order, or the first blocks and the second blocks are written row-by-row in zigzag order.

In a possible implementation of the first aspect, the first blocks are read column-by-column in top-down order and the second blocks are read column-by-column in bottom-up order, or the first blocks are read column-by-column in bottom-up order and the second blocks are read column-by-column in top-down order, or the first blocks and the second blocks are read column-by-column in zigzag order.

Because the code bit sequence could be written into and read out from the rectangle-shaped buffer block-by-block based on group in several different kinds of orders, different application scenario for non-systematic code could be adapted to, thereby improving the flexibility of interleaving for non-systematic code.

In a possible implementation of the first aspect, consecutive bits in the at least one first block in each of multiple groups of blocks are mapped to high-energy bits, and consecutive bits in the at least one second block in each of multiple groups of blocks are mapped to low-energy bits.

Because first blocks and second blocks could be mapped to bits with different energy based on group, the energy difference for different groups of bits could lead to more different capacity in the polarized subchannels, making it even more polarized, thereby the polarization could be improved.

In a possible implementation of the first aspect, the modulation mode is quadrature amplitude modulation (QAM) .

The QAM may be used to modulate the bit sequence obtained after channel interleaving. Parameters of interleaving such as a block size could be dependent on the modulation order of QAM. For different QAM orders, different block sizes may be used. For polar codes, QAM-specific mapping could increase polarization and thus improve performance.

In a second aspect, the present disclosure provides a communication method, including:

receiving interleaved blocks of a first bit sequence, where the interleaved blocks of the first bit sequence is obtained by channel interleaving blocks of the first code bit sequence, where the first code bit sequence is divided into the blocks and the first code bit sequence is obtained after rate matching a second code bit sequence; where the blocks are channel interleaved according to a pre-defined order, where the channel interleaving is applied to the first code bit sequence before modulation and transmission to a channel; and

decoding the encoded sequence to obtain decoded code bit sequence.

In a possible implementation of the second aspect, the pre-defined order is stored in a table or indicated by a sequence.

In a possible implementation of the second aspect, the pre-defined order is a reverse order of the blocks.

In a possible implementation of the second aspect, the order of bits in each of the blocks is unchanged before and after the interleaving.

In a possible implementation of the second aspect, the first code bit sequence is divided into blocks independent of a modulation order.

In a possible implementation of the second aspect, a block size is predefined in a protocol.

In a possible implementation of the second aspect, a block size is a power-of-2 number.

In a possible implementation of the second aspect, the block size is 8, 16, 32, 64, or 128.

In a possible implementation of the second aspect, a block size is a prime number.

In a possible implementation of the second aspect, the block size is 5, 7, 11, 13, 17, or 19.

In a possible implementation of the second aspect, the blocks are interleaved by:

writing the blocks block-by-block into a buffer of a given shape according to the predefined order; and reading the blocks block-by-block from the buffer of the given shape according to a different predefined order to obtain an output sequence.

In a possible implementation of the second aspect, the given shape is a square, a rectangle, a triangle, or a trapezoid.

In a possible implementation of the second aspect, the blocks are interleaved further by:

In a possible implementation of the second aspect, the first code bit sequence is divided into blocks dependent of a modulation order.

In a possible implementation of the second aspect, a block size of block is determined based on the modulation order.

In a possible implementation of the second aspect, the block size is a divisor of the modulation order and a positive even integer.

In a possible implementation of the second aspect, the positive even integer is a fixed value.

In a possible implementation of the second aspect, the positive even integer is 2 4 6 8, or 10.

In a possible implementation of the second aspect, the blocks are grouped into multiple groups of blocks, and a number of blocks in each of the multiple groups is equal to the positive even integer.

In a possible implementation of the second aspect, each of multiple groups of blocks is written block-by-block into a rectangle-shaped buffer row-by-row in either left-to-right order or right-to-left order, where a number of rows of the rectangle-shaped buffer is equal to the positive even integer; and the blocks are read block-by-block from the rectangle-shaped buffer column-by-column in either top-down order or bottom-up order to obtain an output sequence, where each of columns includes a respective group of multiple groups.

In a possible implementation of the second aspect, the first code bit sequence is divided into blocks by:

In a possible implementation of the second aspect, the systematic blocks and the parity blocks for the systematic code are grouped into multiple groups of blocks, where each of multiple groups includes at least one systematic block and at least one parity block.

In a possible implementation of the second aspect, the systematic blocks are written row-by-row in left-to-right order and the parity blocks are written row-by-row in right-to-left order, or the systematic blocks are written row-by-row in right-to-left order and the parity blocks are written row-by-row in left-to-right order, or the systematic blocks and the parity blocks are written in zigzag order.

In a possible implementation of the second aspect, the systematic blocks are read column-by-column in top-down order and the parity blocks are read column-by-column in bottom-up order, or the systematic blocks are read column-by-column in bottom-up order and the parity blocks are read column-by-column in top-down order, or the systematic blocks and the parity blocks are read in zigzag order.

In a possible implementation of the second aspect, consecutive bits in the at least one systematic block in each of multiple groups of blocks are mapped to high-energy bits, and consecutive bits in the at least one parity block in each of multiple groups of blocks are mapped to low-energy bits.

In a possible implementation of the second aspect, the first blocks and the second blocks for the non-systematic code are grouped into multiple groups of blocks.

In a possible implementation of the second aspect, the first blocks are written row-by-row in left-to-right order and the second blocks are written row-by-row in right-to-left order, or the first blocks are written row-by-row in right-to-left order and the second blocks are written row-by-row in left-to-right order, or the first blocks and the second blocks are written row-by-row in zigzag order.

In a possible implementation of the second aspect, the first blocks are read column-by-column in top-down order and the second blocks are read column-by-column in bottom-up order, or the first blocks are read column-by-column in bottom-up order and the second blocks are read column-by-column in top-down order, or the first blocks and the second blocks are read column-by-column in zigzag order.

In a possible implementation of the second aspect, consecutive bits in the at least one first block in each of multiple groups of blocks are mapped to high-energy bits, and consecutive bits in the at least one second block in each of multiple groups of blocks are mapped to low-energy bits.

In a possible implementation of the second aspect, the modulation mode is quadrature amplitude modulation (QAM) .

In a third aspect, the present disclosure provides a first apparatus, including an interface and a channel interleaver for executing the method according to the first aspect or any possible implementation of the first aspect.

In a fourth aspect, the present disclosure provides a second apparatus, including an interface and a channel interleaver for executing the method according to the second aspect or any possible implementation of the second aspect.

In a fifth aspect, the present disclosure provides a third apparatus including a processor configured to cause the third apparatus to perform the method according to the first aspect or any possible implementation of the first aspect.

In a sixth aspect, the present disclosure provides a fourth apparatus including a processor configured to cause the fourth apparatus to perform the method according to the second aspect or any possible implementation of the second aspect.

In a seventh aspect, the present disclosure provides a computer program including programming for execution by a processor, the programming including instructions to perform the method according to the first aspect, any possible implementation of the first aspect, the second aspect, or any possible implementation of the second aspect.

In an eighth aspect, the present disclosure provides a non-transitory computer readable medium storing programming for execution by a processor, the programming including instructions to perform the method according to the first aspect, any possible implementation of the first aspect, the second aspect, or any possible implementation of the second aspect.

In an ninth aspect, the present disclosure provides a system including:

a first communication device configured to perform the method according to the first aspect or any possible implementation of the first aspect; and

a second communication device configured to perform the method according to the second aspect or any possible implementation of the second aspect.

The present disclosure provides a communication method, apparatus, and system. An apparatus such as a channel interleaver could obtain a first code bit sequence, where the first code bit sequence is obtained after rate matching a second code bit sequence, divide the first code bit sequence into blocks, and channel interleave the blocks according to a pre-defined order, where the channel interleaving is applied to the first code bit sequence before modulation and transmission to a channel. Because the first code bit sequence could be divided into blocks for channel interleaving, the blockwise interleaving with higher parallelism could be implemented, and thus, the flexibility, simplicity, and higher throughput can be achieved while stable or superior performance could be provided under high-order modulation or in a fading channel.

BRIEF DESCRIPTION OF DRAWINGS

Reference will now be made, by way of example, to the accompanying drawings which show example embodiments of the present disclosure, and in which:

FIG. 1 is a simplified schematic illustration of a communication system according to one or more example embodiments of the present disclosure.

FIG. 2 is a schematic illustration of an example communication system according to one or more example embodiments of the present disclosure.

FIG. 3 is a schematic illustration of a basic component structure of a communication system according to one or more example embodiments of the present disclosure.

FIG. 4 is a block diagram of a device in a communication system according to one or more example embodiments of the present disclosure.

FIG. 5 is an example trellis graph of polar code according to one or more example embodiments of the present disclosure.

FIG. 6 is a schematic illustration of an example interleaver scheme according to one or more example embodiments of the present disclosure.

FIG. 7 is a schematic illustration of an example polar code rate matching according to one or more example embodiments of the present disclosure.

FIG. 8 is a schematic illustration of an example polar HARQ according to one or more example embodiments of the present disclosure.

FIG. 9 is a schematic illustration of an example encoding process according to one or more example embodiments of the present disclosure.

FIG. 10 is another schematic illustration of the example encoding process according to one or more example embodiments of the present disclosure.

FIG. 11 is yet another schematic illustration of the example encoding process according to one or more example embodiments of the present disclosure.

FIG. 12 is a schematic illustration of an example polar code scheme according to one or more example embodiments of the present disclosure.

FIG. 13 is a schematic flowchart of a communication method according to one or more example embodiments of the present disclosure.

FIG. 14 is a schematic illustration of an example procedure of blockwise QAM-independent interleaver according to one or more example embodiments of the present disclosure.

FIG. 15 is a schematic illustration of an example procedure of blockwise QAM-dependent interleaver according to one or more example embodiments of the present disclosure.

FIG. 16 is a schematic flowchart of another communication method according to one or more example embodiments of the present disclosure.

FIG. 17 is a schematic structural diagram of a first apparatus according to one or more example embodiments of the present disclosure.

FIG. 18 is a schematic structural diagram of a second apparatus according to one or more example embodiments of the present disclosure.

DESCRIPTION OF EMBODIMENTS

In the following description, reference is made to the accompanying figures, which form part of the present disclosure, and which show, by way of illustration, specific aspects of embodiments of the present disclosure or specific aspects in which embodiments of the present disclosure may be used. It is understood that embodiments of the present disclosure may be used in other aspects and include structural or logical changes not depicted in the figures. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims.

To assist in understanding the present disclosure, examples of wireless communication systems and devices are described below.

Referring to FIG. 1, as an illustrative example without limitation, a simplified schematic illustration of a communication system is provided. The communication system 100 comprises a radio access network 120. The radio access network 120 may be a next generation (e.g. sixth generation (6G) or later) radio access network, or a legacy (e.g. 5G, 4G, 3G or 2G) radio access network. One or more communication electronic devices (ED) 110a, 110b, 110c, 110d, 110e, 110f, 110g, 110h, 110i, 110j (generically referred to as 110) may be interconnected to one another or connected to one or more network nodes (170a, 170b, generically referred to as 170) in the radio access network 120. A core network 130 may be a part of the communication system and may be dependent or independent of the radio access technology used in the communication system 100. Also the communication system 100 comprises a public switched telephone network (PSTN) 140, the internet 150, and other networks 160.

FIG. 2 illustrates an example communication system 100. In general, the communication system 100 enables multiple wireless or wired elements to communicate data and other content. The purpose of the communication system 100 may be to provide content, such as voice, data, video, and/or text, via broadcast, multicast, groupcast, unicast, etc. The communication system 100 may operate by sharing resources, such as carrier spectrum bandwidth, between its constituent elements. The communication system 100 may include a terrestrial communication system and/or a non-terrestrial communication system. The communication system 100 may provide a wide range of communication services and applications (such as earth monitoring, remote sensing, passive sensing and positioning, navigation and tracking, autonomous delivery and mobility, etc. ) . The communication system 100 may provide a high degree of availability and robustness through a joint operation of a terrestrial communication system and a non-terrestrial communication system. For example, integrating a non-terrestrial communication system (or components thereof) into a terrestrial communication system can result in what may be considered a heterogeneous network comprising multiple layers. Compared to conventional communication networks, the heterogeneous network may achieve better overall performance through efficient multi-link joint operation, more flexible functionality sharing, and faster physical layer link switching between terrestrial networks and non-terrestrial networks.

The terrestrial communication system and the non-terrestrial communication system could be considered sub-systems of the communication system. In the example shown in FIG. 2, the communication system 100 includes electronic devices (ED) 110a, 110b, 110c, 110d (generically referred to as ED 110) , radio access networks (RANs) 120a, 120b, a non-terrestrial communication network 120c, a core network 130, a public switched telephone network (PSTN) 140, the Internet 150, and other networks 160. The RANs 120a, 120b include respective base stations (BSs) 170a, 170b, which may be generically referred to as terrestrial transmit and receive points (T-TRPs) 170a, 170b. The non-terrestrial communication network 120c includes an access node 172, which may be generically referred to as a non-terrestrial transmit and receive point (NT-TRP) 172.

Any ED 110 may be alternatively or additionally configured to interface, access, or communicate with any T-TRP 170a, 170b and NT-TRP 172, the Internet 150, the core network 130, the PSTN 140, the other networks 160, or any combination of the preceding. In some examples, ED 110a may communicate an uplink and/or downlink transmission over a terrestrial air interface 190a with T-TRP 170a. In some examples, the EDs 110a, 110b, 110c, and 110d may also communicate directly with one another via one or more sidelink air interfaces 190b. In some examples, ED 110d may communicate an uplink and/or downlink transmission over a non-terrestrial air interface 190c with NT-TRP 172.

The air interfaces 190a and 190b may use similar communication technology, such as any suitable radio access technology. For example, the communication system 100 may implement one or more channel access methods, such as code division multiple access (CDMA) , space division multiple access (SDMA) , time division multiple access (TDMA) , frequency division multiple access (FDMA) , orthogonal FDMA (OFDMA) , or single-carrier FDMA (SC-FDMA, also known as discrete Fourier transform spread OFDMA, DFT-s-OFDMA) in the air interfaces 190a and 190b. The air interfaces 190a and 190b may utilize other higher dimension signal spaces, which may involve a combination of orthogonal and/or non-orthogonal dimensions.

The non-terrestrial air interface 190c can enable communication between the ED 110d and one or multiple NT-TRPs 172 via a wireless link or simply a link. For some examples, the link is a dedicated connection for unicast transmission, a connection for broadcast transmission, or a connection between a group of EDs 110 and one or multiple NT-TRPs 172 for multicast transmission.

The RANs 120a and 120b are in communication with the core network 130 to provide the EDs 110a 110b, and 110c with various services such as voice, data, and other services. The RANs 120a and 120b and/or the core network 130 may be in direct or indirect communication with one or more other RANs (not shown) , which may or may not be directly served by core network 130, and may or may not employ the same radio access technology as RAN 120a, RAN 120b or both. The core network 130 may also serve as a gateway access between (i) the RANs 120a and 120b or EDs 110a 110b, and 110c or both, and (ii) other networks (such as the PSTN 140, the Internet 150, and the other networks 160) . In addition, some or all of the EDs 110a 110b, and 110c may include functionality for communicating with different wireless networks over different wireless links using different wireless technologies and/or protocols. Instead of wireless communication (or in addition thereto) , the EDs 110a 110b, and 110c may communicate via wired communication channels to a service provider or switch (not shown) , and to the Internet 150. PSTN 140 may include circuit switched telephone networks for providing plain old telephone service (POTS) . Internet 150 may include a network of computers and subnets (intranets) or both, and incorporate protocols, such as Internet Protocol (IP) , Transmission Control Protocol (TCP) , User Datagram Protocol (UDP) . EDs 110a 110b, and 110c may be multimode devices capable of operation according to multiple radio access technologies, and incorporate multiple transceivers necessary to support such.

FIG. 3 illustrates another example of an ED 110 and a base station 170a, 170b and/or 170c. The ED 110 is used to connect persons, objects, machines, etc. The ED 110 may be widely used in various scenarios including, for example, cellular communications, device-to-device (D2D) , vehicle to everything (V2X) , peer-to-peer (P2P) , machine-to-machine (M2M) , machine-type communications (MTC) , internet of things (IoT) , virtual reality (VR) , augmented reality (AR) , mixed reality (MR) , metaverse, digital twin, industrial control, self-driving, remote medical, smart grid, smart furniture, smart office, smart wearable, smart transportation, smart city, drones, robots, remote sensing, passive sensing, positioning, navigation and tracking, autonomous delivery and mobility, etc.

Each ED 110 represents any suitable end user device for wireless operation and may include such devices (or may be referred to) as a user equipment/device (UE) , a wireless transmit/receive unit (WTRU) , a mobile station, a fixed or mobile subscriber unit, a cellular telephone, a station (STA) , a machine type communication (MTC) device, a personal digital assistant (PDA) , a smartphone, a laptop, a computer, a tablet, a wireless sensor, a consumer electronics device, a smart book, a vehicle, a car, a truck, a bus, a train, or an IoT device, wearable devices (such as a watch, a pair of glasses, head mounted equipment, etc. ) , an industrial device, or an apparatus in (e.g. communication module, modem, or chip) or comprising the forgoing devices, among other possibilities. Future generation EDs 110 may be referred to using other terms. The base station 170a and 170b is a T-TRP and will hereafter be referred to as T-TRP 170. Also shown in FIG. 3, a NT-TRP will hereafter be referred to as NT-TRP 172. Each ED 110 connected to T-TRP 170 and/or NT-TRP 172 can be dynamically or semi-statically turned-on (i.e., established, activated, or enabled) , turned-off (i.e., released, deactivated, or disabled) and/or configured in response to one of more of: connection availability and connection necessity.

The ED 110 includes a transmitter 201 and a receiver 203 coupled to one or more antennas 204. Only one antenna 204 is illustrated to avoid congestion in the drawing. One, some, or all of the antennas 204 may alternatively be panels. The transmitter 201 and the receiver 203 may be integrated, e.g. as a transceiver. The transceiver is configured to modulate data or other content for transmission by at least one antenna 204 or network interface controller (NIC) . The transceiver is also configured to demodulate data or other content received by the at least one antenna 204. Each transceiver includes any suitable structure for generating signals for wireless or wired transmission and/or processing signals received wirelessly or by wire. Each antenna 204 includes any suitable structure for transmitting and/or receiving wireless or wired signals.

The ED 110 includes at least one memory 208. The memory 208 stores instructions and data used, generated, or collected by the ED 110. For example, the memory 208 could store software instructions or modules configured to implement some or all of the functionality and/or embodiments described herein and that are executed by one or more processing unit (s) (e.g., a processor 210) . Each memory 208 includes any suitable volatile and/or non-volatile storage and retrieval device (s) . Any suitable type of memory may be used, such as random access memory (RAM) , read only memory (ROM) , hard disk, optical disc, subscriber identity module (SIM) card, memory stick, secure digital (SD) memory card, on-processor cache, and the like.

The ED 110 may further include one or more input/output devices (not shown) or interfaces (such as a wired interface to the Internet 150 in FIG. 1) . The input/output devices or interfaces permit interaction with a user or other devices in the network. Each input/output device or interface includes any suitable structure for providing information to or receiving information from a user, and/or for network interface communications. Suitable structures include, for example, a speaker, microphone, keypad, keyboard, display, touch screen, etc.

The ED 110 includes the processor 210 for performing operations including those operations related to preparing a transmission for uplink transmission to the NT-TRP 172 and/or the T-TRP 170; those operations related to processing downlink transmissions received from the NT-TRP 172 and/or the T-TRP 170; and those operations related to processing sidelink transmission to and from another ED 110. Processing operations related to preparing a transmission for uplink transmission may include operations such as encoding, modulating, transmit beamforming, and generating symbols for transmission. Processing operations related to processing downlink transmissions may include operations such as receive beamforming, demodulating and decoding received symbols. Depending upon the embodiment, a downlink transmission may be received by the receiver 203, possibly using receive beamforming, and the processor 210 may extract signaling from the downlink transmission (e.g. by detecting and/or decoding the signaling) . An example of signaling may be a reference signal transmitted by the NT-TRP 172 and/or by the T-TRP 170. In some embodiments, the processor 210 implements the transmit beamforming and/or the receive beamforming based on the indication of beam direction, e.g. beam angle information (BAI) , received from the T-TRP 170. In some embodiments, the processor 210 may perform operations relating to network access (e.g. initial access) and/or downlink synchronization, such as operations relating to detecting a synchronization sequence, decoding and obtaining the system information, etc. In some embodiments, the processor 210 may perform channel estimation, e.g. using a reference signal received from the NT-TRP 172 and/or from the T-TRP 170.

Although not illustrated, the processor 210 may form part of the transmitter 201 and/or part of the receiver 203. Although not illustrated, the memory 208 may form part of the processor 210.

The processor 210, the processing components of the transmitter 201, and the processing components of the receiver 203 may each be implemented by the same or different one or more processors that are configured to execute instructions stored in a memory (e.g. in the memory 208) . Alternatively, some or all of the processor 210, the processing components of the transmitter 201, and the processing components of the receiver 203 may each be implemented using dedicated circuitry, such as a programmed field-programmable gate array (FPGA) , an application-specific integrated circuit (ASIC) , or a hardware accelerator such as a graphics processing unit (GPU) or an artificial intelligence (AI) accelerator.

The T-TRP 170 may be known by other names in some implementations, such as a base station, a base transceiver station (BTS) , a radio base station, a network node, a network device, a device on the network side, a transmit/receive node, a Node B, an evolved NodeB (eNodeB or eNB) , a Home eNodeB, a next Generation NodeB (gNB) , a transmission point (TP) , a site controller, an access point (AP) , a wireless router, a relay station, a terrestrial node, a terrestrial network device, a terrestrial base station, a base band unit (BBU) , a remote radio unit (RRU) , an active antenna unit (AAU) , a remote radio head (RRH) , a central unit (CU) , a distributed unit (DU) , a positioning node, among other possibilities. The T-TRP 170 may be a macro BS, a pico BS, a relay node, a donor node, or the like, or combinations thereof. The T-TRP 170 may refer to the forgoing devices or refer to apparatus (e.g. a communication module, a modem, or a chip) in the forgoing devices.

In some embodiments, the parts of the T-TRP 170 may be distributed. For example, some of the modules of the T-TRP 170 may be located remote from the equipment that houses the antennas 256 for the T-TRP 170, and may be coupled to the equipment that houses the antennas 256 over a communication link (not shown) sometimes known as front haul, such as common public radio interface (CPRI) . Therefore, in some embodiments, the term T-TRP 170 may also refer to modules on the network side that perform processing operations, such as determining the location of the ED 110, resource allocation (scheduling) , message generation, and encoding/decoding, and that are not necessarily part of the equipment that houses the antennas 256 of the T-TRP 170. The modules may also be coupled to other T-TRPs. In some embodiments, the T-TRP 170 may actually be a plurality of T-TRPs that are operating together to serve the ED 110, e.g. through the use of coordinated multipoint transmissions.

The T-TRP 170 includes at least one transmitter 252 and at least one receiver 254 coupled to one or more antennas 256. Only one antenna 256 is illustrated to avoid congestion in the drawing. One, some, or all of the antennas 256 may alternatively be panels. The transmitter 252 and the receiver 254 may be integrated as a transceiver. The T-TRP 170 further includes a processor 260 for performing operations including those related to: preparing a transmission for downlink transmission to the ED 110, processing an uplink transmission received from the ED 110, preparing a transmission for backhaul transmission to the NT-TRP 172, and processing a transmission received over backhaul from the NT-TRP 172. Processing operations related to preparing a transmission for downlink or backhaul transmission may include operations such as encoding, modulating, precoding (e.g. multiple input multiple output (MIMO) precoding) , transmit beamforming, and generating symbols for transmission. Processing operations related to processing received transmissions in the uplink or over backhaul may include operations such as receive beamforming, demodulating received symbols, and decoding received symbols. The processor 260 may also perform operations relating to network access (e.g. initial access) and/or downlink synchronization, such as generating the content of synchronization signal blocks (SSBs) , generating the system information, etc. In some embodiments, the processor 260 also generates an indication of beam direction, e.g. BAI, which may be scheduled for transmission by a scheduler 253. The processor 260 performs other network-side processing operations described herein, such as determining the location of the ED 110, determining where to deploy the NT-TRP 172, etc. In some embodiments, the processor 260 may generate signaling, e.g. to configure one or more parameters of the ED 110 and/or one or more parameters of the NT-TRP 172. Any signaling generated by the processor 260 is sent by the transmitter 252. Note that “signaling” , as used herein, may alternatively be called control signaling. Signaling may be transmitted in a physical layer control channel, e.g. a physical downlink control channel (PDCCH) , in which case the signaling may be known as dynamic signaling. Signaling transmitted in a downlink physical layer control channel may be known as Downlink Control Information (DCI) . Siganling transmitted in an uplink physical layer control channel may be known as Uplink Control Information (UCI) . Signaling transmitted in a sidelink physical layer control channel may be known as Sidelink Control Information (SCI) . Signaling may be included in a higher-layer (e.g., higher than physical layer) packet transmitted in a physical layer data channel, e.g. in a physical downlink shared channel (PDSCH) , in which case the signaling may be known as higher-layer signaling, static signaling, or semi-static signaling. Higher-layer signaling may also refer to Radio Resource Control (RRC) protocol signaling or Media Access Control –Control Element (MAC-CE) signaling.

The scheduler 253 may be coupled to the processor 260. The scheduler 253 may be included within or operated separately from the T-TRP 170. The scheduler 253 may schedule uplink, downlink, sidelink, and/or backhaul transmissions, including issuing scheduling grants and/or configuring scheduling-free (e.g., “configured grant” ) resources. The T-TRP 170 further includes a memory 258 for storing information and data. The memory 258 stores instructions and data used, generated, or collected by the T-TRP 170. For example, the memory 258 could store software instructions or modules configured to implement some or all of the functionality and/or embodiments described herein and that are executed by the processor 260.

Although not illustrated, the processor 260 may form part of the transmitter 252 and/or part of the receiver 254. Also, although not illustrated, the processor 260 may implement the scheduler 253. Although not illustrated, the memory 258 may form part of the processor 260.

The processor 260, the scheduler 253, the processing components of the transmitter 252, and the processing components of the receiver 254 may each be implemented by the same or different one or more processors that are configured to execute instructions stored in a memory, e.g. in the memory 258. Alternatively, some or all of the processor 260, the scheduler 253, the processing components of the transmitter 252, and the processing components of the receiver 254 may be implemented using dedicated circuitry, such as a programmed FPGA, a hardware accelerator (e.g., a GPU or AI accelerator) , or an ASIC.

Although the NT-TRP 172 is illustrated as a drone only as an example, the NT-TRP 172 may be implemented in any suitable non-terrestrial form, such as satellites and high altitude platforms, including international mobile telecommunication base stations and unmanned aerial vehicles, for example. Also, the NT-TRP 172 may be known by other names in some implementations, such as a non-terrestrial node, a non-terrestrial network device, or a non-terrestrial base station. The NT-TRP 172 includes a transmitter 272 and a receiver 274 coupled to one or more antennas 280. Only one antenna 280 is illustrated to avoid congestion in the drawing. One, some, or all of the antennas may alternatively be panels. The transmitter 272 and the receiver 274 may be integrated as a transceiver. The NT-TRP 172 further includes a processor 276 for performing operations including those related to: preparing a transmission for downlink transmission to the ED 110, processing an uplink transmission received from the ED 110, preparing a transmission for backhaul transmission to T-TRP 170, and processing a transmission received over backhaul from the T-TRP 170. Processing operations related to preparing a transmission for downlink or backhaul transmission may include operations such as encoding, modulating, precoding (e.g. MIMO precoding) , transmit beamforming, and generating symbols for transmission. Processing operations related to processing received transmissions in the uplink or over backhaul may include operations such as receive beamforming, demodulating received symbols, and decoding received symbols. In some embodiments, the processor 276 implements the transmit beamforming and/or receive beamforming based on beam direction information (e.g. BAI) received from the T-TRP 170. In some embodiments, the processor 276 may generate signaling, e.g. to configure one or more parameters of the ED 110. In some embodiments, the NT-TRP 172 implements physical layer processing, but does not implement higher layer functions such as functions at the medium access control (MAC) or radio link control (RLC) layer. As this is only an example, more generally, the NT-TRP 172 may implement higher layer functions in addition to physical layer processing.

The NT-TRP 172 further includes a memory 278 for storing information and data. Although not illustrated, the processor 276 may form part of the transmitter 272 and/or part of the receiver 274. Although not illustrated, the memory 278 may form part of the processor 276.

The processor 276, the processing components of the transmitter 272, and the processing components of the receiver 274 may each be implemented by the same or different one or more processors that are configured to execute instructions stored in a memory, e.g. in the memory 278. Alternatively, some or all of the processor 276, the processing components of the transmitter 272, and the processing components of the receiver 274 may be implemented using dedicated circuitry, such as a programmed FPGA, a hardware accelerator (e.g., a GPU or AI accelerator) , or an ASIC. In some embodiments, the NT-TRP 172 may actually be a plurality of NT-TRPs that are operating together to serve the ED 110, e.g. through coordinated multipoint transmissions.

The T-TRP 170, the NT-TRP 172, and/or the ED 110 may include other components, but these have been omitted for the sake of clarity.

One or more steps of the embodiment methods provided herein may be performed by corresponding units or modules, according to FIG. 4. FIG. 4 illustrates units or modules in a device, such as in the ED 110, in the T-TRP 170, or in the NT-TRP 172. For example, a signal may be transmitted or output by a transmitting unit or by a transmitting module. A signal may be received or input by a receiving unit or by a receiving module. A signal may be processed by a processing unit or a processing module. Other steps may be performed by an artificial intelligence (AI) or machine learning (ML) module. The respective units or modules may be implemented using hardware, one or more components or devices that execute software, or a combination thereof. For instance, one or more of the units or modules may be a circuit such as an integrated circuit. Examples of an integrated circuit includes a programmed FPGA, a GPU, or an ASIC. For instance, one or more of the units or modules may be logical such as a logical function performed by a circuit, by a portion of an integrated circuit, or by software instructions executed by a processor. It will be appreciated that where the modules are implemented using software for execution by a processor for example, the modules may be retrieved by a processor, in whole or part as needed, individually or together for processing, in single or multiple instances, and that the modules themselves may include instructions for further deployment and instantiation.

While not shown, the transmitting module and the receiving module may be part of, or combined into, a transceiver module. A transceiver module may also be known as an interface module, or simply an interface, for inputting and outputting operations.

Additional details regarding the EDs 110, the T-TRP 170, and the NT-TRP 172 are known to those of skill in the art. As such, these details are omitted here.

The details of the present disclosure will be elaborated in the following description.

The channel coding module in communications systems encode K source bits into N code bits to provide error correction capability against adversary channel conditions such as noise and interference. The code rate is R=K/N. In practice, the code rate R is selected according to channel quality.

Polar codes are capacity-achieving codes and thus a great breakthrough in coding theory. As code length approaches infinity, the synthesized channels (also known as subchannels, which are created by or associated with the polar code) become either noiseless or pure noise. The noiseless subchannels are utilized to transport information, and their proportion is proven to achieve the channel capacity defined by Shannon. The above-mentioned channel polarization phenomenon occurs under successive cancellation (SC) or SC-based decoding, which has a relatively low complexity.

Rate matching is performed after channel encoding, by either puncturing/shortening or repeating some code bits. The purpose of this operation is to obtain a code bit sequence of desired length for transmission over limited channel resources.

Channel interleaving is applied after channel encoding and rate matching by permuting the code bits. The purpose is to provide stable or superior performance under high-order modulation or in a fading channel.

Hybrid automatic repeat request (HARQ) is a mechanism to provide reliable wireless transmission. It combines forward error correction (FEC) and automatic repeat request (ARQ) . In HARQ, the initial transmission is a FEC code word with means (such as CRC bits) to support error detection at the receiver. If a decoding error is detected, the receiver will send back a negative acknowledgment (NACK) signaling to inform the transmitter of the error, and request a retransmission. The retransmitted bits can be directly selected from the initially transmitted bits, or incrementally generated code bits which form a longer code word with the initially transmitted bits. The former approach is called chase-combining HARQ (CC-HARQ) and the latter approach is called incremental-redundancy HARQ (IR-HARQ) . Typically, IR-HARQ outperforms CC-HARQ with the additional coding gain from incremental redundancy.

Polar codes belong to the class of linear block codes. For a polar code of length N, its generator matrix is GN, and its encoding process iswhereis the binary information vector, is the binary code vector. The N×N binary matrixwhereis the polarization kernel matrix, n=log₂ N, and is Kronecker product.

Typically, there are K information bits to be encoded into N code bits. Accordingly, the inequality K<N is given to obtain a code rate R=K/N<1. That implies only part ofis used to carry information bits, and the rest are typically called frozen bits. Denote by I the information bit set (or information set) , and F the frozen bit set (or frozen set) , respectively. Sometimes, there is an additional PC bit set, denoted by P. The frozen bits are known (usually all zeros, but may also be other known values or sequences) before decoding, so they do not carry any payload information. The PC bits are parity-check bits generated from a subset of information bits. Therefore, the PC bits are known once the associated information bits are decoded. The decoding of polar codes attempts to recover all information bits.

The transmitted code length M may not always be the power of 2, i.e., M<N. In practice, puncturing and shortening are used to reduce transmitted code bits from N to M. For convenience, the present disclosure hereinafter refers to N as the mother code length, and M as the code length. In particular, punctured bits are non-transmitted bits unknown to the decoder, but shortened bits are non-transmitted bits known to the decoder (usually all zeros) .

FIG. 5 is an example trellis graph of polar code according to one or more example embodiments of the present disclosure, where a mother code length N=8, source bit length K=4. Each “butterfly” in the graph represents a polarization, i.e., In this example, the information set is I= {u₄, u₆, u₇, u₈} , and the frozen set is F= {u₁, u₂, u₃, u₅} .

Successive cancellation (SC) is the basic decoding algorithm for polar codes, where all the frozen bits and information bits are decoded sequentially, i.e., bit by bit. The preceding bits are typically always decoded first.

Successive cancellation list (SCL) is an enhanced decoding algorithm for polar codes, where multiple (e.g., a number L) SC decoding instances are executed. Each instance is called a “decoding path” . When decoding each binary bit, both “0” and “1” branches are extended to each path, creating 2L paths. Then, all 2L paths are compared, where the most likely L paths are kept, and the least likely L paths are discarded (or pruned) . These path extension and pruning operations are performed during decoding of every information bit, until all information bits are decoded. At last, the most likely path is selected as the decoding output.

CRC-aided successive cancellation list (CA-SCL) works almost the same as SCL, except that in the last step, the most likely path that passes CRC check is selected as the decoding output.

Parity-check successive cancellation list (PC-SCL) works almost the same as SCL, except that when decoding parity-check (PC) bits, the parity check value of associated preceding bits is used as the bit decision result. PC bits may be considered a type of bit in addition to frozen bits and information bits.

Rate-compatible polar coding is a desirable technology for wireless applications. In one example of polar code rate matching, a combination of puncturing, shortening and repetition is used together with a fixed reliability sequence to balance performance and complexity. In particular, subblock-wise interlacing and interleaving is used for both puncturing and shortening. The puncturing and shortening patterns are symmetric.

With mother code length N, and code length M, the specific rate matching scheme used is

● Repetition, when M>N;

● Puncturing, when K/M≤7/16;

● Shortening, when K/M>7/16;

A subblock-wise interleaving is performed before puncturing and shortening. The interleaver partitions the length-N mother code into 32 subblocks of size N/32 and interlaces them. FIG. 6 is a schematic illustration of an example interleaver scheme according to one or more example embodiments of the present disclosure, where the table is sub-block interleaver pattern p (i) and is reproduced from a 3GPP standard specification.

Since puncturing is performed from the 1^st code bit, and shortening is performed from the last code bit, the rate matching module is efficiently implemented through a cyclic buffer. All mother code bits are placed in the cyclic buffer, and puncturing is done by selecting the bits in clockwise order, and shortening is done by selecting bits in counter-clockwise order. FIG. 7 is a schematic illustration of an example polar code rate matching according to one or more example embodiments of the present disclosure, which illustrates the cyclic buffer.

Another polar code rate matching example involves an incremental freezing HARQ method, where transmissions of multiple short code words are supported. As more short codes are transmitted, the overall code length increases, and the overall code rate decreases.

1. In the first transmission, an (M₁, K) polar code is constructed, encoded and transmitted. The code rate is R₁=K/M₁. Usually, the code rate is determined such that R₁<C₁, where C₁ is the channel capacity of the first transmission. But in the case of faded channel or inaccurate channel estimation, there may be inequality R₁>C₁, and decoding will fail and a second transmission is required.

2. In the second transmission, K₂ least reliable information bits are selected from the K information bits in the first transmission. In practice, K₂ is chosen according to the estimated channel capacity of the second transmission. An (M₂, K₂) polar code is constructed accordingly and encoded and transmitted. However, if R₂>C₂, and decoding will fail again and a third transmission is required.

3. The third and fourth transmissions are constructed similarly, and so on.

At the receiver side, the decoder should always decode the last received code word, because it has the lowest code rate and thus the best chance of successful decoding. After the last transmission is correctly decoded, the corresponding information bits in all previous transmissions become known, and can be decoded as frozen bits with known values. This process is repeated as more code words are decoded, until all K bits in the first transmission is decoded. The term “incremental freezing” refers to the operations to additionally freeze some information bits in the previous transmissions once a later transmitted code word is decoded.

FIG. 8 is a schematic illustration of an example polar HARQ according to one or more example embodiments of the present disclosure, where M₁=M₂=M₃=M₄=16, and K₁=12, K₂=6, K₃=4, K₄=3.

Parity-check (PC) polar codes may be used to improve minimum distance of polar codes. PC polar codes may also be used to support IR-HARQ. In the latter case, the PC bits are used to couple multiple retransmissions into a longer polar code with extra coding gain.

The PC functions used for IR-HARQ may be considered a special case, where some information bits are copied from the initial transmitted code block to a retransmitted code block. This one-to-one parity checking between the two shorter code blocks effectively couples the two code blocks into a longer code block.

FIG. 9 is a schematic illustration of an example encoding process according to one or more example embodiments of the present disclosure, where, the initial transmission is a (M₁=8, K=5) polar code, where {u₀, u₁, u₂, u₃, u₄} is the information set, and {u₅, u₆, u₇} is the frozen set.

FIG. 10 is another schematic illustration of the example encoding process according to one or more example embodiments of the present disclosure. In the first retransmission, four additional code bits are transmitted. These four bits are coupled with the initially transmitted 8 bits to form a (M₂=12, K=5) polar code. The coupling is achieved by copying the value of u₄ to u₈ during encoding, thus generating a PC function u₄ + u₈ = 0 (or equivalently u₈ = u₄) . As said, the largest index in this PC function corresponds to the PC bit (here u₈) . During decoding, u₄ decoded as an information bit, while u₈ is decoded as a PC bit using u₈ = u₄. With {u₀, u₁, u₂, u₃, u₈} as the information set, {u₄} as the PC set, and {u₅, u₆, u₇, u₉, u₁₀, u₁₁} as the frozen set.

FIG. 11 is yet another schematic illustration of the example encoding process according to one or more example embodiments of the present disclosure. In the second retransmission, the remaining four bits c₁₂, c₁₃, c₁₄, c₁₅ are transmitted to form a (M₃=16, K=5) polar code. But this time no new PC bits are generated.

From the polar transform matrix point of view, the three transmissions with effective code lengths M₁=8, M₂=12, M₃=16.

Channel interleaving may provide a better and more stable performance when high-order modulation is applied, or when the transmitted signals go through a fading or interference channel. Bit interleaved coded modulation is an effective way to resolve these issues. Random interleavers are good in terms of performance, but these interleavers may not be convenient to implement in hardware. Therefore, interleavers with deterministic structures, but having similar performance to random interleavers, have greater practical application.

FIG. 12 is a schematic illustration of an example polar code scheme according to one or more example embodiments of the present disclosure, where the interleaver is a so-called triangular interleaver. The input sequence is row-by-row written into a triangular-shaped buffer, and then column-by-column read out. The un-written bit positions are marked as <null>, and are skipped when reading out.

In an example LDPC code scheme, a block interleaver (row-in-column-out) is used for interleaving. The input sequence is row-by-row written into a rectangular-shaped buffer, and then column-by-column read out. The number of rows equals the modulation order. The un-written bit positions are filled by zeros and are not skipped when reading out.

Both of these implementations of channel interleavers, however, may cause a bottleneck for high-throughput applications. In some particular examples:

● Both the triangular interleaver and the block interleaver require bit-by-bit serial operations, which can greatly limit their overall throughput.

● The triangular interleaver’s irregular shape introduces extra latency.

FIG. 13 is a schematic flowchart of a communication method according to one or more example embodiments of the present disclosure. The method can be implemented by a first apparatus such as a channel interleaver. Optionally, the channel interleaver could be integrated into an encoder (for example, a channel leaver module) and could also be other device that has similar function (for example, a chip) , which is not limited herein. As shown in FIG. 13, the method can include the following steps.

S1310, obtaining a first code bit sequence, where the first code bit sequence is obtained after rate matching a second code bit sequence;

In details, the second code bit sequence may be a mother code derived through channel encoding. After rate matching is performed on the second code bit sequence, the first code bit sequence could be obtained, which is a rate-matched bit sequence. The manner for channel encoding and rate matching are not limited herein.

S1320, dividing the first code bit sequence into blocks.

In details, in order to improve throughput, one approach is to replace the bit-by-bit operations with block-by-block operations having higher parallelism. For example, the first code bit sequence (the input sequence) with length E is divided into small blocks of length B with consecutive indices, e.g., [i, i+1, i+2, …, i+B-1] . Therefore, there aresuch blocks, where therepresents Ceiling.

S1330, channel interleaving the blocks according to a pre-defined order, where the channel interleaving is applied to the first code bit sequence before modulation and transmission to a channel.

In details, the blocks are interleaved according to a pre-defined order. For example, a blockwise interleaver sequence of lengthcan be used to interleave theblocks, where the pre-defined order could be stored in a table or indicated by a sequence. Alternatively, a simple rule also can be used to interleave theblocks. Specifically, the pre-defined order may be a reverse order of the blocks. For example, if the sequence is divided into blocks of b₁, b₂, b₃, b₄, then the pre-defined order could be b₄, b₃, b₂, b₁.

Moreover, after the first code bit sequence is divided into blocks, the order of bits in each of the blocks should not be changed before and after the interleaving, thereby the blockwise interleaving could be implemented. For example, the bits (sub-sequence) within each block are always written together or read together, but not separately. One property to guarantee this is: the relative ordering within a block remains unchanged before and after blockwise interleaving. For example, a small block of length B with consecutive indices, e.g., [i, i+1, i+2, …, i+B-1] , is interleaved to have new indices, e.g., [j, j+1, j+2, …, j+B-1] , in the interleaved sequence. Note that i and j need not be the same, but the ordering of the B bits is the same.

The above mentioned channel interleaving could be implemented by a channel interleaver. The channel interleaver could be independent of a modulation order or dependent of a modulation order. In other words, the dividing the first code bit sequence into blocks could be performed independent of or dependent of a modulation order. Moreover, although the modulation order could be quadrature amplitude modulation (QAM) , the other suitable modulation modes could also be adopted, which is not limited herein.

Taking the QAM as an example, a blockwise QAM-independent interleaver could be independent of the modulation order, where the interleaver, although having a deterministic structure, serves as a pseudo-random interleaver. Meanwhile, a blockwise QAM-dependent interleaver, which could also called as a blockwise QAM-specific interleaver, could be dependent of the modulation order. In other words, the interleaver comprises parameter (s) depending on the modulation order, thereby joint design is favored to optimize the interleaver given a specific modulation order.

Some embodiments of the present disclosure relate to a blockwise QAM-independent interleaver.

A blockwise QAM-independent interleaver can include one or more of the following features and procedures.

The interleaving steps are as follows.

i. the channel interleaver may divide the first code bit sequence into blocks independent of the modulation order. Specifically, divide the input sequence e₀, e₁, e₂, . . ., e_E-1 intoblocks. Ifthen fillzeros or <null> into the input sequence (e.g., attach to the beginning or the end, or uniformly interlaced the middle) . A block size B could be predefined in a protocol. B can be a power-of-2, e.g., B = 8, 16, 32, 64, 128, etc. The bigger values could provide higher parallelism, thus lead to higher encoding/decoding throughput. The smaller values could provide finer granularity, thus lead to better error correction performance. Moreover, we could use moderate numbers to strike a good balance. For example, in scenarios that do not require very high throughput, a smaller B could be used, but in extremely high-throughput scenarios, a larger B could be used. Furthermore, B can also be a prime number, e.g., B = 5, 7, 11, 13, 17, 19, etc. In addition to the above advantage, using prime numbers could further lead to more random interleaving, and in some cases could enhance performance.

ii. the channel interleaver may write the blocks block-by-block into a buffer of a given shape according to the predefined order. Specifically, write the input sequence block-by-block into a buffer of a given shape, according to a predefined orderThe shape can be a square, a rectangle, a triangle, or a trapezoid.

iii. the channel interleaver may read the blocks block-by-block from the buffer of the given shape according to a different predefined order to obtain an output sequence. Specifically, read the output sequence block-by-block from the buffer of the given shape, according to a different predefined orderIf the bit value to be read out is <null>, then this bit is skipped.

iv. the channel interleaver may sequentially feed the output sequence to a modulator, where consecutive bits in each of blocks of the output sequence are mapped to one symbol. Specifically, the output sequence is sequentially fed to the modulator, where consecutive bits are mapped to one QAM symbol.

An example blockwise QAM-independent interleaver may be described through a pseudocode example:

The rate matching output bit sequence, denoted by e₀, e₁, e₂, . . ., e_E-1, is interleaved into bit sequence f₀, f₁, f₂, . . ., f_E-1, as follows.

The input sequence is first divided into blocks of size and then interleaved by a blockwise row-in-column-out triangle interleaver of length 32.

If I_BIL=1 --the indicator for turning on bit interleaver

The value of E is no larger than 16384.

With the communication method provided by the present disclosure, an apparatus such as a channel interleaver could obtain a first code bit sequence, where the first code bit sequence is obtained after rate matching a second code bit sequence, divide the first code bit sequence into blocks, and channel interleave the blocks according to a pre-defined order, where the channel interleaving is applied to the first code bit sequence before modulation and transmission to a channel. Because the first code bit sequence could be divided into blocks for channel interleaving, the blockwise interleaving with higher parallelism could be implemented, and thus, the flexibility, simplicity, and higher throughput can be achieved while stable or superior performance could be provided under high-order modulation or in a fading channel.

FIG. 14 is a schematic illustration of an example procedure of blockwise QAM-independent interleaver according to one or more example embodiments of the present disclosure. Note that for rate matching output length E<1024, each block has 32 bits, in this case chosen to be a multiple of 8.

Some embodiments of the present disclosure relate to a blockwise QAM-specific interleaver and bit-to-symbol mapping rules.

A blockwise QAM-specific interleaver can include one or more of the following features and procedures.

The general interleaving steps are as follows.

i. the channel interleaver may determine the interleaver parameters. For example, determine a block size based on the modulation order, where the block size could be a divisor of the modulation order and a positive even integer. Specifically, block size B is a factor (or divisor) of the modulation order Q_m. For example, B=Q_m/m, where m is a positive even integer. The positive even integer may be a fixed value, and preferably, the positive even integer could be 2 4 6 8, or 10.

ii. the channel interleaver may divide the first code bit sequence into blocks dependent of the modulation order. Specifically, divide the input sequence e₀, e₁, e₂, . . ., e_E-1 intoblocks. Ifthen fill zeros or <null> into the input sequence (e.g., attach to the beginning or the end, or uniformly interlaced the middle) . The above step for dividing could be adapted to systematic codes and non-systematic codes. For example, for systematic codes (such as LDPC codes) , if a block includes systematic bits, it is called a systematic block; if a block includes parity bits, it is called a parity block. For non-systematic codes (such as polar codes) , if a block includes bits from the first half of the codeword, which could be the second code bit sequence as mentioned above, (with indices from [0, 1, 2, …, N/2] after polar encoding, where N is the mother code length) , it may be called a v-block (which is also called first block herein) ; if a block includes bits from the second half of the codeword (with indices from [N/2, N/2+1, …, N-1] after polar encoding, where N is the mother code length) , it may be called a u-block (which is also called second block herein) .

iii. The blocks may be grouped into multiple groups of blocks, and a number of blocks in each of the multiple groups is equal to the positive even integer. In other words, multiple blocks are grouped together. For example, theblocks are grouped intogroups, and each group includes m blocks, each of length B=Q_m/m, in which the m blocks within a group include both systematic block (s) and parity block (s) .

iv. the channel interleaver may interleave the blocks according to the pre-defined order. Specifically, the channel interleaver may write the blocks in each of the multiple groups block-by-block according to the predefined order, and the channel interleaver may enable each of multiple groups of blocks to be written block-by-block into a rectangle-shaped buffer row-by-row in either left-to-right order or right-to-left order, where a number of rows of the rectangle-shaped buffer is equal to the positive even integer. Then the channel interleaver may enable the blocks to be read block-by-block from the rectangle-shaped buffer column-by-column in either top-down order or bottom-up order so as to obtain an output sequence, where each of columns includes a respective group of multiple groups.

v. the channel interleaver may sequentially feed the output sequence to a modulator, where consecutive bits of each of the multiple groups of block are mapped to one modulated symbol. In other words, form QAM symbols from the groups, in which one QAM symbol is mapped from bits in only one group. For example, a QAM modulated symbol is mapped from Q_m bits. These Q_m bits all come from a group of m blocks, each of length B=Q_m/m.

Example mapping schemes are applicable for both systematic codes and non-systematic codes. For systematic codes (such as LDPC codes) , the bits in the systematic block (s) are mapped to the high-energy (or more reliable) bits; and the bits in the parity block (s) are mapped to the low-energy (or less reliable) bits. For non-systematic codes (such as polar codes) , the bits in the u-block (s) are mapped to the high-energy (or more reliable) bits; and the bits in the v-block (s) are mapped to the low-energy (or less reliable) bits.

An explicit implementation of the systematic codes includes the following steps:

i. the channel interleaver may determine the interleaver parameters dependent of the modulation order. The interleaver parameter could be block size B, and block size B is a factor (or divisor) of the modulation order Q_m. For example, B=Q_m/m, where m is a positive even integer.

ii. the channel interleaver may divide the first code bit sequence into systematic blocks and parity blocks for systematic code, where the systematic blocks are blocks including systematic bits, and the parity blocks are blocks including parity bits. Specifically, divide the input sequence e₀, e₁, e₂, . . ., e_E-1 intoblocks. If then fillzeros or <null> into the input sequence (e.g., attach to the beginning or the end, or uniformly interlaced the middle) . If a block includes systematic bits, it is called a systematic block; if a block includes parity bits, it is called a parity block. Furthermore, multiple blocks are grouped into multiple groups. For example, a group includes m blocks, each of length B=Q_m/m. Specifically, for the systematic code, the systematic blocks and the parity blocks could be grouped into multiple groups of blocks, where each of multiple groups includes at least one systematic block and at least one parity block.

iii. the channel interleaver may enable the systematic blocks to be written row-by-row in left-to-right order and the parity blocks to be written row-by-row in right-to-left order, or the systematic blocks to be written row-by-row in right-to-left order and the parity blocks to be written row-by-row in left-to-right order, or the systematic blocks and the parity blocks to be written in zigzag order. For example, write the input sequence block-by-block into a rectangle-shaped buffer of m rows:

1. The blocks are row-by-row written in either left-to-right order, or right-to-left order;

2. Optionally, systematic blocks are written in row-by-row in left-to-right order (or right-to-left order) ; parity blocks are written in row-by-row in right-to-left order (or left-to-right order) ;

3. Optionally, the blocks are row-by-row written in zigzag order, which means if the current row is written in left-to-right order, then the next row will be written in right-to-left order, and vice versa.

iv. the channel interleaver may enable the systematic blocks to be read column-by-column in top-down order and the parity blocks to be read column-by-column in bottom-up order, or the systematic blocks to be read column-by-column in bottom-up order and the parity blocks to be read column-by-column in top-down order, or the systematic blocks and the parity blocks to be read in zigzag order. For example, read the output sequence block-by-block from the rectangle-shaped buffer of m rows:

1. The blocks are column-by-column read out in either top-down order, or bottom-up order; Each column includes m blocks, thus is also a group defined earlier;

2. Optionally, systematic blocks are column-by-column read out in either top-down order (or bottom-up order) ; parity blocks are w column-by-column read out in bottom-up order (or top-down order) ;

3. Optionally, the blocks are column-by-column read out zigzag order, which means if the current column is read out top-down order, then the next row will be read out in bottom-up order, and vice versa.

v. the channel interleaver may sequentially feed the output sequence to a modulator, where consecutive bits of each of the multiple groups of block are mapped to one modulated symbol. For example, the output sequence is sequentially fed to the modulator, where consecutive Q_m bits (which is a group, or a column) are mapped to one QAM symbol. In other words, a QAM modulated symbol is mapped from Q_m bits, where these Q_m bits all come from a group of m blocks, each of length B=Q_m/m. Furthermore, the consecutive bits in the at least one systematic block in each of multiple groups of blocks could be mapped to high-energy bits, and consecutive bits in the at least one parity block in each of multiple groups of blocks could be mapped to low-energy bits. In short, the bits in the systematic block (s) are mapped to the high-energy (or more reliable) bits; and the bits in the parity block (s) are mapped to the low-energy (or less reliable) bits.

Another explicit implementation of the non-systematic codes includes the following steps:

ii. the channel interleaver may divide the first code bit sequence into first blocks and second blocks for non-systematic code, where the first blocks includes bits from a first half of the second code bit sequence and the second blocks includes bits from a second half of the second code bit sequence. Specifically, divide the input sequence e₀, e₁, e₂, . . ., e_E-1 intoblocks. Ifthen fillzeros or <null> into the input sequence (e.g., attach to the beginning or the end, or uniformly interlaced the middle) . If a block includes bits from the first half of the codeword (with indices from [0, 1, 2, …, N/2] after polar encoding, where N is the mother code length) , it is called a v-block; if a block includes bits from the second half of the codeword (with indices from [N/2, N/2+1, …, N-1] after polar encoding, where N is the mother code length) , it is called a u-block. Furthermore, multiple blocks are grouped into multiple groups. For example, a group includes m blocks, each of length B=Q_m/m. Specifically, for the non-systematic code, the first blocks and the second blocks could be grouped into multiple groups of blocks.

iii. the channel interleaver may enable the first blocks to be written row-by-row in left-to-right order and the second blocks to be written row-by-row in right-to-left order, or the first blocks to be written row-by-row in right-to-left order and the second blocks to be written row-by-row in left-to-right order, or the first blocks and the second blocks to be written row-by-row in zigzag order For example, write the input sequence block-by-block into a rectangle-shaped buffer of m rows:

2. Optionally, v-blocks are written in row-by-row in left-to-right order (or right-to-left order) ; u-blocks are written in row-by-row in right-to-left order (or left-to-right order) ;

iv. the channel interleaver may enable the first blocks to be read column-by-column in top-down order and the second blocks to be read column-by-column in bottom-up order, or the first blocks to be read column-by-column in bottom-up order and the second blocks are read column-by-column in top-down order, or the first blocks and the second blocks to be read column-by-column in zigzag order. For example, read the output sequence block-by-block from the rectangle-shaped buffer of m rows:

2. Optionally, v-blocks are column-by-column read out in either top-down order (or bottom-up order) ; u-blocks are w column-by-column read out in bottom-up order (or top-down order) ;

v. the channel interleaver may sequentially feed the output sequence to a modulator, where consecutive bits of each of the multiple groups of block are mapped to one modulated symbol. For example, the output sequence is sequentially fed to the modulator, where consecutive Q_m bits (which is a group, or a column) are mapped to one QAM symbol. In other words, a QAM modulated symbol is mapped from Q_m bits, where these Q_m bits all come from a group of m blocks, each of length B=Q_m/m. Furthermore, the consecutive bits in the at least one first block in each of multiple groups of blocks are mapped to high-energy bits, and consecutive bits in the at least one second block in each of multiple groups of blocks are mapped to low-energy bits. In short, the bits in the u-block (s) are mapped to the high-energy (or more reliable) bits; and the bits in the v-block (s) are mapped to the low-energy (or less reliable) bits.

An example blockwise QAM-specific interleaver may be described through a pseudocode example:

The rate matching output bit sequence, denoted by e₀, e₁, e₂, . . ., e_E-1, is interleaved into bit sequence f₀, f₁, f₂, . . ., f_E-1, as follows, where the value Q_m is the modulation order and E is a multiple of Q_m. The input sequence is first divided into blocks of size Q_m/Z, where Z=2 is a parameter that can be divided by Q_m, and then interleaved by a blockwise row-in-column-out block interleaver.

The value of E is no larger than 32768.

FIG. 15 is a schematic illustration of an example procedure of blockwise QAM-dependent interleaver according to one or more example embodiments of the present disclosure, where the example procedure may include: row-wise write and colum-wise &block-wise read out. According to FIG. 15, for example, there could be 8 groups, each of which includes 2 blocks.

With the communication method provided by the present disclosure, an apparatus such as a channel interleaver could obtain a first code bit sequence, where the first code bit sequence is obtained after rate matching a second code bit sequence, divide the first code bit sequence into blocks, where the blocks are grouped into multiple groups of blocks, and channel interleave the blocks according to a pre-defined order, where the channel interleaving is applied to the first code bit sequence before modulation and transmission to a channel. Because after the sequence is divided into blocks, the blocks are further grouped into multiple groups, the blockwise interleaving with higher parallelism could be implemented further based on group, and the code bits that will be mapped to one symbol could be grouped together, which could facilitate subsequent modulation and thus improve processing efficiency, thereby further improving the throughput of interleaver. Moreover, the blockwise QAM-independent interleaver could achieve the flexibility, simplicity, and higher throughput. Meanwhile, the blockwise QAM-specific interleaver with bit-to-symbol mapping rules could achieve the standard-friendly specification, improve coding gain, and further improve performance.

In summary, some embodiments of the present disclosure may enable advantageous effects such as:

● Blockwise write-in and read-out for higher parallelism, and thus higher throughput.

● Flexible configuration to support sequence-based and rule-based interleavers.

● For polar codes, QAM-specific mapping can increase polarization and thus improve performance.

FIG. 16 is a schematic flowchart of another communication method according to one or more example embodiments of the present disclosure. The method can be implemented by a second apparatus such as a decoder. Optionally, the decoder could be other device that has similar function (for example, a chip) , which is not limited herein. As shown in FIG. 16, the method can include the following steps.

S1610, receiving interleaved blocks of a first bit sequence, where the interleaved blocks of the first bit sequence is obtained by channel interleaving blocks of the first code bit sequence, where the first code bit sequence is divided into the blocks and the first code bit sequence is obtained after rate matching a second code bit sequence; where the blocks are channel interleaved according to a pre-defined order, where the channel interleaving is applied to the first code bit sequence before modulation and transmission to a channel; and

S1620, decoding the encoded sequence to obtain decoded code bit sequence.

The solutions and effects for block-wise channel interleaving the first code bit sequence block in S1610 is similar as that described above, which is not repeated herein for short.

As shown in FIG. 17, the first apparatus 1700 includes: an interface 1710 for obtaining a first code bit sequence, where the first code bit sequence is obtained after rate matching a second code bit sequence; a channel interleaver 1720 coupled to the interface 1710, for dividing the first code bit sequence into blocks; and channel interleaving the blocks according to a pre-defined order, where the channel interleaving is applied to the first code bit sequence before modulation and transmission to a channel.

In a possible implementation, the pre-defined order is stored in a table or indicated by a sequence.

In a possible implementation, the pre-defined order is a reverse order of the blocks.

In a possible implementation, the order of bits in each of the blocks is unchanged before and after the interleaving.

In a possible implementation, where the dividing the first code bit sequence into blocks is performed independent of a modulation order.

In a possible implementation, block size is predefined in a protocol.

In a possible implementation, a block size is a power-of-2 number.

In a possible implementation, the block size is 8, 16, 32, 64, or 128.

In a possible implementation, a block size is a prime number.

In a possible implementation, the block size is 5, 7, 11, 13, 17, or 19.

In a possible implementation, where the channel interleaver 1720 is further for: writing the blocks block-by-block into a buffer of a given shape according to the predefined order; and reading the blocks block-by-block from the buffer of the given shape according to a different predefined order to obtain an output sequence.

In a possible implementation, the given shape is a square, a rectangle, a triangle, or a trapezoid.

In a possible implementation, the channel interleaver 1720 is further for: sequentially feeding the output sequence to a modulator, where consecutive bits in each of blocks of the output sequence are mapped to one symbol.

In a possible implementation, the dividing the first code bit sequence into blocks is performed dependent of a modulation order.

In a possible implementation, the channel interleaver 1720 is further for: determining a block size based on the modulation order.

In a possible implementation, the block size is a divisor of the modulation order and a positive even integer.

In a possible implementation, the positive even integer is a fixed value.

In a possible implementation, the positive even integer is 2 4 6 8, or 10.

In a possible implementation, the blocks are grouped into multiple groups of blocks, and a number of blocks in each of the multiple groups is equal to the positive even integer.

In a possible implementation, the channel interleaver 1720 is further for: writing the blocks in each of the multiple groups block-by-block according to the predefined order.

In a possible implementation, each of multiple groups of blocks is written block-by-block into a rectangle-shaped buffer row-by-row in either left-to-right order or right-to-left order, where a number of rows of the rectangle-shaped buffer is equal to the positive even integer; and the blocks are read block-by-block from the rectangle-shaped buffer column-by-column in either top-down order or bottom-up order to obtain an output sequence, where each of columns includes a respective group of multiple groups.

In a possible implementation, the channel interleaver 1720 is further for: sequentially feeding an output sequence to a modulator, where consecutive bits of each of the multiple groups of block are mapped to one modulated symbol.

In a possible implementation, the channel interleaver 1720 is further for: dividing the first code bit sequence into systematic blocks and parity blocks for systematic code, where the systematic blocks are blocks including systematic bits, and the parity blocks are blocks including parity bits.

In a possible implementation, the systematic blocks and the parity blocks for the systematic code are grouped into multiple groups of blocks, where each of multiple groups includes at least one systematic block and at least one parity block.

In a possible implementation, the systematic blocks are written row-by-row in left-to-right order and the parity blocks are written row-by-row in right-to-left order, or the systematic blocks are written row-by-row in right-to-left order and the parity blocks are written row-by-row in left-to-right order, or the systematic blocks and the parity blocks are written in zigzag order.

In a possible implementation, the systematic blocks are read column-by-column in top-down order and the parity blocks are read column-by-column in bottom-up order, or the systematic blocks are read column-by-column in bottom-up order and the parity blocks are read column-by-column in top-down order, or the systematic blocks and the parity blocks are read in zigzag order.

In a possible implementation, consecutive bits in the at least one systematic block in each of multiple groups of blocks are mapped to high-energy bits, and consecutive bits in the at least one parity block in each of multiple groups of blocks are mapped to low-energy bits.

In a possible implementation, the channel interleaver 1720 is further for: dividing the first code bit sequence into first blocks and second blocks for non-systematic code, where the first blocks includes bits from a first half of the second code bit sequence and the second blocks includes bits from a second half of the second code bit sequence.

In a possible implementation, the first blocks and the second blocks for the non-systematic code are grouped into multiple groups of blocks.

In a possible implementation, the first blocks are written row-by-row in left-to-right order and the second blocks are written row-by-row in right-to-left order, or the first blocks are written row-by-row in right-to-left order and the second blocks are written row-by-row in left-to-right order, or the first blocks and the second blocks are written row-by-row in zigzag order.

In a possible implementation, the first blocks are read column-by-column in top-down order and the second blocks are read column-by-column in bottom-up order, or the first blocks are read column-by-column in bottom-up order and the second blocks are read column-by-column in top-down order, or the first blocks and the second blocks are read column-by-column in zigzag order.

In a possible implementation, consecutive bits in the at least one first block in each of multiple groups of blocks are mapped to high-energy bits, and consecutive bits in the at least one second block in each of multiple groups of blocks are mapped to low-energy bits.

In a possible implementation, the modulation mode is QAM.

The first apparatus may be applied to the above first apparatus such as the channel interleaver as described in the above possible method implementations. It should be understood by a person skilled in the art that, the relevant description of the above modules in these possible implementations of the present disclosure may be understood with reference to the relevant description of the inverleaving communication method in these possible implementations of the present disclosure. The technical effect achieved by the above first apparatus is similar as that achieved by the above possible method implementation, which is not repeated herein.

As shown in FIG. 18, the second apparatus 1800 includes an interface 1810 for obtaining blocks of encoded sequence by channel interleaving first code bit sequence, where the first code bit sequence is divided into the blocks and the first code bit sequence is obtained after rate matching a second code bit sequence; where the blocks are channel interleaved according to a pre-defined order, where the channel interleaving is applied to the first code bit sequence before modulation and transmission to a channel; and a decoder 1820 for the encoded sequence to obtain decoded code bit sequence.

In a possible implementation, the first code bit sequence is divided into blocks independent of a modulation order.

In a possible implementation, a block size is predefined in a protocol.

In a possible implementation, a block size is a power-of-2 number.

In a possible implementation, the block size is 8, 16, 32, 64, or 128.

In a possible implementation, a block size is a prime number.

In a possible implementation, the block size is 5, 7, 11, 13, 17, or 19.

In a possible implementation, the blocks are interleaved by: writing the blocks block-by-block into a buffer of a given shape according to the predefined order; and reading the blocks block-by-block from the buffer of the given shape according to a different predefined order to obtain an output sequence.

In a possible implementation, the blocks are interleaved further by: sequentially feeding the output sequence to a modulator, where consecutive bits in each of blocks of the output sequence are mapped to one symbol.

In a possible implementation, the first code bit sequence is divided into blocks dependent of a modulation order.

In a possible implementation, a block size of block is determined based on the modulation order.

In a possible implementation, the positive even integer is a fixed value.

In a possible implementation, the positive even integer is 2 4 6 8, or 10.

In a possible implementation, the blocks are interleaved by: writing the blocks in each of the multiple groups block-by-block according to the predefined order.

In a possible implementation, the blocks are interleaved further by: sequentially feeding an output sequence to a modulator, where consecutive bits of each of the multiple groups of block are mapped to one modulated symbol.

In a possible implementation, the first code bit sequence is divided into blocks by: dividing the first code bit sequence into systematic blocks and parity blocks for systematic code, where the systematic blocks are blocks including systematic bits, and the parity blocks are blocks including parity bits.

In a possible implementation, the first code bit sequence is divided into blocks by: dividing the first code bit sequence into first blocks and second blocks for non-systematic code, where the first blocks includes bits from a first half of the second code bit sequence and the second blocks includes bits from a second half of the second code bit sequence.

In a possible implementation, the modulation mode is quadrature amplitude modulation QAM.

The second apparatus may be applied to the above second apparatus such as the decoder as described in the above possible method implementations. It should be understood by a person skilled in the art that, the relevant description of the above modules in these possible implementations of the present disclosure may be understood with reference to the relevant description of the inverleaving communication method in these possible implementations of the present disclosure. The technical effect achieved by the above second apparatus is similar as that achieved by the above possible method implementation, which is not repeated herein.

A possible implementation of the present disclosure provides a third apparatus including a processor configured to cause the third apparatus to perform the method according to any of the above communication method at the first apparatus side. The above method is not repeated herein.

A possible implementation of the present disclosure provides a fourth apparatus including a processor configured to cause the fourth apparatus to perform the method according to any of the above communication method at the second apparatus side. The above method is not repeated herein.

A possible implementation of the present disclosure provides a computer program including programming for execution by a processor, the programming including instructions to perform the method according to any of the above communication method. The above method is not repeated herein.

A possible implementation of the present disclosure provides anon-transitory computer readable medium storing programming for execution by a processor, the programming including instructions to perform the method according to any of the above communication method. The above method is not repeated herein.

A possible implementation of the present disclosure provides a system including: a first communication device configured to perform the method according to any of the above communication method at the first apparatus side; and a second communication device configured to perform the method according to any of the above communication method at the second apparatus side. The above method is not repeated herein.

Acronyms, Abbreviations, and Initialisms

The present disclosure encompasses various embodiments, including not only method embodiments, but also other embodiments such as apparatus embodiments and embodiments related to non-transitory computer readable storage media. Embodiments may incorporate, individually or in combinations, the features disclosed herein.

Although this disclosure refers to illustrative embodiments, this is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the disclosure, will be apparent to persons skilled in the art upon reference to the description.

Features disclosed herein in the context of any particular embodiments may also or instead be implemented in other embodiments. Method embodiments, for example, may also or instead be implemented in apparatus, system, and/or computer program product embodiments. In addition, although embodiments are described primarily in the context of methods and apparatus, other implementations are also contemplated, as instructions stored on one or more non-transitory computer-readable media, for example. Such media could store programming or instructions to perform any of various methods consistent with the present disclosure.

Claims

A communication method, comprising:

obtaining a first code bit sequence, wherein the first code bit sequence is obtained after rate matching a second code bit sequence;

dividing the first code bit sequence into blocks; and

channel interleaving the blocks according to a pre-defined order, wherein the channel interleaving is applied to the first code bit sequence before modulation and transmission to a channel.
The method according to claim 1, wherein the pre-defined order is stored in a table or indicated by a sequence.
The method according to claim 1 or 2, wherein the pre-defined order is a reverse order of the blocks.
The method according to any one of claims 1 to 3, wherein the order of bits in each of the blocks is unchanged before and after the interleaving.
The method according to any one of claims 1 to 4, wherein the dividing the first code bit sequence into blocks is performed independent of a modulation order.
The method according to claim 5, wherein a block size is predefined in a protocol.
The method according to claim 5 or 6, wherein a block size is a power-of-2 number.
The method according to claim 7, wherein the block size is 8, 16, 32, 64, or 128.
The method according to claim 5 or 6, wherein a block size is a prime number.
The method according to claim 9, wherein the block size is 5, 7, 11, 13, 17, or 19.
The method according to any one of claims 5 to 10, wherein the channel interleaving the blocks according to the pre-defined order comprises:

writing the blocks block-by-block into a buffer of a given shape according to the predefined order; and

reading the blocks block-by-block from the buffer of the given shape according to a different predefined order to obtain an output sequence.
The method according to claim 11, wherein the given shape is a square, a rectangle, a triangle, or a trapezoid.
The method according to claim 11 or 12, further comprising:

sequentially feeding the output sequence to a modulator, wherein consecutive bits in each of blocks of the output sequence are mapped to one symbol.
The method according to any one of claims 1 to 4, wherein the dividing the first code bit sequence into blocks is performed dependent of a modulation order.
The method according to claim 14, further comprising:

determining a block size based on the modulation order.
The method according to claim 15, wherein the block size is a divisor of the modulation order and a positive even integer.
The method according to claim 16, wherein the positive even integer is a fixed value.
The method according to claim 16 or 17, wherein the positive even integer is 2 4 6 8, or 10.
The method according to any one of claims 14 to 18, wherein the blocks are grouped into multiple groups of blocks, and a number of blocks in each of the multiple groups is equal to the positive even integer.
The method according to claim 19, wherein the channel interleaving the blocks according to the pre-defined order comprises:

writing the blocks in each of the multiple groups block-by-block according to the predefined order.
The method according to claim 20, wherein each of multiple groups of blocks is written block-by-block into a rectangle-shaped buffer row-by-row in either left-to-right order or right-to-left order, wherein a number of rows of the rectangle-shaped buffer is equal to the positive even integer; and

the blocks are read block-by-block from the rectangle-shaped buffer column-by-column in either top-down order or bottom-up order to obtain an output sequence, wherein each of columns comprises a respective group of multiple groups.
The method according to any one of claims 19 to 21, further comprising:

sequentially feeding an output sequence to a modulator, wherein consecutive bits of each of the multiple groups of block are mapped to one modulated symbol.
The method according to claim 21 or 22, wherein the dividing the first code bit sequence into blocks comprises:

dividing the first code bit sequence into systematic blocks and parity blocks for systematic code, wherein the systematic blocks are blocks comprising systematic bits, and the parity blocks are blocks comprising parity bits.
The method according to claim 23, wherein the systematic blocks and the parity blocks for the systematic code are grouped into multiple groups of blocks, wherein each of multiple groups comprises at least one systematic block and at least one parity block.
The method according to claim 24, wherein the systematic blocks are written row-by-row in left-to-right order and the parity blocks are written row-by-row in right-to-left order, or the systematic blocks are written row-by-row in right-to-left order and the parity blocks are written row-by-row in left-to-right order, or the systematic blocks and the parity blocks are written in zigzag order.
The method according to claim 25, wherein the systematic blocks are read column-by-column in top-down order and the parity blocks are read column-by-column in bottom-up order, or the systematic blocks are read column-by-column in bottom-up order and the parity blocks are read column-by-column in top-down order, or the systematic blocks and the parity blocks are read in zigzag order.
The method according to claim 26, wherein consecutive bits in the at least one systematic block in each of multiple groups of blocks are mapped to high-energy bits, and consecutive bits in the at least one parity block in each of multiple groups of blocks are mapped to low-energy bits.
The method according to claim 21 or 22, wherein the dividing the first code bit sequence into blocks comprises:

dividing the first code bit sequence into first blocks and second blocks for non-systematic code, wherein the first blocks comprises bits from a first half of the second code bit sequence and the second blocks comprises bits from a second half of the second code bit sequence.
The method according to claim 28, wherein the first blocks and the second blocks for the non-systematic code are grouped into multiple groups of blocks.
The method according to claim 29, wherein the first blocks are written row-by-row in left-to-right order and the second blocks are written row-by-row in right-to-left order, or the first blocks are written row-by-row in right-to-left order and the second blocks are written row-by-row in left-to-right order, or the first blocks and the second blocks are written row-by-row in zigzag order.
The method according to claim 30, wherein the first blocks are read column-by-column in top-down order and the second blocks are read column-by-column in bottom-up order, or the first blocks are read column-by-column in bottom-up order and the second blocks are read column-by-column in top-down order, or the first blocks and the second blocks are read column-by-column in zigzag order.
The method according to claim 31, wherein consecutive bits in the at least one first block in each of multiple groups of blocks are mapped to high-energy bits, and consecutive bits in the at least one second block in each of multiple groups of blocks are mapped to low-energy bits.
The method according to any one of claims 5 to 32, wherein the modulation mode is quadrature amplitude modulation (QAM) .
A communication method, comprising:

receiving interleaved blocks of a first bit sequence, wherein the interleaved blocks of the first bit sequence is obtained by channel interleaving blocks of the first code bit sequence, wherein the first code bit sequence is divided into the blocks and the first code bit sequence is obtained after rate matching a second code bit sequence; wherein the blocks are channel interleaved according to a pre-defined order, wherein the channel interleaving is applied to the first code bit sequence before modulation and transmission to a channel; and

decoding the encoded sequence to obtain decoded code bit sequence.
The method according to claim 34, wherein the pre-defined order is stored in a table or indicated by a sequence.
The method according to claim 34 or 35, wherein the pre-defined order is a reverse order of the blocks.
The method according to any one of claims 34 to 36, wherein the order of bits in each of the blocks is unchanged before and after the interleaving.
The method according to any one of claims 34 to 37, wherein the first code bit sequence is divided into blocks independent of a modulation order.
The method according to claim 38, wherein a block size is predefined in a protocol.
The method according to claim 38 or 39, wherein a block size is a power-of-2 number.
The method according to claim 40, wherein the block size is 8, 16, 32, 64, or 128.
The method according to claim 38 or 39, wherein a block size is a prime number.
The method according to claim 42, wherein the block size is 5, 7, 11, 13, 17, or 19.
The method according to any one of claims 38 to 43, wherein the blocks are interleaved by:

writing the blocks block-by-block into a buffer of a given shape according to the predefined order; and

reading the blocks block-by-block from the buffer of the given shape according to a different predefined order to obtain an output sequence.
The method according to claim 44, wherein the given shape is a square, a rectangle, a triangle, or a trapezoid.
The method according to claim 44 or 45, wherein the blocks are interleaved further by:

sequentially feeding the output sequence to a modulator, wherein consecutive bits in each of blocks of the output sequence are mapped to one symbol.
The method according to any one of claims 34 to 37, wherein the first code bit sequence is divided into blocks dependent of a modulation order.
The method according to claim 47, wherein a block size of block is determined based on the modulation order.
The method according to claim 48, wherein the block size is a divisor of the modulation order and a positive even integer.
The method according to claim 49, wherein the positive even integer is a fixed value.
The method according to claim 49 or 50, wherein the positive even integer is 2 4 6 8, or 10.
The method according to any one of claims 47 to 51, wherein the blocks are grouped into multiple groups of blocks, and a number of blocks in each of the multiple groups is equal to the positive even integer.
The method according to claim 52, wherein the blocks are interleaved by:

writing the blocks in each of the multiple groups block-by-block according to the predefined order.
The method according to claim 53, wherein each of multiple groups of blocks is written block-by-block into a rectangle-shaped buffer row-by-row in either left-to-right order or right-to-left order, wherein a number of rows of the rectangle-shaped buffer is equal to the positive even integer; and

the blocks are read block-by-block from the rectangle-shaped buffer column-by-column in either top-down order or bottom-up order to obtain an output sequence, wherein each of columns comprises a respective group of multiple groups.
The method according to any one of claims 52 to 54, wherein the blocks are interleaved further by:

sequentially feeding an output sequence to a modulator, wherein consecutive bits of each of the multiple groups of block are mapped to one modulated symbol.
The method according to claim 54 or 55, wherein the first code bit sequence is divided into blocks by:

dividing the first code bit sequence into systematic blocks and parity blocks for systematic code, wherein the systematic blocks are blocks comprising systematic bits, and the parity blocks are blocks comprising parity bits.
The method according to claim 56, wherein the systematic blocks and the parity blocks for the systematic code are grouped into multiple groups of blocks, wherein each of multiple groups comprises at least one systematic block and at least one parity block.
The method according to claim 57, wherein the systematic blocks are written row-by-row in left-to-right order and the parity blocks are written row-by-row in right-to-left order, or the systematic blocks are written row-by-row in right-to-left order and the parity blocks are written row-by-row in left-to-right order, or the systematic blocks and the parity blocks are written in zigzag order.
The method according to claim 58, wherein the systematic blocks are read column-by-column in top-down order and the parity blocks are read column-by-column in bottom-up order, or the systematic blocks are read column-by-column in bottom-up order and the parity blocks are read column-by-column in top-down order, or the systematic blocks and the parity blocks are read in zigzag order.
The method according to claim 59, wherein consecutive bits in the at least one systematic block in each of multiple groups of blocks are mapped to high-energy bits, and consecutive bits in the at least one parity block in each of multiple groups of blocks are mapped to low-energy bits.
The method according to claim 54 or 55, wherein the first code bit sequence is divided into blocks by:

dividing the first code bit sequence into first blocks and second blocks for non-systematic code, wherein the first blocks comprises bits from a first half of the second code bit sequence and the second blocks comprises bits from a second half of the second code bit sequence.
The method according to claim 61, wherein the first blocks and the second blocks for the non-systematic code are grouped into multiple groups of blocks.
The method according to claim 62, wherein the first blocks are written row-by-row in left-to-right order and the second blocks are written row-by-row in right-to-left order, or the first blocks are written row-by-row in right-to-left order and the second blocks are written row-by-row in left-to-right order, or the first blocks and the second blocks are written row-by-row in zigzag order.
The method according to claim 63, wherein the first blocks are read column-by-column in top-down order and the second blocks are read column-by-column in bottom-up order, or the first blocks are read column-by-column in bottom-up order and the second blocks are read column-by-column in top-down order, or the first blocks and the second blocks are read column-by-column in zigzag order.
The method according to claim 64, wherein consecutive bits in the at least one first block in each of multiple groups of blocks are mapped to high-energy bits, and consecutive bits in the at least one second block in each of multiple groups of blocks are mapped to low-energy bits.
The method according to any one of claims 38 to 65, wherein the modulation mode is quadrature amplitude modulation (QAM) .
A first apparatus comprising:

an interface for obtaining a first code bit sequence, wherein the first code bit sequence is obtained after rate matching a second code bit sequence; and

a channel interleaver coupled to the interface for:

dividing the first code bit sequence into blocks; and

channel interleaving the blocks according to a pre-defined order, wherein the channel interleaving is applied to the first code bit sequence before modulation and transmission to a channel.
The first apparatus according to claim 67, wherein the pre-defined order is stored in a table or indicated by a sequence.
The first apparatus according to claim 67 or 68, wherein the pre-defined order is a reverse order of the blocks.
The first apparatus according to any one of claims 67 to 69, wherein the order of bits in each of the blocks is unchanged before and after the interleaving.
The first apparatus according to any one of claims 67 to 70, wherein the dividing the first code bit sequence into blocks is performed independent of a modulation order.
The first apparatus according to claim 71, wherein a block size is predefined in a protocol.
The first apparatus according to claim 71 or 72, wherein a block size is a power-of-2 number.
The first apparatus according to claim 73, wherein the block size is 8, 16, 32, 64, or 128.
The first apparatus according to claim 71 or 72, wherein a block size is a prime number.
The first apparatus according to claim 75, wherein the block size is 5, 7, 11, 13, 17, or 19.
The first apparatus according to any one of claims 72 to 76, wherein the channel interleaver is further for:

writing the blocks block-by-block into a buffer of a given shape according to the predefined order; and

reading the blocks block-by-block from the buffer of the given shape according to a different predefined order to obtain an output sequence.
The first apparatus according to claim 77, wherein the given shape is a square, a rectangle, a triangle, or a trapezoid.
The first apparatus according to claim 77 or 78, wherein the channel interleaver is further for:

sequentially feeding the output sequence to a modulator, wherein consecutive bits in each of blocks of the output sequence are mapped to one symbol.
The first apparatus according to any one of claims 67 to 70, wherein the dividing the first code bit sequence into blocks is performed dependent of a modulation order.
The first apparatus according to claim 80, the channel interleaver is further for:

determining a block size based on the modulation order.
The first apparatus according to claim 81, wherein the block size is a divisor of the modulation order and a positive even integer.
The first apparatus according to claim 82, wherein the positive even integer is a fixed value.
The first apparatus according to claim 82 or 83, wherein the positive even integer is 2 4 6 8, or 10.
The first apparatus according to any one of claims 80 to 84, wherein the blocks are grouped into multiple groups of blocks, and a number of blocks in each of the multiple groups is equal to the positive even integer.
The first apparatus according to claim 85, wherein the channel interleaver is further for:

writing the blocks in each of the multiple groups block-by-block according to the predefined order.
The first apparatus according to claim 86, wherein each of multiple groups of blocks is written block-by-block into a rectangle-shaped buffer row-by-row in either left-to-right order or right-to-left order, wherein a number of rows of the rectangle-shaped buffer is equal to the positive even integer; and

the blocks are read block-by-block from the rectangle-shaped buffer column-by-column in either top-down order or bottom-up order to obtain an output sequence, wherein each of columns comprises a respective group of multiple groups.
The first apparatus according to any one of claims 85 to 87, wherein the channel interleaver is further for:

sequentially feeding an output sequence to a modulator, wherein consecutive bits of each of the multiple groups of block are mapped to one modulated symbol.
The first apparatus according to claim 87 or 88, wherein the channel interleaver is further for:

dividing the first code bit sequence into systematic blocks and parity blocks for systematic code, wherein the systematic blocks are blocks comprising systematic bits, and the parity blocks are blocks comprising parity bits.
The first apparatus according to claim 89, wherein the systematic blocks and the parity blocks for the systematic code are grouped into multiple groups of blocks, wherein each of multiple groups comprises at least one systematic block and at least one parity block.
The first apparatus according to claim 90, wherein the systematic blocks are written row-by-row in left-to-right order and the parity blocks are written row-by-row in right-to-left order, or the systematic blocks are written row-by-row in right-to-left order and the parity blocks are written row-by-row in left-to-right order, or the systematic blocks and the parity blocks are written in zigzag order.
The first apparatus according to claim 91, wherein the systematic blocks are read column-by-column in top-down order and the parity blocks are read column-by-column in bottom-up order, or the systematic blocks are read column-by-column in bottom-up order and the parity blocks are read column-by-column in top-down order, or the systematic blocks and the parity blocks are read in zigzag order.
The first apparatus according to claim 92, wherein consecutive bits in the at least one systematic block in each of multiple groups of blocks are mapped to high-energy bits, and consecutive bits in the at least one parity block in each of multiple groups of blocks are mapped to low-energy bits.
The first apparatus according to claim 87 or 88, wherein the channel interleaver is further for:

dividing the first code bit sequence into first blocks and second blocks for non-systematic code, wherein the first blocks comprises bits from a first half of the second code bit sequence and the second blocks comprises bits from a second half of the second code bit sequence.
The first apparatus according to claim 94, wherein the first blocks and the second blocks for the non-systematic code are grouped into multiple groups of blocks.
The first apparatus according to claim 95, wherein the first blocks are written row-by-row in left-to-right order and the second blocks are written row-by-row in right-to-left order, or the first blocks are written row-by-row in right-to-left order and the second blocks are written row-by-row in left-to-right order, or the first blocks and the second blocks are written row-by-row in zigzag order.
The first apparatus according to claim 96, wherein the first blocks are read column-by-column in top-down order and the second blocks are read column-by-column in bottom-up order, or the first blocks are read column-by-column in bottom-up order and the second blocks are read column-by-column in top-down order, or the first blocks and the second blocks are read column-by-column in zigzag order.
The first apparatus according to claim 97, wherein consecutive bits in the at least one first block in each of multiple groups of blocks are mapped to high-energy bits, and consecutive bits in the at least one second block in each of multiple groups of blocks are mapped to low-energy bits.
The first apparatus according to any one of claims 71 to 98, wherein the modulation mode is quadrature amplitude modulation (QAM) .
A second apparatus comprising:

an interface for obtaining blocks of encoded sequence by channel interleaving first code bit sequence, wherein the first code bit sequence is divided into the blocks and the first code bit sequence is obtained after rate matching a second code bit sequence; wherein the blocks are channel interleaved according to a pre-defined order, wherein the channel interleaving is applied to the first code bit sequence before modulation and transmission to a channel; and

a decoder for decoding the encoded sequence to obtain decoded code bit sequence.
The second apparatus according to claim 100, wherein the pre-defined order is stored in a table or indicated by a sequence.
The second apparatus according to claim 100 or 101, wherein the pre-defined order is a reverse order of the blocks.
The second apparatus according to any one of claims 100 to 102, wherein the order of bits in each of the blocks is unchanged before and after the interleaving.
The second apparatus according to any one of claims 100 to 103, wherein the first code bit sequence is divided into blocks independent of a modulation order.
The second apparatus according to claim 104, wherein a block size is predefined in a protocol.
The second apparatus according to claim 104 or 105, wherein a block size is a power-of-2 number.
The second apparatus according to claim 106, wherein the block size is 8, 16, 32, 64, or 128.
The second apparatus according to claim 104 or 105, wherein a block size is a prime number.
The second apparatus according to claim 108, wherein the block size is 5, 7, 11, 13, 17, or 19.
The second apparatus according to any one of claims 104 to 101, wherein the blocks are interleaved by:

writing the blocks block-by-block into a buffer of a given shape according to the predefined order; and

reading the blocks block-by-block from the buffer of the given shape according to a different predefined order to obtain an output sequence.
The second apparatus according to claim 110, wherein the given shape is a square, a rectangle, a triangle, or a trapezoid.
The second apparatus according to claim 110 or 111, wherein the blocks are interleaved further by:

sequentially feeding the output sequence to a modulator, wherein consecutive bits in each of blocks of the output sequence are mapped to one symbol.
The second apparatus according to any one of claims 100 to 103, wherein the first code bit sequence is divided into blocks dependent of a modulation order.
The second apparatus according to claim 113, wherein a block size of block is determined based on the modulation order.
The second apparatus according to claim 114, wherein the block size is a divisor of the modulation order and a positive even integer.
The second apparatus according to claim 115, wherein the positive even integer is a fixed value.
The second apparatus according to claim 115 or 116, wherein the positive even integer is 2 4 6 8, or 10.
The second apparatus according to any one of claims 113 to 117, wherein the blocks are grouped into multiple groups of blocks, and a number of blocks in each of the multiple groups is equal to the positive even integer.
The second apparatus according to claim 118, wherein the blocks are interleaved by:

writing the blocks in each of the multiple groups block-by-block according to the predefined order.
The second apparatus according to claim 119, wherein each of multiple groups of blocks is written block-by-block into a rectangle-shaped buffer row-by-row in either left-to-right order or right-to-left order, wherein a number of rows of the rectangle-shaped buffer is equal to the positive even integer; and

the blocks are read block-by-block from the rectangle-shaped buffer column-by-column in either top-down order or bottom-up order to obtain an output sequence, wherein each of columns comprises a respective group of multiple groups.
The second apparatus according to any one of claims 118 to 120, wherein the blocks are interleaved further by:

sequentially feeding an output sequence to a modulator, wherein consecutive bits of each of the multiple groups of block are mapped to one modulated symbol.
The second apparatus according to claim 120 or 121, wherein the first code bit sequence is divided into blocks by:

dividing the first code bit sequence into systematic blocks and parity blocks for systematic code, wherein the systematic blocks are blocks comprising systematic bits, and the parity blocks are blocks comprising parity bits.
The second apparatus according to claim 122, wherein the systematic blocks and the parity blocks for the systematic code are grouped into multiple groups of blocks, wherein each of multiple groups comprises at least one systematic block and at least one parity block.
The second apparatus according to claim 123, wherein the systematic blocks are written row-by-row in left-to-right order and the parity blocks are written row-by-row in right-to-left order, or the systematic blocks are written row-by-row in right-to-left order and the parity blocks are written row-by-row in left-to-right order, or the systematic blocks and the parity blocks are written in zigzag order.
The second apparatus according to claim 124, wherein the systematic blocks are read column-by-column in top-down order and the parity blocks are read column-by-column in bottom-up order, or the systematic blocks are read column-by-column in bottom-up order and the parity blocks are read column-by-column in top-down order, or the systematic blocks and the parity blocks are read in zigzag order.
The second apparatus according to claim 125, wherein consecutive bits in the at least one systematic block in each of multiple groups of blocks are mapped to high-energy bits, and consecutive bits in the at least one parity block in each of multiple groups of blocks are mapped to low-energy bits.
The second apparatus according to claim 119 or 120, wherein the first code bit sequence is divided into blocks by:

dividing the first code bit sequence into first blocks and second blocks for non-systematic code, wherein the first blocks comprises bits from a first half of the second code bit sequence and the second blocks comprises bits from a second half of the second code bit sequence.
The second apparatus according to claim 127, wherein the first blocks and the second blocks for the non-systematic code are grouped into multiple groups of blocks.
The second apparatus according to claim 128, wherein the first blocks are written row-by-row in left-to-right order and the second blocks are written row-by-row in right-to-left order, or the first blocks are written row-by-row in right-to-left order and the second blocks are written row-by-row in left-to-right order, or the first blocks and the second blocks are written row-by-row in zigzag order.
The second apparatus according to claim 129, wherein the first blocks are read column-by-column in top-down order and the second blocks are read column-by-column in bottom-up order, or the first blocks are read column-by-column in bottom-up order and the second blocks are read column-by-column in top-down order, or the first blocks and the second blocks are read column-by-column in zigzag order.
The second apparatus according to claim 130, wherein consecutive bits in the at least one first block in each of multiple groups of blocks are mapped to high-energy bits, and consecutive bits in the at least one second block in each of multiple groups of blocks are mapped to low-energy bits.
The second apparatus according to any one of claims 103 to 131, wherein the modulation mode is quadrature amplitude modulation (QAM) .
A third apparatus comprising a processor configured to cause the third apparatus to perform the method according to any one of claims 1 to 33.
A fourth apparatus comprising a processor configured to cause the fourth apparatus to perform the method according to any one of claims 34 to 66.
A computer program comprising programming for execution by a processor, the programming including instructions to perform the method according to any one of claims 1 to 66.
A non-transitory computer readable medium storing programming for execution by a processor, the programming including instructions to perform the method according to any one of claims 1 to 66.
A system comprising:

a first communication device configured to perform the method according to any one of claims 1 to 33; and

a second communication device configured to perform the method according to any one of claims 34 to 66.