WO2025104659A1 - Micro-led with etching-free pixel definition - Google Patents

Abstract

A green light emitting micro-light emitting device (micro-LED) (300) includes a pixel (232) and an oxidized region (236) fully enclosing a lateral surface of the pixel (232). The pixel (232) includes an n-doped GaN layer (206), a super lattice buffer layer (208) located on the n-doped GaN layer (206), multiple quantum well layers (210) located on the supper lattice buffer layer (208), a p-doped GaN layer (214/216) located over the multiple quantum well layers (210), and first and second electrodes (242, 240), the first electrode (242) being in direct electrical contact with the n-doped GaN layer (206) and the second electrode (240) being in electrical contact with the p-doped GaN layer (214/216). The oxidized region (236) includes corresponding layers as the pixel (232), but partially oxidized so that the oxidized region is a dielectric.

Description

MICRO-LED WITH ETCHING-FREE PIXEL DEFINITION

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No. 63/548,417, filed on November 14, 2023, entitled “ETCHING-FREE PIXEL DEFINITION THROUGH SELECTIVE THERMAL OXDIZATION IN 11 l-NITRIDE MICRO-LEDs,” the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

TECHNICAL FIELD

[0002] Embodiments of the subject matter disclosed herein generally relate to a system and method for obtaining a green micro-light emitting diode (LED) based on an etching-free pixel definition approach for reducing, if not eliminating, sidewall damage and defect formation, which is conducive to improved device efficiency.

DISCUSSION OF THE BACKGROUND

[0003] The existing InGaN-based blue, green, and red micro-LEDs have garnered significant attention and interest due to their exceptional features such as high contrast, intense brightness, excellent energy efficiency, and long device lifetimes, thus positioning them as strong contenders as the next-generation display technology. Compared to large-scale LEDs (in which the individual red, green, or blue diodes, that make up a pixel, having a size larger than about 200 pm), micro- LEDs (the individual diodes have a size smaller than about 100 urn) exhibit superior current spreading and heat dissipation capabilities, which contribute to enhanced device performance.

[0004] Furthermore, the sustainable high current density of micro-LEDs also holds the promise for applications in high-bandwidth visible light communication. However, to define micro-LED pixels, plasma or ion etching methods are widely adopted to selectively remove portions of the active region, resulting in severe sidewall damage and defect formation of the pixels. These defects act as non- radiative recombination centers and paths for leakage current, hampering the efficiency of micro-LEDs. The negative impact from plasma damage is not limited to the sidewall surface of the pixels but, depending on the applied etching conditions, the damage penetrates to a certain depth, known as the “dead zone.” Due to a higher area ratio between the sidewall and mesa’s top surface, the sidewall damage has a more pronounced impact on the efficiency of smaller devices, known as the efficiency size effect or sidewall effect in micro-LEDs.

[0005] Several methods have been reported to mitigate these issues:

[0006] (i) Remove the sidewall damage regions. Etchants such as KOH and tetramethyl ammonium hydroxide (TMAH) were extensively employed to selectively etch the damaged regions at the sidewall facets of the pixels, reducing micro-LED leakage current.

[0007] (ii) Surface passivation of sidewalls: material surfaces are present at the end of the periodic lattice, aiding in increasing the number of dangling bonds. At the same time, the sidewall surface also bears a significant amount of plasma damage. Therefore, surface passivation is an effective method to passivate dangling bonds and suppress surface states caused by ions and plasmas. Recently, atomic layer deposition (ALD) dielectrics, like AI2O3, have been widely used to deposit on micro-LED sidewalls for surface passivation. ALD-AIN has also been demonstrated as an efficient passivation material for Ill-nitride-based micro-LEDs. Additionally, various approaches, such as rapid thermal annealing to repair sidewall defects and (NH4)2S treatment to remove unstable native oxides and form monolayer sulfide passivation, have been introduced to optimize micro-LEDs.

[0008] (iii) Modulate the current path to steer it away from the sidewall regions in order to reduce non-radiative carrier recombination near the mesa edge. For instance, some groups have proposed an oxide-confined structure to reduce current diffusion to the sidewall. One group employed the resistive ITO/p-GaN junction and Ta2Os high-k insulator to modulate the band structure and reduce hole concentration near damaged regions. Another group utilized H2 plasma to passivate Mg acceptors of p-type layers near the sidewall and formed an insulating region to suppress carrier non-radiative recombination.

[0009] However, all these methods involve subsequent optimization following plasma etching for pixel definition. Thus, there is a need for a method and micro-LED that has its side walls not damaged by the processed used for defining the pixels.

SUMMARY OF THE INVENTION

[0010] According to an embodiment, there is a green light emitting micro-light emitting device (micro-LED) that includes a pixel and an oxidized region fully enclosing a lateral surface of the pixel. The pixel includes an n-doped GaN layer, a super lattice buffer layer located on the n-doped GaN layer, multiple quantum well layers located on the supper lattice buffer layer, a p-doped GaN layer located over the multiple quantum well layers, and first and second electrodes, the first electrode being in direct electrical contact with the n-doped GaN layer and the second electrode being in electrical contact with the p-doped GaN layer. The oxidized region includes corresponding layers as the pixel, but partially oxidized so that the oxidized region is a dielectric.

[0011 ] According to another embodiment, there is a method for making a green light emitting micro-light emitting device (micro-LED). The method includes providing a wafer having an n-doped GaN layer, a super lattice buffer layer located on the n-doped GaN layer, multiple quantum well layers located on the supper lattice buffer layer, and a p-doped GaN layer located over the multiple quantum well layers, depositing a protective SiO2 layer over the p-doped GaN layer, patterning the protective SiO2 layer to define a pixel, and applying selective thermal oxidation to the wafer in open atmosphere to form an oxidized region that fully encloses a lateral surface of the pixel. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

[0013] FIG. 1 is a flow chart of a method for making a micro-LED device using a selective thermal oxidation (STO) procedure;

[0014] FIG. 2 is a cross-section through a wafer that includes an active layer for generating a green light;

[0015] FIGs. 3A to 3E illustrate various phases of making the micro-LED device with the STO procedure in the wafer of FIG. 2;

[0016] FIG. 4A shows a cross-section of the wafer of FIG. 2, before the STO procedure, while FIG. 4B shows the same cross-section of the same wafer, after the STO procedure;

[0017] FIGs. 5A to 5G illustrate various phases of making individual pixels with the STO procedure, in the wafer of FIG. 2, and FIG. 5H is a cross-section of an individual pixel made with the STO procedure;

[0018] FIG. 6A illustrates the effect of the STO procedure on a p-layer electrical behavior of the micro-LED device, for various thickness of a protecting SiO2 layer while FIG. 6B illustrates the effect of the annealing time on the electrical behavior of the same layer of the micro-LED device; [0019] FIG. 7 illustrates the effect of the thickness of a protecting SiC>2 layer and the annealing time for p-layer electrical behavior of the the micro-LED device;

[0020] FIG. 8A illustrates the current-voltage (l-V) characteristic of the micro- LED device for different STO times;

[0021] FIG. 8B illustrates the wall plug efficiency of the micro-LED device for different STO times;

[0022] FIG. 8C illustrates the external quantum efficiency of the micro-LED device for different STO times;

[0023] FIG. 8D illustrates the optical power of the micro-LED device for different STO times;

[0024] FIG. 8E illustrates the full width at half maximum of the micro-LED device for different STO times;

[0025] FIG. 8F illustrates the peak wavelength of the micro-LED device for different STO times;

[0026] FIG. 9A illustrates the l-V characteristic at forward bias of the micro- LED device for various sizes;

[0027] FIG. 9B illustrates the l-V characteristic in log scale of the micro-LED device for various sizes;

[0028] FIG. 9C illustrates the external quantum efficiency of the micro-LED device for various sizes; and

[0029] FIG. 9D illustrates the spectrum of the full width at half maximum of the micro-LED device for various sizes. DETAILED DESCRIPTION OF THE INVENTION

[0030] The following description of the embodiments refers to the accompanying drawings. The same reference numbers in different drawings identify the same or similar elements. The following detailed description does not limit the invention. Instead, the scope of the invention is defined by the appended claims. The following embodiments are discussed, for simplicity, with regard to a green pixel that is part of micro-LED device. However, the embodiments to be discussed next are not limited to green pixels, but may be applied to other visible light pixels or ultraviolet pixels.

[0031] Reference throughout the specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with an embodiment is included in at least one embodiment of the subject matter disclosed. Thus, the appearance of the phrases “in one embodiment” or “in an embodiment” in various places throughout the specification is not necessarily referring to the same embodiment. Further, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments.

[0032] According to an embodiment, a method for defining pixels in a micro- LED device is avoiding the use of plasma etching, to provide an alternative solution for the development of micro-LEDs. In this embodiment, the inventors applied an innovative selective thermal oxidation (STO) method that achieved pixel definition without sidewall plasma damage, potentially avoiding the harmful effects brought about by ion and plasma etching. Thermal annealing in ambient air oxidized the LED layers and formed insulating oxides. However, the LED pixels were protected by a SiC>2 layer to prevent oxidation and maintain their luminescent functionality. Some of the parameters of this approach, e.g., the annealing time and SiC>2 thickness, contributed to the improved micro-LED performance. Using the STO method, the inventors achieved micro-LED arrays with pixel sizes as small as 2.3-pm and provided a comprehensive performance analysis for devices with different pixel sizes.

[0033] A free-etching method for fabricating the micro-LED is now discussed with regard to FIGs. 1 to 4B. The LED fabrication process 100, which is illustrated in FIG. 1 , starts with an InGaN-based green LED wafer 200, as schematically depicted in FIG. 2. Note that the InGaN-based green LED wafer emits green light (i.e., works in the visible range), due to the In incorporation (doping) in the active layer. If the In atoms are replaced by Al, then ultraviolet light is generated. For this case, the wafer 200 may include AIGaN/AIGaN multiple quantum wells (MQWs), and the STO process will oxidize to n-AIGaN instead of n-GaN. Those skilled in the art would understand that other atoms or combination of atoms may be used in the super- lattice (SL) buffer layers, MQWs, electron blocking layers, and electron (hole) injection layers, etc.

[0034] The LED wafer 200 is grown in this embodiment on a sapphire substrate 202, by known methods. Other materials may be used for the substrate, for example, Si, glass, SiC, Ga2Oa, AIN, GaN, etc. The wafer 200 is made with known methods in the art. In this embodiment, the wafer 200 includes a GaN buffer layer 204, an n-GaN electron injection layer 206, two pairs of InGaN/GaN SL layers 208 (each pair having, for example, a thickness of about 3/17 nm, respectively), eight pairs of InGaN/GaN MQWs layers 210 (e.g., having a thickness of about 4/15 nm, respectively) with a photoluminescence wavelength around 551 nm (i.e. , green light). Other atoms instead of the In atom may be used in the MQWs layers 210, depending on the desired light wavelength. In one embodiment, the eight pairs of MQWs layers 210 are formed on top of the two pairs of SL layers 208. In this or another embodiment, the MQWs layers have an SL structure. More or less than eight pairs of MQWs layers may be used. The SL buffer layers 208 and the MQWs layers 210 form the lattice region 212 of the micro-LED device.

[0035] The LED wafer 200 further includes an about 50 nm thick low temperature (LT) p-GaN layer 214 located over the latice region 212, an about 25 nm electron-blocking layer 216 located over the LT p-GaN layer 214, an about 125 nm high temperature (HT) p-GaN layer 218 located over the electron-blocking layer 216, and a p-contact layer 220 located over the HT p-GaN layer. One skilled in the art would understand that some of the layers may be omitted or other layers may be added and still obtaining functional micro-LED devices.

[0036] FIGs. 3A to 3E illustrate the STO process flow for forming a micro-LED having plural pixels 232. Initially, in step 102 of FIG. 1 , a plasma etching process (based on BCh, CI2, and Ar plasma) is used on the wafer 200 to expose the n-GaN layer 206 for a given surface area 206A of the wafer 200, as shown in FIG. 3A. This exposed surface area 206A facilitates the subsequent formation of the n-contact. Note that this initial etching process is not used for the pixel definition, and the etched regions 206A are far away from the pixels 232, thus causing no damage to them. In step 104, a layer of SiC>2 is deposited over the whole wafer area 200 (e.g., the p-contact layer 220), using plasma-enhanced chemical vapor deposition. The SiC>2 layer is then patterned in step 106, for example, by dry etching (C4F8 and O2 plasma with Cr as a hard mask) as a protective layer 222 on the surface 206A of the n-GaN 206 and as protective regions 224 on the surface of the p-contact layer 220, as shown in FIG. 3B. The areas of the wafer 200 covered with the SiO2 regions 224 serve as the future pixel region.

[0037] For determining the impact of the size of the pixel region, this method was used for making micro-LED 300 having pixels 232 with a diameter D of 50-, 30-, and 10-pm sizes, with the total emitting area being held constant (e.g., about 0.0177 mm²). Subsequently, the LED wafer 200 was annealed in step 108 in ambient air, for example, in a tube furnace, to selectively oxidize the exposed portions 226 of the p- contact layer 220 (not protected by the patterned SiO2). Note that the regions of the wafer 200 protected by the layer 222/224 are essentially not affected by this oxidation process. This means that the dense structure of the SiO2 layer 222/224 blocked the penetration of oxygen, from the air into the pixel regions 232, thereby protecting the underlying LED structure. Similar to the thermal oxidation process of Si, the SiO2 surface layer 222, 224 functions as a barrier to oxygen diffusion, shielding the underlying material from additional oxidation. The step 108 is also called the STO step. In one embodiment, the SiO2 layer has a thickness of about 3.5-pm. [0038] Following the STO step 108, the SiC>2 remaining regions 222/224 were removed in step 110 using HF vapor (other methods may be used as known in the art), resulting in the LED device 300 being shown in FIG. 3C. The LED device 300 includes plural pixels 232 and the LED device 300 is a micro-LED device. In one embodiment, one pixel 232 forms the micro-LED device 300. Thus, there are situations when a micro-LED device 300 includes a single pixel 232 (as shown in FIG. 5G), in which case these two terms refer to the same product. Various tests performed by the inventors indicated that the micro-LED device 300 top surface 228, without SiO2 protection, (see FIG. 3C) became extremely rough compared to a reference sample, due to the occurrence of oxidation. In contrast to the 3.5-pm SiO2 protection layer 222/224, the micro-LED device protected top surface 230 remained smooth even after 8 h of thermal annealing in the ambient air, indicating the importance of the SiO2 layer 222/224 in blocking oxygen during the STO process 108.

[0039] FIG. 4A shows a cross-section through the wafer 200, before the STO step 108 is performed and FIG. 4B shows the same cross-section after the removal of the protection layer 224 after the STO step 108. It is noted that the oxidized part of the p-layer 220 (its surface 228 after annealing) is about 150 to 300 nm higher than the smooth pixel surface 230 (also after annealing, but protected by the SiO2 layer). The pixel interface 234 of the pixel 232, which has a diameter D, after SiO2 removal is rough relative to the surface 230, for example, the local RMS roughness is about 10 nm or more. For the original sample, it is around 200 pm. [0040] The annealing temperature during the STO step 108 influences the thermal oxidation performance. Given the stability of the InGaN MQWs layers 210, especially the indium diffusion issue, the annealing temperature should not be excessively high (not higher than 950 °C) even with the SiO2 protection layer. The annealing temperature may depend on the wavelength of the micro-LEDs as the wavelength is determined by different In compositions in the MQW: for red LEDs, the In composition is higher, for blue LEDs, the In composition is lower. Therefore, the blue LEDs are more stable MQWs than the red. On the other hand, the temperature should be sufficiently high (at least 800 to 900 °C) to oxidize the GaN layer 214-220 and InGaN layer 210 in the absence of SiO2. If Al is used instead of In for the doping, then the temperature may go as high as about 1200 °C. In one embodiment, the annealing temperature for the STO is between 800 and 950 °C. In yet another embodiment, the annealing temperature for the STO is about 900 °C. This means that the regions 236 including parts of the layers 206-220, corresponding to the unprotected areas 228, have been oxidized during the STO step 108, while the regions 232 of the same layers, corresponding to the protected areas 230 (due to the SiO2 layer) were not oxidized, as schematically illustrated in FIG. 4B. In other words, the oxidation of the regions 236 defines the pixels 232. Note that the original structure of the now oxidized layers 208-220, now part of the regions 236, have been severely affected by the STO process, so that the layers in these regions are barely recognizable, have different crystallization. Note that the layer 206 can be free of oxidation or partially oxidized, but it cannot be fully oxidized. The STO process in essence destroyed the diode functionality of the layers 208-220 (and optionally, a part of layer 206) in the regions 236, transforming them into a dielectric material, which insulates the pixels from each other.

[0041] Therefore, a final annealing temperature of about 900 °C was chosen for this embodiment, as it has been demonstrated to be a relatively lower temperature for thorough oxidation of the GaN layers. The heating and cooling rates were set at 5 °C/min during the thermal oxidization. The stability (no peel-off) of the SiC>2 mask under prolonged high-temperature annealing was maintained for the STO step.

[0042] Following the annealing step 108, the SiC>2 222 and 224 was removed in step 110 by HF vapor at a substrate temperature of about 40 °C. It was found that the HF vapor exhibited etching selectivity between SiC>2 and other oxides. Thus, the inventors opted for HF vapor to minimize the thickness decrease of formed oxide materials 236 when removing the SiC>2 protective layer 222/224. After the removal of SiC>2, cathodoluminescence (CL) has been observed in the formed pixels 232, forming a strong contrast with the oxidized regions 236. In step 1 12, a 20/300 nm Ni (using, for example, e-beam deposition)/Au (using, for example, sputter deposition) (annealed in O2 at about 550 °C for about 300 s) was formed over the pixels 232 as the p-contact 240, as illustrated in FIG. 3D. During the same step, 30/200 nm Cr/Au (e.g., by sputter deposition and annealed in N2 at about 300 °C for about 300 s) were deposited as the p- and n-electrodes 242, respectively, as illustrated in FIG.

3E. Note that the pad 240 and electrodes 242 may be replaced with a single electrode. In one embodiment, each pixel may be provided with its own pad 240 and electrode 242. [0043] Because the formed oxide region 236 already serve as insulation between the pixels 232 (note that there is no empty space between adjacent pixels 232 that need to be filled up with a dielectric layer, as in the traditional micro-LED devices), there is no need for additional dielectric deposition in the process 100. Simultaneously, procedures like selective dielectric etching required in traditional micro-LED fabrication for subsequent metal contact and the associated photolithography alignment are no longer necessary. Therefore, the proposed STO process 100 for micro-LED fabrication is a self-aligned technique, reducing the complexity of photolithography for small-size device fabrication. The wafer size used in this embodiment was 1 cm x 1 cm. After mounting the chips on sapphire substrates (other substrates are also possible) and wire bonding, the optical characteristics of the micro-LEDs were on-wafer measured, and the light was extracted from the bottom of the chip. Through the aforementioned process 100, 50-, 30-, and 10-pm pixel micro-LED arrays have been fabricated.

[0044] FIG. 4A schematically illustrates the wafer 200 being patterned with the SiC>2 layer 224 for generating the micro-LEDs 300. FIG. 4B schematically illustrates the wafer 200 after the STO step 108, in which the newly oxidized regions 236 were formed. Note that the oxidized regions 236 were formed from the initial layers 208 to 220 (and optionally, part of layer 206) by their interaction with the O2 from air during the STO step discussed above. The structure of the oxidized regions 236 does not resemble the initial structure of the layers 208 to 220. If layer 206 is partially oxidized, then its oxidized structure does not resemble its non-oxidized structure. Note that in one embodiment, layer 206 is not oxidized and layer 208 is partially oxidized. In another embodiment, the O2 penetrated into the MQW layers 210 and SL buffer layer 208. In another embodiment, the O2 penetrated into the MQW layers 210, layer 208, and partially into the layer 206. The depth of the O2 penetration into the layers of the wafer 200 may be controlled by the duration of the STO step, and/or its temperature.

[0045] Transmission electron microscopy (TEM) images obtained near the oxide region 236/pixels 232 interfaces 410 (see FIG. 4B) after 4 h of STO were generated (not shown) and these images showed a clear boundary 410 between the Si02-protected regions (i.e., pixels 232) and the Si02-unprotected regions 236. Under SiO2 protection, the LED structure remained intact (see FIG. 4B, layers 204 to 220 are not affected), exhibiting a clear SL structure (MQWs layers 210 and the SL buffer layers 208) and excellent crystalline quality in the MQWs layers 210. However, once the SiO2 protection was lost, most of the layers 214-220 and MQWs layers 210 in the region 236 were oxidized. The oxidized layers show a distinctly polycrystalline nature with multiple crystal orientations mixed together.

[0046] While FIGs. 3A to 3E show the formation of a single contact/electrode 240 over an array of pixels 232, in one embodiment, FIGs. 5A to 5G show the formation of individual pixels 232. The method for forming individual pixels includes the steps 102 to 112 of the method of FIG. 1 , and the additional step 114 of wafer dicing as illustrated in FIG. 5F, and the step 116 of the die release from the substrate 202 (i.e., laser lift off) illustrated in FIG. 5G. FIG. 5H shows a cross-section of a single, independent pixel 232 (which is at the same time a micro-LED device 300 having a single pixel). The pixel 232 diameter D can be about 2 pm or even less, depending on a desired display resolution. The pairs of InGaN/GaN layers 208 is shown as including a layer 208A of GaN and a layer 208B of InGaN. In one embodiment the GaN layer is 208B and the InGaN layer is 208A. The MQWs layers 210 are shown including plural first layers 210A of InGaN and plural second layers 21 OB of GaN, which are interleaved to form the pairs of layers 210. Note that the sidewall of the individual pixel 232 is fully enclosed by the oxidized region 236. In one application, an annular diameter DD of the oxidized region 236 may be between 0.1 and 50 pm. Note that a distance between two adjacent pixels 232 on a same micro-LED device 300 forms the pixel pitch, which may be between 0.4 and 100 pm. The individual pixels 232 obtained in FIG. 5G may then be mass-transferred to an actual display.

[0047] The obtained micro-LEDs 300 demonstrate the significant presence of oxygen elements in areas 236 lacking SiO2 protection, implying structural oxidation of those areas. The experiments performed on the micro-LEDs 300 confirmed that the lateral diffusion distance of oxygen in the protected region 232 was about 300 nm after 4-h thermal oxidization.

[0048] As discussed above, after the thermal annealing step 108 in ambient air, the nitrides of the wafer layers without SiO2 protection underwent oxidation, forming oxides. The insulating properties of these oxides are beneficial for reducing LED leakage current between pixels and enhancing device efficiency. In this regard, [1] reported the formation of Ga2Oa through the oxidation of a p-type GaN layer and its application in deep ultraviolet photodetectors. As the annealing time initially increased, the film resistance rapidly increased. However, with prolonged annealing time, the resistance of the Ga20a began to decrease. Consequently, a sufficiently long and appropriate annealing duration was considered for improving the oxide insulation and reducing micro-LED leakage current.

[0049] However, a longer annealing time may introduce some parasitic effects like: (i) while the dense structure of SiC>2 can effectively suppress oxygen from entering the pixel’s interior, it is challenging to achieve complete blocking. As the annealing time increases, more oxygen elements may enter the LED from the air. (ii) As previously reported in the field, oxygen elements from SiC>2 can diffuse into the GaN under high-temperature thermal annealing. With an extended annealing time, the depth and concentration of oxygen diffusion significantly increase as studied by [2].

[0050] Because the LED wafers used by the inventors were based on InGaN and GaN epitaxial layers, this oxygen diffusion effect was observed in the formed micro-LEDs 300. While infiltrating oxygen may disrupt the original LED structure, reduce current conduction, and affect luminescent functionality through oxidation, after thermal annealing, the p-side metal contacts may deteriorate due to the formation of surface oxides, and these surface oxides are complicated to eliminate by HF vapor etching. In this regard, it is well known that the conductivity of the p- layer and the metal contact performance determine the operation voltage of the fabricated micro-LEDs at the same current density, which is, in other words, the device resistance.

[0051 ] Using circular transmission line measurement patterns with 10-pm spacing, as shown in FIGs. 6A and 6B, the inventors investigated the influence of SiO2 thickness and annealing time on the current conduction of the p-type layer with Ni/Au contacts 240. The influence of SiC>2 thickness and annealing time on the p- layer current at 5 V bias has also been summarized in FIG. 7. In the tests, the SiC>2 thickness was verified with a profile meter, and minor thickness variations from material deposition were considered to have no significant impact on the results. Following thermal annealing, the SiC>2 protective layer was removed by HF vapor. The reference sample with the same Ni/Au contact did not suffer any thermal annealing for comparison with other samples.

[0052] FIG. 6A reveals that under the same 4-h annealing conditions, as the SiO2 protective layer thinned from 3500 to 600 nm, the behavior of the Ni/Au metal contacts 240 gradually shifted from pure Ohmic to Schottky behavior.

Simultaneously, the p-layer current conduction including all the p-type layers 214- 220 significantly decreased from 10.65 to 2.92 mA. Since the annealing time was the same for all samples, the diffusion of oxygen elements from SiO2 to the LED should be similar. Therefore, it proved that a thicker SiO2 layer may be more effective in preventing oxygen intrusion from the air. However, FIG. 6B shows that under the same SiO2 thickness protection, the contact behavior with p-contact layer 220 and p- type layers 214-220 current conduction deteriorated with a longer annealing time, particularly beyond 4 h. The analysis suggested that even though a thicker SiO2 layer was beneficial in impeding oxygen diffusion from the air to the sample, it could not effectively prevent the penetration of oxygen elements from SiO2 into the LED. With prolonged annealing time at 900 °C, oxygen diffusing from SiO2 would oxidize the LED surface, impairing its conductivity and the performance of the metal contact. This also explains why, despite using a 3500 nm thick SiC>2 protective layer 222, as shown in FIG. 6A, the current in the annealed samples decreased compared to the reference samples without thermal annealing.

[0053] To further support the above analysis, the inventors compared the atomic force microscopy (AFM) surface morphologies of samples (not shown) with 3.5-pm SiC>2 protection and different annealing times (0, 4, and 8 h), measured by Bruker’s Dimension Icon. Compared to the non-annealed reference sample, samples annealed for 4 and 8 h still maintained a relatively smooth surface 230 overall, compared with non-annealed sample surface 220, consistent with the previous information. However, locally, the inventors observed that the annealed samples exhibited numerous protrusions on the surface 230, and this phenomenon was slightly more pronounced in the sample annealed for 8 h. It is believed that this was due to oxygen diffusion from SiC>2 into the LED, resulting in its slight oxidation of the surface and a minor increase in surface roughness. Thus, controlling the annealing time and the SiO2 protection thickness results in reducing the leakage current while maintaining reasonable operation voltage or device resistance.

[0054] The inventors also explored the performance of micro-LEDs 300 fabricated through the STO method 100 by fabricating four samples with STO durations of 2, 4, 8, and 12 h (referred to as devices A-D). The SiC>2 protective layer thickness used in these devices was about 3.5 pm. FIG. 8A displays the l-V curves of the investigated devices. The results indicated that, compared to the device A with a 2-h annealing, device B, which was annealed for 4 h, exhibited lower reverse leakage current at -10 V, 2.1 x 10^-10 A (1 .2 x 10^-6 A/cm2), suggesting that controlling the increased annealing time helped improve oxide insulation and reduce the leakage current. Leakage behavior in device A was also observed at low forward voltages (around 0-1 V), which raised following the voltage much more rapidly than in device B due to additional defect- related current paths. However, with the extended annealing time in devices C and D, the reverse leakage current increases again to 10^-8 to 10^-9 A at -10 V, indicating that 4 h was the preferred annealing time for controlling leakage current compared to other annealing times.

[0055] The leakage current paths in the studied devices include an LED bulk leakage, an oxide/LED interface leakage, and an oxide bulk leakage. It should be noted that due to the diode l-V behavior, both the LED bulk leakage and oxide/LED interface leakage significantly increased under forward voltage and LED emission. More current flowed through the defect regions under forward voltage, leading to significant non-radiative recombination and efficiency losses. It should be noted that the LED bulk defect is related to material epitaxy and is relatively independent of the fabrication process. As for the oxide bulk region, it was farther from the pixel, making it challenging for the current to spread to that area under forward voltage. It had high resistance (current < 10^-8 A at -10 V), generating only negligible leakage current and non-radiative recombination during LED emission.

[0056] From the l-V characteristics shown in FIG. 8A, device A exhibited a significant increase in current at low forward voltages, a phenomenon widely observed in micro-LEDs with severe sidewall defects [3]. Therefore, it is believed that the oxide/LED interface leakage was considerable in device A and became a dominant factor for the leakage current. It also led to a more accelerated increase of the leakage current after a specific revere voltage (around -4 V).

[0057] For devices C and D, unlike device A, they exhibited a slower increase in the leakage current at low forward voltages. It was inferred that the oxide/LED inter-face leakage in devices C and D was insignificant, and oxide bulk leakage was the main factor contributing to their reverse leakage. An oxidation time exceeding 4 h may lead to a decrease in the bulk insulation of the formed oxide, which aligned with the trend reported in the literature, and explains why devices C and D had higher reverse leakage currents compared to device B.

[0058] Consistent with the previous analysis, devices A and B, annealed for 2 and 4 h, respectively, exhibited similar forward operating voltages. A 3.5-pm SiC>2 layer was used to block the oxygen from the environment, and the diffusion of oxygen elements from the SiC>2 did not significantly affect device the resistance when the annealing time was shorter than 4 h. However, after annealing for more than 4 h, even with sufficiently thick SiC>2 protection layer, the device’s conductivity was greatly reduced. For annealing durations of 4, 8, and 12 h, the working voltage at 10 A/cm² increased from 2.9 V to 3.75 and 8.0 V. It is believed that the oxygen diffused from the SiC>2 layer to the LED 300, thus leading to the surface oxidization, which was the primary reason for the device’s resistance increase. Based on the observed behavior, it was concluded that device B, with 4 h of STO, exhibited the best performance with low-leakage current and device resistance.

[0059] This conclusion was further validated through the on-wafer wall-plug efficiency (WPE) and external quantum efficiency (EQE) shown in FIGs. 8B and 8C. For the device A, the WPE and EQE peaks were observed at a higher current (1 .53% at 10 mA) and (2.89% at 25 mA) compared to other devices, and the efficiency degradation was highly suppressed. This was a typical characteristic of high-leakage devices (LED bulk defect leakage and interface leakage) such as nanowire-LEDs and micro-LEDs. Leakage paths contributed to more Shockley- Read-Hall recombination, equivalent to an increase in the “A” value (Shockley-Read recombination coefficient) in the internal quantum efficiency ABC model (not shown), which correlates the “q” the internal quantum efficiency, “Rsp ” the spontaneous emission rate, “RSRH” the Shockley-Read recombination rate, “RAuger” the Auger recombination rate, “B” the radiative recombination coefficient, “C” the Auger recombination coefficient, and “n” the carrier concentration.

[0060] According to this model, compared to low-leakage devices with a smaller “A” value, the efficiency peak in high-leakage devices appeared at a higher current density, and the efficiency drop is less pronounced. However, the overall efficiency of such devices was poor. The efficiency curve of device A was highly consistent with the above feature and corroborated with the leakage behavior in the I— V characteristics presented earlier. In contrast to other devices, device B exhibited the highest WPE and EQE (5.72% and 6.48% at 0.4 mA) due to its low-leakage current and appropriate operating voltage. WPE and EQE were expected to be further improved by device packaging, optimizing wafer epitaxy, and optimizing STO conditions.

[0061] In contrast to devices A and B, devices C and D, although experiencing a significant growth in reverse leakage after extended annealing, did not exhibit a significant current value increase at efficiency peak. Consistent with the previous analysis, the reverse leakage of devices C and D primarily came from the oxide bulk path, which did not significantly impact device performance. However, as mentioned earlier, prolonged annealing led to oxygen diffusion from the SiC>2 layer to the pixel, further resulting in surface oxidation. Therefore, the operating voltages and device resistance were higher for devices C and D. The WPE of devices C and D was only 3.04% at 0.6 mA and 1 .20% at 1 .3 mA, respectively. The large device resistance of devices C and D results in heat generation during device operation, which can also lead to the deterioration of EQE. Besides, as shown in FIG. 8D, the output power at 60 mA for devices A-D is 3.618, 4.787, 3.622, and 2.633 mW, respectively.

[0062] Furthermore, the inventors have measured the spectral full width at half maximum (FWHM) for devices A-D, as shown in FIG. 8E. Due to band-filling effects and heat generation, the FWHM of all devices increased with the increasing current. At a current of 60 mA, the FWHM values for devices A-D were 40.7, 39.9, 42.6, and 48.2 nm. The noticeable increase in FWHM for devices C and D compared to devices A and B was attributed to higher device resistance and increased heat generation.

[0063] Moreover, as shown in FIG. 8F, the peak wavelength for devices A-D gradually decreased with increasing the current due to carrier filling and polarization field screening. However, the inventors did not find significant evidence of wavelength variation with the annealing time. The wavelength fluctuations between different devices is due to the non-uniformity in the epitaxial growth, but remained within a reasonable range. The similarity of wavelength across all four samples suggested that the quantum well structure was not significantly compromised under the protection of the SiC>2 layer, and the indium inside the MQWs 210 did not diffuse extensively.

[0064] The inventors also investigated the size dependence (50, 30, and 10 pm) of the l-V behavior, EQE, and spectral parameters for device B, as shown in FIGs. 9A to 9D. Device B was investigated because it exhibited the highest efficiency among all samples annealed for various times. It was observed that smaller pixel arrays had slightly higher operating voltages at the same current, especially for the 10-pm micro-LED shown in FIG. 9A. This is so because it may be related to the HF vapor etching process. In larger pixel arrays, the material surface, after removing the SiO2 layer by HF vapor, may have fewer residues and a cleaner surface. More reaction residues may lead to a higher operation voltage of the 10-pm device. Additionally, since the thermal oxidation process was isotropic, oxygen penetrated not only vertically but also laterally. Since the total pixel area was the same for all micro-arrays, smaller pixel arrays had relatively larger “side-surface” areas, indicating that more relative regions were exposed to the laterally diffused oxygen. This may also lead to an increase in the operating voltage.

[0065] Under reverse bias, all devices exhibited stable and low-leakage current of about 1 x 10^-6 A/cm² at -10 V, as shown in FIG. 9B. Compared to microLEDs reported in other studies that utilized conventional plasma etching and dielectric passivation processes, this leakage current was at a relatively low level. In conventional plasma-etched micro-LEDs, as the size decreases, the leakage current rapidly increases due to sidewall defects caused by the plasma. However, with pixel definition using the STO method, the leakage current for the 10 gm array only increased slightly compared to the 30-and 50-pm arrays, indicating that the size effect on leakage current was suppressed.

[0066] Nevertheless, at 0.4 mA, on-wafer EQE gradually decreased from 8.02% to 7.79% and 6.48% as the pixel size changed from 50 to 30 and 10 pm, as shown in FIG. 9C. It is believed that the efficiency degradation of smaller-sized devices was related to the leakage current and large resistance of the device. The latter led to a higher heat generation and junction temperature. Due to Auger recombination and carrier overflow, all devices exhibited similar efficiency droop at higher currents. The inventors also measured the FWHM of the emission spectra, as shown in FIG. 9D. All devices exhibited similar FWHM. Compared to the 10 pm pixel device (41 .3 nm), the 30 and 50 pm pixel devices had slightly lower FWHM at 80 mA (40.6 and 40.8 nm), possibly due to lower device resistance and less heat generation.

[0067] Thus, the above embodiments demonstrated pixel definition for microLEDs using the STO method 100 without plasma damage and dielectric passivation. The protection SiO2 layer thickness and annealing time were considered as factors in achieving excellent selectivity between oxidized regions 236 and unoxidized regions 232. The oxidized regions 236 exhibited satisfactory oxide insulation properties, while the unoxidized regions 232 (pixels) maintained their original structure and functionality, resisting the effects of thermal oxidation. This high contrast between the two regions ensured achieving high-performance and small-sized micro-LEDs through STO. Through a series of experiments, 10-pm pixel green micro-LED arrays 300 and corresponding pixels 232 with an on-wafer EQE of 6.48% have been realized using the STO method. Notably, the leakage current density was only slightly size-dependent and highly suppressed to 1.2x10“⁶ A/cm² at -10 V in the 10 pm pixel array. Besides, the limited lateral oxygen diffusion (around 300 nm) beneath the SiC>2 protection layer after 4 h annealing are encouraging for further reducing micro-LED dimensions.

[0068] To achieve more applications based on micro-LEDs 300, such as tiny micro-displays, the pixel size of the micro-LEDs 300 should be reduced to be as small as 2 micrometers. The embodiments of the STO approach discussed above achieved 2.3-pm micro-LED pixilation. Individual micro-LEDs 232 fabricated through the STO method 100 can be applied for display purposes through subsequent mass transfer processes such as stamp transfer and laser induced forward transfer.

[0069] The term “about” is used in this application to mean a variation of up to 20% of the parameter characterized by this term.

[0070] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first object or step could be termed a second object or step, and, similarly, a second object or step could be termed a first object or step, without departing from the scope of the present disclosure. The first object or step, and the second object or step, are both, objects or steps, respectively, but they are not to be considered the same object or step. [0071] The terminology used in the description herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used in this description and the appended claims, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any possible combinations of one or more of the associated listed items. It will be further understood that the terms "includes," "including," "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Further, as used herein, the term "if" may be construed to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context.

[0072] The disclosed embodiments provide a micro-LED device having pixels with no side damage. It should be understood that this description is not intended to limit the invention. On the contrary, the embodiments are intended to cover alternatives, modifications and equivalents, which are included in the spirit and scope of the invention as defined by the appended claims. Further, in the detailed description of the embodiments, numerous specific details are set forth in order to provide a comprehensive understanding of the claimed invention. However, one skilled in the art would understand that various embodiments may be practiced without such specific details. [0073] Although the features and elements of the present embodiments are described in the embodiments in particular combinations, each feature or element can be used alone without the other features and elements of the embodiments or in various combinations with or without other features and elements disclosed herein.

[0074] This written description uses examples of the subject matter disclosed to enable any person skilled in the art to practice the same, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the subject matter is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims.

References

The entire content of all the publications listed herein is incorporated by reference in this patent application.

[1 ] Wang, J. J. et al. High sensitivity Ga2O3 ultraviolet photodetector by one-step thermal oxidation of p-GaN films, Mater. Sci. Semicond. Proces. 159, 107372 (2023).

[2] Pearton, S. J. et al. Oxygen diffusion into SiO2-capped GaN during annealing. AppL Phys. Lett. 75, 2939-2941 , (1991 ).

[3] Islam, A. B. M. H. et al. Generation of sidewall defects in InGaN/GaN blue microLED under forward-current stress. App Phys. Lett. 121 , 013501 (2022).

Claims

WHAT IS CLAIMED IS:

1 . A green light emitting micro-light emitting device (micro-LED) (300) comprising: a pixel (232); and an oxidized region (236) fully enclosing a lateral surface of the pixel (232), the pixel (232) comprising: an n-doped GaN layer (206); a super lattice buffer layer (208) located on the n-doped GaN layer (206); multiple quantum well layers (210) located on the supper lattice buffer layer (208); a p-doped GaN layer (214/216) located over the multiple quantum well layers (210); and first and second electrodes (242, 240), the first electrode (242) being in direct electrical contact with the n-doped GaN layer (206) and the second electrode (240) being in electrical contact with the p-doped GaN layer (214/216), wherein the oxidized region (236) includes corresponding layers as the pixel (232), but partially oxidized so that the oxidized region is a dielectric.

2. The device of Claim 1 , wherein a corresponding n-doped GaN layer of the oxidized region is not oxidized.

3. The device of Claim 1 , wherein a corresponding n-doped GaN layer of the oxidized region is partially oxidized.

4. The device of Claim 1 , wherein a corresponding super lattice buffer layer of the oxidized region is fully oxidized.

5. The device of Claim 1 , wherein a diameter of the pixel is about 2 pm.

6. The device of Claim 1 , wherein the superlattice buffer layer includes an InGaN layer and a GaN layer.

7. The device of Claim 1 , wherein each of the multiple quantum well layers includes an InGaN layer and a GaN layer, which are configured to emit the green light.

8. The device of Claim 1 , wherein the p-doped GaN layer includes a low temperature p-GaN layer and a high temperature p-GaN layer.

9. The device of Claim 8, further comprising: an electron blocking layer sandwiched between the low temperature p-GaN layer and the high temperature p-GaN layer.

10. The device of Claim 1 , further comprising: an additional pixel (232) located adjacent to the pixel, and having a lateral surface fully enclosed by the oxidized region (236).

1 1 . A method (100) for making a green light emitting micro-light emitting device (micro-LED) (300), the method (100) comprising: providing a wafer (200) having an n-doped GaN layer (206), a super lattice buffer layer (208) located on the n-doped GaN layer (206), multiple quantum well layers (210) located on the supper lattice buffer layer (208), and a p-doped GaN layer (214/216) located over the multiple quantum well layers (210); depositing (104) a protective SiO2 layer over the p-doped GaN layer (214/26); patterning (106) the protective SiO2 layer to define a pixel (232); and applying selective thermal oxidation (108) to the wafer (200) in open atmosphere to form an oxidized region (236) that fully encloses a lateral surface of the pixel (232).

12. The method of Claim 11 , wherein the step of applying selective thermal oxidation is performed at about 900 °C.

13. The method of Claim 12, wherein the step of applying selective thermal oxidation is performed for about 4 h.

14. The method of Claim 11 , further comprising: removing the protective SiC>2 layer to expose the pixel.

15. The method of Claim 14, further comprising: forming electrodes on the n-doped GaN layer and the p-doped GaN layer.

16. The method of Claim 15, further comprising: cutting the wafer to obtain individual pixels.

17. The method of Claim 11 , wherein the oxidized region (236) includes corresponding layers as the pixel (232), but partially oxidized so that the oxidized region is a dielectric.

18. The method of Claim 11 , wherein a corresponding n-doped GaN layer of the oxidized region is not oxidized, or is only partially oxidized.

19. The method of Claim 11 , wherein the p-doped GaN layer includes a low temperature p-GaN layer and a high temperature p-GaN layer.

20. The method of Claim 19, further comprising: forming an electron blocking layer between the low temperature p-GaN layer and the high temperature p-GaN layer.