[go: up one dir, main page]

WO2025195689A1 - Support de composant et procédé de fabrication du support de composant - Google Patents

Support de composant et procédé de fabrication du support de composant

Info

Publication number
WO2025195689A1
WO2025195689A1 PCT/EP2025/053851 EP2025053851W WO2025195689A1 WO 2025195689 A1 WO2025195689 A1 WO 2025195689A1 EP 2025053851 W EP2025053851 W EP 2025053851W WO 2025195689 A1 WO2025195689 A1 WO 2025195689A1
Authority
WO
WIPO (PCT)
Prior art keywords
encapsulating material
component
component carrier
cavity
electrically conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/EP2025/053851
Other languages
English (en)
Inventor
Nina WANG
Artan Baftiri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&S Austria Technologie und Systemtechnik AG
Original Assignee
AT&S Austria Technologie und Systemtechnik AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&S Austria Technologie und Systemtechnik AG filed Critical AT&S Austria Technologie und Systemtechnik AG
Publication of WO2025195689A1 publication Critical patent/WO2025195689A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H10W20/40—
    • H10W42/20—
    • H10W70/092—
    • H10W70/614—
    • H10W70/65—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09918—Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10515—Stacked components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/1053—Mounted components directly electrically connected to each other, i.e. not via the PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1305—Moulding and encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
    • H10W72/9413—

Definitions

  • Component carrier and method for manufacturing the component carrier
  • the invention relates to a component carrier that comprises a stack with a cavity, and a component embedded in said cavity. Exposed connecting elements of the component are connected to exposed conductive structures at the bottom of the cavity through an interconnection structure. A first encapsulating material and a second encapsulation material interface at a boundary region. Further, a method to manufacture the component carrier is described.
  • the invention may relate to the technical field of component carriers, such as printed circuit boards or IC substrates, and their manufacture.
  • component carriers equipped with one or more electronic components and increasing miniaturization of such electronic components as well as a rising number of electronic components to be mounted on the component carriers such as printed circuit boards
  • increasingly more powerful array-like components or packages having several electronic components are being employed, which have a plurality of contacts or connections, with ever smaller spacing between these contacts.
  • Removal of heat generated by such electronic components and the component carrier itself during operation becomes an increasing issue.
  • an efficient protection against electromagnetic interference (EMI) becomes an increasing issue.
  • component carriers shall be mechanically robust and electrically and magnetically reliable so as to be operable even under harsh conditions.
  • substrates e.g. a motherboard with additional modules/components embedded in and/or mounted thereon
  • substrates are getting larger and implement more functionalities, which may be realized by assembling together a plurality of different modules. These modules may have different densities, so that integration may be challenging.
  • FIG. 7 shows a conventional example of an (ultra) large substrate 200.
  • a motherboard 201 with three layers that comprises an embedded substrate 210.
  • an interposer 260 with a semiconductor chip 262 thereon. While the embedded substrate 210 comprises large electric contacts 211, the interposer 260 comprises small electric contacts. This structure is quite large and electric contacting therein may not be optimal.
  • a component carrier and a method of manufacturing are described.
  • a (large, in particular ultra large) component carrier having a stack comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure, the component carrier comprising: i) a cavity formed in the stack (in particular at a main surface), ii) at least one electrically conductive structure (e.g. a pad) exposed at the bottom of the cavity, iii) at least one component (an electronic component or a layer stack (acting as a component carrier)) embedded in the cavity, wherein the component has at least one exposed connecting element (e.g. a pad) facing the at least one exposed electrically conductive structure, iv) an interconnection structure (e.g.
  • a pillar arranged between the bottom of the cavity and the at least one component, wherein the interconnection structure connects the at least one exposed electrically conductive structure and the at least one exposed connecting element (thermally/electrically), v) a first encapsulating material, arranged at the bottom of the cavity, and encapsulating the interconnecting structure and/or a first portion of the component, and vi) a second encapsulating material, encapsulating a second portion of the component.
  • the first encapsulating material and the second encapsulating material are in contact with each other and define a boundary region (in particular arranged between the component and the cavity; in the horizontal direction).
  • a method of manufacturing a component carrier having a stack comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure comprising: i) forming a cavity in the stack, so that at least one electrically conductive structure is exposed at the bottom of the cavity, ii) embedding at least one component in the cavity, wherein the at least one component has at least one exposed connecting element facing the at least one exposed electrically conductive structure, iii) arranging an interconnection structure between the bottom of the cavity and the component, wherein the interconnection structure connects the at least one exposed electrically conductive structure and the at least one exposed connecting element, iv) encapsulating the interconnecting structure and/or a first portion of the component by a first encapsulating material, and v) encapsulating a second portion of the component by a second encapsulating material.
  • the first encapsulating material and the second encapsulating material are in contact with each other and define a boundary region.
  • the term "connecting element” may refer to an electrically conductive body being configured to electrically and/or mechanically connect different (vertical) layers of the stack.
  • the connecting element may comprise metal, in particular copper, silver or nickel.
  • the connecting element may have a cylindrical shape or a frustoconical shape.
  • the connecting element may be configured to (electrically) connect the main surface of the component carrier with a central portion of the stack, for example an inner layer, or a component embedded in the stack.
  • the term "interconnecting structure” may refer to a structure suitable to electrically/thermally interconnect electric contacts of a component and electric contacts of a stack, in particular at a cavity bottom.
  • the interconnecting structure may extend in the vertical direction, in particular through a sheet of first encapsulating material.
  • the interconnecting structure may be implemented as a copper pillar.
  • the interconnecting structure may be copper bumps with tin or copper bumps with nickel and tin or tin balls or nano wires or pure metal bonding structure.
  • the term "encapsulating material” may in particular refer to a material, in particular a resin/mold material, suitable to at least partially encapsulate at least one of a cavity bottom, a cavity sidewall, and a component.
  • the encapsulating material may be at least partially uncured/flowable, when applied.
  • the second encapsulating material may (fully) encapsulate the component in the cavity by flowing into the cavity.
  • the second encapsulating material may be provided by lamination of a stack material.
  • the first encapsulating material may flow in one embodiment into the cavity.
  • the first encapsulating material may be provided as an intermediate sheet that is directly placed in the cavity.
  • the first and second encapsulating material may separately encapsulate the component and/or the interconnection structure and may thereby provide a solution to have a good gap filling for the double side connection in the cavity.
  • it realizes the double side connection of component carrier with the bottom side and top side of components as it can totally fill the gap of interconnection structures of component and the interconnection structure at the bottom of cavity (with the conventional method or structure, it may always cause voids at the bottom of cavity). Therefore it may ensure the good electrical connection at the bottom side for the components and the component carriers.
  • component carrier may refer to a final component carrier product as well as to a component carrier preform (i.e. a component carrier in production, in other words a semi-finished product).
  • a component carrier preform may be a panel that comprises a plurality of semi-finished component carriers that are manufactured together. At a final stage, the panel may be separated into the plurality of final component carrier products.
  • the component carrier "stack” comprises at least one electrically insulating layer structure and at least one electrically conductive layer structure.
  • the component carrier may be a laminate of the mentioned electrically insulating layer structure(s) and electrically conductive layer structure(s), in particular formed by applying mechanical pressure and/or thermal energy.
  • the mentioned stack may provide a plate-shaped component carrier capable of providing a large mounting surface for further components.
  • the stack may be nevertheless very thin and compact.
  • the stack may be very thick for a high density product.
  • the stacking direction (height/thickness) may be arranged in the vertical direction z. Further, the stacking direction may be perpendicular to the two directions of main extension (along x and y) of the (plate-shaped) component carrier.
  • all layers of the component carrier may form the stack. In another example, only a part of the layers of the component carrier form the stack.
  • layer structure may in particular refer to a continuous or discontinuous layer (or separated islands within the same plane) of electrically conductive or electrically insulating material. A plurality of such layers, parallel stacked one upon the other, may form the stack in the vertical direction.
  • the invention may be based on the idea that an efficient and robust architecture for a large component carrier may be provided, when a component is embedded in a cavity of a stack, thereby interconnecting electric contacts of the component and electric contacts of the stack by an interconnection structure, and the component is protected by a first encapsulating material and a second encapsulating material.
  • large components such as substrates, layer stack, etc.
  • a large component carrier e.g. a motherboard
  • further components may be surface-mounted and (electrically) connected to the component (and/or the stack), thereby enabling double side interconnection.
  • a thin total thickness with shorter integration paths may be provided.
  • a robust, design-flexible, and thin component carrier may be yielded.
  • the at least one exposed electrically conductive structure at the bottom of the cavity comprises at least one pad and/or at least one protruding conductive portion.
  • an efficient and reliable electrical or thermal connection may be established.
  • the exposed electrically conductive structure may be further connected to conductive layer structures in the stack, thereby enabling an efficient electric/thermal connection of the component to further functionalities of the stack.
  • the invention may provide a solution by forming a protrusion on the pads, so it may not only resolve the problem of connection quality but may also provide a lower cost solution.
  • the at least one exposed connecting element of the component comprises a pad and/or at least one protruding conductive portion. Also in this configuration, an efficient and reliable electrical/thermal connection may be enabled.
  • the component may already comprise these pads/protrusions, so that the component can be directly connected to the interconnection structures without further effort.
  • the interconnection structure comprises a vertical electrically conductive connection structure. This may provide the advantage that a robust and reliable connection of the component and the stack can be realized. Due to the vertical extension, the interconnection structures may be especially suitable to protrude through openings in the first encapsulating material.
  • the encapsulating material may be designed with a pattern with opening advanced. Due to the predesigned opening structure of encapsulating material, the alignment between the opening and the interconnection structure may be guaranteed and the encapsulating material can be totally filling in the gaps of interconnection structure of cavity bottom of component carrier.
  • the vertical electrically conductive connection structure comprises at least one of the following: a pillar, a solder material, a nanowire, a spongy structure, a rubber containing solder material, two or more portions being different from each other or same to each other, in particular defined a step-like structure.
  • the first encapsulating material is in contact with the (entire) lateral surface of the at least one exposed electrically conductive structure at the bottom of the cavity. In an embodiment, the first encapsulating material is in contact with the (entire) lateral surface of the at least one exposed connecting structure. In an embodiment, the first encapsulating material is in contact with the (entire) lateral surface of the interconnection structure. Depending on the desired application, one or more of these configurations may be applied. The first encapsulating material may provide additional protection for the electrical interconnections.
  • the first encapsulating material may ensure reliable adhesion to the exposed electrically conductive structure and thus reduces the risk of delamination between the respective materials and/or constituents.
  • the first encapsulating material is in contact with at least a portion of the lateral/bottom surface of the component and/or with at least a portion of the lateral surface of the cavity.
  • the first encapsulating material may extend from one lateral surface of the cavity (sidewall) to the other.
  • the lateral surface of the component may be contacted.
  • a (direct/physical) contact with the first encapsulating material may increase the stability within the cavity.
  • the first encapsulating material is at least partially cured before the provision of the second encapsulating material, in particular defining the structure of the boundary region.
  • the first encapsulating material may be produced and transported as a separate inlay. Openings for the interconnection structures may be formed (e.g. by drilling) in said inlay. This may ensure the full filling of the gaps at the cavity bottom.
  • the first encapsulating material should be at least partially cured.
  • the second encapsulating material may be rather provided into the cavity in an (at least partially) flowable state, thus being less cured than the first encapsulating material.
  • the interface of encapsulating materials of different curing states may be visible in the final product, thereby reflecting the manufacture step of providing the first encapsulating material in a more cure state than the second encapsulating material.
  • the second encapsulating material comprises an electrically insulating layer structure being part of the stack, in particular comprising stack material. This may provide the advantage that the second encapsulating material can be formed in the same process, (essentially) without using different materials. Meanwhile, the second encapsulating material may flow into the gap of the cavity and the gap of the interconnection structure of the components and then fill all the gaps (essentially) without void in this manner.
  • the component carrier further comprises a centering element (e.g. an alignment structure such as an alignment pin), arranged in the cavity, wherein the centering element is associated with the first encapsulating material (in particular extend/protrudes through the first encapsulating material).
  • a centering element e.g. an alignment structure such as an alignment pin
  • the centering element is associated with the first encapsulating material (in particular extend/protrudes through the first encapsulating material).
  • the centering element can also help provide the alignment mark for the component mounting on the interconnection structure of cavity bottom of the component carrier accurately without shift, so it can have a good electrical conductivity for signal transmission.
  • the centering element comprises a protrusion, in particular a pin or a bump. In an embodiment, the centering element comprises a recess, in particular an opening.
  • the centering element is a protruding element that may pass through an opening of the first encapsulating material. In a second example, the centering element itself may be formed as an opening/recess into which a protruding portion of the first encapsulating material may be introduced.
  • PCB related manufacturing methods may allow the creation of centering elements with a high precision and in a highly efficient manner and/or throughput.
  • the centering element can be a pattern on the component carrier, for example at least one pad on the top main surface of the component carrier. This may provide the advantage that the manufacturing process can be reduced by using the original pattern of the component carrier.
  • the centering element can be formed in the stack, for example formed in the stack on the same (vertical) level as the cavity bottom surface.
  • the centering element is configured to protrude inside/through the first encapsulating material. In an embodiment, the centering element is configured to be at least partially filled by the first encapsulating material. Here, it is again referred to the two examples described above. In an embodiment, the centering element is a recess where a protrusion of the first encapsulating material inserted before full curing. During manufacture, the protruding centering element may be selectively recognized by the manufacturing apparatus and thus may enhance the accuracy the manufacture of the component carrier.
  • the centering element is made of the material of the at least one exposed electrically conductive structure, in particular provided on a portion of said at least one exposed electrically conductive structure.
  • the centering element 170 can be formed directly on the exposed electrically conductive structure. This may provide the advantage that the centering element can be directly plated on the exposed electrically conductive structure, thereby making the manufacture straightforward (compare Figure 6C).
  • At least a portion of the centering element is made of the material of the interconnection structure. This may provide the advantage that both structures may be manufactured from the same material, eventually in the same (plating) process. Thereby, costs and efforts may be saved.
  • the centering element comprises a step-like shape.
  • a bottom part of the centering element may have a larger diameter/width than an upper part of the centering element.
  • the step structure may serve for an easier alignment (first aligned to the thin part and then aligned to the thick part).
  • the centering element comprises an extremity at a vertical height being different from a further vertical height defined by one of the extremities of the interconnection structure.
  • the centering element e.g. alignment pin
  • the interconnection structure e.g. pillar
  • the centering element is provided outside of the cavity. Such an embodiment may help to correctly align the first encapsulating material already before entering the cavity.
  • the portion of the first encapsulating material arranged between the component and the bottom of the cavity comprises a first surface being in contact with the component and a second, opposed, surface being in contact with the bottom of the cavity.
  • the two opposed surfaces have a different roughness. This may provide the advantage that the first encapsulating material serves as a robust support structure, filling the space between component and bottom of cavity. There may be good adhesion between the two encapsulating materials.
  • the component after the component is embedded in the cavity, there can be a dry desmear process to treat the exposed first encapsulating material (roughening the surface) to increase the adhesion with the second encapsulating material, which will encapsulate the gaps of the cavity after the component embedding.
  • the interface of the two materials may comprise the undulation and the second encapsulating material will fill the recess of the first encapsulating material. Then, the peak area of the first encapsulating material will penetrate into the second encapsulating material.
  • the second surface is rougher than the first surface. This may enable a better adhesion to electrically conductive layer structures.
  • the first encapsulating material and the second encapsulating material comprise the same or have a common composition. This may provide the advantage that costs and efforts can be saved, since comparable materials (and processes) may be applied. Further, comparable material may have a better integrity, e.g. regarding thermal expansion. It may reduce the delamination or crack risk due to the CTE mismatch issue.
  • the boundary region comprises an irregular shape, in particular an undulating shape.
  • a structural feature may be typical for an interface between two encapsulating materials, wherein one of them is more cured than the other.
  • the first encapsulating material may have a (partially cured) rough surface and the second encapsulating material may flow around the ridges and valleys, thereby becoming adapted to the irregular shape. Therefore, the two layers may be penetrated with each other, the interface may have two material emerged with each other.
  • the first (and/or second) encapsulating material comprises a resin with fillers (particles), in particular a fiber-free resin, or a resin with glass fiber.
  • a resin with fillers particles
  • Ajinomoto build-up film may be used.
  • Resins with fillers instead of fibers may flow in a more flexible way, but may still provide sufficient robustness. Thereby, an efficient encapsulation may be provided.
  • the cavity and the embedded component are arranged in a core layer structure.
  • a core layer structure e.g. fully cured (enforced) resin, metal, glass, ceramic, etc.
  • a robust structure well suitable for embedded components may be increased.
  • the cavity and the embedded component are arranged in the build-up layer structure of the stack. Thereby, the design flexibility may be increased.
  • the cavity can be formed through a build-up layer structure (portion).
  • a build-up structure may end at the core layer structure or in the core layer structure.
  • the build-up structure may extend (at least partially) through the core layer structure (to a further build-up structure). Thereby, deep cavity formation may be realized.
  • the method further comprises: providing a first encapsulating material preform (intermediate sheet, inlay), and forming an opening, in particular using drilling, more in particular mechanical drilling or laser drilling, in the first encapsulating material preform.
  • a first opening is for the interconnection structure and/or a second opening is for a centering element.
  • the first encapsulating material may be pre-prepared as a separate inlay to be placed in the cavity (so that the interconnection structures/centering elements protrude through the openings). Thereby, an efficient and accurate placement into the cavity may be enabled.
  • This method may realize a big form factor component carrier for high performance computing.
  • the method further comprises: placing the first encapsulating material preform in the cavity, so that the interconnection structure passes through the first opening and/or the centering element passes through the second opening.
  • the first encapsulating material and/or the second encapsulating material preform comprises at least one of an uncured resin, a partially cured resin, ABF, PP (polypropylene), NCF (non-conductive film), photo imageable dielectric (PID), a further molding material.
  • ABF uncured resin
  • PP polypropylene
  • NCF non-conductive film
  • PID photo imageable dielectric
  • the first encapsulating material is at least partially cured before the provision of the second encapsulating material.
  • this process step may lead to a boundary region that reflects the advantageous manufacture process: the first encapsulating material is placed in the cavity in a partially cured state to enable the interconnection structure to extend through.
  • the second encapsulating material may be provided e.g. by laminating (like stack material).
  • the component carrier is shaped as a plate. This contributes to the compact design, wherein the component carrier nevertheless provides a large basis for mounting components thereon. Furthermore, in particular a bare die as example for an embedded electronic component, can be conveniently embedded, thanks to its small thickness, into a thin plate such as a printed circuit board.
  • the component carrier is configured as one of the group consisting of a printed circuit board, a substrate (in particular an IC substrate), and an interposer.
  • the term "printed circuit board” may particularly denote a plate-shaped component carrier which is formed by laminating several electrically conductive layer structures with several electrically insulating layer structures, for instance by applying pressure and/or by the supply of thermal energy.
  • the electrically conductive layer structures are made of copper
  • the electrically insulating layer structures may comprise resin and/or glass fibers, so-called prepreg or FR4 material.
  • the various electrically conductive layer structures may be connected to one another in a desired way by forming holes through the laminate, for instance by laser drilling or mechanical drilling, and by partially or fully filling them with electrically conductive material (in particular copper), thereby forming vias or any other through-hole connections.
  • the filled hole either connects the whole stack, (through-hole connections extending through several layers or the entire stack), or the filled hole connects at least two electrically conductive layers, called via.
  • optical interconnections can be formed through individual layers of the stack in order to receive an electro-optical circuit board (EOCB).
  • EOCB electro-optical circuit board
  • a printed circuit board is usually configured for accommodating one or more components on one or both opposing surfaces of the plate-shaped printed circuit board. They may be connected to the respective main surface by soldering.
  • a dielectric part of a PCB may be composed of resin with reinforcing fibers (such as glass fibers).
  • a substrate may particularly denote a small component carrier.
  • a substrate may be a, in relation to a PCB, comparably small component carrier onto which one or more components may be mounted and that may act as a connection medium between one or more chip(s) and a further PCB.
  • a substrate may have substantially the same size as a component (in particular an electronic component) to be mounted thereon (for instance in case of a Chip Scale Package (CSP)).
  • CSP Chip Scale Package
  • a substrate can be understood as a carrier for electrical connections or electrical networks as well as component carrier comparable to a printed circuit board (PCB), however with a considerably higher density of laterally and/or vertically arranged connections.
  • Lateral connections are for example conductive paths, whereas vertical connections may be for example drill holes.
  • These lateral and/or vertical connections are arranged within the substrate and can be used to provide electrical, thermal and/or mechanical connections of housed components or unhoused components (such as bare dies), particularly of IC chips, with a printed circuit board or intermediate printed circuit board.
  • the term "substrate” also includes "IC substrates".
  • a dielectric part of a substrate may be composed of resin with reinforcing particles (such as reinforcing spheres, in particular glass spheres).
  • the term "inorganic layer structure” may particularly denote a layer structure which comprises inorganic material, such as an inorganic compound.
  • dielectric material of the inorganic layer structure or even the entire inorganic layer structure may be made exclusively or at least substantially exclusively from inorganic material.
  • the inorganic layer structure may comprise inorganic dielectric material and additionally another dielectric material.
  • An inorganic compound may be a chemical compound that lacks carbon-hydrogen bonds or a chemical compound that is not an organic compound.
  • the inorganic layer structure may comprise glass, for example silicon base glass, in particular soda lime glass, and/or boro-silicate glass and/or alumo-silicate glass and/or lithium silicate glass and/or alkaline free glass.
  • the inorganic layer structure may comprise ceramic material, for example aluminum nitride and/or aluminum oxide and/or silicon nitride and/or boron nitride and/or tungsten comprising ceramic material.
  • the inorganic layer structure may comprise semiconducting material, for example silicon and/or germanium and/or silicon oxide and/or germanium oxide and/or silicon carbide and/or gallium nitride.
  • the inorganic layer structure may comprise (elemental) metal and/or metal alloys, for example, copper and/or tin and/or bronze.
  • the inorganic layer structure may comprise inorganic material, which is not listed in the above mentioned example, such as: MoS2, CuGaO2, AgAIO2, LiGaTe2, AgInSe2, CuFeS2, BeO.
  • the substrate or interposer may comprise or consist of at least a layer of glass, silicon (Si) and/or a photoimageable or dry-etchable organic material like epoxy-based build-up material (such as epoxy-based buildup film) or polymer compounds (which may or may not include photo- and/or thermosensitive molecules) like polyimide or polybenzoxazole.
  • the at least one electrically insulating layer structure (and/or the curable dielectric elements) comprises at least one of the group consisting of a resin or a polymer, such as epoxy resin, cyanate ester resin, benzocyclobutene resin, bismaleimide-triazine resin, polyphenylene derivate (e.g.
  • polyphenylenether PPE
  • polyimide PI
  • polyamide PA
  • liquid crystal polymer LCP
  • polytetrafluoroethylene PTFE
  • PVDF polyvinylidene fluoride
  • Reinforcing structures such as webs, fibers, spheres or other kinds of filler particles, for example made of glass (multilayer glass) in order to form a composite, could be used as well.
  • a semi-cured resin in combination with a reinforcing agent, e.g. fibers impregnated with the above-mentioned resins is called prepreg.
  • These prepregs are often named after their properties e.g. FR4 or FR5, which describe their flame retardant properties.
  • prepreg particularly FR4 are usually preferred for rigid PCBs
  • other materials in particular epoxy-based build-up materials (such as build-up films) or photoimageable dielectric materials, may be used as well.
  • high-frequency materials such as polytetrafluoroethylene, liquid crystal polymer and/or cyanate ester resins, may be preferred.
  • low temperature cofired ceramics (LTCC) or other low, very low or ultra-low DK materials may be applied in the component carrier as electrically insulating structures.
  • the at least one electrically conductive layer structure comprises at least one of the group consisting of copper, aluminum, nickel, silver, gold, palladium, tungsten, carbon, platinum, (doped) silicon, and magnesium.
  • copper is usually preferred, other materials or coated versions thereof are possible as well, in particular coated with supra-conductive material or conductive polymers, such as graphene or poly(3,4-ethylenedioxythiophene) (PEDOT), respectively.
  • PEDOT poly(3,4-ethylenedioxythiophene)
  • At least one component may be embedded in the component carrier and/or may be surface mounted on the component carrier.
  • a component can be selected from a group consisting of an electrically non- conductive inlay, an electrically conductive inlay (such as a metal inlay, preferably comprising copper or aluminum), a heat transfer unit (for example a heat pipe), a light guiding element (for example an optical waveguide or a light conductor connection), an electronic component, or combinations thereof.
  • An inlay can be for instance a metal block, with or without an insulating material coating (IMS-inlay), which could be either embedded or surface mounted for the purpose of facilitating heat dissipation. Suitable materials are defined according to their thermal conductivity, which should be at least 2 W/mK.
  • Such materials are often based, but not limited to metals, metal-oxides and/or ceramics as for instance copper, aluminium oxide (AI2O3) or aluminum nitride (AIN).
  • metals metal-oxides and/or ceramics as for instance copper, aluminium oxide (AI2O3) or aluminum nitride (AIN).
  • AI2O3 aluminium oxide
  • AIN aluminum nitride
  • a component can be an active electronic component (having at least one p- n-junction implemented), a passive electronic component such as a resistor, an inductance, or capacitor, an electronic chip, a storage device (for instance a DRAM or another data memory), a filter, an integrated circuit (such as field-programmable gate array (FPGA), programmable array logic (PAL), generic array logic (GAL) and complex programmable logic devices (CPLDs)), a signal processing component, a power management component (such as a field-effect transistor (FET), metal- oxide-semiconductor field-effect transistor (MOSFET), complementary metal-oxide-semiconductor (CMOS), junction field-effect transistor (JFET), or insulated-gate field-effect transistor (IGFET), all based on semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (Ga2O3), indium gallium arsen
  • a magnetic element can be used as a component.
  • a magnetic element may be a permanent magnetic element (such as a ferromagnetic element, an antiferromagnetic element, a multiferroic element or a ferrimagnetic element, for instance a ferrite core) or may be a paramagnetic element.
  • the component may also be a IC substrate, an interposer or a further component carrier, for example in a board-in-board configuration.
  • the component may be surface mounted on the component carrier and/or may be embedded in an interior thereof.
  • other components in particular those which generate and emit electromagnetic radiation and/or are sensitive with regard to electromagnetic radiation propagating from an environment, may be used as component.
  • the component carrier is a laminate-type component carrier.
  • the component carrier is a compound of multiple layer structures which are stacked and connected together by applying a pressing force and/or heat.
  • an electrically insulating solder resist may be applied to one or both opposing main surfaces of the layer stack or component carrier in terms of surface treatment. For instance, it is possible to form such a solder resist on an entire main surface and to subsequently pattern the layer of solder resist so as to expose one or more electrically conductive surface portions which shall be used for electrically coupling the component carrier to an electronic periphery. The surface portions of the component carrier remaining covered with solder resist may be efficiently protected against oxidation or corrosion, in particular surface portions containing copper.
  • Such a surface finish may be an electrically conductive cover material on exposed electrically conductive layer structures (such as pads, conductive tracks, etc., in particular comprising or consisting of copper) on a surface of a component carrier. If such exposed electrically conductive layer structures are left unprotected, then the exposed electrically conductive component carrier material (in particular copper) might oxidize, making the component carrier less reliable.
  • a surface finish may then be formed for instance as an interface between a surface mounted component and the component carrier. The surface finish has the function to protect the exposed electrically conductive layer structures (in particular copper circuitry) and enable a joining process with one or more components, for instance by soldering.
  • Examples for appropriate materials for a surface finish are Organic Solderability Preservative (OSP), Electroless Nickel Immersion Gold (ENIG), Electroless Nickel Immersion Palladium Immersion Gold (ENIPIG), gold (in particular hard gold), chemical tin, nickel-gold, nickel-palladium, etc.
  • OSP Organic Solderability Preservative
  • ENIG Electroless Nickel Immersion Gold
  • ENIPIG Electroless Nickel Immersion Palladium Immersion Gold
  • gold in particular hard gold
  • chemical tin nickel-gold, nickel-palladium, etc.
  • Figure 1A shows a cross-section of a component carrier and Figure IB shows a detailed portion of Figure 1A, according to an exemplary embodiment of the invention.
  • Figure 2 and Figure 3 respectively show a cross-section of a component carrier, according to an exemplary embodiment of the invention.
  • Figure 4 shows interconnection structures, according to an exemplary embodiment of the invention.
  • Figure 5 shows a first encapsulating material, according to an exemplary embodiment of the invention.
  • Figures 6A to 6G show a method of manufacturing a component carrier, according to an exemplary embodiment of the invention.
  • FIG. 7 shows a conventional ultra large substrate.
  • Figure 1 shows a cross-section of a component carrier, according to an exemplary embodiment of the invention.
  • the component carrier 100 (in this example a motherboard) has a stack 101 comprising electrically conductive layer structures 104 and electrically insulating layer structures 102.
  • a cavity 156 is formed in the electrically insulating layer structures 102 that embed a plurality of electrically conductive blind vias 104, stacked on onto each other.
  • the component carrier 100 of this example is an ultra large substrate that comprises three modules.
  • the upper module comprises a cavity 156 with an embedded component 110.
  • the middle module comprises a core layer structure 103, and the lower module comprises a redistribution layer structure 105.
  • the cavity 156 is formed at the upper main surface of the stack 101.
  • a plurality of electrically conductive structures 155 are exposed at the bottom of the cavity 156.
  • a component 110 (that can be a substrate/component carrier) is embedded in the cavity 156, wherein the component 110 has a plurality of exposed connecting elements 111 facing the plurality of exposed electrically conductive structures 155, respectively.
  • the term "facing" may refer to the orientation/alignment of the exposed connecting elements 111 and the exposed electrically conductive structures 155 with respect to each other.
  • the bottom side of the exposed connecting elements 111 may be oriented towards the top side of the exposed electrically conductive structures 155.
  • at least part of the area of the exposed connecting elements 111 may overlap with at least part of the exposed electrically conductive structure 155.
  • a plurality of interconnection structures 150 are arranged between the bottom of the cavity 156 and the at least one component 110, wherein the interconnection structure 150 connects the plurality of exposed electrically conductive structures 155 and the plurality of exposed connecting elements 111, respectively.
  • solder (Sn) bumps are arranged between the interconnection structures 150 and the exposed connecting elements 111, respectively. In another embodiment, these structures can be connected without the bumps.
  • a first encapsulating material 120 (here provided as an inlay, e.g. a molding film) is arranged at the bottom of the cavity 156 and encapsulates the interconnecting structure 150 and a first portion of the component 110.
  • the first encapsulating material 120 is in contact with the entire lateral surfaces of the exposed electrically conductive structures 155 at the bottom of the cavity 156, the exposed connecting structures 111, and the interconnection structure 150.
  • the first encapsulating material 120 is in contact with a (very small) portion of the lateral surface of the component 110 and with a portion of the lateral surface of the cavity 156.
  • the first encapsulating material 120 may be in contact with the exposed connecting structure 111.
  • the first encapsulating material 120 is in contact with the exposed electrically conductive structures 155 or the interconnection structure 150.
  • the first encapsulating material 120 can comprise a resin with fillers (a fiber-free resin), e.g. ABF, or a resin with glass fiber.
  • the first encapsulating material 120 comprises epoxy resin and/or poly (meth) acrylate.
  • a second encapsulating material 130 encapsulates a second portion of the component 110, wherein the first encapsulating material 120 and the second encapsulating material 130 are in contact with each other and define a boundary region 140 (interface).
  • the second encapsulating material 130 is in contact with the sidewall of the component 110 and optionally at least one, in particular two, main surface(s).
  • the second encapsulating material 130 may be different from the first encapsulating material 120.
  • the first encapsulating material 120 and the second encapsulating material 130 may comprise similar material.
  • main surface of a body may particularly denote one of two largest opposing surfaces of the body.
  • the main surfaces may be connected by circumferential side walls.
  • the thickness of a body, such as a stack, may be defined by the distance between the two opposing main surfaces.
  • the first encapsulating material 120 is at least partially cured before the provision of the second encapsulating material 130, thus defining the structure of the boundary region 140.
  • the boundary region 140 comprises an irregular shape such as an undulating shape.
  • the component 110 further comprises top exposed connecting elements 112 for connection to a further device.
  • the component carrier 100 further comprises a centering element 170, arranged in the cavity 156, and on an exposed electrically conductive structure 155, wherein the centering element 170 is associated with the first encapsulating material 120 (extending/protruding through the first encapsulating material 120).
  • the centering element 170 comprises a protrusion, here an alignment pin.
  • the centering element 170 comprises an extremity at a vertical height being different from a further vertical height defined by one of the extremities of the interconnection structure 150 (the centering element 170 is longer than the other interconnection structures 150).
  • the centering element 170 may comprise similar, in particular the same, material as the interconnection structure 150 and/or the exposed electrically conductive structure 155. In an example, the centering element 170 may be in contact with the first encapsulating material 120. Additionally, the centering element 170 may be in contact with the second encapsulating material 130.
  • Figure IB shows in detail the interface (boundary region) 140 between the first encapsulating material 120 and the second encapsulating material 130. Directly above the centering element 170, there is no component 110 arranged.
  • Figure 2 shows the upper module with the cavity 156 and the embedded component 110 without the first encapsulating material 120 and the second encapsulating material 130, according to an exemplary embodiment of the invention.
  • Figure 3 shows an embodiment of the component carrier 100, according to an exemplary embodiment of the invention, whereby two additional components 160, 162 (electronic components or layer stacks) are arranged on the main surface of the stack 101 and the cavity 156 (surface-mounted). It can be seen that electric contacts 161, 163 of the components 160, 162 are connected with the top exposed connecting elements 112 of the embedded component 110, thus enabling a double side interconnection of the component 110.
  • This structure can provide a high density component carrier to fulfil the requirement of miniaturization and big form factor for the high performance computing.
  • Figure 4 shows a top view on interconnection structures 150, according to an exemplary embodiment of the invention.
  • the electrically insulating layer structures 102 there is formed the cavity 156, and at the bottom of said cavity 156, there are arranged the exposed electrically conductive structures 155.
  • the interconnection structure 150 In the middle/center of each exposed electrically conductive structure 155, there is arranged an interconnection structure 150. Further, it can be seen that three of the four corners respectively comprise a centering element 170 (alignment pin).
  • Figure 5 shows a first encapsulating material 120, according to an exemplary embodiment of the invention.
  • the first encapsulating material 120 is hereby configured as a transportable inlay/intermediate sheet (at least partially cured) to be placed at the bottom of the cavity, so that the interconnection structures 150 protrude through.
  • the first encapsulating material 120 comprises a plurality of openings 121 for the interconnection structures 150 and three openings (in the corners) for the centering elements 170.
  • the openings 121, 122 can be formed e.g. by laser cutting through an insulating material such as ABF or a molding film. If it is PID, it can be formed by exposure.
  • Figures 6A to 6G show a method of manufacturing a component carrier 100, according to an exemplary embodiment of the invention.
  • a stack 101 (for providing a motherboard) comprises at the upper main surface and at the lower main surface exposed electrically conductive structures 155, respectively.
  • a mask material 180 is provided, the mask material can be photo sensitive material (e.g. formed by DFR lamination, then following with DFR exposure, DFR developing, etc.), so that in a subsequent step the interconnection structures 150 can be formed by plating on top of the exposed electrically conductive structures 155.
  • the mask material can be photo sensitive material (e.g. formed by DFR lamination, then following with DFR exposure, DFR developing, etc.), so that in a subsequent step the interconnection structures 150 can be formed by plating on top of the exposed electrically conductive structures 155.
  • Figure 6C a second mask material 181 is applied on top of the mask material 180), so that in a subsequent step the centering element 170 can be formed by plating on top of one exposed electrically conductive structure 155, the centering element 170 can have same or different height from the interconnection structures 150 (the higher the centering element, the interconnection structures may have better accuracy).
  • the mask material 180, 181 is stripped.
  • Figure 6D using lamination, an electrically insulating layer structure 102 is arranged on the stack 101. Before the electrically insulating layer structure, the release ink should be printed on and/or around the interconnection structure 150 and the centering element 170. Then, the ABF will be laminated on the whole surface, so the ink is also covered by ABF. This is for cavity formation. Afterwards, there may be vias formed and then a metal layer 106 is arranged (e.g. sputtering or eless plated) on the electrically insulating layer structure 102 and patterned in a further step.
  • a metal layer 106 is arranged (e.g. sputtering or eless plated) on the electrically insulating layer structure 102 and patterned in a further step.
  • Figure 6E using patterning of electrically conductive layer structures 104 and laminating electrically insulating layer structures 102, a build-up can be provided. Then, a laser is used to cut the cavity 156 out of the electrically insulating layer structures 102.
  • Figure 6F a portion of the electrically insulating layer structures 102 has been cut out (decap) and the ink material has been removed/stripped, thereby forming the cavity 156.
  • a surface finish ENEPIG
  • ENEPIG a surface finish
  • Figure 6G the first encapsulating material 120 of Figure 4 is placed into the cavity 156, so that the interconnection structures 150 respectively extend through the interconnection structure openings 121.
  • the alignment pin 170 extends through the centering element opening 122, thereby helping to accurately place the first encapsulating material 120 inlay.
  • the component 110 is placed in the cavity 156, so that exposed connecting elements of the components 110 are connected to the interconnection structures 150, respectively.
  • the second encapsulating material 130 is provided, forming a boundary region 140 at the interface with the more cured first encapsulating material 120.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Injection Moulding Of Plastics Or The Like (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

L'invention concerne un support de composant et un procédé de fabrication d'un support de composant. Le support de composant comporte un empilement comprenant au moins une structure de couche électroconductrice et au moins une structure de couche électriquement isolante, le support de composant comprenant : i) une cavité formée dans l'empilement ; ii) au moins une structure électroconductrice exposée au fond de la cavité ; iii) au moins un composant intégré dans la cavité, le composant ayant au moins un élément de connexion exposé faisant face à la ou aux structures électroconductrices exposées ; iv) une structure d'interconnexion, disposée entre le fond de la cavité et le ou les composants, la structure d'interconnexion connectant la ou les structures électroconductrices exposées et le ou les éléments de connexion exposés ; v) un premier matériau d'encapsulation, disposé au fond de la cavité, et encapsulant la structure d'interconnexion et/ou une première partie du composant ; et vi) un second matériau d'encapsulation, encapsulant une seconde partie du composant. Le premier matériau d'encapsulation et le second matériau d'encapsulation sont en contact l'un avec l'autre et définissent une région limite.
PCT/EP2025/053851 2024-03-21 2025-02-13 Support de composant et procédé de fabrication du support de composant Pending WO2025195689A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202410326192.9 2024-03-21
CN202410326192.9A CN120690790A (zh) 2024-03-21 2024-03-21 部件承载件及制造部件承载件的方法

Publications (1)

Publication Number Publication Date
WO2025195689A1 true WO2025195689A1 (fr) 2025-09-25

Family

ID=94687756

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2025/053851 Pending WO2025195689A1 (fr) 2024-03-21 2025-02-13 Support de composant et procédé de fabrication du support de composant

Country Status (2)

Country Link
CN (1) CN120690790A (fr)
WO (1) WO2025195689A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090189270A1 (en) * 2008-01-30 2009-07-30 Advanced Semiconductor Engineering, Inc. Manufacturing process and structure for embedded semiconductor device
US20170213794A1 (en) * 2016-01-22 2017-07-27 Samsung Electro-Mechanics Co., Ltd. Electronic component package and method of manufacturing the same
US20220319943A1 (en) * 2021-04-02 2022-10-06 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Embedding Methods for Fine-Pitch Components and Corresponding Component Carriers

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090189270A1 (en) * 2008-01-30 2009-07-30 Advanced Semiconductor Engineering, Inc. Manufacturing process and structure for embedded semiconductor device
US20170213794A1 (en) * 2016-01-22 2017-07-27 Samsung Electro-Mechanics Co., Ltd. Electronic component package and method of manufacturing the same
US20220319943A1 (en) * 2021-04-02 2022-10-06 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Embedding Methods for Fine-Pitch Components and Corresponding Component Carriers

Also Published As

Publication number Publication date
CN120690790A (zh) 2025-09-23

Similar Documents

Publication Publication Date Title
US12165964B2 (en) Component carrier with embedded interposer laterally between electrically conductive structures of stack and method for manufacturing the component carrier
EP4220710A1 (fr) Module comprenant un composant à base de semi-conducteur et son procédé de fabrication
US12495498B2 (en) Component carrier interconnection and manufacturing method
EP4221474A2 (fr) Support de composant avec incrustation de substrat de circuit intégré intégrée, et procédé de fabrication
US12322622B2 (en) Component carrier with gap around component core and filled with first material in bottom portion and with second material in top portion
US20250054820A1 (en) Component Carrier With Mounting Region for Mounting a Component
US20220310563A1 (en) Hybrid Core and Method of Manufacturing Component Carriers Using a Hybrid Core
WO2025195689A1 (fr) Support de composant et procédé de fabrication du support de composant
US20240332104A1 (en) Component Carrier With Reinforcement Layer Structure and Manufacturing Method Using Two Temporary Carriers
EP4615173A1 (fr) Support de composant avec composant incorporé dans de la résine et procédé de fabrication
EP4345895A1 (fr) Substrat de circuit intégré avec élément de pont intégré, agencement et procédé de fabrication
EP4554340A1 (fr) Support de composant doté de parties de résine s'écoulant distinctes, et procédé de fabrication
EP4622403A1 (fr) Composant, agencement de support de composant et procédé de fabrication du support de composant
US20250273555A1 (en) Component Carrier with Ultra-thin Insulation Film and Manufacturing Method
EP4489533A1 (fr) Support de composant et procédé de fabrication du support de composant
US20250301570A1 (en) Component Carrier and Method Manufacturing the Component Carrier
US20240422907A1 (en) Component Carrier With Continuously Extending Vertical Connection Structure, and Manufacturing Method
US20250071907A1 (en) Component Carrier With Embedded Interposer Laterally Between Electrically Conductive Structures of Stack
US20240021440A1 (en) Component Carrier and Method of Manufacturing the Same
US12041721B2 (en) Component carrier comprising at least two components
EP4576950A1 (fr) Support de composant avec des empilements reliés par une couche intermédiaire et procédé de fabrication
EP4247130A2 (fr) Support de composants avec liaison par empilement pour relier des composants
WO2024115565A1 (fr) Support de composant avec partie de renforcement et procédé de fabrication
EP4602650A1 (fr) Support de composant à structure thermique en saillie, et procédé de fabrication
EP4540857A1 (fr) Emballage et son procédé de fabrication

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 25706684

Country of ref document: EP

Kind code of ref document: A1