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WO2025182009A1 - Generation device, generation method, and generation program - Google Patents

Generation device, generation method, and generation program

Info

Publication number
WO2025182009A1
WO2025182009A1 PCT/JP2024/007541 JP2024007541W WO2025182009A1 WO 2025182009 A1 WO2025182009 A1 WO 2025182009A1 JP 2024007541 W JP2024007541 W JP 2024007541W WO 2025182009 A1 WO2025182009 A1 WO 2025182009A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
plan
generation
processor
streams
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/JP2024/007541
Other languages
French (fr)
Japanese (ja)
Inventor
淳也 加藤
朗 金丸
伸太郎 水野
正久 川島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
NTT Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NTT Inc filed Critical NTT Inc
Priority to PCT/JP2024/007541 priority Critical patent/WO2025182009A1/en
Publication of WO2025182009A1 publication Critical patent/WO2025182009A1/en
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]

Definitions

  • This disclosure relates to a generation device, a generation method, and a generation program.
  • Communications infrastructure with its strengths of ultra-low latency and massive connectivity, is expected to promote smart industrial processes such as remote factory control and distributed energy resource control. To achieve this, computing infrastructure must also be able to transfer and process data in deterministic time with ultra-low latency and support massive connectivity.
  • the time it takes to collect data from a real-world data source and complete processing such as AI (Artificial Intelligence) analysis must be kept deterministically below a specified value. Even when collecting data from multiple data sources at the same time and performing multi-dimensional analysis, the time it takes must be kept deterministically below a specified value.
  • AI Artificial Intelligence
  • one technique for improving the efficiency of packet sending and receiving is to divide large amounts of data received by the kernel or NIC (Network Interface Card) into smaller, more easily processed sizes, or to combine smaller pieces of processed data into smaller, more easily transmitted sizes (Non-Patent Document 1).
  • This disclosure has been made in light of the above circumstances, and its purpose is to provide technology that can improve the time required to process data in a storage area.
  • a generation device includes a generation unit that generates a data placement plan for placing data from multiple data streams with the same data period or similar data characteristics within a data stream group in contiguous storage areas, based on the arrival times of data from the data stream group that have been determined in advance.
  • a generation device generates a data placement plan that places data from multiple data streams with the same data period or similar data characteristics within a data stream group in contiguous storage areas based on the arrival times of data from the data stream group that have been determined in advance.
  • a generation program causes a computer to function as the generation device.
  • This disclosure provides technology that can reduce the time required to process data in a storage area.
  • FIG. 1 is a diagram showing an example of the overall configuration of a system according to this embodiment.
  • FIG. 2 is a diagram illustrating an example of the configuration of a video analysis system.
  • FIG. 3 is a diagram illustrating an example of a method for generating a data allocation plan and a data readout plan.
  • FIG. 4 is a diagram showing an example (first example) of processor arrangement.
  • FIG. 5 is a diagram showing an example (first example) of a data allocation plan and a data read plan.
  • FIG. 6 is a diagram showing an example (second example) of processor arrangement.
  • FIG. 7 is a diagram showing an example (second example) of a data allocation plan and a data read plan.
  • FIG. 8 is a diagram illustrating an example (third example) of processor arrangement.
  • FIG. 1 is a diagram showing an example of the overall configuration of a system according to this embodiment.
  • FIG. 2 is a diagram illustrating an example of the configuration of a video analysis system.
  • FIG. 3 is a
  • FIG. 9 is a diagram showing an example (third example) of a data allocation plan and a data read plan.
  • FIG. 10 is a diagram illustrating an example of a method for generating a data transfer plan.
  • FIG. 11 is a diagram showing a process flow for generating each plan.
  • FIG. 12 is a diagram showing a processing flow of a data stream.
  • FIG. 13 is a diagram illustrating a hardware configuration of the generation device.
  • This disclosure therefore attempts to build a real-time system that guarantees no fluctuations in waiting time or processing time.
  • optimization is performed to reduce processing waiting time and processor idle time, taking into account the I/O processing load on the storage area.
  • this is premised on the assumption that the data arrival time (including the data arrival time pattern) is known in advance.
  • Communication networks in which the data arrival time is known in advance are existing technology.
  • a data placement plan is generated that places data from multiple data streams (groups of data that flow intermittently over time) with the same data cycle or similar data characteristics in a contiguous storage area, and a data reading plan is generated in advance that bulks the data from the multiple data streams from that contiguous storage area and reads it all at once.
  • FIG. 1 is a diagram showing an example of the overall configuration of a system 1 according to this embodiment.
  • the system 1 includes multiple cameras 10, multiple processing devices 20, a user terminal 30, and a generating device 40. These are connected so as to be able to communicate with each other via a communication network 50.
  • Figure 2 shows an example configuration of a video analysis system.
  • a group of video data streams output from multiple cameras 10 are distributed to a user terminal 30 via one or more processing devices 20 in series and/or in parallel.
  • the processing device 20 comprises a NIC 21 that receives multiple data streams from multiple cameras 10, a memory 22 that stores the multiple data streams, and one or more processors 23 that process the multiple data streams.
  • the multiple processors 23 are connected in multiple stages. Video data is processed sequentially by a first processor 23a, a second processor 23b, and a third processor 23c.
  • the first processing device 20a is, for example, a video termination device.
  • the first processor 23a performs color correction and contour enhancement on frames of the data stream.
  • the second processor 23b changes the resolution of frames of the data stream to a resolution that can be processed by a video analysis device.
  • the second processing device 20b is, for example, a video analysis device, and analysis processing is performed by the third processor 23c.
  • the processing device 20 may be a processing device that executes any processing.
  • the processor 23 may also be a processor that executes any processing.
  • the number of processing devices 20 and the number of processors 23 are also arbitrary.
  • the processor may be, for example, a CPU, GPU, FPGA, etc.
  • the memory 22 may be a shared memory. A sensor may be used instead of the camera 10.
  • the video analysis system of this embodiment includes a generating device 40.
  • the generating device 40 includes a generating unit 41, a transmitting unit 42, and a storage unit 43.
  • the generation unit 41 has the function of allocating a memory area in advance to temporarily store each piece of data in the data stream group, generating a plan to write each piece of data into the allocated memory area when it arrives, and generating a plan to bulk out each piece of data from the memory area and read it all at once.
  • the generation unit 41 has the function of generating a data placement plan that places, based on the pre-determined arrival times (including data arrival time patterns) of data from a data stream group, data from multiple data streams related to the same or similar tasks, that is, data from multiple data streams with the same data period or similar data characteristics, in contiguous memory areas.
  • the generation unit 41 has the function of generating a data reading plan for reading the data of the multiple data streams from the continuous memory area all at once.
  • the generation unit 41 has the function of generating a data transfer plan in which, after a first-stage processor among the multi-stage first processor 23a to third processor 23c has processed all of the data from the multiple data streams, the data from the multiple data streams is transferred all at once to a subsequent-stage processor.
  • the generation unit 41 has the function of generating a software program for referencing the data placement plan, the data readout plan, and the data transfer plan.
  • the generation unit 41 can also generate the data placement plan, data readout plan, and data transfer plan as a single plan.
  • the transmission unit 42 has the function of transmitting the software program to one or more processing devices 20.
  • the memory unit 43 has the function of storing the above software programs.
  • the storage unit 43 has the function of storing the data necessary to generate the data placement plan, data readout plan, and data transfer plan.
  • the necessary data includes, for example, processor time slot design information (maximum processor execution time, maximum communication time between processors, etc.), and placement information (processing task content (data characteristics, etc.), input data volume, processor placement). This data can be obtained, for example, from actual machines in a test environment.
  • FIG. 3 is a diagram showing an image of generating a data allocation plan and a data readout plan, and an image of processing data based on these plans.
  • a data placement plan is generated in advance that bulks I/O processing of data streams with the same timing or similar characteristics and allocates them to contiguous memory areas, and a data reading plan is generated in advance that reads data from those contiguous memory areas all at once, thereby reducing the number of I/Os to memory and optimizing data processing wait times and processor idle time.
  • the generation unit 41 generates a data placement plan that places 30 fps frames A1, C1, D1, and E1 in consecutive memory areas R11 to R14, in that order, and 15 fps frames B1 and F1 in consecutive memory areas R21 to R22, in that order, based on the arrival times of the data in the data stream group that have been determined in advance.
  • the generation unit 41 For the subsequent 30 fps frames A2, C2, D2, and E2, the generation unit 41 generates a data placement plan for allocating them in consecutive memory areas in that order. Similarly, for the subsequent 15 fps frames B2 and F2, the generation unit 41 generates a data placement plan for allocating them in consecutive memory areas in that order.
  • the generation unit 41 generates a data reading plan that reads out 30 fps frames A1, C1, D1, and E1 arranged in consecutive memory areas R11 to R14 in that order, all at once, and reads out 15 fps frames B1 and F1 arranged in consecutive memory areas R21 to R22 in that order, all at once, and reads out 15 fps frames B1 and F1 arranged in consecutive memory areas R21 to R22 in that order, all at once.
  • the generation unit 41 For the subsequent 30 fps frames A2, C2, D2, and E2, the generation unit 41 generates a data readout plan to read them all at once from consecutive memory areas in that order. Similarly, for the subsequent 15 fps frames B2 and F2, the generation unit 41 generates a data readout plan to read them all at once from consecutive memory areas in that order.
  • the generation unit 41 generates a data placement plan that places frames A1, B1, and C1 input to the first data pipeline in consecutive memory areas in that order.
  • the generation unit 41 also generates a data readout plan that reads frames A1, B1, and C1 in that order all at once from consecutive memory areas.
  • Figure 5 shows a data placement plan and a data read plan corresponding to the configuration of the first data pipeline in Figure 4.
  • the first processor 23a obtains all of the data in a single read, since frames A1, B1, and C1 are arranged in a contiguous area.
  • the second processor 23b obtains the processing results of frames A1, B1, and C1 from the first processor 23a in a single read.
  • the third processor 23c writes the processing results of frames A1, B1, and C1 to contiguous shared memory in a single output.
  • the generation unit 41 generates a data placement plan and a data read plan as shown in Fig. 7. At time 0 and time 75, frames A1 to J1 are I/O processed in consecutive memory areas.
  • first processors 23a and third processors 23c are also possible to reduce the number of first processors 23a and third processors 23c to two each, divide 300 fps (equivalent to 10 data streams) into 150 fps (equivalent to 5 data streams), and allocate this to the two first processors 23a.
  • the generation unit 41 generates a data placement plan and a data readout plan as shown in Fig. 9. At time 0 and time 75, frames A1 to J1 are I/O processed in consecutive memory areas.
  • the memory 22 is a shared memory that can be commonly accessed by multiple processors 23, it is preferable to plan for multiple data write operations to be performed between data read operations by each processor 23. This can further reduce the time required to process data in the memory area.
  • [How to generate a data transfer plan] 10 is a diagram showing an example of how a data transfer plan is generated and how data is processed based on that plan.
  • the control unit 14 generates a data transfer plan for transferring, for example, four 30 fps frames A1, C1, D1, and E1 all at once to a downstream processor. Since multiple frames are transferred all at once, a delay occurs while the data is stored in a buffer, but the delay can be planned to be within a predetermined delay requirement.
  • the nth (n is a natural number) processor 23 receives four frames A1, C1, D1, and E1 all at once from the n-1th processor, according to the data transfer plan, processes them all, and then transfers the four frames A1, C1, D1, and E1 all at once to the n+1th processor.
  • the number of data input/output operations for the nth processor for the four frames A1, C1, D1, and E1 is a total of two.
  • the number of data input/output operations is a total of eight.
  • the number of data input/output operations between processors is reduced to one-fourth of the conventional number, enabling a reduction in the number of data input/output operations between processors.
  • the data placement plan, data reading plan, and data transfer plan are generated by the generation device 4.
  • the generation device 4 may generate each plan as is based on the plan input by the user.
  • the generation device 4 may also generate each plan autonomously using the data required to generate each plan.
  • the generation device 4 may also generate each plan collectively at once.
  • the generation device 4 may utilize machine learning, etc., when generating the task allocation plan.
  • FIG. 11 is a diagram showing a process flow for generating each plan.
  • Step S12 The generator 41 generates a data readout plan for reading the data of the plurality of data streams from the continuous memory area all at once.
  • Step S13 The generation unit 41 generates a data transfer plan in which, after a first-stage processor among multiple multi-stage processors has processed all of the data of the multiple data streams, the data of the multiple data streams is transferred all at once to a second-stage processor.
  • Step S14 The generating unit 41 generates software programs relating to the generated data placement plan, data read plan, and data transfer plan.
  • the transmitting unit 42 transmits the software programs to one or more processing devices 20.
  • FIG. 12 is a diagram showing a processing flow of a data stream.
  • Step S22 Each processor 23 of the processing device 20 executes the software program and, based on the data reading plan used by the execution, reads out each frame (each frame of multiple data streams with the same data period) from consecutive memory areas all at once.
  • Step S23 Each processor 23 of the processing device 20 executes the software program, processes all of the frames based on the data transfer plan used by the execution, and then transfers all of the frames together at once to the subsequent processor 23. Thereafter, the last processor 23 of the processing device 20 allocates the processed frames in a continuous memory area based on the data allocation plan.
  • Application example 1 For example, the present invention can be applied to assisting safe driving of a vehicle.
  • This use case prevents accidents by conducting a multi-dimensional assessment and prediction of the risk of collisions between vehicles and between vehicles and pedestrians at intersections through integrated analysis of multiple cameras, and providing real-time feedback to vehicles and pedestrians (via traffic lights, signs, speakers, etc.).
  • One use case is short-term power supply and demand adjustment.
  • Power consumption data for factories, data centers, homes, etc., as well as power supply data for energy conservation and automobile batteries, are collected and analyzed (sensing and risk assessment) with high frequency and low latency, and a stable power supply is achieved by adjusting demand and supply in response to adjustment requests from the grid, etc. based on the results of near-future power supply and demand forecasts.
  • the generation unit 41 of the generation device 40 generates a data placement plan for placing data from multiple data streams with the same data period or similar data characteristics within the arriving data stream group in consecutive memory areas based on the arrival times of the data from the data stream group that have been determined in advance, thereby reducing the number of times data is input into the memory 22 and the time required to process the data in the memory area.
  • the generation unit 41 of the generation device 40 generates a data reading plan that reads the data of the above multiple data streams from consecutive memory areas all at once, thereby reducing the number of times data is output from the memory 22 and further reducing the time required to process the data in the memory area.
  • the generation unit 41 of the generation device 40 generates a data transfer plan in which, after a first-stage processor among multiple multi-stage processors has processed all of the data in the multiple data streams, the data in the multiple data streams is transferred all at once to a second-stage processor. This reduces the number of data transfers and shortens the data transfer time between processors.
  • the generation device 40 of this embodiment described above can be realized, for example, as shown in FIG. 13, using a general-purpose computer system equipped with a CPU 901, memory 902, storage 903, communication device 904, input device 905, and output device 906.
  • the memory 902 and storage 903 are storage devices.
  • the CPU 901 executes a predetermined program loaded onto the memory 902, thereby realizing each function of the generation device 40.
  • the generating device 40 may be implemented as a single computer.
  • the generating device 40 may be implemented as multiple computers.
  • the generating device 40 may be a virtual machine implemented on a computer.
  • the program for the generation device 40 can be stored on a computer-readable recording medium such as a HDD, SSD, USB memory, CD, or DVD.
  • the computer-readable recording medium is, for example, a non-transitory recording medium.
  • the program for the generation device 40 can also be distributed via a communications network.

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Abstract

A generation device 40 comprises a generation unit 41 that uses the arrival time of data from a data stream group determined in advance as a basis to generate a data arrangement plan for arranging, in a continuous storage area, data from a plurality of data streams having the same data cycle or similar data characteristics among the data stream group.

Description

生成装置、生成方法、及び、生成プログラムGeneration device, generation method, and generation program

 本開示は、生成装置、生成方法、及び、生成プログラムに関する。 This disclosure relates to a generation device, a generation method, and a generation program.

 超低遅延や超多数接続を強みとする通信インフラにより、工場の遠隔制御や分散型エネルギーリソース制御等の産業のスマート化を促進できると期待されている。そのためには、コンピューティングインフラも、超低遅延で超多数接続に対応したデータ転送及びデータ処理を確定的な時間で実現する必要がある。 Communications infrastructure, with its strengths of ultra-low latency and massive connectivity, is expected to promote smart industrial processes such as remote factory control and distributed energy resource control. To achieve this, computing infrastructure must also be able to transfer and process data in deterministic time with ultra-low latency and support massive connectivity.

 例えば、実空間のデータ源からデータを収集してAI(Artificial Intelligence)分析等の処理を完了するまでの時間を、確定的に所定値以下に保てる必要がある。複数のデータ源から同時刻のデータを収集して多元分析を行う際にも、かかる時間を確定的に所定値以下に保てる必要がある。 For example, the time it takes to collect data from a real-world data source and complete processing such as AI (Artificial Intelligence) analysis must be kept deterministically below a specified value. Even when collecting data from multiple data sources at the same time and performing multi-dimensional analysis, the time it takes must be kept deterministically below a specified value.

 この点、パケットの送受信を効率化する技術として、カーネルやNIC(Network Interface Card)が受信した大きなデータを処理しやすいサイズに分割したり、処理後の小さなデータを通信しやすいサイズに統合したりする方法がある(非特許文献1)。 In this regard, one technique for improving the efficiency of packet sending and receiving is to divide large amounts of data received by the kernel or NIC (Network Interface Card) into smaller, more easily processed sizes, or to combine smaller pieces of processed data into smaller, more easily transmitted sizes (Non-Patent Document 1).

“Segmentation Offloads”、“Generic Segmentation Offload”、“Generic Receive Offload”、The Linux Kernel documentation、[online]、[令和5年12月12日検索]、<URL: https://docs.kernel.org/networking/segmentation-offloads.html>“Segmentation Offloads”, “Generic Segmentation Offload”, “Generic Receive Offload”, The Linux Kernel documentation, [online], [Retrieved December 12, 2020], <URL: https://docs.kernel.org/networking/segmentation-offloads.html>

 しかしながら、データ分割やデータ統合を状況に応じて動的に最適化できない。また、データ分割を行う場合、膨大な分割データをそれぞれ処理しなければならないため、データを一時的に記憶する記憶領域へのI/O回数が増加してしまう。 However, it is not possible to dynamically optimize data partitioning and data integration depending on the situation. Furthermore, when partitioning data, huge amounts of data must be processed separately, which increases the number of I/O operations to the storage area where the data is temporarily stored.

 本開示は、上記事情に鑑みてなされたものであり、本開示の目的は、データの記憶領域への処理に要する時間を改善可能な技術を提供することである。 This disclosure has been made in light of the above circumstances, and its purpose is to provide technology that can improve the time required to process data in a storage area.

 本開示の一態様の生成装置は、事前に確定しているデータストリーム群のデータの到着時刻に基づき、前記データストリーム群内でデータ周期が同一又はデータ特性が類似する複数のデータストリームのデータを、連続する記憶領域に配置するデータ配置計画を生成する生成部、を備える。 A generation device according to one aspect of the present disclosure includes a generation unit that generates a data placement plan for placing data from multiple data streams with the same data period or similar data characteristics within a data stream group in contiguous storage areas, based on the arrival times of data from the data stream group that have been determined in advance.

 本開示の一態様の生成方法は、生成装置で行う生成方法において、事前に確定しているデータストリーム群のデータの到着時刻に基づき、前記データストリーム群内でデータ周期が同一又はデータ特性が類似する複数のデータストリームのデータを、連続する記憶領域に配置するデータ配置計画を生成する。 In one aspect of the generation method disclosed herein, a generation device generates a data placement plan that places data from multiple data streams with the same data period or similar data characteristics within a data stream group in contiguous storage areas based on the arrival times of data from the data stream group that have been determined in advance.

 本開示の一態様の生成プログラムは、上記生成装置としてコンピュータを機能させる。 A generation program according to one aspect of the present disclosure causes a computer to function as the generation device.

 本開示によれば、データの記憶領域への処理に要する時間を低減可能な技術を提供できる。 This disclosure provides technology that can reduce the time required to process data in a storage area.

図1は、本実施形態に係るシステムの全体構成例を示す図である。FIG. 1 is a diagram showing an example of the overall configuration of a system according to this embodiment. 図2は、映像解析システムの構成例を示す図である。FIG. 2 is a diagram illustrating an example of the configuration of a video analysis system. 図3は、データ配置計画及びデータ読出計画の生成方法の例を示す図である。FIG. 3 is a diagram illustrating an example of a method for generating a data allocation plan and a data readout plan. 図4は、プロセッサの配置例(第1の例)を示す図である。FIG. 4 is a diagram showing an example (first example) of processor arrangement. 図5は、データ配置計画及びデータ読出計画の例(第1の例)を示す図である。FIG. 5 is a diagram showing an example (first example) of a data allocation plan and a data read plan. 図6は、プロセッサの配置例(第2の例)を示す図である。FIG. 6 is a diagram showing an example (second example) of processor arrangement. 図7は、データ配置計画及びデータ読出計画の例(第2の例)を示す図である。FIG. 7 is a diagram showing an example (second example) of a data allocation plan and a data read plan. 図8は、プロセッサの配置例(第3の例)を示す図である。FIG. 8 is a diagram illustrating an example (third example) of processor arrangement. 図9は、データ配置計画及びデータ読出計画の例(第3の例)を示す図である。FIG. 9 is a diagram showing an example (third example) of a data allocation plan and a data read plan. 図10は、データ転送計画の生成方法の例を示す図である。FIG. 10 is a diagram illustrating an example of a method for generating a data transfer plan. 図11は、各計画の生成処理フローを示す図である。FIG. 11 is a diagram showing a process flow for generating each plan. 図12は、データストリームの処理フローを示す図である。FIG. 12 is a diagram showing a processing flow of a data stream. 図13は、生成装置のハードウェア構成を示す図である。FIG. 13 is a diagram illustrating a hardware configuration of the generation device.

 以下、図面を参照して、本開示の実施形態を説明する。図面の記載において同一部分には同一符号を付し説明を省略する。 Embodiments of the present disclosure will be described below with reference to the drawings. In the drawings, identical parts will be designated by the same reference numerals and their description will be omitted.

 [本開示の概要]
 クラウド等で現在多く使用されている汎用OSの場合、タスク間のプロセッサ利用時間の公平性を重視したスケジューリングが行われるため、タスクにプロセッサが割り当てられるまでの待ち時間は常に変動する。また、割り込み処理はタスクの優先度とは無関係に最優先で行われるため、処理時間も常に変動する。
[Summary of the Disclosure]
In the case of general-purpose operating systems (OS) currently widely used in cloud computing, scheduling is performed with an emphasis on fairness in processor usage time among tasks, so the wait time until a processor is assigned to a task is constantly fluctuating. In addition, interrupt processing is given top priority regardless of the task priority, so processing time is also constantly fluctuating.

 そこで、本開示は、待ち時間の揺らぎや処理時間の揺らぎがないこと保証するリアルタイムシステムの構築を試みる。特に、記憶領域へのI/O処理負荷を考慮して、処理待ち時間やプロセッサの空き時間を削減するように最適化を行う。但し、データの到着時刻(データの到着時刻パタンを含む)は事前に判明していることを前提とする。データの到着時刻が事前に判明している通信ネットワーク(データの到着に関して確定性を持った通信手段)は、既存技術である。 This disclosure therefore attempts to build a real-time system that guarantees no fluctuations in waiting time or processing time. In particular, optimization is performed to reduce processing waiting time and processor idle time, taking into account the I/O processing load on the storage area. However, this is premised on the assumption that the data arrival time (including the data arrival time pattern) is known in advance. Communication networks in which the data arrival time is known in advance (communication means with determinism regarding data arrival) are existing technology.

 具体的には、その前提において、データ周期が同一又はデータ特性が類似する複数のデータストリーム(時系列に沿って断続的に流れるデータ群)のデータを連続する記憶領域に配置するデータ配置計画を生成し、その連続する記憶領域から当該複数のデータストリームのデータをバルク化して一度に読み出すデータ読出計画を事前に生成する。 Specifically, based on this premise, a data placement plan is generated that places data from multiple data streams (groups of data that flow intermittently over time) with the same data cycle or similar data characteristics in a contiguous storage area, and a data reading plan is generated in advance that bulks the data from the multiple data streams from that contiguous storage area and reads it all at once.

 これにより、記憶領域へのI/O回数が少なくなるので、データの記憶領域への処理に要する時間を低減できる。 This reduces the number of I/O operations to the storage area, thereby reducing the time required to process data in the storage area.

 [システムの構成例]
 本実施形態では、複数のカメラ映像を集約して映像解析を行う例を説明する。
[System configuration example]
In this embodiment, an example will be described in which video analysis is performed by aggregating video from a plurality of cameras.

 図1は、本実施形態に係るシステム1の全体構成例を示す図である。システム1は、複数のカメラ10と、複数の処理装置20と、ユーザ端末30と、生成装置40と、を備える。それらは、通信ネットワーク50を介して通信可能に接続されている。 FIG. 1 is a diagram showing an example of the overall configuration of a system 1 according to this embodiment. The system 1 includes multiple cameras 10, multiple processing devices 20, a user terminal 30, and a generating device 40. These are connected so as to be able to communicate with each other via a communication network 50.

 図2は、映像解析システムの構成例を示す図である。複数のカメラ10から出力される映像のデータストリーム群は、1つ又は複数の処理装置20を直列及び/又は並列に介してユーザ端末30へ配信される。 Figure 2 shows an example configuration of a video analysis system. A group of video data streams output from multiple cameras 10 are distributed to a user terminal 30 via one or more processing devices 20 in series and/or in parallel.

 処理装置20は、複数のカメラ10からの複数のデータストリームを受信するNIC21と、複数のデータストリームを記憶するメモリ22と、複数のデータストリームを処理する1つ又は複数のプロセッサ23と、を備える。複数のプロセッサ23は、多段に接続された構成となる。映像データは、第1のプロセッサ23aと、第2のプロセッサ23bと、第3のプロセッサ23cと、により、順次処理される。 The processing device 20 comprises a NIC 21 that receives multiple data streams from multiple cameras 10, a memory 22 that stores the multiple data streams, and one or more processors 23 that process the multiple data streams. The multiple processors 23 are connected in multiple stages. Video data is processed sequentially by a first processor 23a, a second processor 23b, and a third processor 23c.

 図2(b)の場合、第1の処理装置20aは、例えば、映像終端装置である。第1のプロセッサ23aは、データストリームのフレームの色調補正や輪郭強調を行う。第2のプロセッサ23bは、映像解析装置が処理可能な解像度へデータストリームのフレームの解像度を変更する。第2の処理装置20bは、例えば、映像解析装置であり、第3のプロセッサ23cにより解析処理が行われる。 In the case of Figure 2(b), the first processing device 20a is, for example, a video termination device. The first processor 23a performs color correction and contour enhancement on frames of the data stream. The second processor 23b changes the resolution of frames of the data stream to a resolution that can be processed by a video analysis device. The second processing device 20b is, for example, a video analysis device, and analysis processing is performed by the third processor 23c.

 但し、処理装置20は、任意の処理を実行する処理装置でよい。プロセッサ23も任意の処理を実行するプロセッサでよい。処理装置20の数及びプロセッサ23の数も任意である。プロセッサは、例えば、CPU、GPU、FPGA等である。メモリ22は、共有メモリでもよい。カメラ10に代えて、センサでもよい。 However, the processing device 20 may be a processing device that executes any processing. The processor 23 may also be a processor that executes any processing. The number of processing devices 20 and the number of processors 23 are also arbitrary. The processor may be, for example, a CPU, GPU, FPGA, etc. The memory 22 may be a shared memory. A sensor may be used instead of the camera 10.

 [生成装置の構成]
 上記映像解析システムに対し、本実施形態は、図1に示したように、生成装置40を備える。生成装置40は、生成部41と、送信部42と、記憶部43と、を備える。
[Configuration of the generation device]
1, the video analysis system of this embodiment includes a generating device 40. The generating device 40 includes a generating unit 41, a transmitting unit 42, and a storage unit 43.

 生成部41は、データストリーム群の各データに対して一時的に留置するメモリ領域を事前に割り当てておき、各データが到着したタイミングで割り当て済みのメモリ領域に各データを書き込む計画を生成し、各データをメモリ領域からバルク化して一度に読み出す計画を生成する機能を備える。 The generation unit 41 has the function of allocating a memory area in advance to temporarily store each piece of data in the data stream group, generating a plan to write each piece of data into the allocated memory area when it arrives, and generating a plan to bulk out each piece of data from the memory area and read it all at once.

 具体的には、生成部41は、事前に確定しているデータストリーム群のデータの到着時刻(データの到着時刻パタンを含む)に基づき、到着したデータストリーム群のデータのうち、同一又は類似のタスクに係る複数のデータストリームのデータ、つまり、データ周期が同一又はデータ特性が類似する複数のデータストリームのデータを、連続するメモリ領域に配置するデータ配置計画を生成する機能を備える。 Specifically, the generation unit 41 has the function of generating a data placement plan that places, based on the pre-determined arrival times (including data arrival time patterns) of data from a data stream group, data from multiple data streams related to the same or similar tasks, that is, data from multiple data streams with the same data period or similar data characteristics, in contiguous memory areas.

 生成部41は、上記連続するメモリ領域から上記複数のデータストリームのデータをまとめて一度に読み出すデータ読出計画を生成する機能を備える。 The generation unit 41 has the function of generating a data reading plan for reading the data of the multiple data streams from the continuous memory area all at once.

 生成部41は、多段な第1のプロセッサ23a~第3のプロセッサ23cのうち前段のプロセッサが上記複数のデータストリームのデータを全て処理した後に、当該複数のデータストリームのデータをまとめて一度に後段のプロセッサへ転送するデータ転送計画を生成する機能を備える。 The generation unit 41 has the function of generating a data transfer plan in which, after a first-stage processor among the multi-stage first processor 23a to third processor 23c has processed all of the data from the multiple data streams, the data from the multiple data streams is transferred all at once to a subsequent-stage processor.

 生成部41は、上記データ配置計画、上記データ読出計画、上記データ転送計画を参照させるためのソフトウェアプログラムを生成する機能を備える。 The generation unit 41 has the function of generating a software program for referencing the data placement plan, the data readout plan, and the data transfer plan.

 なお、生成部41は、上記データ配置計画、上記データ読出計画、上記データ転送計画を1つの計画として生成することも可能である。 The generation unit 41 can also generate the data placement plan, data readout plan, and data transfer plan as a single plan.

 送信部42は、上記ソフトウェアプログラムを1つ以上の処理装置20へ送信する機能を備える。 The transmission unit 42 has the function of transmitting the software program to one or more processing devices 20.

 記憶部43は、上記ソフトウェアプログラムを記憶する機能を備える。 The memory unit 43 has the function of storing the above software programs.

 記憶部43は、上記データ配置計画、上記データ読出計画、上記データ転送計画を生成するために必要なデータを記憶する機能を備える。必要なデータとは、例えば、プロセッサのタイムスロット設計情報(プロセッサの最大実行時間、プロセッサ間の通信最大時間、等)、配置情報(処理タスクの内容(データ特性、等)、入力データ量、プロセッサの配置)である。これらのデータは、例えば、試験環境の実機から取得可能である。 The storage unit 43 has the function of storing the data necessary to generate the data placement plan, data readout plan, and data transfer plan. The necessary data includes, for example, processor time slot design information (maximum processor execution time, maximum communication time between processors, etc.), and placement information (processing task content (data characteristics, etc.), input data volume, processor placement). This data can be obtained, for example, from actual machines in a test environment.

 [データ配置計画及びデータ読出計画の生成方法]
 図3は、データ配置計画及びデータ読出計画の生成イメージ及びそれらの計画に基づくデータの処理イメージを示す図である。
[Method for generating data placement plan and data readout plan]
FIG. 3 is a diagram showing an image of generating a data allocation plan and a data readout plan, and an image of processing data based on these plans.

 互いに異なる複数のカメラ10が同時刻に生成した複数のフレームであっても、カメラ10内での処理の揺らぎや第1の処理装置20aまでの線路長がカメラ10毎に異なるため、位相のずれが生じ、必ずしも同時に到着するとは限らない。 Even if multiple frames are generated at the same time by multiple different cameras 10, there will be a phase shift due to fluctuations in processing within the cameras 10 and differences in the line length to the first processing device 20a for each camera 10, and the frames will not necessarily arrive at the same time.

 そこで、データの到着時刻が事前に判明していることを前提に、同じタイミングや似た特性のデータストリームのデータのI/O処理をバルク化して連続するメモリ領域へ割り当てるデータ配置計画を事前に生成し、その連続するメモリ領域からデータをまとめて一度に読み出すデータ読出計画を事前に生成しておくことにおり、メモリへのI/O回数を削減し、データの処理待ち時間やプロセッサの空き時間を削減する最適化を行う。 Assuming that the data arrival time is known in advance, a data placement plan is generated in advance that bulks I/O processing of data streams with the same timing or similar characteristics and allocates them to contiguous memory areas, and a data reading plan is generated in advance that reads data from those contiguous memory areas all at once, thereby reducing the number of I/Os to memory and optimizing data processing wait times and processor idle time.

 (データ配置計画の生成方法)
 図3に示すように、データストリームA、C、D、Eは30fpsであり、データストリームB、Fは15fpsであることは、事前に判明している。また、所定時刻において、データストリームA→C→D→B→E→Fの順に、それらの各フレームが到着することも事前に判明している。
(Method for generating a data placement plan)
3, it is known in advance that data streams A, C, D, and E are 30 fps, and data streams B and F are 15 fps. It is also known in advance that the frames of the data streams will arrive in the following order at a given time: A → C → D → B → E → F.

 この場合、生成部41は、事前に確定しているデータストリーム群のデータの到着時刻に基づき、30fpsのフレームA1、C1、D1、E1を、その順に、連続するメモリ領域R11~R14に配置し、15fpsのフレームB1、F1を、その順に、連続するメモリ領域R21~R22に配置するデータ配置計画を生成する。 In this case, the generation unit 41 generates a data placement plan that places 30 fps frames A1, C1, D1, and E1 in consecutive memory areas R11 to R14, in that order, and 15 fps frames B1 and F1 in consecutive memory areas R21 to R22, in that order, based on the arrival times of the data in the data stream group that have been determined in advance.

 後続する30fpsのフレームA2、C2、D2、E2についても同様に、生成部41は、その順に、連続するメモリ領域に配置するデータ配置計画を生成する。後続する15fpsのフレームB2、F2についても同様に、生成部41は、その順に、連続するメモリ領域に配置するデータ配置計画を生成する。 Similarly, for the subsequent 30 fps frames A2, C2, D2, and E2, the generation unit 41 generates a data placement plan for allocating them in consecutive memory areas in that order.Similarly, for the subsequent 15 fps frames B2 and F2, the generation unit 41 generates a data placement plan for allocating them in consecutive memory areas in that order.

 (データ読出計画の生成方法)
 生成部41は、上記例の場合、連続するメモリ領域R11~R14に配置されている30fpsのフレームA1、C1、D1、E1を、その順に、連続してまとめて一度に読み出し、連続するメモリ領域R21~R22に配置されている15fpsのフレームB1、F1を、その順に、連続してまとめて一度に読み出すデータ読出計画を生成する。
(How to generate a data readout plan)
In the above example, the generation unit 41 generates a data reading plan that reads out 30 fps frames A1, C1, D1, and E1 arranged in consecutive memory areas R11 to R14 in that order, all at once, and reads out 15 fps frames B1 and F1 arranged in consecutive memory areas R21 to R22 in that order, all at once, and reads out 15 fps frames B1 and F1 arranged in consecutive memory areas R21 to R22 in that order, all at once.

 後続する30fpsのフレームA2、C2、D2、E2についても同様に、生成部41は、その順に、連続するメモリ領域からまとめて一度に読み出すデータ読出計画を生成する。後続する15fpsのフレームB2、F2についても同様に、生成部41は、その順に、連続するメモリ領域からまとめて一度に読み出すデータ読出計画を生成する。 Similarly, for the subsequent 30 fps frames A2, C2, D2, and E2, the generation unit 41 generates a data readout plan to read them all at once from consecutive memory areas in that order. Similarly, for the subsequent 15 fps frames B2 and F2, the generation unit 41 generates a data readout plan to read them all at once from consecutive memory areas in that order.

 (データ配置計画及びデータ読出計画の具体例)
 (第1の例)
 図4に示すように、複数のプロセッサが多段(紙面の横方向)かつ並列(紙面の縦方向)に配置され、3本の30fpsのデータストリームの各処理を1本のデータパイプラインに集約する場合を考える。
(Specific examples of data placement plans and data reading plans)
(First example)
As shown in FIG. 4, consider a case where multiple processors are arranged in multiple stages (horizontally on the page) and in parallel (vertically on the page), and the processing of three 30 fps data streams is consolidated into one data pipeline.

 この場合、生成部41は、第1のデータパイプラインに入力されるフレームA1、B1、C1を、その順に、連続するメモリ領域に配置するデータ配置計画を生成する。また、生成部41は、フレームA1、B1、C1を、その順に、連続するメモリ領域からまとめて一度に読み出すデータ読出計画を生成する。 In this case, the generation unit 41 generates a data placement plan that places frames A1, B1, and C1 input to the first data pipeline in consecutive memory areas in that order. The generation unit 41 also generates a data readout plan that reads frames A1, B1, and C1 in that order all at once from consecutive memory areas.

 図5は、図4の第1のデータパイプラインの構成に対応するデータ配置計画及びデータ読出計画を示す図である。時刻0において、第1のプロセッサ23aは、フレームA1、B1、C1が連続した領域に配置されているので、1回の読み出しでそれら全てのデータを取得する。次に、時刻20において、第2のプロセッサ23bは、第1のプロセッサ23aのフレームA1、B1、C1に対する処理結果を、1回の読み込みで取得する。第3のプロセッサ23cのデータ取得について同様である。最後に、時刻65において、第3のプロセッサ23cは、フレームA1、B1、C1の処理結果を1回の出力によって連続する共有メモリへ書き出す。 Figure 5 shows a data placement plan and a data read plan corresponding to the configuration of the first data pipeline in Figure 4. At time 0, the first processor 23a obtains all of the data in a single read, since frames A1, B1, and C1 are arranged in a contiguous area. Next, at time 20, the second processor 23b obtains the processing results of frames A1, B1, and C1 from the first processor 23a in a single read. The same is true for data acquisition by the third processor 23c. Finally, at time 65, the third processor 23c writes the processing results of frames A1, B1, and C1 to contiguous shared memory in a single output.

 なお、図面内の「●」は、プロセッサの空き状態を示している。 Note that the "●" in the diagram indicates the processor's available status.

 (第2の例)
 図6に示すように、データストリームのデータの処理を処理単位の小さいフレーム単位で振り分ける場合も考えらえる。この場合、生成部41は、図7に示すようなデータ配置計画及びデータ読出計画を生成する。時刻0と時刻75でフレームA1~J1を連続するメモリ領域にI/O処理する。
(Second Example)
As shown in Fig. 6, it is also possible to allocate the processing of data in a data stream in units of frames, which are smaller processing units. In this case, the generation unit 41 generates a data placement plan and a data read plan as shown in Fig. 7. At time 0 and time 75, frames A1 to J1 are I/O processed in consecutive memory areas.

 (第3の例)
 図8に示すように、第1のプロセッサ23aと第3のプロセッサ23cの各数をそれぞれ2つに減らし、300fps(=10本のデータストリームに相当する量)を150fps(=5本のデータストリームに相当する量)に分けて、2つの第1のプロセッサ23aに振り分ける場合も考えられる。この場合、生成部41は、図9に示すようなデータ配置計画及びデータ読出計画を生成する。時刻0と時刻75でフレームA1~J1を連続するメモリ領域にI/O処理する。
(Third Example)
As shown in Fig. 8, it is also possible to reduce the number of first processors 23a and third processors 23c to two each, divide 300 fps (equivalent to 10 data streams) into 150 fps (equivalent to 5 data streams), and allocate this to the two first processors 23a. In this case, the generation unit 41 generates a data placement plan and a data readout plan as shown in Fig. 9. At time 0 and time 75, frames A1 to J1 are I/O processed in consecutive memory areas.

 (補足)
 メモリ22が、複数のプロセッサ23から共通にアクセスできる共有メモリの場合、各プロセッサ23によるデータの読み取り処理の合間に、複数回のデータの書き込み処理を実行させるように計画することが好ましい。これにより、データのメモリ領域への処理に要する時間を更に低減できる。
(supplement)
If the memory 22 is a shared memory that can be commonly accessed by multiple processors 23, it is preferable to plan for multiple data write operations to be performed between data read operations by each processor 23. This can further reduce the time required to process data in the memory area.

 [データ転送計画の生成方法]
 図10は、データ転送計画の生成イメージ及びその計画に基づくデータの処理イメージを示す図である。制御部14は、例えば、30fpsの4つのフレームA1、C1、D1、E1をまとめて一度に後段のプロセッサへ転送するデータ転送計画を生成する。なお、複数のフレームをまとめて一度に転送するので、データをバッファに留置する遅延が生じるが、所定の遅延要件の範囲内に収まるように計画すればよい。
[How to generate a data transfer plan]
10 is a diagram showing an example of how a data transfer plan is generated and how data is processed based on that plan. The control unit 14 generates a data transfer plan for transferring, for example, four 30 fps frames A1, C1, D1, and E1 all at once to a downstream processor. Since multiple frames are transferred all at once, a delay occurs while the data is stored in a buffer, but the delay can be planned to be within a predetermined delay requirement.

 第n(nは自然数)のプロセッサ23は、上記データ転送計画に基づき、当該データ転送計画の通りに、第n-1のプロセッサから4つのフレームA1、C1、D1、E1をまとめて一度に受け取り、それらを全て処理した後、その4つのA1、C1、D1、E1をまとめて一度に第n+1のプロセッサへ転送する。 The nth (n is a natural number) processor 23 receives four frames A1, C1, D1, and E1 all at once from the n-1th processor, according to the data transfer plan, processes them all, and then transfers the four frames A1, C1, D1, and E1 all at once to the n+1th processor.

 その結果、図10(a)に示すように、4つのフレームA1、C1、D1、E1について、第nのプロセッサでのデータ入出力回数は、合計2回で済む。一方、従来の場合、図10(b)に示すように、そのデータ入出力回数は、合計8回となる。プロセッサ間のデータ入出力回数は従来の1/4となり、プロセッサ間のデータ入出力回数を削減できる。 As a result, as shown in Figure 10(a), the number of data input/output operations for the nth processor for the four frames A1, C1, D1, and E1 is a total of two. In contrast, in the conventional case, as shown in Figure 10(b), the number of data input/output operations is a total of eight. The number of data input/output operations between processors is reduced to one-fourth of the conventional number, enabling a reduction in the number of data input/output operations between processors.

 上記データ配置計画、上記データ読出計画、上記データ転送計画は、生成装置4により生成される。生成装置4は、ユーザが入力した各計画をそのまま各計画として生成してもよい。生成装置4は、各計画を生成するために必要なデータを用いて、各計画を自律的に生成してもよい。生成装置4は、各計画をまとめて一度に生成してもよい。生成装置4は、タスク割当計画を生成する際、機械学習等を活用してもよい。 The data placement plan, data reading plan, and data transfer plan are generated by the generation device 4. The generation device 4 may generate each plan as is based on the plan input by the user. The generation device 4 may also generate each plan autonomously using the data required to generate each plan. The generation device 4 may also generate each plan collectively at once. The generation device 4 may utilize machine learning, etc., when generating the task allocation plan.

 [各計画の生成動作]
 図11は、各計画の生成処理フローを示す図である。
[Plan generation operation]
FIG. 11 is a diagram showing a process flow for generating each plan.

 ステップS11;
 生成部41は、事前に確定しているデータストリーム群のデータの到着時刻に基づき、データ周期が同一の複数のデータストリームのデータを、連続するメモリ領域に配置するデータ配置計画を生成する。
Step S11:
The generator 41 generates a data allocation plan for allocating data of a plurality of data streams having the same data period in consecutive memory areas based on the arrival times of data of the data stream group that have been determined in advance.

 ステップS12;
 生成部41は、上記連続するメモリ領域から上記複数のデータストリームのデータをまとめて一度に読み出すデータ読出計画を生成する。
Step S12:
The generator 41 generates a data readout plan for reading the data of the plurality of data streams from the continuous memory area all at once.

 ステップS13;
 生成部41は、多段な複数のプロセッサのうち前段のプロセッサが上記複数のデータストリームのデータを全て処理した後に、当該複数のデータストリームのデータをまとめて一度に後段のプロセッサへ転送するデータ転送計画を生成する。
Step S13:
The generation unit 41 generates a data transfer plan in which, after a first-stage processor among multiple multi-stage processors has processed all of the data of the multiple data streams, the data of the multiple data streams is transferred all at once to a second-stage processor.

 ステップS14;
 生成部41は、生成したデータ配置計画、データ読出計画、データ転送計画に係るソフトウェアプログラムを生成する。送信部42は、そのソフトウェアプログラムを1つ以上の処理装置20へ送信する。
Step S14:
The generating unit 41 generates software programs relating to the generated data placement plan, data read plan, and data transfer plan. The transmitting unit 42 transmits the software programs to one or more processing devices 20.

 [データストリームの処理動作]
 図12は、データストリームの処理フローを示す図である。
[Data Stream Processing Operation]
FIG. 12 is a diagram showing a processing flow of a data stream.

 ステップS21;
 処理装置20のNIC21は、上記ソフトウェアプログラムを実行し、データストリーム群のデータが到着すると、その実行により使用されるデータ配置計画を基に、データ周期が同一の複数のデータストリームの各フレームを連続するメモリ領域に配置する。
Step S21:
The NIC 21 of the processing device 20 executes the above software program, and when data from the data stream group arrives, it places each frame of multiple data streams with the same data period in a consecutive memory area based on the data placement plan used by the execution.

 ステップS22;
 処理装置20の各プロセッサ23は、上記ソフトウェアプログラムを実行し、その実行により使用されるデータ読出計画を基に、連続するメモリ領域から各フレーム(データ周期が同一の複数のデータストリームの各フレーム)をまとめて一度に読み出す。
Step S22:
Each processor 23 of the processing device 20 executes the software program and, based on the data reading plan used by the execution, reads out each frame (each frame of multiple data streams with the same data period) from consecutive memory areas all at once.

 ステップS23;
 処理装置20の各プロセッサ23は、上記ソフトウェアプログラムを実行し、その実行により使用されるデータ転送計画を基に、上記各フレームを全て処理した後、その各フレームを全てまとめて一度に後段のプロセッサ23へ転送する。その後、処理装置20の最後のプロセッサ23は、データ配置計画を基に、処理後の上記各フレームを連続するメモリ領域に配置する。
Step S23:
Each processor 23 of the processing device 20 executes the software program, processes all of the frames based on the data transfer plan used by the execution, and then transfers all of the frames together at once to the subsequent processor 23. Thereafter, the last processor 23 of the processing device 20 allocates the processed frames in a continuous memory area based on the data allocation plan.

 [適用例]
 (適用例1)
 例えば、車両の安全運転を支援する場合に適用できる。
[Application example]
(Application example 1)
For example, the present invention can be applied to assisting safe driving of a vehicle.

 交差点における車両同士の接触事故、車両と歩行者の接触事故の発生リスクを、複数カメラを統合分析することにより多元的に評価・予測し、車両・歩行者にリアルタイムにフィードバック(信号機、標識、スピーカー等)することで、事故を未然に防ぐユースケースである。 This use case prevents accidents by conducting a multi-dimensional assessment and prediction of the risk of collisions between vehicles and between vehicles and pedestrians at intersections through integrated analysis of multiple cameras, and providing real-time feedback to vehicles and pedestrians (via traffic lights, signs, speakers, etc.).

 このようなユースケースを実現するためには、カメラ映像の収集から事故発生リスクの評価・予測処理、運転者や歩行者に対する警報までを低遅延かつ確定的な遅延時間で処理する必要がある。 To realize such use cases, it is necessary to process everything from collecting camera footage to assessing and predicting the risk of accidents and issuing warnings to drivers and pedestrians with low and deterministic latency.

 そこで、本実施形態を適用することにより、交差点事故で多発している右折衝突防止や出会い頭衝突等の事故を防止可能となる。具体的には、右折時の運転者の見込み違いや見通し不良、信号無視が原因で生じる対向直進車との衝突事故を低減できる。信号機のない一時停止交差点で、運転者の不注意や見通し不良が原因で生じる事故を低減できる。 By applying this embodiment, it is possible to prevent accidents such as right-turn collisions and head-on collisions, which occur frequently at intersections. Specifically, it is possible to reduce collisions with oncoming vehicles caused by drivers misjudging the road or poor visibility when turning right, or ignoring traffic lights. It is also possible to reduce accidents caused by driver inattention or poor visibility at intersections with no traffic lights and stop signs.

 (適用例2)
 本実施形態の技術は、高速かつ低遅延で処理を行う事例において大きな効果を発揮する。適用事例としては、以下のようなユースケースが考えられる。
(Application example 2)
The technology of this embodiment is highly effective in cases where high-speed, low-latency processing is required. The following use cases are possible examples of application.

 短時間電力需給調整を行うユースケースがある。工場、データセンタ、住宅、等の電力消費量や省エネ、自動車バッテリーなどの電力供給量を高頻度かつ低遅延で収集・解析(センシングとリスク評価)し、近未来の電力需給予測した結果に基づきグリッド等からの調整要望に対して需要や供給量を調整することで安定的な電力供給を実現する。 One use case is short-term power supply and demand adjustment. Power consumption data for factories, data centers, homes, etc., as well as power supply data for energy conservation and automobile batteries, are collected and analyzed (sensing and risk assessment) with high frequency and low latency, and a stable power supply is achieved by adjusting demand and supply in response to adjustment requests from the grid, etc. based on the results of near-future power supply and demand forecasts.

 低遅延トレーディングを行うユースケースがある。金融市場における自動取引システム(市場からデータを受信し、受信データを分析して売買注文を自動生成して、生成した注文を取引所のシステムに送信する市場参加者のシステム)において、運用成績を高めるために、時々刻々と変化する様々な市況データを用いたリアルタイム分析を実現する。 One use case is low-latency trading. In automated trading systems in financial markets (systems used by market participants that receive data from the market, analyze the received data, automatically generate buy and sell orders, and send the generated orders to the exchange's system), real-time analysis is achieved using a variety of constantly changing market data in order to improve operational performance.

 [効果]
 本実施形態によれば、生成装置40の生成部41が、事前に確定しているデータストリーム群のデータの到着時刻に基づき、到着したデータストリーム群内でデータ周期が同一又はデータ特性が類似する複数のデータストリームのデータを、連続するメモリ領域に配置するデータ配置計画を生成するので、メモリ22へのデータのインプット回数が削減し、データのメモリ領域への処理に要する時間を低減できる。
[effect]
According to this embodiment, the generation unit 41 of the generation device 40 generates a data placement plan for placing data from multiple data streams with the same data period or similar data characteristics within the arriving data stream group in consecutive memory areas based on the arrival times of the data from the data stream group that have been determined in advance, thereby reducing the number of times data is input into the memory 22 and the time required to process the data in the memory area.

 また、本実施形態によれば、生成装置40の生成部41が、連続するメモリ領域から上記複数のデータストリームのデータをまとめて一度に読み出すデータ読出計画を生成するので、メモリ22からのデータのアウトプット回数が削減し、データのメモリ領域への処理に要する時間を更に低減できる。 Furthermore, according to this embodiment, the generation unit 41 of the generation device 40 generates a data reading plan that reads the data of the above multiple data streams from consecutive memory areas all at once, thereby reducing the number of times data is output from the memory 22 and further reducing the time required to process the data in the memory area.

 また、本実施形態によれば、生成装置40の生成部41が、多段な複数のプロセッサのうち前段のプロセッサが上記複数のデータストリームのデータを全て処理した後に、当該複数のデータストリームのデータをまとめて一度に後段のプロセッサへ転送するデータ転送計画を生成するので、データの転送回数が削減し、プロセッサ間のデータ転送時間を低減できる。 Furthermore, according to this embodiment, the generation unit 41 of the generation device 40 generates a data transfer plan in which, after a first-stage processor among multiple multi-stage processors has processed all of the data in the multiple data streams, the data in the multiple data streams is transferred all at once to a second-stage processor. This reduces the number of data transfers and shortens the data transfer time between processors.

 [その他]
 本開示は、上記実施形態に限定されない。本開示は、本開示の要旨の範囲内で数々の変形が可能である。
[others]
The present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope of the present disclosure.

 上記説明した本実施形態の生成装置40は、例えば、図13に示すように、CPU901と、メモリ902と、ストレージ903と、通信装置904と、入力装置905と、出力装置906と、を備えた汎用的なコンピュータシステムを用いて実現できる。メモリ902及びストレージ903は、記憶装置である。当該コンピュータシステムにおいて、CPU901がメモリ902上にロードされた所定のプログラムを実行することにより、生成装置40の各機能が実現される。 The generation device 40 of this embodiment described above can be realized, for example, as shown in FIG. 13, using a general-purpose computer system equipped with a CPU 901, memory 902, storage 903, communication device 904, input device 905, and output device 906. The memory 902 and storage 903 are storage devices. In this computer system, the CPU 901 executes a predetermined program loaded onto the memory 902, thereby realizing each function of the generation device 40.

 生成装置40は、1つのコンピュータで実装されてもよい。生成装置40は、複数のコンピュータで実装されてもよい。生成装置40は、コンピュータに実装される仮想マシンであってもよい。 The generating device 40 may be implemented as a single computer. The generating device 40 may be implemented as multiple computers. The generating device 40 may be a virtual machine implemented on a computer.

 生成装置40用のプログラムは、HDD、SSD、USBメモリ、CD、DVD等のコンピュータ読取り可能な記録媒体に記憶できる。コンピュータ読取り可能な記録媒体は、例えば、非一時的な(non-transitory)記録媒体である。生成装置40用のプログラムは、通信ネットワークを介して配信することもできる。 The program for the generation device 40 can be stored on a computer-readable recording medium such as a HDD, SSD, USB memory, CD, or DVD. The computer-readable recording medium is, for example, a non-transitory recording medium. The program for the generation device 40 can also be distributed via a communications network.

 1 システム
 10 カメラ
 20 処理装置
 21 NIC
 22 メモリ
 23a 第1のプロセッサ
 23b 第2のプロセッサ
 23c 第3のプロセッサ
 30 ユーザ端末
 40 生成装置
 41 生成部
 42 送信部
 43 記憶部
 50 通信ネットワーク
 901 CPU
 902 メモリ
 903 ストレージ
 904 通信装置
 905 入力装置
 906 出力装置
1 System 10 Camera 20 Processing device 21 NIC
22 Memory 23a First processor 23b Second processor 23c Third processor 30 User terminal 40 Generation device 41 Generation unit 42 Transmission unit 43 Storage unit 50 Communication network 901 CPU
902 Memory 903 Storage 904 Communication device 905 Input device 906 Output device

Claims (5)

 事前に確定しているデータストリーム群のデータの到着時刻に基づき、前記データストリーム群内でデータ周期が同一又はデータ特性が類似する複数のデータストリームのデータを、連続する記憶領域に配置するデータ配置計画を生成する生成部、
 を備える生成装置。
a generation unit that generates a data allocation plan for allocating data of a plurality of data streams having the same data period or similar data characteristics within a data stream group into consecutive storage areas based on arrival times of data of the data stream group that have been determined in advance;
A generating device comprising:
 前記生成部は、
 前記連続する記憶領域から前記複数のデータストリームのデータをまとめて一度に読み出すデータ読出計画を生成する請求項1に記載の生成装置。
The generation unit
The generating device according to claim 1 , further comprising: a data readout plan for reading the data of the plurality of data streams from the continuous storage area all at once;
 前記生成部は、
 多段な複数のプロセッサのうち前段のプロセッサが前記複数のデータストリームのデータを全て処理した後に、前記複数のデータストリームのデータをまとめて一度に後段のプロセッサへ転送するデータ転送計画を生成する請求項1に記載の生成装置。
The generation unit
The generation device according to claim 1 generates a data transfer plan in which, after a first-stage processor among a plurality of multi-stage processors processes all of the data of the plurality of data streams, the data of the plurality of data streams is transferred all at once to a second-stage processor.
 生成装置で行う生成方法において、
 事前に確定しているデータストリーム群のデータの到着時刻に基づき、前記データストリーム群内でデータ周期が同一又はデータ特性が類似する複数のデータストリームのデータを、連続する記憶領域に配置するデータ配置計画を生成する、
 生成方法。
In a generation method performed by a generation device,
generating a data allocation plan for allocating data of a plurality of data streams having the same data period or similar data characteristics within the data stream group into consecutive storage areas based on the arrival times of data of the data stream group that are determined in advance;
Generation method.
 請求項1乃至3のいずれかに記載の生成装置としてコンピュータを機能させる生成プログラム。 A generation program that causes a computer to function as the generation device described in any one of claims 1 to 3.
PCT/JP2024/007541 2024-02-29 2024-02-29 Generation device, generation method, and generation program Pending WO2025182009A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06348776A (en) * 1993-06-07 1994-12-22 Toshiba Corp Logic simulation device
JP2001188701A (en) * 1999-10-21 2001-07-10 Matsushita Electric Ind Co Ltd Access device for semiconductor memory card, computer-readable recording medium, initialization method, and semiconductor memory card
JP2003233821A (en) * 2002-02-06 2003-08-22 Sony Corp Image processor and image processing method
JP2011198357A (en) * 2010-02-26 2011-10-06 Jvc Kenwood Corp Processing device and write method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06348776A (en) * 1993-06-07 1994-12-22 Toshiba Corp Logic simulation device
JP2001188701A (en) * 1999-10-21 2001-07-10 Matsushita Electric Ind Co Ltd Access device for semiconductor memory card, computer-readable recording medium, initialization method, and semiconductor memory card
JP2003233821A (en) * 2002-02-06 2003-08-22 Sony Corp Image processor and image processing method
JP2011198357A (en) * 2010-02-26 2011-10-06 Jvc Kenwood Corp Processing device and write method

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