WO2025179543A1 - Shift register unit and driving method therefor, and display panel - Google Patents

Abstract

A shift register unit and a driving method therefor, and a display substrate. The shift register unit comprises a node control sub-circuit, a pull-down sub-circuit and an output sub-circuit. The node control sub-circuit is electrically connected to a signal input end, a first clock signal end, a second clock signal end, a power supply signal end, a first reference signal end, a first node and a second node, and is configured to provide to the first node a signal from the signal input end under the control of a signal from the first clock signal end, provide to the second node a signal from the first reference signal end or the first clock signal end under the control of signals from the first node and the first clock signal end, and provide to the first node a signal from the power supply signal end under the control of the second node and the second clock signal end, wherein the level of the signal from the first reference signal end is lower than the level of a signal from a second reference signal end.

Description

Shift register unit, driving method thereof, and display panel Technical Field

The present disclosure relates to, but is not limited to, the field of display technology, and particularly to a shift register unit, a driving method thereof, and a display substrate.

Background Art

Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting elements and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art.

Summary of the Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

In a first aspect, the present disclosure provides a shift register unit, comprising:

a node control subcircuit, electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the power signal terminal, the first reference signal terminal, the first node, and the second node, and configured to provide a signal from the signal input terminal to the first node under control of a signal from the first clock signal terminal, provide a signal from the first reference signal terminal or the first clock signal terminal to the second node under control of signals from the first node and the first clock signal terminal, and provide a signal from the power signal terminal to the first node under control of the second node and the second clock signal terminal;

a pull-down sub-circuit electrically connected to the first node and the first reference signal terminal, and configured to provide a signal of the first reference signal terminal to the first node;

an output subcircuit electrically connected to the first node, the second node, the second clock signal terminal, the third clock signal terminal, the power signal terminal, the second reference signal terminal, the first signal output terminal, and the second output signal terminal, and configured to, under control of the signals of the first node and the second node, provide a signal from the power signal terminal or the second clock signal terminal to the first signal output terminal, and provide a signal from the second reference signal terminal or the third clock signal terminal to the second signal output terminal;

The signal level of the first reference signal terminal is lower than the signal level of the second reference signal terminal.

In an exemplary embodiment, a signal low level of at least one of the first clock signal terminal and the second clock signal terminal is lower than a signal level of the second reference signal terminal.

In an exemplary embodiment, the low level of a signal of at least one of the first clock signal terminal and the second clock signal terminal is equal to the signal level of the first reference signal terminal.

In an exemplary embodiment, the low level of the signal at the third clock signal terminal is equal to the signal level at the second reference signal terminal.

In an exemplary embodiment, the signal level of the first reference signal terminal and the signal low level of at least one of the first clock signal terminal and the second clock signal terminal are in the range of -15V to -9V, and the signal level of the second reference signal terminal is in the range of -4V to -8V.

In an exemplary embodiment, the node control subcircuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor;

The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node;

The control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the second node;

A control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is connected to the first reference signal terminal, and a second electrode of the third transistor is electrically connected to the second node;

The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the fourth node;

The control electrode of the fifth transistor is electrically connected to the second clock signal terminal, the first electrode of the fifth transistor is connected to the fourth node, and the second electrode of the fifth transistor is electrically connected to the first node.

In an exemplary embodiment, the output sub-circuit includes: a sixth transistor, a seventh transistor, an eighth transistor a transistor, a ninth transistor, a first capacitor, and a second capacitor;

The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is connected to the power signal terminal, and the second electrode of the sixth transistor is electrically connected to the first signal output terminal;

The control electrode of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is connected to the second clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the first signal output terminal;

The control electrode of the eighth transistor is electrically connected to the first node, the first electrode of the eighth transistor is connected to the third clock signal terminal, and the second electrode of the eighth transistor is electrically connected to the second signal output terminal;

The control electrode of the ninth transistor is electrically connected to the second node, the first electrode of the ninth transistor is electrically connected to the second reference signal terminal, and the second electrode of the ninth transistor is electrically connected to the second signal output terminal;

The first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the power signal terminal;

The first plate of the second capacitor is electrically connected to the control electrode of the seventh transistor, and the second plate of the second capacitor is electrically connected to the first signal output terminal.

In an exemplary embodiment, the output sub-circuit further includes: a tenth transistor, the control electrode of the seventh transistor being electrically connected to the first node through the tenth transistor;

The control electrode of the tenth transistor is electrically connected to the second reference signal terminal, the first electrode of the tenth transistor is connected to the first node, and the second electrode of the tenth transistor and the control electrode of the seventh transistor are connected to the third node.

In an exemplary embodiment, the output sub-circuit further includes: an eleventh transistor; the control electrode of the eighth transistor is electrically connected to the first node through the eleventh transistor;

The control electrode of the eleventh transistor is electrically connected to the second reference signal terminal, the first electrode of the eleventh transistor is electrically connected to the first node, and the second electrode of the eleventh transistor is electrically connected to the control electrode of the eighth transistor.

In an exemplary embodiment, the pull-down sub-circuit includes: a twelfth transistor;

The control electrode of the twelfth transistor is electrically connected to the third node, the first electrode of the twelfth transistor is electrically connected to the first reference signal terminal, and the second electrode of the twelfth transistor is electrically connected to the first node.

In an exemplary embodiment, at least one of the first to twelfth transistors is a low temperature polysilicon transistor.

In an exemplary embodiment, at least one of the first to twelfth transistors is a P-type low temperature polysilicon transistor.

In an exemplary embodiment, the shift register unit further includes: a voltage stabilizing subcircuit, which is connected to the first node, the second node and the first reference signal terminal, and is configured to provide the signal of the first reference signal terminal to the second node under the control of the first node.

In an exemplary embodiment, the voltage stabilization sub-circuit includes: a thirteenth transistor, a control electrode of the thirteenth transistor connected to the first node, a first electrode of the thirteenth transistor connected to the first reference signal terminal, and a second electrode of the thirteenth transistor connected to the second node.

In an exemplary embodiment, the thirteenth transistor is a metal oxide transistor.

In an exemplary embodiment, the thirteenth transistor is an N-type metal oxide transistor.

In an exemplary embodiment, the signal at the third clock signal terminal and the signal at the second clock signal terminal are inverted signals in a partial time period.

In an exemplary embodiment, the signal at the first clock signal terminal and the signal at the second clock signal terminal are not at active levels at the same time.

In a second aspect, the present disclosure further provides a display substrate, comprising: a substrate, and sub-pixels, gate lines, and a gate driving circuit disposed on the substrate, wherein the substrate is provided with a display area and a non-display area, the gate driving circuit is located in the non-display area, the sub-pixels and the gate lines are located in the display area, and the gate lines are electrically connected to the sub-pixels and the gate driving circuit, respectively;

The gate drive circuit includes: a plurality of cascaded shift register units according to any one of claims 1 to 18, wherein the first signal output end of the n-th stage shift register unit is connected to the signal input end of the n+i-th stage shift register unit, 1≤n＜N, i is an integer greater than or equal to 1, and N is the total number of shift register units.

In an exemplary embodiment, the first signal output terminal of the shift register unit is electrically connected to the gate line.

In an exemplary embodiment, the display substrate further includes: a first clock signal line, a second clock signal line, a power signal line, a first reference signal line, a second reference signal line, a third reference signal line, a third clock signal line, and a fourth reference signal line disposed on the base, located in the non-display area and extending along the first direction;

The first clock signal line, the second clock signal line, the power signal line, the first reference signal line, the second reference signal line, the third reference signal line, the third clock signal line and the fourth reference signal line are arranged in sequence along a second direction toward the display area, and the first direction intersects the second direction;

The first reference signal line and the third reference signal line are connected to the first reference signal line of the shift register unit. Test the signal end;

The second reference signal line and the fourth reference signal line are connected to the second reference signal terminal of the shift register unit;

The power signal line is connected to the power signal terminal of the shift register unit;

The first clock signal line is connected to the first clock signal terminal of the shift register unit, the second clock signal line is connected to the second clock signal terminal of the shift register unit, and the third clock signal line is connected to the third clock signal terminal of the shift register unit.

In an exemplary embodiment, the display substrate further includes an initial signal line and a fourth clock signal line extending along the first direction, the initial signal line being located on a side of the first clock signal line away from the display area along the second direction, and the fourth clock signal line being located between the third clock signal line and the fourth reference signal line.

In an exemplary embodiment, the first transistor, the second transistor, and the third transistor of the shift register unit are located between the power signal line and the second reference signal line, the second transistor and the third transistor are located between the first reference signal line and the second reference signal line, and the first transistor is located between the power signal line and the first reference signal line.

In an exemplary embodiment, the shift register unit further includes a thirteenth transistor, which is located between the first reference signal line and the second reference signal line, a first electrode of the thirteenth transistor is connected to the first reference signal line, and a second electrode of the thirteenth transistor and the second electrode of the third transistor are connected to a second node.

In an exemplary embodiment, the active layer of the thirteenth transistor extends along the second direction.

In an exemplary embodiment, the second transistor and the third transistor are located on the same side of the active layer of the thirteenth transistor along the first direction.

In an exemplary embodiment, a control electrode of the thirteenth transistor is connected to a first node across the first reference signal line and the second electrode of the first transistor.

In an exemplary embodiment, a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer are sequentially stacked on the substrate;

The control electrode of at least one of the first to twelfth transistors of the shift register unit and the first electrode plate of at least one of the first capacitor and the second capacitor are located in the first conductive layer;

The second electrode plate of at least one of the first capacitor and the second capacitor is located in the second conductive layer;

The initial signal line, the power signal line, the second reference signal line, the fourth reference signal line and the first electrodes and the second electrodes of the plurality of transistors of the shift register unit are located in the third conductive layer;

The first reference signal line is located in the third conductive layer or the fourth conductive layer, and the third reference signal line is located in the third conductive layer or the fourth conductive layer.

In an exemplary embodiment, the first reference signal line and the third reference signal line are both located in the fourth conductive layer.

In an exemplary embodiment, at least one of the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line has a first sublayer located in the third conductive layer and a second sublayer located in the fourth conductive layer.

In an exemplary embodiment, the first semiconductor layer is a low-temperature polysilicon semiconductor layer.

In an exemplary embodiment, a second semiconductor layer and a fifth conductive layer are further provided between the second conductive layer and the third conductive layer;

The shift register unit further includes a thirteenth transistor, wherein the active layer of the thirteenth transistor is located in the second semiconductor layer, the control electrode of the thirteenth transistor is located in the fifth conductive layer, and the first electrode and the second electrode of the thirteenth transistor are located in the third conductor layer.

In example embodiments, the second semiconductor layer is an oxide semiconductor layer.

In a third aspect, the present disclosure further provides a display device, comprising: the above-mentioned display substrate.

In a fourth aspect, the present disclosure further provides a method for driving a shift register unit, which is configured to drive the shift register unit. The method includes:

The node control subcircuit provides a signal from the signal input terminal to the first node under the control of the signal from the first clock signal terminal, and provides a signal from the first reference signal terminal or the first clock signal terminal to the second node under the control of the signals from the first node and the first clock signal terminal;

The pull-down sub-circuit provides a signal of the first reference signal terminal to the first node;

Under the control of the signals of the first node and the second node, the output subcircuit provides the signal of the power signal terminal or the second clock signal terminal to the first signal output terminal, and provides the signal of the second reference signal terminal or the third clock signal terminal to the second signal output terminal.

BRIEF DESCRIPTION OF THE DRAWINGS

The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

FIG1 is a schematic structural diagram of a shift register unit provided by an embodiment of the present disclosure;

FIG2 is one of the equivalent circuit diagrams of the shift register unit provided in an embodiment of the present disclosure;

FIG3 is a signal timing simulation diagram of the shift register provided in FIG2 ;

4 is a schematic diagram of a signal simulation waveform at a second output signal terminal when the second node in the shift register unit is undercompensated according to an exemplary embodiment of the present disclosure;

FIG5 is one of the equivalent circuit diagrams of the shift register unit provided in an embodiment of the present disclosure;

FIG6 is a signal timing simulation diagram of the shift register provided in FIG5 ;

FIG7 is a schematic structural diagram of a display device;

FIG8 is a schematic diagram of a cascade connection of a gate driving circuit according to an exemplary embodiment of the present disclosure;

FIG9 is a partial schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure;

FIG10 is a partial schematic plan view of the first semiconductor layer in the display substrate according to FIG9 ;

FIG11 is a partial schematic plan view of the first conductive layer in the display substrate according to FIG9 ;

FIG12 is a partial plan view of the second conductive layer in the display substrate according to FIG9 ;

FIG13 is a partial schematic plan view of the third conductive layer in the display substrate according to FIG9 ;

FIG14 is a partial plan view of the fourth conductive layer in the display substrate according to FIG9 ;

FIG15 is a partial plan view of a combined film layer of a first semiconductor layer and a first conductive layer in the display substrate according to FIG9 ;

FIG16 is a partial plan view of a combined film layer of the first semiconductor layer, the first conductive layer, the second conductive layer and the third conductive layer in the display substrate according to FIG9 ;

FIG17 is a structural diagram of a sub-pixel in a display area of a display substrate according to an exemplary embodiment of the present disclosure;

FIG18 is a partial schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure;

FIG19 is a partial schematic plan view of the first semiconductor layer in the display substrate according to FIG18 ;

FIG20 is a partial plan view of the first conductive layer in the display substrate according to FIG18 ;

FIG21 is a partial plan view of the second conductive layer in the display substrate according to FIG18 ;

FIG22 is a partial schematic plan view of the second semiconductor layer in the display substrate according to FIG18 ;

FIG23 is a partial schematic plan view of the fifth conductive layer in the display substrate according to FIG18 ;

FIG24 is a partial plan view of the third conductive layer in the display substrate according to FIG18 ;

FIG. 25 is a partial schematic plan view of the fourth conductive layer in the display substrate according to FIG. 18 .

It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present invention, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale.

DETAILED DESCRIPTION

In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings below. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

In the drawings, the sizes of various components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or numerical values shown in the drawings.

In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle,""upper,""lower,""front,""back,""vertical,""horizontal,""top,""bottom,""inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

In this specification, the control electrode can be the gate electrode, the first electrode can be the drain electrode, and the second electrode can be the source electrode, or the first electrode can be the source electrode and the second electrode can be the drain electrode. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

In this specification, triangles, rectangles, trapezoids, pentagons or hexagons are not strictly defined. It is approximately a triangle, rectangle, trapezoid, pentagon or hexagon, etc., and there may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

The display substrate includes a pixel driver circuit, light-emitting elements, and a gate driver circuit. The gate driver circuit is configured to provide gate signals to the transistors in the pixel driver circuit, enabling the pixel driver circuit to drive the light-emitting elements to emit light. The display substrate utilizes low-temperature polysilicon (LTPS) technology, which boasts advantages such as high resolution, fast response time, high brightness, and a high aperture ratio. While popular in the market, LTPS technology also has drawbacks, such as high production costs and high power consumption. This is why low-temperature polycrystalline oxide (LTPO) technology has emerged as a viable solution. Compared to LTPS technology, which includes low-temperature polysilicon transistors in the pixel driver circuit, LTPO technology incorporates both low-temperature polysilicon transistors and metal oxide transistors. Metal oxide transistors have lower leakage current, resulting in faster pixel response. The display substrate incorporates an additional oxide layer, which reduces the energy required to activate the pixels, thereby reducing power consumption during screen display. Display products using LTPO technology include a driver circuit to control the metal oxide transistors within the display. As display substrates increase in size, resolution, and refresh rate, the compensation time of pixel driver circuits within a frame is becoming increasingly shorter. Furthermore, the driver circuits used to control metal oxide transistors (MOS transistors) in display substrates often experience insufficient voltage at some nodes, preventing the output signal from the driver circuit from reaching the desired voltage. This results in weak driving capability for the MOS transistors, which in turn leads to a lowered conduction level for the MOS transistors, impacting the performance of the pixel driver circuit and, consequently, reducing the display quality of the display substrate.

FIG1 is a schematic structural diagram of a shift register unit provided in an embodiment of the present disclosure; FIG2 is one of equivalent circuit diagrams of a shift register unit provided in an embodiment of the present disclosure.

As shown in FIG. 1 , the shift register unit provided by the embodiment of the present disclosure may include: a node control sub-circuit 100 , a pull-down sub-circuit 200 , and an output sub-circuit 300 .

As shown in FIG1 , the node control subcircuit 100 is electrically connected to the signal input terminal IN, the first clock signal terminal CK1, the second clock signal terminal CK2, the power signal terminal VGH, the first reference signal terminal VGL1, the first node N1, and the second node N2. The node control subcircuit 100 can provide the signal of the signal input terminal IN to the first node N1 under the signal control of the first clock signal terminal CK1. The first reference signal terminal VGL1 or the first clock signal terminal CK1 is provided to the second node N2 under the control of the signal, and the power signal terminal VGH is provided to the first node N1 under the control of the second node N2 and the second clock signal terminal CK2.

The pull-down sub-circuit 200 is electrically connected to the first node N1 and the first reference signal terminal VGL1 , and the pull-down sub-circuit 200 provides the signal of the first reference signal terminal VGL1 to the first node N1 .

The output sub-circuit 300 is electrically connected to the first node N1, the second node N2, the second clock signal terminal CK2, the third clock signal terminal CK3, the power signal terminal VGH, the second reference signal terminal VGL2, the first signal output terminal OUT1, and the second output signal terminal OUT2, respectively. Under the control of the signals of the first node N1 and the second node N2, the output sub-circuit 300 provides the signal of the power signal terminal VGH or the second clock signal terminal CK2 to the first signal output terminal OUT1, and provides the signal of the second reference signal terminal VGL2 or the third clock signal terminal CK3 to the second signal output terminal OUT2.

According to an embodiment of the present disclosure, the signal level of the first reference signal terminal VGL1 can be lower than the signal level of the second reference signal terminal VGL2. The low level of the signal of at least one of the first clock signal terminal CK1 and the second clock signal terminal CK2 can be lower than the signal level of the second reference signal terminal VGL2. For example, the signal level of the first reference signal terminal VGL1 and the low level of the signal of at least one of the first clock signal terminal CK1 and the second clock signal terminal CK2 can be in the range of -15V to -9V, and the signal level of the second reference signal terminal VGL2 can be in the range of -4V to -8V.

In an exemplary embodiment, the power signal terminal VGH can receive a power signal, which can be a constant high level, for example, in the range of 10V to 18V, and in some embodiments, approximately 14V. The first reference signal terminal VGL1 can receive a first reference signal, and the second reference signal terminal VGL2 can receive a second reference signal. The first reference signal and the second reference signal can both be constant low levels. For example, the signal level of the first reference signal can be a constant first reference level, which can be in the range of -15V to -9V, and in some embodiments, can be -12V. The signal level of the second reference signal can be a constant second reference level, which can be in the range of -4V to -8V, and in some embodiments, can be -6V.

In the related art, there may be a loss of compensation voltage at the second node N2, resulting in insufficient voltage being written to some transistors in the output sub-circuit, which makes it impossible to start, causing leakage in the gate drive circuit during operation. As shown in Figure 4, the horizontal axis is time (in seconds) and the vertical axis is voltage (in V). When the compensation voltage at the second node N2 is insufficient, the output signal of the second signal output terminal OUT2 has an obvious voltage drop. Fluctuation. As can be seen from Figure 4, the output signal of the second signal output terminal OUT2 is a high voltage pulse. The low level of this output signal cannot be maintained at a stable level. When the pulse ends, the voltage drops to about -7V, then gradually increases, and rises to about -6V at the beginning of the next pulse, which has an adverse effect on the display effect.

The exemplary embodiment of the present disclosure connects the node control sub-circuit 100 and the output sub-circuit to the first reference signal terminal VGL1 and the second reference signal terminal VGL2 respectively, and makes the first reference signal terminal VGL1 smaller than the second reference signal terminal VGL2. This can make the voltage at the second node N2 lower, which is beneficial to the normal operation of the output sub-circuit 300 coupled to the second node N2 and avoids leakage problems caused by the loss of compensation voltage at the second node N2.

In an exemplary embodiment, referring to FIG2 , the node control subcircuit 100 may include a first transistor T1, a second transistor T2, and a third transistor T3. The control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK1, the first electrode of the first transistor is connected to the signal input terminal IN, and the second electrode of the first transistor is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK1, and the second electrode of the second transistor T2 is electrically connected to the second node N2. The control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, the first electrode of the third transistor T3 is connected to the first reference signal terminal VGL1, and the second electrode of the third transistor T3 is electrically connected to the second node N2.

For example, the first transistor T1 may be controlled to turn on by the first clock signal terminal CK1 to write the input signal provided by the signal input terminal IN into the first node N1.

For example, the second transistor T2 may be controlled to turn on by the voltage signal of the first node N1 , so that the first clock signal provided by the first clock signal terminal CK1 is written into the second node N2 .

For example, the third transistor T3 may be controlled to turn on by the first clock signal terminal CK1 to write the first reference signal terminal VGL1 into the second node N2.

In an exemplary embodiment, the node control subcircuit 100 may further include a fourth transistor T4 and a fifth transistor T5. The control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to the power signal terminal VGH, and the second electrode of the fourth transistor T4 is electrically connected to the fourth node N4. The control electrode of the fifth transistor T5 is electrically connected to the second clock signal terminal CK2, the first electrode of the fifth transistor T5 is electrically connected to the fourth node N4, and the second electrode of the fifth transistor T5 is electrically connected to the first node N1.

For example, the fourth transistor T4 can be turned on by controlling the voltage of the second node N2, and the fifth transistor T5 can be turned on by controlling the signal provided by the second clock signal terminal CK2, so that the signal provided by the power signal terminal VGH is written into the first node N1.

In an exemplary embodiment, the output sub-circuit 300 may include: a sixth transistor T6 , a seventh transistor T7 , an eighth transistor T8 , a ninth transistor T9 , a first capacitor C1 , and a second capacitor C2 .

A control electrode of the sixth transistor T6 is electrically connected to the second node N2 , a first electrode of the sixth transistor T6 is connected to the power signal terminal VGH, and a second electrode of the sixth transistor T6 is electrically connected to the first signal output terminal OUT1 .

A control electrode of the seventh transistor T7 is electrically connected to the first node N1 , a first electrode of the seventh transistor T7 is connected to the second clock signal terminal CK2 , and a second electrode of the seventh transistor T7 is electrically connected to the first signal output terminal OUT1 .

A control electrode N1 of the eighth transistor T8 is electrically connected to the first node N1 , a first electrode of the eighth transistor T8 is connected to the third clock signal terminal CK3 , and a second electrode of the eighth transistor T8 is electrically connected to the second signal output terminal OUT2 .

A control electrode of the ninth transistor T9 is electrically connected to the second node N2 , a first electrode of the ninth transistor T9 is electrically connected to the second reference signal terminal VGL2 , and a second electrode of the ninth transistor T9 is electrically connected to the second signal output terminal OUT2 .

For example, the voltage at the second node N2 can affect the conduction of the ninth transistor T9. For example, if the compensation voltage at the second node N2 is insufficient, the ninth transistor T9 may not turn on properly, thereby causing output leakage. By designing the first reference signal terminal VGL1 to be lower than the second reference signal terminal VGL2 in the output sub-circuit 300 (for example, the first reference signal terminal VGL1 is -12V and the second reference signal terminal VGL2 is -6V), the voltage at the second node N2 can be lowered, which facilitates the normal operation of the ninth transistor T9 and avoids leakage caused by the loss of the compensation voltage at the second node N2.

A first plate of the first capacitor C1 is electrically connected to the second node N2 , and a second plate of the first capacitor C1 is electrically connected to the power signal terminal VGH.

A first plate of the second capacitor C2 is electrically connected to the control electrode of the seventh transistor T7 , and a second plate of the second capacitor C2 is electrically connected to the first signal output terminal OUT1 .

In some embodiments, the output sub-circuit 300 may further include a third capacitor C3 and a fourth capacitor C4 (not shown) in addition to the first capacitor C1 and the second capacitor C2. The first plate of the third capacitor C3 is electrically connected to the control electrode of the eighth transistor T8, and the second plate of the third capacitor C3 is connected to the second signal output terminal OUT3. A first plate of the fourth capacitor C4 is electrically connected to the second node N2 , and a second plate of the fourth capacitor C4 is electrically connected to the second reference signal terminal VGL2 .

For example, the connection path between the control electrode of the seventh transistor T7 and the first node N1 may further include another transistor, such as a tenth transistor T10. The control electrode of the seventh transistor T7 is electrically connected to the first node N1 via the tenth transistor T10. The control electrode of the tenth transistor T10 is electrically connected to the second reference signal terminal VGL2, a first electrode of the tenth transistor T10 is connected to the first node N1, and a second electrode of the tenth transistor T10 and the control electrode of the seventh transistor T7 are connected to the third node N3.

For example, the connection path between the control electrode of the eighth transistor T8 and the first node N1 may further include another transistor, such as an eleventh transistor T11. The control electrode of the eighth transistor T8 is electrically connected to the first node N1 via the eleventh transistor T11. The control electrode of the eleventh transistor T11 is electrically connected to the second reference signal terminal VGL2, a first electrode of the eleventh transistor T11 is electrically connected to the first node N1, and a second electrode of the eleventh transistor T11 is electrically connected to the control electrode of the eighth transistor T8.

In an exemplary embodiment, the pull-down sub-circuit 200 may include a twelfth transistor T12. A control electrode of the twelfth transistor T12 is electrically connected to the third node N3, a first electrode of the twelfth transistor T12 is electrically connected to the first reference signal terminal VGL1, and a second electrode of the twelfth transistor T12 is electrically connected to the first node N1. The pull-down sub-circuit can write a signal from the first reference signal terminal VGL1 to the first node N1, ensuring a low potential at the first node N1. By providing the pull-down sub-circuit, the signal at the first node can be pulled down to a low-level signal with a relatively low voltage value, allowing some transistors in the shift register unit to fully turn on. This allows the voltage of the output signal of the shift register unit to reach a predetermined voltage, thereby improving the driving capability of the shift register unit and ensuring the conduction capability of the transistors in the pixel driver circuit. This in turn improves the performance of the pixel driver circuit and the display effect of the display substrate.

It should be understood that in the pixel circuit provided in the embodiments of the present disclosure, the first node N1, the second node N2, the third node N3, and the fourth node N4 do not necessarily represent actual components. In some embodiments, these nodes represent the junction points of related couplings (i.e., electrical connections) in the equivalent circuit diagram of the pixel circuit. That is, these nodes are nodes formed by the equivalent junction points of related electrical connections in the circuit diagram.

In an exemplary embodiment, a signal low level of at least one of the first clock signal terminal CK1 and the second clock signal terminal CK2 is equal to a signal level of the first reference signal terminal VGL1 .

In an exemplary embodiment, the low level of the signal at the third clock signal terminal CK3 is equal to the low level of the signal at the second reference signal terminal The signal level of VGL2.

In an exemplary embodiment, the signal level of the first reference signal terminal VGL1 and the signal low level of at least one of the first clock signal terminal CK1 and the second clock signal terminal CK2 are within a range of -15 V to -9 V, and the signal level of the second reference signal terminal VGL2 is within a range of -4 V to -8 V. For example, the signal level of the first reference signal terminal VGL1 is -12 V, and the signal level of the second reference signal terminal VGL2 is -6 V.

By setting the first reference signal terminal VGL1 in the node control sub-circuit to be lower than the second reference signal terminal VGL2 in the output sub-circuit, the voltage at the second node N2 can be lowered, for example, lower than the second reference signal terminal VGL2, thereby facilitating the normal operation of the output sub-circuit 300 coupled to the second node. For example, if the signal level of the first reference signal terminal VGL1 is higher, for example, equal to the signal level of the second reference signal terminal VGL2, then when the signal level of the first clock signal terminal CK1 reaches a low level, the third transistor T3 is turned on, and the control electrode and the first electrode of the ninth transistor T9 are both low, i.e., equal to the voltage of the second reference signal terminal VGL2. In this case, due to the threshold voltage loss of the ninth transistor T9, the voltage difference between the control electrode and the first electrode of the ninth transistor T9 is insufficient to turn on the ninth transistor T9, thereby preventing the ninth transistor T9 from providing the low-level signal of the second reference signal terminal VGL2 to the output signal terminal OUT2. In the embodiments of the present disclosure, by setting the signal level of the first reference signal terminal VGL1 lower than the signal level of the second reference signal terminal VGL2, the second node N2 can be pulled to a level lower than VGL2 when the third transistor T3 is turned on, thereby increasing the voltage difference between the control electrode and the first electrode of the ninth transistor T9, thereby ensuring that the ninth transistor T9 can be turned on normally. In this way, the voltage of the second node N2 is optimized, avoiding output leakage problems in the output sub-circuit caused by insufficient write voltage at the second node N2. In addition, the embodiments of the present disclosure further stabilize the voltage of the second node N2 by setting the signal low level of at least one of the first clock signal terminal CK1 and the second clock signal terminal CK2 to be lower than the level of the second reference signal terminal VGL2. For example, the signal low level of the first clock signal terminal CK1 is lower than the level of the second reference signal terminal VGL2, which is conducive to fully turning on the third transistor T3 and the first transistor T1. The signal low level of the second clock signal terminal CK2 is lower than the level of the second reference signal terminal VGL2, which is conducive to fully turning on the fifth transistor T5. By making the signal low level of the third clock signal terminal CK3 equal to the level of the second reference signal terminal VGL2, the signal low level generated at the second output signal terminal OUT2 when the eighth transistor T8 is turned on is consistent with the signal low level generated at the second output signal terminal OUT2 when the ninth transistor T9 is turned on.

In an exemplary embodiment, at least one of the first to twelfth transistors T1 to T12 may be It is a low-temperature polysilicon transistor, for example, a P-type low-temperature polysilicon transistor.

In an exemplary embodiment, the signal at any one of the first clock signal terminal CK1, the second clock signal terminal CK2, and the third clock signal terminal CK3 may be a periodic pulse signal. In an exemplary embodiment, the signal at the first clock signal terminal CK1 and the signal at the second clock signal terminal CK2 are not simultaneously active level signals. For example, when the signal at the first clock signal terminal CK1 is active level, the signal at the second clock signal terminal CK2 is inactive level; and when the signal at the second clock signal terminal CK2 is active level, the signal at the first clock signal terminal CK1 is inactive level. In an exemplary embodiment, the signal at the third clock signal terminal CK3 and the signal at the second clock signal terminal CK2 may or may not be inverted phases. When the signal at the third clock signal terminal CK3 and the signal at the second clock signal terminal CK2 are inverted phases, when the signal at the third clock signal terminal CK3 is active level, the signal at the second clock signal terminal CK2 is inactive level; and when the signal at the third clock signal terminal CK3 is inactive level, the signal at the second clock signal terminal CK2 is active level.

In an exemplary embodiment, the signal at the signal output terminal IN is a single pulse signal.

In an exemplary embodiment, the signals at the first signal output terminal OUT1 and the second signal output terminal OUT2 are single-shot pulse signals, and the signals at the first signal output terminal OUT1 and the second signal output terminal OUT2 are inverted signals. That is, when the signal at the first signal output terminal OUT1 is a high-level signal, the signal at the second signal output terminal OUT2 is a low-level signal, and when the signal at the first signal output terminal OUT1 is a low-level signal, the signal at the second signal output terminal OUT2 is a high-level signal. In an exemplary embodiment, the first signal output terminal OUT1 is configured to output a cascade signal, which is a low-level signal, and the second signal output terminal OUT2 is configured to output a gate scan signal. Exemplarily, the gate scan signal is a high-level signal or a low-level signal.

Fig. 3 is a signal timing simulation diagram of the shift register provided in Fig. 2. Fig. 3 is illustrated by taking an example where all transistors in the shift register are P-type transistors.

2 and 3 , the operation process of the control shift register unit provided in FIG2 includes the following stages:

In the first phase S1, i.e., the input phase, the signals at the signal input terminal IN, the first clock signal terminal CK1, and the third clock signal terminal CK3 are low-level signals, and the signal at the second clock signal terminal CK2 is high-level signal. The signal at the first clock signal terminal CK1 is low-level signal, the first transistor T1 and the third transistor T3 are turned on, The low-level signal at the signal input terminal IN is written to the first node N1, and the low-level signal at the first reference signal terminal VGL1 is written to the second node N2. Because the tenth transistor T10 is continuously on, the signals at the third node N3 and the first node N1 are both low-level signals. The signal at the first node N1 is a low-level signal, and the eleventh transistor T11 is continuously on. Therefore, the second transistor T2 and the eighth transistor T8 are turned on, and the low-level signal at the first clock signal terminal CK1 is written to the second node N2, ensuring that the signal at the second node N2 remains a low-level signal. The low-level signal at the third clock signal terminal CK3 is written to the second signal output terminal OUT2. The signal at the second node N2 is a low-level signal, and the sixth transistor T6 and the ninth transistor T9 are turned on. The high-level signal at the power supply signal terminal VGH is written to the first signal output terminal OUT1, and the low-level signal at the second reference signal terminal VGL2 is written to the second signal output terminal OUT2. The signal at the third node N3 is a low-level signal, and the seventh transistor T7 is turned on, thereby providing the high-level signal at the second clock signal terminal CK2 to the first output signal terminal. The low level at the third node N3 also turns on the twelfth transistor T12, thereby writing the signal at the first reference signal terminal VGL1 to the first node N1, further pulling down the level of the signal at the first node N1 and causing the signal at the first node N1 to remain low. Because the signal at the second clock signal terminal CK2 is high, the fifth transistor T5 is off. Even if the low level at the second node N2 turns on the fourth transistor T4, the high level signal at the power supply signal terminal VGH is not written to the first node N1, and the signal at the first node N1 is not pulled high. In this stage, the signals at the first node N1, the second node N2, and the third node N3 are low level signals, and the signal at the fourth node N4 is high level. The signal at the power supply signal terminal VGH is written to the first signal output terminal OUT1, and the output signal of the first signal output terminal OUT1 is high level. The signal at the third clock signal terminal CK3 and the signal at the second reference signal terminal VGL2 are written to the second signal output terminal OUT2, and the output signal of the second signal output terminal OUT2 is low level.

In the second stage S2, i.e., the output stage, the signals of the signal input terminal IN, the first clock signal terminal CK1 and the third clock signal terminal CK3 are high-level signals, and the signal of the second clock signal terminal CK2 is a low-level signal. The signal of the first clock signal terminal CK1 is a high-level signal, the first transistor T1 and the third transistor T3 are disconnected, and the signal of the first node N1 remains a low-level signal. Since the tenth transistor T10 is continuously turned on, the signal of the third node N3 and the signal of the first node N1 are both low-level signals. The signal of the first node N1 is a low-level signal and the eleventh transistor T11 is continuously turned on, the second transistor T2 and the eighth transistor T8 are turned on, the high-level signal of the first clock signal terminal CK1 is written into the second node N2, the signal of the second node N2 is a high-level signal, the high-level signal of the third clock signal terminal CK3 is written into the second signal output terminal OUT2, the signal of the second node N2 is a high-level signal, the fourth transistor T4, the sixth transistor T6 and the ninth transistor T9 are disconnected, and the power signal terminal The high-level signal of VGH cannot be written to the first signal output terminal OUT1, and the low-level signal of the second reference signal terminal VGL2 cannot be written to the second signal output terminal OUT2. The signal of the third node N3 is a low-level signal. The seventh transistor T7 and the twelfth transistor T12 are turned on. The signal of the first reference signal terminal VGL1 is written to the first node N1, maintaining the signal of the first node N1 at a continuous low-level signal. The low-level signal of the second clock signal terminal CK2 is written to the first signal output terminal OUT1. Because the signal of the second clock signal terminal CK2 is a low-level signal, the fifth transistor T5 is turned on. The signal of the fourth node N4 is pulled low by the signal of the first node N1, and the signal of the fourth node N4 is a low-level signal. In this stage, the signals of the first node N1, the third node N3, and the fourth node N4 are low-level signals, and the signal of the second node N2 is a high-level signal. The low-level signal of the second clock signal terminal CK2 is written to the first signal output terminal OUT1, and the output signal of the first signal output terminal OUT1 is a low-level signal. The signal of the third clock signal terminal CK3 is written to the second signal output terminal OUT2, and the output signal of the second signal output terminal OUT2 is a high-level signal.

In the third phase S3, the signals at the signal input terminal IN and the second clock signal terminal CK2 are high-level signals, while the signals at the first clock signal terminal CK1 and the third clock signal terminal CK3 are low-level signals. The signal at the first clock signal terminal CK1 is low-level, the first transistor T1 and the third transistor T3 are turned on, the high-level signal at the signal input terminal IN is written to the first node N1, and the low-level signal at the first reference signal terminal VGL1 is written to the second node N2. Because the tenth transistor T10 is continuously turned on, the signals at the third node N3 and the first node N1 are both high-level signals. The signal at the first node N1 is high-level, and the second transistor T2 and the eighth transistor T8 are turned off. The signal at the second node N2 is low-level, the fourth transistor T4, the sixth transistor T6, and the ninth transistor T9 are turned on, the high-level signal at the power supply signal terminal VGH is written to the first signal output terminal OUT1 and the fourth node N4, and the low-level signal at the second reference signal terminal VGL2 is written to the second signal output terminal OUT2. The signal at the third node N3 is high, the seventh transistor T7 and the twelfth transistor T12 are disconnected, and the signal at the first reference signal terminal VGL1 cannot be written to the first node N1. The signal at the first node N1 remains high, and the high-level signal at the second clock signal terminal CK2 cannot be written to the first signal output terminal OUT1. Because the signal at the second clock signal terminal CK2 is high, the fifth transistor T5 is disconnected. In this stage, the signal at the second node N2 is low, and the signals at the first node N1, the third node N3, and the fourth node N4 are high. The signal at the power supply signal terminal VGH is written to the first signal output terminal OUT1, and the output signal at the first signal output terminal OUT1 is high. The signal at the second reference signal terminal VGL2 is written to the second signal output terminal OUT2, and the output signal at the second signal output terminal OUT2 is low.

In the fourth phase S4, the signals at the signal input terminal IN, the first clock signal terminal CK1, and the third clock signal terminal CK3 are high-level signals, and the signal at the second clock signal terminal CK2 is low-level. The signal at the first clock signal terminal CK1 is high-level, the first transistor T1 and the third transistor T3 are turned off, and the signal at the first node N1 remains high-level. Because the tenth transistor T10 is continuously turned on, the signals at the third node N3 and the first node N1 are both high-level signals. The signal at the first node N1 is high-level, the second transistor T2 and the eighth transistor T8 are turned off, and the high-level signal at the third clock signal terminal CK3 cannot be written to the second output signal terminal OUT2. The signal at the second node N2 remains low-level, the fourth transistor T4, the sixth transistor T6, and the ninth transistor T9 are turned on, the high-level signal at the power supply signal terminal VGH is written to the first signal output terminal OUT1 and the fourth node N4, and the low-level signal at the second reference signal terminal VGL2 is written to the second signal output terminal OUT2. The signal at the third node N3 is high, the seventh transistor T7 and the twelfth transistor T12 are disconnected, and the signal at the first reference signal terminal VGL1 cannot be written to the first node N1. The signal at the first node N1 remains high, and the high-level signal at the second clock signal terminal CK2 cannot be written to the first signal output terminal OUT1. Because the signal at the second clock signal terminal CK2 is high, the fifth transistor T5 is disconnected. In this stage, the signal at the second node N2 is low, and the signals at the first node N1, the third node N3, and the fourth node N4 are high. The signal at the power supply signal terminal VGH is written to the first signal output terminal OUT1, and the output signal at the first signal output terminal OUT1 is high. The signal at the second reference signal terminal VGL2 is written to the second signal output terminal OUT2, and the output signal at the second signal output terminal OUT2 is low.

The working process of the shift register unit includes: a plurality of third stages S3 and fourth stages S4, and the third stages S3 and the fourth stages S4 work alternately.

In the above process, when the first clock signal terminal CK1 is at a low level (for example, in the first phase S1 and the third phase S3), the low level of the first reference signal terminal VGL1 is written to the second node N2, causing the voltage of the second node N2 to be lower than the voltage of the second reference signal terminal VGL2. In other words, the voltage of the control electrode of the ninth transistor T9 is lower than the voltage of the first electrode. This enables the ninth transistor T9 to be fully turned on, thereby generating a stable output signal at the second output signal terminal OUT2. In this way, the problem of the ninth transistor T9 being unable to turn on due to insufficient voltage compensation at the second node N2 is avoided, and the voltage of the second signal output terminal OUT2 is stabilized.

In an exemplary embodiment, referring to FIG. 3 , a low level signal of the first clock signal line CK1 may be equal to a level signal of the first reference signal terminal VGL1 .

FIG5 is one of the equivalent circuit diagrams of the shift register unit provided in an embodiment of the present disclosure.

Similar to the shift register unit of FIG2 , the shift register unit of FIG5 may also include a node control subcircuit 100, an output subcircuit 200, and a pull-down subcircuit 300. The above description of the control subcircuit, output subcircuit, and pull-down subcircuit also applies to this embodiment. Unlike the shift register unit of FIG2 , the shift register unit of FIG5 further includes a voltage stabilization subcircuit 400. For ease of description, the following will mainly describe the differences in detail.

As shown in FIG5 , the voltage stabilization sub-circuit 400 is connected to a first node N1, a second node N2, and a first reference signal terminal VGL1. Under control of the first node N1, the voltage stabilization sub-circuit 400 can provide a signal from the first reference signal terminal VGL1 to the second node N2. In an exemplary embodiment, the voltage stabilization sub-circuit 400 may include a thirteenth transistor T13. A control electrode of the thirteenth transistor T13 is connected to the first node N1, a first electrode of the thirteenth transistor T13 is connected to the first reference signal terminal VGL1, and a second electrode of the thirteenth transistor T13 is connected to the second node N2.

By designing a voltage-stabilizing subcircuit, insufficient compensation voltage at the second node can be avoided. For example, when the first node N1 is at a high level (e.g., during the third stage S3 and the fourth stage S4), the thirteenth transistor T13 is turned on, thereby providing the low level of the first reference signal terminal VGL1 to the second node N2, so that the second node N2 remains at the low level of the first reference signal terminal VGL1 (i.e., the first reference level). In this way, the voltage at the second node is ensured to fully meet the voltage required for the normal operation of the output subcircuit, thereby ensuring the stability of the output signal in the output subcircuit, which is conducive to improving the display effect of the display device.

In an exemplary embodiment, the thirteenth transistor T13 is a metal oxide transistor.

In an exemplary embodiment, the thirteenth transistor T13 is an N-type metal oxide transistor. The effective level of the control electrode of the P-type transistor is a low level, such as a negative voltage. Then, when the first electrode and the control electrode of the P-type transistor receive a negative voltage, the voltage of the control electrode will affect the signal output of the second electrode, resulting in a threshold voltage loss. In contrast, the effective level of the control electrode of the N-type transistor is a high level, such as a positive voltage. Then, when the first electrode of the N-type transistor receives a negative voltage, no threshold voltage loss will occur, that is, the output signal of the second electrode is not affected by the control electrode. The embodiment of the present disclosure sets the thirteenth transistor T13 of N type so that when the first node N1 is at a high level (for example, in the third stage S3 and the fourth stage S4), the thirteenth transistor T13 is turned on. Since the thirteenth transistor T13 is an N-type transistor, it can provide the low level of the first reference signal terminal VGL1 to the second node N2 without generating a threshold voltage loss, thereby maintaining the second node N2 at the low level of the first reference signal terminal VGL1 (i.e., the first reference level). This is further conducive to the stability of the voltage of the second node N2. At a desired low level, for example, around -12V, leakage problems caused by compensation voltage loss at the second node N2 are avoided.

By designing the thirteenth transistor T13 as an N-type metal oxide transistor, the metal oxide transistor has lower leakage current and higher anti-electromagnetic interference capability, which is beneficial to improving the stability of the voltage stabilization sub-circuit, thereby ensuring the stability of the voltage at the second node N2, ensuring the normal operation of the output sub-circuit, and reducing the probability of leakage current at the output signal end.

In the example of FIG5 , the first electrode of the third transistor T3 is connected to the first reference signal terminal VGL1. However, the embodiments of the present disclosure are not limited thereto. As an alternative embodiment, when the voltage stabilization sub-circuit 400 is provided, the first electrode of the third transistor T3 can be connected to the second reference signal terminal VGL2 instead of the first reference signal terminal VGL1. This is because the addition of the voltage stabilization sub-circuit 400 itself can stabilize the potential of the second node N2. Even if the first electrode of the third transistor T3 is connected to the second reference signal terminal VGL2, which has a higher voltage, the second node N2 can still be stabilized within an acceptable low voltage range.

In an exemplary embodiment, the low level of at least one of the first clock signal terminal CK1 and the second clock signal terminal CK2 is equal to the signal level of the first reference signal terminal VGL1, and the low level of the third clock signal terminal CK3 is equal to the signal level of the second reference signal terminal VGL2. Alternatively, if the voltage stabilization sub-circuit 400 is provided, the low level of at least one of the first clock signal terminal CK1, the second clock signal terminal CK2, and the third clock signal terminal CK3 can be equal to the signal level of the second reference signal terminal VGL2. For example, the low levels of the signals from the first clock signal terminal CK1 to the third clock signal terminal CK3 can be equal to the signal level of the second reference signal terminal VGL2, i.e., the second reference level. This is because the addition of the voltage stabilization sub-circuit 400 itself stabilizes the potential of the second node N2. Even if the low level of the signals from the first clock signal terminal CK1 and/or the second clock signal terminal CK2 is equal to the higher second reference level, the voltage of the second node N2 can be stabilized within an acceptable low voltage range.

As shown in Figure 5, the output sub-circuit 300 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first capacitor C1, and a second capacitor C2. The sixth transistor T6 and the ninth transistor T9 share the first capacitor C1, and the seventh transistor T7 and the eighth transistor T8 share the second capacitor C2. This design can reduce the number of capacitors in the shift register unit, which helps optimize the layout space of the shift register unit, saves the area occupied by wiring, and facilitates the narrowing of the frame of the display device.

FIG6 is a signal timing simulation diagram of the shift register provided in FIG5. FIG6 is a signal timing simulation diagram of the shift register provided in FIG5. The following description is given assuming that all transistors are P-type transistors.

5 and 6 , the operation process of the control shift register unit provided in FIG5 includes the following stages:

In the first phase S1, i.e., the input phase, the signals at the signal input terminal IN, the first clock signal terminal CK1, and the third clock signal terminal CK3 are low-level signals, and the signal at the second clock signal terminal CK2 is high-level. The signal at the first clock signal terminal CK1 is low-level, the first transistor T1 and the third transistor T3 are conductive, the low-level signal at the signal input terminal IN is written to the first node N1, and the low-level signal at the first reference signal terminal VGL1 is written to the second node N2. Because the tenth transistor T10 is continuously conductive, the signals at the third node N3 and the first node N1 are both low-level signals. The signal at the first node N1 is low-level, and the eleventh transistor T11 is continuously conductive. Therefore, the second transistor T2 and the eighth transistor T8 are conductive, the low-level signal at the first clock signal terminal CK1 is written to the second node N2, ensuring that the signal at the second node N2 remains low-level. The low-level signal at the third clock signal terminal CK3 is written to the second signal output terminal OUT2. The signal at the second node N2 is low, turning on the sixth transistor T6 and the ninth transistor T9. The high-level signal at the power supply signal terminal VGH is written to the first signal output terminal OUT1, and the low-level signal at the second reference signal terminal VGL2 is written to the second signal output terminal OUT2. The signal at the third node N3 is low, turning on the seventh transistor T7, thereby providing the high-level signal at the second clock signal terminal CK2 to the first output signal terminal. The low level at the third node N3 also turns on the twelfth transistor T12, writing the signal at the first reference signal terminal VGL1 to the first node N1, further lowering the level of the signal at the first node N1 and causing the signal at the first node N1 to remain low. Because the signal at the second clock signal terminal CK2 is high, the fifth transistor T5 is turned off. Even though the low level at the second node N2 turns on the fourth transistor T4, the high-level signal at the power supply signal terminal VGH is not written to the first node N1, and the signal at the first node N1 is not pulled high. Since the signal at the first node N1 is a low-level signal, the thirteenth transistor T13 is turned off, and the signal at the first reference signal terminal VGL1 is not written into the second node N2. In this stage, the signals at the first node N1, the second node N2, and the third node N3 are low-level signals, the signal at the fourth node N4 is a high-level signal, the signal at the power supply signal terminal VGH is written into the first signal output terminal OUT1, and the output signal of the first signal output terminal OUT1 is a high-level signal. The signal at the third clock signal terminal CK3 and the signal at the second reference signal terminal VGL2 are written into the second signal output terminal OUT2, and the output signal at the second signal output terminal OUT2 is a low-level signal.

In the second phase S2, i.e. the output phase, the signal input terminal IN, the first clock signal terminal CK1 and the third clock signal terminal CK2 are connected. The signal at the clock signal terminal CK3 is a high-level signal, and the signal at the second clock signal terminal CK2 is a low-level signal. The signal at the first clock signal terminal CK1 is a high-level signal, the first transistor T1 and the third transistor T3 are disconnected, and the signal at the first node N1 remains a low-level signal. Because the tenth transistor T10 is continuously turned on, the signals at the third node N3 and the first node N1 are both low-level signals. The signal at the first node N1 is a low-level signal, the eleventh transistor T11 is continuously turned on, the second transistor T2 and the eighth transistor T8 are turned on, the high-level signal at the first clock signal terminal CK1 is written to the second node N2, the signal at the second node N2 is a high-level signal, the high-level signal at the third clock signal terminal CK3 is written to the second signal output terminal OUT2, the signal at the second node N2 is a high-level signal, the fourth transistor T4, the sixth transistor T6, and the ninth transistor T9 are disconnected, the high-level signal at the power supply signal terminal VGH cannot be written to the first signal output terminal OUT1, and the low-level signal at the second reference signal terminal VGL2 cannot be written to the second signal output terminal OUT2. The signal at the third node N3 is low, the seventh transistor T7 and the twelfth transistor T12 are turned on, and the signal at the first reference signal terminal VGL1 is written to the first node N1, maintaining the signal at the first node N1 at a low level. The low-level signal at the second clock signal terminal CK2 is written to the first signal output terminal OUT1. Because the signal at the second clock signal terminal CK2 is low, the fifth transistor T5 is turned on, and the signal at the fourth node N4 is pulled low by the signal at the first node N1, resulting in a low-level signal. Because the signal at the first node N1 is low, the thirteenth transistor T13 is turned off, and the signal at the first reference signal terminal VGL1 is not written to the second node N2. In this stage, the signals at the first node N1, the third node N3, and the fourth node N4 are low-level signals, and the signal at the second node N2 is high-level. The low-level signal at the second clock signal terminal CK2 is written to the first signal output terminal OUT1, and the output signal of the first signal output terminal OUT1 is a low-level signal. The signal at the third clock signal terminal CK3 is written to the second signal output terminal OUT2, and the output signal of the second signal output terminal OUT2 is a high-level signal.

In the third stage S3, the signals at the signal input terminal IN and the second clock signal terminal CK2 are high-level signals, and the signals at the first clock signal terminal CK1 and the third clock signal terminal CK3 are low-level signals. The signal at the first clock signal terminal CK1 is a low-level signal, the first transistor T1 and the third transistor T3 are turned on, the high-level signal at the signal input terminal IN is written into the first node N1, and the low-level signal at the first reference signal terminal VGL1 is written into the second node N2. Since the tenth transistor T10 is continuously turned on, the signal at the third node N3 and the signal at the first node N1 are both high-level signals. The signal at the first node N1 is a high-level signal, and the second transistor T2 and the eighth transistor T8 are turned off. The signal at the second node N2 is a low-level signal, the fourth transistor T4, the sixth transistor T6 and the ninth transistor T9 are turned on, and the high-level signal at the power supply signal terminal VGH is written into the first signal output terminal OUT1 and the third transistor T8. At the fourth node N4, the low-level signal at the second reference signal terminal VGL2 is written to the second signal output terminal OUT2. The signal at the third node N3 is a high-level signal, and the seventh transistor T7 and the twelfth transistor T12 are disconnected. The signal at the first reference signal terminal VGL1 cannot be written to the first node N1, maintaining the signal at the first node N1 at a high level. The high-level signal at the second clock signal terminal CK2 cannot be written to the first signal output terminal OUT1. Because the signal at the second clock signal terminal CK2 is a high-level signal, the fifth transistor T5 is disconnected. Because the signal at the first node N1 is a high-level signal, the thirteenth transistor T13 is turned on, allowing the signal at the first reference signal terminal VGL1 to be written to the second node N2. This ensures that the voltage at the second node N2 is sufficiently low during the third stage S3, thereby facilitating the normal operation of the transistors in the output signal terminal, for example, ensuring the normal operation of the ninth transistor, and improving leakage at the second signal output terminal OUT2. In this stage, the signal of the second node N2 is a low-level signal, the signals of the first node N1, the third node N3 and the fourth node N4 are high-level signals, the signal of the power supply signal terminal VGH is written to the first signal output terminal OUT1, and the output signal of the first signal output terminal OUT1 is a high-level signal. The signal of the second reference signal terminal VGL2 is written to the second signal output terminal OUT2, and the output signal of the second signal output terminal OUT2 is a low-level signal.

In the fourth phase S4, the signals at the signal input terminal IN, the first clock signal terminal CK1, and the third clock signal terminal CK3 are high-level signals, and the signal at the second clock signal terminal CK2 is low-level. The signal at the first clock signal terminal CK1 is high-level, the first transistor T1 and the third transistor T3 are turned off, and the signal at the first node N1 remains high-level. Because the tenth transistor T10 is continuously turned on, the signals at the third node N3 and the first node N1 are both high-level signals. The signal at the first node N1 is high-level, the second transistor T2 and the eighth transistor T8 are turned off, and the high-level signal at the third clock signal terminal CK3 cannot be written to the second output signal terminal OUT2. The signal at the second node N2 remains low-level, the fourth transistor T4, the sixth transistor T6, and the ninth transistor T9 are turned on, the high-level signal at the power supply signal terminal VGH is written to the first signal output terminal OUT1 and the fourth node N4, and the low-level signal at the second reference signal terminal VGL2 is written to the second signal output terminal OUT2. The signal at the third node N3 is a high-level signal, the seventh transistor T7 and the twelfth transistor T12 are turned off, the signal at the first reference signal terminal VGL1 cannot be written to the first node N1, the signal at the first node N1 is kept high-level, and the high-level signal at the second clock signal terminal CK2 cannot be written to the first signal output terminal OUT1. Since the signal at the second clock signal terminal CK2 is a high-level signal, the fifth transistor T5 is turned off. Since the signal at the first node N1 is a high-level signal, the thirteenth transistor T13 is turned on, and the signal at the first reference signal terminal VGL1 can be written to the second node N2, ensuring that the voltage at the second node N2 is kept high during the third stage S3. The voltage is low enough to facilitate the normal operation of the transistors in the output signal terminal, for example, to ensure the normal operation of the ninth transistor, and to improve the leakage of the second signal output terminal OUT2. In this stage, the signal of the second node N2 is a low-level signal, the signals of the first node N1, the third node N3, and the fourth node N4 are high-level signals, the signal of the power supply signal terminal VGH is written to the first signal output terminal OUT1, and the output signal of the first signal output terminal OUT1 is a high-level signal. The signal of the second reference signal terminal VGL2 is written to the second signal output terminal OUT2, and the output signal of the second signal output terminal OUT2 is a low-level signal.

The working process of the shift register unit includes: a plurality of third stages S3 and fourth stages S4, and the third stages S3 and the fourth stages S4 work alternately.

During the third and fourth phases S3 and S4, the thirteenth transistor T13 in the voltage stabilization sub-circuit is turned on. Because the thirteenth transistor is an N-type metal oxide transistor (NMOT) with low leakage, it can eliminate the loss of compensation voltage at the second node N2, thereby ensuring that the potential of the second node N2 is sufficiently low during the third and fourth phases S3 and S4. For example, referring to the dashed area A in FIG6 , the low-level signal at the second node N2 during the third and fourth phases S3 and S4 can be substantially equal to the low-level signal at the second node N2 during the first phase S1.

In an exemplary embodiment, the low level of the signal of at least one of the first clock signal terminal CK1, the second clock signal terminal CK2, and the third clock signal terminal CK3 may be equal to the signal level of the second reference signal terminal VGL2. For example, referring to FIG. 6 , the low level of the signal of the first clock signal terminal CK1 may be equal to the signal level of the second reference signal terminal VGL2.

The embodiment of the present disclosure further provides a driving method of a shift register unit, which is configured to drive the shift register unit. The driving method of the shift register unit may include the following steps:

Step 100: The node control subcircuit provides a signal from the signal input terminal to the first node under the signal control of the first clock signal terminal, and provides a signal from the first reference signal terminal or the first clock signal terminal to the second node under the signal control of the first node and the first clock signal terminal.

Step 200: The pull-down sub-circuit provides a signal of the third power terminal to the first node.

Step 300: Under the control of the signals of the first node and the second node, the output subcircuit provides the signal of the power signal terminal or the second clock signal terminal to the first signal output terminal, and provides the signal of the second reference signal terminal or the third clock signal terminal to the second signal output terminal.

The shift register unit is the shift register unit provided by any of the aforementioned embodiments, and its implementation principle and implementation effect are similar, which will not be described in detail here.

In an exemplary embodiment, the shift register unit may further include an output control subcircuit; and the driving method of the shift register unit may further include the output control subcircuit storing a voltage difference between a signal at the first signal output terminal and a signal at the first power supply terminal.

The present disclosure also provides a display device. FIG7 is a schematic diagram of the structure of a display device. As shown in FIG7, the display device may include a display substrate. In some embodiments, the display device may also include a timing controller, a data signal driver, and a light signal driver.

The display substrate may include: a substrate, and a plurality of sub-pixels Pxij, a plurality of gate lines (S1 to Sm), and a gate driving circuit disposed on the substrate, wherein i and j may be natural numbers, and at least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The substrate is provided with a display area and a non-display area, the gate driving circuit is located in the non-display area, the sub-pixels Pxij and the plurality of gate lines (S1 to Sm) are located in the display area, and the plurality of gate lines (S1 to Sm) are electrically connected to the plurality of sub-pixels Pxij and the gate driving circuit, respectively.

The timing controller is respectively connected to the data signal driver, the gate drive circuit, and the light-emitting signal driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the gate drive circuit is respectively connected to a plurality of gate lines (S1 to Sm), and the light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a circuit unit and a pixel drive circuit, and the pixel drive circuit may be respectively connected to the gate lines, the light-emitting signal lines, and the data signal lines. In an exemplary embodiment, the timing controller may provide grayscale values and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the gate drive circuit to the gate drive circuit, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting signal driver to the light-emitting signal driver. The data signal driver may use the grayscale values and control signals received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., and Dn. For example, the data signal driver can sample the grayscale value using a clock signal, and apply the data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, where n can be a natural number. The gate drive circuit can generate a scan signal to be provided to the gate lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the gate drive circuit can sequentially provide a scan signal with a conduction level pulse to the gate lines S1 to Sm. For example, the gate drive circuit can be constructed in the form of a shift register unit, and can generate a scan signal by sequentially transmitting the scan start signal provided in the form of a conduction level pulse to the next level circuit under the control of a clock signal, where m can be a natural number. The luminous signal driver can generate a scan signal to be provided to the gate lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from a timing controller. The emission signal driver may generate an emission signal to be provided to the light emitting signal lines E1, E2, E3, ..., and Eo by using an emission stop signal, etc. For example, the light emitting signal driver may sequentially provide an emission signal having an off-level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting signal driver may be configured in the form of a shift register unit and may generate an emission signal in a manner such that the emission stop signal provided in the form of an off-level pulse is sequentially transmitted to the next stage circuit under the control of a clock signal. o may be a natural number.

In an exemplary embodiment, the display device may be a liquid crystal display (LCD) or an organic light emitting diode (OLED) display device. The display device may be any product or component with a display function, such as an LCD panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system.

FIG8 is a schematic diagram of a cascade connection of a gate driving circuit according to an exemplary embodiment of the present disclosure.

In an exemplary embodiment, as shown in FIG8 , the gate drive circuit includes: a plurality of cascaded shift register units GOA, numbered sequentially as GOA(1), GOA(2), ..., GOA(N), where N is the total number of shift register units. A first signal output terminal of the nth stage shift register unit is connected to a signal input terminal of the n+ith stage shift register unit, where 1≤n＜N, and i is an integer greater than or equal to 1.

In an exemplary embodiment, the first signal output terminal OUT1 of the shift register unit is electrically connected to the gate line.

Figure 9 is a partial planar schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure; Figure 10 is a partial planar schematic diagram of the first semiconductor layer in the display substrate according to Figure 9; Figure 11 is a partial planar schematic diagram of the first conductive layer in the display substrate according to Figure 9; Figure 12 is a partial planar schematic diagram of the second conductive layer in the display substrate according to Figure 9; Figure 13 is a partial planar schematic diagram of the third conductive layer in the display substrate according to Figure 9; Figure 14 is a partial planar schematic diagram of the fourth conductive layer in the display substrate according to Figure 9; Figure 15 is a partial planar schematic diagram of a combined film layer of the first semiconductor layer and the first conductive layer in the display substrate according to Figure 9; Figure 16 is a partial planar schematic diagram of a combined film layer of the first semiconductor layer, the first conductive layer, the second conductive layer and the third conductive layer in the display substrate according to Figure 9.

In an exemplary embodiment, FIG9 is an example of the shift register unit provided in FIG2. In conjunction with FIG9, the display substrate may further include, in addition to the shift register unit, a first clock signal line ck1 and a second clock signal line ck2 provided on the substrate and located in the non-display area and extending along the first direction Y. ck2, a power signal line vgh, a first reference signal line vgl1, a second reference signal line vgl2, a third reference signal line vgl3, a third clock signal line ck3 and a fourth reference signal line vgl4.

The first clock signal line ck1, the second clock signal line ck2, the power signal line vgh, the first reference signal line vgl1, the second reference signal line vgl2, the third reference signal line vgl3, the third clock signal line ck3 and the fourth reference signal line vgl4 are arranged in sequence along the second direction X toward the display area, and the first direction Y intersects the second direction X.

The first reference signal line vgl1 and the third reference signal line vgl3 are connected to the first reference signal terminal VGL1 of the shift register unit. The second reference signal line vgl2 and the fourth reference signal line vgl4 are connected to the second reference signal terminal VGL2 of the shift register unit. The power signal line vgh is connected to the power signal terminal VGH of the shift register unit. The first clock signal line ck1 is connected to the first clock signal terminal CK1 of the shift register unit, the second clock signal line ck2 is connected to the second clock signal terminal CK2 of the shift register unit, and the third clock signal line ck3 is connected to the third clock signal terminal CK3 of the shift register unit.

In an exemplary embodiment, the display substrate may further include an initial signal line stv and a fourth clock signal line ck4 extending in the first direction Y. The initial signal line stv is located on a side of the first clock signal line ck1 away from the display area along the second direction X, and the fourth clock signal line ck4 is located between the third clock signal line ck3 and the fourth reference signal line vgl4.

In an exemplary embodiment, in combination with Figures 2 and 9, the first transistor T1, the second transistor T2, and the third transistor T3 of the shift register unit can be located between the power signal line vgh and the second reference signal line vgl2, the second transistor T2 and the third transistor T3 can be located between the first reference signal line vgl1 and the second reference signal line vgl2, and the first transistor T1 can be located between the power signal line vgh and the first reference signal line vgl1.

The fourth transistor T4 and the fifth transistor T5 can be located between the power signal line VGH and the first reference signal line vgl1. The sixth transistor T6 and the seventh transistor T7 can be located between the second reference signal line vgl2 and the third clock signal line CK3. The orthographic projection of the active layer ACT6 of the sixth transistor T6 on the substrate substrate can at least partially overlap with the orthographic projection of the third reference signal line vgl3 on the substrate substrate. The orthographic projection of the active layer ACT7 of the seventh transistor T7 on the substrate substrate can at least partially overlap with the orthographic projection of the third reference signal line vgl3 on the substrate substrate. The eighth transistor T8 and the ninth transistor T9 can be located on the side of the fourth reference signal line vgl4 close to the display area. The tenth transistor T10 and the twelfth transistor T12 can be located between the second reference signal line vgl2 and the fourth reference signal line vgl4. The first capacitor C1 can be located between the third reference signal line vgl3 and the third clock signal line CK3. The second capacitor C2 can be located between the fourth clock signal line CK4 and the ninth transistor T9 The orthographic projection of the second capacitor C2 on the substrate at least partially overlaps with the orthographic projection of the fourth reference signal line vgl4 on the substrate.

In an exemplary embodiment, with reference to Figures 10 to 16, the display substrate may include a first semiconductor layer (as shown in Figure 10), a first conductive layer (as shown in Figure 11), a second conductive layer (as shown in Figure 12), a third conductive layer (as shown in Figure 13) and a fourth conductive layer (as shown in Figure 14) stacked sequentially on a base 1.

Exemplarily, the transistor of the register unit includes an active layer, a control electrode, a first electrode and a second electrode. For example, the active layer of at least one of the first to twelfth transistors T1 to T12 of the shift register unit described above is located in the first semiconductor layer.

As shown in FIG10 , the first to twelfth transistors T1 to T12 respectively include active layers ACT1 to ACT12 . At least one of the active layers ACT1 to ACT12 is located in the first semiconductor layer, and for example, all of the active layers ACT1 to ACT12 may be located in the first semiconductor layer. In an exemplary embodiment, the first semiconductor layer may be a low-temperature polycrystalline silicon semiconductor layer.

In the example of FIG10 , active layers ACT1, ACT2, ACT3, ACT10, and ACT12 are formed as independent active material layers. Active layers ACT4 and ACT5 can be formed as an integrated active material layer (also referred to as the first active material layer) and arranged along the first direction. Similarly, active layers ACT6 and ACT7 are formed as an integrated active material layer (also referred to as the second active material layer) and arranged along the first direction; active layers ACT8 and ACT9 are formed as an integrated active material layer (also referred to as the third active material layer) and arranged along the first direction. As shown in FIG10 , the third active material layer including active layers ACT8 and ACT9 is located on the side close to the display area, and the second active material layer including the sixth active layers ACT6 and ACT7 is located on the side of the third active material layer away from the display area. Active layer ACT12 is located on one side of the second active material layer along the first direction. Active layer ACT10 is located on one side of active layer ACT2 along the first direction. The active layer ACT3 is located on one side of the active layer ACT10 along the second direction, and the active layer ACT2 is designed in an L-shape. The active layers ACT4 and ACT5 are located on one side of the active layer ACT1 along the first direction.

Exemplarily, the control electrode of at least one of the first transistor T1 to the twelfth transistor T12 of the register unit and the first electrode plate of at least one of the first capacitor C1 to the second capacitor C2 may be located in the first conductive layer.

As shown in FIG11 , the first conductive layer includes a first conductive connection portion m1, a second conductive connection portion m2, a fourth conductive connection portion m4, a fifth conductive connection portion m5, a seventh conductive connection portion m7, a ninth conductive connection portion m9, Fifteenth conductive connection portion m15, nineteenth conductive connection portion m19. In conjunction with Figure 15, the first conductive connection portion m1 includes the control electrode G1 of the first transistor T1 and the control electrode G3 of the third transistor T3, wherein the portion of the first conductive connection portion m1 overlapping with the active layer ACT1 serves as the control electrode G1 of the first transistor T1, and the portion of the first conductive connection portion m1 overlapping with the active layer ACT3 serves as the control electrode G2 of the third transistor T3. In a similar manner, the portion of the second conductive connection portion m2 overlapping with the active layer ACT2 serves as the control electrode G2 of the second transistor T2. The fourth conductive connection portion m4 includes the control electrode G4 of the fourth transistor T4, the control electrode G6 of the sixth transistor T6, and the control electrode G9 of the ninth transistor T9, wherein the portions of the fourth conductive connection portion m4 overlapping with the active layers ACT4, ACT6, and ACT9 serve as the control electrode G4 of the fourth transistor T4, the control electrode G6 of the sixth transistor T6, and the control electrode G9 of the ninth transistor T9, respectively. In conjunction with Figure 12, the fourth conductive connection portion m4 also includes the first plate C2a of the second capacitor C2, wherein the portion where the fourth conductive connection portion m4 overlaps with the second plate C2b of the second capacitor C2 serves as the first plate C2a of the second capacitor C2. The portion where the fifth conductive connection portion m5 overlaps with the active layer ACT5 serves as the control electrode G5 of the fifth transistor. The portion where the seventh conductive connection portion m7 overlaps with the active layer ACT12 serves as the control electrode G12 of the twelfth transistor. In conjunction with Figure 12, the seventh conductive connection portion m7 also includes the first plate C1a of the first capacitor C1, wherein the portion where the seventh conductive connection portion m7 overlaps with the second plate C1b of the first capacitor C1 serves as the first plate C1a of the first capacitor.

The portion where the ninth conductive connection portion m9 overlaps the active layer ACT8 serves as the control electrode G8 of the eighth transistor. The control electrode G8 of the eighth transistor may include multiple conductive components arranged in parallel along the second direction. The nineteenth conductive connection portion m19 extends along the second direction and does not intersect with the orthographic projection of the active layer on the substrate.

For example, as shown in FIG12 , the second plate of at least one of the multiple first capacitors of the register unit may be located in the second conductive layer. As shown in FIG12 , the second conductive layer may include the second plate C1b of the first capacitor C1 and the second substrate C2b of the second capacitor C2b. The second conductive layer may further include a sixth conductive connection portion m6, a twelfth conductive connection portion m12, and a fourteenth conductive connection portion m14. The sixth conductive connection portion m6 is located on a side of the twelfth conductive connection portion m12 away from the display area. The fourteenth conductive connection portion m14 is located on a side of the twelfth conductive connection portion m12 closer to the display area. The second plate C1b of the first capacitor C1 is located between the sixth conductive connection portion m6 and the twelfth conductive connection portion m12, and the second substrate C2b of the second capacitor C2b is located on one side of the twelfth conductive connection portion m12 along the first direction. The sixth conductive connection portion m6 and the twelfth conductive connection portion m12 may extend along the first direction, and the fourteenth conductive connection portion m14 may extend along the second direction.

As shown in FIG13 , the third conductive layer may include an initial signal line stv, a power signal line vgh, a second reference signal line vgl2, a fourth reference signal line vgl4, a signal input line in, a first node N1, a first signal output terminal out1, a third conductive connection portion m3, a second node N2, an eighth conductive connection portion m8, a tenth conductive connection portion m10, an eleventh conductive connection portion m11, a thirteenth conductive connection portion m13, a sixteenth conductive connection portion m16, an eighteenth conductive connection portion m18, a twentieth conductive connection portion m20, and a twenty-first conductive connection portion m21. The initial signal line stv, the first clock signal first sub-line ck11, the second clock signal first sub-line ck21, the power signal line vgh, the second reference signal line vgl2, the third clock signal first sub-line ck31, the fourth clock signal first sub-line ck41, and the fourth reference signal line vgl4 all extend along the first direction. The initial signal line stv, the first clock signal first sub-line ck11, the second clock signal first sub-line ck21, the power signal line vgh, the second reference signal line vgl2, the third clock signal first sub-line ck31, the fourth clock signal first sub-line ck41, and the fourth reference signal line vgl4 are arranged in sequence along the second direction toward the display area. The signal input line in, the first node N1, the first signal output terminal out1, the third conductive connecting portion m3, and the second node N2 are all located between the power signal line vgh and the second reference signal line vgl2. The first node N1 is located on one side of the first signal output terminal out1 along the first direction, and the signal input line in is located on the side of the first node N1 away from the first signal output terminal out1 along the first direction. The second node N2 is located on the side of the first node closer to the display area along the second direction, and the third conductive transition portion m3 is located on one side of the second node N2 along the first direction. The eighth conductive connection portion m8, the tenth conductive connection portion m10, the sixteenth conductive connection portion m16, the eighteenth conductive connection portion m18, the twentieth conductive connection portion m20, and the twenty-first conductive connection portion m21 are all located between the second reference signal line vgl2 and the first sub-line of the third clock signal ck31. The sixteenth conductive connection portion m16 and the twenty-first conductive connection portion m21 extend along the second direction. The eighth conductive connection portion m8 and the twenty-first conductive connection portion m20 extend along the first direction. The eleventh conductive connection portion m11 and the thirteenth conductive connection portion m13 are located on a side of the fourth reference signal line vgl4 that is closer to the display area. The eleventh conductive connection portion m11 may have a U-shaped design. The thirteenth conductive connection portion m13 may include multiple conductive components arranged parallel to the second direction.

As shown in FIG14 , the fourth conductive layer may include a first reference signal line vgl1 and a third reference signal line vgl3. The first reference signal line vgl1 and the third reference signal line vgl3 both extend along a first direction. The first reference signal line vgl1 is located between the second clock signal second sub-line ck22 and the third clock signal second sub-line ck32. The third reference signal line vgl3 is located between the first reference signal line vgl1 and the third clock signal second sub-line ck32.

In the exemplary embodiment of FIG. 14 , the first reference signal line vgl1 and the third reference signal line vgl3 may be Both are located in the fourth conductive layer 6. However, the embodiments of the present disclosure are not limited thereto. The first reference signal line vgl1 can be located in either the third conductive layer or the fourth conductive layer, and the third reference signal line vgl3 can also be located in either the third conductive layer or the fourth conductive layer. In other words, the first reference signal line vgl1 and the third reference signal line vgl3 can be located in the same layer or in different layers. The first reference signal line vgl1 and the third reference signal line vgl3 are both electrically connected to the first reference signal terminal VGL1 of the shift register unit.

In an exemplary embodiment, at least one of the first clock signal line ck1, the second clock signal line ck2, the third clock signal line ck3, and the fourth clock signal line ck4 includes a first sublayer located in the third conductive layer and a second sublayer located in the fourth conductive layer. As shown in Figures 9, 13, and 14, the first clock signal line ck1 may include a first clock signal first subline ck11 located in the third conductive layer and a first clock signal first subline ck12 located in the fourth conductive layer. The orthographic projections of the first clock signal first subline ck11 and the first clock signal second subline ck12 on the substrate substrate at least partially overlap. In some embodiments, the orthographic projections of the first clock signal first subline ck11 and the first clock signal second subline ck12 on the substrate substrate may completely overlap. Similarly, the second clock signal line ck2 may include a second clock signal first subline ck21 located in the third conductive layer and a second clock signal second subline ck22 located in the fourth conductive layer. The orthographic projections of the second clock signal first subline ck21 and the second clock signal second subline ck22 on the substrate substrate at least partially overlap. The third clock signal line ck3 may include a third clock signal first sub-line ck31 located in the third conductive layer and a third clock signal second sub-line ck32 located in the fourth conductive layer. The orthographic projections of the third clock signal first sub-line ck31 and the third clock signal second sub-line ck32 on the substrate at least partially overlap. The fourth clock signal line ck4 may include a fourth clock signal first sub-line ck41 located in the third conductive layer and a fourth clock signal second sub-line ck42 located in the fourth conductive layer. The orthographic projections of the fourth clock signal first sub-line ck41 and the fourth clock signal second sub-line ck42 on the substrate at least partially overlap.

At least one of the first clock signal line ck1, the second clock signal line ck2, the third clock signal line ck3 and the fourth clock signal line ck4 adopts a double-layer routing design, which can improve the signal transmission stability in the clock signal line, such as reducing voltage drop and improving anti-interference ability, thereby improving timing stability, which is beneficial to improving the display effect of the display substrate.

In the above embodiment, the first clock signal line ck1, the second clock signal line ck2, the third clock signal line ck3 and the fourth clock signal line ck4 adopt a double-layer routing design. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, the first clock signal line ck1, the second clock signal line ck2, the third clock signal line ck3 and the fourth clock signal line ck4 adopt a double-layer routing design. Any one or more of the clock signal line ck1 and the fourth clock signal line ck4 may also adopt a single-layer routing design, for example, be arranged in the third conductive layer or the fourth conductive layer.

The connection relationship between the layers is described below with reference to FIG. 9 to FIG. 16 .

The first conductive connection portion m1 is connected to the first clock signal line ck1, thereby connecting the control electrode G1 of the first transistor T1 to the first clock signal line ck1. The signal input line in can be the first electrode D1 of the first transistor T1, and the signal input line in is connected to the signal input terminal IN. The first node N1 can include the second electrode S1 of the first transistor T1.

The second conductive connection portion m2 is connected to the first node N1, thereby connecting the control electrode G2 of the second transistor T2 to the first node N1. The third conductive connection portion m3 may include the first electrode D2 of the second transistor T2. The third conductive connection portion m3 is connected to the first clock signal line ck1 through the first conductive connection portion m1, thereby connecting the first electrode D2 of the second transistor T2 to the first clock signal line ck1. The second electrode S2 of the second transistor T2 is connected to the second node N2.

The first conductive connection portion m1 may further include a control electrode G3 of a third transistor T3. The first conductive connection portion m1 is connected to the first clock signal line ck1, thereby connecting the control electrode G3 of the third transistor T3 to the first clock signal line ck1. A first electrode D3 of the third transistor T3 is connected to the first reference signal line vgl1, and a second electrode S3 of the third transistor T3 is connected to the second node N2.

The fourth conductive connection portion m4 may include a control electrode G4 of the fourth transistor T4. The fourth conductive connection portion m4 is connected to the second node N2, thereby connecting the control electrode G4 of the fourth transistor T4 to the second node N2. A first electrode D4 of the fourth transistor T4 is connected to the power signal line vgh, and a second electrode S4 of the fourth transistor T4 is connected to the fourth node N4. The active layer ACT4 of the fourth transistor T4 and the active layer ACT5 of the fifth transistor T5 share the fourth node N4. The fifth conductive connection portion m5 may include a control electrode G5 of the fifth transistor T5. The fifth conductive connection portion m5 is connected to the second clock signal line ck2, thereby connecting the control electrode G5 of the fifth transistor T5 to the second clock signal line ck2. The first electrode D5 of the fifth transistor is connected to the fourth node N4, and the second electrode S5 of the fifth transistor T5 is connected to the first node N1.

The fourth conductive connection portion m4 may include the control electrode G6 of the sixth transistor T6, and the fourth conductive connection portion m4 is connected to the second node N2, thereby realizing the connection between the control electrode G6 of the sixth transistor T6 and the second node N2. The twenty-first conductive connection portion m21 may include the first electrode D6 of the sixth transistor T6, and the twenty-first conductive connection portion m21 is connected to the power signal line vgh through the sixth conductive connection portion m6, thereby realizing the connection between the sixth transistor T6 and the power signal line vgh. The first electrode D6 of the sixth transistor T6 is connected to the power signal line vgh. The second electrode S6 of the sixth transistor T6 is connected to the first electrode D7 of the seventh transistor T7.

For example, the eighteenth conductive connection portion m18 may include both the second electrode S6 of the sixth transistor T6 and the first electrode D7 of the seventh transistor T7. The eighteenth conductive connection portion m18 may also be connected to the first output signal line out1 via the nineteenth conductive connection portion m19, thereby connecting the second electrode S6 of the sixth transistor T6 and the first electrode D7 of the seventh transistor T7 to the first output signal line out1. The first signal output line out1 may be connected to the first signal output terminal OUT1.

The seventh conductive connection portion m7 may include the control electrode G7 of the seventh transistor T7 and may be connected to the second electrode S10 of the tenth transistor T10 via the eighth conductive connection portion m8. The sixteenth conductive connection portion m16 may include the second electrode S7 of the seventh transistor T7 and may be connected to the second clock signal line ck2 via the fifth conductive connection portion m5, thereby achieving a connection between the second electrode S7 of the seventh transistor T7 and the second clock signal line ck2.

The ninth conductive connection portion m9 may include the control electrode G8 of the eighth transistor T8. The ninth conductive connection portion m9 is connected to the first node N1 via the tenth conductive connection portion m10 and the second conductive connection portion m2, thereby connecting the control electrode G8 of the eighth transistor T8 to the first node N1. The eleventh conductive connection portion m11 may include the first electrode D8 of the eighth transistor T8. The eleventh conductive connection portion m11 is connected to the third clock signal line ck3 via the twelfth conductive connection portion m12, thereby connecting the first electrode D8 of the eighth transistor T8 to the third clock signal line ck3. The thirteenth conductive connection portion m13 may include both the second electrode S8 of the eighth transistor T8 and the first electrode D9 of the ninth transistor T9. The thirteenth conductive connection portion m13 is connected to the second signal output terminal OUT2 via the fourteenth conductive connection portion m14. The thirteenth conductive connection portion m13 is located in the third conductive layer, and the fourteenth conductive connection portion m14 is located in the second conductive layer.

The fourth conductive connection portion m4 may include a control electrode G9 of the ninth transistor T9, and the fourth conductive connection portion m4 is connected to the second node N2, thereby achieving a connection between the control electrode G9 of the ninth transistor T9 and the second node N2. The second electrode S9 of the ninth transistor T9 is connected to the fourth reference signal line vgl4.

The fifteenth conductive connection portion m15 may include the control electrode G10 of the tenth transistor T10. The fifteenth conductive connection portion m15 is connected to the second reference signal line vgl2, thereby achieving the connection between the control electrode G10 of the tenth transistor T10 and the second reference signal line vgl2. The tenth conductive connection portion m10 may include the first electrode D10 of the tenth transistor T10. The tenth conductive connection portion m10 is connected to the control electrode G10 of the eighth transistor T8 through the ninth conductive connection portion m9. The eighth conductive connection portion m8 may include the second electrode S10 of the tenth transistor T10, and the eighth conductive connection portion m8 is connected to the control electrode G7 of the seventh transistor T7 through the seventh conductive connection portion m7, thereby connecting the second electrode S10 of the tenth transistor T10 to the control electrode G7 of the seventh transistor T7.

The seventh conductive connection portion m7 may include a control electrode G12 of the twelfth transistor T12. The first electrode D12 of the twelfth transistor T12 is connected to the first node N1 via the second conductive connection portion m2. The twentieth conductive connection portion m20 may include a second electrode S12 of the twelfth transistor T12. The twentieth conductive connection portion m20 is electrically connected to the third reference signal line vgl3, thereby connecting the second electrode S12 of the twelfth transistor T12 to the third reference signal line vgl3.

A control electrode of the eleventh transistor T11 (not shown) may be connected to the second reference signal line vgl2 , a first electrode of the eleventh transistor T11 may be connected to the first node N1 , and a second electrode of the eleventh transistor may be connected to the control electrode of the eighth transistor T8 .

The first capacitor C1 includes a first plate C1a and a second plate C1b. The first plate C1a is located in the first conductive layer, and the second plate C1b is located in the second conductive layer.

The second capacitor C2 includes a first plate C2a and a second plate C2b. The first plate C2a of the second capacitor C2 is located in the first conductive layer, and the second plate C2b of the second capacitor is located in the second conductive layer.

FIG. 17 is a structural diagram of a sub-pixel in a display area of a display substrate according to an exemplary embodiment of the present disclosure.

As shown in FIG17 , at least one of the multiple sub-pixels includes a driving thin-film transistor and a storage capacitor. The driving thin-film transistor includes an active layer P-Si located on the base substrate 110, a gate G located on the side of the active layer P-Si away from the base substrate 110, a first gate insulating layer 202 located between the active layer P-Si and the gate G, a second gate insulating layer 203 located on the side of the gate G away from the base substrate 110, an interlayer dielectric layer 204 located on the side of the second gate insulating layer 203 away from the base substrate, and a source S and a drain D located on the side of the interlayer dielectric layer 204 away from the base substrate. The storage capacitor includes a first capacitor electrode ED1 and a second capacitor electrode ED2. The first capacitor electrode ED1 is located on the same layer as the gate G, and the second capacitor electrode ED2 is located between the second gate insulating layer 203 and the interlayer dielectric layer 204.

As shown in FIG17 , at least one of the plurality of sub-pixels further includes a first planar layer 206, a second planar layer 208, a switching electrode 210, an anode 207, and a pixel defining layer 209. The first planar layer 206 is located on a side of the interlayer dielectric layer 204 away from the substrate 110. The switching electrode 210 is located on the first planar layer 206. The first planar layer 206 is located on a side of the switching electrode 210 away from the base substrate 110 and is connected to the source electrode S of the thin film transistor through a via hole provided in the first planar layer 206. The second planar layer 208 is located on a side of the switching electrode 210 away from the base substrate 110. The anode 207 is located on a side of the second planar layer 208 away from the base substrate 110 and is connected to the switching electrode 210 through a via hole in the second planar layer 208. The pixel defining layer 209 is located on a side of the second planar layer 208 away from the base substrate and at least partially covers the anode 207.

In some embodiments, the sub-pixel may further include a buffer layer 201 , which is located between the base substrate 110 and the first gate insulating layer 202 , and the active layer P-Si of the driving thin film transistor is located between the buffer layer 201 and the first gate insulating layer 202 .

In some embodiments, the sub-pixel may further include a passivation layer 205 , which is located between the planar layer 206 and the interlayer dielectric layer 204 and covers the source S and drain D of the driving thin film transistor. The anode 207 passes through the interlayer dielectric layer 206 and the passivation layer 205 and is connected to the source S of the driving thin film transistor.

In some embodiments, the subpixel may further include a light emitting layer 211 and a cathode 212. The light emitting layer 211 is located on a side of the anode 210 away from the substrate 110 and partially covers the anode 210. The cathode 212 is located on a side of the light emitting layer 211 away from the substrate 110.

In some embodiments, the sub-pixel may further include an encapsulation layer 213. The encapsulation layer 213 is located on a side of the cathode 212 away from the base substrate 110. In some embodiments, the encapsulation layer 213 may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked in sequence.

In some embodiments, the layer where the active layer P-Si is located can be the same layer as the first semiconductor layer in the embodiment of FIG. 9 . The layer where the gate G is located can be the same layer as the first conductive layer in the embodiment of FIG. 9 . The layer where the second capacitor electrode ED2 is located can be the same layer as the second conductive layer in the embodiment of FIG. 9 . The layer where the source electrode S and the drain electrode D are located can be the same layer as the third conductive layer in the embodiment of FIG. 9 .

Figure 18 is a partial plan schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure; Figure 19 is a partial plan schematic diagram of the first semiconductor layer in the display substrate according to Figure 18; Figure 20 is a partial plan schematic diagram of the first conductive layer in the display substrate according to Figure 18; Figure 21 is a partial plan schematic diagram of the second conductive layer in the display substrate according to Figure 18; Figure 22 is a partial plan schematic diagram of the second semiconductor layer in the display substrate according to Figure 18; Figure 23 is a partial plan schematic diagram of the fifth conductive layer in the display substrate according to Figure 18; Figure 24 is a partial plan schematic diagram of the third conductive layer in the display substrate according to Figure 18; Figure 25 is a partial plan schematic diagram of the fourth conductive layer in the display substrate according to Figure 18.

In an exemplary embodiment, FIG18 is illustrated using the shift register unit provided in FIG5 as an example. Similar to the shift register unit in FIG9 , the shift register unit in FIG18 may also include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a twelfth transistor T12, a first capacitor C1, and a second capacitor C2.

The connection method of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the twelfth transistor T12, the first capacitor C1, and the second capacitor C2 can be the same as the connection method of the corresponding transistors and capacitors in the embodiment of FIG9 , and will not be repeated here. Different from the shift register unit of FIG9 , the shift register of FIG18 further includes a thirteenth transistor and the signal line connected to the first electrode of the third transistor T3 is different.

In an exemplary embodiment, as shown in FIG18 , the second transistor T2 and the third transistor T3 are located on the same side of the active layer ACT13 of the thirteenth transistor T13 along the first direction Y. In an exemplary embodiment, a control electrode G13 of the thirteenth transistor T13 is connected to a first node N1 across the first reference signal line vgl1 and the second electrode S1 of the first transistor T1. In an exemplary embodiment, the thirteenth transistor T13 is located between the first reference signal line vgl1 and the second reference signal line vgl2.

In FIG18 , because the thirteenth transistor T13 in the shift register unit can stabilize the voltage at the second node N2, the first electrode D3 of the third transistor T3 can be connected to the second reference signal line vgl2 rather than the first reference signal line vgl1 as in FIG9 , thereby minimizing circuit modifications. In some embodiments, the first electrode D3 of the third transistor T3 can also be connected to the first reference signal line vgl1 as in FIG9 , thereby further improving the voltage stability at the second node N.

18 to 25 , the display substrate may include, in addition to a first semiconductor layer (as shown in FIG. 19 ), a first conductive layer (as shown in FIG. 20 ), a second conductive layer (as shown in FIG. 21 ), a third conductive layer (as shown in FIG. 24 ), and a fourth conductive layer (as shown in FIG. 25 ), a second semiconductor layer (as shown in FIG. 22 ) and a fifth conductive layer (as shown in FIG. 23 ) disposed between the second conductive layer and the third conductive layer.

22 , the active layer ACT13 of the thirteenth transistor T13 of the shift register unit is located in the second semiconductor layer, and the active layer ACT13 may extend along the second direction. In an exemplary embodiment, the second semiconductor layer may be an oxide semiconductor layer.

As shown in FIG. 23 , the control electrode G13 of the thirteenth transistor T13 is located in the fifth conductive layer, and the projection of the control electrode G13 on the substrate at least partially overlaps with the active layer ACT3 .

As shown in FIG24 , the first electrode D13 and the second electrode S13 of the thirteenth transistor T13 are located in the third conductive layer. In FIG24 , the third conductive layer may further include a twenty-first conductive connection portion m21, and the node N2 of the third conductive layer may be implemented as a twenty-second conductive connection portion. The first electrode D13 of the thirteenth transistor T13 is implemented as the twenty-first conductive connection portion m21 in the third conductive layer, and the second electrode S13 of the thirteenth transistor T13 is implemented in the twenty-second conductive connection portion (represented by node N2) of the third conductive layer. In FIG24 , the twenty-second conductive connection portion (represented by node N2) includes, in addition to the second electrode of the thirteenth transistor T13, the second electrode of the second transistor T2 and the second electrode of the third transistor T3. The portions of the twenty-second conductive connection portion (represented by node N2) that overlap with the active layers ACT2, ACT2, and ACT13 serve as the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the second electrode of the thirteenth transistor T13, respectively. The twenty-second conductive connection portion realizes the electrical connection between the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the second electrode of the thirteenth transistor T13, and thus the twenty-second conductive connection portion can serve as a node N2. In Figure 24, the node N1 in the third conductive layer can be realized as a twenty-third conductive connection portion, which includes the second electrode of the first transistor T1 and the second electrode of the fifth transistor T5, thereby realizing the electrical connection between the second electrode of the first transistor T1 and the second electrode of the fifth transistor T5. The twenty-third conductive connection portion (represented by N1) can partially surround the twenty-first conductive connection portion m21 so as to be connected to the gate G13 of the thirteenth transistor T13 across the first reference signal line vlg1.

The control electrode G13 of the thirteenth transistor T13 is connected to the first node N1. The twenty-first conductive connection portion m21 in the third conductive layer is connected to the first reference signal line vgl1, thereby connecting the first electrode D13 of the thirteenth transistor to the first reference signal line vgl1. The first reference signal line vgl1 is connected to the first reference signal terminal VGL1. The second electrode S13 of the thirteenth transistor T13 and the second electrode S3 of the third transistor T3 are connected to the second node N2.

As shown in FIG25 , since the first electrode D3 of the third transistor T3 is connected to the second reference signal line vgl2 in this embodiment, rather than being connected to the first reference signal line vgl1 as shown in FIG9 , the first reference signal line vgl1 can be configured as a simple strip shape without having to include a branch extending toward the first electrode D3 of the third transistor T3 as shown in FIG14 .

Although certain embodiments of the present general inventive concept have been shown and described, those skilled in the art will appreciate that It will be appreciated that changes may be made in these embodiments without departing from the principles and spirit of the general disclosed concept, the scope of which is defined in the claims and their equivalents.

Claims (20)

A shift register unit, comprising: a node control subcircuit, electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the power signal terminal, the first reference signal terminal, the first node, and the second node, and configured to provide a signal from the signal input terminal to the first node under control of a signal from the first clock signal terminal, provide a signal from the first reference signal terminal or the first clock signal terminal to the second node under control of signals from the first node and the first clock signal terminal, and provide a signal from the power signal terminal to the first node under control of the second node and the second clock signal terminal; a pull-down sub-circuit electrically connected to the first node and the first reference signal terminal, and configured to provide a signal of the first reference signal terminal to the first node; an output subcircuit electrically connected to the first node, the second node, the second clock signal terminal, the third clock signal terminal, the power signal terminal, the second reference signal terminal, the first signal output terminal, and the second output signal terminal, and configured to, under control of the signals of the first node and the second node, provide a signal from the power signal terminal or the second clock signal terminal to the first signal output terminal, and provide a signal from the second reference signal terminal or the third clock signal terminal to the second signal output terminal; The signal level of the first reference signal terminal is lower than the signal level of the second reference signal terminal. The shift register unit according to claim 1, wherein a low level of a signal at at least one of the first clock signal terminal and the second clock signal terminal is lower than a signal level at the second reference signal terminal. The shift register unit according to claim 1 or 2, wherein a low level of a signal of at least one of the first clock signal terminal and the second clock signal terminal is equal to a signal level of the first reference signal terminal. The shift register unit according to any one of claims 1 to 3, wherein the low level of the signal at the third clock signal terminal is equal to the signal level of the second reference signal terminal. The shift register unit according to any one of claims 1 to 4, wherein the signal level of the first reference signal terminal and the signal low level of at least one of the first clock signal terminal and the second clock signal terminal are in the range of -15V to -9V, and the signal level of the second reference signal terminal is in the range of -4V to -8V. The shift register unit according to any one of claims 1 to 5, wherein the node control subcircuit comprises: a first transistor, a second transistor, a third transistor, a third transistor, and a fourth transistor; The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node; The control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the second node; A control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is connected to the first reference signal terminal, and a second electrode of the third transistor is electrically connected to the second node; The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the fourth node; The control electrode of the fifth transistor is electrically connected to the second clock signal terminal, the first electrode of the fifth transistor is connected to the fourth node, and the second electrode of the fifth transistor is electrically connected to the first node. The shift register unit according to any one of claims 1 to 6, wherein the output sub-circuit comprises: a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitor, and a second capacitor; The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is connected to the power signal terminal, and the second electrode of the sixth transistor is electrically connected to the first signal output terminal; The control electrode of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is connected to the second clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the first signal output terminal; The control electrode of the eighth transistor is electrically connected to the first node, the first electrode of the eighth transistor is connected to the third clock signal terminal, and the second electrode of the eighth transistor is electrically connected to the second signal output terminal; The control electrode of the ninth transistor is electrically connected to the second node, the first electrode of the ninth transistor is electrically connected to the second reference signal terminal, and the second electrode of the ninth transistor is electrically connected to the second signal output terminal; The first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the power signal terminal; The first plate of the second capacitor is electrically connected to the control electrode of the seventh transistor, and the second plate of the second capacitor is electrically connected to the first signal output terminal. The shift register unit according to claim 7, wherein the output sub-circuit further comprises: a tenth transistor, wherein the control electrode of the seventh transistor is electrically connected to the first node through the tenth transistor; The control electrode of the tenth transistor is electrically connected to the second reference signal terminal, the first electrode of the tenth transistor is connected to the first node, and the second electrode of the tenth transistor and the control electrode of the seventh transistor are connected to the third node. The shift register unit according to claim 7 or 8, wherein the output sub-circuit further comprises: an eleventh transistor; the control electrode of the eighth transistor is electrically connected to the first node through the eleventh transistor; The control electrode of the eleventh transistor is electrically connected to the second reference signal terminal, the first electrode of the eleventh transistor is electrically connected to the first node, and the second electrode of the eleventh transistor is electrically connected to the control electrode of the eighth transistor. The shift register unit according to any one of claims 1 to 9, wherein the pull-down sub-circuit comprises: a twelfth transistor; The control electrode of the twelfth transistor is electrically connected to the third node, the first electrode of the twelfth transistor is electrically connected to the first reference signal terminal, and the second electrode of the twelfth transistor is electrically connected to the first node. The shift register unit according to any one of claims 6 to 10, wherein at least one of the first to twelfth transistors is a low-temperature polysilicon transistor. The shift register unit according to claim 11, wherein at least one of the first to twelfth transistors is a P-type low-temperature polysilicon transistor. The shift register unit according to any one of claims 1 to 12 further includes: a voltage stabilizing subcircuit, wherein the voltage stabilizing subcircuit is connected to the first node, the second node and the first reference signal terminal, and is configured to provide the signal of the first reference signal terminal to the second node under the control of the first node. The shift register unit according to claim 13, wherein the voltage stabilizing subcircuit comprises: a thirteenth transistor, a control electrode of the thirteenth transistor being connected to the first node, a first electrode of the thirteenth transistor being connected to the first reference signal terminal, and a second electrode of the thirteenth transistor being connected to the second node. The shift register unit according to claim 14, wherein the thirteenth transistor is a metal oxide transistor. The shift register unit according to claim 15, wherein the thirteenth transistor is an N-type metal oxide transistor. The shift register unit according to any one of claims 1 to 16, wherein the signal at the third clock signal terminal and the signal at the second clock signal terminal are inverted signals in a partial time period. The shift register unit according to any one of claims 1 to 17, wherein the signal at the first clock signal terminal and the signal at the second clock signal terminal are not at valid levels at the same time. A display substrate comprises: a substrate, and sub-pixels, gate lines, and a gate driving circuit arranged on the substrate, wherein the substrate is provided with a display area and a non-display area, the gate driving circuit is located in the non-display area, the sub-pixels and the gate lines are located in the display area, and the gate lines are electrically connected to the sub-pixels and the gate driving circuit, respectively; The gate drive circuit includes: a plurality of cascaded shift register units according to any one of claims 1 to 18, wherein the first signal output end of the n-th stage shift register unit is connected to the signal input end of the n+i-th stage shift register unit, 1≤n＜N, i is an integer greater than or equal to 1, and N is the total number of shift register units. A method for driving a shift register unit according to any one of claims 1 to 18, the method comprising: The node control subcircuit provides the signal of the signal input terminal to the first node under the signal control of the first clock signal terminal. signal, providing a signal from the first reference signal terminal or the first clock signal terminal to the second node under the control of the signal from the first node and the first clock signal terminal; The pull-down sub-circuit provides a signal of the first reference signal terminal to the first node; Under the control of the signals of the first node and the second node, the output subcircuit provides the signal of the power signal terminal or the second clock signal terminal to the first signal output terminal, and provides the signal of the second reference signal terminal or the third clock signal terminal to the second signal output terminal.