WO2025173599A1 - Light detection device and electronic apparatus - Google Patents

Abstract

Provided is a light detection device in which narrowing of a dynamic range is minimized. This light detection device comprises a photoelectric conversion element, a charge accumulation region, a reset transistor, an amplification transistor, and a selection transistor connected in series to the amplification transistor. At least one of the reset transistor and the selection transistor is configured using a CMOS transistor including a parallel connection of an NMOS transistor and a PMOS transistor.

Description

Photodetector and electronic equipment

This technology (the technology disclosed herein) relates to photodetection devices and electronic devices, and in particular to photodetection devices and electronic devices in which signal lines are shared by multiple pixels.

Conventionally, each pixel has a transfer gate that transfers charge from the pixel (PD) to a floating potential node, an amplification transistor that transfers that signal to the downstream circuit, and a selection transistor that switches the target pixel. Having this selection transistor allows the signal line (VSL) that transfers the signal to the downstream circuit to be shared by multiple pixels, making it possible to reduce the scale of the downstream circuit. However, as mentioned above, when the VSL is shared by multiple pixels, the dynamic range (D-Range) of the pixel output can often be narrowed due to the selection transistors of the non-selected pixels.

The image sensor disclosed in Patent Document 1 uses a charge pump to prevent the dynamic range from being narrowed.

Furthermore, Patent Document 2 shows a transistor in which a portion of the gate electrode is buried in the substrate.

Japanese Patent Application Laid-Open No. 2021-82901 JP 2013-125862 A

The purpose of this technology is to provide a photodetector and electronic device in which the dynamic range is prevented from being narrowed.

A photodetector according to one aspect of the present technology includes a photoelectric conversion element, a charge accumulation region, a reset transistor, an amplification transistor, and a selection transistor connected in series to the amplification transistor, and at least one of the reset transistor and the selection transistor is configured using a CMOS transistor including a parallel connection of an NMOS transistor and a PMOS transistor.

An electronic device according to one aspect of the present technology includes the above-described light detection device and an optical system that focuses image light from a subject onto the light detection device.

1 is a chip layout diagram showing a configuration example of a photodetector according to a first embodiment of the present technology; 1 is a block diagram showing an example of the configuration of a photodetector according to a first embodiment of the present technology; 1 is an equivalent circuit diagram of a pixel of a photodetector according to a first embodiment of the present technology; 1 is an equivalent circuit diagram showing a selected pixel and a non-selected pixel of a photodetector according to a first embodiment of the present technology; FIG. 10 is an explanatory diagram showing the relationship between the voltage range that can be output by the amplification transistor, the voltage range that can pass through the selection transistor of a selected pixel, and the voltage range that can be cut off by the selection transistor of a non-selected pixel in the first embodiment of the present technology. 1 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a first embodiment of the present technology. FIG. 2 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a first modified example of the first embodiment of the present technology. FIG. 10 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a second modification of the first embodiment of the present technology. FIG. 10 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a third modification of the first embodiment of the present technology. FIG. 11 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a fourth modified example of the first embodiment of the present technology. FIG. 11 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a fifth modified example of the first embodiment of the present technology. FIG. 13 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a sixth modified example of the first embodiment of the present technology. FIG. 13 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a seventh modified example of the first embodiment of the present technology. FIG. 13 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to an eighth modification of the first embodiment of the present technology. FIG. 13 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a ninth modification of the first embodiment of the present technology. FIG. 22 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a tenth modification of the first embodiment of the present technology. FIG. 23 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to an eleventh modification of the first embodiment of the present technology. FIG. 23 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a twelfth modification of the first embodiment of the present technology. FIG. 23 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a thirteenth modification of the first embodiment of the present technology. FIG. 23 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a fourteenth modification of the first embodiment of the present technology. FIG. 23 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a fifteenth modification of the first embodiment of the present technology. FIG. 23 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a sixteenth modification of the first embodiment of the present technology. FIG. 23 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a seventeenth modification of the first embodiment of the present technology. FIG. 23 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to an eighteenth modification of the first embodiment of the present technology. FIG. 23 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a nineteenth modification of the first embodiment of the present technology. FIG. 20 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a twentieth modification of the first embodiment of the present technology. FIG. 23 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a twenty-first modification of the first embodiment of the present technology. FIG. 10 is an equivalent circuit diagram of a pixel of a photodetector according to a second embodiment of the present technology. FIG. 10 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a second embodiment of the present technology. FIG. 10 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a first modified example of the second embodiment of the present technology. FIG. 10 is an equivalent circuit diagram of a pixel of a photodetector according to a fourth embodiment of the present technology. FIG. 10 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a fourth embodiment of the present technology. FIG. 1 is a block diagram illustrating an example of a schematic configuration of an electronic device.

Below, a preferred embodiment for implementing this technology will be described with reference to the drawings. Note that the embodiment described below is an example of a typical embodiment of this technology, and should not be construed as narrowing the scope of this technology.

In the following drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratios of each layer, etc., may differ from reality. Therefore, specific thicknesses and dimensions should be determined with reference to the following explanation. Naturally, parts with different dimensional relationships and ratios are included between the drawings. Furthermore, because drawings suitable for explaining this technology have been used, there may be differences in configuration between the drawings. Note that well regions may be omitted from the drawings relating to this technology. Even when well regions are omitted, NMOS transistors are provided in p-type well regions, and PMOS transistors are provided in n-type well regions.

Furthermore, the embodiments described below are examples of devices and methods that embody the technical concept of the present technology, and the technical concept of the present technology does not limit the materials, shapes, structures, arrangements, etc. of the components to those described below. The technical concept of the present technology can be modified in various ways within the technical scope defined by the claims.

Furthermore, the definitions of directions such as up and down in the following explanation are merely for the convenience of explanation and do not limit the technical ideas of this disclosure. For example, if an object is rotated 90 degrees and observed, up and down will be converted to left and right and read as such, and if it is rotated 180 degrees and observed, up and down will of course be read as reversed.

The explanation will be given in the following order.
1. First embodiment 2. Second embodiment 3. Third embodiment 4. Fourth embodiment 5. Fifth embodiment 6. Sixth embodiment Application examples to electronic devices

[First embodiment]
In this embodiment, an example in which the present technology is applied to a photodetector device that is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor will be described.

<Overall configuration of the photodetector>
First, the overall configuration of the photodetector 1 will be described. As shown in Fig. 1 , the photodetector 1 according to the first embodiment of the present technology is mainly composed of a semiconductor chip 2 having a rectangular two-dimensional planar shape when viewed in plan. That is, the photodetector 1 is mounted on the semiconductor chip 2. As shown in Fig. 33 , the photodetector 1 captures image light (incident light 106) from a subject via an optical system (optical lens) 102, converts the amount of incident light 106 formed on an imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal as a pixel signal.

As shown in Figure 1, the semiconductor chip 2 on which the photodetector 1 is mounted has a rectangular pixel region 2A located in the center of a two-dimensional plane including the X and Y directions, which intersect with each other, and a peripheral region 2B located outside this pixel region 2A so as to surround it.

The pixel region 2A is a light receiving surface that receives light collected by the optical system 102 shown in FIG. 33, for example. In the pixel region 2A, a plurality of pixels 3 are arranged in a matrix on a two-dimensional plane including the X and Y directions. In other words, the pixels 3 are repeatedly arranged in each of the X and Y directions that intersect with each other within the two-dimensional plane. In this embodiment, as an example, the X and Y directions are orthogonal to each other. The direction orthogonal to both the X and Y directions is the Z direction (thickness direction, stacking direction, depth direction). The direction perpendicular to the Z direction is the horizontal direction (lateral direction).

As shown in FIG. 1, a plurality of bonding pads 14 are arranged in the peripheral region 2B. Each of the plurality of bonding pads 14 is arranged, for example, along each of the four sides of the semiconductor chip 2 in a two-dimensional plane. Each of the plurality of bonding pads 14 is an input/output terminal used to electrically connect the semiconductor chip 2 to an external device.

<Logic circuit>
2, the semiconductor chip 2 includes a logic circuit 13. The logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 is configured with a CMOS (Complementary MOS) circuit having, as field effect transistors, for example, n-channel conductivity type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and p-channel conductivity type MOSFETs.

The vertical drive circuit 4 is composed of, for example, a shift register. The vertical drive circuit 4 sequentially selects the desired pixel drive lines 10 and supplies pulses to the selected pixel drive lines 10 to drive the pixels 3, driving each pixel 3 row by row. In other words, the vertical drive circuit 4 sequentially selects and scans each pixel 3 in the pixel region 2A row by row in the vertical direction, and supplies pixel signals from the pixels 3 based on signal charges generated by the photoelectric conversion elements of each pixel 3 in accordance with the amount of light received to the column signal processing circuit 5 via the vertical signal lines 11.

The column signal processing circuit 5 is arranged, for example, for each column of pixels 3, and performs signal processing such as noise removal for each pixel column on the signals output from one row of pixels 3. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) to remove fixed pattern noise specific to the pixels and AD (Analog-Digital) conversion. A horizontal selection switch (not shown) is provided at the output stage of the column signal processing circuit 5 and connected between it and the horizontal signal line 12.

The horizontal drive circuit 6 is composed of, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuits 5, thereby selecting each of the column signal processing circuits 5 in turn and causing each column signal processing circuit 5 to output processed pixel signals to the horizontal signal line 12.

The output circuit 7 processes and outputs pixel signals sequentially supplied from each column signal processing circuit 5 via the horizontal signal line 12. Signal processing can include, for example, buffering, black level adjustment, column variation correction, and various types of digital signal processing.

The control circuit 8 generates clock signals and control signals that serve as the basis for the operation of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc. based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal. The control circuit 8 then outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

<Pixels>
3 is an equivalent circuit diagram showing an example of the configuration of a pixel 3. The pixel 3 includes a photoelectric conversion element PD, a charge accumulation region (floating diffusion) FD that accumulates (holds) signal charges photoelectrically converted by the photoelectric conversion element PD, and a transfer transistor TR (or transfer gate) that transfers the signal charges photoelectrically converted by the photoelectric conversion element PD to the charge accumulation region FD. The pixel 3 also includes a readout circuit 15 electrically connected to the charge accumulation region FD.

The photoelectric conversion element PD generates a signal charge according to the amount of light received. The photoelectric conversion element PD also temporarily accumulates (holds) the generated signal charge. The cathode side of the photoelectric conversion element PD is electrically connected to the source region of the transfer transistor TR, and the anode side is electrically connected to a reference potential line (e.g., ground). For example, a photodiode is used as the photoelectric conversion element PD.

The drain region of the transfer transistor TR is electrically connected to the charge storage region FD. The gate electrode of the transfer transistor TR is electrically connected to a transfer transistor drive line, one of the pixel drive lines 10 (see Figure 2).

The charge storage region FD temporarily stores and holds the signal charge transferred from the photoelectric conversion element PD via the transfer transistor TR.

The readout circuit 15 reads out the signal charge accumulated in the charge accumulation region FD and outputs a pixel signal based on the signal charge. The readout circuit 15 includes, but is not limited to, pixel transistors, such as an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. These transistors (AMP, SEL, RST) are configured as MOSFETs having a gate insulating film made of a silicon oxide film (SiO ₂ film, SiO 2 film), a gate electrode, and a pair of main electrode regions functioning as a source region and a drain region. These transistors may also be metal insulator semiconductor FETs (MISFETs) whose gate insulating film is made of a silicon nitride film (Si ₃ N ₄ film, SiN film) or a stacked film of a silicon nitride film, a silicon oxide film, etc. A readout circuit 15 may be provided for each photoelectric conversion element PD, or one readout circuit 15 may be shared by multiple photoelectric conversion elements PD. Similarly, a charge accumulation region FD may be provided for each photoelectric conversion element PD, or one charge accumulation region FD may be shared by a plurality of photoelectric conversion elements PD.

The source region of the amplifier transistor AMP is electrically connected to the first terminal a of the select transistor SEL, and the drain region is electrically connected to the power supply line Vdd and the drain region of the reset transistor. The gate electrode of the amplifier transistor AMP is electrically connected to the charge storage region FD and the source region of the reset transistor RST.

The second terminal b of the selection transistor SEL is electrically connected to the vertical signal line 11 (VSL), and the first terminal a is electrically connected to the source region of the amplification transistor AMP. The gate electrode of the selection transistor SEL is electrically connected to a selection transistor drive line among the pixel drive lines 10 (see Figure 2).

The source region of the reset transistor RST is electrically connected to the charge storage region FD and the gate electrode of the amplifier transistor AMP, and the drain region is electrically connected to the power supply line Vdd (or power supply line VBO) and the drain region of the amplifier transistor AMP. The gate electrode of the reset transistor RST is electrically connected to the reset transistor drive line, which is one of the pixel drive lines 10 (see Figure 2).

Below, the amplification transistor AMP and the selection transistor SEL will be described in more detail with reference to Figure 4. Note that Figure 4 omits the illustration of transistors other than the amplification transistor AMP and the selection transistor SEL. The amplification transistor AMP is connected in series with the selection transistor SEL and is electrically connected to the vertical signal line 11 (VSL) via the selection transistor SEL. Since the selection transistor SEL switches the pixel 3 to be read, one vertical signal line 11 can be shared by multiple pixels 3. Note that the number of pixels 3 sharing one vertical signal line 11 is not limited to that shown in Figure 4. The selection transistor SEL is configured as a CMOS transistor (CMOS circuit). The CMOS transistor (CMOS circuit) includes a first transistor SEL1 and a second transistor SEL2 connected in parallel. The first transistor SEL1 is an NMOS transistor (n-channel conductivity type MOSFET, hereinafter sometimes referred to as NMOS), and the second transistor SEL2 is a PMOS transistor (p-channel conductivity type MOSFET, hereinafter sometimes referred to as PMOS). The drain region of the first transistor SEL1 and the source region of the second transistor SEL2 are connected to the first terminal a. The source region of the first transistor SEL1 and the drain region of the second transistor SEL2 are connected to the second terminal b. Hereinafter, the pixel 3 to be read out will be referred to as the selected pixel 3a, and the pixel 3 not to be read out will be referred to as the non-selected pixel 3b, to distinguish them from each other. When there is no need to distinguish between the selected pixel 3a and the non-selected pixel 3b, they will simply be referred to as the pixel 3. The selection transistor SEL of the selected pixel 3a is in the on state, and the amplification transistor AMP is electrically connected to the vertical signal line 11 via the selection transistor SEL. The selection transistor SEL of the non-selected pixel 3b is in the off state.

5 shows the relationship between the voltage range L that the amplifier transistor AMP can output, the voltage range M that can pass through the select transistor SEL of the selected pixel 3a, and the voltage range N that can cut off the select transistor SEL of the non-selected pixel 3b. The voltage range L that the amplifier transistor AMP can output is designed to range from voltage V1 to voltage V2. The voltage range M that can pass through the select transistor SEL of the selected pixel 3a is designed to range from voltages higher than voltage V1 to voltages lower than voltage V2. In the selected pixel 3a, the output voltage of the amplifier transistor AMP is supplied to the vertical signal line 11 via at least one of the first transistor SEL1 and the second transistor SEL2. The voltage range N that can cut off the select transistor SEL of the non-selected pixel 3b is designed to range from voltages higher than voltage V1 to voltages lower than voltage V2. Because the select transistor SEL is composed of the above-mentioned CMOS transistor, it is possible to design the cut-off voltage CutLo of the first transistor SEL1 to a voltage lower than voltage V2, which is the lower limit of the voltage that the amplifier transistor AMP can output. This prevents the voltage V2 from being restricted by the cut-off voltage CutLo. As a result, in the non-selected pixel 3b, the selection transistor SEL can block a voltage range that includes the voltage range L that can be output by the amplification transistor AMP.

<<Specific configuration of the photodetector>>
Next, a specific configuration of the photodetector 1 according to the first embodiment of the present technology will be described with reference to Fig. 6. Note that in Fig. 6 and subsequent drawings, wiring in the equivalent circuit shown in Fig. 3 may be indicated by solid lines or dotted lines.

<Layer structure of photodetector>
The photodetector 1 has a stacked structure in which, for example, a first semiconductor layer 20 and a first wiring layer 30 are stacked in that order. The photodetector 1 further has a second semiconductor layer 40. In the following description, a case will be described in which the first conductivity type is n-type and the second conductivity type is p-type. Note that simply referring to n-type indicates the first conductivity type, and simply referring to p-type indicates the second conductivity type. Note that the present technology is not limited to this, and the first conductivity type may be p-type and the second conductivity type may be n-type.

<First Semiconductor Layer>
One surface of the first semiconductor layer 20 is a first surface S1, and the other surface is a second surface S2. The first surface S1 may be referred to as an element formation surface or a main surface, and the second surface S2 may be referred to as a back surface. In this embodiment, a case where the second surface S2 is a light incident surface will be described, but the present technology is not limited to this. The first surface S1 may be a light incident surface.

The first semiconductor layer 20 is composed of a semiconductor substrate. The first semiconductor layer 20 is composed of, for example, a single-crystal silicon substrate, although this is not limited to this. The first semiconductor layer 20 is provided with semiconductor regions such as an n-type photoelectric conversion region 21, an n+-type charge accumulation region 22, and a p-type well region (not shown). Furthermore, a transfer transistor TR, a reset transistor RST, and an amplification transistor AMP are provided on the first surface S1 side of the first semiconductor layer 20. All of the transfer transistor TR, reset transistor RST, and amplification transistor AMP are NMOS transistors capable of forming an n-channel.

As shown in FIG. 1, a plurality of island-shaped cell regions 20a partitioned by isolation regions are provided in a matrix in the portion of the first semiconductor layer 20 corresponding to the pixel region 2A. For example, one cell region 20a is provided for each pixel 3. A plurality of photoelectric conversion regions 21 (FIG. 6) are provided in a matrix in the portion of the first semiconductor layer 20 corresponding to the pixel region 2A. For example, one photoelectric conversion region 21 is provided for each cell region 20a. The photoelectric conversion element PD includes a photoelectric conversion region 21.

<Second Wiring Layer and Second Semiconductor Layer>
As shown in FIG. 6 , the first wiring layer 30 is a multi-layer wiring layer stacked on the first surface S1. The first wiring layer 30 includes, but is not limited to, an insulating film 31 made of a known insulating material, and wiring such as horizontal wiring and vertical wiring (vias) made of a conductive material provided within the insulating film 31. The insulating film 31 may have a layered structure in which multiple insulating films are stacked. The horizontal wiring is wiring that extends mainly in the horizontal direction. The vertical wiring is wiring that extends mainly in the depth direction. Furthermore, the first wiring layer 30 is provided with gate electrodes of transistors.

A second semiconductor layer 40 is provided on the first wiring layer 30. The second semiconductor layer 40 is a semiconductor layer provided at a position different from the first semiconductor layer 20 along the depth direction of the photodetector 1. The second semiconductor layer 40 is not in direct contact with the first semiconductor layer 20, and an insulating film, for example, is provided between the two. The first transistor SEL1 and the second transistor SEL2 of the select transistor SEL are provided on the second semiconductor layer 40. The second semiconductor layer 40 is a thin-film semiconductor layer and is different from the first semiconductor layer 20, which is a bulk semiconductor layer. The first transistor SEL1 and the second transistor SEL2 are thin-film transistors (TFTs) provided on the thin-film semiconductor layer. Hereinafter, all transistors provided on the thin-film semiconductor layer will be considered to be thin-film transistors. The first transistor SEL1 is an NMOS capable of forming a channel of the same conductivity type (e.g., n-type) as the conductivity type of the photoelectric conversion region 21. The second transistor SEL2 is a PMOS that can form a channel of a different conductivity type (e.g., p-type) from the conductivity type of the photoelectric conversion region 21.

The first transistor SEL1 has a first semiconductor region 40a in the second semiconductor layer 40, electrodes 32a and 32b, a gate electrode 33a, and a gate insulating film 34a. The second transistor SEL2 has a second semiconductor region 40b in the second semiconductor layer 40, electrodes 32b and 32c, a gate electrode 33b, and a gate insulating film 34b. When the first semiconductor region 40a and the second semiconductor region 40b are not distinguished from one another, they are simply referred to as the second semiconductor layer 40. When the electrodes 32a, 32b, and 32c are not distinguished from one another, they are simply referred to as the electrode 32. When the gate electrodes 33a and 33b are not distinguished from one another, they are simply referred to as the gate electrode 33. When the gate insulating film 34a and the gate insulating film 34b are not distinguished from one another, they are simply referred to as the gate insulating film 34. The second transistor SEL2, which is a PMOS, is desirably provided in a semiconductor layer other than the first semiconductor layer 20.

The insulating film 31 (interlayer insulating film) of the first wiring layer 30 is made of, for example, TEOS, silicon nitride, silicon oxide, etc. Furthermore, for example, the insulating film of the first wiring layer 30 can be made of SiCN, _SiCON , _HfO2 , _Al2O3 , _ZrO2, etc. Note that the insulating film of the first wiring layer 30 may be made of other insulating materials. The insulating film of the first wiring layer 30 also serves as a passivation film (protective film) for the thin film transistors, and is formed so as to cover the periphery of each thin film transistor.

The first semiconductor region 40a and the second semiconductor region 40b of the second semiconductor layer 40 are regions where a channel is formed (channel regions). The second semiconductor layer 40 is formed using, for example, a two-dimensional material ( _MoS2 , _WS2 , _MoSe2 , _WSe2 , _HfS2 , etc.), an oxide semiconductor (InGaZnO, InZnO, ZnO, SnO, _TiO2 , etc.), etc. The second semiconductor layer 40 may be configured using an organic semiconductor (fullerene, pentacene, rubrene, etc.), carbon nanotubes, hydrogenated amorphous silicon, low-temperature polysilicon, etc. as a channel material.

One of electrodes 32a, 32b is the source electrode of first transistor SEL1, and the other of electrodes 32a, 32b is the drain electrode of first transistor SEL1. One of electrodes 32b, 32c is the source electrode of second transistor SEL2, and the other of electrodes 32b, 32c is the drain electrode of second transistor SEL2. Electrode 32 is formed using a metal material such as copper (Cu), tungsten (W), ruthenium (Ru), or cobalt (Co). Note that electrode 32 may also be formed using other conductive materials. Electrode 32 may be formed from a low-resistance conductive material. Electrode 32 may also be formed using part of the wiring provided in the first wiring layer 30.

The gate electrode 33 is formed using a metal material such as Au, Pt, Cu, Ti, W, Pd, TiN, TaN, TiAl, Bi, In, Al, Sc, Co, or Mo. The gate electrode 33 may also be formed using other conductive materials. The gate electrode 33 may also be formed using part of the wiring provided in the first wiring layer 30.

The gate insulating film 34 is made of, for example, silicon oxide, silicon nitride, etc. Also, for example, the gate insulating film 34 is formed using an insulating material such as Al ₂ O ₃ , HfO ₂ , ZrO ₂ , LaO ₂ , HfSiO, Y ₂ O ₃ , SiON, etc. Note that the gate insulating film 34 may be made of other insulating materials.

<<Major Effects of First Embodiment>>
The main effects of the first embodiment will be described below, but first, an overview will be provided. Conventionally, the selection transistor SEL has been configured with a single transistor. For example, the selection transistor SEL has been configured with a single NMOS. As a result, in a non-selected pixel 3b, a leakage current may be supplied to the vertical signal line 11 via the selection transistor SEL in the off state. More specifically, the cut-off voltage of the selection transistor SEL cannot be made sufficiently small, and a leakage current may be supplied to the vertical signal line 11 via the selection transistor SEL in the off state. As a result, the voltage range L that can be output by the amplification transistor AMP of the selected pixel 3a may be narrowed. More specifically, the voltage range L that can be output by the amplification transistor AMP of the selected pixel 3a may be limited to between the voltage V1 and the cut-off voltage of the selection transistor SEL.

In addition, pixel transistors are generally all NMOS transistors capable of forming the same n-type channel as the photoelectric conversion region 21, and do not include PMOS transistors. In the first semiconductor layer 20, a p-type well region is provided between the n-type photoelectric conversion region 21 and the NMOS transistor. The reason why it is difficult to configure pixel transistors with PMOS transistors is explained below. To provide a PMOS transistor in the cell region 20a, an n-type well region must be provided. However, to ensure an area for providing an n-type well region in the minute cell region 20a, the area occupied by the n-type photoelectric conversion region 21 must be reduced. This ends up affecting the saturation charge amount of the photoelectric conversion region 21.

In contrast, in the photodetector device 1 according to the first embodiment of the present technology, the select transistor SEL is configured using a CMOS transistor that includes a parallel connection of an NMOS and a PMOS. This makes it possible to design the cut-off voltage CutLo of the first transistor SEL1 to be lower than the voltage V2, which is the lower limit of the voltage range L that can be output by the amplifier transistor AMP. For the NMOS and PMOS of the select transistor SEL, a cut-off voltage CutLo that does not generate a leak current in non-selected pixels 3b can be set. Therefore, even when multiple pixels 3 share the vertical signal line 11, it is possible to prevent the dynamic range of the amplifier transistor AMP from being narrowed due to non-selected pixels 3b.

Furthermore, according to the photodetector device 1 of the first embodiment of the present technology, the select transistor SEL is configured using a CMOS transistor, so that in the selected pixel 3a, the output voltage of the amplifier transistor AMP can be supplied to the vertical signal line 11 via at least one of an NMOS and a PMOS. As a result, the voltage range L that can be output by the amplifier transistor AMP is included in the voltage range M that can pass through the select transistor SEL in the selected pixel 3a. The threshold voltage of the amplifier transistor AMP can be lowered without any restrictions on the cut-high voltage CutHi of the select transistor SEL, preventing random noise (RN) from increasing and preventing the saturation charge amount (Qs) from decreasing by increasing the operating value of the amplifier transistor AMP.

Furthermore, according to the photodetector 1 according to the first embodiment of the present technology, the narrowing of the dynamic range is suppressed by using CMOS transistors. As a result, there is no need to use a charge pump to lower the cut-low voltage CutLo, and there is no need to secure an area on the semiconductor chip 2 for the charge pump.

Furthermore, because the photodetector 1 according to the first embodiment of the present technology uses CMOS transistors for switching, the on/off potential difference of the transistors can be reduced compared to when switching is performed using only NMOS or only PMOS. This makes it possible to reduce power consumption.

Furthermore, according to the photodetector 1 of the first embodiment of the present technology, the photodetector 1 includes a first semiconductor layer 20 and a second semiconductor layer 40 provided at a different position from the first semiconductor layer 20 in the depth direction. Of the NMOS and PMOS transistors included in the CMOS transistor, the PMOS is provided in the second semiconductor layer 40. By providing the PMOS in the second semiconductor layer 40, only NMOS transistors are provided in the cell region 20a of the first semiconductor layer 20. Therefore, the well region provided in the cell region 20a of the first semiconductor layer 20 can be only a p-type well region out of p-type and n-type well regions. This eliminates the need to provide an n-type well region in the cell region 20a of the first semiconductor layer 20, which may compress the region where the photoelectric conversion region 21 is provided. This makes it possible to suppress a decrease in the saturated charge amount. Furthermore, by providing the PMOS in the second semiconductor layer 40, it is possible to prevent the area occupied by the select transistor SEL in the cell region 20a of the first semiconductor layer 20 from becoming too large. This prevents the area occupied by the amplifier transistor AMP from becoming too small, and prevents random noise from becoming too large.

<<Modification of the First Embodiment>>
Modifications of the first embodiment will be described below. In each of the following modifications, the positions of the first transistor SEL1 and the second transistor SEL2 may be interchanged. In such cases, the routing of the wiring related to the first transistor SEL1 and the second transistor SEL2 may be appropriately changed according to the equivalent circuit diagram shown in FIG.

<Modification 1>
7 , the photodetector 1 according to the first modification of the first embodiment has a stacked structure in which a first semiconductor layer 20, a first wiring layer 30, a second semiconductor layer 40, and a second wiring layer 50 are stacked in that order. The second semiconductor layer 40 is a bulk semiconductor layer rather than a thin film. The first transistor SEL1 and the second transistor SEL2 included in the select transistor SEL are provided in the second semiconductor layer 40.

One surface of the second semiconductor layer 40 is the third surface S3, and the other surface is the fourth surface S4. The third surface S3 may be called the element formation surface or main surface, and the fourth surface S4 may be called the back surface. In this modification, the fourth surface S4 faces the first surface S1 of the first semiconductor layer 20. The second semiconductor layer 40 is made of a semiconductor substrate. The second semiconductor layer 40 is made of, for example, a single-crystal silicon substrate, although this is not limited to this. The first transistor SEL1 and second transistor SEL2 provided in the second semiconductor layer 40 are not thin-film transistors, but are ordinary planar transistors provided in a bulk semiconductor layer.

A second wiring layer 50 is laminated on the third surface S3 of the second semiconductor layer 40. The second wiring layer 50 is a multi-layer wiring layer. The second wiring layer 50 includes, but is not limited to, an insulating film 51 made of a known insulating material, and wiring such as horizontal wiring and vertical wiring (vias) made of a conductive material disposed within the insulating film 51. The insulating film 51 may have a layered structure in which multiple insulating films are stacked. Examples of insulating materials that make up the insulating film 51 include silicon oxide, silicon nitride, and silicon oxynitride (SiON). Examples of conductive materials include metal materials such as copper (Cu), aluminum (Al), and tungsten (W), and semiconductor materials such as silicon that has been made conductive with impurities. The material that makes up the second wiring layer 50 may be the same as the material that makes up the first wiring layer 30.

The photodetector 1 has a through conductor TSV that forms part of the wiring of the equivalent circuit of the pixel 3. The through conductor TSV penetrates the second semiconductor layer 40.

Even with the light detection device 1 according to this first modification of the first embodiment, the same effects as those of the light detection device 1 according to the first embodiment described above can be obtained.

<Modification 2>
As shown in FIG. 8 , the photodetector 1 according to the second modification of the first embodiment has a stacked structure in which a first semiconductor layer 20, a first wiring layer 30, a second wiring layer 50, and a second semiconductor layer 40 are stacked in that order. The second semiconductor layer 40 is a bulk semiconductor layer rather than a thin film. The first transistor SEL1 and the second transistor SEL2 of the select transistor SEL are provided in the second semiconductor layer 40. More specifically, the first transistor SEL1, which is an NMOS transistor, is provided in a p-type well region 41, and the second transistor SEL2, which is a PMOS transistor, is provided in an n-type well region 42. In this modification, the third surface S3 faces the first surface S1 of the first semiconductor layer 20.

The photodetector 1 has connection pads C1 and C2 that electrically connect the wiring. Connection pad C1 is provided on the first wiring layer 30, and connection pad C2 is provided on the second wiring layer 50. Connection pad C1 and connection pad C2 form a pair of connection pads and are bonded to each other. For example, connection pads C1 and C2 electrically connect the wiring provided on the first wiring layer 30 and the wiring provided on the second wiring layer 50.

The light detection device 1 according to this second modification of the first embodiment also provides the same effects as the light detection device 1 according to the first embodiment described above.

<Modification 3>
9 , the photodetector 1 according to the third modification of the first embodiment has a stacked structure in which a first semiconductor layer 20, a first wiring layer 30, a first layer 40A of a second semiconductor layer 40, and a second wiring layer 50 are stacked in that order. The second semiconductor layer 40 includes the first layer 40A and a second layer 40B that is provided at a different position in the depth direction from the first layer 40A. The first layer 40A is not in direct contact with the second layer 40B, and an insulating film, for example, is provided between the two.

The first layer 40A is a bulk semiconductor layer, not a thin film. The first layer 40A has a configuration similar to that of the second semiconductor layer 40 described in Variation 1 of the first embodiment. The fourth surface S4 of the first layer 40A faces the first surface S1 of the first semiconductor layer 20. The second transistor SEL2 is provided in the first layer 40A. The second layer 40B is a thin film semiconductor layer and is provided in the second wiring layer 50. The second layer 40B has a configuration similar to that of the second semiconductor layer 40 described in the first embodiment. The first transistor SEL1 is provided in the second layer 40B. The photodetector 1 has a through conductor TSV that penetrates the first layer 40A. In this way, the first transistor SEL1 and the second transistor SEL2 may be provided separately in a thin film semiconductor layer and a bulk semiconductor layer.

The light detection device 1 according to this third modification of the first embodiment also provides the same effects as the light detection device 1 according to the first embodiment described above.

<Modification 4>
10 , the photodetector 1 according to the fourth modification of the first embodiment has a stacked structure in which a first semiconductor layer 20, a first wiring layer 30, a first layer 40A, and a second wiring layer 50 are stacked in that order. A fourth surface S4 of the first layer 40A faces the first surface S1 of the first semiconductor layer 20. The first layer 40A is a bulk semiconductor layer. The second transistor SEL2 is provided on the first layer 40A. The second layer 40B is a thin-film semiconductor layer and is provided on the first wiring layer 30. The first transistor SEL1 is provided on the second layer 40B. The photodetector 1 has a through conductor TSV that penetrates the first layer 40A.

The light detection device 1 according to this fourth modification of the first embodiment also provides the same effects as the light detection device 1 according to the first embodiment described above.

<Modification 5>
11 , the photodetector 1 according to the fifth modification of the first embodiment has a stacked structure in which a first semiconductor layer 20, a first wiring layer 30, a second wiring layer 50, and a first layer 40A are stacked in that order. The third surface S3 of the first layer 40A faces the first surface S1 of the first semiconductor layer 20. The first layer 40A is a bulk semiconductor layer. The second transistor SEL2 is provided on the first layer 40A. The second layer 40B is a thin-film semiconductor layer and is provided on the first wiring layer 30. The first transistor SEL1 is provided on the second layer 40B. The photodetector 1 has connection pads C1 and C2.

The light detection device 1 according to this fifth modification of the first embodiment also provides the same effects as the light detection device 1 according to the first embodiment described above.

<Modification 6>
12 , the photodetector 1 according to the sixth modification of the first embodiment has a stacked structure in which a first semiconductor layer 20, a first wiring layer 30, a second wiring layer 50, and a first layer 40A are stacked in that order. A third surface S3 of the first layer 40A faces the first surface S1 of the first semiconductor layer 20. The first layer 40A is a bulk semiconductor layer. A second transistor SEL2 is provided on the first layer 40A. A second layer 40B is a thin-film semiconductor layer and is provided on the second wiring layer 50. A first transistor SEL1 is provided on the second layer 40B. The photodetector 1 has connection pads C1 and C2.

Even with the light detection device 1 according to this sixth modification of the first embodiment, the same effects as those of the light detection device 1 according to the first embodiment described above can be obtained.

<Modification 7>
As shown in FIG. 13 , the photodetector 1 according to the seventh modification of the first embodiment has a stacked structure in which a first semiconductor layer 20, a first wiring layer 30, a first layer 40A, a second wiring layer 50, a third wiring layer 60, and a second layer 40B are stacked in this order. The fourth surface S4 of the first layer 40A faces the first surface S1 of the first semiconductor layer 20. The first layer 40A is a bulk semiconductor layer. The second transistor SEL2 is provided in the first layer 40A. The second layer 40B is a bulk semiconductor layer, not a thin film. The second layer 40B has a configuration similar to that of the first layer 40A. The first transistor SEL1 is provided in the second layer 40B.

A third wiring layer 60 is laminated on the fifth surface S5 of the second layer 40B. The third wiring layer 60 is a multi-layer wiring layer. The third wiring layer 60 includes, but is not limited to, an insulating film 61 made of a known insulating material, and wiring such as horizontal wiring and vertical wiring (vias) made of a conductive material disposed within the insulating film 61. The insulating film 61 may have a layered structure in which multiple insulating films are stacked. Examples of insulating materials that make up the insulating film 61 include silicon oxide, silicon nitride, and silicon oxynitride (SiON). Examples of conductive materials include metal materials such as copper (Cu), aluminum (Al), and tungsten (W), and semiconductor materials such as silicon that has been made conductive with impurities. The material that makes up the third wiring layer 60 may be the same as the material that makes up the first wiring layer 30.

The photodetector 1 has connection pads C1 and C2 that electrically connect the wiring. The connection pad C1 is provided on the second wiring layer 50, and the connection pad C2 is provided on the third wiring layer 60. For example, the connection pads C1 and C2 electrically connect the wiring provided on the second wiring layer 50 and the wiring provided on the third wiring layer 60. The photodetector 1 has a through conductor TSV that penetrates the first layer 40A.

Even with the light detection device 1 according to this seventh modification of the first embodiment, the same effects as those of the light detection device 1 according to the first embodiment described above can be obtained.

<Modification 8>
As shown in FIG. 14 , the photodetector 1 according to the eighth modification of the first embodiment has a stacked structure in which a first semiconductor layer 20, a first wiring layer 30, a second wiring layer 50, a first layer 40A, a third wiring layer 60, and a second layer 40B are stacked in that order. The third surface S3 of the first layer 40A faces the first surface S1 of the first semiconductor layer 20. The first layer 40A is a bulk semiconductor layer. The second transistor SEL2 is provided in the first layer 40A. The second layer 40B is a bulk semiconductor layer, not a thin film. The second layer 40B has a configuration similar to that of the first layer 40A. The first transistor SEL1 is provided in the second layer 40B.

The photodetector 1 has connection pads C1 and C2 that electrically connect the wiring. The connection pad C1 is provided on the first wiring layer 30, and the connection pad C2 is provided on the second wiring layer 50. For example, the connection pads C1 and C2 electrically connect the wiring provided on the first wiring layer 30 and the wiring provided on the second wiring layer 50. The photodetector 1 has a through conductor TSV that penetrates the first layer 40A.

Even with the light detection device 1 according to this eighth modification of the first embodiment, the same effects as those of the light detection device 1 according to the first embodiment described above can be obtained.

<Modification 9>
15 , the photodetector 1 according to the ninth modification of the first embodiment has a stacked structure in which a first semiconductor layer 20 and a first wiring layer 30 are stacked in that order. A second semiconductor layer 40 is provided on the first wiring layer 30. The second semiconductor layer 40 is a thin-film semiconductor layer, which differs from the bulk first semiconductor layer 20. The second semiconductor layer 40 is a semiconductor layer provided at a position different from the first semiconductor layer 20 along the depth direction of the photodetector 1. The first transistor SEL1 is provided in the first semiconductor layer 20, and the second transistor SEL2 is provided in the second semiconductor layer 40. The first transistor SEL1 is an NMOS, and therefore can be provided in the first semiconductor layer 20.

The light detection device 1 according to this variation 9 of the first embodiment also provides the same effects as the light detection device 1 according to the first embodiment described above.

<Modification 10>
16 shows a photodetector 1 according to a tenth modification of the first embodiment. The photodetector 1 according to this modification differs from the photodetector 1 according to the first modification of the first embodiment shown in FIG. 7 in that the first transistor SEL1 is provided in the first semiconductor layer 20. The first transistor SEL1 is an NMOS, and therefore can be provided in the first semiconductor layer 20.

Even with the light detection device 1 according to this modification 10 of the first embodiment, the same effects as those of the light detection device 1 according to the first embodiment described above can be obtained.

<Modification 11>
As shown in FIG. 17, the photodetector 1 according to the eleventh modification of the first embodiment differs from the photodetector 1 according to the tenth modification in the routing of the wiring.

Even with the light detection device 1 according to this variation 11 of the first embodiment, the same effects as those of the light detection device 1 according to the first embodiment described above can be obtained.

<Modification 12>
18 shows a photodetector 1 according to a twelfth modification of the first embodiment. The photodetector 1 according to this modification differs from the photodetector 1 according to the second modification of the first embodiment shown in FIG. 8 in that the first transistor SEL1 is provided in the first semiconductor layer 20. The first transistor SEL1 is an NMOS, and therefore can be provided in the first semiconductor layer 20.

Even with the light detection device 1 according to this modification 12 of the first embodiment, the same effects as those of the light detection device 1 according to the first embodiment described above can be obtained.

<Modification 13>
19 shows a photodetector 1 according to a thirteenth modification of the first embodiment. The photodetector 1 according to this modification differs from the photodetector 1 according to the first modification of the first embodiment shown in FIG. 7 in that the amplification transistor AMP is provided in the second semiconductor layer 40.

Even with the light detection device 1 according to this variation 13 of the first embodiment, the same effects as those of the light detection device 1 according to the first embodiment described above can be obtained.

<Modification 14>
As shown in FIG. 20 , the photodetector 1 according to the fourteenth modification of the first embodiment has a stacked structure in which a first semiconductor layer 20, a first wiring layer 30, a first layer 40A of a second semiconductor layer 40, and a second wiring layer 50 are stacked in that order. The first layer 40A is a bulk semiconductor layer rather than a thin film. A fourth surface S4 of the first layer 40A faces the first surface S1 of the first semiconductor layer 20. An amplifying transistor AMP is provided in the first layer 40A. The second layer 40B is a thin film semiconductor layer and is provided in the second wiring layer 50. The first transistor SEL1 and the second transistor SEL2 are provided in the second layer 40B. The photodetector 1 has a through conductor TSV penetrating the first layer 40A.

Even with the light detection device 1 according to this modification 14 of the first embodiment, the same effects as those of the light detection device 1 according to the first embodiment described above can be obtained.

<Modification 15>
21 shows a photodetector 1 according to a fifteenth modification of the first embodiment. The photodetector 1 according to this modification differs from the photodetector 1 according to the fourteenth modification of the first embodiment shown in FIG. 20 in that the second transistor SEL2 is provided on the first layer 40A.

Even with the light detection device 1 according to this modification 15 of the first embodiment, the same effects as those of the light detection device 1 according to the first embodiment described above can be obtained.

<Modification 16>
22 shows a photodetector 1 according to Modification 16 of the first embodiment. The photodetector 1 according to this modification differs from the photodetector 1 according to Modification 7 of the first embodiment shown in FIG. 13 in that the second transistor SEL2 is provided on the second layer 40B and the amplification transistor AMP is provided on the first layer 40A.

Even with the light detection device 1 according to this variation 16 of the first embodiment, the same effects as those of the light detection device 1 according to the first embodiment described above can be obtained.

<Modification 17>
23 shows a photodetector 1 according to Modification 17 of the first embodiment. The photodetector 1 according to this modification differs from the photodetector 1 according to Modification 16 of the first embodiment shown in FIG. 22 in that the second semiconductor layer 40 has a third layer 40C. The third layer 40C is a thin-film semiconductor layer and is provided in the second wiring layer 50. The third layer 40C has a configuration similar to that of the second semiconductor layer 40 described in the first embodiment. The second transistor SEL2 is provided in the third layer 40C.

Even with the light detection device 1 according to this modification 17 of the first embodiment, the same effects as those of the light detection device 1 according to the first embodiment described above can be obtained.

<Modification 18>
24 shows a photodetector 1 according to Modification 18 of the first embodiment. The photodetector 1 according to this modification differs from the photodetector 1 according to Modification 17 of the first embodiment shown in Fig. 23 in that a third layer 40C is provided in the third wiring layer 60. The second transistor SEL2 is provided in the third layer 40C.

Even with the light detection device 1 according to this variation 18 of the first embodiment, the same effects as those of the light detection device 1 according to the first embodiment described above can be obtained.

<Modification 19>
25 shows a photodetector 1 according to a 19th modification of the first embodiment. The photodetector 1 according to this modification differs from the photodetector 1 according to the 2nd modification of the first embodiment shown in FIG. 8 in that the amplification transistor AMP is provided in the second semiconductor layer 40.

Even with the light detection device 1 according to this variation 19 of the first embodiment, the same effects as those of the light detection device 1 according to the first embodiment described above can be obtained.

<Modification 20>
26 shows a photodetector 1 according to Modification 20 of the first embodiment. The photodetector 1 according to this modification differs from the photodetector 1 according to Modification 6 of the first embodiment shown in FIG. 12 in that the amplification transistor AMP is provided in the first layer 40A and the second transistor SEL2 is provided in the second layer 40B.

Even with the light detection device 1 according to this modification 20 of the first embodiment, the same effects as those of the light detection device 1 according to the first embodiment described above can be obtained.

<Modification 21>
Fig. 27 shows a photodetector 1 according to Modification 21 of the first embodiment. The photodetector 1 according to this modification differs from the photodetector 1 according to Modification 20 of the first embodiment shown in Fig. 26 in that the second transistor SEL2 is provided on the first layer 40A.

Even with the light detection device 1 according to this modification 21 of the first embodiment, the same effects as those of the light detection device 1 according to the first embodiment described above can be obtained.

Second Embodiment
28 and 29 , a second embodiment of the present technology will be described below. In this embodiment, instead of the select transistor SEL, the reset transistor RST is configured as a CMOS transistor (CMOS circuit). The CMOS transistor (CMOS circuit) includes a first transistor RST1 and a second transistor RST2 connected in parallel. The first transistor RST1 is an NMOS (n-channel conductivity type MOSFET), and the second transistor RST2 is a PMOS (p-channel conductivity type MOSFET).

As shown in FIG. 28, the fourth terminal d of the reset transistor RST is electrically connected to the charge storage region FD and the gate electrode of the amplifier transistor AMP, and the third terminal c is electrically connected to the power supply line Vdd (or power supply line VBO) and the drain region of the amplifier transistor AMP. The drain region of the first transistor RST1 and the source region of the second transistor RST2 are connected to the third terminal c. The source region of the first transistor RST1 and the drain region of the second transistor RST2 are connected to the fourth terminal d.

<Layer structure of photodetector>
29 , the photodetector 1 has a stacked structure in which, for example, a first semiconductor layer 20 and a first wiring layer 30 are stacked in that order. The photodetector 1 has a second semiconductor layer 40 provided on the first wiring layer 30. The second semiconductor layer 40 is a thin-film semiconductor layer and is different from the bulk first semiconductor layer 20. The first transistor RST1 and the second transistor RST2 are thin-film transistors provided on the second semiconductor layer 40. The second transistor RST2, which is a PMOS, is desirably provided in a semiconductor layer other than the first semiconductor layer 20.

<<Major Effects of the Second Embodiment>>
The main effects of the second embodiment will be described below, but first a brief overview will be provided. Conventionally, the reset transistor RST has been configured with a single transistor. For example, the reset transistor RST has been configured with a single NMOS. The reset transistor RST has the function of initializing the charge storage region FD. When the reset transistor RST is turned on, electrons accumulated in the charge storage region FD are discharged, and the voltage of the charge storage region FD rises to the power supply voltage Vdd. The reset transistor RST then turns off. After the initialization of the charge storage region FD is complete, the transfer transistor TR turns on. When the transfer transistor TR is turned on, signal charges (electrons) generated by the photoelectric conversion element PD are transferred to the charge storage region FD, and the voltage of the charge storage region FD drops. However, the minimum value of the voltage of the charge storage region FD is restricted by the cut-off voltage of the reset transistor RST. Therefore, it is difficult for the minimum value of the voltage of the charge storage region FD to be smaller than the cut-off voltage of the reset transistor RST. Therefore, the voltage range that can be output from the charge storage region FD is restricted by the cut-off voltage of the reset transistor RST, making it difficult to sufficiently lower the lower limit of the voltage input to the gate electrode of the amplification transistor AMP.

Furthermore, the conventional reset transistor RST suffers from the reset field-through phenomenon. The reset field-through phenomenon occurs when the potential of the charge storage region FD drops from the Vdd potential when the reset transistor RST switches from on to off. This limits the voltage range that can be output from the charge storage region FD.

In the photodetector 1 according to the second embodiment, the reset transistor RST is configured as a CMOS transistor, so the same effects as those of the photodetector 1 according to the first embodiment can be obtained. More specifically, the output range of the charge accumulation region FD is less likely to be restricted by the cut-off voltage of the reset transistor RST, so the dynamic range of the voltage range that can be output by the charge accumulation region FD can be prevented from being narrowed.

Furthermore, in the photodetector device 1 according to the second embodiment, the reset transistor RST is configured as a CMOS transistor, so the reset field-through phenomena of the NMOS and PMOS cancel each other out. More specifically, the voltage of the charge storage region FD, which drops due to the reset field-through phenomenon of the NMOS, rises due to the reset field-through phenomenon of the PMOS. As a result, the possible output range of the charge storage region FD is less susceptible to the impact of the reset field-through phenomenon, and the dynamic range of the amplification transistor AMP can be prevented from being narrowed.

<<Modification of the Second Embodiment>>
Modifications of the second embodiment will be described below. In each of the following modifications, the positions of the first transistor RST1 and the second transistor RST2 may be interchanged. In such cases, the routing of the wiring related to the first transistor RST1 and the second transistor RST2 may be appropriately changed according to the equivalent circuit diagram shown in FIG.

<Modification 1>
As shown in FIG. 30 , the photodetector 1 according to the first modification of the second embodiment has a stacked structure in which a first semiconductor layer 20, a first wiring layer 30, a second semiconductor layer 40, and a second wiring layer 50 are stacked in that order. The second semiconductor layer 40 is a bulk semiconductor layer rather than a thin film. The first transistor RST1 and the second transistor RST2 included in the reset transistor RST are provided in the second semiconductor layer 40. The first transistor RST1 and the second transistor RST2 are not thin film transistors but ordinary planar transistors provided in a bulk semiconductor layer. In this modification, the fourth surface S4 faces the first surface S1 of the first semiconductor layer 20. The photodetector 1 has a through conductor TSV penetrating the second semiconductor layer 40.

The light detection device 1 according to this modification 1 of the second embodiment also provides the same effects as the light detection device 1 according to the second embodiment described above.

<Modification 2>
In the photodetector 1 according to the second modification of the second embodiment, the positions of the first transistor RST1 and the second transistor RST2 are not limited to the positions described in the second embodiment ( FIG. 29 ) and the first modification of the second embodiment ( FIG. 30 ). The positions of the first transistor RST1 and the second transistor RST2 may be determined with reference to the positions of the transistors shown in the second modification of the first embodiment ( FIG. 8 ) to the 12 modification of the first embodiment ( FIG. 18 ).

The light detection device 1 according to this modification 2 of the second embodiment also provides the same effects as the light detection device 1 according to the second embodiment described above.

[Third embodiment]
A third embodiment of the present technology will be described below. In this embodiment, the selection transistor SEL according to the first embodiment or any of its modifications and the reset transistor RST according to the second embodiment or any of its modifications are combined.

The photodetector 1 according to the third embodiment also provides the same effects as the photodetector 1 according to the first embodiment and the photodetector 1 according to the second embodiment.

[Fourth embodiment]
A fourth embodiment of the present technology shown in Figures 31 and 32 will be described below. In this embodiment, the photodetector 1 includes an inverter circuit INV that inverts the positive and negative polarities of an input voltage and outputs it. The inverter circuit INV is provided for each of the multiple selection transistors SEL (CMOS transistors). The inverter circuit INV is connected to only one of the gate electrode of the first transistor SEL1 and the gate electrode of the second transistor SEL2. By providing the inverter circuit INV, the voltages simultaneously supplied to the gate electrode of the first transistor SEL1 and the gate electrode of the second transistor SEL2 have opposite positive and negative polarities.

As shown in FIG. 31, the inverter circuit INV includes a third transistor INV3 and a fourth transistor INV4 connected in series. The third transistor INV3 is an NMOS, and the fourth transistor INV4 is a PMOS. The inverter circuit INV inverts the voltage sel input to terminal e and supplies it to the gate electrode of the second transistor SEL2. The voltage sel input to terminal e is input to the gate electrode of the first transistor SEL1 without passing through the inverter circuit INV. Therefore, the first transistor SEL1 and the second transistor SEL2 can be turned on simultaneously, and the first transistor SEL1 and the second transistor SEL2 can be turned off simultaneously.

As shown in FIG. 32, the photodetector 1 has a second semiconductor layer 40 provided on the first wiring layer 30. The second semiconductor layer 40 is a thin-film semiconductor layer. The third transistor INV3 and fourth transistor INV4 of the inverter circuit INV are thin-film transistors provided on the second semiconductor layer 40. The fourth transistor INV4, which is a PMOS, is desirably provided in a semiconductor layer other than the first semiconductor layer 20.

The photodetector 1 according to the fourth embodiment also achieves the same effects as the photodetector 1 according to the first embodiment described above. Note that the inverter circuit INV can be provided in the select transistor SEL according to the first embodiment and its modifications.

<<Modification of Fourth Embodiment>>
Modifications of the fourth embodiment will be described below. In each of the following modifications, the positions of the third transistor INV3 and the fourth transistor INV4 may be interchanged. In such cases, the routing of the wiring related to the third transistor INV3 and the fourth transistor INV4 may be appropriately changed according to the equivalent circuit diagram shown in FIG.

<Modification 1>
In the photodetector 1 according to the first modification of the fourth embodiment, an inverter circuit INV is provided for each of the multiple reset transistors RST. The inverter circuit INV is connected to only one of the gate electrode of the first transistor RST1 and the gate electrode of the second transistor RST2. By providing the inverter circuit INV, the voltages simultaneously supplied to the gate electrodes of the first transistor RST1 and the second transistor RST2 are voltages of opposite polarity.

The photodetector 1 according to this first modification of the fourth embodiment also provides the same effects as the photodetector 1 according to the fourth embodiment described above. Note that the inverter circuit INV can be provided for the reset transistor RST according to the second embodiment and its modifications.

<Modification 2>
In the photodetector 1 according to the second modification of the fourth embodiment, an inverter circuit INV is provided for each of the selection transistor SEL and the reset transistor RST according to the third embodiment.

The photodetector 1 according to this modification 2 of the fourth embodiment also provides the same effects as the photodetector 1 according to the fourth embodiment described above.

<Modification 3>
In the photodetector 1 according to the third modification of the fourth embodiment, the third transistor INV3 and the fourth transistor INV4 may be provided in a bulk semiconductor layer, or may be provided separately in a thin-film semiconductor layer and a bulk semiconductor layer. The positions of the third transistor INV3 and the fourth transistor INV4 may be determined with reference to the positions of the transistors shown in the previously described embodiments and their modifications. The third transistor INV3 may be provided in the first semiconductor layer 20 or the second semiconductor layer 40. Furthermore, in the photodetector 1 according to the third modification of the fourth embodiment, the stacked structure and wiring layout of the photodetector 1 may be similar to the stacked structures shown in the previously described embodiments and their modifications.

The light detection device 1 according to this modification 3 of the fourth embodiment also provides the same effects as the light detection device 1 according to the fourth embodiment described above.

Fifth Embodiment
In the already-described embodiments and their modifications, the transistors provided in the bulk semiconductor layer are planar transistors with a two-dimensional structure, but the present technology is not limited to this. In the photodetector 1 according to the modification 3 of the fourth embodiment, any transistor provided in the bulk semiconductor layer may be a transistor with a three-dimensional structure. A three-dimensional transistor is, for example, a transistor having a structure similar to that of the amplification transistor 34 described in Patent Document 2.

The optical detection device 1 according to the fifth embodiment also provides the same effects as the optical detection device 1 according to the first embodiment described above.

Sixth Embodiment
<1. Application examples to electronic devices>
Next, an electronic device 100 according to a sixth embodiment of the present technology will be described with reference to Fig. 33. The electronic device 100 includes a solid-state imaging device 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. The electronic device 100 is, for example, an electronic device such as a camera, but is not limited thereto. The electronic device 100 also includes the above-described photodetector 1 as the solid-state imaging device 101.

The optical lens (optical system) 102 focuses image light (incident light 106) from the subject onto the imaging surface of the solid-state imaging device 101. This causes signal charge to accumulate within the solid-state imaging device 101 for a certain period of time. The shutter device 103 controls the light irradiation period and light blocking period for the solid-state imaging device 101. The drive circuit 104 supplies drive signals that control the transfer operation of the solid-state imaging device 101 and the shutter operation of the shutter device 103. The drive signals (timing signals) supplied from the drive circuit 104 cause signal transfer from the solid-state imaging device 101. The signal processing circuit 105 performs various signal processing on the signals (pixel signals) output from the solid-state imaging device 101. The processed video signals are stored in a storage medium such as a memory, or output to a monitor.

With this configuration, the electronic device 100 can prevent the dynamic range of the solid-state imaging device 101 from being narrowed, thereby improving the image quality of the video signal.

Note that electronic device 100 is not limited to a camera and may be other electronic devices. For example, it may be an imaging device such as a camera module for a mobile device such as a mobile phone.

Furthermore, the electronic device 100 can be equipped with, as the solid-state imaging device 101, a photodetector 1 according to any of the first to fifth embodiments and their modified examples, or a photodetector 1 according to a combination of at least two of the first to fifth embodiments and their modified examples.

[Other embodiments]
As described above, the present technology has been described by the first to sixth embodiments, but the descriptions and drawings that form part of this disclosure should not be understood to limit the present technology. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

For example, it is possible to combine the technical concepts described in the first through sixth embodiments.

Furthermore, this technology can be applied to all light detection devices, including not only the solid-state imaging devices used as image sensors described above, but also distance measurement sensors that measure distance, also known as ToF (Time of Flight) sensors. Distance measurement sensors emit light toward an object, detect the light that is reflected back from the surface of the object, and calculate the distance to the object based on the time of flight from when the light is emitted until the reflected light is received. The structure of this distance measurement sensor can be the CMOS transistor structure described above.

Furthermore, for example, the materials listed as constituting the above-mentioned components may contain additives, impurities, etc.

As such, it goes without saying that this technology includes various embodiments not described here. Therefore, the technical scope of this technology is defined only by the invention-specific matters set forth in the claims that are appropriate based on the above explanation.

Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present.

The present technology may be configured as follows.
(1)
a photoelectric conversion element;
a charge storage region;
A reset transistor;
an amplifying transistor;
a selection transistor connected in series to the amplification transistor;
Equipped with
At least one of the reset transistor and the selection transistor is configured using a CMOS transistor including a parallel connection of an NMOS transistor and a PMOS transistor.
Light detection device.
(2)
a first semiconductor layer including the photoelectric conversion element;
a second semiconductor layer provided at a position different from the first semiconductor layer in a depth direction;
Equipped with
the first semiconductor layer includes a transistor of a first conductivity type;
When the NMOS transistor and the PMOS transistor included in the CMOS transistor are defined as a first transistor and a second transistor, the second transistor is provided in the second semiconductor layer.
The optical detection device according to (1).
(3)
the first transistor is provided in the first semiconductor layer or the second semiconductor layer;
(2) A photodetector according to (1).
(4)
At least one of the first transistor and the second transistor is a thin film transistor.
The photodetector according to (2) or (3).
(5)
the second semiconductor layer includes a first layer and a second layer provided at a position different from the first layer in a depth direction,
the second transistor is provided in the first layer or the second layer;
The photodetector according to any one of (2) to (5).
(6)
the first semiconductor layer and the second semiconductor layer are bulk semiconductor layers;
The photodetector according to any one of (2) to (6).
(7)
a pair of connection pads for electrically connecting the wirings;
(6) A photodetector according to (6).
(8)
an inverter circuit provided for each of the CMOS transistors, which inverts the polarity of an input voltage and outputs the inverted voltage;
the inverter circuit is connected to only one of the gate electrode of the first transistor and the gate electrode of the second transistor;
The photodetector according to any one of (2) to (7).
(9)
the inverter circuit includes an NMOS transistor and a PMOS transistor;
When the NMOS transistor and the PMOS transistor included in the inverter circuit are a first conductivity type transistor and a second conductivity type transistor, the fourth transistor is provided in the second semiconductor layer.
(8) A photodetector according to (8).
(10)
the third transistor is provided in the first semiconductor layer or the second semiconductor layer;
(9) A photodetector according to (9).
(11)
At least one of the third transistor and the fourth transistor is a thin film transistor.
The photodetector according to (9) or (10).
(12)
the second semiconductor layer includes a first layer and a second layer provided at a position different from the first layer in a depth direction,
the fourth transistor is provided in the first layer or the second layer;
The photodetector according to any one of (9) to (11).
(13)
the first semiconductor layer and the second semiconductor layer are bulk semiconductor layers;
The photodetector according to any one of (9) to (12).
(14)
a pair of connection pads for electrically connecting the wirings;
(13) A photodetector according to (13).
(15)
a light detection device; and an optical system that forms an image of image light from a subject on the light detection device,
The photodetector device
a photoelectric conversion element;
a charge accumulation region capable of accumulating signal charges generated by the photoelectric conversion element;
a reset transistor capable of initializing the charge storage region;
an amplifying transistor that outputs a voltage corresponding to the amount of signal charge accumulated in the charge accumulation region;
a selection transistor connected in series to the amplification transistor;
Equipped with
At least one of the reset transistor and the selection transistor is configured using a CMOS transistor including a parallel connection of an NMOS transistor and a PMOS transistor.
electronic equipment.

The scope of the present technology is not limited to the exemplary embodiments shown and described, but also includes all embodiments that achieve equivalent effects to those intended by the present technology. Furthermore, the scope of the present technology is not limited to the combination of features of the invention defined by the claims, but can be defined by any desired combination of specific features among all the respective disclosed features.

1 Photodetector device 20 First semiconductor layer 21 Photoelectric conversion region 22, FD Charge storage region 34 Amplifying transistor 40 Second semiconductor layer 40A First layer 40B Second layer 100 Electronic device 102 Optical system AMP Amplifying transistor C1, C2 Connection pad INV Inverter circuit INV3 Third transistor INV4 Fourth transistor PD Photoelectric conversion element RST Reset transistor RST1 First transistor RST2 Second transistor sel Voltage SEL Select transistor SEL1 First transistor SEL2 Second transistor

Claims (15)

a photoelectric conversion element;
a charge storage region;
A reset transistor;
an amplifying transistor;
a selection transistor connected in series to the amplification transistor;
Equipped with
At least one of the reset transistor and the selection transistor is configured using a CMOS transistor including a parallel connection of an NMOS transistor and a PMOS transistor.
Light detection device. a first semiconductor layer including the photoelectric conversion element;
a second semiconductor layer provided at a position different from the first semiconductor layer in a depth direction;
Equipped with
the first semiconductor layer includes a transistor of a first conductivity type;
When the NMOS transistor and the PMOS transistor included in the CMOS transistor are defined as a first transistor and a second transistor, the second transistor is provided in the second semiconductor layer.
The photodetector device according to claim 1 . the first transistor is provided in the first semiconductor layer or the second semiconductor layer;
The photodetector device according to claim 2 . At least one of the first transistor and the second transistor is a thin film transistor.
The photodetector device according to claim 2 . the second semiconductor layer includes a first layer and a second layer provided at a position different from the first layer in a depth direction,
the second transistor is provided in the first layer or the second layer;
The photodetector device according to claim 2 . the first semiconductor layer and the second semiconductor layer are bulk semiconductor layers;
The photodetector device according to claim 2 . a pair of connection pads for electrically connecting the wirings;
7. The photodetector according to claim 6. an inverter circuit provided for each of the CMOS transistors, which inverts the polarity of an input voltage and outputs the inverted voltage;
the inverter circuit is connected to only one of the gate electrode of the first transistor and the gate electrode of the second transistor;
The photodetector device according to claim 2 . the inverter circuit includes an NMOS transistor and a PMOS transistor;
When the NMOS transistor and the PMOS transistor included in the inverter circuit are a first conductivity type transistor and a second conductivity type transistor, the fourth transistor is provided in the second semiconductor layer.
The photodetector device according to claim 8 . the third transistor is provided in the first semiconductor layer or the second semiconductor layer;
The photodetector device according to claim 9 . At least one of the third transistor and the fourth transistor is a thin film transistor.
The photodetector device according to claim 9 . the second semiconductor layer includes a first layer and a second layer provided at a position different from the first layer in a depth direction,
the fourth transistor is provided in the first layer or the second layer;
The photodetector device according to claim 9 . the first semiconductor layer and the second semiconductor layer are bulk semiconductor layers;
The photodetector device according to claim 9 . a pair of connection pads for electrically connecting the wirings;
14. The optical detection device according to claim 13. a light detection device; and an optical system that forms an image of image light from a subject on the light detection device,
The photodetector device
a photoelectric conversion element;
a charge accumulation region capable of accumulating signal charges generated by the photoelectric conversion element;
a reset transistor capable of initializing the charge storage region;
an amplifying transistor that outputs a voltage corresponding to the amount of signal charge accumulated in the charge accumulation region;
a selection transistor connected in series to the amplification transistor;
Equipped with
At least one of the reset transistor and the selection transistor is configured using a CMOS transistor including a parallel connection of an NMOS transistor and a PMOS transistor.
electronic equipment.