WO2025153186A1

WO2025153186A1 - Extender phy transceiver architecture

Info

Publication number: WO2025153186A1
Application number: PCT/EP2024/051273
Authority: WO
Inventors: Maxim Kuschnerov; Stefano Calabro
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2024-01-19
Filing date: 2024-01-19
Publication date: 2025-07-24
Anticipated expiration: 2026-07-19

Abstract

This disclosure relates to an extender module, a communication system, and a corresponding method. The extender module proposed in this disclosure comprises: an input interface configured to receive signals from a transmission medium, wherein the received signals are encoded with a FEC code, wherein the FEC code is designed for admitting an iterative decoding process; an extender FEC decoder, configured to apply a first FEC algorithm to partially correct errors within the received signals; and an output interface configured to transmit the partially corrected received signals to a host module. This disclosure also proposes a communication system comprising the extender module and a host module.

Description

EXTENDER PHY TRANSCEIVER ARCHITECTURE

TECHNICAL FIELD

The present disclosure relates to the field of telecommunications and data communication equipment. Developments to reduce power consumption and improve the efficiency of network equipment are presented. Challenges in the power efficiency of networking hardware are addressed, for example in large-scale data center environments housing numerous servers and networking devices. To this end, this disclosure proposes an extender module, a communication system, and corresponding methods.

BACKGROUND

In the realm of telecom and datacom equipment, power consumption is a critical feature that significantly impacts both the spatial footprint and operational costs of data centers. In facilities with a substantial number of servers, the power consumption of networking equipment occupies a considerable portion of the overall power budget. Traditional methods to reduce power consumption have included advancing complementary metal-oxide semiconductor (CMOS) process nodes for application specific integrated circuits (ASICs) and increasing symbol rates for analog front ends.

One aspect of current networking equipment is the uniformity of fan speed across all pluggable modules in a device, wherein the fans are used for cooling the modules. Regardless of individual power consumption levels of the modules, the fan speed is set to accommodate the module with the highest power consumption, leading to inefficiencies. Since fan power consumption increases cubically with speed, this approach results in significant energy usage. Consequently, optimizing power consumption is a high priority in the design and operation of these systems.

SUMMARY

In view of the above-mentioned challenges, the present disclosure provides a solution that significantly lowers power consumption while simultaneously elevating the efficiency of network equipment within communication systems. A solution is desired that facilitates low-power implementations across diverse interface types, thereby contributing to more energyefficient network operations. One objective of this disclosure is to enable Ethernet scenarios with multiple reach capabilities, while utilizing the same host Forward Error Correction (FEC). Another objective is to provide a versatile architecture capable of accommodating various latency requirements.

These and other objectives are achieved by the solutions of this disclosure as provided in the independent claims. Advantageous implementations are further defined in the dependent claims.

A first aspect of this disclosure provides an extender module comprising: an input interface configured to receive signals from a transmission medium, wherein the received signals are encoded with a FEC code, wherein the FEC code is designed for admitting an iterative decoding process; an extender FEC decoder, configured to apply a first FEC algorithm to partially correct errors within the received signals; and an output interface configured to transmit the partially corrected received signals to a host module.

The extender module enables multi-reach Ethernet scenarios based on the same host FEC with optimized power consumption. In an implementation form of the first aspect, the extender module is further configured to support at least one of the following signal detection schemes: intensity modulation direct detection (IMDD); coherent detection; or semi-coherent detection. Accordingly, the extender module can be applied to different transceiver types, and to any modulation and detection scheme.

In an implementation form of the first aspect, the extender module is further configured to perform one or more signal processing steps on the received signals, wherein the one or more signal processing steps comprise one or more of: clock recovery, signal equalizing, and carrier recovery. The level of supplemental processing applied by the extender module is adjustable and may include optional components.

In an implementation form of the first aspect, the extender module is further configured to perform a bulk chromatic dispersion (CD) compensation in addition to the one or more signal processing steps. The implementation of bulk CD compensation can be tailored or omitted as required by the network's demands, e.g., to enable longer-reach user cases.

In an implementation form of the first aspect, the extender FEC decoder is adapted to perform a soft decision FEC decoding. Optionally, the implementation of Soft Decision-FEC (SD-FEC) decoding can be tailored or omitted as required by the network's demands, e.g., to enable longer-reach user cases.

In an implementation form of the first aspect, the extender module is implemented within a pluggable optics, an on-board optics, or a near-package optics. Various options for designing a switch/router system with optical interfaces, such as pluggable optics, on-board optics, or near-package optics are possible.

A second aspect of this disclosure provides a communication system comprising the extender module of the first aspect or any of its implementation forms, and a host module. It is possible to include a strong FEC encoder that allows multi-step decoding, for example, iterative decoding.

Implementation forms of the receiver device of the second aspect may correspond to the implementation forms of the extender module of the first aspect described above. The receiver device of the second aspect and its implementation forms achieve the same advantages and effects as described above for the extender module of the first aspect and its implementation forms.

In an implementation form of the second aspect, the host module comprises: a FEC encoder, configured to encode outputting data frames with the FEC code; a FEC decoder, configured to decode incoming data frames that are encoded with the FEC code; and a transceiver, configured to receive the partially corrected signals from the extender module, wherein the FEC decoder is configured to apply a second FEC algorithm to correct errors within the partially corrected signals, so as to complete the iterative decoding process. Optionally, each of the host module and the extender module is designed to decode the FEC partially. As a result, the FEC is decoded in an iterative decoding process. It may be understood that the first and second FEC algorithms collectively constitute an iterative FEC decoding algorithm, enhancing error correction through successive processing stages.

In an implementation form of the second aspect, the FEC decoder of the host module is adapted to perform a hard decision FEC decoding. The interaction between the extender module and the host module can utilize either hard decision metrics or soft information parameters. Each method requires appropriate encoding to facilitate chip-to-chip electrical transmission. For instance, preliminary hard decisions made in the extender module may be remapped to conform to the original modulation scheme. This ensures that the signal integrity is maintained through the transmission process between chips. In an implementation form of the second aspect, the communication system further comprises an optical and electrical frontend operatively coupled to the host module, wherein the optical and electrical front end is configured to: receive electrical signals from the host module; receive optical signals from an optical medium; and convert between the optical signals and the electrical signals.

In an implementation form of the second aspect, the optical medium is a duplex fiber, or a parallel fiber.

In an implementation form of the second aspect, the communication system further comprises a gearbox operatively coupled between the host module and the optical and electrical front end, wherein the gearbox is configured to match data transmission rates between the host module and the optical and electrical front end. Optionally, the communication system can be provided with or without a gearbox.

In an implementation form of the second aspect, the gearbox is configured to multiplex a first number of electrical lanes from the host chip into a second number of electrical lanes to the optical and electrical front end, wherein the first number is larger than the second number. Possibly, the number of electrical lanes driving the optical front-end is reduced through multiplexing. This can reduce the cost, size and power of the optical subassembly by using less components with higher bandwidth (e.g., 1 instead of 2 lasers). Gearbox can also be implemented differently, e.g., as an analog electrical mux or optical multiplexer.

In an implementation form of the second aspect, the extender module is further configured to demultiplex the second number of electrical lanes from the optical and electrical front end to the first number of electrical lanes to the host module.

A third aspect of this disclosure provides a method for an extender module, comprising: receiving signals from a transmission medium, wherein the received signals are encoded with a FEC code, wherein the FEC code is designed for admitting an iterative decoding process; applying a first FEC algorithm to partially correct errors within the received signals, wherein the first FEC algorithm comprises an iterative FEC decoding algorithm; and transmitting the partially corrected received signals to a host module.

Implementation forms of the method of the third aspect may correspond to the implementation forms of the extender module of the first aspect described above. The method of the third aspect and its implementation forms achieve the same advantages and effects as described above for the extender module of the first aspect and its implementation forms.

It has to be noted that all modules, elements, units, and means described in the present application could be implemented in the software or hardware elements or any kind of combination thereof. All steps that are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective extender module is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that extender module that performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements or any kind of combination thereof. BRIEF DESCRIPTION OF DRAWINGS

The above-described aspects and implementation forms will be explained in the following description of specific embodiments in relation to the enclosed drawings, in which:

FIG. 1 shows an extender module according to an embodiment of the disclosure.

FIG. 2 shows exemplary Ethernet FEC architectures.

FIG. 3 shows an optics architecture structure according to an embodiment of the disclosure.

FIG. 4 shows an optical interface type according to an embodiment of the disclosure.

FIG. 5 shows a communication system according to an embodiment of this disclosure.

FIG. 6 shows two exemplary communication system architectures according to an embodiment of the disclosure.

FIG. 7 shows two generalized optics according to an embodiment of the disclosure.

FIG. 8 shows a method for generating an eye diagram according to an embodiment of the disclosure.

DETAILED DESCRIPTION OF EMBODIMENTS

Illustrative embodiments of an extender module, a communication system, and a corresponding method are described with reference to the figures. Although this description provides a detailed example of possible implementations, it should be noted that the details are intended to be exemplary and in no way limit the scope of the application.

Moreover, an embodiment/example may refer to other embodiments/examples. For example, any description including but not limited to terminology, element, process, explanation, and/or technical advantage mentioned in one embodiment/example is applicable to the other embodiments/examples. The same elements are labeled with the same reference signs and may function similarly or likewise.

FIG. 1 shows an extender module 100 according to this disclosure. The extender module 100 may comprise a processor or processing circuitry (not shown) configured to perform, conduct, or initiate the various operations of the extender module 100 described herein. The processing circuitry may comprise hardware and/or the processing circuitry may be controlled by software. The hardware may comprise analog circuitry digital circuitry, or both analog and digital circuitry. The digital circuitry may comprise components such as application-specific integrated circuits (ASICs), field-programmable arrays (FPGAs), digital signal processors (DSPs), or multi-purpose processors. The extender module 100 may further comprise memory circuitry, which stores one or more instructions) that can be executed by the processor or by the processing circuitry, in particular under the control of the software. For instance, the memory circuitry may comprise a non-transitory storage medium storing executable software code which, when executed by the processor or the processing circuitry, causes the various operations of the extender module 100 to be performed. In one embodiment, the processing circuitry comprises one or more processors and a non-transitory memory connected to the one or more processors. The non-transitory memory may carry executable program code which, when executed by the one or more processors, causes the extender module 100 to perform, conduct, or initiate the operations or methods described herein. In particular, the extender module 100 comprises an input interface 101 configured to receive signals from a transmission medium, wherein the received signals are encoded with a FEC code, wherein the FEC code is designed for admitting an iterative decoding process. The extender module 100 further comprises an extender FEC decoder 102, configured to apply a first FEC algorithm to partially correct errors within the received signals; and an output interface 103 configured to transmit the partially corrected received signals to a host module 200.

This disclosure proposes an extender module to enable multi-reach Ethernet scenarios based on the same host FEC with optimized power consumption.

The state of the art in datacom layer 0 reveals various architectural configurations, with different approaches used for electrical signaling rates. For instance, for rates up to 25Gb/s, binary signaling was common, employing gearboxes, Clock Data Recovery (CDR) units, or direct drives into optical front ends. Above 50Gb/s, PAM4 modulation became standard, typically interfacing with a Digital Signal Processing (DSP) modem chip for advanced signal processing and optional error correction (FEC). At lOOGb/s per lane and beyond, full-resolution Digital-to- Analog and Analog-to-Digital Converters (DAC/ADC) were employed, along with integrated DSP capabilities.

Within the context of Ethernet applications, the standard Ethernet FEC is commonly used, with KR4 for Non-Retum to Zero (NRZ) signaling at lOGb/s and 25Gb/s, and KP4 for Pulse Amplitude Modulation 4-level (PAM4) signaling at higher rates. In scenarios involving more challenging reach classes, an option is to define an additional mode within the Physical Layer (PHY). This includes the use of an inner FEC in a concatenated approach, such as Hamming FEC with soft decoding, where the host FEC is not terminated. Typical examples of this approach are found in 800G FR4 and 800G LR4 (IMDD). Another approach is the standalone FEC, examples being CFEC or OFEC, wherein the host FEC is terminated, as seen in 400ZR and 800ZR (coherent optical). The above-mentioned Ethernet FEC architectures are illustrated in FIG. 2.

The current Ethernet FEC architecture demonstrates certain limitations, for example a separation of use case domains and an inability to cover a wide range of reach classes with the same Serializer/Deserializer (SerDes) for optical transceivers without a dedicated DSP ASIC. For instance, in the case of 200G/lane PAM4, two distinct modes with different FECs and line rates would need support to cover reach classes from 100m-500m (KP4, 106Gbaud) and 2km-10km (KP4+Hamming FEC, 113Gbaud). Supporting different symbol rates for chip Inputs/Outputs (IOS) necessitates various voltage-controlled oscillators, adding complexity to the board design surrounding the host chip.

To mitigate chip and board design complexities, typically only a single FEC mode is supported in a standard switch Integrated Circuit (IC). This known approach, however, could limit the versatility of the host SerDes in the market. It may also hinder interoperability in systems using a dedicated PHY DSP in the optical transceiver that operates on a different FEC mode. Moreover, the architecture typically limits flexibility in FEC choice due to IEEE standards, leading to non-interoperable definitions. Transmitter-sided PHY processing, while limited in digital logic, consumes significant analog power for SerDes IOs and DAC, while receiver-sided DSP involves more complex equalization and FEC decoding.

These limitations in the prior art highlight the need for an innovative approach that addresses power efficiency, flexibility, and interoperability in the design and operation of telecom and datacom equipment.

Embodiments of the present disclosure thus propose to include a strong FEC encoder in the host module and thus be able to omit Tx DSP PHY. This FEC must allow multi-step decoding, for example, iterative decoding. In particular, this disclosure proposes an approach to decode the (power-intensive) FEC partially in a dedicated Rx PHY which also includes strong equalization. This disclosure can be applied to different transceiver types. For instance, the extender module 100 can support at least one of the following signal detection schemes: IMDD, coherent detection, semi-coherent detection, and other receiver types. In IMDD, the intensity of the light source is modulated to represent the data being transmitted. Coherent detection involves modulating not just the intensity but also the phase and polarization of the light. Semi-coherent detection is somewhat of a middle ground between IMDD and fully coherent detection. In semi-coherent detection, some aspects of the coherent technique are used, like phase or frequency modulation, but the system is not as complex as a fully coherent system.

To cover all major reach scenarios, the FEC code used for encoding needs to be strong and allow for iterative decoding. Optionally, the FEC code proposed in this disclosure may comprise one of the following types: a concatenated code, a low- density parity-check code, or a turbo product code.

According to an embodiment of this disclosure, the extender module 100 is configured to perform one or more signal processing steps on the received signals, wherein the one or more signal processing steps comprise one or more of: clock recovery, signal equalizing, and carrier recovery.

It should be noted that the amount of additional processing in the extender module 100 can be varied. Optionally, the extender module 100 may be further configured to perform a bulk CD compensation in addition to the one or more signal processing steps.

FIG. 3 shows a coherent optics architecture according to an embodiment of this disclosure. This figure illustrates two distinct signal processing paths for data transmission and reception within a network.

Path 1, delineated in the dashed lines, shows the processing steps on the “Host ASIC”, e.g., the host module 200, which possesses basic functionality to cover a defined set of short-reach use cases.

Path 2, delineated in the solid lines, represents the case where the “Rx DSP ASIC”, i.e., the extender module 100, is used. It can be seen that when the extender module 100 is used, the modem on the receiver side of the host can be bypassed, e.g., the processing steps for signal equalization and carrier recovery, can be omitted. The Rx modem can be powered down to save power.

It should be noted that the level of supplemental processing applied by the extender module 100 is adjustable and includes optional components. Specifically, the implementation of Bulk CD compensation and/or SD-FEC decoding can be tailored or omitted as required by the network's demands, e.g., to enable longer-reach user cases. Optionally, the extender FEC decoder 102 may be adapted to perform a soft decision FEC decoding.

Interfacing between the extender module 100 and host module 200 can be based on hard decisions or soft information, which would both need to be accordingly encoded for the chip to chip electrical transmission.

According to an embodiment of this disclosure, the extender module 100 is implemented within a pluggable optics, an onboard optics, or a near-package optics.

Embodiments of this disclosure support the implementation of pluggable optics by relaxing the power requirements of the pluggable modules which need to support longer reaches (XPO), as shown in FIG. 4. In this disclosure, XPO is referred to as extender pluggable optics, which is a continuation of the linear drive pluggable optics (LPO), near package optics (NPO), and co-packaged optics (CPO) terminology. FIG. 4 shows various optical interface types supported by the extender module 100. XPO and LPO modules can both support duplex and parallel fibers.

According to an embodiment of this disclosure, onboard optics may also be employed, where the extender module 100 may be put on a printed circuit board (PCB). In this application scenario, the power consumption and cooling are distributed from a centralized host switch to the whole board and thus do not burden the host switch with long-reach use cases.

FIG. 5 shows a communication system 10 according to an embodiment of this disclosure. The communication system 10 comprises an extender module 100 and a host module 200. In particular, the extender module 100 is the extender module shown in FIG. 1.

In particular, the host module 200 comprises a FEC encoder, configured to encode outputting data frames with the FEC code; a FEC decoder, configured to decode incoming data frames that are encoded with the FEC code; and a transceiver, configured to receive the partially corrected signals from the extender module 100. The FEC decoder is configured to apply a second FEC algorithm to correct errors within the partially corrected signals, so as to complete the iterative decoding process.

It may be understood that the first and second FEC algorithms collectively constitute an iterative FEC decoding algorithm, enhancing error correction through successive processing stages.

According to an embodiment of this disclosure, the FEC decoder of the host module 200 is adapted to perform a hard decision FEC decoding.

FIG. 6 shows exemplary architectures according to embodiments of this disclosure. In particular, FIG. 6(a) shows the proposed communication system 10 which includes the extender module 100. This structure can deliver high performance to enable a long-distance user case.

According to the present disclosure it is proposed to include a strong FEC encoder in the host module 200 to omit Tx DSP PHY. As discussed in the previous embodiments, this FEC must allow multi-step decoding, for example, iterative decoding. The extender module 100 is designed to decode the FEC partially using the extender FEC encoder. In this disclosure, the return path is protected using the same FEC, but with additional decoding iterations.

FIG. 6(a) shows an application scenario where the extender module use is optional and can be omitted for short reaches. In this example, for short-distance user cases, by using a strong FEC encoder, the host module can achieve low latency communication without deploying the extender module.

Table 1 shows an architecture comparison between the conventional solution and the solution proposed in embodiments of this disclosure. It can be seen that this solution enables power saving while maintaining a flexible architecture design with a single host rate and a potentially single FEC. It supports various use cases from 100m to 2,000+ km with a single switch ASIC, single FEC, and the lowest overall latency solution.

Table 1

According to an embodiment of this disclosure, the communication system 10 further comprises an optical and electrical front end operatively coupled to the host module 200. The optical and electrical front end is configured to: receive electrical signals from the host module 200: receive optical signals from an optical medium; and convert between the optical signals and the electrical signals. Optionally, the optical medium is a duplex fiber, or a parallel fiber.

FIG. 7 shows application scenarios with or without a gearbox, according to two embodiments of this disclosure. FIG. 7(a) shows a serial option, where the number of electrical lanes at the host is identical to the number of lanes driving the optical front end. This resembles the state-of-art architectures for LPO, NPO, and CPO.

FIG. 7(b) shows a multiplexed option, where the number of electrical lanes driving the optical front end is reduced through multiplexing. This can reduce the cost, size, and power of the optical subassembly by using fewer components with higher bandwidth (e.g. 1 instead of 2 lasers). Gearbox can be implemented differently, e.g. as an analog electrical mux or optical multiplexer.

According to an embodiment of this disclosure, the communication system 10 further comprises a gearbox operatively coupled between the host module 200 and the optical and electrical front end. The gearbox is configured to match data transmission rates between the host module 200 and the optical and electrical front end.

Optionally, the gearbox is configured to multiplex a first number of electrical lanes from the host chip into a second number of electrical lanes to the optical and electrical front end, wherein the first number is larger than the second number.

Accordingly, the extender module 100 is further configured to demultiplex the second number of electrical lanes from the optical and electrical front end to the first number of electrical lanes to the host module 200.

The teaching of the present disclosure can be applied to Ethernet switches, optical transport network (OTN) switches, Internet Protocol (IP) routers, or optical transceivers. That is, the host module may be implemented within Ethernet switches, optical transport network (OTN) switches, Internet Protocol (IP) routers, or optical transceivers. FIG. 8 shows a method 800 according to this disclosure. The method 800 may be performed by the extender module 100, as shown in FIG. 1 or FIG. 5.

The method 800 comprises a step 801 of receiving signals from a transmission medium, wherein the received signals are encoded with a FEC code, wherein the FEC code is designed for admitting an iterative decoding process. The method 800 further comprises a step 802 of applying a first FEC algorithm to partially correct errors within the received signals; and a step 803 of transmitting the partially corrected received signals to a host module 200. In a particular example, the host module 200 may be the host module shown in FIG. 1 or FIG. 5.

To summarize, embodiments of the present disclosure introduce a refined Ethernet host architecture that employs a singular mode/FEC capable of addressing all principal use cases. This design facilitates a low-power execution for a variety of interface types, utilizing extender receiver DSP PHYs tailored to specific scenarios. Additionally, this disclosure further enhances the system by integrating gear-boxed transmitters equipped with sophisticated end-to-end equalization and error correction capabilities. The use of an analog transmitter gearbox to consolidate lane numbers does not impede the application of intensive equalization and error correction, marking a significant improvement over the current KP4-based Ethernet architectures.

The present disclosure has been described in conjunction with various embodiments as examples as well as implementations. However, other variations can be understood and effected by those persons skilled in the art and practicing the claimed matter, from the studies of the drawings, this disclosure, and the independent claims. In the claims as well as in the description the word “comprising” does not exclude other elements or steps and the indefinite article “a” or “an” does not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in the mutual different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.

Claims

1. An extender module (100) comprising: an input interface (101) configured to receive signals from a transmission medium, wherein the received signals are encoded with a Forward Error Correction, FEC, code, wherein the FEC code is designed for admitting an iterative decoding process; an extender FEC decoder (102), configured to apply a first FEC algorithm to partially correct errors within the received signals; and an output interface (103) configured to transmit the partially corrected received signals to a host module (200).

2. The extender module (100) according to claim 1, configured to: support at least one of the following signal detection schemes: intensity modulation direct detection; coherent detection; or semi-coherent detection.

3. The extender module (100) according to claim 1 or 2, wherein the FEC code comprises one of the following types: a concatenated code, a low-density parity-check code, or a turbo product code.

4. The extender module (100) according to one of the claims 1 to 3, further configured to: perform one or more signal processing steps on the received signals, wherein the one or more signal processing steps comprise one or more of: clock recovery, signal equalizing or carrier recovery.

5. The extender module (100) according to claim 4, further configured to: perform a bulk chromatic dispersion compensation in addition to the one or more signal processing steps.

6. The extender module (100) according to one of the claims 1 to 5, wherein the extender FEC decoder (102) is adapted to perform a soft decision FEC decoding.

7. The extender module (100) according to one of the claims 1 to 6, wherein the extender module (100) is implemented within a pluggable optics, an on-board optics, or a near-package optics.

8. A communication system (10) comprising an extender module (100) according to one of the claims 1 to 7, and a host module (200).

9. A communication system (10) according to claim 8, wherein the host module (200) comprises: a FEC encoder, configured to encode outputting data frames with the FEC code; a FEC decoder, configured to decode incoming data frames that are encoded with the FEC code; and a transceiver, configured to receive the partially corrected signals from the extender module (100), wherein the FEC decoder is configured to apply a second FEC algorithm to correct errors within the partially corrected signals, so as to complete the iterative decoding process.

10. The communication system (10) according to claim 9, wherein the FEC decoder of the host module (200) is adapted to perform a hard decision FEC decoding.

11. The communication system (10) according to one of the claims 8 to 10, further comprising: an optical and electrical frontend operatively coupled to the host module (200), wherein the optical and electrical front end is configured to: receive electrical signals from the host module (200); receive optical signals from an optical medium; and convert between the optical signals and the electrical signals.

12. The communication system (10) according to claim 11 , wherein the optical medium is a duplex fiber, or a parallel fiber.

13. The communication system (10) according to claim 11 or 12, further comprising: a gearbox operatively coupled between the host module (200) and the optical and electrical front end, wherein the gearbox is configured to: match data transmission rates between the host module (200) and the optical and electrical front end.

14. The communication system (10) according to claim 13, wherein the gearbox is configured to: multiplex a first number of electrical lanes from the host chip into a second number of electrical lanes to the optical and electrical front end, wherein the first number is larger than the second number.

15. The communication system (10) according to claim 14, wherein the extender module (100) is further configured to: demultiplex the second number of electrical lanes from the optical and electrical front end to the first number of electrical lanes to the host module (200).

16. A method (800) for an extender module (100), comprising: receiving (801) signals from a transmission medium, wherein the received signals are encoded with a Forward Error Correction, FEC, code, wherein the FEC code is designed for admitting an iterative decoding process; applying (802) a first FEC algorithm to partially correct errors within the received signals; and transmitting (803) the partially corrected received signals to a host module (200).