WO2025152421A1 - Preparation method for stacked transistor, and stacked transistor, device and apparatus - Google Patents

Abstract

Provided in the present disclosure are a preparation method for a stacked transistor, and a stacked transistor, a device and an apparatus. The method comprises: forming on a substrate a first active structure, a first intermediate layer and a second active structure, which are sequentially stacked; forming a first transistor on the basis of the first active structure; flipping a wafer and removing the substrate, so as to expose the second active structure; forming a second transistor on the basis of the second active structure, wherein the first transistor and the second transistor are self-aligned in a direction perpendicular to a channel; and forming an isolation dielectric structure on the basis of the first intermediate layer, wherein the material of the isolation dielectric structure is different from the material of the first intermediate layer, and the isolation structure is used for isolating the first active structure from the second active structure.

Description

Method for preparing stacked transistor, stacked transistor, device and equipment

CROSS-REFERENCE TO RELATED APPLICATIONS

The present disclosure is based on Chinese patent application with application number 202410057642.9, application date January 15, 2024, and invention name “Method for preparing stacked transistors, stacked transistors, devices and equipment” and Chinese patent application with application number 202410130550.9, application date January 30, 2024, and invention name “Method for preparing stacked transistors, stacked transistors, devices and equipment”, and claims the priority of the Chinese patent application. The entire contents of the Chinese patent application are hereby introduced into the present disclosure as a reference.

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a stacked transistor, a stacked transistor, a device and an apparatus.

Background Art

As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors integrate two or more layers of transistors in a vertical space to further increase the integration density of transistors, becoming one of the important technologies to continue the miniaturization of integrated circuit size.

When using the traditional monolithic stacking solution to prepare stacked transistors, there are the following technical difficulties: it is difficult to achieve electrical isolation of the active area.

Summary of the invention

The present disclosure provides a method for preparing a stacked transistor, a stacked transistor, a device and an apparatus.

The first aspect of the present disclosure provides a method for preparing a stacked transistor. The method includes: forming a first active structure, a first intermediate layer, and a second active structure stacked in sequence on a substrate; forming a first transistor based on the first active structure; flipping the wafer and removing the substrate to expose the second active structure; forming a second transistor based on the second active structure; the first transistor and the second transistor are self-aligned in a direction perpendicular to the channel; forming an isolation dielectric structure based on the first intermediate layer; the material of the isolation dielectric structure is different from the material of the first intermediate layer; the isolation structure is used to isolate the first active structure from the second active structure.

The second aspect of the present disclosure provides a stacked transistor. The stacked transistor includes: a first transistor; a second transistor, the first transistor and the second transistor are self-aligned in a direction perpendicular to the channel; an isolation dielectric structure, the isolation dielectric structure is located between a first active structure of the first transistor and a second active structure of the second transistor, and the isolation dielectric structure is used to isolate the first active structure from the second active structure.

A third aspect of the present disclosure provides a semiconductor device, comprising: a stacked transistor as provided in the second aspect.

A fourth aspect of the present disclosure provides an electronic device, which includes: a circuit board and the semiconductor device provided in the third aspect, wherein the semiconductor device is arranged on the circuit board.

In the present disclosure, by providing an isolation dielectric structure between the first active structure and the second active structure, electrical isolation between the first active structure and the second active structure can be achieved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure.

FIG. 1 is a schematic diagram of a first implementation flow of a method for preparing a stacked transistor provided according to an embodiment of the present disclosure.

FIG. 2 is a schematic diagram of a first structure of a stacked transistor provided according to an embodiment of the present disclosure.

3A to 3F are schematic diagrams of a first manufacturing process of a stacked transistor provided according to an embodiment of the present disclosure.

FIG. 4 is a schematic diagram of a second structure of a stacked transistor provided according to an embodiment of the present disclosure.

5A to 5C are schematic diagrams of a second manufacturing process of a stacked transistor provided according to an embodiment of the present disclosure.

FIG. 6 is a schematic diagram of a second implementation flow of a method for preparing a stacked transistor according to an embodiment of the present disclosure.

FIG. 7 is a schematic diagram of a third structure of a stacked transistor provided according to an embodiment of the present disclosure.

8A to 8F are schematic diagrams of a third manufacturing process of a stacked transistor provided according to an embodiment of the present disclosure.

9A to 9D are schematic diagrams of a fourth manufacturing process of a stacked transistor provided according to an embodiment of the present disclosure.

Description of Reference Numerals

stacked transistor 10; first transistor 11; first active structure 111; first gate structure 112; first source-drain structure 113; first Source-drain metal 114; first interlayer dielectric layer 115; first gate dielectric layer 116; first spacer 117; first metal interconnection layer 118; second transistor 12; second active structure 121; second gate structure 122; second source-drain structure 123; second source-drain metal 124; second interlayer dielectric layer 125; second gate dielectric layer 126; second spacer 127; second metal interconnection layer 128; isolation dielectric structure 13; shallow trench isolation layer 14; first insulating layer 15; carrier wafer 16; substrate 21; bottom substrate 211; middle sacrificial layer 212; top substrate 213; Fin-shaped structure 22; first fin-shaped structure 221; second fin-shaped structure 222; first intermediate layer 223; shallow trench isolation structure 23; second shallow trench isolation structure 231; first shallow trench isolation structure 232; third shallow trench isolation structure 233; fourth shallow trench isolation structure 234; first dummy gate structure 241; second dummy gate structure 242; columnar structure 25; first part 251 of columnar structure; second part 252 of columnar structure; first inner sidewall 26; first groove 27; first filling structure 28; first semiconductor material layer 31; second semiconductor material layer 32; third semiconductor material layer 33.

DETAILED DESCRIPTION

Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the embodiments of the present disclosure.

The terms used in the embodiments of the present disclosure are only for the purpose of describing specific embodiments, and are not intended to limit the embodiments of the present disclosure. The singular forms of "a", "said", and "the" used in the present disclosure are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and/or" used in this article refers to and includes any or all possible combinations of one or more associated listed items.

As Moore's Law continues to deepen, after the technology node of gate-all-around FET (GAA), continuing to promote transistor size miniaturization is a hot issue in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve transistor integration density and circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.

In one embodiment, there are two schemes for the preparation process of stacked transistors, the first is a monolithic stacking scheme, and the second is a sequential scheme.

The first solution is to make N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) on the same substrate without using wafer bonding technology. This determines that the transistors on the same layer must be of the same type, namely NFET or PFET. In addition, the upper and lower layers of transistors must be strictly in the same plane space without alignment deviation. The advantage of this solution is that it has a better integration density. The disadvantages of this solution include the following two points: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and it must rely on two layers of transistors to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, which has poor design flexibility.

The second solution is based on wafer bonding and layer-by-layer processing. The upper transistor is prepared by bonding a wafer on top of the already fabricated lower transistor, and the two transistors are stacked vertically. However, this solution requires strict temperature control during the thermal process of processing the upper transistor to avoid affecting the lower transistor and interconnects. The advantage of this solution is that thanks to wafer bonding, the device structure, channel crystal orientation and even channel material used by the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance. This solution currently has the following technical challenges: (1) Preparation of high-quality upper transistor active layer; (2) Thinning and defect control of the upper bonded wafer; (3) There is an alignment error between the upper and lower transistors, which requires extremely high lithography accuracy.

Among them, when using monolithic stacked transistors, the active areas of the upper transistor and the lower transistor need to be electrically isolated. The current methods include: (1) using a silicon-on-insulator (SOI) substrate and utilizing a buried oxide (BOX) layer to form a natural electrical isolation layer; (2) forming an electrical isolation layer by ion implantation of P-type ions, N-type ions or oxygen ions.

However, the cost of SOI substrates is very high, and it is difficult to obtain SOI substrates with suitable thickness of BOX layer and device layer; the process control of ion implantation is difficult, and the diffusion effect of implanted ions will have a great impact on the thermal budget of subsequent processes, and the implanted ions will also cause damage to the device structure.

In order to solve the above technical problems, an embodiment of the present disclosure provides a method for preparing a stacked transistor to achieve electrical isolation between a first active structure and a second active structure.

In some embodiments, the stacked transistor may be applied to semiconductor devices such as memory and processor.

In one embodiment, the stacked transistor may include at least two transistors, for example, a first transistor and a second transistor. The first transistor and the second transistor are arranged back to back. A first active structure in the first transistor and a second active structure in the second transistor are formed by the same process, and the first active structure and the second active structure are self-aligned.

In some embodiments, the first transistor and the second transistor in the stacked transistor may be transistors of the same type, such as any one of the following: a fin field effect transistor, a nanosheet field effect transistor, a planar transistor, and a vertical field effect transistor.

FIG. 1 is a schematic diagram of a first implementation flow of a method for preparing a stacked transistor according to an embodiment of the present disclosure. Referring to FIG. 1 , The method for preparing the stacked transistor may include:

Step S101 , forming a first active structure, a first intermediate layer, and a second active structure stacked in sequence on a substrate.

It can be understood that a substrate is provided, and then the first active structure, the first intermediate layer and the second active structure are etched on the substrate through the same process, wherein the second intermediate layer is located between the first active structure and the second active structure.

In some embodiments, the first active structure, the first intermediate layer, and the second active structure may be made of the same material, such as silicon (Si).

In some embodiments, when the first active structure, the first intermediate layer, and the second active structure are made of the same material, and the stacked transistor is a fin field effect transistor, the above step S101 may include: etching the substrate to form a plurality of fin structures; the fin structure is divided into three parts from top to bottom, the first part is the first active structure, the second part is the first intermediate layer, and the third part is the second active structure.

In some embodiments, when the first active structure, the first intermediate layer, and the second active structure are made of the same material, and the stacked transistor is a full-surround gate transistor, the step S101 may include: etching the substrate to form a columnar structure.

In some embodiments, the substrate is formed of alternately deposited silicon layers and silicon germanium layers; the columnar structure is divided into three parts from top to bottom, the first part is a first active structure, the second part is a first intermediate layer, and the third part is a second active structure.

In some embodiments, when the first active structure, the first intermediate layer, and the second active structure are made of the same material, and the stacked transistor is a planar transistor, the above step S101 may include: etching the substrate to form a block structure; the block structure is divided into three parts from top to bottom, the first part is the first active structure, the second part is the first intermediate layer, and the third part is the second active structure.

In some embodiments, since the stacked transistor includes two transistors (i.e., a first transistor and a second transistor), and the first active structure of the first transistor and the second active structure of the second transistor are formed by the same etching process, a larger etching depth can be used when etching the substrate. The height of the fin-shaped structure (which may also be a columnar structure or a block structure) obtained by etching can be greater than 100 nanometers (nm). It should be noted that the height of the fin-shaped structure can be set according to actual conditions, and the embodiments of the present disclosure are not limited to this.

In some embodiments, the substrate may include a top substrate, an intermediate sacrificial layer, and a bottom substrate stacked in sequence, wherein the top substrate and the bottom substrate are made of the same material, such as silicon material, and the intermediate sacrificial layer is made of a material different from the bottom substrate and the top substrate. The first active structure is formed by etching the bottom substrate, the second active structure is formed by etching the bottom substrate, and the first intermediate layer is formed by etching the intermediate sacrificial layer.

In some embodiments, when the substrate includes a top substrate, an intermediate sacrificial layer, and a bottom substrate stacked in sequence, the preparation process of the substrate may include: epitaxially growing a layer of sacrificial layer material on the original substrate (i.e., the bottom substrate) to form an intermediate sacrificial layer; then, epitaxially growing the same semiconductor material as the bottom substrate on top of the intermediate sacrificial layer to form a top substrate. The substrate formed by the above preparation method includes a top substrate, an intermediate sacrificial layer, and a bottom substrate stacked in sequence. The top substrate is used to prepare a front transistor (i.e., a first transistor), and the bottom substrate is used to prepare a back transistor (i.e., a second transistor).

In some embodiments, when the substrate includes a top substrate, a middle sacrificial layer and a bottom substrate stacked in sequence, the middle sacrificial layer material can be silicon germanium (SiGe) material or other semiconductor materials, which is not limited in the embodiments of the present disclosure.

In some embodiments, when the substrate includes a top substrate, an intermediate sacrificial layer, and a bottom substrate stacked in sequence, when the type of the stacked transistor is different, the arrangement of the substrate is also different accordingly. When the stacked transistor is any one of a fin-type field effect transistor, a planar transistor, and a vertical field effect transistor, the bottom substrate and the top substrate may be silicon materials. When the stacked transistor is a nanosheet field effect transistor, the bottom substrate and the top substrate may be a stack formed by alternating deposition of silicon and silicon germanium.

In some embodiments, when the substrate includes a top substrate, an intermediate sacrificial layer and a bottom substrate stacked in sequence, the height of the top substrate can be designed according to actual needs, such as 50nm, the height of the bottom substrate is greater than the top substrate, and the height of the intermediate sacrificial layer is less than the height of the top substrate.

In some embodiments, when the substrate includes a top substrate, an intermediate sacrificial layer, and a bottom substrate stacked in sequence, the above step S101 may include: by standard process steps, the active structure is patterned, and the top substrate, the intermediate sacrificial layer, and the bottom substrate are sequentially etched to obtain an active structure. The active structure includes a first active structure in the first transistor and a second active structure in the second transistor. A larger etching depth may be used when etching the substrate. The height of the active structure should be greater than a preset height threshold, and the height of the active structure may be greater than 100 nm. It should be noted that the height of the active structure may be designed according to actual needs, and the embodiments of the present disclosure are not limited to this.

In some embodiments, when the substrate includes a top substrate, a middle sacrificial layer and a bottom substrate stacked in sequence, when the stacked transistor is a fin-type field effect transistor, the above step S101 may include: etching the top silicon substrate, the middle silicon germanium sacrificial layer and the bottom silicon substrate in sequence to form a plurality of fin structures; the upper half of the fin structure (i.e., the top silicon substrate after etching) is the first active structure, and the lower half of the fin structure (i.e., the bottom silicon substrate after etching) is the second active structure.

In some embodiments, when the substrate includes a top substrate, a middle sacrificial layer and a bottom substrate stacked in sequence, when the stacked transistor is a nanosheet field effect transistor, the above step S101 may include: etching the top stacked substrate, the middle silicon germanium sacrificial layer and the bottom stacked substrate in sequence to form a columnar structure; the upper half of the columnar structure (i.e., the top stacked substrate after etching) is the first active structure, and the lower half of the columnar structure (i.e., the bottom stacked substrate after etching) is the second active structure.

In some embodiments, when the substrate includes a top substrate, a middle sacrificial layer, and a bottom substrate stacked in sequence, When the transistor is a planar transistor, the above step S101 may include: etching the top silicon substrate, the middle silicon germanium sacrificial layer and the bottom silicon substrate in sequence to form a block structure; the upper half of the block structure (i.e., the top silicon substrate after etching) is the first active structure, and the lower half of the block structure (i.e., the bottom silicon substrate after etching) is the second active structure.

In some embodiments, when the substrate includes a top substrate, a middle sacrificial layer and a bottom substrate stacked in sequence, when the stacked transistor is a vertical field effect transistor, the above step S101 may include: etching the top silicon substrate, the middle silicon germanium sacrificial layer and the bottom silicon substrate in sequence to form a columnar structure; the upper half of the columnar structure (i.e., the top silicon substrate after etching) is the first active structure, and the lower half of the columnar structure (i.e., the bottom silicon substrate after etching) is the second active structure.

In some embodiments, when the stacked transistor is a fin-type field effect transistor, after forming a plurality of fin structures, a fin cut process may be performed on the plurality of fin structures so that the heights of the plurality of fin structures remain consistent.

In some possible implementations, when the substrate includes a top substrate, an intermediate sacrificial layer, and a bottom substrate stacked in sequence, after step S101, the method may further include: filling oxide above the active structure to form a second shallow trench isolation (STI). The height of the second shallow trench isolation structure is greater than the height of the active structure.

In some embodiments, the oxide forming the second shallow trench isolation structure may be any one of the following: silicon nitride (SiN, Si3N4), silicon dioxide ( _SiO2 ), silicon oxycarbide (SiCO), etc.

In some embodiments, after forming the second shallow trench isolation structure, the above method may further include: performing chemical-mechanical planarization (CMP) on the second shallow trench isolation structure.

In some embodiments, chemical mechanical planarization is performed on the second shallow trench isolation structure so that when the second shallow trench isolation structure is subsequently etched, the corrosion depths corresponding to the second shallow trench isolation structure in different regions are the same, thereby making the heights of the exposed active structures the same.

In some possible embodiments, when the substrate includes a top substrate, an intermediate sacrificial layer, and a bottom substrate stacked in sequence, after the above step S101, the method may further include: forming a first dummy gate structure spaced apart on the surface of the first active structure and a first shallow trench isolation structure wrapping the second active structure.

It can be understood that the first shallow trench isolation structure is formed before the second shallow trench isolation structure. After the second shallow trench isolation structure is formed, the second shallow trench isolation structure that wraps the first active structure can be removed by etching, and the unetched second shallow trench isolation structure serves as the first shallow trench isolation structure, and the first active structure is exposed, and a first pseudo gate structure can be formed based on the first active structure.

Step S102: forming a first transistor based on the first active structure.

It can be understood that after the first active structure is formed, other structures in the first transistor, such as a first source-drain structure, a first gate structure, and a first metal interconnection layer, can be formed based on the first active structure.

In some possible embodiments, when the substrate includes a top substrate, an intermediate sacrificial layer, and a bottom substrate stacked in sequence, the above step S102 may include: etching a portion of the first active structure along the extension direction of the first active structure to form a first source-drain structure; depositing semiconductor material on the first active structure and the first source-drain structure to form a first interlayer dielectric layer; removing the first dummy gate structure and forming a first gate structure; removing a portion of the first interlayer dielectric layer to form a first source-drain metal groove; depositing metal material in the first source-drain metal groove to form a first source-drain metal; performing a back-end process above the first interlayer dielectric layer and the first gate structure to form a first metal interconnection layer.

In some embodiments, etching a portion of the first active structure along the extension direction of the first active structure and forming a first source-drain structure may include: removing a portion of the first active structure by etching to provide a source-drain groove of the first transistor. Using the first spacer as a mask, forming a strained material such as silicon germanium or silicon carbide in the source-drain groove of the first transistor by selective epitaxial growth to fill the source-drain groove of the first transistor, and then forming the first source-drain structure on the strained material by a heavy doping process.

It should be noted that, for ease of explanation, the first source-drain structure mentioned in the embodiments of the present disclosure is an abbreviation, which refers to the first source structure and/or the first drain structure. In addition, the second source-drain structure, the first source-drain metal, the second source-drain metal, the source-drain groove, etc. are similar to the first source-drain structure, where "source-drain" is an abbreviation for "source and/or drain".

In some embodiments, depositing a semiconductor material on the first active structure and the first source-drain structure to form a first interlayer dielectric layer may include: depositing an insulating material (such as silicon dioxide (SiO2)) above the first active structure and the first source-drain structure to form a first interlayer dielectric layer; the first interlayer dielectric layer may cover the first active structure and the first source-drain structure.

In some embodiments, removing the first dummy gate structure and forming a first gate structure may include: removing the first dummy gate structure by etching to expose the gate region of the first transistor, and depositing metal material in the gate region of the first transistor to form the first gate structure of the first transistor.

In some embodiments, the metal materials of the first gate structure and the second gate structure may include: tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN). The materials of the first gate structure and the second gate structure can be selected according to actual conditions and are not limited to the metal materials listed above.

In some embodiments, the materials of the first gate structure and the second gate structure can be made of the same or different metal materials according to actual conditions, and the embodiments of the present disclosure are not limited to this.

In some embodiments, before preparing the first gate structure, the method may further include: depositing a semiconductor material on the surface of the first active structure to form a first gate dielectric layer of the first transistor, wherein the first gate dielectric layer is used to isolate the first active structure from the first gate structure.

In some embodiments, removing a portion of the first interlayer dielectric layer to form a first source-drain metal groove; depositing a metal material in the first source-drain metal groove to form the first source-drain metal may include: etching a portion of the first interlayer dielectric layer located above the first source-drain structure until the upper surface of the first source-drain structure is exposed to form the first source-drain metal groove. Depositing a metal material in the first source-drain metal groove to obtain the first source-drain metal.

In some embodiments, a back-end process is performed above the first interlayer dielectric layer and the first gate structure to form a first metal interconnection layer, which may include: performing interconnection line dielectric deposition, metal line formation, lead pad formation and other processes on the first interlayer dielectric layer and the first gate structure to form the first metal interconnection layer of the first transistor.

In some possible implementations, when the first active structure, the first intermediate layer, and the second active structure are made of the same material, before the above step S102, the above method may further include: depositing a dielectric material on the first active structure, the first intermediate layer, and the second active structure to form a shallow trench isolation structure; the shallow trench isolation structure wraps the first active structure, the first intermediate layer, and the second active structure; and removing a first portion of the shallow trench isolation structure to expose the first active structure.

In some embodiments, the dielectric material (or insulating material) forming the shallow trench isolation structure may be any of the following: silicon nitride (SiN, Si ₃ N ₄ ), SiO ₂ or silicon oxycarbide (SiCO), etc., or other insulating materials, which are not limited in the embodiments of the present disclosure.

In some embodiments, after forming the shallow trench isolation structure, the method may further include: performing CMP treatment on the shallow trench isolation structure.

In some embodiments, chemical mechanical planarization is performed on the shallow trench isolation structure so that when the shallow trench isolation structure is subsequently etched, the corresponding corrosion depths of the shallow trench isolation structure in different regions are the same, thereby making the top heights of the exposed active structures the same.

In some possible embodiments, when the first active structure, the first intermediate layer, and the second active structure are made of the same material, the above step S102 may include: based on the first active structure, sequentially forming a first dummy gate structure, a first spacer, a first source-drain structure, and a first interlayer dielectric layer of the first transistor; removing the first dummy gate structure, and forming a first gate structure and a first gate dielectric layer; performing post-processing on the first interlayer dielectric layer to form a first metal interconnection layer.

In some embodiments, the first pseudo-gate structure, the first spacer, the first source-drain structure and the first interlayer dielectric layer of the first transistor are sequentially formed based on the first active structure, which may include: photolithography to open the gate region of the first transistor, and deposit a semiconductor material (such as polysilicon) in the gate region to form the first pseudo-gate structure of the first transistor; forming a first spacer on both sides of the first pseudo-gate structure; removing a portion of the first active structure by etching to provide a source-drain groove of the first transistor, and using the first spacer as a mask, forming a strained material such as silicon germanium or silicon carbide in the source-drain groove of the first transistor by selective epitaxial growth to fill The source and drain grooves of the first transistor are formed, and then a first source and drain structure is formed on the above-mentioned strained material through a heavy doping process; an insulating material (such as silicon dioxide) is deposited above the first active structure and the first source and drain structure to form a first interlayer dielectric layer; the first interlayer dielectric layer can cover the first active structure and the first source and drain structure; then, the first dummy gate structure is removed, and an insulating material is deposited on the surface of the first active structure to form a first gate dielectric layer of the first transistor; a metal material is deposited in the gate area to form a first gate structure; finally, a post-processing is performed on the first interlayer dielectric layer and the first gate structure to form a first metal interconnection layer.

In some embodiments, the active region is a collective term for the source region, the drain region, and the channel region.

Step S103, flipping the wafer and removing the substrate to expose the second active structure.

It can be understood that after forming the first transistor, the first transistor can be flipped so that the substrate is placed upward, and then the substrate is removed so that the second active structure is exposed.

In some possible implementations, before the above step S103, the above method may further include: depositing an insulating material on the upper surface of the first transistor to form an insulating layer; and bonding the insulating layer to the carrier wafer.

In some embodiments, the bonded carrier wafer can provide physical support for the flipped first transistor after inversion, effectively preventing the first transistor from being broken by external force during the preparation of the second transistor.

In some possible implementations, the above step S103 may include: flipping the first transistor; and performing wafer thinning and planarization on the substrate to expose the bottom of the second active structure.

It can be understood that after the first transistor is flipped over, the bottom substrate is placed upward and the bottom substrate can be removed by wafer thinning and planarization (such as CMP). The CMP process stops at the first shallow trench isolation structure, so that the surface of the second active structure away from the first active structure is also exposed.

In some embodiments, after removing the bottom substrate, the first shallow trench isolation structure can be removed by etching to expose the second active structure for subsequent preparation of the second transistor.

It should be noted that during the etching process of the first shallow trench isolation structure, the first shallow trench isolation structure of a preset height can be retained and used as a shallow trench isolation layer. The shallow trench isolation layer is located between the first gate structure and the second gate structure and is used to isolate the first gate structure from the second gate structure.

In some possible embodiments, when the first active structure, the first intermediate layer, and the second active structure are made of the same material, after the above step S103, the above method may further include: removing a portion of the second active structure away from the first active structure to form a first groove; depositing a second insulating material in the first groove to form a first filling structure; and removing a second portion of the shallow trench isolation structure to expose the second active structure and the first intermediate layer.

It is understandable that after removing the substrate, the shallow trench isolation structure is exposed, and at this time, the shallow trench isolation structure and the second active structure have the same horizontal height in a direction perpendicular to the substrate. Then, a portion of the second active structure can be etched by selective etching to form a first groove.

In some embodiments, the etching height (ie, the height of the first groove) can be set according to actual conditions, and the embodiments of the present disclosure are not limited to this.

In some embodiments, a second insulating material is deposited in the first groove and above the shallow trench isolation structure. The deposited second insulating material fills the first groove and covers the surface of the shallow trench isolation structure. Then, the deposited second insulating material is subjected to CMP treatment. The CMP stops at the surface of the shallow trench isolation structure. The second insulating material in the first groove is not removed, thereby forming a first filling structure.

In some embodiments, the shallow trench isolation structure consists of a first portion and a second portion, the first portion encapsulates the first active structure, and the second portion encapsulates the second active structure and the first intermediate layer.

In some possible embodiments, when the first active structure, the first intermediate layer, and the second active structure are made of the same material and the above-mentioned first filling structure is formed, the above-mentioned removal of a portion of the second semiconductor material layer covering the first semiconductor material layer to expose the first semiconductor material layer may include: removing a portion of the second semiconductor material layer covering the first semiconductor material layer and a portion of the second semiconductor material layer covering the first filling structure to expose the first semiconductor material layer and the first filling structure; after oxidizing the first intermediate layer to form the isolation dielectric structure, the above-mentioned method may also include: removing the first filling structure and the second semiconductor material layer to expose the second active structure.

It can be understood that the second semiconductor material layer covers the surface of the first filling structure, the first semiconductor material layer and the first active structure. Since the second semiconductor material layer and the first filling structure are both made of the second insulating material (for example, SiN), the thickness of the SiN material on the second surface of the second active structure (i.e., the side of the second active structure away from the first active structure) is greater than the thickness of the SiN material on the first semiconductor material layer. At this time, the SiN material covering the first semiconductor material layer and part of the SiN material on the second surface of the second active structure can be removed by anisotropic etching, and the remaining SiN material wraps the surface of the second active structure. Taking the second insulating material as SiN material as an example, after forming the isolation dielectric structure, the SiN material covering the surface of the second active structure is removed to expose the second active structure, so as to facilitate the subsequent preparation of the second transistor.

In some possible embodiments, when the first active structure, the first intermediate layer, and the second active structure are made of the same material and the first filling structure is not formed, the removal of a portion of the second semiconductor material layer covering the first semiconductor material layer to expose the first semiconductor material layer may include: removing a portion of the second semiconductor material layer covering the first semiconductor material layer and a portion of the second semiconductor material layer covering the second surface of the second active structure to expose the first semiconductor material layer and the second surface; the second surface is a surface of the second active structure away from the first active structure.

It can be understood that, taking the second insulating material as SiN material as an example, after a layer of SiN material is deposited (such as atomic layer deposition) on the surface of the second active structure and the first semiconductor material layer, the deposited SiN material is the second semiconductor material layer, and the second semiconductor material layer wraps the second active structure and covers the first semiconductor material layer. Then, the SiN material on the second surface of the second active structure and on the first semiconductor material layer can be removed by anisotropic etching. After the etching is completed, the retained SiN material is located on the side of the second active structure (i.e., the surface of the second active structure except the surface where the second surface contacts the first intermediate layer).

In some possible embodiments, when the first active structure, the first intermediate layer, and the second active structure are made of the same material and the first filling structure is not formed, after removing the first semiconductor material layer to expose the first intermediate layer, the method may further include: depositing a second insulating material on the second surface and the first area of the first surface to form a third semiconductor material layer; the first area is not in contact with the second active structure; after oxidizing the first intermediate layer to form the isolation dielectric structure, the method may further include: removing the second semiconductor material layer and the third semiconductor material layer to expose the second active structure.

It can be understood that, taking the second insulating material as SiN material as an example, after removing the first semiconductor material layer, a layer of SiN material is deposited (such as physical vapor deposition) on the second surface of the second active structure and the area on the first surface that does not contact the first intermediate layer (i.e., the first area) to form a third semiconductor material layer. The third semiconductor material layer does not contact the first intermediate layer. While exposing the first intermediate layer, the third semiconductor material layer and the second semiconductor material layer jointly wrap the second active structure, so that the second active structure can be protected from oxidation during the subsequent oxidation process. Taking the second insulating material as SiN material as an example, after forming the isolation dielectric structure, the SiN material wrapped on the surface of the second active structure and the first surface of the first transistor is removed to expose the second active structure, so as to facilitate the subsequent preparation of the second transistor.

Step S104: forming a second transistor based on the second active structure; the first transistor and the second transistor are self-aligned in a direction perpendicular to the channel.

It can be understood that after the second active structure is formed, other structures in the second transistor, such as a second source-drain structure, a second gate structure, and a second metal interconnection layer, can be formed based on the second active structure.

In some possible embodiments, when the substrate includes a top substrate, an intermediate sacrificial layer, and a bottom substrate stacked in sequence, the above step S104 may include: forming a second dummy gate structure spaced apart on the surface of the second active structure; etching a portion of the second active structure along an extension direction of the second active structure to form a second source-drain structure; depositing semiconductor material on the second active structure and the second source-drain structure to form a second interlayer dielectric layer; removing the second dummy gate structure and forming a second gate structure; removing a portion of the second interlayer dielectric layer to form a second source-drain metal groove; depositing metal material in the second source-drain metal groove to form a second source-drain metal; performing a back-end process above the second interlayer dielectric layer and the second gate structure to form a second metal interconnection layer.

In some embodiments, forming a second dummy gate structure spaced apart on the surface of the second active structure may include: photolithographically opening a gate region of the second transistor, and depositing a semiconductor material in the gate region of the second transistor to form a second dummy gate structure of the second transistor.

It should be noted that the first dummy gate structure and the second dummy gate structure may be prepared using the same semiconductor material or different semiconductor materials, which is not limited in the embodiments of the present disclosure.

In some embodiments, after forming the second dummy gate structure, the method may further include: depositing an insulating material on both sides of the second dummy gate structure to form a second spacer.

It should be noted that the first spacer and the second spacer may be prepared using the same insulating material or different insulating materials, which is not limited in the embodiments of the present disclosure.

In some embodiments, etching a portion of the second active structure along the extension direction of the second active structure to form a second source-drain structure may include: removing a portion of the second active structure by etching to provide a source-drain groove of the second transistor. Using the second spacer as a mask, forming a strained material such as silicon germanium or silicon carbide in the source-drain groove of the second transistor by selective epitaxial growth to fill the source-drain groove of the second transistor, and then forming the second source-drain structure on the strained material by a heavy doping process.

In some embodiments, depositing a semiconductor material on the second active structure and the second source-drain structure to form a second interlayer dielectric layer may include: depositing an insulating material above the second active structure and the second source-drain structure to form a second interlayer dielectric layer; the second interlayer dielectric layer may cover the second active structure and the second source-drain structure.

It should be noted that the first interlayer dielectric layer and the second interlayer dielectric layer may be prepared using the same semiconductor material or different semiconductor materials, which is not limited in the embodiments of the present disclosure.

In some embodiments, removing the second dummy gate structure and forming a second gate structure may include: removing the second dummy gate structure by etching to expose the gate region of the second transistor, and depositing metal material in the gate region of the second transistor to form a second gate structure of the second transistor.

It should be noted that the first gate structure and the second gate structure may be prepared using the same metal material or different metal materials, which is not limited in the embodiments of the present disclosure.

In some embodiments, before preparing the second gate structure, the method may further include: depositing a semiconductor material on the surface of the second active structure to form a second gate dielectric layer of the second transistor, wherein the second gate dielectric layer is used to isolate the second active structure from the second gate structure.

It should be noted that the first gate dielectric layer and the second gate dielectric layer may be prepared using the same semiconductor material or different semiconductor materials, which is not limited in the embodiments of the present disclosure.

In some embodiments, removing a portion of the second interlayer dielectric layer to form a second source-drain metal groove; depositing a metal material in the second source-drain metal groove to form a second source-drain metal may include: etching a portion of the second interlayer dielectric layer located above the second source-drain structure until the upper surface of the second source-drain structure is exposed to form the second source-drain metal groove. Depositing a metal material in the second source-drain metal groove to obtain the second source-drain metal.

In some embodiments, a back-end process is performed above the second interlayer dielectric layer and the second gate structure to form a second metal interconnect layer, which may include: performing interconnect line dielectric deposition, metal line formation, lead pad formation and other processes on the second interlayer dielectric layer to form a second metal interconnect layer of the second transistor.

In some possible embodiments, when the first active structure, the first intermediate layer, and the second active structure are made of the same material, before the above-mentioned step S104, the method may further include: depositing a first insulating material on the first surface of the first transistor facing the second active structure to form a first semiconductor material layer; the first semiconductor material layer surrounds the first intermediate layer; depositing a second insulating material on the second active structure and the first semiconductor material layer to form a second semiconductor material layer; the second semiconductor material layer wraps the second active structure; removing a portion of the second semiconductor material layer covering the first semiconductor material layer to expose the first semiconductor material layer; removing the first semiconductor material layer to expose the first intermediate layer.

It can be understood that the first transistor and the second transistor are arranged back to back. During the preparation process, the first transistor is prepared first. After the first transistor is prepared, the first transistor is flipped over and a first insulating material is deposited above the first transistor (i.e., the first surface of the first transistor close to the second transistor) to form a first semiconductor material layer. Using an atomic layer deposition method, a second insulating material is deposited on the second active structure and the first semiconductor material layer. The formed second semiconductor material layer can wrap the second active structure and cover the first semiconductor material layer. In the subsequent preparation process, the first intermediate layer needs to be exposed, so according to the order in which the material layers are stacked, the portion of the second semiconductor material layer covering the first semiconductor material layer (i.e., the portion of the second semiconductor material layer covering the first semiconductor material layer) is removed first. ), exposing the first semiconductor layer to facilitate subsequent removal of the first semiconductor material layer.

In some embodiments, the first semiconductor material layer covers the first surface and surrounds the first intermediate layer.

In some embodiments, the first insulating material may include, but is not limited to, amorphous carbon and amorphous silicon, or may be other insulating materials, which is not limited in the embodiments of the present disclosure.

In some embodiments, the second insulating material is different from the first insulating material. For ease of description, the second insulating material is silicon nitride (SiN) as an example. It should be noted that the second insulating material may also be other insulating materials, which is not limited in the embodiments of the present disclosure.

In some embodiments, the second semiconductor material layer wraps around the second active structure and covers the first semiconductor material layer.

In some possible implementations, when the first active structure, the first intermediate layer and the second active structure are made of the same material, before the step S104, the method may further include: removing a portion of the second semiconductor material layer covering the second active structure to expose the second active structure.

It can be understood that in the above-mentioned process of removing a portion of the second semiconductor material layer covering the first semiconductor material layer to expose the first semiconductor material layer, the second semiconductor material layer is not completely removed, and a portion of the second semiconductor material layer still surrounds the surface of the second active structure. After removing this portion of the second semiconductor material layer, the second active structure can be exposed, which is convenient for the subsequent preparation of the second transistor.

In some possible implementations, when the first active structure, the first intermediate layer, and the second active structure are made of the same material, the above step S104 may include: based on the second active structure, sequentially forming a second dummy gate structure, a second spacer, a second source-drain structure, and a second interlayer dielectric layer of the second transistor; removing the second dummy gate structure, and forming a second gate structure and a second gate dielectric layer; performing a post-processing on the second interlayer dielectric layer to form a second metal interconnection layer.

It should be noted that, when the first active structure, the first intermediate layer and the second active structure are made of the same material, the process of preparing the second transistor is the same as the process of preparing the first transistor.

Step S105 , forming an isolation dielectric structure based on the first intermediate layer; the material of the isolation dielectric structure is different from the material of the first intermediate layer; the isolation dielectric structure is used to isolate the first active structure from the second active structure.

It can be understood that, in the process of preparing the stacked transistor, the material of the first intermediate layer can be replaced to form an isolation dielectric structure; the material of the isolation dielectric structure is different from the material of the first intermediate layer.

In some possible implementations, when the substrate includes a top substrate, an intermediate sacrificial layer, and a bottom substrate stacked in sequence, after forming the first dummy gate structure, the above step S105 may include: removing the first intermediate layer to form a first gap; and filling the first gap with an insulating material to form an isolation dielectric structure. The isolation dielectric structure is used to isolate the first active structure from the second active structure.

It is understandable that the first intermediate layer between the first active structure and the second active structure can be selectively removed to form a first gap. During the selective removal process, the first pseudo-gate structure can provide structural support for the first active structure, so that the position of the first active structure in the first transistor does not change, and the first active structure and the second active structure remain self-aligned. Filling the first gap with an insulating material (such as a low dielectric constant material (low K) material) can form an isolation dielectric structure, and the isolation dielectric structure can achieve electrical isolation between the first transistor and the second transistor by isolating the first active structure and the second active structure.

In some embodiments, after forming the first dummy gate structure, an insulating material may be deposited on both sides of the first dummy gate structure to form a first spacer. It should be noted that the first spacer and the isolation dielectric structure may be prepared at the same time.

In some possible embodiments, when the substrate includes a top substrate, an intermediate sacrificial layer, and a bottom substrate stacked in sequence, the above-mentioned formation of a first dummy gate structure spaced apart on the surface of a first active structure and a first shallow trench isolation structure wrapping a second active structure may include: forming a second shallow trench isolation structure wrapping the first active structure, the first intermediate layer, and the second active structure; removing a portion of the second shallow trench isolation structure to expose the first active structure and the first intermediate layer, and forming a first shallow trench isolation structure; and forming a first dummy gate structure based on the first active structure.

It can be understood that the second shallow trench isolation structure wraps the entire active structure, and a portion of the second shallow trench isolation structure can be removed by etching, so that the first active structure and the first intermediate layer are exposed. For the sake of distinction, the etched second shallow trench isolation structure can be referred to as the first shallow trench isolation structure, and the first shallow trench isolation structure wraps the second active structure. Then, a semiconductor material (such as polysilicon (poly Si)) is deposited in the gate region of the first transistor to form a first pseudo-gate structure of the first transistor.

It should be noted that the etching process mentioned in the embodiments of the present disclosure may include but is not limited to any of the following: dry etching, wet etching, reactive ion etching and chemical oxide removal process, and the embodiments of the present disclosure are not limited to this.

In some embodiments, the solvent used to etch the second shallow trench isolation structure may be: DHF (including hydrofluoric acid (HF), _hydrogen peroxide ( _H2O2 ) and water ( _H2O )) solution or buffer oxide etching (BOE) solution. The solvent used in the etching process of the embodiment of the present disclosure can be selected according to actual conditions and is not limited to the above-mentioned DHF solution or BOE solution.

In some embodiments, the method of forming the first dummy gate structure may include: photolithographically opening a gate region of the first transistor, and depositing a semiconductor material in the gate region of the first transistor to form the first dummy gate structure of the first transistor.

It can be understood that the first dummy gate structure is connected to the first shallow trench isolation structure at the first intermediate layer.

In some possible implementations, when the first active structure, the first intermediate layer, and the second active structure are made of the same material, the step S105 may include: performing an oxidation treatment on the first intermediate layer to form an isolation dielectric structure.

It is understandable that after the oxidation treatment, the material of the first intermediate layer is oxidized into another material different from the first active structure and the second active structure, and the first intermediate layer is transformed into an isolation dielectric structure. Due to the difference in materials, the isolation dielectric structure can be used to isolate the first active structure and the second active structure.

In some embodiments, since the isolation dielectric structure is located between the first active structure and the second active structure, and the material of the isolation dielectric structure formed by oxidation treatment is different from the material of the first active structure and the second active structure, the isolation dielectric structure can achieve isolation between the active area of the first transistor and the active area of the second transistor.

Below, taking the first transistor and the second transistor as fin-type field effect transistors, and the substrate including a top substrate, an intermediate sacrificial layer and a bottom substrate stacked in sequence as an example, the stacked transistor provided by the embodiment of the present disclosure is described. Figure 2 is a schematic diagram of the first structure of the stacked transistor provided according to the embodiment of the present disclosure. (a) in Figure 2 is a design layout of the stacked transistor. It should be noted that, for ease of understanding, only the fin structure, the gate structure, and the source-drain structure are shown in the design layout; (b) is a cross-sectional view of the stacked transistor made along the cross-sectional direction of the gate structure (i.e., the A-A' direction); (c) is a cross-sectional view of the stacked transistor made along the cross-sectional direction of the source-drain structure (i.e., the B-B' direction); (d) is a cross-sectional view of the stacked transistor made along the cross-sectional direction of the fin structure (i.e., the C-C' direction).

As shown in FIG. 2 , the stacked transistor 10 includes a first transistor 11 and a second transistor 12, and the active structure in the stacked transistor 10 is a plurality of fin-shaped structures. The fin-shaped structure is divided into two parts, namely, the first part and the second part, the first part is used as the first active structure 111 in the first transistor 11, and the second part is used as the second active structure 121 in the second transistor 12. An isolation dielectric structure 13 is provided between the first active structure 111 and the second active structure 121, and the isolation dielectric structure 13 is used to isolate the first active structure 111 and the second active structure 121.

In combination with the above-mentioned preparation method, the preparation process of the stacked transistor 10 shown in Figure 2 is described below. The stacked transistor 10 shown in Figure 2 can be prepared by the process shown in Figures 3A to 3F, which are schematic diagrams of the first preparation process of the stacked transistor provided according to an embodiment of the present disclosure.

In an example, taking the first transistor 11 and the second transistor 12 as fin-type field effect transistors as an example, a first preparation process of the stacked transistor 10 may include the following steps:

The first step is to provide a bottom substrate 211 (such as a Si substrate); epitaxially grow a layer of silicon germanium material on the bottom substrate 211 as an intermediate sacrificial layer 212; and then epitaxially grow Si material on the intermediate sacrificial layer 212 to form a top substrate 213 (see (a) in FIG. 3A ).

In some embodiments, the bottom substrate 211 , the middle sacrificial layer 212 , and the top substrate 213 together constitute the substrate 21 .

Step 2: The top substrate 213 , the middle sacrificial layer 212 and the bottom substrate 211 are sequentially etched to form a plurality of fin structures 22 (see (b) in FIG. 3A ).

In some embodiments, the height of fin structure 22 is greater than 100 nm.

Step 3: fill oxide above the fin structure 22 to form a second shallow trench isolation structure 231 ; then, perform chemical mechanical planarization on the second shallow trench isolation structure 231 (see (c) in FIG. 3A ).

In some embodiments, the height of the second shallow trench isolation structure 231 is greater than the height of the fin structure 22 , and may cover a plurality of fin structures 22 .

Step 4: etching a portion of the second shallow trench isolation structure 231 until the first fin structure 221 and the first intermediate layer 223 are exposed (see (a) in FIG. 3B ).

In some embodiments, the etched second shallow trench isolation structure 231 wraps the second fin structure 222 , and for ease of distinction, may be referred to as a first shallow trench isolation structure 232 .

Step 5: Photolithography is performed to open the gate region of the first transistor 11 , and polysilicon is deposited at the gate region of the first transistor 11 to form a first dummy gate structure 241 (see (b) in FIG. 3B ).

In some embodiments, the first dummy gate structure 241 spans across the first fin structure 221 and is disposed at intervals on the surface of the first fin structure 221 .

Step 6: Selectively remove the first intermediate layer 223 to form a first gap (see (c) in FIG. 3B ).

In some embodiments, during the process of removing the first intermediate layer 223 , the first dummy gate structure 241 provides structural support for the first fin structure 221 .

Step 7: Fill the first gap with a lowK material to form an isolation dielectric structure 13. At the same time, first spacers 117 are formed on both sides of the first dummy gate structure 241 (see (a) in FIG. 3C ).

Step 8: Etch a portion of the fin structure to form a source-drain groove of the first transistor 11, and perform source-drain epitaxial growth at the source-drain groove of the first transistor 11 to form a first source-drain structure 113. Then, deposit a semiconductor material on the first fin structure 221 to form a first interlayer dielectric layer 115 (see (b) in FIG. 3C ).

Step 9: Remove the first dummy gate structure 241, then deposit an insulating material on the surface of the first fin structure 221 to form a first gate dielectric layer 116, and then deposit a metal in the gate region of the first transistor 11 to form a first gate structure 112 (see FIG. 3C ). (c)).

Step 10: Prepare a first source-drain metal 114 on the first source-drain structure 113, and then perform a back-end process on the first interlayer dielectric layer 115 to form a first metal interconnection layer 118 (see (a) in FIG. 3D ).

Step 11: Deposit oxide on top of the first metal interconnect layer 118 to form a first insulating layer 15; then bond the first insulating layer 15 to the carrier wafer 16; then, flip the first transistor 11 after bonding to the carrier wafer 16 so that the bottom substrate 211 is placed facing upward (see (b) in Figure 3D).

Step 12: Use wafer thinning and CMP processes to remove the bottom substrate 211 until the bottom of the fin structure 22 is exposed (see (c) in FIG. 3D ).

Step 13: Selectively etch the first shallow trench isolation structure 232 until the second fin structure 222 is exposed (see (a) in FIG. 3E ).

In some embodiments, a first shallow trench isolation structure 232 of a certain thickness is retained as a shallow trench isolation layer 14 , and the shallow trench isolation layer 14 is used to isolate the first gate structure 112 from the second gate structure 122 .

Step 14: Photolithography is performed to open the gate region of the second transistor 12, and polysilicon is deposited at the gate region of the second transistor 12 to form a second dummy gate structure 242 (see (b) in FIG. 3E ).

Step 15: forming the second spacer 127, the second source-drain structure 123 and the second interlayer dielectric layer 125 of the second transistor 12 (the preparation process can refer to the seventh and eighth steps) (see (c) in FIG. 3E ).

Step 16: forming the second gate structure 122 of the second transistor 12 (the preparation process can refer to step 9).

Step 17: forming the second source-drain metal 124 and the second metal interconnection layer 128 of the second transistor 12 (the preparation process can refer to step 10).

At this point, the stacked transistor 10 in which the first transistor 11 and the second transistor 12 are fin-type field effect transistors is completed.

Below, taking the first transistor and the second transistor as nanosheet field effect transistors, and the substrate including a top substrate, an intermediate sacrificial layer and a bottom substrate stacked in sequence as an example, the stacked transistor provided by the embodiment of the present disclosure is described. Figure 4 is a schematic diagram of the second structure of the stacked transistor provided according to the embodiment of the present disclosure. (a) in Figure 4 is a design layout of the stacked transistor. It should be noted that, for ease of understanding, only the nanosheet structure, the gate structure, and the source-drain structure are shown in the design layout; (b) is a cross-sectional view of the stacked transistor made along the cross-sectional direction of the gate structure (i.e., the A-A' direction); (c) is a cross-sectional view of the stacked transistor made along the cross-sectional direction of the source-drain structure (i.e., the B-B' direction); (d) is a cross-sectional view of the stacked transistor made along the cross-sectional direction of the nanosheet structure (i.e., the C-C' direction).

As shown in FIG4 , the stacked transistor 10 includes a first transistor 11 and a second transistor 12, and the active structure in the stacked transistor 10 is a plurality of nanosheet structures. The nanosheet structure is divided into two parts, namely, the first part and the second part, the first part is used as the first active structure 111 in the first transistor 11, and the second part is used as the second active structure 121 in the second transistor 12. An isolation dielectric structure 13 is provided between the first active structure 111 and the second active structure 121, and the isolation dielectric structure 13 is used to isolate the first active structure 111 and the second active structure 121.

The following describes the preparation process of the stacked transistor 10 shown in Figure 4 in combination with the above preparation method. The stacked transistor 10 shown in Figure 4 can be prepared by the process shown in Figures 5A to 5C, which are schematic diagrams of a second preparation process of the stacked transistor provided according to an embodiment of the present disclosure.

In one example, taking the first transistor 11 and the second transistor 12 as nanosheet field effect transistors as an example, the second preparation process of the stacked transistor 10 may include the following steps:

The first step: providing a bottom substrate 211, the bottom substrate 211 is a stack formed by alternately depositing Si material and SiGe 1 material (i.e., a stack composed of Si layer and SiGe 1 layer); depositing SiGe 2 material on the bottom substrate 211 as an intermediate sacrificial layer 212; and then alternately depositing Si material and SiGe 1 material on the intermediate sacrificial layer 212 to form a top substrate 213 (see (a) in Figure 5A).

In some embodiments, to facilitate subsequent selective etching, the Ge concentration in the SiGe 1 material is different from the Ge concentration in the SiGe 2 material.

In some embodiments, the above-mentioned deposition of SiGe 2 material as the middle sacrificial layer 212 is only an example, and other semiconductor materials can also be used to prepare the middle sacrificial layer 212, or other forms of material layers (such as stacked layers) can be used to prepare the middle sacrificial layer, which is not limited in the embodiments of the present disclosure. Si material, SiGe 2 material and Si material are alternately deposited in sequence to form a stacked layer, and the stacked layer is used as the middle sacrificial layer 212. The stacked layer formed by Si material, SiGe 2 material and Si material can improve the etching selectivity.

Step 2: Etch the top substrate 213, the middle sacrificial layer 212 and the bottom substrate 211 in sequence to form a columnar structure 25; fill oxide above the columnar structure 25 to form a second shallow trench isolation structure 231; then, perform chemical mechanical planarization on the second shallow trench isolation structure 231; etch a portion of the second shallow trench isolation structure 231 until the first portion 251 of the columnar structure and the first middle layer 223 are exposed to form a first shallow trench isolation structure 232; then, form a first dummy gate structure 241 (see (b) in FIG. 5A ) (the process can refer to the fifth step of the first preparation process of the stacked transistor).

Step 3: Selectively remove the first intermediate layer 223 to form a first gap (see (c) in FIG. 5A ).

Step 4: Selectively remove a portion of the first portion 251 of the columnar structure located in the first source-drain region of the first transistor 11 to The first source-drain region is exposed for subsequent preparation of the first source-drain structure 113 (see (a) in FIG. 5B ).

Step 5: Etch the SiGe 1 material layer at the junction of the first part 251 of the columnar structure (i.e., the upper half of the stack) and the first source and drain region to form a first inner sidewall 26 (see (b) in Figure 5B).

Step 6: Fill the first gap with lowK material to form an isolation dielectric structure 13, and fill the first inner sidewall 26 with lowK material to achieve isolation between the SiGe 1 material layer and the first source and drain structure 113; at the same time, form a first spacer 117 on both sides of the first pseudo-gate structure 241 (see (c) in FIG. 5B ).

Step 7: Form a first source-drain structure 113, a first interlayer dielectric layer 115, a first gate structure 112, a first gate dielectric layer 116 and a first metal interconnection layer 118 (see (a) in FIG. 5C ) (the process can refer to steps 8 to 10 of the first preparation process of the stacked transistor).

Step 8: After flipping the wafer, remove the bottom substrate 211 until the upper surface of the second portion 252 of the columnar structure is exposed (see (b) in FIG. 5C ) (the process can refer to the eleventh and twelfth steps of the first preparation process of the stacked transistor).

Step 9: Form a second transistor according to standard process (see (c) in FIG. 5C ) (the process can refer to steps 13 to 17 of the first preparation process of the stacked transistor).

At this point, the stacked transistor 10 in which the first transistor 11 and the second transistor 12 are nanosheet field effect transistors is completed.

In some embodiments, when the first transistor and the second transistor are planar transistors or vertical field effect transistors, except for the active structure being different from the active structure of the stacked transistor composed of the above-mentioned fin-type field effect transistors and the active structure of the stacked transistor composed of the above-mentioned nanosheet field effect transistors, the other structures are the same as the stacked transistor composed of the above-mentioned fin-type field effect transistors and the stacked transistor composed of the above-mentioned nanosheet field effect transistors; accordingly, except for the different preparation process of the active structure, the preparation process of the remaining structures is the same as the preparation process shown in the above-mentioned example.

In the embodiment of the present disclosure, electrical isolation between the first active structure and the second active structure is achieved through an isolation dielectric structure. Compared with an isolation method using an SOI substrate and performing ion implantation between the first active structure and the second active structure, the preparation cost and process difficulty can be reduced.

Below, taking the case where the first transistor and the second transistor are fin field effect transistors, and the first active structure, the first intermediate layer, and the second active structure are made of the same material as an example, the stacked transistor provided by the embodiment of the present disclosure is described. Figure 6 is a schematic diagram of the third structure of the stacked transistor provided according to the embodiment of the present disclosure. (a) in Figure 6 is a design layout of the stacked transistor. It should be noted that, for ease of understanding, only the fin structure, the gate structure, and the source-drain structure are shown in the design layout; (b) is a cross-sectional view of the stacked transistor along the cross-sectional direction of the gate structure (i.e., the A-A' direction); (c) is a cross-sectional view of the stacked transistor along the cross-sectional direction of the source-drain structure (i.e., the B-B' direction); (d) is a cross-sectional view of the stacked transistor along the cross-sectional direction of the fin structure (i.e., the C-C' direction).

As shown in Figure 6, the stacked transistor 10 includes a first transistor 11, a second transistor 12 and an isolation dielectric structure 13; the first active structure 111 of the first transistor 11 and the second active structure 121 of the second transistor 12 are formed by the same process, and the first transistor 11 and the second transistor 12 are self-aligned; the isolation dielectric structure 13 is used to isolate the first active structure 111 and the second active structure 121, and the isolation dielectric structure 13 is located between the first active structure 111 and the second active structure 121.

In some embodiments, since the first active structure 111 of the first transistor 11 and the second active structure 121 of the second transistor 12 are formed by the same etching process, self-alignment of the first transistor 11 and the second transistor 12 can be achieved.

The following describes the preparation process of the stacked transistor shown in Figure 6 in combination with the above preparation method. The stacked transistor shown in Figure 6 can be prepared by the process shown in Figures 7A to 7F, which are schematic diagrams of the third preparation process of the stacked transistor provided in the embodiment of the present disclosure.

In one example, taking the first transistor 11 and the second transistor 12 as fin field effect transistors, and the first active structure, the first intermediate layer, and the second active structure as the same material, the third preparation process of the stacked transistor 10 may include the following steps:

The first step: providing a substrate 21 (such as a Si substrate) (see (a) in FIG. 7A ).

Step 2: etching the substrate 21 to form a plurality of fin-shaped structures 22 , and depositing a dielectric material on the plurality of fin-shaped structures 22 to form a shallow trench isolation structure 23 (see (b) in FIG. 7A ).

In some embodiments, as shown in (b) of Figure 8A, the fin structure 22 is composed of a first fin structure 221, a second fin structure 222 and a first intermediate layer 223; the shallow trench isolation structure 23 is composed of a third shallow trench isolation structure 233, a fourth shallow trench isolation structure 234 and a shallow trench isolation layer 14.

Step 3: Remove the third shallow trench isolation structure 233 to expose the first fin structure 221; then, form the first dummy gate structure, the first spacer 117, the first source-drain structure 113, and the first interlayer dielectric layer 115 in the first transistor 11 in sequence according to standard steps; after removing the first dummy gate structure, form the first gate dielectric layer 116, the first gate structure 112 and the first metal interconnection layer 118 (see (c) in FIG. 7A ).

Step 4: Deposit oxide on the first metal interconnect layer 118 to form a first insulating layer 15, and the first insulating layer 15 is bonded to the carrier wafer 16. Next, the first transistor 11 bonded to the carrier wafer 16 is flipped over so that the substrate 21 is placed upward (see (a) in FIG. 7B ).

Step 5: Perform wafer thinning on the substrate 21 until the substrate 21 is removed, exposing the second fin structure 222 away from the first fin structure 221's surface (see (b) in FIG. 7B ).

Step 6: Remove a portion of the second fin structure 222 by selective etching to form a first groove 27 (see (c) in FIG. 7B ).

Step 7: Deposit SiN material (not shown in the figure) in the first groove 27 and on the fourth shallow trench isolation structure 234, and perform CMP treatment on the deposited SiN material, and the CMP stops at the surface of the fourth shallow trench isolation structure 234; after the CMP treatment, a first filling structure 28 is formed (see (a) in Figure 7C).

Step 8: Remove the fourth shallow trench isolation structure 234 by etching to expose the second fin structure 222 and the shallow trench isolation layer 14 (see (b) in FIG. 7C ).

In some embodiments, the shallow trench isolation layer 14 is used to isolate the first transistor 11 from the second transistor 12 .

Step 9: depositing amorphous carbon on the shallow trench isolation layer 14 to form a first semiconductor material layer 31 (see (c) in FIG. 7C ).

Step 10: A layer of SiN material is atomically deposited on the first semiconductor material layer 31 and the surface of the second fin structure 222 to form the second semiconductor material layer 32. Due to the first filling structure 28, the thickness of the SiN material on the surface of the second fin structure 222 away from the first fin structure 221 is greater than the thickness of the SiN material on the remaining surfaces (see (a) in FIG. 7D ).

Step 11: Remove the SiN material on the surface of the second fin structure 222 away from the first fin structure 221 and the first semiconductor material layer 31 by anisotropic etching (see (b) in FIG. 7D ).

Step 12: Remove the first semiconductor material layer 31 by isotropic etching to expose the first intermediate layer 223 (see (c) in FIG. 7D ).

Step 13: Oxidize the first intermediate layer 223 to form an isolation dielectric structure 13 (see (a) in FIG. 7E ).

Step 14: Remove the SiN material on the surface of the second fin structure 222 by isotropic etching (see (b) in FIG. 7E ).

Step 15: Using standard steps, a second dummy gate structure 242 of the second transistor 12 is formed (see (c) in FIG. 7E ).

Step 16: Using standard steps, prepare the second spacer 127, the second source-drain structure 123, and the second interlayer dielectric layer 125 in the second transistor 12 in sequence (see (a) in FIG. 7F ).

Step 17: Remove the second dummy gate structure 242 to expose the gate region of the second transistor 12, and deposit an insulating material at the connection between the gate region and the second fin structure 222 to form a second gate dielectric layer 126; deposit a metal material in the gate region to form a second gate structure 122 (see (b) in Figure 7F).

Step 18: Perform a back-end process on the second interlayer dielectric layer 125 to form a second metal interconnection layer 128 (see (c) in FIG. 7F ).

At this point, the stacked transistor 10 is manufactured by the third manufacturing method, in which the first transistor 11 and the second transistor 12 are fin field effect transistors and the first active structure 111 and the second active structure 121 are isolated by the isolation dielectric structure 13 .

In some embodiments, compared with traditional ion implantation and isolation methods using silicon on insulator (SOI), the process for preparing the isolation dielectric structure in the embodiments of the present disclosure is simpler, and at the same time takes into account the self-alignment problem of the first transistor and the second transistor, thereby ensuring the consistency of the active areas of the first transistor and the second transistor.

The manufacturing process shown in the above-mentioned FIGS. 7A to 7F is only one example of the stacked transistor in the embodiment of the present disclosure. The stacked transistor in the embodiment of the present disclosure can also be manufactured by the process shown in FIGS. 8A to 8D, which are schematic diagrams of the fourth manufacturing process of the stacked transistor provided according to the embodiment of the present disclosure.

In an example, taking the first transistor 11 and the second transistor 12 as fin field effect transistors, and the first active structure, the first intermediate layer, and the second active structure as the same material, the fourth preparation process of the stacked transistor 10 may include the following steps:

The first step: providing a substrate 21 (such as a Si substrate); forming a plurality of fin structures 22 and a shallow trench isolation structure 23; forming a first transistor 11; flipping the first transistor 11 after bonding the carrier wafer 16 so that the substrate 21 is placed facing upward; removing the substrate 21 to expose the second fin structure 222 away from the surface of the first fin structure 221 (the process can refer to the first to fifth steps in the first preparation process of the stacked transistor mentioned above) (see (a) in Figure 9A).

Step 2: remove the fourth shallow trench isolation structure 234 to expose the second fin structure 222 and the first intermediate layer 223 , and form a shallow trench isolation layer 14 (see (b) in FIG. 9A ).

Step 3: depositing amorphous carbon on the shallow trench isolation layer 14 to form a first semiconductor material layer 31 (see (c) in FIG. 9A ).

Step 4: A layer of SiN material is atomically deposited on the first semiconductor material layer 31 and the surface of the second fin structure 222 to form a second semiconductor material layer 32 (see (a) in FIG. 9B ).

Step 5: Remove the SiN material on the surface of the second fin structure 222 away from the first fin structure 221 and the SiN material on the first semiconductor material layer 31 by anisotropic etching (see (b) in FIG. 9B ).

Step 6: Remove the first semiconductor material layer 31 by anisotropic etching (see (c) in FIG. 9B ).

Step 7: Deposit SiN material on the surface of the second fin structure 222 away from the first fin structure 221 and on a portion of the shallow trench isolation layer 14 (the area not in contact with the first intermediate layer 223) to form a third semiconductor material layer 33 (see (a) in Figure 9C).

Step 8: Oxidize the first intermediate layer 223 exposed to the outside to form an isolation dielectric structure 13 (see (b) in FIG. 9C ).

Step 9: Remove the second semiconductor material layer 32 and the third semiconductor material layer 33 to expose the second fin structure 222 (see FIG. 9C ). (c) in the figure.

Step 10: Forming the second transistor 12 (the process can refer to steps 15 to 17 in the third preparation process of the stacked transistor described above) (see FIG. 9D )

At this point, the stacked transistor 10 is manufactured by the fourth manufacturing method, in which the first transistor 11 and the second transistor 12 are fin field effect transistors and the first active structure 111 and the second active structure 121 are isolated by the isolation dielectric structure 13 .

It should be noted that when the stacked transistor is a full-surround gate transistor, a planar transistor or a vertical transistor, the preparation method of the stacked transistor is the same as the preparation method of the stacked transistor being a fin field effect transistor in the above embodiment.

In the embodiment of the present disclosure, by providing an isolation dielectric structure between the first active structure and the second active structure, electrical isolation between the first active structure and the second active structure can be achieved.

In the disclosed embodiment, the above-mentioned method for preparing the stacked transistor not only optimizes the process flow of the stacked transistor, but also takes into account the consistency, defect density and alignment of the active regions of the upper and lower transistors (i.e., the first transistor and the second transistor). In addition, the above-mentioned method for preparing the stacked transistor further solves the long-standing problems existing in the mainstream technical solutions of the stacked transistor, such as complex process, fixed type (monolithic solution), difficult alignment, and high defect density of the upper semiconductor material (sequential solution), thereby promoting the industrialization of the stacked transistor technology.

Secondly, the preparation method of the stacked transistor described in the embodiment of the present disclosure is also an organic fusion of the current sequential and monolithic stacked transistor solutions. The mature technology has high reuse, can avoid a large amount of expensive process development to save costs, and has high feasibility. At the same time, in the embodiment of the present disclosure, the stacked transistor adopts a self-aligned "back-to-back" active area and metal gate design, and the front and back transistors (i.e., the first transistor and the second transistor) have independent signal and power supply networks, and are connected through local interconnection. Without changing the extremely miniaturized 4T track unit design, the metal wiring resources are greatly released (can be increased by more than 60%), and there is huge space in the direction of collaborative optimization of process design. Finally, the isolation method of the stacked transistor is compatible with the existing mainstream device architecture, and can realize the front and back stacking of planar transistors, fin field effect transistors, nanosheet field effect transistors and even vertical field effect transistors (VTFETs) without the need for special process development for specific device architectures. It has strong flexibility and is highly extensible from the perspective of semiconductor process node iteration. The inverted stacked transistor is very advanced in concept, has important industrial value, and has strong practicality and broad prospects for expansion.

The stacked transistor provided in the embodiment of the present disclosure can be inspected using an inspection and analysis instrument, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), etc. Taking TEM as an example, the stacked transistor provided in the embodiment of the present disclosure can be inspected by TEM slicing to inspect the isolation dielectric structure located between the first active structure and the second active structure.

The present disclosure provides a semiconductor device, including: a stacked transistor as described in the above embodiment. The definition of the stacked transistor can refer to the stacked transistors shown in FIG. 2 , FIG. 4 , and FIG. 6 .

The present disclosure provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiment, the semiconductor device being arranged on the circuit board. The semiconductor device includes the above stacked transistor. The definition of the stacked transistor can refer to the stacked transistors shown in FIG. 2, FIG. 4, and FIG. 6.

In the above embodiments, the description of each embodiment has different emphases. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

The above is only an exemplary embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims (14)

A method for preparing a stacked transistor, the method comprising: Forming a first active structure, a first intermediate layer, and a second active structure stacked in sequence on a substrate; Based on the first active structure, forming a first transistor; Flipping and removing the substrate to expose the second active structure; Based on the second active structure, a second transistor is formed; the first transistor and the second transistor are self-aligned in a direction perpendicular to the channel; An isolation dielectric structure is formed based on the first intermediate layer; the material of the isolation dielectric structure is different from the material of the first intermediate layer; and the isolation dielectric structure is used to isolate the first active structure from the second active structure. The method according to claim 1, wherein After forming the first active structure, the first intermediate layer, and the second active structure stacked in sequence on the substrate, the method further includes: A first dummy gate structure spaced apart on a surface of the first active structure and a first shallow trench isolation structure wrapping the second active structure are formed. The method according to claim 2, wherein forming an isolation dielectric structure based on the first intermediate layer comprises: removing the first intermediate layer to form a first gap; An insulating material is filled in the first gap to form the isolation dielectric structure. The method according to claim 3, wherein the forming of a first dummy gate structure spaced apart on the surface of the first active structure and a first shallow trench isolation structure wrapping the second active structure comprises: forming a second shallow trench isolation structure encapsulating the first active structure, the first intermediate layer and the second active structure; removing a portion of the second shallow trench isolation structure to expose the first active structure and the first intermediate layer, and forming the first shallow trench isolation structure; Based on the first active structure, the first dummy gate structure is formed. The method according to claim 1, wherein before forming the second transistor based on the second active structure, the method further comprises: Depositing a first insulating material on a first surface of the first transistor facing the second active structure to form a first semiconductor material layer; the first semiconductor material layer surrounds the first intermediate layer; Depositing a second insulating material on the second active structure and the first semiconductor material layer to form a second semiconductor material layer; the second semiconductor material layer wraps the second active structure; removing a portion of the second semiconductor material layer covering the first semiconductor material layer to expose the first semiconductor material layer; The first semiconductor material layer is removed to expose the first intermediate layer. The method according to claim 5, wherein forming an isolation dielectric structure based on the first intermediate layer comprises: The first intermediate layer is oxidized to form the isolation dielectric structure. The method according to claim 6, wherein before forming the first transistor based on the first active structure, the method further comprises: A dielectric material is deposited on the first active structure, the first intermediate layer and the second active structure to form a shallow trench isolation structure; the shallow trench isolation structure wraps the first active structure, the first intermediate layer and the second active structure; and a first portion of the shallow trench isolation structure is removed to expose the first active structure. The method according to claim 7, wherein after flipping the wafer and removing the substrate to expose the second active structure, the method further comprises: removing a portion of the second active structure away from the first active structure to form a first groove; depositing the second insulating material in the first groove to form a first filling structure; A second portion of the shallow trench isolation structure is removed to expose the second active structure and the first intermediate layer. The method according to claim 8, wherein The removing a portion of the second semiconductor material layer covering the first semiconductor material layer to expose the first semiconductor material layer comprises: removing a portion of the second semiconductor material layer covering the first semiconductor material layer and a portion of the second semiconductor material layer covering the first filling structure to expose the first semiconductor material layer and the first filling structure; After the first intermediate layer is oxidized to form the isolation dielectric structure, the method further includes: removing the first filling structure and the second semiconductor material layer to expose the second active structure. The method according to claim 7, wherein removing a portion of the second semiconductor material layer covering the first semiconductor material layer to expose the first semiconductor material layer comprises: A portion of the second semiconductor material layer covering the first semiconductor material layer and a portion of the second semiconductor material layer covering the second surface of the second active structure are removed to expose the first semiconductor material layer and the second surface; the second surface is a surface of the second active structure away from the first active structure. The method according to claim 10, wherein After removing the first semiconductor material layer to expose the first intermediate layer, the method further includes: depositing a second insulating material on the second surface and a first region of the first surface to form a third semiconductor material layer; the first region is not in contact with the second active structure; After the first intermediate layer is oxidized to form the isolation dielectric structure, the method further includes: removing the second semiconductor material layer and the third semiconductor material layer to expose the second active structure. A stacked transistor comprising: a first transistor; a second transistor; the first transistor and the second transistor are self-aligned in a direction perpendicular to the channel; An isolation dielectric structure; the isolation dielectric structure is located between a first active structure of the first transistor and a second active structure of the second transistor, and the isolation dielectric structure is used to isolate the first active structure from the second active structure. A semiconductor device comprising: the stacked transistor as claimed in claim 12. An electronic device comprises: a circuit board and the semiconductor device according to claim 13, wherein the semiconductor device is arranged on the circuit board.