WO2025034904A2

WO2025034904A2 - Zipper-stacked transistors

Info

Publication number: WO2025034904A2
Application number: PCT/US2024/041340
Authority: WO
Inventors: Michael Daniel HU; Sean Thomas VIBBERT; Oliver Ethan FORMAN; Jeffrey Scott KAUPPILA; William Timothy HOLMAN; Lloyd Wilson MASSENGILL
Original assignee: Vanderbilt University
Current assignee: Vanderbilt University
Priority date: 2023-08-10
Filing date: 2024-08-07
Publication date: 2025-02-13
Anticipated expiration: 2026-02-10
Also published as: WO2025034904A3

Abstract

An integrated circuit includes a substrate, having a plan view describable along a first axis and a second axis, and a plurality of transistors provided on an area of the substrate. The first axis and the second axis are orthogonal. Each transistor has a distinct active area. The plurality of transistors consists of a plurality of both p-type and n-type transistors. A first transistor is arranged in a first row containing a second transistor, and the active areas of the first transistor and the second transistor are in a similar orientation as the first axis. A third transistor is arranged in a second row and oriented in a same direction as the first axis. A fourth transistor is arranged in a third row distinct from both the first row and the second row. Compared to the third transistor, the fourth transistor is farther from the first and the second transistors.

Description

ZIPPER-STACKED TRANSISTORS

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. Provisional Application No. 63/518,614, filed August 10, 2023, which is hereby incorporated by reference herein in its entirety.

FIELD OF THE INVENTION

[0002] The present invention relates generally to integrated circuits, and more specifically, to integrated circuits having increased resilience to single-event upsets when compared to traditional integrated circuits.

BACKGROUND OF THE INVENTION

[0003] A single-event upset (SEU) is an unwanted transition at a circuit node. SEUs are changes of state in circuits caused by one single ionizing particle striking a sensitive node in a circuit. Circuits vulnerable to SEUs are said to be susceptible to radiation, and SEUs can cause incorrect outputs or corrupt data included in circuits. Circuits are ubiquitous in today’s society, with microelectronics, microcontrollers, and/or microprocessors being embedded in electronic devices today. Techniques for radiation hardening of circuits used in electronic devices can reduce SEUs, thus enhancing reliability and accuracy associated with the functions of the electronic devices. Radiation hardening techniques can improve reliability in environments with higher-than- normal radiation. For example, radiation hardening techniques can improve reliability of electronic devices in aerospace applications. The present disclosure provides solutions that at least reduce or mitigate effects of radiation on circuits.

SUMMARY OF THE INVENTION

[0004] The term “embodiment” and like terms, e.g., “implementation,” “configuration,” “aspect,” “example,” and “option,” are intended to refer broadly to all of the subject matter of this disclosure and the claims below. Statements containing these terms should be understood not to limit the subject matter described herein or to limit the meaning or scope of the claims below. Embodiments of the present disclosure covered herein are defined by the claims below, not this summary. This summary is a high-level overview of various aspects of the disclosure and introduces some of the concepts that are further described in the Detailed Description section below. This summary is not intended to identify key or essential features of the claimed subject matter. This summary is also not intended to be used in isolation to determine the scope of the claimed subject matter. The subject matter should be understood by reference to appropriate portions of the entire specification of this disclosure, any or all drawings, and each claim.

[0005] According to certain aspects of the present disclosure, an integrated circuit is provided. The integrated circuit includes a substrate describable as having a plan view disposed along a first axis and second axis orthogonal to each other. The integrated circuit further includes a plurality of transistors provided on an area of the substrate, each transistor in the plurality of transistors having separate and distinct active areas. The plurality of transistors includes a plurality of p-type transistors and a plurality of n-type transistors. A first transistor of the plurality of transistors is arranged in a first row containing a second transistor of the plurality of transistors. The active areas of the first transistor and the second transistor are defined in a similar orientation as the first axis. A third transistor of the plurality of transistors is arranged in a second row distinct from the first row, the active area of the third transistor is oriented in a same direction as the first axis, the third transistor is arranged in close proximity to both the first transistor and the second transistor. A fourth transistor of the plurality of transistors is arranged in a third row distinct from both the first row and the second row. A separation between the active area of the fourth transistor and any one of the first transistor or the second transistor is greater than both (i) a separation between the active areas of the third transistor and the first transistor and (ii) a separation between the active areas of the third transistor and the second transistor.

[0006] In an implementation, the area of the substrate is a rectangular area. In an implementation, the fourth transistor and the first transistor are centered around a same axis of symmetry. In an implementation, gates of both of the fourth transistor and the first transistor lie on the same axis of symmetry. In an implementation, the first row and the second row have different heights. In an implementation, the height of the first row is determined by transistor width of a largest transistor in the first row. In an implementation, the plurality of p-type transistors includes the first transistor, the second transistor, and the third transistor; and the plurality of n- type transistors includes the fourth transistor. In an implementation, the plurality of n-type transistors includes the first transistor, the second transistor, and the third transistor; and the plurality of p-type transistors includes the fourth transistor. [0007] In an implementation, no gate of a transistor in the first row shares a same axis of symmetry as a gate of a transistor in the second row. In an implementation, no gate of a transistor in the second row shares a same axis of symmetry as a gate of a transistor in the third row. In an implementation, in the area, gate pitch on the first row and gate pitch on the second row are equal. In an implementation, in the area, poly pitch is twice the gate pitch of either one of the first row or the second row. In an implementation, the first transistor and the third transistor are stacked transistors in a stacked-transistor design. A series connection between the first transistor and the third transistor includes a metal connection oriented in a same direction as the second axis. All transistors can be in the stacked-transistor design. Series connections between adjacent transistors in the stacked-transistor design can include metal connections oriented in a same direction as the second axis.

[0008] In an implementation, a fifth transistor of the plurality of transistors is arranged in a fourth row distinct from the first row, the second row, and the third row. In an implementation, a separation between the active area of the fifth transistor and any one of the first transistor or the second transistor is greater than (i) a separation between the active areas of the third transistor and the first transistor, (ii) a separation between the active areas of the third transistor and the second transistor, and (iii) a separation between the active areas of the fourth transistor and the first transistor. In an implementation, the fifth transistor and the fourth transistor are of the same type. In an implementation, the fifth transistor and the third transistor share the same axis of symmetry. In an implementation, the first row and the second row are adjacent to each other, the third row and the fourth row are adjacent to each other, and a fifth row adjacent to both the second row and the third row separates the third row from the second row, and wherein the fifth row is a routing without any transistors.

[0009] In an implementation, the integrated circuit includes a zipper-stacked DICE flip flop, a zipper-stacked inverter, a zipper-stacked transmission gate, a zipper-stacked D flip flop, a nonstacked DICE flip flop, a non-stacked inverter, a non-stacked transmission gate, a non-stacked D flip flop, or any combination thereof. In an implementation, the integrated circuit is a silicon-on- insulator integrated circuit.

[0010] According to certain aspects of the present disclosure, a method for obtaining a layout for an integrated circuit is provided. The method includes arranging a first plurality of cells in a first row. The first plurality of cells is arranged in a top-down orientation, and each of the first plurality of cells includes a plurality of a first type of transistors and a plurality of a second type of transistors. Each transistor has a separate and distinct active area. The method further includes arranging a second plurality of cells in a second row. The second row partially overlaps with the first row. The second plurality of cells are arranged in a down-top orientation, and each of the second plurality of cells includes a plurality of the first type of transistors and a plurality of the second type of transistors. Each transistor has a separate and distinct active area. A combination of a plurality of the first type of transistors in the first plurality of cells and a plurality of the first type of transistors in the second plurality of cells are arranged in a checkered pattern. The first type can be a p-type and the second type an n-type, or the first type can be an n-type and the second type a p-type.

[0011] In some implementations, the first plurality of cells in the first row and the second plurality of cells in the second row share a well. In some implementations, the combination of the plurality of the first type of transistors in the first plurality of cells and the plurality of the first type of transistors in the second plurality of cells share the well.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee.

[0013] The disclosure, and its advantages and drawings, will be better understood from the following description of representative embodiments together with reference to the accompanying drawings. These drawings depict only representative embodiments, and are therefore not to be considered as limitations on the scope of the various embodiments or claims.

[0014] FIG. 1 illustrates a process for converting a simple inverter 100 to a stacked-transistor inverter 101.

[0015] FIG. 2 illustrates a vertically-spaced stacked-transistor layout configuration applied to the stacked-transistor inverter of FIG. 1.

[0016] FIG. 3 illustrates a horizontally-spaced stacked-transistor layout configuration applied to the stacked-transistor inverter of FIG. 1.

[0017] FIG. 4 illustrates a zipper layout configuration applied to the stacked-transistor inverter of FIG. 1. [0018] FIG. 5 illustrates top-down ray-tracing renderings of the solid angle that a particle must pass through to upset both p-type transistors in the stacked-transistor inverter designs of FIGS. 2 and 4.

[0019] FIG. 6 illustrates head-on ray-tracing renderings of the solid angle that a particle must pass through to upset both p-type transistors in the stacked-transistor inverter designs of FIGS. 2 and 4.

[0020] FIG. 7A illustrates two zipper stacked-transistor inverters.

[0021] FIG. 7B illustrates a single poly overlap of the two zipper stacked-transistor inverters of FIG. 7A.

[0022] FIG. 7C illustrates double poly overlap of the two zipper stacked-transistor inverters of FIG. 7A.

[0023] FIG. 8A illustrates two horizontally-spaced stacked-transistor inverters.

[0024] FIG. 8B illustrates a single poly overlap of the two horizontally-spaced stacked- transistor inverters of FIG. 8A.

[0025] FIG. 9 is a generalized integrated circuit, according to some implementations of the present disclosure.

[0026] FIG. 10 is an example layout showing direction and orientation of cell placement.

[0027] FIG. 11A is a schematic of a D flip flop, according to some implementations of the present disclosure.

[0028] FIG. 1 IB is a layout of a zipper-stacked D flip flop for the schematic of FIG. HA, according to some implementations of the present disclosure.

[0029] FIG. 11C is an area comparison of a vertically-spaced stacked-transistor layout with a zipper-stacked transistor layout using standard cells, according to some implementations of the present disclosure.

[0030] FIG. 12 is a table comparing results of the zipper-stacked D flip flop to other implementations.

[0031] FIG. 13 illustrates layout configurations for inverters used for simulation.

[0032] FIG. 14A illustrates simulation results from MRED for a vertically-spaced stacked- transistor layout configuration for two transistors.

[0033] FIG. 14B illustrates simulation results from MRED for a horizontally-spaced stacked- transistor layout configuration for two transistors. [0034] FIG. 14C illustrates simulation results from MRED for a zipper-stacked layout configuration for two transistors, according to some implementations of the present disclosure.

[0035] FIG. 15 is a graph comparing upset rate vs. critical charge in space station orbit for different layout configurations in FIG. 13.

[0036] FIG. 16 is a graph comparing upset rate vs. critical charge in GPS satellite orbit for different layout configurations in FIG. 13.

[0037] FIG. 17 is a first graph comparing upset rate vs. critical charge in geosynchronous orbit for different layout configurations in FIG. 13.

[0038] FIG. 18 is a second graph comparing upset rate vs. critical charge in geosynchronous orbit for different layout configurations in FIG. 13.

[0039] FIG. 19 is a third graph comparing upset rate vs. critical charge in geosynchronous orbit for different layout configurations in FIG. 13.

DETAILED DESCRIPTION

[0040] Various embodiments are described with reference to the attached figures, where like reference numerals are used throughout the figures to designate similar or equivalent elements. The figures are not necessarily drawn to scale and are provided merely to illustrate aspects and features of the present disclosure. Numerous specific details, relationships, and methods are set forth to provide a full understanding of certain aspects and features of the present disclosure, although one having ordinary skill in the relevant art will recognize that these aspects and features can be practiced without one or more of the specific details, with other relationships, or with other methods. In some instances, well-known structures or operations are not shown in detail for illustrative purposes. The various embodiments disclosed herein are not necessarily limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are necessarily required to implement certain aspects and features of the present disclosure.

[0041] For purposes of the present detailed description, unless specifically disclaimed, and where appropriate, the singular includes the plural and vice versa. The word “including” means “including without limitation.” Moreover, words of approximation, such as “about,” “almost,” “substantially,” “approximately,” and the like, can be used herein to mean “at,” “near,” “nearly at,” “within 3-5% of,” “within acceptable manufacturing tolerances of,” or any logical combination thereof. Similarly, terms “vertical” or “horizontal” are intended to additionally include “within 3- 5% of’ a vertical or horizontal orientation, respectively. Additionally, words of direction, such as “top,” “bottom,” “left,” “right,” “above,” and “below” are intended to relate to the equivalent direction as depicted in a reference illustration; as understood contextually from the object(s) or element(s) being referenced, such as from a commonly used position for the object(s) or element(s); or as otherwise described herein.

[0042] Single-event upsets (SEUs) can introduce errors in circuits, leading to unwanted signal propagation or corruption of memory bits. Circuits affected by SEUs can be unreliable or may require additional circuitry for error correction. These techniques can unnecessarily increase the area of the circuits. In some cases, stacked-transistor designs (i.e., vertically-spaced stacked- transistor designs or horizontally-spaced stacked-transistor designs) are used at vulnerable circuit nodes to reduce effects of SEUs at the vulnerable nodes. Stacked-transistor designs involve replacing transistors at vulnerable circuit nodes with doubled-up transistors. The doubled-up transistors are connected in-series (from drain to source or vice-versa) with electrically connected gate nodes.

[0043] For example, FIG. 1 illustrates a process for converting a simple inverter 100 to a stacked-transistor inverter 101. In FIG. 1, the simple inverter 100 includes a p-type transistor P0 and an n-type transistor NO. The simple inverter 100 takes in an input X and provides an output Y. Functionality of the stacked-transistor inverter 101 is similar to that of the simple inverter 100, that is, the input X is received and the output Y is provided. Compared to the simple inverter 100, the stacked-transistor inverter 101 provides two p-type transistors P0-1 and PO-2 and two n-type transistors N0-1 and NO-2. Converting from the simple inverter 100 to the stacked-inverter 101 involves duplicating P0 to obtain P0-1 and PO-2 and duplicating NO to obtain N0-1 and NO-2. The output Y for the stacked-transistor inverter 101 is more resistant to SEUs compared to the output Y for the simple inverter 100.

[0044] The stacked transistor 101 can be realized on a substrate (e.g., using a bulk silicon process, using a silicon-on-insulator process, etc.) using different layout techniques. FIG. 2 illustrates a layout 200 for a vertically-spaced stacked-transistor design applied to the stacked- transistor inverter 101. A transistor is formed when a polysilicon trace crosses an active area. For example, poly silicon trace 212 crosses active areas 204, 206, 208, and 210. The poly silicon trace 212 crossing the active areas 204, 206, 208, and 210 indicates that the gates of the transistors formed by the crossings are all connected together. In FIG. 2, the polysilicon trace 212 corresponds to the input X (FIG. 1, FIG. 2). The active areas 204 and 206 are situated in a well, in this case, an N-well 202. Transistors formed in the N-well 202 are p-type transistors, and transistors formed outside of the N-well 202 are n-type transistors. The transistors are connected according to the schematic of the stacked-transistor inverter 101 (FIG. 1) to distinguish transistors P0-1, P0-2, N0- 1, and NO-2. The transistor P0-1 is connected to the transistor N0-1 at the output Y, thus a line labeled Y is drawn to show such connection. The transistor P0-1 and PO-2 are connected in series, as indicated by the line 222. Similarly, the transistor N0-1 and NO-2 are connected in series are indicated by the line 224. The power terminal VDD is connected to node 220, and the ground terminal VSS is connected to node 218. Dummy polysilicon 214 and 216 are provided for alignment purposes. The dotted arrow 250 shows a path that a particle must travel to upset both p- type transistors P0-1 and PO-2 to cause an SEU in a SOI process. The layout 200 for the vertically- spaced stacked-transistor design shows an effective inverter cell width of three polysilicon spacing. [0045] FIG. 3 illustrates a layout 300 for a horizontally-spaced stacked-transistor design applied to the stacked-transistor inverter 101. The layout 300 is similar to that of FIG. 2, except, the transistors N0-1 and NO-2 and the transistors P0-1 and PO-2 are situated in the same row. The area consumed by the horizontally-spaced stacked-transistor design of FIG. 3 is greater than that of the vertically-spaced stacked-transistor design. For a similar cell height, the horizontally-spaced stacked-transistor design takes up about twice the area of the vertically-spaced stacked-transistor design. Area can be estimated based on a pitch width of the polysilicon provided in the designs. Reference numbers 3XX correspond to reference numbers 2XX of FIG. 2. The layout 300 includes additional dummy polysilicon 313 and 315 not present in FIG. 2. The polysilicon 312 provided for the gates of the different transistors forms an H-shape and can be described as having multiple polysilicon sections. The dotted arrow 350 shows a path that a particle must travel to upset both p-type transistors P0-1 and PO-2 to cause an SEU. The layout 300 for the horizontally-spaced- stacked-transistor design shows an effective inverter cell width of five poly silicon traces.

[0046] FIG. 4 illustrates a layout 400 for a zipper stacked-transistor design of the stacked- transistor inverter 101, according to some implementations of the present disclosure. Reference numbers 4XX correspond to reference numbers 2XX of FIG. 2. For example, lines 422 and 424 indicate connections, active areas of transistors are indicated by 404, 406, 408, and 410, etc. In the zipper stacked-transistor design of FIG. 4, the p-type transistors are arranged in separate rows, similar to the design of FIG. 2, but the p-type transistor PO-2 is offset from the p-type transistor PO-1. Similarly, the n-type transistors are arranged in separate rows, and the n-type transistor N0- 1 is offset from the n-type transistor NO-2. The offset introduced causes a staggering of the transistors such that the transistors are no longer vertically aligned. The layout 400 for the zipper stacked-transistor design shows an effective inverter cell width of four polysilicon spacing. The dotted arrow 450 shows a path that a particle must travel to upset both p-type transistors PO-1 and PO-2 to cause an SEU. The staggering of transistors reduces the solid angle a particle must travel through to cause an SEU by approximately 60%, compared to the design of FIG. 2. This figure (60%) is idealized for the technology process in which the zipper stacked-transistor design was conceived because the solid angle is correlated to the transistor body thickness.

[0047] FIG. 5 illustrates top-down ray-tracing renderings of the solid angle that a particle must pass through to upset both p-type transistors in the stacked-transistor inverter designs of FIGS. 2 and 4. If a particle with sufficient energy passes through either cone provided in the ray-tracing rendering, the circuit node will be upset. FIG. 6 illustrates head-on ray-tracing renderings of the solid angle that a particle must pass through to upset both p-type transistors in the stacked- transistor inverter designs of FIGS. 2 and 4. As illustrated in FIG. 6, the zipper-stacked design of FIG. 4 results in a solid angle that is about 40% of the volume of that of the vertically-spaced stacked-transistor inverter. Again, this figure (40%) is idealized for the technology process in which the zipper stacked-transistor design was conceived because the solid angle is correlated to the transistor body thickness.

[0048] The zipper-stacked design of FIG. 4 provides advantages when combining zipper- stacked designs. For example, FIG. 7A illustrates two zipper stacked-transistor inverters 700 and 701. The connections (e.g., metal layer connections, associated via connections, etc.) between the transistors are omitted for clarity. In this example, the zipper stacked-transistor inverters 700 and 701 are identical inverter cells. The zipper stacked-transistor inverters 700 and 701 can be placed together to overlap on one polysilicon as provided in FIG. 7B. To achieve optimum area, the zipper stacked-transistor inverters 700 and 701 can overlap across two polysilicon as provided in FIG. 7C. Comparing FIG. 7B and FIG. 7C, area can be reduced as a function of a gate length of a transistor. Thus, in a fully staggered or zippered pattern, cells placed next to each other can overlap, allowing the overall design (e.g., a super cell made up of individual cells) to only add one gate length penalty instead of each cell’s gate length penalty becoming additive. For example, if the two zipper-stacked-transistor inverters 700 and 701 are identical inverter cells connected to create a buffer cell, the buffer cell will show an effective buffer cell width of six polysilicon spacing (FIG. 7C) instead of the seven polysilicon spacing (FIG. 7B). In comparison, using a vertically- spaced stacked-transistor inverter cell (e.g., like that of FIG. 2), a buffer cell will theoretically show an effective buffer cell width of five polysilicon spacing.

[0049] In some implementations, the zipper stacked-transistor inverters 700 and 701 are not identical, allowing for one or more corresponding transistor pairs within the inverter cells to have different transistor widths and/or lengths. FIGS. 7A-7C are merely used as examples to illustrate different cell placement considerations when combining individual cells to create a more complex cell or a more complex design.

[0050] In some implementations, the zipper stacked-transistor designs provide area advantages compared to vertically-spaced stacked-transistor designs. Depending on design of industry standard cells, in particular fixed cell heights, the zipper stacked-transistor designs may not require additional spacing for routing and connecting transistors compared to the vertically-spaced stacked-transistor designs. Typically, to allow space for routing channels, additional polysilicon widths (i.e., dummy polysilicon) are added, thus increasing effective width of the more complex design. These routing channels may be required for vertically-spaced stacked-transistor designs but not the zipper stacked-transistor designs.

[0051] In contrast to FIGS. 7A and 7C, FIG. 8A illustrates two horizontally-spaced stacked- transistor inverters 800 and 801. FIG. 8B illustrates a single poly overlap of the two horizontallyspaced stacked-transistor inverters 800 and 801. The area penalty of each horizontally-spaced stacked-transistor inverter cell is additive in the overall design of FIG. 8B. By overlapping across two polysilicon, as shown in FIG. 7C, zipper stacked-transistor designs can provide area advantages compared to horizontally-spaced stacked-transistor design of FIG. 8B. FIG. 8B shows an effective design cell width of nine poly silicon spacing.

[0052] FIG. 9 illustrates a generalized view of an integrated circuit 900 using the zippered pattern. The integrated circuit 900 includes multiple transistors, for example, a first transistor 902, a second transistor 904, a third transistor 906, a fourth transistor 908, a fifth transistor 910, a sixth transistor 912, a seventh transistor 914, an eighth transistor 916, etc. These transistors are provided on a substrate 918. The substrate 918 can be bulk silicon in some embodiments. The substrate 918 can be silicon-on-insulator in some embodiments. The substrate 918 can be some other material compatible with integrated circuit processing technology.

[0053] A plan view of the substrate can be described along a first axis and a second axis. The first axis and the second axis are orthogonal to each other as provided in FIG. 9. The transistors provided in the integrated circuit have separate and distinct active areas. That is, no two transistors share source/drain diffusion regions. For example, two transistors having a series connection are connected via metal layers instead of fusing diffusion regions of the transistors (see, e.g., 422, 424 of FIG. 4). Lines 422 and 424 of FIG. 4 indicate metal connections are used to connect the diffusion regions of the adjacent transistors.

[0054] An area drawn on the substrate 918 that consists of a plurality of p-type transistors and n-type has certain characteristics. The drawn area can be a polygon, a rectangle, a circle, or some irregular shape. For example, the drawn area can be a right angle triangle that includes the first transistor 902, the second transistor 904, the third transistor 906, and the fourth transistor 908. In some implementations, a rectangular area is preferred.

[0055] In some implementations, within the area drawn on the substrate 918, the first transistor 902, the second transistor 904, the third transistor 906, and the fourth transistor 908 are included. The first transistor 902 is arranged in a first row containing the second transistor 904. The active areas of the first transistor 902 and the second transistor 904 are defined in a similar orientation as the first axis. For example, the transistor PO-2 of FIG. 4 has the active area 404 as a rectangle with the polysilicon trace 412 crossing the active area 404. Orientation of the active area 404 is orthogonal to that of the poly silicon trace 412. That is, orientation of the active area 404 is defined relative to the polysilicon trace 412 that defines the transistor PO-2. In FIG. 4, the active area 404 would be oriented in the first axis as provided in FIG. 9.

[0056] The third transistor 906 is arranged in a second row distinct from the first row. The active area of the third transistor 906 is oriented in a same direction as the first axis. The third transistor 906 is arranged in close proximity to both the first transistor 902 and the second transistor 904. The fourth transistor 908 is arranged in a third row distinct from both the first row and the second row. The separation between the active area of the fourth transistor 908 and any one of the first transistor 902 or the second transistor 904 is greater than both (i) a separation between the active areas of the third transistor 906 and the first transistor 902 and (ii) a separation between the active areas of the third transistor 906 and the second transistor 904.

[0057] In some implementations, the third transistor is arranged in close proximity to both the first transistor and the second transistor. In such an exemplary implementation, the separation between the third transistor 906 and the first transistor 902 is about the same distance as the separation between the first transistor 902 and the second transistor 904. In some implementations, the separation along the first axis between the gate of the third transistor 906 and the gate of the first transistor 902 is smaller than the separation along the first axis between the second transistor 904 and the first transistor 902. That is, the third transistor 906 and the first transistor 902 are separated by fewer polysilicon trace positions along the first axis than the second transistor 904 is separated along the first axis from the first transistor 902. For example, consider the zipper stacked-transistor inverters 700 and 701 from FIG. 7C, where the transistors correspond to those in FIG. 4. Transistor NO-2 of inverter 700, playing the role of the first transistor 902, is separated along axis one by one polysilicon trace from transistor N0-1 of inverter 701 (in this example, the third transistor 904). Transistor NO-2 of inverter 700 (acting as the first transistor 902) is separated by two polysilicon traces along the first axis from transistor NO-2 of inverter 701 (acting as the second transistor 904). In some implementations, the gate of the third transistor 906 is arranged offset from gates of both the first transistor 902 and the second transistor 904. That is, connecting the centers of the first transistor 902, the second transistor 904, and the third transistor 906 with straight lines can result in an acute scalene triangle, an acute isosceles triangle, an obtuse scalene triangle, or an obtuse isosceles triangle. To determine the center of a transistors, the active area of the transistors can be treated as a rectangle, and the center of the transistor is the center of the rectangle.

[0058] In some implementations, the fourth transistor 908 and the third transistor 906 share an axis of symmetry instead of being offset as provided in FIG. 9. For example, the fourth transistor 908 can be positioned between the fifth transistor 910 and the third transistor 906 to share an axis of symmetry that is parallel to the second axis.

[0059] In some implementations, the first transistor 902, the second transistor 904, and the third transistor 906 are p-type transistors, and the fourth transistor 908 is an n-type transistor. In some implementations, the first row and the second row include p-type transistors, and the third row and the fourth row include n-type transistors.

[0060] Alternatively, the first transistor 902, the second transistor 904, and the third transistor 906 are n-type transistors, and the fourth transistor 908 is a p-type transistor. In some implementations, the first row and the second row include n-type transistors, and the third row and the fourth row include p-type transistors.

[0061] To effectuate a reliable zippered pattern, in some implementations, the fourth transistor 908 and the first transistor 902 are centered around a same axis of symmetry. For example, the axis of symmetry can be parallel to the second axis. Similarly, the third transistor 906 and the fifth transistor 910 are centered around a same axis of symmetry. For example, the axis of symmetry can be parallel to the second axis. Transistors that share a same axis of symmetry can have gates that lie on the axis of symmetry. For example, gates of both of the fourth transistor 908 and the first transistor 902 can lie on the same axis of symmetry. For example, this is shown in PO-2 and N0-1 transistors of FIG. 4.

[0062] FIG. 9 is not drawn to scale, thus the first row and the second row can have different heights. Note that row heights are a function of transistor gate widths. For example, a largest transistor width on a row can determine height of the row. The fifth transistor 910 has a transistor width greater than the eighth transistor 916, the first transistor 902, and the second transistor 904. Thus, the height of the fourth row is larger than the height of the first row.

[0063] In some implementations, in a fully zippered pattern, adjacent rows do not have gates that share a same axis of symmetry. For example, as provided in FIG. 9, no gate of a transistor in the first row shares a same axis of symmetry as a gate of a transistor in the second row. The first transistor 902 in the first row does not have a corresponding transistor in the second row that shares an axis of symmetry with the first transistor 902. Similarly, no gate of a transistor in the second row shares a same axis of symmetry as a gate of a transistor in the third row.

[0064] In some implementations, within the drawn area on the substrate 918, gate pitch on the first row and gate pitch on the second row are equal. For example, referring to FIG. 4, poly silicon pitch in the row where the transistor N0-1 is situated is equal to polysilicon pitch in the row where the transistor NO-2 is situated. When looking at the two combined zippered patterns of FIG. 7C, the gate pitch is half that of the polysilicon pitch. That is, on each row, a transistor gate appears at every other polysilicon location. Although gate pitch and polysilicon pitch are different, the example of FIG. 7C shows how gate pitch can be the same between two rows of transistors.

[0065] In some implementations, the integrated circuit of FIG. 9 includes a stacked-transistor design, where the first transistor 902 and the third transistor 906 are stacked transistors in the stacked-transistor design. A series connection between the first transistor 902 and the third transistor 906 includes a metal connection oriented in a same direction as the second axis. An example of this is provided in FIG. 4 where 422 indicates a metal connection used to connect the diffusion regions of transistor PO-1 and PO-2. Thus, in some cases, the series connection between the first transistor 902 and the third transistor 906 consists of a metal connection oriented in the same direction as the second axis and any vias necessary to make the connections to the diffusion regions.

[0066] In some implementations, the first row and the second row are adjacent to each other, and the third row and the fourth row are adjacent to each other. A fifth row can be inserted. The fifth row can be adjacent to both the second row and the third row, separating the third row from the second row. The fifth row can be used for routing such that no transistors are placed in the fifth row. For example, in FIG. 4, the spacing between transistors PO-1 and NO-1 can be designated as the fifth row if the transistor NO-1 is in the second row and transistor PO-1 is in the third row.

[0067] Embodiments of the present disclosure provide at least a method for transistor and/or cell placement. In some implementations, the method includes arranging a first plurality of cells in a first row. The first plurality of cells is arranged in a top-down orientation, and each of the first plurality of cells includes a plurality of a first type of transistors and a plurality of a second type of transistors. Each transistor has separate and distinct active areas. For example, referring to FIG. 10, a top-down orientation is provided in row 1, where p-type transistors are positioned at the top of the row and n-type transistors are positioned at the bottom of the row. The top of row 1 is indicated with label 1001a and contains p-type transistors, and the bottom of row 1 is indicated with label 1002a and contains n-type transistors.

[0068] The method further includes arranging a second plurality of cells in a second row. The second row can be partially overlapping with the first row, for example, to share wells (e.g., to share an N-well) or to share polysilicon traces. The second plurality of cells is arranged in a down- top orientation. The down-top orientation is the opposite of the top-down orientation. Each of the second plurality of cells includes a plurality of the first type of transistors and a plurality of the second type of transistors. For example, in FIG. 10, row 2 provides n-type transistors at the top of the row and p-type transistors at the bottom of the row. The top of row 2 is indicated with label 1001b and contains n-type transistors, and the bottom of row 2 is indicated with label 1002b and contains p-type transistors.

[0069] In some implementations, row 3 and row 4 can be provided with similar label indications 1001c and 1002c indicating top of row 3 and bottom of row 3, respectively, and lOOld and 1002d indicating top of row 4 and bottom of row 4, respectively. The rows can be placed in alternating top-down and down-top configurations to facilitate well-sharing, poly-sharing, etc.

[0070] A combination of a plurality of the first type of transistors in the first plurality of cells and a plurality of the first type of transistors in the second plurality of cells are arranged in a checkered pattern. For example, when looking at the transition between rows 1 and 2, rows 2 and 3, and rows 3 and 4, the transistors at these transitions are placed in a zippered pattern such that in four consecutive rows, there are single transistors spaced out and staggered to resemble the checkered pattern. FIG. 10 does not show poly-sharing and well sharing across rows, but row 1 and row 2 can be placed such that the poly silicon pitch aligns and the polysilicon partially overlaps. [0071] In alternative configurations, in FIG. 9, gates of one or more of the first transistor 902, the second transistor 904, the third transistor 906, the fourth transistor 908, the fifth transistor 910, the sixth transistor 912, the seventh transistor 914, or the eighth transistor 916 is oriented along the first axis and not the second axis. As discussed above, orientation of the gate is orthogonal to orientation of the active area, therefore, any one of these transistors’ active areas can be oriented along the second axis.

[0072] Some implementations of the present disclosure have been provided for design of inverters. Inverters are not the only circuit components that can benefit from techniques provided in the present disclosure. Integrated circuits of various types, including DICE flip flops, flip flops (e g., D flip flop), transmission gates, a zipper-stacked transmission gate, a zipper-stacked D flip flop, a non-stacked DICE flip flop, a non-stacked inverter, a non-stacked transmission gate, a nonstacked D flip flop, or any combination thereof, can use the techniques. In an example, FIG. 1 IB illustrates a layout for a zipper-stacked D flip flop circuit. FIG. 11 A provides the schematic for the D flip flop circuit of FIG. 1 IB. FIG. 12 includes results associated with the zipper-stacked D flip flop circuit compared to other circuit implementations. The results in FIG. 12 correspond to the implementation provided in FIG. 1 IB showing that the zipper-stacked D flip flop provides an area penalty of about 1 ,6X compared to the vertically-spaced stacked-transistor D flip flop area penalty of about 1.55X. This translates to an area penalty of 1 gate length with 40% reduction of solid angle of vertically-spaced stacked-transistor design. As discussed previously, this area penalty is removed when neighboring zipper stacked-transistor designs are interconnected as in FIG. 7C.

[0073] FIG. 11C compares a vertically-spaced stacked-transistor layout to a zipper-stacked transistor layout using a fixed cell height and fixed transistor sizes. As can be seen in FIG. 11C, the vertically-spaced stacked-transistor design is less area efficient compared to the zipper-stacked design and requires additional routing channels 1110. These additional routing channels 1110 make the effective width of the D flip flop 24 poly silicon spacing (or poly silicon tracks). Because the additional routing channels 1110 are not required in the zipper-stacked design, the zipper- stacked design has a smaller area due to the effective width of the D flip flop being 22 poly silicon spacing (or polysilicon tracks). Although theoretically, the vertically-spaced stacked-transistor design should consume a smaller area, practically layout rules and routing considerations can result in the vertically-spaced stacked- transistor design consuming a larger area. The zipper-stacked transistor of FIG. 11C was generated in a 45 nm silicon-on-insulator technology process, and resulted in around an 8% area savings compared to the vertically-spaced stacked-transistor counterpart. The horizontal offset of the transistors in the zipper configuration results in more optimized area for routing compared to the vertically-spaced stacked-transistor design.

[0074] Furthermore, in FIG. 11C the zipper-stacked design can be described as having a first grid of transistors interleaved with a second grid of transistors. For example, transistors 1120a and 1120b exist on a first grid and share a same axis of symmetry around their shared polysilicon gate. Transistors 1124b and 1124a exist on the first grid as well and share a same axis of symmetry around their shared polysilicon gate. As such, the first grid contains transistors along the same rows as the transistors 1120a, 1120b, 1124a, and 1124b. Transistors 1122a and 1122b exist on the second grid and share a same axis of symmetry around their shared polysilicon gate. The second grid contains transistors along the same rows as the transistors 1122a and 1122b. A method of laying out transistors to obtain the zipper-stacked design of FIG. 11C can involve interleaving the first grid of transistors with the second grid of transistors. FIG. 11C is used here as an example to describe the layout of the transistors, but in some circuit designs, fewer (or more) transistors than included in FIG. 11C are arranged in the first and/or the second grids.

[0075] FIG. 13 illustrates layout configurations for inverters used to generate simulation results provided in FIGS. 14-19. “Stacked inverter schematic” is the same as the stacked-transistor inverter 101 of FIG. 1. “Vertical scheme” is similar to the layout of FIG. 2, “horizontal scheme” is similar to the layout of FIG. 3, and “zipper scheme” is similar to the layout of FIG. 4. The unhardened design corresponds to the simple inverter 100 of FIG. 1. Simulation results were generated in the MRED program. MRED is a physics-based Monte Carlo radiation transport simulation tool developed at Vanderbilt and can be used to predict charge deposition within transistor pairs arranged using different layout techniques. Active silicon volumes representative of the PMOS devices in the stacked-transistor pairs were used to predict the charge deposition within the transistor bodies. Several environments were simulated as provided in the following. No trapped protons are considered in the following MRED simulations.

[0076] FIG. 14A illustrates 10 million isotropic 500 MeV Fe particle simulation results from MRED for a vertically-spaced stacked-transistor layout configuration for two transistors. Data points are where a single particle struck and generated charge within both transistors. For example, for the vertical scheme inverter in FIG. 2, “both transistors” would be P0-1 and PO-2. Dashed lines in Fig. 14 represent maximum observed charge. The vertical layout shows 25 strikes where charge was generated within both transistors. The amount of charge generated in one transistor is indicated in femto-Coulombs (fC) on one axis, and the amount of charge generated in the other transistor is indicated in fC on the other axis. For example, 2 fC is generated in transistor 1 while 40 fC is generated in transistor 2 for the strike 1402.

[0077] FIG. 14B illustrates 10 million isotropic 500 MeV Fe particle simulation results from MRED for a horizontally-spaced stacked-transistor layout configuration for two transistors. The two transistors in this case would be, for example, P0-1 and PO-2 in FIG. 3. Compared to FIG. 14 A, FIG. 14B has more strikes (240 strikes), but the magnitude of charge generated in the transistors for these increased number of strikes is smaller than that of FIG. 14A.

[0078] FIG. 14C illustrates 10 million isotropic 500 MeV Fe particle simulation results from MRED for a zipper-stacked layout configuration for two transistors, according to some implementations of the present disclosure. The two transistors in this case would be, for example, P0-1 and PO-2 in FIG. 4. Compared to FIG. 14A, FIG. 14C has more strikes (48 strikes), but the magnitude of charge generated in the transistors for these increased number of strikes is smaller than that of FIG. 14A. The magnitude in FIG. 14C is about half of that in FIG. 14A. In both number of strikes and charge magnitude, FIG. 14C sits intermediate to FIGS. 14A and 14B.

[0079] FIG. 15 is a graph comparing upset rate vs. critical charge for 20 million isotropic particles in a space station orbit for different layout configurations in FIG. 13. CREME96 is a tool used for upset rate prediction. The CREME96 curve is used to verify credibility of MRED simulation. FIGS. 15-19 show that the zipper-stacked scheme achieves an area savings with virtually no radiation hardness penalties relative to the other stacked layouts. As provided in FIGS. 15-19, the stacked layouts are orders of magnitude better than the unhardened layout. [0080] FIG. 16 is a graph comparing upset rate vs. critical charge for 20 million isotropic particles in a GPS satellite orbit for different layout configurations in FIG. 13. As shown in FIG. 16, the horizontal layout, zipper layout, and vertical layout have a similar shape and similar upset rate even though the zipper layout is more area efficient. FIG. 17 is a first graph comparing upset rate vs. critical charge for 20 million isotropic particles in a geosynchronous orbit for different layout configurations in FIG. 13. As shown in FIG. 17, the horizontal layout, zipper layout, and vertical layout have a similar shape and similar upset rate even though the zipper layout is more area efficient. As shown in FIG. 18, a second graph comparing upset rate vs. critical charge for 20 million isotropic particles in a geosynchronous orbit is provided for the different layout configurations in FIG. 13. In FIG. 18, the Al shielding is thicker compared to FIG. 17, thus, the upset rate profile is slightly improved on the logarithmic plot with FIG. 18 having overall lower upset rate magnitudes. FIG. 19 is a third graph comparing upset rate vs. critical charge for 20 million isotropic particles in a geosynchronous orbit for different layout configurations in FIG. 13. FIG. 19 has a different scale due to the solar flare. The upset rate profile is worse due to the solar flare, thus higher upset rate magnitudes.

[0081] Some implementations of the present disclosure provide arrangement of transistors’ active areas in a diagonally-staggered, interleavable “zippered” pattern (see, e.g., FIG. 1 IB, 11C). The diagonally-staggered active areas can result in over 50% reduction in the solid angle necessary to cause an SEU when compared to traditional stacked transistor implementations. Often, great effort is spent to reduce the effective cross sections of circuit designs. The effective cross section is a function of the solid angle, so any reduction in the solid angle is an improvement. The interleavable nature of zipper pattern allows resulting designs to theoretically be 1 single transistor's gate length larger than a standard stacked implementation. For example, for a standard stacked implementation using 10 gate lengths, arrangement of transistors according to some implementations of the present disclosure can use 10+1 gate lengths, resulting in a 10% area penalty. For a standard stacked implementation using 100 gate lengths, arrangement of transistors according to some implementations of the present disclosure can use 100+1 gate lengths, a 1% area penalty. In the context of billions of transistors on modem integrated circuits, the size of 1 extra transistor is negligible. As provided above in FIG. 11C, design rules from semiconductor foundries or industry standards can result in needing to add routing channels, thus rendering the standard stacked implementation less area efficient compared to the diagonally-positioned implementation. Therefore, when real-world non-idealities are considered, a diagonally-positioned implementation can achieve a smaller area than the standard stacked implementation while providing a similar radiation hardness performance.

[0082] Some implementations of the present disclosure can be used in applications for space or terrestrial aerospace integrated circuits. Those circuits are more sensitive and currently implement other more penalizing methods of reducing the SEU rate. Some implementations of the present disclosure can be used in integrated circuit devices that monitor nuclear reactors or that are situated in environments exhibiting higher than normal radiation, such as airplane circuitry.

[0083] Although the disclosed embodiments have been illustrated and described with respect to one or more implementations, equivalent alterations and modifications will occur or be known to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application.

[0084] While various embodiments of the present disclosure have been described above, it should be understood that they have been presented by way of example only, and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein, without departing from the spirit or scope of the disclosure. Thus, the breadth and scope of the present disclosure should not be limited by any of the above described embodiments. Rather, the scope of the disclosure should be defined in accordance with the following claims and their equivalents.

ALTERNATIVE IMPLEMENTATIONS

[0085] Alternative implementation 1. An integrated circuit comprising: (a) a substrate having a plan view describable along a first axis and a second axis, the first axis and the second axis being orthogonal to each other; and (b) a plurality of transistors provided on an area of the substrate, each transistor in the plurality of transistors having separate and distinct active areas, the plurality of transistors consisting of a plurality of p-type transistors and a plurality of n-type transistors, wherein: (i) a first transistor of the plurality of transistors is arranged in a first row containing a second transistor of the plurality of transistors, the active areas of the first transistor and the second transistor are defined in a similar orientation as the first axis; (ii) a third transistor of the plurality of transistors is arranged in a second row distinct from the first row, the active area of the third transistor is oriented in a same direction as the first axis, the third transistor arranged in close proximity to both the first transistor and the second transistor; and (iii) a fourth transistor of the plurality of transistors is arranged in a third row distinct from both the first row and the second row, a separation between the active area of the fourth transistor and any one of the first transistor or the second transistor is greater than both (i) a separation between the active areas of the third transistor and the first transistor and (ii) a separation between the active areas of the third transistor and the second transistor.

[0086] Alternative implementation 2. The integrated circuit of alternative implementation 1, wherein the area of the substrate is a rectangular area.

[0087] Alternative implementation 3. The integrated circuit of alternative implementation 1 or alternative implementation 2, wherein the fourth transistor and the first transistor are centered around a same axis of symmetry.

[0088] Alternative implementation 4. The integrated circuit of alternative implementation 3, wherein gates of both of the fourth transistor and the first transistor lie on the same axis of symmetry.

[0089] Alternative implementation 5. The integrated circuit of any one of alternative implementations 1 to 4, wherein the first row and the second row have different heights.

[0090] Alternative implementation 6. The integrated circuit of alternative implementation 5, wherein the height of the first row is determined by transistor width of a largest transistor in the first row.

[0091] Alternative implementation 7. The integrated circuit of any one of alternative implementations 1 to 6, wherein: the plurality of p-type transistors includes the first transistor, the second transistor, and the third transistor; and the plurality of n-type transistors includes the fourth transistor.

[0092] Alternative implementation 8. The integrated circuit of any one of alternative implementations 1 to 6, wherein: the plurality of n-type transistors includes the first transistor, the second transistor, and the third transistor; and the plurality of p-type transistors includes the fourth transistor.

[0093] Alternative implementation 9. The integrated circuit of any one of alternative implementations 1 to 8, wherein no gate of a transistor in the first row shares a same axis of symmetry as a gate of a transistor in the second row.

[0094] Alternative implementation 10. The integrated circuit of any one of alternative implementations 1 to 9, wherein no gate of a transistor in the second row shares a same axis of symmetry as a gate of a transistor in the third row.

[0095] Alternative implementation 11 The integrated circuit of any one of alternative implementations 1 to 10, wherein in the area, gate pitch on the first row and gate pitch on the second row are equal.

[0096] Alternative implementation 12. The integrated circuit of any one of alternative implementations 1 to 11, wherein in the area, poly pitch is twice the gate pitch of either one of the first row or the second row.

[0097] Alternative implementation 13. The integrated circuit of any one of alternative implementations 1 to 12, wherein the first transistor and the third transistor are stacked transistors in a stacked-transistor design, a series connection between the first transistor and the third transistor including a metal connection oriented in a same direction as the second axis.

[0098] Alternative implementation 14. The integrated circuit of alternative implementation

13, wherein all transistors are in the stacked-transistor design.

[0099] Alternative implementation 15. The integrated circuit of alternative implementation

14, wherein series connections between adjacent transistors in the stacked-transistor design include metal connections oriented in a same direction as the second axis.

[00100] Alternative implementation 16. The integrated circuit of any one of alternative implementations 1 to 15, wherein a fifth transistor of the plurality of transistors is arranged in a fourth row distinct from the first row, the second row, and the third row, a separation between the active area of the fifth transistor and any one of the first transistor or the second transistor is greater than (i) a separation between the active areas of the third transistor and the first transistor, (ii) a separation between the active areas of the third transistor and the second transistor, and (iii) a separation between the active areas of the fourth transistor and the first transistor.

[00101] Alternative implementation 17 The integrated circuit of alternative implementation 16, wherein the fifth transistor and the fourth transistor are of the same type.

[00102] Alternative implementation 18. The integrated circuit of alternative implementation 16 or alternative implementation 17, wherein the fifth transistor and the third transistor share the same axis of symmetry. [00103] Alternative implementation 19. The integrated circuit of any one of alternative implementations 16 to 18, wherein the first row and the second row are adjacent to each other, the third row and the fourth row are adjacent to each other, and a fifth row adjacent to both the second row and the third row separates the third row from the second row, and wherein the fifth row is a routing row without any transistors.

[00104] Alternative implementation 20. The integrated circuit of any one of alternative implementations 1 to 19, wherein the integrated circuit includes a zipper-stacked DICE flip flop, a zipper-stacked inverter, a zipper-stacked transmission gate, a zipper-stacked D flip flop, a nonstacked DICE flip flop, a non-stacked inverter, a non-stacked transmission gate, a non-stacked D flip flop, or any combination thereof.

[00105] Alternative implementation 21. The integrated circuit of any one of alternative implementations 1 to 20, wherein the integrated circuit is a silicon-on-insulator integrated circuit. [00106] Alternative implementation 22. A method for obtaining a layout for an integrated circuit, comprising: (a) arranging a first plurality of cells in a first row, the first plurality of cells arranged in a top-down orientation, and each of the first plurality of cells including a plurality of a first type of transistors and a plurality of a second type of transistors, each transistor having separate and distinct active areas; and (b) arranging a second plurality of cells in a second row, the second row partially overlapping with the first row, the second plurality of cells arranged in a down-top orientation, and each of the second plurality of cells including a plurality of the first type of transistors and a plurality of the second type of transistors, each transistor having separate and distinct active areas; wherein a combination of a plurality of the first type of transistors in the first plurality of cells and a plurality of the first type of transistors in the second plurality of cells are arranged in a checkered pattern; wherein (i) the first type is a p-type and the second type is an n- type, or (ii) the first type is an n-type and the second type is a p-type.

[00107] Alternative implementation 23. The method of alternative implementation 22, wherein the first plurality of cells in the first row and the second plurality of cells in the second row share a well.

[00108] Alternative implementation 24. The method of alternative implementation 22 or alternative implementation 23, wherein the combination of the plurality of the first type of transistors in the first plurality of cells and the plurality of the first type of transistors in the second plurality of cells share the well. [00109] Alternative implementation 25. A method for integrated circuit layout comprising: (a) placing a first plurality of transistors in a first grid, the first grid having at least a first row and a second row, such that a first transistor is placed in the first row and a second transistor is placed in the second row; (b) placing a second plurality of transistors in a second grid, the second grid having at least a third row, such that a third transistor is placed on the third row; and (c) interleaving the first grid and the second grid, such that the first transistor and the second transistor share a first axis of symmetry and the third transistor has a separate axis of symmetry, the first transistor being a first-type transistor and the second and third transistors being second-type transistors.

Claims

CLAIMS What is claimed is:

1. An integrated circuit comprising: a substrate having a plan view describable along a first axis and a second axis, the first axis and the second axis being orthogonal to each other; and a plurality of transistors provided on an area of the substrate, each transistor in the plurality of transistors having separate and distinct active areas, the plurality of transistors consisting of: a plurality of p-type transistors and a plurality of n-type transistors, wherein: a first transistor of the plurality of transistors is arranged in a first row containing a second transistor of the plurality of transistors, the active areas of the first transistor and the second transistor are defined in a similar orientation as the first axis; a third transistor of the plurality of transistors is arranged in a second row distinct from the first row, the active area of the third transistor is oriented in a same direction as the first axis, the third transistor arranged in close proximity to both the first transistor and the second transistor; and a fourth transistor of the plurality of transistors is arranged in a third row distinct from both the first row and the second row, a separation between the active area of the fourth transistor and any one of the first transistor or the second transistor is greater than both (i) a separation between the active areas of the third transistor and the first transistor and (ii) a separation between the active areas of the third transistor and the second transistor.

2. The integrated circuit of claim 1, wherein the area of the substrate is a rectangular area.

3. The integrated circuit of claim 1, wherein the fourth transistor and the first transistor are centered around a same axis of symmetry.

4. The integrated circuit of claim 3, wherein gates of both of the fourth transistor and the first transistor lie on the same axis of symmetry.

5. The integrated circuit of claim 1, wherein the first row and the second row have different heights.

6. The integrated circuit of claim 5, wherein the height of the first row is determined by transistor width of a largest transistor in the first row.

7. The integrated circuit of claim 1, wherein: the plurality of p-type transistors includes the first transistor, the second transistor, and the third transistor; and the plurality of n-type transistors includes the fourth transistor.

8. The integrated circuit of claim 1, wherein: the plurality of n-type transistors includes the first transistor, the second transistor, and the third transistor; and the plurality of p-type transistors includes the fourth transistor.

9. The integrated circuit of claim 1, wherein no gate of a transistor in the first row shares a same axis of symmetry as a gate of a transistor in the second row.

10. The integrated circuit of claim 1, wherein no gate of a transistor in the second row shares a same axis of symmetry as a gate of a transistor in the third row.

11. The integrated circuit of claim 1, wherein in the area, gate pitch on the first row and gate pitch on the second row are equal.

12. The integrated circuit of claim 1, wherein in the area, poly pitch is twice the gate pitch of either one of the first row or the second row.

13. The integrated circuit of claim 1, wherein the first transistor and the third transistor are stacked transistors in a stacked-transistor design, a series connection between the first transistor and the third transistor including a metal connection oriented in a same direction as the second axis.

14. The integrated circuit of claim 13, wherein all transistors are in the stacked-transistor design.

15. The integrated circuit of claim 14, wherein series connections between adjacent transistors in the stacked-transistor design include metal connections oriented in a same direction as the second axis.

16. The integrated circuit of any one of claims 1 to 15, wherein a fifth transistor of the plurality of transistors is arranged in a fourth row distinct from the first row, the second row, and the third row, a separation between the active area of the fifth transistor and any one of the first transistor or the second transistor is greater than (i) a separation between the active areas of the third transistor and the first transistor, (ii) a separation between the active areas of the third transistor and the second transistor, and (iii) a separation between the active areas of the fourth transistor and the first transistor.

17. The integrated circuit of claim 16, wherein the fifth transistor and the fourth transistor are of the same type.

18. The integrated circuit of claim 16, wherein the fifth transistor and the third transistor share the same axis of symmetry.

19. The integrated circuit of claim 16, wherein the first row and the second row are adjacent to each other, the third row and the fourth row are adjacent to each other, and a fifth row adjacent to both the second row and the third row separates the third row from the second row, and wherein the fifth row is a routing row without any transistors.

20. The integrated circuit of claim 1, wherein the integrated circuit includes a zipper-stacked DICE flip flop, a zipper-stacked inverter, a zipper-stacked transmission gate, a zipper-stacked D flip flop, a non-stacked DICE flip flop, a non-stacked inverter, a non-stacked transmission gate, a non-stacked D flip flop, or any combination thereof.

21. The integrated circuit of claim 1, wherein the integrated circuit is a silicon-on-insulator integrated circuit.

22. A method for obtaining a layout for an integrated circuit, comprising: arranging a first plurality of cells in a first row, the first plurality of cells arranged in a top- down orientation, and each of the first plurality of cells including a plurality of a first type of transistors and a plurality of a second type of transistors, each transistor having separate and distinct active areas; and arranging a second plurality of cells in a second row, the second row partially overlapping with the first row, the second plurality of cells arranged in a down-top orientation, and each of the second plurality of cells including a plurality of the first type of transistors and a plurality of the second type of transistors, each transistor having separate and distinct active areas; wherein a combination of a plurality of the first type of transistors in the first plurality of cells and a plurality of the first type of transistors in the second plurality of cells are arranged in a checkered pattern; wherein (i) the first type is a p-type and the second type is an n-type, or (ii) the first type is an n-type and the second type is a p-type.

23. The method of claim 22, wherein the first plurality of cells in the first row and the second plurality of cells in the second row share a well.

24. The method of claim 22 or claim 23, wherein the combination of the plurality of the first type of transistors in the first plurality of cells and the plurality of the first type of transistors in the second plurality of cells share the well.

5. A method for integrated circuit layout comprising: placing a first plurality of transistors in a first grid, the first grid having at least a first row and a second row, such that a first transistor is placed in the first row and a second transistor is placed in the second row; placing a second plurality of transistors in a second grid, the second grid having at least a third row, such that a third transistor is placed on the third row; and interleaving the first grid and the second grid, such that the first transistor and the second transistor share a first axis of symmetry and the third transistor has a separate axis of symmetry, the first transistor being a first-type transistor and the second and third transistors being second-type transistors.