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WO2025032987A1 - Photodétecteur et appareil électronique - Google Patents

Photodétecteur et appareil électronique Download PDF

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Publication number
WO2025032987A1
WO2025032987A1 PCT/JP2024/022686 JP2024022686W WO2025032987A1 WO 2025032987 A1 WO2025032987 A1 WO 2025032987A1 JP 2024022686 W JP2024022686 W JP 2024022686W WO 2025032987 A1 WO2025032987 A1 WO 2025032987A1
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WIPO (PCT)
Prior art keywords
transistor
pixel
semiconductor layer
region
semiconductor region
Prior art date
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PCT/JP2024/022686
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English (en)
Japanese (ja)
Inventor
翔一 田路
悠介 大竹
表徳 遠藤
秀俊 大石
純一 松尾
央 大長
和弘 米田
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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Publication of WO2025032987A1 publication Critical patent/WO2025032987A1/fr
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Definitions

  • This disclosure relates to a light detection device and electronic equipment.
  • An image sensor has been proposed that has multiple unit pixels, each of which includes a photoelectric conversion element, a transmission transistor, a reset transistor, a selection transistor, and a drive transistor (Patent Document 1).
  • a photodetector includes a semiconductor layer, a plurality of pixels including a first pixel having a photoelectric conversion element provided in the semiconductor layer, and a trench provided in the semiconductor layer between adjacent pixels.
  • the first pixel includes a transistor provided on a first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region.
  • the first semiconductor region is provided adjacent to the transistor.
  • the transistor has a gate electrode provided on the first surface side of the semiconductor layer so as to sandwich a portion of the semiconductor layer.
  • a photodetector includes a semiconductor layer, a plurality of pixels including a first pixel having a first photoelectric conversion element and a second photoelectric conversion element provided in the semiconductor layer, and a trench provided in the semiconductor layer between the plurality of adjacent pixels.
  • the first pixel includes a first transistor and a second transistor provided on a first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region.
  • the first semiconductor region is provided adjacent to the first transistor and the second transistor.
  • the first transistor has a gate electrode provided on the first surface side of the semiconductor layer so as to sandwich a part of the semiconductor layer.
  • An electronic device includes an optical system and a photodetector that receives light transmitted through the optical system.
  • the photodetector includes a semiconductor layer, a plurality of pixels including a first pixel having a photoelectric conversion element provided in the semiconductor layer, and a trench provided in the semiconductor layer between the plurality of adjacent pixels.
  • the first pixel includes a transistor provided on a first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region.
  • the first semiconductor region is provided adjacent to the transistor.
  • the transistor has a gate electrode provided on the first surface side of the semiconductor layer so as to sandwich a part of the semiconductor layer.
  • An electronic device includes an optical system and a photodetector that receives light transmitted through the optical system.
  • the photodetector includes a semiconductor layer, a plurality of pixels including a first pixel having a first photoelectric conversion element and a second photoelectric conversion element provided in the semiconductor layer, and a trench provided in the semiconductor layer between the plurality of adjacent pixels.
  • the first pixel includes a first transistor and a second transistor provided on a first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region.
  • the first semiconductor region is provided adjacent to the first transistor and the second transistor.
  • the first transistor has a gate electrode provided on the first surface side of the semiconductor layer so as to sandwich a part of the semiconductor layer.
  • FIG. 1 is a block diagram illustrating an example of a schematic configuration of an imaging device which is an example of a light detection device according to a first embodiment of the present disclosure.
  • FIG. 2 is a diagram illustrating an example of pixel arrangement in the imaging device according to the first embodiment of the present disclosure.
  • FIG. 3 is a diagram for explaining an example of a circuit configuration of a pixel of the imaging device according to the first embodiment of the present disclosure.
  • FIG. 4A is a diagram for explaining another example of a circuit configuration of a pixel of the imaging device according to the first embodiment of the present disclosure.
  • FIG. 4B is a diagram for explaining another example of the circuit configuration of a pixel of the imaging device according to the first embodiment of the present disclosure.
  • FIG. 1 is a block diagram illustrating an example of a schematic configuration of an imaging device which is an example of a light detection device according to a first embodiment of the present disclosure.
  • FIG. 2 is a diagram illustrating an example of pixel arrangement in the imaging device according to the first
  • FIG. 5 is a diagram illustrating an example of a planar configuration of a pixel of the imaging device according to the first embodiment of the present disclosure.
  • FIG. 6 is a diagram for explaining an example of a cross-sectional configuration of a pixel of the imaging device according to the first embodiment of the present disclosure.
  • FIG. 7 is a diagram illustrating an example of an arrangement of pixel transistors in the imaging device according to the first embodiment of the present disclosure.
  • FIG. 8 is a diagram illustrating an example of an arrangement of pixel transistors in the imaging device according to the first embodiment of the present disclosure.
  • FIG. 9 is a diagram illustrating an example of a cross-sectional configuration of the imaging device according to the first embodiment of the present disclosure.
  • FIG. 10A is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to a first modification of the present disclosure.
  • FIG. 10B is a diagram illustrating an example of a cross-sectional configuration of a pixel of an imaging device according to Modification 1 of the present disclosure.
  • FIG. 11A is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to a second modification of the present disclosure.
  • FIG. 11B is a diagram illustrating an example of a cross-sectional configuration of a pixel of an imaging device according to Modification 2 of the present disclosure.
  • FIG. 12A is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to a third modification of the present disclosure.
  • FIG. 12A is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to a third modification of the present disclosure.
  • FIG. 12B is a diagram illustrating an example of a cross-sectional configuration of a pixel of an imaging device according to Modification 3 of the present disclosure.
  • FIG. 13A is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to a fourth modification of the present disclosure.
  • FIG. 13B is a diagram illustrating an example of a cross-sectional configuration of a pixel of an imaging device according to Modification 4 of the present disclosure.
  • FIG. 14 is a diagram showing another example of the planar configuration of pixels in an imaging device according to the fourth modification of the present disclosure.
  • FIG. 15A is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to a fifth modification of the present disclosure.
  • FIG. 15B is a diagram illustrating an example of a cross-sectional configuration of a pixel of an imaging device according to Modification 5 of the present disclosure.
  • FIG. 16A is a diagram for explaining another example configuration of a pixel of an imaging device according to the fifth modification of the present disclosure.
  • FIG. 16B is a diagram for explaining another example configuration of a pixel of an imaging device according to the fifth modification of the present disclosure.
  • FIG. 17 is a diagram for explaining an example of the configuration of a pixel of an imaging device according to the sixth modification of the present disclosure.
  • FIG. 18 is a diagram for explaining an example of the configuration of a pixel of an imaging device according to the seventh modification of the present disclosure.
  • FIG. 16A is a diagram for explaining another example configuration of a pixel of an imaging device according to the fifth modification of the present disclosure.
  • FIG. 16B is a diagram for explaining another example configuration of a pixel of an imaging device according to the fifth modification of the present disclosure.
  • FIG. 17 is a diagram
  • FIG. 19A is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to Modification 8 of the present disclosure.
  • FIG. 19B is a diagram illustrating an example of a cross-sectional configuration of a pixel of an imaging device according to Modification Example 8 of the present disclosure.
  • FIG. 20A is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to a ninth modification of the present disclosure.
  • FIG. 20B is a diagram showing an example of a cross-sectional configuration of a pixel of an imaging device according to Modification 9 of the present disclosure.
  • FIG. 21 is a diagram illustrating an example of pixel arrangement in an imaging device according to the second embodiment of the present disclosure.
  • FIG. 22 is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to the second embodiment of the present disclosure.
  • FIG. 23 is a diagram for explaining an example of the configuration of a pixel of an imaging device according to a tenth modification of the present disclosure.
  • FIG. 24 is a diagram for explaining an example of the configuration of a pixel of an imaging device according to the eleventh modification of the present disclosure.
  • FIG. 25 is a diagram for explaining another example configuration of a pixel of an imaging device according to the eleventh modification of the present disclosure.
  • FIG. 26 is a diagram for explaining an example of the configuration of a pixel of an imaging device according to Modification 12 of the present disclosure.
  • FIG. 27 is a diagram for explaining another example configuration of a pixel of an imaging device according to the twelfth modification of the present disclosure.
  • FIG. 28 is a diagram for explaining an example of the configuration of a pixel of an imaging device according to the thirteenth modification of the present disclosure.
  • FIG. 29 is a diagram for explaining an example of the configuration of a pixel of an imaging device according to a fourteenth modification of the present disclosure.
  • FIG. 30 is a diagram for explaining an example of the configuration of a pixel of an imaging device according to a fifteenth modification of the present disclosure.
  • FIG. 31 is a diagram for explaining another example configuration of a pixel of an imaging device according to the fifteenth modification of the present disclosure.
  • FIG. FIG. 28 is a diagram for explaining an example of the configuration of a pixel of an imaging device according to the thirteenth modification of the present disclosure.
  • FIG. 29 is a diagram for explaining an example of the configuration of a pixel of an imaging device according to a fourteenth modification of the present disclosure.
  • FIG. 32 is a diagram for explaining a configuration example of an imaging device according to a third embodiment of the present disclosure.
  • FIG. 33A is a diagram for explaining another configuration example of the imaging device according to the third embodiment of the present disclosure.
  • FIG. 33B is a diagram for explaining another configuration example of the imaging device according to the third embodiment of the present disclosure.
  • FIG. 33C is a diagram for explaining another configuration example of the imaging device according to the third embodiment of the present disclosure.
  • FIG. 33D is a diagram for explaining another configuration example of the imaging device according to the third embodiment of the present disclosure.
  • FIG. 33E is a diagram for explaining another configuration example of the imaging device according to the third embodiment of the present disclosure.
  • FIG. 34 is a diagram for explaining a configuration example of an imaging device according to a third embodiment of the present disclosure.
  • FIG. 35A is a diagram for explaining another configuration example of the imaging device according to the third embodiment of the present disclosure.
  • FIG. FIG. 35B is a diagram for explaining another configuration example of the imaging device according to the third embodiment of the present disclosure.
  • FIG. 35C is a diagram for explaining another configuration example of the imaging device according to the third embodiment of the present disclosure.
  • FIG. 35D is a diagram for explaining another configuration example of the imaging device according to the third embodiment of the present disclosure.
  • FIG. 35E is a diagram for explaining another configuration example of the imaging device according to the third embodiment of the present disclosure.
  • FIG. 36 is a block diagram illustrating an example of the configuration of an electronic device having an imaging device.
  • FIG. 37 is a block diagram showing an example of a schematic configuration of a vehicle control system.
  • FIG. 38 is an explanatory diagram showing an example of the installation positions of the outside-vehicle information detection unit and the imaging unit.
  • FIG. 39 is a diagram showing an example of a schematic configuration of an endoscopic surgery system.
  • FIG. 40 is a block diagram showing an example of the functional configuration of the camera head and the CCU.
  • First embodiment 1 is a block diagram showing an example of a schematic configuration of an imaging device which is an example of a light detection device according to a first embodiment of the present disclosure.
  • the light detection device is a device capable of detecting incident light.
  • the imaging device 1 which is a light detection device has a plurality of pixels P having a photoelectric conversion unit (photoelectric conversion element) and is configured to perform photoelectric conversion of incident light to generate a signal.
  • the imaging device 1 can receive light transmitted through an optical system (not shown) including an optical lens to generate a signal.
  • the imaging device 1 is configured, for example, using a semiconductor substrate (e.g., a silicon substrate) on which a plurality of pixels P are provided.
  • the photoelectric conversion unit of each pixel P of the imaging device 1 is, for example, a photodiode (PD) and is configured to be capable of photoelectrically converting light.
  • the imaging device 1 has an area (pixel section 100) in which a plurality of pixels P are arranged two-dimensionally in a matrix form as an imaging area.
  • the pixel section 100 of the imaging device 1 can also be considered a pixel array in which a plurality of pixels P are arranged.
  • the photoelectric conversion unit of each pixel P can also be considered a photoelectric conversion area.
  • the imaging device 1 captures incident light (image light) from a subject to be measured via an optical system including an optical lens.
  • the imaging device 1 captures an image of the subject formed by the optical lens.
  • the imaging device 1 can generate pixel signals by photoelectrically converting the received light (e.g. visible light, infrared light, etc.).
  • the imaging device 1, which is a light detection device, is a device that can receive incident light and generate a signal, and can also be called a light receiving device.
  • the imaging device 1 (light detection device) can be configured as an image sensor, for example.
  • the imaging device 1 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor.
  • the imaging device 1 can be used in various electronic devices, such as digital still cameras, video cameras, and mobile phones.
  • the imaging device 1 includes a pixel section 100, a pixel driving section 111, a signal processing section 112, a control section 113, and a processing section 114.
  • the imaging device 1 is also provided with, for example, a plurality of control lines L1 and a plurality of signal lines L2.
  • the control line L1 is a signal line capable of transmitting a signal that controls the pixel P, and is connected to the pixel drive unit 111 and the pixel P of the pixel unit 100.
  • a plurality of control lines L1 are wired for each pixel row made up of a plurality of pixels P arranged in the horizontal direction (row direction).
  • the control line L1 is configured to transmit a control signal for reading out a signal from the pixel P.
  • the multiple control lines L1 for each pixel row of the imaging device 1 include, for example, wiring that transmits a signal that controls a transfer transistor, wiring that transmits a signal that controls a selection transistor, wiring that transmits a signal that controls a reset transistor, etc.
  • the control lines L1 can also be considered drive lines (pixel drive lines) that transmit signals that drive the pixels P.
  • the signal line L2 is a signal line capable of transmitting a signal from the pixel P, and is connected to the pixel P of the pixel unit 100 and the signal processing unit 112.
  • the signal line L2 is wired for each pixel column made up of a plurality of pixels P aligned in the vertical direction (column direction).
  • the signal line L2 is a vertical signal line, and is configured to transmit a signal output from the pixel P.
  • the pixel driving unit 111 is configured to be able to drive each pixel P of the pixel unit 100.
  • the pixel driving unit 111 is a driving circuit and is configured with multiple circuits including, for example, a buffer, a shift register, an address decoder, etc.
  • the pixel driving unit 111 generates a signal for driving the pixel P and outputs it to each pixel P of the pixel unit 100 via a control line L1.
  • the pixel driving unit 111 is controlled by the control unit 113, and controls the pixels P of the pixel unit 100.
  • the pixel driving unit 111 generates signals for controlling the pixel P, such as a signal for controlling the transfer transistor of the pixel P, a signal for controlling the selection transistor, and a signal for controlling the reset transistor, and supplies these to each pixel P via a control line L1.
  • the pixel driving unit 111 can control the reading of pixel signals from each pixel P.
  • the pixel driving unit 111 can also be referred to as a pixel control unit configured to be able to control each pixel P.
  • the pixel driving unit 111 and the control unit 113 can also be referred to collectively as a pixel control unit.
  • the signal processing unit 112 is configured to be able to perform signal processing of the input pixel signal.
  • the signal processing unit 112 is a signal processing circuit, and has, for example, a load circuit, an AD (Analog Digital) conversion circuit, a horizontal selection switch, etc.
  • the load circuit is configured by a current source capable of supplying current to the amplification transistor of the pixel P.
  • the signal processing unit 112 may have an amplifier circuit configured to amplify a signal read from the pixel P via the signal line L2.
  • a load circuit, an amplifier circuit, an AD conversion circuit, etc. are provided for each of the multiple signal lines L2, for example.
  • a load circuit, an amplifier circuit, an AD conversion circuit, etc. may be provided for each pixel column of the pixel unit 100.
  • the signal output from each pixel P selected and scanned by the pixel driving unit 111 is input to the signal processing unit 112 via the signal line L2.
  • the signal processing unit 112 can perform signal processing such as AD conversion of the pixel P signal and CDS (Correlated Double Sampling).
  • the signal of each pixel P transmitted through each of the signal lines L2 is subjected to signal processing by the signal processing unit 112 and output to the processing unit 114.
  • the processing unit 114 is configured to be able to perform signal processing on the input signal.
  • the processing unit 114 is a signal processing circuit, and is configured, for example, by a circuit that performs various types of signal processing on pixel signals.
  • the processing unit 114 may include a processor and a memory.
  • the processing unit 114 performs signal processing on pixel signals input from the signal processing unit 112, and outputs the processed pixel signals.
  • the processing unit 114 can perform various types of signal processing, for example, noise reduction processing, tone correction processing, etc.
  • the control unit 113 is configured to be able to control each unit of the imaging device 1.
  • the control unit 113 receives an externally provided clock, data instructing the operation mode, and the like, and can also output data such as internal information of the imaging device 1.
  • the control unit 113 is a control circuit, and has, for example, a timing generator configured to be able to generate various timing signals.
  • the control unit 113 controls the driving of the pixel driving unit 111 and the signal processing unit 112 based on various timing signals (pulse signals, clock signals, etc.) generated by the timing generator. Note that the control unit 113 and the processing unit 114 may be configured as an integrated unit.
  • the pixel driving unit 111, the signal processing unit 112, the control unit 113, the processing unit 114, etc. may be provided on one semiconductor substrate, or may be provided separately on multiple semiconductor substrates.
  • the imaging device 1 may have a structure (a stacked structure) formed by stacking multiple substrates. Some or all of the signal processing unit 112, the control unit 113, and the processing unit 114 may be configured integrally.
  • FIG. 2 is a diagram showing an example of pixel arrangement in an imaging device according to a first embodiment.
  • a pixel P of the imaging device 1 has a photoelectric conversion unit 12, a lens 21, and a filter 22.
  • the incident direction of light from a subject is the Z-axis direction
  • the left-right direction on the paper perpendicular to the Z-axis direction is the X-axis direction
  • the up-down direction on the paper perpendicular to the Z-axis and X-axis directions is the Y-axis direction.
  • directions may be indicated based on the directions of the arrows in FIG. 2.
  • a lens 21 and a filter 22 may be provided on the side where light is incident from an optical system such as an imaging lens (see also FIG. 9 described later).
  • the lens 21 (lens unit) is a lens that collects light, and is an optical member also known as an on-chip lens.
  • the lens 21 is provided above the photoelectric conversion unit 12, for example, for each pixel P or for each set of pixels P.
  • the lens 21 guides the incident light to the photoelectric conversion unit 12 of the pixel P.
  • the photoelectric conversion unit 12 of the pixel P photoelectrically converts the light incident via the lens 21 and the filter 22.
  • the filter 22 is configured to selectively transmit light of a specific wavelength range from among the incident light.
  • the filter 22 is, for example, an RGB color filter, a filter that transmits infrared light, etc.
  • the filter 22 is provided above the photoelectric conversion unit 12, for example, for each pixel P or for each set of multiple pixels P.
  • the multiple pixels P provided in the pixel section 100 of the imaging device 1 include, as an example, a pixel (R pixel) provided with a filter 22 that transmits red (R) light, a pixel (G pixel) provided with a filter 22 that transmits green (G) light, and a pixel (B pixel) provided with a filter 22 that transmits blue (B) light.
  • a pixel (R pixel) provided with a filter 22 that transmits red (R) light
  • a pixel (G pixel) provided with a filter 22 that transmits green (G) light
  • a pixel (B pixel) provided with a filter 22 that transmits blue (B) light.
  • multiple R pixels, multiple G pixels, and multiple B pixels are repeatedly arranged.
  • the R, G, and B pixels are arranged, for example, according to a Bayer array.
  • the R, G, and B pixels can generate R component pixel signals, G component pixel signals, and B component pixel signals, respectively.
  • the imaging device 1 can obtain RGB pixel signals. Note that the pixel arrangement is not limited to the above example, and can be set arbitrarily.
  • the R pixels, G pixels, and B pixels can each be arranged in 2 x 2 pixel units.
  • the R pixels, G pixels, and B pixels are each arranged periodically in 2 rows and 2 columns.
  • the filter 22 provided in the pixel P of the pixel unit 100 is not limited to a primary color (RGB) color filter, but may be a complementary color filter such as Cy (cyan), Mg (magenta), or Ye (yellow).
  • a filter corresponding to W (white), that is, a filter that transmits light of all wavelengths of incident light, may also be disposed.
  • the filter 22 may be a filter that transmits infrared light.
  • the filter 22 may be omitted as necessary.
  • the filter 22 may not be provided in some or all of the pixels P of the imaging device 1.
  • the filter 22 may not be provided in the pixels P that receive white (W) light and perform photoelectric conversion.
  • FIG. 3 is a diagram for explaining an example of the circuit configuration of a pixel of the imaging device according to the first embodiment.
  • a pixel P of the imaging device 1 has a photoelectric conversion unit 12 (photoelectric conversion element), a transfer transistor TR, a floating diffusion FD, and a readout circuit 20.
  • the photoelectric conversion unit 12 is configured to receive light and generate a signal.
  • the photoelectric conversion unit 12 is a light receiving unit (light receiving element) and is configured to be able to generate an electric charge by photoelectric conversion.
  • the readout circuit 20 is configured to be capable of outputting a signal based on the charge photoelectrically converted.
  • the readout circuit 20 can read out a pixel signal based on the charge photoelectrically converted by the photoelectric conversion unit 12.
  • the readout circuit 20 is provided for multiple pixels P.
  • the imaging device 1 has a configuration in which multiple pixels P share one readout circuit 20. This makes it possible to reduce the number of elements (e.g., the number of transistors) per pixel P (or per photoelectric conversion unit 12).
  • the imaging device 1 can have a structure that is advantageous for miniaturizing pixels.
  • a readout circuit 20 is arranged for every four pixels P (referred to as pixels Pa to Pd). Pixels Pa, Pb, Pc, and Pd share one readout circuit 20. For example, 2 ⁇ 2 pixels consisting of adjacent pixels Pa to Pd share one readout circuit 20.
  • the imaging device 1 can read out the pixel signals of each of the 2 x 2 pixels by operating the readout circuit 20 in a time-division manner.
  • the imaging device 1 can also read out a pixel signal in which the signals of each of the 2 x 2 pixels are added together.
  • the imaging device 1 can read out a pixel signal corresponding to the charge obtained by adding up the charges photoelectrically converted by each of the 2 x 2 pixels.
  • the photoelectric conversion unit 12 is a photodiode (PD) that converts incident light into an electric charge.
  • the photoelectric conversion unit 12 (in FIG. 3, the photodiode PD of pixel Pa to the photodiode PD of pixel Pd) can perform photoelectric conversion to generate an electric charge according to the amount of light received.
  • the transfer transistor TR (in FIG. 3, the transfer transistor TR of pixel Pa to the transfer transistor TR of pixel Pd) is configured to be able to transfer the charge photoelectrically converted in the photoelectric conversion unit 12 to the floating diffusion FD.
  • the transfer transistor TR is controlled by a signal STR, and electrically connects or disconnects the photoelectric conversion unit 12 and the floating diffusion FD.
  • the transfer transistor TR can transfer the charge photoelectrically converted and accumulated in the photoelectric conversion unit 12 to the floating diffusion FD.
  • the transfer transistors TR of pixels Pa to Pd are turned on and off by different signals.
  • the transfer transistor TR of pixel Pa is controlled by signal STR1
  • the transfer transistor TR of pixel Pb is controlled by signal STR2.
  • the transfer transistor TR of pixel Pc is controlled by signal STR3
  • the transfer transistor TR of pixel Pd is controlled by signal STR4.
  • the floating diffusion FD is an accumulation section and is configured to be able to accumulate the transferred charge.
  • the floating diffusion FD can accumulate the charge photoelectrically converted by the photoelectric conversion section 12.
  • the floating diffusion FD can also be said to be a retention section capable of retaining the transferred charge.
  • the floating diffusion FD accumulates the transferred charge and converts it into a voltage according to the capacity of the floating diffusion FD.
  • the readout circuit 20 has an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST, as shown in FIG. 3.
  • the amplification transistor AMP is configured to generate and output a signal based on the charge accumulated in the floating diffusion FD.
  • the amplification transistor AMP can generate and output a signal based on the charge converted by the photoelectric conversion unit 12.
  • the gate of the amplifier transistor AMP is electrically connected to the floating diffusion FD of each pixel P, and the voltage converted by the floating diffusion FD is input.
  • the drain of the amplifier transistor AMP is connected to a power supply line through which the power supply voltage VDD is supplied.
  • the source of the amplification transistor AMP is connected to the signal line L2 via the selection transistor SEL.
  • the amplification transistor AMP is configured to generate a signal based on the charge stored in the floating diffusion FD, i.e., a signal based on the voltage of the floating diffusion FD, and output it to the signal line L2.
  • the selection transistor SEL is configured to be capable of controlling the output of a pixel signal.
  • the selection transistor SEL is electrically connected in series to the amplification transistor AMP.
  • the selection transistor SEL is controlled by a signal SSEL, and is configured to be capable of outputting a signal from the amplification transistor AMP to a signal line L2.
  • the selection transistor SEL can control the output timing of the pixel signal.
  • the selection transistor SEL is configured to be capable of outputting a signal based on the charge converted by the photoelectric conversion unit 12.
  • the selection transistor SEL can output a pixel signal of the pixel P to a signal line L2.
  • the selection transistor SEL may be electrically connected between a power supply line to which a power supply voltage VDD is applied and the amplification transistor AMP. Furthermore, the selection transistor SEL may be omitted as necessary.
  • the reset transistor RST is configured to be able to reset the voltage of the floating diffusion FD.
  • the reset transistor RST is electrically connected to a power supply line to which a power supply voltage VDD is applied, and is configured to reset the charge of the pixel P.
  • the reset transistor RST is controlled by a signal SRST, and can reset the charge accumulated in the floating diffusion FD and reset the voltage of the floating diffusion FD.
  • the reset transistor RST electrically connects the power supply line and the floating diffusion FD, and can discharge the charge accumulated in the floating diffusion FD.
  • the reset transistor RST can also discharge the charge accumulated in the photoelectric conversion unit 12 via the transfer transistor TR.
  • FIG. 4A is a diagram for explaining another example of the circuit configuration of a pixel of the imaging device according to the first embodiment.
  • the readout circuit 20 may have a transistor FDG, as in the example shown in FIG. 4A.
  • the transistor FDG is configured to be able to electrically connect the floating diffusion FD and the reset transistor RST.
  • the transistor FDG is controlled by a signal SFDG to electrically connect or disconnect the floating diffusion FD and the reset transistor RST.
  • the transistor FDG When the transistor FDG is turned on, the capacitance added to the floating diffusion FD of the pixel P increases, and the conversion efficiency (gain) when converting charge to voltage is switched.
  • the transistor FDG is a switching transistor used to set the conversion efficiency.
  • the transistor FDG can change the conversion efficiency by switching the capacitance connected to the gate of the amplification transistor AMP.
  • the transistor FDG may be electrically connected in series to the reset transistor RST, or may be electrically connected in parallel to the reset transistor RST.
  • the transistor FDG may be configured to be able to electrically connect the floating diffusion FD and the capacitive element C1, as in the example shown in FIG. 4B.
  • the transistor FDG is controlled by a signal SFDG to electrically connect or disconnect the floating diffusion FD and the capacitive element C1. By switching the connection state of the capacitive element C1, it is possible to change the conversion efficiency.
  • the transfer transistor TR, the amplification transistor AMP, the selection transistor SEL, the transistor FDG (switching transistor), and the reset transistor RST described above are each a MOS transistor (MOSFET) having a gate, a source, and a drain terminal.
  • MOSFET MOS transistor
  • the transfer transistor TR, the amplification transistor AMP, the selection transistor SEL, the transistor FDG, and the reset transistor RST are each configured as an NMOS transistor.
  • the transistor of the pixel P may be configured as a PMOS transistor.
  • the transistor of the pixel P may be configured as a 3D transistor, for example, a FinFET.
  • the imaging device 1 may have a configuration in which five or more pixels P, for example, eight pixels P, share one readout circuit 20.
  • a readout circuit 20 is arranged for every eight pixels P, and 2 ⁇ 4 pixels share one readout circuit 20.
  • the pixel driving unit 111 (see FIG. 1) of the imaging device 1 supplies control signals to the gates of the transfer transistor TR, selection transistor SEL, transistor FDG, reset transistor RST, etc. of each pixel P via the control line L1 described above, turning the transistors on (conducting state) or off (non-conducting state).
  • the multiple control lines L1 for each pixel row of the imaging device 1 include, for example, wiring that transmits a signal STR that controls the transfer transistor TR, wiring that transmits a signal SSEL that controls the selection transistor SEL, wiring that transmits a signal SFDG that controls the transistor FDG, wiring that transmits a signal SRST that controls the reset transistor RST, etc.
  • the transfer transistor TR, selection transistor SEL, transistor FDG, reset transistor RST, etc. are controlled to be turned on and off by the pixel driving unit 111.
  • the pixel driving unit 111 controls the readout circuit 20 of each pixel P to output a pixel signal from each pixel P to the signal line L2.
  • the pixel driving unit 111 can control the reading out of the pixel signal of each pixel P to the signal line L2.
  • FIG. 5 is a diagram showing an example of the planar configuration of a pixel of the imaging device according to the first embodiment.
  • FIG. 6 is a diagram for explaining an example of the cross-sectional configuration of a pixel of the imaging device.
  • FIG. 6 shows an example of the pixel configuration in the direction of line A-A' shown in FIG. 5.
  • Each pixel P of the imaging device 1 has, for example, the structure shown in FIG. 5 and FIG. 6.
  • the pixel P has a photoelectric conversion unit 12, a transfer transistor TR, a floating diffusion FD, a pixel transistor 30, and a semiconductor region 35.
  • the pixel transistor 30 is, for example, a transistor of the readout circuit 20 described above.
  • the pixel transistor 30 is used as an amplification transistor AMP, a selection transistor SEL, a transistor FDG, a reset transistor RST, or the like. Note that the pixel transistor 30 of some pixels P may be a dummy transistor.
  • the readout circuit 20 may include a dummy transistor as the pixel transistor 30.
  • Each transistor of the readout circuit 20, such as the amplification transistor AMP, the selection transistor SEL, the transistor FDG, and the reset transistor RST, is provided separately as pixel transistors 30 in multiple pixels P, for example, and is shared by multiple pixels P. By configuring the imaging device 1 in this way, it is possible to reduce the number of transistors in one pixel P.
  • the imaging device 1 is configured using a substrate 101 including a semiconductor layer 110.
  • the substrate 101 is configured, for example, of a semiconductor substrate such as a Si (silicon) substrate.
  • the above-mentioned photoelectric conversion unit 12 and readout circuit 20 are formed on the substrate 101 including the semiconductor layer 110.
  • the substrate 101 may be formed using an SOI (Silicon On Insulator) substrate, a SiGe (Silicon Germanium) substrate, other compound semiconductor materials, etc.
  • SOI Silicon On Insulator
  • SiGe Silicon Germanium
  • the substrate 101 is formed to include a semiconductor layer 110 and a wiring layer 120.
  • the semiconductor layer 110 has opposing surfaces 11S1 and 11S2.
  • Surface 11S2 is the surface opposite to surface 11S1.
  • Surface 11S1 of the semiconductor layer 110 is an element formation surface on which elements such as transistors are formed.
  • a gate electrode, a gate insulating film (e.g., a gate oxide film), etc. are provided on surface 11S1 of the semiconductor layer 110.
  • Surface 11S2 of the semiconductor layer 110 is, for example, a light receiving surface (light incident surface).
  • a plurality of photoelectric conversion units 12 are provided along the faces 11S1 and 11S2 of the semiconductor layer 110.
  • a plurality of photoelectric conversion units 12 are embedded in the semiconductor layer 110.
  • the photoelectric conversion units 12 can also be called a photoelectric conversion layer.
  • the photoelectric conversion units 12 are provided between the faces 11S1 and 11S2 of the semiconductor layer 110.
  • the semiconductor layer 110 has a well 25.
  • the well 25 is, for example, a p-type semiconductor region, or a p-type well (p-well).
  • the well 25, which is a p-type well region, is provided in the semiconductor layer 110.
  • the photoelectric conversion unit 12 is configured to include a semiconductor region 15 provided within the well 25.
  • the semiconductor region 15 is, for example, an n-type semiconductor region.
  • a transfer transistor TR, a floating diffusion FD, a pixel transistor 30, a semiconductor region 35, etc. are provided on the surface 11S1 side of the semiconductor layer 110.
  • the floating diffusion FD is configured to include, for example, an n-type semiconductor region.
  • the imaging device 1 is provided with trenches 91 and 92.
  • the trenches 91 and 92 are each provided between adjacent pixels P in the semiconductor layer 110.
  • the trenches 91 and 92 are provided between the photoelectric conversion units 12 of adjacent pixels P, and separate the pixels P (or the photoelectric conversion units 12). It can also be said that the pixels P have a structure partitioned by the trenches 91 and 92.
  • Trench 91 and trench 92 are each an isolation portion (groove portion) and are formed, for example, using an insulating material. At least a portion of each of trench 91 and trench 92 is provided at the boundary between adjacent pixels P (or photoelectric conversion portions 12).
  • Trench 91 has an STI (Shallow Trench Isolation) structure and is provided on the surface 11S1 side of semiconductor layer 110.
  • Trench 92 has an FTI (Full Trench Isolation) structure and is provided so as to penetrate semiconductor layer 110.
  • trench 91 is provided in semiconductor layer 110 so as to surround transfer transistor TR, floating diffusion FD, pixel transistor 30, semiconductor region 35, etc.
  • trench 92 is provided in semiconductor layer 110 so as to surround photoelectric conversion unit 12.
  • trenches 91 and trench 92 are provided in a lattice shape so as to surround each photoelectric conversion unit 12 of each pixel P.
  • Trench 91 and trench 92 can also be referred to as inter-pixel separation unit or inter-pixel separation wall.
  • an insulating film such as an oxide film (e.g., a silicon oxide film) or a nitride film (e.g., a silicon nitride film) is provided.
  • the trenches 91 and 92 may be filled with polysilicon, a metal material, other insulating materials, etc. Also, a void (cavity) may be provided in the trenches 91 and 92.
  • the trench 92 may be formed in the trench 91.
  • the trench 92 may be provided from the trench 91 provided on the surface 11S1 side of the semiconductor layer 110 to the surface 11S2 of the semiconductor layer 110.
  • the imaging device 1 is also provided with a trench 93.
  • the trench 93 is an isolation portion (groove portion) having an STI structure.
  • An insulating film such as an oxide film (e.g., a silicon oxide film) or a nitride film (e.g., a silicon nitride film) is provided within the trench 93.
  • the trench 93 is provided on the surface 11S1 side of the semiconductor layer 110, and isolates the elements.
  • the trench 93 is formed between the pixel transistor 30 and the floating diffusion FD, between the pixel transistor 30 and the transfer transistor TR, between the transfer transistor TR and the semiconductor region 35, etc.
  • the imaging device 1 is provided with a plurality of regions (active regions) partitioned by separation portions (trench).
  • the imaging device 1 has, for example, an active region 81 and an active region 82 provided in the semiconductor layer 110 of the substrate 101.
  • each pixel P of the imaging device 1 is formed with an active region 81 and an active region 82 surrounded by a trench 93 (or trench 91).
  • Active region 81 and active region 82 are, for example, regions of semiconductor layer 110 (or well 25 of semiconductor layer 110) electrically isolated by trenches 93 and 91, and are island-shaped regions. As in the example shown in FIG. 5, pixel transistor 30 and semiconductor region 35 are provided in active region 81. Furthermore, transfer transistor TR and floating diffusion FD are provided in active region 82.
  • the transfer transistor TR has a gate insulating film 45 and a gate electrode 46.
  • the transfer transistor TR has a planar gate structure.
  • the transfer transistor TR is configured as, for example, a planar type transistor.
  • the transfer transistor TR is disposed in the active region 82.
  • the transfer transistor TR may have a vertical gate structure.
  • the gate electrode 46 and the gate insulating film 45 of the transfer transistor TR may be formed in the semiconductor layer 110 so as to reach the photoelectric conversion unit 12.
  • the semiconductor region 35 is a semiconductor region of the same conductivity type as the well 25, and is provided on the surface 11S1 side of the semiconductor layer 110.
  • the semiconductor region 35 is provided relative to the well 25 in the active region 81, and is electrically connected to the well 25.
  • the semiconductor region 35 is, for example, a p-type semiconductor region, and is a region formed using p-type impurities.
  • the semiconductor region 35 has, for example, a higher impurity concentration than the impurity concentration of the well 25, and is a p+ type semiconductor region.
  • the semiconductor region 35 which is a p+ region, is a p+ type diffusion region, and can also be said to be a p+ type conductive region.
  • the semiconductor region 35 is also electrically connected to the contact 55.
  • the contact 55 is provided in the wiring layer 120 of the substrate 101.
  • the semiconductor region 35 is connected to a contact 55 provided on the semiconductor region 35, and is electrically connected to wiring (not shown) of the wiring layer 120 via the contact 55.
  • the contact 55 is electrically connected to the well 25 by the semiconductor region 35.
  • the contact 55 is, for example, in ohmic contact with the semiconductor region 35 and electrically connected to the well 25 via the semiconductor region 35.
  • a predetermined potential (voltage) is supplied to the region of the well 25 electrically connected to the semiconductor region 35 by the wiring of the wiring layer 120, the contact 55, etc.
  • the contact 55 is a well contact, and the semiconductor region 35 is a well contact region.
  • the contact 55 and the semiconductor region 35 are arranged, for example, for each pixel P.
  • the semiconductor region 35 and the contact 55 together can also be referred to as a well contact region.
  • the semiconductor region 35 is electrically connected to a reference potential line in the wiring layer 120 via, for example, the contact 55, and a reference potential is applied to the semiconductor region 35 and the well 25.
  • a GND potential ground potential
  • the pixel transistor 30 has a semiconductor region 31, a semiconductor region 32, a semiconductor region 33, a gate insulating film 41, and a gate electrode 42.
  • the semiconductor regions 31 to 33 are each provided with respect to a well 25 in the active region 81. It can also be said that the semiconductor regions 32, 33, etc. are arranged to replace part of the well 25.
  • the semiconductor region 31 and the semiconductor region 32 (or the semiconductor region 33) have mutually different conductivity types.
  • the semiconductor region 31 is a region where a channel is formed (channel region). As shown in the example of FIG. 6, a portion P1 of a gate electrode 42 and a gate insulating film 41 are provided around the semiconductor region 31.
  • the semiconductor region 31 is, for example, a p-type semiconductor region, and is a region formed using p-type impurities.
  • the semiconductor region 31 is a p-type diffusion region, and can also be said to be a p-type conductive region.
  • the semiconductor region 32 and the semiconductor region 33 are the source region and the drain region of the pixel transistor 30.
  • One of the semiconductor regions 32 and 33 is the source region of the pixel transistor 30, and the other of the semiconductor regions 32 and 33 is the drain region of the pixel transistor 30.
  • Semiconductor region 32 and semiconductor region 33 are, for example, n-type semiconductor regions, and are regions formed using n-type impurities. Semiconductor region 32 and semiconductor region 33 are, for example, formed by doping (adding) n-type impurities into a region of semiconductor layer 110. Semiconductor region 32 and semiconductor region 33 are, for example, n-type diffusion regions, and can also be called n-type conductive regions.
  • the semiconductor region 32 is connected to a contact 52 provided on the semiconductor region 32, and is electrically connected to the wiring (not shown) of the wiring layer 120 via the contact 52.
  • the semiconductor region 33 is connected to a contact 53 provided on the semiconductor region 33, and is electrically connected to the wiring of the wiring layer 120 via the contact 53.
  • a semiconductor region 32 and a semiconductor region 33 are arranged around the gate electrode 42 of the pixel transistor 30.
  • the pixel transistor 30 having the semiconductor regions 32 and 33 is formed in a region around the transfer transistor TR. Note that the shape of the pixel transistor 30 is not limited to the example shown in FIG. 5 and can be changed as appropriate.
  • the gate electrode 42 of the pixel transistor 30 is provided, for example, on the surface 11S1 side of the semiconductor layer 110 so as to sandwich a part of the semiconductor layer 110.
  • a part of the gate electrode 42 is provided within the semiconductor layer 110 so as to sandwich a part of the semiconductor layer 110 that will become the channel region of the pixel transistor 30, via the gate insulating film 41.
  • the pixel transistor 30 can be configured as a Fin type transistor.
  • At least a portion of the gate electrode 42 of the pixel transistor 30 is provided, for example, in the semiconductor layer 110. At least a portion of each of the gate electrode 42 and the gate insulating film 41 is provided, for example, by recessing the semiconductor layer 110. At least a portion of each of the gate electrode 42 and the gate insulating film 41 of the pixel transistor 30 can be disposed so as to be embedded, for example, in the semiconductor layer 110.
  • the gate electrode 42 of the pixel transistor 30 has multiple portions P1, for example, as shown in the example in FIG. 6.
  • the multiple portions P1 of the gate electrode 42 are provided in the semiconductor layer 110 so as to sandwich the semiconductor region 31 that becomes the channel region of the pixel transistor 30.
  • the multiple portions P1 are arranged, for example, so as to be aligned with each other in the Y-axis direction (or X-axis direction) with the semiconductor region 31 in between. Note that the number, shape, etc. of the portions P1 are not limited to the example shown in the figure, and can be changed as appropriate.
  • the gate electrode 42 of the pixel transistor 30 may have a plurality of portions P1 provided in the semiconductor layer 110.
  • the plurality of portions P1 of the gate electrode 42 are arranged in a plurality of grooves (trenches) provided in the semiconductor layer 110.
  • the pixel transistor 30 may have the gate electrode 42 which is a trench-type gate electrode.
  • the multiple portions P1 of the gate electrode 42 have a fin shape and can also be called fin portions.
  • the semiconductor region 31 of the semiconductor layer 110 has a fin shape and can also be called fin portions. Note that the portions P1 or the semiconductor region 31 are protruding structural parts and can also be called protruding portions.
  • the portion P1 of the gate electrode 42 protrudes, for example, from the surface 11S1 of the semiconductor layer 110 toward the inside of the semiconductor layer 110.
  • the portion P1 or the semiconductor region 31 can also be considered a convex portion (or a protruding portion).
  • the portion P1 can also be considered a convex portion that extends from the surface 11S1 of the semiconductor layer 110 toward the inside of the semiconductor layer 110.
  • the gate electrode 42 of the pixel transistor 30 may be configured to include multiple structural portions arranged to extend in the thickness direction of the semiconductor layer 110 (or the substrate 101).
  • the gate electrode 42 has multiple portions P1 formed to extend in the thickness direction perpendicular to the surface 11S1 of the semiconductor layer 110.
  • portion P1 of gate electrode 42 is provided between trench 93 and trench 91. As shown in FIG. 6, bottom B1 (lower end) of gate electrode 42 is located above bottom B2 of trench 93. Portion P1 (fin portion) of gate electrode 42 is formed, for example, in a region whose depth from surface 11S1 of semiconductor layer 110 is shallower than bottom B2 (lower end) of trench 93.
  • the gate insulating film 41 of the pixel transistor 30 is provided on the channel region (semiconductor region 31) of the pixel transistor 30.
  • the gate insulating film 41 e.g., a gate oxide film
  • the gate electrode 42 is provided on the gate insulating film 41.
  • the gate electrode 42 is arranged to cover the semiconductor region 31 of the semiconductor layer 110 via the gate insulating film 41, as shown in FIG. 6, for example.
  • the gate insulating film 41 is formed along the multiple portions P1 of the gate electrode 42 within the semiconductor layer 110.
  • the portion P1 of the gate electrode 42 and the gate insulating film 41 are provided by digging into the semiconductor layer 110, for example, as shown in the example of FIG. 6.
  • the pixel transistor 30 may have a dug-in gate structure. A portion of each of the gate electrode 42 and the gate insulating film 41 is disposed so as to be embedded in the semiconductor layer 110, for example.
  • the pixel transistor 30 has a dug-in fin structure and may also be called a dug-in fin transistor.
  • the gate insulating film 41 of the pixel transistor 30 and the gate insulating film 45 of the transfer transistor TR are composed of, for example, a single layer film made of one of silicon oxide (SiO), silicon oxynitride (SiON), hafnium oxide (HfO), etc., or a laminated film made of two or more of these.
  • the gate insulating films 41 and 45 may be formed using a high-dielectric material having a higher dielectric constant than that of silicon oxide, such as a hafnium-based insulating film.
  • the gate electrode 42 of the pixel transistor 30 and the gate electrode 46 of the transfer transistor TR are made of, for example, polysilicon (Poly-Si).
  • the gate electrodes 42 and 46 may be made of a metal material or a metal compound.
  • the gate electrodes 42 and 46 may be made of, for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), etc. Sidewalls may be provided on the side surfaces of the gate electrode 42 and the gate electrode 46.
  • the contacts 52, 53, and 55 are each made of a conductive material.
  • the contacts 52, 53, and 55 are each formed by embedding (filling) a conductive material such as tungsten (W) into a contact hole.
  • a conductive material such as tungsten (W) into a contact hole.
  • Each of the contacts 52, 53, and 55 may be made of a metal material such as aluminum (Al) or copper (Cu), or may be made of other materials.
  • the semiconductor region 35 is provided adjacent to the pixel transistor 30.
  • the semiconductor region 35 is provided adjacent to the source region or drain region of the pixel transistor 30.
  • the semiconductor region 35 and the source region or drain region of the pixel transistor 30 are provided in the active region 81 as shown in FIG. 5.
  • the semiconductor region 35 is disposed adjacent to the semiconductor region 33 of the pixel transistor 30 on the surface 11S1 side of the semiconductor layer 110.
  • adjacent includes cases where there is no contact.
  • Adjacent includes cases where there is direct contact and cases where there is adjacent via a natural oxide film or the like.
  • in contact includes cases where there is direct contact and cases where there is contact via a natural oxide film or the like.
  • the semiconductor region 35 is provided, for example, adjacent to an end (side) of the semiconductor region 33, which is the source region or drain region of the pixel transistor 30.
  • the semiconductor region 35 may be provided adjacent to the semiconductor region 32.
  • the semiconductor region 35 may also be provided adjacent to the gate of the pixel transistor 30.
  • the semiconductor region 35 is provided adjacent to the pixel transistor 30.
  • This allows the imaging device 1 to have a structure that is advantageous for miniaturization. Compared to a case in which the semiconductor region 35 and the pixel transistor 30 are provided in different active regions, the area of the region in which the transistors, etc. are arranged in the pixel P can be increased. It is possible to increase the size (e.g., gate width, gate length, etc.) of the transistor arranged in the pixel P.
  • the pixel transistor 30 has a gate electrode 42 arranged to sandwich a part of the semiconductor layer 110, as described above.
  • the pixel transistor 30 can be configured as a Fin type transistor. This allows the area of the gate electrode 42 of the pixel transistor 30 to be increased. It is possible to increase the effective gate width, etc., of the pixel transistor 30.
  • the area of the transistor of the readout circuit 20, for example the gate of the amplification transistor AMP, can be increased, making it possible to suppress noise that gets mixed into the pixel signal.
  • the area efficiency of fine pixels can be improved, and the size of the pixel transistor 30 can be increased.
  • the pixel transistor 30 can be configured to have multiple fin portions (portion P1), and the gate area of the pixel transistor 30 can be secured. This makes it possible to improve the characteristics of the transistors (amplification transistor AMP, selection transistor SEL, transistor FDG, reset transistor RST, etc.) of the readout circuit 20. This makes it possible to prevent the quality of the pixel signal from deteriorating, and to prevent deterioration in the image quality of the image.
  • the gate electrode 42 of the pixel transistor 30 is provided such that the bottom B1 of the gate electrode 42 is located above the bottom B2 of the trench 93. This allows the pixel transistor 30 to be isolated from other elements, and crosstalk between elements can be suppressed. It is possible to suppress noise from being mixed into the pixel signal.
  • the portion P1 (fin portion) of the gate electrode 42 is formed in a region whose depth from the surface 11S1 of the semiconductor layer 110 is shallower than the bottom B2 of the trench 93. This makes it possible to suppress manufacturing variations in the portion P1 (variations in the length of the portion P1, the width (thickness) of the portion P1, etc.), and to suppress deterioration of the characteristics of the pixel transistor 30.
  • FIG. 7 is a diagram showing an example of the arrangement of pixel transistors in an imaging device according to the first embodiment.
  • four pixels P that share a readout circuit 20 are pixels Pa to Pd, and 2 ⁇ 2 pixels are shown.
  • the other pixels P in the imaging device 1 may also have a configuration similar to that shown in FIG. 7.
  • pixel Pa is provided with an amplification transistor AMP as the pixel transistor 30.
  • Pixel Pb is provided with a selection transistor SEL as the pixel transistor 30.
  • Pixel Pc is provided with a reset transistor RST as the pixel transistor 30.
  • pixel Pd is provided with a transistor FDG as the pixel transistor 30.
  • a wiring L3 is provided in the imaging device 1, for example, as shown in the example in FIG. 7, a wiring L3 is provided.
  • the floating diffusion FD of each of the multiple pixels P that share the readout circuit 20 is electrically connected to the transistor of the readout circuit 20 via the wiring L3.
  • the floating diffusion FD of each of the pixels Pa to Pd is electrically connected to the gate electrode of the amplification transistor AMP, which is, for example, the pixel transistor 30 of the pixel Pa, via the wiring L3.
  • the wiring L3 is a wiring shared by the four pixels Pa to Pd.
  • the wiring L3 is formed using a metal material such as aluminum (Al) or tungsten (W). Note that the wiring L3 may also be made of polysilicon (Poly-Si) or other conductive materials.
  • the imaging device 1 may have a configuration in which a floating diffusion FD is shared by multiple pixels P, as in the example shown in FIG. 8.
  • a floating diffusion FD is provided for four pixels Pa to Pd, and is shared by pixels Pa to Pd.
  • FIG. 9 is a diagram showing an example of a cross-sectional configuration of an imaging device according to the first embodiment.
  • the imaging device 1 has, for example, a light guide section 90, a semiconductor layer 110, and a wiring layer 120.
  • the imaging device 1 has a configuration in which the light guide section 90, the semiconductor layer 110, and the wiring layer 120 are stacked in the Z-axis direction.
  • a wiring layer 120 is provided on the surface 11S1 side of the semiconductor layer 110.
  • a light guide section 90 is provided on the surface 11S2 side of the semiconductor layer 110.
  • the light guide section 90 is provided on the side where light from the optical system is incident, and the wiring layer 120 is provided on the side opposite the side where the light is incident.
  • the imaging device 1 is a so-called back-illuminated type imaging device.
  • the wiring layer 120 includes, for example, a conductor film and an insulating film, and has multiple wirings and vias (VIAs), etc.
  • the wiring layer 120 includes, for example, two or more layers of wirings, or three or more layers of wirings.
  • the wiring layer 120 may include five or more layers of wirings.
  • the wiring layer 120 has a configuration in which multiple wirings are stacked via an insulating film serving as an interlayer insulating film (interlayer insulating layer).
  • the insulating film of the wiring layer 120 can also be called an interlayer insulating film (interlayer insulating layer).
  • the wiring of the wiring layer 120 is formed using, for example, a metal material such as aluminum (Al), tungsten (W), or copper (Cu).
  • the wiring of the wiring layer 120 may be formed using polysilicon (Poly-Si) or other conductive materials.
  • the interlayer insulating film is formed using, for example, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or the like.
  • the semiconductor layer 110 and the wiring layer 120 are provided with, for example, the photoelectric conversion unit 12, the readout circuit 20, etc. Furthermore, the pixel driving unit 111, the signal processing unit 112, the control unit 113, the processing unit 114, etc. described above can be provided on a substrate separate from the semiconductor layer 110, or on the semiconductor layer 110 and the wiring layer 120.
  • the light guide section 90 shown in FIG. 9 is laminated on the semiconductor layer 110 in a thickness direction perpendicular to the surface 11S2 of the semiconductor layer 110.
  • the light guide section 90 has a lens 21 and a filter 22, and guides the incident light to the semiconductor layer 110 side.
  • the lens 21 is provided on the filter 22, for example, for each pixel P or for each set of pixels P.
  • Light from a subject enters the lens 21 via an optical system such as an imaging lens.
  • the photoelectric conversion unit 12 photoelectrically converts the light that enters through the lens 21 and the filter 22.
  • the imaging device 1 is provided with a light-shielding section 23.
  • the light-shielding section 23 (light-shielding film) is made of a material that blocks light, and is provided at the boundary between multiple adjacent pixels P.
  • at least a portion of the light-shielding section 23 (light-shielding material) is provided between adjacent filters 22, and may be located at the boundary between the adjacent filters 22.
  • the light shielding portion 23 is made of, for example, a metal material that blocks light (aluminum (Al), tungsten (W), copper (Cu), etc.).
  • the light shielding portion 23 may be made of a material that absorbs light.
  • the light shielding portion 23 is provided to prevent light from leaking to the surrounding pixels P. Unnecessary light is prevented from leaking to the surroundings, and color mixing can be prevented.
  • the imaging device 1 may have at least one of a fixed charge film and an anti-reflection film.
  • the fixed charge film and the anti-reflection film are provided, for example, on the surface 11S2 side of the semiconductor layer 110.
  • the fixed charge film is a film having a fixed charge, and may be formed using a high dielectric material.
  • the fixed charge film is made of a metal oxide such as hafnium oxide or aluminum oxide.
  • the fixed charge film is, for example, a film having a negative fixed charge.
  • the fixed charge film is provided between the semiconductor layer 110 and the filter 22. By providing the fixed charge film, the generation of dark current at the interface of the semiconductor layer 110 is suppressed.
  • the fixed charge film may be formed of another metal oxide film, or may be formed using a metal nitride film or a metal oxynitride film. A film having a positive fixed charge may be provided as the fixed charge film.
  • the anti-reflection film is, for example, made of an insulating material such as silicon nitride (SiN) or silicon oxide (SiO).
  • the anti-reflection film is provided, for example, so as to be laminated with the fixed charge film.
  • the anti-reflection film is provided, for example, between the semiconductor layer 110 and the filter 22, and reduces (suppresses) reflection.
  • the anti-reflection film may be made of a metal compound (metal oxide, metal nitride, etc.) such as aluminum oxide, hafnium oxide, or tantalum oxide, or may be made of other materials.
  • the photodetector includes a semiconductor layer (semiconductor layer 110), a plurality of pixels including a first pixel (e.g., pixel Pa) having a photoelectric conversion element (photoelectric conversion unit 12) provided in the semiconductor layer, and trenches (trench 91, trench 92) provided between the plurality of adjacent pixels in the semiconductor layer.
  • the first pixel includes a transistor (pixel transistor 30) provided on the first surface side of the semiconductor layer, a first semiconductor region (semiconductor region 35) of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact (contact 55) electrically connected to the first semiconductor region.
  • the first semiconductor region is provided adjacent to the transistor.
  • the transistor has a gate electrode (gate electrode 42) provided on the first surface side of the semiconductor layer so as to sandwich a part of the semiconductor layer.
  • the semiconductor region 35 is provided adjacent to the pixel transistor 30.
  • the semiconductor region 35 is provided adjacent to the semiconductor region 33, which is the source region or drain region of the pixel transistor 30.
  • the pixel transistor 30 also has a gate electrode 42 that is provided to sandwich a part of the semiconductor layer 110.
  • the imaging device 1 can have a structure that is advantageous for miniaturization of pixels.
  • the gate area of the pixel transistor can be increased, making it possible to improve the characteristics of the pixel transistor. It is possible to realize a photodetection device that is advantageous for miniaturization.
  • Fig. 10A is a diagram showing an example of a planar configuration of a pixel of an imaging device according to Modification 1 of the present disclosure.
  • Fig. 10B is a diagram for explaining an example of a cross-sectional configuration of a pixel of the imaging device.
  • Fig. 10B is a schematic diagram showing an example of the configuration of a pixel in the direction of line AA' shown in Fig. 10A.
  • the transfer transistor TR has a vertical gate structure. That is, the transfer transistor TR has a vertical gate (VG) structure.
  • the transfer transistor TR can also be called a vertical transistor.
  • At least a portion of each of the gate insulating film 45 and the gate electrode 46 of the transfer transistor TR is provided within the semiconductor layer 110.
  • At least a portion of each of the gate insulating film 45 and the gate electrode 46 is provided by digging into the semiconductor layer 110, for example, as shown in the example of FIG. 10B.
  • each part of the gate electrode 46 and the gate insulating film 45 of the transfer transistor TR is disposed so as to be embedded in, for example, the semiconductor layer 110.
  • the gate electrode 46 is provided so as to reach, for example, the photoelectric conversion unit 12.
  • the gate electrode 46 can be provided in the semiconductor layer 110 from between the floating diffusion FD and the trench 93 to the region of the photoelectric conversion unit 12.
  • the gate insulating film 45 is formed along the gate electrode 46 within the semiconductor layer 110.
  • the bottom B3 (lower end) of the gate electrode 46 of the transfer transistor TR is located, for example, below the bottom B2 of the trench 93.
  • the bottom B3 of the gate electrode 46 is formed, for example, to a region whose depth from the surface 11S1 of the semiconductor layer 110 is deeper than the bottom B2 of the trench 93.
  • the transfer transistor TR has a VG structure.
  • the gate electrode 46 of the transfer transistor TR can be provided so as to reach the photoelectric conversion unit 12. This makes it possible to improve the efficiency of charge transfer from the photoelectric conversion unit 12 to the floating diffusion FD.
  • the gate electrode 42 of the pixel transistor 30 is provided so that the bottom B1 of the gate electrode 42 is located higher than the bottom B3 of the gate electrode 46 of the transfer transistor TR and the bottom B2 of the trench 93. This allows the pixel transistor 30 to be appropriately isolated from other elements, and crosstalk between elements can be suppressed. It becomes possible to suppress the introduction of noise into the pixel signal.
  • FIG. 11A is a diagram showing an example of a planar configuration of a pixel of an imaging device according to Modification 2.
  • Fig. 11B is a diagram for explaining an example of a cross-sectional configuration of a pixel of an imaging device.
  • Fig. 11B is a schematic diagram showing an example of the configuration of a pixel in the direction of line AA' shown in Fig. 11A.
  • the gate electrode 46 of the transfer transistor TR may be provided adjacent to the trench 93.
  • the gate insulating film 45 and gate electrode 46 of the transfer transistor TR are provided to contact the trench 93, for example, as in the example shown in Figures 11A and 11B. This makes it possible to reduce the parasitic capacitance added to the transfer transistor TR.
  • the parasitic capacitance added to the transfer transistor TR can be reduced, and the characteristics of the transfer transistor TR can be improved.
  • the gm (mutual conductance) of the transfer transistor TR can be improved.
  • power consumption can be reduced.
  • FIG. 12A is a diagram showing an example of a planar configuration of a pixel of an imaging device according to Modification 3.
  • Fig. 12B is a diagram for explaining an example of a cross-sectional configuration of a pixel of the imaging device.
  • Fig. 12B is a schematic diagram showing an example of the configuration of a pixel in the direction of line AA' shown in Fig. 12A.
  • the pixel transistor 30 has a sidewall 43.
  • the sidewall 43 is provided on the side of the gate electrode 42 of the pixel transistor 30.
  • the transfer transistor TR also has a sidewall 47.
  • the sidewall 47 is provided on the side of the gate electrode 46 of the transfer transistor TR.
  • the sidewalls 43, 47 are made of an insulating film such as silicon oxide (SiO) or silicon nitride (SiN), and are provided around the gate electrodes 42, 46.
  • the sidewalls 43, 47 may be made of silicon oxynitride (SiON) or other materials.
  • an insulating film 49 is provided.
  • the insulating film 49 is provided in the semiconductor layer 110 between the floating diffusion FD and the gate electrode 46 of the transfer transistor TR.
  • the insulating film 49 is provided in a recessed portion 96 in the gate electrode 46. It can also be said that the insulating film 49 is disposed by replacing a part of the gate electrode 46.
  • the recessed portion 96 can also be said to be a groove portion (recess).
  • the insulating film 49 is composed of an insulating film such as an oxide film, a nitride film, or an oxynitride film.
  • the insulating film 49 is formed using silicon oxide (SiO), silicon nitride (SiN), aluminum oxide (AlO), or other insulating material.
  • the insulating film 49 can be provided, for example, in the region of the side of the gate electrode 46 that faces the floating diffusion FD (recessed portion 96 of the gate electrode 46 in FIG. 12B).
  • the insulating film 49 is provided, so that the parasitic capacitance added to the transfer transistor TR can be reduced.
  • the characteristics of the transfer transistor TR can be improved.
  • the insulating film 49 may be configured integrally with the sidewall 47. At least a portion of the sidewall 47 may be provided within the semiconductor layer 110 and disposed as the insulating film 49.
  • FIG. 13A is a diagram showing an example of a planar configuration of a pixel of an imaging device according to Modification 4.
  • Fig. 13B is a diagram for explaining an example of a cross-sectional configuration of a pixel of the imaging device.
  • Fig. 13B is a schematic diagram showing an example of the configuration of a pixel in the direction of line AA' shown in Fig. 13A.
  • an insulating film 48 may be provided.
  • the insulating film 48 is provided, for example, in the semiconductor layer 110, in a recessed portion 95 at the end of the gate electrode 42 of the pixel transistor 30.
  • the insulating film 48 can be said to be disposed by replacing part of the portion P1 of the gate electrode 42.
  • the insulating film 48 is provided in the recessed portion 96 of the gate electrode 42, making it possible to suppress deterioration of the characteristics of the pixel transistor 30 caused by variations in the gate position.
  • the shape and arrangement of the insulating film 48 of the imaging device 1 are not limited to the example shown in the figure.
  • the insulating film 48 may be provided on both ends of the gate electrode 42 of the pixel transistor 30.
  • the insulating film 48 may be configured integrally with the sidewall 43. At least a portion of the sidewall 43 may be provided within the semiconductor layer 110 and arranged as the insulating film 48.
  • Fig. 15A is a diagram showing an example of a planar configuration of a pixel of an imaging device according to Modification 5.
  • Fig. 15B is a diagram for explaining an example of a cross-sectional configuration of a pixel of the imaging device.
  • Fig. 15B is a schematic diagram showing an example of the configuration of a pixel in the direction of line AA' shown in Fig. 15A.
  • the transfer transistor TR may have multiple vertical gates (VG).
  • the transfer transistor TR has a gate electrode 46a and a gate electrode 46b.
  • the transfer transistor TR can transfer charges from the photoelectric conversion unit 12 by the gate electrode 46a and the gate electrode 46b, which are vertical gates. This makes it possible to improve the charge transfer efficiency.
  • FIGS. 16A and 16B are diagrams for explaining another example of the configuration of a pixel of an imaging device according to Modification 5.
  • an insulating film 49 may be provided in the recessed portion of at least one of the gate electrodes 46a and 46b.
  • the parasitic capacitance added to the transfer transistor TR can be reduced, and the characteristics of the transfer transistor TR can be improved.
  • (1-6. Modification 6) 17 is a diagram for explaining a configuration example of a pixel of an imaging device according to Modification 6.
  • the source region and the drain region of the pixel transistor 30 may have different sizes.
  • the size of the semiconductor region 33 close to the semiconductor region 35, which is a well contact region, is smaller than the size of the semiconductor region 32.
  • the size of the area of the active region 81 in which the pixel transistors 30 are arranged, on the semiconductor region 33 side closer to the semiconductor region 35, may be smaller than the size of the area on the semiconductor region 32 side.
  • the pixel transistors 30 may have, for example, a trapezoidal shape.
  • Fig. 18 is a diagram for explaining a configuration example of a pixel of an imaging device according to Modification 7.
  • the semiconductor region 35 may be provided adjacent to at least one of the gate electrode 42 and the gate insulating film 41 of the pixel transistor 30 in the pixel P.
  • the semiconductor region 35 is arranged in the active region 81 on the surface 11S1 side of the semiconductor layer 110 so as to be adjacent to the gate insulating film 41 and the gate electrode 42 of the pixel transistor 30.
  • the semiconductor region 35 is provided in contact with the active region 81 in which the gate electrode 42 and the like are arranged.
  • the shape of the pixel transistor 30 is not limited to the example shown in Fig. 18 and can be changed as appropriate.
  • the transistor has a gate electrode and a gate insulating film (gate electrode 42 and gate insulating film 41) provided on a first region (active region 81) of the semiconductor layer (semiconductor layer 110).
  • the first semiconductor region is provided in contact with the first region (active region 81) so as to be adjacent to at least one of the gate electrode and the gate insulating film of the transistor.
  • the imaging device 1 can also have a structure that is advantageous for miniaturization. Compared to a case in which the semiconductor region 35 and the pixel transistor 30 are disposed apart, the area of the region in which the transistors, etc. are disposed in the pixel P can be increased. The size of the pixel transistor 30 disposed in the pixel P can be increased, making it possible to improve the characteristics of the transistors (amplification transistor AMP, selection transistor SEL, etc.) of the readout circuit 20.
  • FIG. 19A is a diagram showing an example of a planar configuration of a pixel of an imaging device according to Modification 8.
  • Fig. 19B is a diagram for explaining an example of a cross-sectional configuration of a pixel of an imaging device.
  • Fig. 19B is a schematic diagram showing an example of the configuration of a pixel in the direction of line AA' shown in Fig. 19A.
  • a conductor region 36 is provided.
  • the conductor region 36 is provided around the semiconductor region 35. At least a portion of the conductor region 36 is provided in contact with the semiconductor region 35.
  • the conductor region 36 is formed adjacent to the semiconductor region 35, for example, on the surface 11S1 side of the semiconductor layer 110. In the example shown in Fig. 19B, the conductor region 36 is located above and inside the trenches 91 and 92.
  • the conductor region 36 is made of, for example, polysilicon doped with impurities. Note that the conductor region 36 (conductive portion) may be made of other conductive materials (e.g., metal materials, etc.). The conductor region 36 has, for example, an impurity concentration higher than the impurity concentration of the well 25.
  • the contact 55 is provided on the conductor region 36.
  • the contact 55 is electrically connected to the semiconductor region 35 and the well 25 via the conductor region 36.
  • the semiconductor region 35 provided in the well 25 is electrically connected to the contact 55 via the conductor region 36.
  • the impurity concentration of the semiconductor region 35 required for electrical connection with the contact 55 it is possible to reduce the impurity concentration of the semiconductor region 35 required for electrical connection with the contact 55.
  • the impurity concentration of the semiconductor region 35 it is possible to reduce the electric field between the semiconductor region 35 and the semiconductor region 33 (source region or drain region) of the pixel transistor 30. This makes it possible to suppress the occurrence of defects in the pixel transistor 30. It is also possible to prevent an increase in noise mixed into the pixel signal.
  • Fig. 20A is a diagram showing an example of a planar configuration of a pixel of an imaging device according to Modification 9.
  • Fig. 20B is a diagram for explaining an example of a cross-sectional configuration of a pixel of an imaging device.
  • Fig. 20B is a schematic diagram showing an example of the configuration of a pixel in the direction of line AA' shown in Fig. 20A.
  • the imaging device 1 may have a semiconductor region 37.
  • the semiconductor region 37 is provided in the semiconductor layer 110 around the floating diffusion FD.
  • the semiconductor region 37 is made of polysilicon doped with impurities. Note that the semiconductor region 37 may also be made of other conductive materials. At least a portion of the semiconductor region 37 is provided in contact with the floating diffusion FD.
  • the floating diffusions FD of the multiple pixels P (for example, pixels Pa to Pd in FIG. 7 and the like) that share the readout circuit 20 can be electrically connected to each other via the semiconductor region 37.
  • the floating diffusions FD of the pixels Pa to Pd are electrically connected to the amplification transistor AMP, reset transistor RST, etc. of the readout circuit 20 via the semiconductor region 37.
  • the floating diffusion FD and the semiconductor region 37 are made to have a side contact structure, which makes it possible to improve the area efficiency of the pixel P. It becomes possible to secure the area of the region in the pixel P in which the transistors and the like are arranged.
  • FIG. 21 is a diagram showing an example of pixel arrangement of an imaging device according to a second embodiment of the present disclosure.
  • a pixel P of the imaging device 1 has multiple photoelectric conversion units 12 (photoelectric conversion unit 12a and photoelectric conversion unit 12b in the example shown in FIG. 21).
  • Photoelectric conversion unit 12b is provided next to photoelectric conversion unit 12a. It can also be said that a pixel having photoelectric conversion unit 12a and a pixel having photoelectric conversion unit 12b are provided.
  • one lens 21 (lens unit) is provided for multiple photoelectric conversion units 12, for example, two photoelectric conversion units 12 (photoelectric conversion unit 12a, photoelectric conversion unit 12b).
  • the photoelectric conversion units 12a and 12b receive light that has passed through different regions of an optical system such as an imaging lens, and perform pupil division.
  • phase difference data (phase difference information) can be obtained.
  • phase difference AF Auto Focus
  • the readout circuit 20 is configured to be capable of outputting a first pixel signal and a second pixel signal for each pixel P that shares the readout circuit 20.
  • the readout circuit 20 can also read out a pixel signal corresponding to the charge obtained by adding up the charge converted by the photoelectric conversion unit 12a and the charge converted by the photoelectric conversion unit 12b.
  • FIG. 22 is a diagram showing an example of the planar configuration of a pixel of an imaging device according to the second embodiment.
  • a pixel P of the imaging device 1 includes transfer transistors TRa and TRb, floating diffusions FDa and FDb, pixel transistors 30a and 30b, and a semiconductor region 35.
  • the transfer transistor TRa is configured to be capable of transferring charges photoelectrically converted by the photoelectric conversion unit 12a to the floating diffusion FDa.
  • the transfer transistor TRb is configured to be capable of transferring charges photoelectrically converted by the photoelectric conversion unit 12b to the floating diffusion FDb.
  • the floating diffusion FDa can store charges photoelectrically converted by the photoelectric conversion unit 12a.
  • the floating diffusion FDb can store charges photoelectrically converted by the photoelectric conversion unit 12b.
  • the readout circuit 20 is configured to be capable of outputting, for example, a pixel signal based on the charge accumulated in the floating diffusion FDa, a pixel signal based on the charge accumulated in the floating diffusion FDb, etc. Also, for example, the readout circuit 20 is configured to be capable of outputting a pixel signal corresponding to the charge obtained by adding up the charge accumulated in the floating diffusion FDa and the charge accumulated in the floating diffusion FDb.
  • the pixel transistor 30a and the pixel transistor 30b are, for example, transistors of the readout circuit 20.
  • the semiconductor region 32a and the semiconductor region 33a are the source region and the drain region of the pixel transistor 30a.
  • One of the semiconductor regions 32a and 33a is the source region of the pixel transistor 30a, and the other of the semiconductor regions 32a and 33a is the drain region of the pixel transistor 30a.
  • the semiconductor region 32b and the semiconductor region 33b are the source region and the drain region of the pixel transistor 30b.
  • One of the semiconductor regions 32b and 33b is the source region of the pixel transistor 30b, and the other of the semiconductor regions 32b and 33b is the drain region of the pixel transistor 30b.
  • the pixel transistors 30a and 30b are used as an amplification transistor AMP, a selection transistor SEL, a transistor FDG, a reset transistor RST, or the like.
  • the pixel transistor 30a or the pixel transistor 30b of some pixels P may be a dummy transistor.
  • the readout circuit 20 may include a dummy transistor as the pixel transistor 30a or the pixel transistor 30b.
  • One pixel transistor 30 may be provided for each of the photoelectric conversion units 12a and 12b.
  • the pixel transistors 30a and 30b can each be configured as a Fin type transistor.
  • the pixel transistor 30a has a gate electrode 42a that includes multiple portions P1a (fin portions).
  • the multiple portions P1a of the gate electrode 42a are provided in the semiconductor layer 110 so as to sandwich a portion of the semiconductor layer 110 that becomes the channel region of the pixel transistor 30a.
  • the pixel transistor 30b also has a gate electrode 42b that includes multiple portions P1b (fin portions).
  • the multiple portions P1b of the gate electrode 42b are provided in the semiconductor layer 110 so as to sandwich a portion of the semiconductor layer 110 that becomes the channel region of the pixel transistor 30b.
  • the pixel transistors 30a and 30b each have, for example, a recessed Fin structure and can also be called a recessed Fin transistor.
  • the imaging device 1 may also have a separation portion 95a and a separation portion 95b.
  • the separation portion 95a and the separation portion 95b may each include a trench, for example.
  • the separation portion 95a and the separation portion 95b may each be provided between the photoelectric conversion portion 12a and the photoelectric conversion portion 12b in the semiconductor layer 110, for example.
  • Isolation portion 95a and isolation portion 95b may be made of an insulating material, or may be made of a semiconductor region formed by ion implantation.
  • isolation portion 95a and isolation portion 95b may be made of a p-type semiconductor region or an n-type semiconductor region.
  • the separation portion 95a is provided, for example, between adjacent floating diffusions FD on the surface 11S1 side of the semiconductor layer 110. In the example shown in FIG. 22, the separation portion 95a is formed between the floating diffusion FDa and the floating diffusion FDb.
  • the separation portion 95b is provided between adjacent pixel transistors 30 on the surface 11S1 side of the semiconductor layer 110. In the example shown in FIG. 22, the separation portion 95b is formed between pixel transistor 30a and pixel transistor 30b.
  • the semiconductor region 35 is provided between the separation portion 95a and separation portion 95b in a plan view, for example, as shown in FIG. 22.
  • the semiconductor region 35 is provided adjacent to the pixel transistor 30a and the pixel transistor 30b.
  • the semiconductor region 35 is disposed adjacent to the source region or drain region of the pixel transistor 30a and the source region or drain region of the pixel transistor 30b.
  • the semiconductor region 35, the source region or drain region of the pixel transistor 30a, and the source region or drain region of the pixel transistor 30b are provided in the active region 81.
  • the semiconductor region 35 is provided adjacent to the semiconductor region 33a of the pixel transistor 30a and the semiconductor region 33b of the pixel transistor 30b.
  • the semiconductor region 35 may be provided adjacent to the semiconductor regions 32a and 32b.
  • the semiconductor region 35 may also be provided adjacent to the gates of the pixel transistors 30a and 30b.
  • the semiconductor region 35 is provided adjacent to the pixel transistor 30a and the pixel transistor 30b.
  • This allows the imaging device 1 to have a structure that is advantageous for miniaturization. Compared to a case in which the semiconductor region 35 and the pixel transistors 30a and 30b are provided apart, the area of the region in which the transistors and the like are arranged in the pixel P can be increased. It is possible to increase the size of the transistors arranged in the pixel P.
  • the pixel transistors 30a, 30b can each be configured as a Fin-type transistor. This allows the area of the gate electrodes 42a, 42b of the pixel transistors 30a, 30b to be increased. It is possible to increase the effective gate width, etc., of each of the gate electrodes 42a, 42b.
  • the gate area of the transistors of the readout circuit 20 e.g., the amplification transistor AMP
  • the amplification transistor AMP can be increased, making it possible to suppress noise that gets mixed into the pixel signal.
  • the photodetector includes a semiconductor layer (semiconductor layer 110), a plurality of pixels including a first pixel having a first photoelectric conversion element and a second photoelectric conversion element (photoelectric conversion unit 12a and photoelectric conversion unit 12b, i.e., a first photoelectric conversion region and a second photoelectric conversion region) provided in the semiconductor layer, and trenches (trench 91, trench 92) provided between the adjacent pixels in the semiconductor layer.
  • the first pixel includes a first transistor and a second transistor (pixel transistor 30a, pixel transistor 30b) provided on the first surface side of the semiconductor layer, a first semiconductor region (semiconductor region 35) of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact (contact 55) electrically connected to the first semiconductor region.
  • the first semiconductor region is provided adjacent to the first transistor and the second transistor.
  • the first transistor has a gate electrode (e.g., gate electrode 42a) provided on the first surface side of the semiconductor layer so as to sandwich a part of the semiconductor layer.
  • the semiconductor region 35 is provided adjacent to the pixel transistor 30a and the pixel transistor 30b.
  • the semiconductor region 35 is provided adjacent to the semiconductor region 33a, which is the source region or drain region of the pixel transistor 30a, and the semiconductor region 33b, which is the source region or drain region of the pixel transistor 30b.
  • the pixel transistor 30a also has a gate electrode 42a that is provided to sandwich a part of the semiconductor layer 110.
  • the imaging device 1 can have a structure that is advantageous for miniaturization of pixels.
  • the gate area of the pixel transistor can be increased, making it possible to improve the characteristics of the pixel transistor. It is possible to realize a photodetection device that is advantageous for miniaturization.
  • (2-1. Modification 10) 23 is a diagram for explaining a configuration example of a pixel of an imaging device according to Modification 10.
  • the transfer transistor TR may have a vertical gate (VG) structure.
  • the transfer transistors TRa and TRb each have a vertical gate (VG).
  • VG vertical gate
  • (2-2. Modification 11) 24 is a diagram for explaining a configuration example of a pixel of an imaging device according to Modification 11.
  • the gate electrode 46a of the transfer transistor TRa and the gate electrode 46b of the transfer transistor TRb may be provided adjacent to the trench 91 (or the trench 93). In this case, the parasitic capacitance added to the transfer transistors TRa and TRb can be reduced. The characteristics of the transfer transistors TRa and TRb can be improved.
  • FIG. 25 is a diagram for explaining another example of the configuration of a pixel of an imaging device according to Modification 11.
  • the imaging device 1 may have an insulating film 49a and an insulating film 49b.
  • the insulating film 49a is provided in the semiconductor layer 110 between the floating diffusion FDa and the gate electrode 46a of the transfer transistor TRa.
  • the insulating film 49a may be formed, for example, in a recessed portion of the gate electrode 46a.
  • the insulating film 49b is provided in the semiconductor layer 110 between the floating diffusion FDb and the gate electrode 46b of the transfer transistor TRb.
  • the insulating film 49b can be formed, for example, in a recessed portion of the gate electrode 46b.
  • the insulating film 48 described above may be provided in the recessed portion at the end of the gate electrode 42a of the pixel transistor 30a. Also, for example, the insulating film 48 may be provided in the recessed portion at the end of the gate electrode 42b of the pixel transistor 30b.
  • (2-3. Modification 12) 26 is a diagram for explaining a configuration example of a pixel of an imaging device according to Modification 12.
  • Each of the transfer transistors TRa and TRb may have a plurality of vertical gates (VG).
  • the transfer transistor TRa has a gate electrode 46a1 and a gate electrode 46a2.
  • the transfer transistor TRb has a gate electrode 46b1 and a gate electrode 46b2.
  • FIG. 27 is a diagram for explaining another example of the configuration of a pixel of an imaging device according to Modification 12.
  • the gate electrode 46a1 and the gate electrode 46a2 of the transfer transistor TRa are provided between the pixel transistor 30a and the floating diffusion FDa.
  • the pixel transistor 30a, the gate electrode 46a1 (or the gate electrode 46a2), and the floating diffusion FDa are arranged to be aligned in the Y-axis direction in a plan view.
  • the gate electrodes 46b1 and 46b2 of the transfer transistor TRb are provided between the pixel transistor 30b and the floating diffusion FDb.
  • the pixel transistor 30b, the gate electrode 46b1 (or the gate electrode 46b2), and the floating diffusion FDb are arranged in the Y-axis direction in a plan view.
  • the pixel transistor 30a, the gate electrode 46a1 (or the gate electrode 46a2), and the floating diffusion FDa may be arranged side by side in the X-axis direction in a planar view.
  • the pixel transistor 30b, the gate electrode 46b1 (or the gate electrode 46b2), and the floating diffusion FDb may be arranged side by side in the X-axis direction in a planar view.
  • Fig. 28 is a diagram for explaining a configuration example of a pixel of an imaging device according to Modification 13.
  • the source region and the drain region of the pixel transistor 30a (or the pixel transistor 30b) may have different sizes from each other, as in the example shown in Fig. 28.
  • the size of the semiconductor region 33a close to the semiconductor region 35 is smaller than the size of the semiconductor region 32a.
  • the size of the region on the semiconductor region 33a side close to the semiconductor region 35 may be smaller than the size of the region on the semiconductor region 32a side.
  • the size of the semiconductor region 33b close to the semiconductor region 35 is smaller than the size of the semiconductor region 32b.
  • the size of the region on the semiconductor region 33b side close to the semiconductor region 35 may be smaller than the size of the region on the semiconductor region 32b side.
  • the pixel transistor 30a and the pixel transistor 30b may each have, for example, a trapezoidal shape.
  • Fig. 29 is a diagram for explaining a configuration example of a pixel of an imaging device according to Modification Example 14.
  • the imaging device 1 may have a semiconductor region 37 that electrically connects a plurality of floating diffusions FD, as in the example shown in Fig. 29.
  • the imaging device 1 may also have the above-mentioned conductor region 36 that electrically connects a contact 55 and the semiconductor region 35.
  • FIG. 30 is a diagram for explaining a configuration example of a pixel of an imaging device according to Modification 15.
  • a semiconductor region 35 may be provided between a semiconductor region 33a which is a source region or drain region of a pixel transistor 30a and a semiconductor region 33b which is a source region or drain region of a pixel transistor 30b. In this case, a distance between a contact 55 and the channel regions of the pixel transistors 30a and 30b can be ensured.
  • the imaging device 1 may have a separation portion 95a and a separation portion 95b, as in the example shown in FIG. 30.
  • the imaging device 1 may be configured to have only one of the separation portion 95a and the separation portion 95b.
  • the separation portion 95b may not be disposed.
  • the semiconductor region 35 may be disposed between the semiconductor region 32a, which is the source region or drain region of the pixel transistor 30a, and the semiconductor region 32b, which is the source region or drain region of the pixel transistor 30b.
  • the semiconductor region 35 (or the active region 81) can have a first portion 61 and a second portion 62.
  • the first portion 61 is provided adjacent to the pixel transistors 30a and 30b in the horizontal direction (X-axis direction) in a plan view.
  • the first portion 61 is disposed, for example, adjacent to the gates of the pixel transistors 30a and 30b.
  • the second portion 62 is in contact with the first portion 61 in the vertical direction (Y-axis direction).
  • the contact 55 is provided in the second portion 62.
  • the contact 55 is provided on the second portion 62.
  • the first portion 61 has, for example, an impurity concentration lower than the impurity concentration of the second portion 62.
  • the semiconductor region 35 is located between the isolation portions 95a and 95b, and the contact 55 is separated from the channel regions of the pixel transistors 30a and 30b. This makes it possible to prevent noise from being mixed into the pixel signal. It is also possible to prevent a decrease in the accuracy of phase difference detection. It is also expected that a decrease in image quality can be prevented. Furthermore, by separating (moving away) the contact 55 from the channel region, it is also possible to lower the impurity concentration near the portion where the channel region and the semiconductor region 35 are adjacent to each other. This makes it possible to design in a way that reduces the generation of strong electric fields.
  • the first portion 61 has, for example, an impurity concentration lower than the impurity concentration of the second portion 62 connected to the contact 55.
  • the impurity concentration of the first portion 61 By lowering the impurity concentration of the first portion 61, it is possible to suppress the generation of a strong electric field between the first portion 61 and the channel region. This is expected to reduce noise mixed into the pixel signal.
  • FIG. 32 is a diagram for explaining a configuration example of an imaging device according to a third embodiment of the present disclosure.
  • the semiconductor region 35 and the pixel transistor 30 are arranged in the same active region, but the semiconductor region 35 and the pixel transistor 30 may be arranged in different active regions.
  • the pixel transistor 30 is provided in the active region 81a, and the semiconductor region 35 is provided in the active region 81b.
  • the transfer transistor TR and the floating diffusion FD are provided in the active region 82.
  • the configuration of the pixel P of the imaging device 1 is not limited to the example shown in FIG. 32, and can be changed as appropriate.
  • FIGS. 33A to 33E are diagrams for explaining another example configuration of the imaging device according to the third embodiment.
  • the transfer transistor TR may have a vertical gate (VG) structure as shown in FIG. 33A.
  • the gate electrode 46 of the transfer transistor TR may be provided adjacent to the trench 91 (or trench 93) as shown in FIG. 33B.
  • the imaging device 1 may have an insulating film 49 as shown in FIG. 33C.
  • the transfer transistor TR may have multiple vertical gates (gate electrodes 46a and 46b in FIG. 33D) as shown in FIG. 33D.
  • an insulating film 49 may be provided in the recessed portions of the gate electrodes 46a and 46 as shown in the example in FIG. 33E.
  • FIG. 34 is a diagram for explaining a configuration example of an imaging device according to a third embodiment of the present disclosure.
  • a pixel P of the imaging device 1 may have multiple photoelectric conversion units 12 (photoelectric conversion unit 12a, photoelectric conversion unit 12b in the example shown in FIG. 34). It can also be said that a pixel having a photoelectric conversion unit 12a and a pixel having a photoelectric conversion unit 12b are provided.
  • the semiconductor region 35 and the pixel transistor 30a (and also the pixel transistor 30b) may be arranged in different active regions.
  • One lens 21 (lens unit) is provided for multiple photoelectric conversion units 12, for example two photoelectric conversion units 12 (photoelectric conversion unit 12a, photoelectric conversion unit 12b).
  • Phase difference data can be obtained by using a first pixel signal based on the charge photoelectrically converted by photoelectric conversion unit 12a and a second pixel signal based on the charge photoelectrically converted by photoelectric conversion unit 12b.
  • Phase difference AF can be performed by using the phase difference data.
  • FIGS. 35A to 35E are diagrams for explaining another example configuration of the imaging device according to the third embodiment.
  • the transfer transistors TRa and TRb may each have a vertical gate (VG) structure as shown in FIG. 35A.
  • the gate electrode 46a of the transfer transistor TRa and the gate electrode 46b of the transfer transistor TRb may be provided adjacent to the trench 91 (or trench 93).
  • the imaging device 1 may have an insulating film 49a and an insulating film 49b as shown in FIG. 35C.
  • the transfer transistors TRa and TRb may each have multiple vertical gates (VG).
  • the transfer transistor TRa may have gate electrodes 46a1 and 46a2.
  • the transfer transistor TRb may have gate electrodes 46b1 and 46b2.
  • the imaging device 1 may have a semiconductor region 37 that electrically connects multiple floating diffusions FD, as in the example shown in FIG. 35E.
  • the imaging device 1 may also have the above-mentioned conductor region 36 that electrically connects the contact 55 and the semiconductor region 35.
  • the pixel transistor 30 has a gate electrode 42 arranged to sandwich a part of the semiconductor layer 110.
  • the pixel transistor 30 can be configured as a Fin-type transistor. This allows the imaging device 1 to have a structure that is advantageous for miniaturization of pixels.
  • the gate area of the pixel transistor can be increased, making it possible to improve the characteristics of the pixel transistor. It is possible to realize a photodetection device that is advantageous for miniaturization.
  • the imaging device 1 and the like can be applied to any type of electronic device equipped with an imaging function, for example, a camera system such as a digital still camera or a video camera, a mobile phone equipped with an imaging function, etc.
  • Fig. 36 shows a schematic configuration of an electronic device 1000.
  • the electronic device 1000 includes, for example, a lens group 1001, an imaging device 1, a DSP (Digital Signal Processor) circuit 1002, a frame memory 1003, a display unit 1004, a recording unit 1005, an operation unit 1006, and a power supply unit 1007, which are interconnected via a bus line 1008.
  • a lens group 1001 an imaging device 1
  • a DSP (Digital Signal Processor) circuit 1002 a frame memory 1003, a display unit 1004, a recording unit 1005, an operation unit 1006, and a power supply unit 1007, which are interconnected via a bus line 1008.
  • DSP Digital Signal Processor
  • the lens group 1001 captures incident light (image light) from a subject and forms an image on the imaging surface of the imaging device 1.
  • the imaging device 1 converts the amount of incident light formed on the imaging surface by the lens group 1001 into an electrical signal on a pixel-by-pixel basis and supplies the signal as a pixel signal to the DSP circuit 1002.
  • the DSP circuit 1002 is a signal processing circuit that processes the signal supplied from the imaging device 1.
  • the DSP circuit 1002 outputs image data obtained by processing the signal from the imaging device 1.
  • the frame memory 1003 temporarily holds the image data processed by the DSP circuit 1002 on a frame-by-frame basis.
  • the display unit 1004 is, for example, a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and records image data of moving images or still images captured by the imaging device 1 on a recording medium such as a semiconductor memory or a hard disk.
  • a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel
  • a recording medium such as a semiconductor memory or a hard disk.
  • the operation unit 1006 outputs operation signals for various functions of the electronic device 1000 in accordance with operations by the user.
  • the power supply unit 1007 appropriately supplies various types of power to the DSP circuit 1002, frame memory 1003, display unit 1004, recording unit 1005, and operation unit 1006 to these devices.
  • the technology according to the present disclosure can be applied to various products.
  • the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, or a robot.
  • FIG. 37 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology disclosed herein can be applied.
  • the vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050.
  • Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio/video output unit 12052, and an in-vehicle network I/F (interface) 12053.
  • the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the drive system control unit 12010 functions as a control device for a drive force generating device for generating the drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force for the vehicle.
  • the body system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs.
  • the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, tail lamps, brake lamps, turn signals, and fog lamps.
  • radio waves or signals from various switches transmitted from a portable device that replaces a key can be input to the body system control unit 12020.
  • the body system control unit 12020 accepts the input of these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.
  • the outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000.
  • the image capturing unit 12031 is connected to the outside-vehicle information detection unit 12030.
  • the outside-vehicle information detection unit 12030 causes the image capturing unit 12031 to capture images outside the vehicle and receives the captured images.
  • the outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received.
  • the imaging unit 12031 can output the electrical signal as an image, or as distance measurement information.
  • the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared light.
  • the in-vehicle information detection unit 12040 detects information inside the vehicle.
  • a driver state detection unit 12041 that detects the state of the driver is connected.
  • the driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's degree of fatigue or concentration based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.
  • the microcomputer 12051 can calculate the control target values of the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, and output a control command to the drive system control unit 12010.
  • the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating vehicle collisions, following based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.
  • ADAS Advanced Driver Assistance System
  • the microcomputer 12051 can also perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.
  • the microcomputer 12051 can also output control commands to the body system control unit 12020 based on information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.
  • the audio/image output unit 12052 transmits at least one output signal of audio and image to an output device capable of visually or audibly notifying the occupants of the vehicle or the outside of the vehicle of information.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices.
  • the display unit 12062 may include, for example, at least one of an on-board display and a head-up display.
  • FIG. 38 shows an example of the installation position of the imaging unit 12031.
  • the vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100.
  • the imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100.
  • the imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100.
  • the imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100.
  • the images of the front acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.
  • FIG. 38 shows an example of the imaging ranges of the imaging units 12101 to 12104.
  • Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose
  • imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively
  • imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door.
  • an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple imaging elements, or an imaging element having pixels for phase difference detection.
  • the microcomputer 12051 can obtain the distance to each solid object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and can extract as a preceding vehicle, in particular, the closest solid object on the path of the vehicle 12100 that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km/h or faster). Furthermore, the microcomputer 12051 can set the inter-vehicle distance that should be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on the driver's operation.
  • automatic braking control including follow-up stop control
  • automatic acceleration control including follow-up start control
  • the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects, such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, based on the distance information obtained from the imaging units 12101 to 12104, and can use the data to automatically avoid obstacles.
  • the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see.
  • the microcomputer 12051 determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or exceeds a set value and there is a possibility of a collision, it can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the image captured by the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the image captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian.
  • the audio/image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian.
  • the audio/image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
  • the technology according to the present disclosure can be applied to, for example, the imaging unit 12031.
  • the imaging device 1 or the like can be applied to the imaging unit 12031.
  • the technology according to the present disclosure (Application example to endoscopic surgery system)
  • the technology according to the present disclosure can be applied to various products.
  • the technology according to the present disclosure may be applied to an endoscopic surgery system.
  • FIG. 39 is a diagram showing an example of the general configuration of an endoscopic surgery system to which the technology disclosed herein (the present technology) can be applied.
  • an operator (doctor) 11131 is shown using an endoscopic surgery system 11000 to perform surgery on a patient 11132 on a patient bed 11133.
  • the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.
  • the endoscope 11100 is composed of a lens barrel 11101, the tip of which is inserted into the body cavity of the patient 11132 at a predetermined length, and a camera head 11102 connected to the base end of the lens barrel 11101.
  • the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.
  • the tip of the tube 11101 has an opening into which an objective lens is fitted.
  • a light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the tube by a light guide extending inside the tube 11101, and is irradiated via the objective lens towards an object to be observed inside the body cavity of the patient 11132.
  • the endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.
  • An optical system and an image sensor are provided inside the camera head 11102, and the reflected light (observation light) from the object of observation is focused on the image sensor by the optical system.
  • the image sensor converts the observation light photoelectrically to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image.
  • the image signal is sent to the camera control unit (CCU: Camera Control Unit) 11201 as RAW data.
  • CCU Camera Control Unit
  • the CCU 11201 is composed of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and controls the overall operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102, and performs various image processing on the image signal, such as development processing (demosaic processing), in order to display an image based on the image signal.
  • a CPU Central Processing Unit
  • GPU Graphics Processing Unit
  • the display device 11202 under the control of the CCU 11201, displays an image based on the image signal that has been subjected to image processing by the CCU 11201.
  • the light source device 11203 is composed of a light source such as an LED (Light Emitting Diode) and supplies irradiation light to the endoscope 11100 when photographing the surgical site, etc.
  • a light source such as an LED (Light Emitting Diode) and supplies irradiation light to the endoscope 11100 when photographing the surgical site, etc.
  • the input device 11204 is an input interface for the endoscopic surgery system 11000.
  • a user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204.
  • the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.
  • the treatment tool control device 11205 controls the operation of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc.
  • the insufflation device 11206 sends gas into the body cavity of the patient 11132 via the insufflation tube 11111 to inflate the body cavity in order to ensure a clear field of view for the endoscope 11100 and to ensure a working space for the surgeon.
  • the recorder 11207 is a device capable of recording various types of information related to the surgery.
  • the printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.
  • the light source device 11203 that supplies irradiation light to the endoscope 11100 when photographing the surgical site can be composed of a white light source composed of, for example, an LED, a laser light source, or a combination of these.
  • a white light source composed of, for example, an LED, a laser light source, or a combination of these.
  • the white light source is composed of a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so that the white balance of the captured image can be adjusted in the light source device 11203.
  • the light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals.
  • the image sensor of the camera head 11102 may be controlled to acquire images in a time-division manner in synchronization with the timing of the change in the light intensity, and the images may be synthesized to generate an image with a high dynamic range that is free of so-called blackout and whiteout.
  • the light source device 11203 may be configured to supply light of a predetermined wavelength band corresponding to special light observation.
  • special light observation for example, by utilizing the wavelength dependency of light absorption in body tissue, a narrow band of light is irradiated compared to the light irradiated during normal observation (i.e., white light), and a specific tissue such as blood vessels on the surface of the mucosa is photographed with high contrast, so-called narrow band imaging is performed.
  • fluorescent observation may be performed in which an image is obtained by fluorescence generated by irradiating excitation light.
  • excitation light is irradiated to the body tissue and the fluorescence from the body tissue is observed (autofluorescence observation), or a reagent such as indocyanine green (ICG) is locally injected into the body tissue and excitation light corresponding to the fluorescent wavelength of the reagent is irradiated to the body tissue to obtain a fluorescent image.
  • the light source device 11203 may be configured to supply narrow band light and/or excitation light corresponding to such special light observation.
  • FIG. 40 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in FIG. 39.
  • the camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405.
  • the CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413.
  • the camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.
  • the lens unit 11401 is an optical system provided at the connection with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401.
  • the lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.
  • the imaging unit 11402 is composed of an imaging element.
  • the imaging element constituting the imaging unit 11402 may be one (so-called single-plate type) or multiple (so-called multi-plate type).
  • each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these.
  • the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical site.
  • 3D dimensional
  • the imaging unit 11402 does not necessarily have to be provided in the camera head 11102.
  • the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.
  • the driving unit 11403 is composed of an actuator, and moves the zoom lens and focus lens of the lens unit 11401 a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.
  • the communication unit 11404 is configured with a communication device for transmitting and receiving various information to and from the CCU 11201.
  • the communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.
  • the communication unit 11404 also receives control signals for controlling the operation of the camera head 11102 from the CCU 11201, and supplies them to the camera head control unit 11405.
  • the control signals include information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value during imaging, and/or information specifying the magnification and focus of the captured image.
  • the above-mentioned frame rate, exposure value, magnification, focus, and other imaging conditions may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal.
  • the endoscope 11100 is equipped with so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.
  • the camera head control unit 11405 controls the operation of the camera head 11102 based on a control signal from the CCU 11201 received via the communication unit 11404.
  • the communication unit 11411 is configured with a communication device for transmitting and receiving various information to and from the camera head 11102.
  • the communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.
  • the communication unit 11411 also transmits to the camera head 11102 a control signal for controlling the operation of the camera head 11102.
  • the image signal and the control signal can be transmitted by electrical communication, optical communication, etc.
  • the image processing unit 11412 performs various image processing operations on the image signal, which is the RAW data transmitted from the camera head 11102.
  • the control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100, and the display of the captured images obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.
  • the control unit 11413 also causes the display device 11202 to display the captured image showing the surgical site, etc., based on the image signal that has been image-processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition techniques. For example, the control unit 11413 can recognize surgical tools such as forceps, specific body parts, bleeding, mist generated when the energy treatment tool 11112 is used, etc., by detecting the shape and color of the edges of objects included in the captured image. When the control unit 11413 causes the display device 11202 to display the captured image, it may use the recognition result to superimpose various types of surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.
  • various image recognition techniques such as forceps, specific body parts, bleeding, mist generated when the energy treatment tool 11112 is used, etc.
  • the transmission cable 11400 that connects the camera head 11102 and the CCU 11201 is an electrical signal cable that supports electrical signal communication, an optical fiber that supports optical communication, or a composite cable of these.
  • communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.
  • the technology of the present disclosure can be suitably applied to, for example, the imaging unit 11402 provided in the camera head 11102 of the endoscope 11100.
  • the technology of the present disclosure it is possible to provide a high-definition endoscope 11100.
  • an imaging device has been described as an example, but the light detection device of the present disclosure may be, for example, a device that receives incident light and converts the light into an electric charge.
  • the output signal may be a signal of image information or a signal of distance measurement information.
  • the light detection device (imaging device) may be applied to an image sensor, a distance measurement sensor, and the like. Note that the present disclosure is not limited to back-illuminated image sensors, but may also be applied to front-illuminated image sensors.
  • the optical detection device disclosed herein may also be applied as a distance measurement sensor capable of measuring distance using the Time Of Flight (TOF) method.
  • the optical detection device (imaging device) may also be applied as a sensor capable of detecting events, for example, an event-driven sensor (called an Event Vision Sensor (EVS), Event Driven Sensor (EDS), Dynamic Vision Sensor (DVS), etc.).
  • EVS Event Vision Sensor
  • EDS Event Driven Sensor
  • DVS Dynamic Vision Sensor
  • the photodetector of one embodiment of the present disclosure includes a semiconductor layer, a plurality of pixels including a first pixel having a photoelectric conversion element provided in the semiconductor layer, and a trench provided in the semiconductor layer between adjacent pixels.
  • the first pixel includes a transistor provided on the first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region.
  • the first semiconductor region is provided adjacent to the transistor.
  • the transistor has a gate electrode provided on the first surface side of the semiconductor layer so as to sandwich a portion of the semiconductor layer. Therefore, the photodetector can have a structure that is advantageous for miniaturization of pixels. It is possible to realize a photodetector that is advantageous for miniaturization.
  • the photodetector of one embodiment of the present disclosure includes a semiconductor layer, a plurality of pixels including a first pixel having a photoelectric conversion element provided in the semiconductor layer, and a trench provided in the semiconductor layer between adjacent pixels.
  • the first pixel includes a transistor having a gate electrode provided on the first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region.
  • the first semiconductor region is provided adjacent to the transistor.
  • At least a portion of the gate electrode of the transistor is provided within the semiconductor layer.
  • the photodetector can have a structure that is advantageous for miniaturization of pixels.
  • the gate area of the transistor can be increased, making it possible to improve the characteristics of the transistor. It is possible to realize a photodetector that is advantageous for miniaturization.
  • a semiconductor layer A plurality of pixels including a first pixel having a photoelectric conversion element provided in the semiconductor layer; a trench provided in the semiconductor layer between adjacent ones of the pixels; the first pixel includes a transistor provided on a first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region; the first semiconductor region is provided adjacent to the transistor; the transistor has a gate electrode provided on the first surface side of the semiconductor layer so as to sandwich a part of the semiconductor layer.
  • the transistor has a second semiconductor region of a second conductivity type provided in the semiconductor layer; the second semiconductor region is a source region or a drain region, The photodetector according to any one of (1) to (5), wherein the first semiconductor region is provided adjacent to the second semiconductor region.
  • the transistor has a third semiconductor region of the second conductivity type provided in the semiconductor layer; the second semiconductor region is one of the source region and the drain region, the third semiconductor region is the other of the source region and the drain region, The photodetector according to (6), wherein the second semiconductor region is smaller than the third semiconductor region.
  • the first semiconductor region is a p-type semiconductor region
  • the transistor has a gate electrode and a gate insulating film provided on the first region of the semiconductor layer;
  • a first well of the first conductivity type provided in the semiconductor layer; the first semiconductor region is provided in the first well;
  • the first pixel is Floating diffusion and and a transfer transistor provided on a first surface side of the semiconductor layer and capable of transferring charges converted by the photoelectric conversion element to the floating diffusion.
  • the gate electrode of the transistor has a plurality of first portions provided in the semiconductor layer so as to sandwich a part of the semiconductor layer; The photodetector according to (12), wherein a bottom of the first portion is located above a bottom of the gate electrode of the transfer transistor.
  • the plurality of pixels includes a second pixel adjacent to the first pixel, The photodetector according to any one of (1) to (18), wherein the first pixel and the second pixel each have the photoelectric conversion element, a floating diffusion, the transistor, and the first semiconductor region.
  • a fourth semiconductor region electrically connecting the floating diffusion of the first pixel and the floating diffusion of the second pixel;
  • the photodetector according to any one of (1) to (21), wherein the transistor is an amplification transistor, a selection transistor, a reset transistor, a switching transistor, or a dummy transistor.
  • the semiconductor layer further includes a lens provided on a second surface side opposite to the first surface, The photodetector according to any one of (1) to (22), wherein the photoelectric conversion element photoelectrically converts light transmitted through the lens.
  • a semiconductor layer a plurality of pixels including a first pixel having a first photoelectric conversion element and a second photoelectric conversion element provided in the semiconductor layer; a trench provided in the semiconductor layer between adjacent ones of the pixels; the first pixel includes a first transistor and a second transistor provided on a first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region; the first semiconductor region is provided adjacent to the first transistor and the second transistor; the first transistor has a gate electrode provided on the first surface side of the semiconductor layer so as to sandwich a part of the semiconductor layer.
  • a separation portion provided around the plurality of first portions in the semiconductor layer;
  • the first pixel is a first isolation portion provided between the first transistor and the second transistor; a first floating diffusion and a second floating diffusion;
  • An optical system a light detection device that receives light transmitted through the optical system;
  • the light detection device includes: A semiconductor layer; a plurality of pixels including a first pixel having a first photoelectric conversion element and a second photoelectric conversion element provided in the semiconductor layer; a trench provided in the semiconductor layer between adjacent ones of the pixels;
  • the first pixel includes a first transistor and a second transistor provided on a first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region;
  • the first semiconductor region is provided adjacent to the first transistor and the second transistor;
  • the first transistor has a gate electrode provided on the first surface side of the semiconductor layer so as to sandwich a part of the semiconductor layer therebetween.
  • a semiconductor layer A plurality of pixels including a first pixel having a photoelectric conversion element provided in the semiconductor layer; a trench provided in the semiconductor layer between adjacent ones of the pixels; the first pixel includes a transistor having a gate electrode provided on a first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region; the first semiconductor region is provided adjacent to the transistor; At least a portion of the gate electrode of the transistor is provided within the semiconductor layer.
  • a semiconductor layer including a first pixel having a photoelectric conversion element provided in the semiconductor layer; a trench provided in the semiconductor layer between adjacent ones of the pixels; the first pixel includes a transistor provided on a first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region; the first semiconductor region is provided adjacent to the transistor;
  • the transistor has a trench gate electrode.
  • a semiconductor layer A plurality of pixels including a first pixel having a photoelectric conversion element provided in the semiconductor layer; a trench provided in the semiconductor layer between adjacent ones of the pixels; the first pixel includes a transistor provided on a first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region; the first semiconductor region is provided adjacent to the transistor;
  • the transistor has a gate electrode including a plurality of first portions disposed in the semiconductor layer.
  • a separation portion provided around the plurality of first portions in the semiconductor layer; The photodetector according to any one of (34) to (35), wherein a bottom of the first portion is located above a bottom of the separation portion.

Landscapes

  • Solid State Image Pick-Up Elements (AREA)

Abstract

Un photodétecteur selon un mode de réalisation de la présente divulgation comprend : une couche semi-conductrice; une pluralité de pixels comprenant un premier pixel qui a un élément de conversion photoélectrique disposé dans la couche semi-conductrice; et des tranchées disposées, dans la couche semi-conductrice, entre des pixels adjacents parmi la pluralité de pixels. Le premier pixel comprend : un transistor disposé sur un côté de première surface de la couche semi-conductrice; une première région semi-conductrice d'un premier type de conduction, qui est disposée sur le côté première surface de la couche semi-conductrice; et un premier contact, qui est électriquement connecté à la première région semi-conductrice. La première région semi-conductrice est disposée de façon à jouxter le transistor. Le transistor comprend une électrode de grille disposée sur le côté première surface de la couche semi-conductrice de façon à prendre en sandwich une partie de la couche semi-conductrice.
PCT/JP2024/022686 2023-08-04 2024-06-21 Photodétecteur et appareil électronique Pending WO2025032987A1 (fr)

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JP2021077870A (ja) * 2019-11-08 2021-05-20 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． イメージセンサー
WO2022209681A1 (fr) * 2021-03-31 2022-10-06 ソニーセミコンダクタソリューションズ株式会社 Dispositif de détection de lumière et appareil électronique

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JP2021034435A (ja) * 2019-08-20 2021-03-01 ソニーセミコンダクタソリューションズ株式会社 固体撮像装置およびその製造方法、並びに電子機器
WO2021065587A1 (fr) * 2019-10-04 2021-04-08 パナソニックＩｐマネジメント株式会社 Dispositif d'imagerie
JP2021077870A (ja) * 2019-11-08 2021-05-20 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． イメージセンサー
WO2022209681A1 (fr) * 2021-03-31 2022-10-06 ソニーセミコンダクタソリューションズ株式会社 Dispositif de détection de lumière et appareil électronique

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