WO2025098179A1 - Polar code rate matching method and communication apparatus - Google Patents

Abstract

Embodiments of the present application provide a polar code rate matching method and a communication apparatus. The method comprises: on the basis of a first symbol quantity n, determining a second symbol quantity n', n' being greater than or equal to n, n' being an integer power of 2, and n being a positive integer; on the basis of the first symbol quantity n and the second symbol quantity n', determining a first position set, the first position set comprising first bit positions corresponding to (n'-n) symbols; and pre-freezing bits in a second sequence that are indicated by the first bit positions, to obtain a third sequence, the third sequence being a pre-frozen sequence related to polar code coding. The present method determines the first position set on the basis of the first symbol quantity and the second symbol quantity, and pre-freezes the bits indicated by the first bit positions in the first position set to obtain a third sequence. The method can ensure alignment of rate matching positions corresponding to the corresponding number of coding layers in MLC, thereby improving coding and decoding performance.

Description

Polar code rate matching method and communication device

This application claims the priority of the Chinese patent application filed with the State Intellectual Property Office of China on November 6, 2023, with application number 202311473427.9 and invention name “Polar code rate matching method and communication device”, all contents of which are incorporated by reference in this application.

Technical Field

The embodiments of the present application relate to the field of coding, and more specifically, to a method for polar code rate matching and a communication device.

Background Art

Communication systems usually use channel coding to improve the reliability of data transmission and ensure the quality of communication. Polar code is a coding method that can achieve Shannon capacity and has low coding complexity.

Polar code is a channel coding scheme that can be strictly proven to achieve Shannon channel capacity. Polar code has the characteristics of good performance and low complexity. It is currently identified by the 3rd Generation Partnership Project (3GPP) as the control channel coding scheme for the enhanced mobile broadband (eMBB) scenario (uplink/downlink) of the fifth generation 5G (5th generation, 5G) scenario.

In multi-level coding (MLC), m polar codes can be coupled through modulation, and the serial demodulation corresponding to MLC can be regarded as a stronger polarization effect than polar codes. At present, the rate matching method of polar codes in MLC is often determined according to the code rate size corresponding to each layer of coding in MLC, resulting in different rate matching methods corresponding to the number of MLC coding layers, that is, there are bit positions of rate matching corresponding to the number of coding layers that cannot be aligned, further affecting the subsequent encoding and decoding performance.

Summary of the invention

The embodiment of the present application provides a method for polar code rate matching, which relates to a polar code rate matching method in a multi-layer coding MLC scenario, and can improve coding performance.

In a first aspect, a method for polar code rate matching is provided, the method comprising: determining a second symbol number n' based on a first symbol number n, n'≥n, and n' is an integer power of 2, and n is a positive integer; determining a first position set according to the first symbol number n and the second symbol number n', the first position set including first bit positions corresponding to (n'-n) symbols; in a second sequence, pre-freezing the bits indicated by the first bit positions to obtain a third sequence, the third sequence being a pre-freezing sequence related to polar polar code encoding, wherein the second sequence is a sequence obtained by pre-freezing bits corresponding to (N-n') symbols in the first sequence according to the second symbol number n', the first sequence corresponds to the number of symbols N and the modulation order M, N≥n', and N and M are both positive integers.

It should be understood that the first symbol number n is allocated by the system according to channel resources, and the specific value of n is not limited in this application.

It should also be understood that the modulation order in the present application corresponds to the number of coding layers in MLC. For example, if the modulation order corresponding to the sequence is M, then the number of coding layers in MLC is M.

It should also be understood that the first sequence is a sequence preset by the system, and the first sequence corresponds to the number of symbols N and the modulation order M, that is, the length of the first sequence can be expressed as (N*M), wherein the specific values of N and M are not limited in this application.

It should also be understood that the second symbol number n' is determined according to the first symbol number n, and the second symbol number n' is a positive integer of an integer power of 2 determined according to the first symbol number n. For example, if the first symbol number n is 22, the second symbol number n' may be 32, and so on; if the first symbol number n is 6, the second symbol number n' may be 8, and so on.

According to the method provided by the present application, the second symbol number n' is determined by the first symbol number n, and the first position set is further determined according to the first symbol number n and the second symbol number n'. The first bit position included in the first position set is used to indicate that the (n'-n)*M bit positions in the second sequence are pre-frozen to obtain a third sequence. The second sequence is obtained by pre-freezing the bits corresponding to the N-n' symbols in the sequence preset by the system (for example, the first sequence). Among them, the third sequence is a pre-frozen sequence, which can be understood The pre-frozen bit position in the third sequence may be a bit position for subsequent rate matching, or the pre-frozen bit position corresponding to the third sequence is subsequently used to determine the final rate matching bit position. The method provided by the present application determines a first position set according to a first symbol number and a second symbol number, and the first bit position included in the first position set is used to determine the pre-frozen sequence, rather than determining the rate matching method (such as puncturing, truncation) according to the code rate size, thereby ensuring that the rate matching positions corresponding to the corresponding coding layer numbers in the MLC are aligned, thereby improving the performance of encoding and decoding.

In combination with the first aspect, in some possible implementation methods, determining the first position set based on the first symbol number n and the second symbol number n’ includes: determining the second position set based on the first symbol number n, the second symbol number n’ and the second sequence, the second position set including the bit position corresponding to the nth symbol to the bit position corresponding to the (n’-1)th symbol in the second sequence, the second position set including the second bit positions corresponding to the (n’-n)th symbols; and reversing the bits of the second bit positions corresponding to the (n’-n)th symbols to determine the first position set.

Based on the above technical solution, the first symbol number n, the second symbol number n' and the second sequence determine the second position set, and the second position set includes the bit position corresponding to the nth symbol in the second sequence to the bit position corresponding to the n'-1th symbol, where n is less than or equal to n'-1. By reversing the bits of the second bit positions corresponding to the (n'-n) symbols in the second position set, (n'-n) first bit positions are obtained, and the (n'-n) first bit positions are called the first position set. The third sequence is determined by the first bit positions included in the first position set, and the rate matching method (such as puncturing, truncation) is not determined according to the code rate size, so that the rate matching positions corresponding to the corresponding coding layers in the MLC are aligned, thereby improving the encoding and decoding performance.

In combination with the first aspect, in some possible implementation methods, determining the first position set based on the first symbol number n and the second symbol number n’ includes: determining the first position set based on the first symbol number n, the second symbol number n’ and the second sequence, the first bit position corresponding to the (n’-n) symbols in the first position set being the bit position corresponding to the nth symbol to the bit position corresponding to the (n’-1)th symbol determined after sub-block interleaving of the bit positions corresponding to the second sequence.

Based on the above technical solution, the first bit position included in the first position set is determined by sub-block interleaving according to the bit position in the second sequence, and the pre-freeze positions corresponding to each coding layer in the MLC are all determined according to the first position set, rather than according to the bit rate corresponding to each coding layer, thereby ensuring the position alignment of the rate matching of each layer in the coding layer and improving the encoding and decoding performance.

In combination with the first aspect, in some possible implementation methods, determining the first position set according to the first symbol number n and the second symbol number n' includes: determining the first position set according to the first symbol number n, the second symbol number n' and the code rate Ri, the first bit position corresponding to the (n'-n)th symbol in the first position set is the bit position corresponding to the nth symbol to the bit position corresponding to the (n'-1)th symbol determined after sub-block interleaving of the bit positions corresponding to the second sequence, or the first bit position corresponding to the (n'-n)th symbol in the first position set is the bit position corresponding to the 0th symbol to the bit position corresponding to the (n'-n-1)th symbol determined after sub-block interleaving of the bit positions corresponding to the second sequence, wherein Ri is the ratio of the number ki of information bits corresponding to the i-th modulation order in the second sequence to the first symbol number n, 0≤i≤M-1.

It should be understood that the K information bits are divided into M parts according to the modulation order M, that is, each of the coding layers M corresponding to the modulation order M can include one or more information bits among the K information bits. Alternatively, it can be said that the number of information bits included in the i-th modulation order is ki, and the code rate Ri corresponding to the i-th modulation order is further determined.

For example, the Ri is the ratio of the number of information bits ki included in the i-th modulation order to the first number of symbols n.

Among them, when Ri is greater than the first threshold, the first bit position corresponding to the (n’-n)th symbol in the first position set is the bit position corresponding to the nth symbol to the bit position corresponding to the (n’-1)th symbol determined after sub-block interleaving of the bit position corresponding to the second sequence; when Ri is less than or equal to the first threshold, the first bit position corresponding to the (n’-n)th symbol in the first position set is the bit position corresponding to the 0th symbol to the bit position corresponding to the (n’-n-1)th symbol determined after sub-block interleaving of the bit position corresponding to the second sequence.

It should be understood that the first threshold is predefined by the system or specified by the protocol. The size of the first threshold is not limited in this application.

In combination with the first aspect, in some possible implementation methods, the method also includes: according to the third sequence, allocating K information bits to non-pre-frozen bits corresponding to M modulation orders in the third sequence; encoding each of the coding layers corresponding to the modulation order M of the third sequence to obtain M n’-length codewords; modulating the M n’-length codewords to obtain n’ symbols; using the bit position corresponding to the modulation order with the highest reliability in the third sequence as a rate matching sequence; and selecting n symbols from the n’ symbols as transmission symbols according to the rate matching sequence, and sending them.

Based on the above technical solution, the bits corresponding to the modulation order with the highest reliability in the third sequence are used as the rate matching sequence; and according to The rate matching sequence selects n symbols from the n' symbols as transmission symbols for transmission. The method can first encode the non-pre-frozen bits corresponding to the M modulation orders allocated to the K information bits, and each layer corresponding to the M coding layers, and modulate the encoded codeword to obtain n' coded modulation symbols, and select n symbols as transmission symbols for transmission. Thus, coding modulation is implemented first, and rate matching is performed on the n' symbols after coding modulation to obtain n symbols as transmission symbols for transmission, thereby ensuring the coding performance.

Optionally, selecting n symbols from the n’ symbols as transmitting symbols according to the rate matching sequence includes: taking the bit position corresponding to the modulation order with the highest reliability in the first position set as the rate matching position; and selecting n symbols other than the rate matching position from the rate matching sequence as transmitting symbols.

It should be understood that the rate matching position in the rate matching sequence is a pre-freeze position, or the rate matching position is used to determine the pre-freeze position. The rate matching position and the pre-freeze position may be the same or different, and this application does not limit this. Among them, the symbol corresponding to the rate matching position is not sent.

It should also be understood that the bits corresponding to the modulation order with the highest reliability in the third sequence are used as the rate matching sequence, and the bit positions corresponding to the modulation order with the highest reliability in the first position set are used as the rate matching positions, and the symbols corresponding to the bit positions other than the rate matching positions are selected from the rate matching sequence as transmission symbols for transmission, thereby ensuring the encoding and decoding performance.

In combination with the first aspect, in some possible implementation methods, the method also includes: according to the third sequence, allocating K information bits to non-pre-frozen bits corresponding to M modulation orders in the third sequence; encoding each layer of the coding layers corresponding to the modulation order M of the third sequence to obtain M n'-length codewords; using the third sequence as a rate matching sequence to obtain M n-length transmission sequences, sending n transmission symbols, and the n transmission symbols are modulated according to the M n-length transmission sequences.

Based on the above technical solution, the third sequence is used as a rate matching sequence, and the encoded M n'-length codewords are rate matched to obtain M n-length codewords; and the M n-length codewords are encoded to obtain n transmission symbols for transmission. This method can first encode the non-pre-frozen bits corresponding to the M modulation orders allocated to the K information bits, and each layer corresponding to the M coding layers, and rate match the encoded codewords to obtain M n-length codewords from the M n'-length codewords. The M n-length codewords are modulated into n symbols as transmission symbols for transmission. Thus, encoding is achieved first, rate matching is performed on the encoded codewords, and finally modulation is performed into n symbols as transmission symbols for transmission, thereby ensuring the coding performance.

In a second aspect, a method for rate matching of a polar code is provided, characterized in that it includes: determining a second symbol number n' based on a first symbol number n, where n'≥n, and n' is an integer power of 2, and n is a positive integer; determining a first position set according to the first symbol number n and the second symbol number n', wherein the first position set includes first bit positions corresponding to (n'-n) symbols; in a second sequence, pre-freezing the bits indicated by the first bit positions to obtain a third sequence, wherein the third sequence is a pre-freezing sequence related to polar code decoding, wherein the second sequence is a sequence obtained by pre-freezing bits corresponding to (N-n') symbols in the first sequence according to the second symbol number n', and the first sequence corresponds to the number of symbols N and the modulation order M, where N≥n', and N and M are both positive integers.

According to the method provided by the present application, the second symbol number n' is determined by the first symbol number n, and the first position set is further determined according to the first symbol number n and the second symbol number n'. The first bit position included in the first position set is used to indicate that the (n'-n) bit positions in the second sequence are pre-frozen to obtain a third sequence. The second sequence is obtained by pre-freezing the bits corresponding to the N-n' symbols in a sequence preset by the system (for example, the first sequence). Among them, the third sequence is a pre-frozen sequence, which can be understood as: the pre-frozen bit position in the third sequence can be the bit position for subsequent rate matching, or the pre-frozen bit position corresponding to the third sequence is subsequently used to determine the bit position for rate matching. The method provided by the present application determines a first position set according to the first symbol number and the second symbol number, and the first bit position included in the first position set is used to determine the pre-frozen sequence, thereby improving the performance of encoding and decoding.

In conjunction with the second aspect, in some possible implementations, determining the first position set according to the first symbol number n and the second symbol number n′ includes:

Determine a second position set according to the first symbol number n, the second symbol number n' and the second sequence, the second position set including a bit position corresponding to the nth symbol to a bit position corresponding to the (n'-1)th symbol in the second sequence, and the second position set including second bit positions corresponding to the (n'-n)th symbol;

The second bit positions corresponding to the (n’-n) symbols are bit reversed to determine the first position set.

Based on the above technical solution, the first symbol number n, the second symbol number n' and the second sequence determine a second position set, and the second position set includes the bit position corresponding to the nth symbol in the second sequence to the bit position corresponding to the n'-1th symbol, where n is less than n'-1. By reversing the second bit positions corresponding to the (n'-n) symbols in the second position set, (n'-n) first bit positions are obtained, and the (n'-n) first bit positions are called the first position set. The third sequence is determined by the first bit positions included in the first position set, and the position of the rate matching corresponding to the corresponding number of coding layers in the MLC is determined to improve the performance of encoding and decoding.

In combination with the second aspect, in some possible implementation methods, determining the first position set based on the first symbol number n and the second symbol number n’ includes: determining the first position set based on the first symbol number n, the second symbol number n’ and the second sequence, the first bit position corresponding to the (n’-n) symbols in the first position set being the bit position corresponding to the nth symbol to the bit position corresponding to the (n’-1)th symbol determined after sub-block interleaving of the bit positions corresponding to the second sequence.

Based on the above technical solution, the first bit position included in the first position set is determined by sub-block interleaving according to the bit position in the second sequence, and the pre-freeze positions corresponding to each coding layer in the MLC are all determined according to the first position set, rather than according to the bit rate corresponding to each coding layer, to ensure encoding and decoding performance.

In conjunction with the second aspect, in some possible implementations, the method further includes:

The determining of a first position set according to the first symbol number n and the second symbol number n' comprises:

The first position set is determined according to the first symbol number n, the second symbol number n' and the code rate Ri, the first bit position corresponding to the (n'-n)th symbol in the first position set is the bit position corresponding to the nth symbol to the bit position corresponding to the (n'-1)th symbol determined after sub-block interleaving of the bit position corresponding to the second sequence, or the first bit position corresponding to the (n'-n)th symbol in the first position set is the bit position corresponding to the 0th symbol to the bit position corresponding to the (n'-n-1)th symbol determined after sub-block interleaving of the bit position corresponding to the second sequence,

Among them, the Ri is the ratio of the number ki of information bits corresponding to the i-th modulation order in the second sequence to the first number of symbols n, 0≤i≤M-1.

In conjunction with the second aspect, in some possible implementations, the method further includes:

receiving n transmitted symbols, serially demodulating the n transmitted symbols layer by layer according to the number of coding layers corresponding to the modulation order M, to obtain an n-length information sequence to be rate matched; performing rate de-matching on the M n-length information sequences to be rate matched according to the bit position with the highest reliability in the first position set to obtain M n'-length information sequences to be decoded; decoding the M n'-length information sequences to be decoded layer by layer according to the number of coding layers corresponding to the modulation order M, to obtain ki information bits corresponding to the i-th coding layer number in the coding layer number, K is a positive integer.

It should be understood that the second device receives n transmitted symbols, and serially demodulates the n transmitted symbols layer by layer according to the number of coding layers corresponding to the modulation order M, to obtain M n-length information sequences to be rate matched. The specific process of the second device serially demodulating the number of coding layers layer by layer can be similar to the serial demodulation in the above-mentioned MLC.

It should also be understood that, assuming that the code rate of the i-th layer in MLC is less than the first threshold, then when the second device solves the rate matching, the second device fills in "0" for the corresponding first bit position in the first position set; assuming that the code rate of the i-th layer in MLC is greater than or equal to the first threshold, then when the second device solves the rate matching, the second device fills in an infinite value, for example, positive infinity, or negative infinity, for the corresponding first bit position in the first position set.

In conjunction with the second aspect, in some possible implementations, the method further includes:

Receive n transmitted symbols, perform serial demodulation layer by layer on the n transmitted symbols according to the number of coding layers corresponding to the modulation order M, and obtain M n-length information sequences to be rate matched; perform rate demodulation on the M n-length information sequences to be rate matched according to the first bit position in the first position set corresponding to the i-th coding layer number in the number of coding layers corresponding to the modulation order M, and obtain M n'-length information sequences to be decoded; and decode the M n'-length information sequences to be decoded layer by layer according to the number of coding layers corresponding to the modulation order M, and obtain ki information bits corresponding to the i-th coding layer number. K is a positive integer.

In a third aspect, a communication device is provided, which has the function of implementing the method in the first aspect or any possible implementation of the first aspect. The function can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above functions.

In a fourth aspect, a communication device is provided, which has the function of implementing the method in the second aspect or any possible implementation of the second aspect. The function can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above functions.

In a fifth aspect, a communication device is provided, comprising a processor and a memory. Optionally, a transceiver may also be included. The memory is used to store a computer program, the processor is used to call and run the computer program stored in the memory, and control the transceiver to send and receive signals. So that the communication device executes the method in the first aspect or any possible implementation manner of the first aspect.

In a sixth aspect, a communication device is provided, comprising a processor and a memory. Optionally, a transceiver may also be included. The memory is used to store a computer program, and the processor is used to call and run the computer program stored in the memory, and control the transceiver to send and receive signals, so that the communication device executes the method in the second aspect or any possible implementation of the second aspect.

In a seventh aspect, a communication device is provided, comprising a processor and a communication interface, wherein the communication interface is used to receive data and/or information and transmit the received data and/or information to the processor, and the processor processes the data and/or information, and the communication interface is also used to output the data and/or information processed by the processor, so that the method in the first aspect, or any possible implementation of the first aspect, is executed.

In an eighth aspect, a communication device is provided, comprising a processor and a communication interface, wherein the processor processes data and/or information to be sent, and the communication interface is also used to output the data and/or information processed by the processor, so that the method in the second aspect, or any possible implementation of the second aspect, is executed.

In a ninth aspect, a computer-readable storage medium is provided, in which computer instructions are stored. When the computer instructions are executed on a computer, the method in the first aspect or the second aspect, or any possible implementation of these aspects, is executed.

In a tenth aspect, a computer program product is provided, which includes a computer program code. When the computer program code runs on a computer, the method in any possible implementation of the first aspect or the second aspect, or any of these aspects, is executed.

In an eleventh aspect, a communication system is provided, comprising the communication device as described in the fifth aspect, or the communication device as described in the sixth aspect.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the system architecture of a communication system applicable to the technical solution of the present application.

FIG. 2 is a schematic flow chart of a rate matching method 200 .

FIG. 3 is a schematic diagram of the MLC process of m-order modulation.

FIG. 4 is a simulation diagram of serial demodulation and parallel demodulation.

FIG. 5 is a schematic diagram of an MLC sequence.

FIG6 is a flow chart of a polar code rate matching method provided in the present application.

FIG. 7 is a schematic diagram of another MLC sequence.

FIG8 is a schematic diagram of another MLC sequence.

FIG. 9 is a schematic diagram of another MLC sequence.

FIG. 10 is a schematic diagram of a BLER simulation.

FIG. 11 is a schematic diagram of another BLER simulation.

FIG12 is a schematic block diagram of a communication device 1200 provided in the present application.

FIG13 is a schematic structural diagram of a communication device 1300 provided in the present application.

DETAILED DESCRIPTION

The technical solution in this application will be described below in conjunction with the accompanying drawings.

The technical solutions of the embodiments of the present application can be applied to various communication systems, including but not limited to: satellite communication systems, the 5th generation (5G) systems, long term evolution (LTE) systems (LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems), etc. The technical solutions provided in the present application can also be applied to future communication systems, such as the sixth generation mobile communication system. In addition, it can also be applied to device to device (D2D) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), and Internet of Things (IoT) communication systems or other communication systems, etc., which are not limited in this article.

The technical solution of the embodiment of the present application can also be applied to narrowband Internet of Things (NB-IoT), global system for mobile communications (GSM), enhanced data rate for GSM evolution (EDGE), wideband code division multiple access (WCDMA) and other systems. The 5G mobile communication system is based on the three major application scenarios of the next generation 5G mobile communication system, namely enhanced mobile broadband (eMBB), ultra-reliable and low-latency communications (URLLC) and massive machine type communications (eMTC).

Fig. 1 is a schematic diagram of the system architecture of a communication system applicable to the technical solution of the present application. The communication system may include one or more network devices and one or more terminal devices.

Exemplarily, the terminal device may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent or user device. The terminal device in the embodiment of the present application may be a device that provides voice and/or data connectivity to a user, and may be used to connect people, objects and machines, such as a handheld device with wireless connection function, a vehicle-mounted device, etc. The terminal device in the embodiment of the present application can be a mobile phone, a tablet computer, a laptop computer, a PDA, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a personal digital assistant, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, a mobile terminal in a vehicle, etc. Optionally, the UE can be used to act as a base station. For example, the UE can act as a scheduling entity that provides sidelink signals between UEs in V2X or D2D, etc.

In the embodiment of the present application, the device for realizing the function of the terminal can be a terminal, or a device capable of supporting the terminal to realize the function, such as a chip system or a chip, which can be installed in the terminal. In the embodiment of the present application, the chip system can be composed of a chip, or can include a chip and other discrete devices.

Exemplarily, a network device may be a device with wireless transceiver functions, and the network device may be a device that provides wireless communication function services, and is usually located on the network side, including but not limited to the next generation base station (gNodeB, gNB) in the fifth generation (5th generation, 5G) communication system, the base station in the sixth generation (6th generation, 6G) mobile communication system, the base station in the future mobile communication system or the access node in the wireless fidelity (wireless fidelity, Wi-Fi) system, the evolved node B (evolved node B, eNB) in the long term evolution (long term evolution, LTE) system, and the wireless network controller. The network device may include a radio network controller (RNC), a node B (NB), a base station controller (BSC), a home base station (e.g., home evolved NodeB, or home Node B, HNB), a base band unit (BBU), a transmission reception point (TRP), a transmitting point (TP), a base transceiver station (BTS), etc. In a network structure, the network device may include a centralized unit (CU) node, or a distributed unit (DU) node, or a RAN device including a CU node and a DU node, or a RAN device including a control plane CU node and a user plane CU node, and a DU node, or the network device may also be a wireless controller, a relay station, a vehicle-mounted device, and a wearable device in a cloud radio access network (CRAN) scenario. In addition, the base station can be a macro base station, a micro base station, a relay node, a donor node, or a combination thereof. The base station can also refer to a communication module, a modem, or a chip used to be set in the aforementioned device or apparatus. The base station can also be a mobile switching center and a device that performs the base station function in D2D, V2X, and M2M communications, a network-side device in a 6G network, and a device that performs the base station function in a future communication system. The base station can support networks with the same or different access technologies without limitation.

In the embodiment of the present application, the device for implementing the function of the network device can be a network device, or a device that can support the network device to implement the function, such as a chip system or a chip, which can be installed in the network device. In the embodiment of the present application, the chip system can be composed of a chip, or it can include a chip and other discrete devices.

It should be understood that the rate matching method provided in the present application can be considered as a channel coding scheme, which can be used in a dedicated network device or a general device, can be applied to various network devices (e.g., base station devices) as described above, and can also be applied to various terminal devices as described above. Specifically, the channel coding scheme is mainly implemented by a channel coding unit in these devices.

The method provided in the embodiments of the present application can also be implemented by application specific integrated circuit (ASIC), field programmable gate array (FPGA), etc., or by software (for example, program code in a memory), without limitation.

Next, in order to facilitate understanding of the embodiments provided in this application, the terms involved in this application are briefly introduced below:

1. Polarization code

Polar code, also known as Polar code, is a new coding method based on channel polarization. It has a deterministic construction method and is the only known channel coding method that has been strictly proven to "reach" channel capacity. From the perspective of algebraic coding and probabilistic coding, polar code has the characteristics of both.

The theoretical basis of Polar code is channel polarization. Channel polarization includes channel combination and channel decomposition. When the number of combined channels is infinite, polarization will occur: one part of the channel will tend to be a noiseless channel, and the other part will tend to be a full-noise channel. This phenomenon is channel polarization linearity. The transmission rate of the noiseless channel will reach the channel capacity, while the transmission rate of the full-noise channel will tend to zero. The coding strategy of Polar code applies the characteristics of this phenomenon, using the noiseless channel to transmit useful information for users, and the full-noise channel to transmit agreed information or no information.

After the channel polarization is completed, part of the channel whose capacity approaches 1 can be used to carry information bits, while the remaining channels can be used to carry frozen bits that are consistent at both the transmitting and receiving ends, which is the polarization coding method.

Among them, Polar code is a linear block code, its encoding matrix (also called generator matrix) is GN, and the encoding process can be expressed by the following formula:

in, is a binary row vector (i.e., information bit sequence) with a length of N, where N=2n, n is a positive integer. GN is an N×N matrix, Defined as the Kronecker product of log2N matrices F2, The addition and multiplication operations involved in the above formulas are all addition and multiplication operations on the binary Galois Field.

The codes generated by this method will produce polarization through the successive cancellation (SC) decoding method. That is, some bits in u will be decoded correctly with high probability through an equivalent high-reliability channel, and the remaining bits will be decoded correctly with low probability through an equivalent low-reliability channel. Therefore, people can use the high-reliability channel for information transmission, and set the bits corresponding to the low-reliability channel to zero (that is, freeze), not use them for data transmission, or transmit data known to both parties.

At the same time, the algorithms for serial cancellation decoding currently include (successive cancellation list, SCL) decoding and (CRC-aided successive cancellation list, CA-SCL) decoding, etc. Among them, SC decoding is the worst in terms of decoding performance, SCL decoding is much better than SC decoding, and CA-SCL decoding after CRC verification can make the performance of polar code better than LDPC code and Turbo code.

Figure 2 is a flow chart of a communication link using Polar code channel coding. The transmitter uses Polar code to perform channel coding on the source from the media access control (MAC), and the receiver sends the demodulated log likelihood ratio (LLR) soft information to the Polar decoder, which then recovers the source information and uploads it to the MAC. The specific Polar code encoding process is shown in Figure 2. In order to avoid redundancy, it will not be repeated here.

When wireless technology is used for communication, the source of the transmitter is generally sent on the channel after undergoing source coding, channel coding, rate matching and modulation. After receiving the signal, the receiver obtains the destination after demodulation, rate matching, channel decoding and source decoding.

Channel coding and decoding is one of the core technologies in the field of wireless communications. The improvement of its performance will directly improve network coverage and user transmission rate. At present, polar codes are a channel coding technology that can be theoretically proven to reach the Shannon limit and has practical linear complexity coding and decoding capabilities.

2. Multi-level coding (MLC)

MLC technology is a modulation technology that combines coding and modulation. MLC neither increases the signal bandwidth nor reduces the actual data transmission rate, while improving the reliability of data transmission. Therefore, MLC is also called "high-efficiency bandwidth coding".

According to Shannon's channel capacity theorem, when the code rate of each component code in MLC is equal to the equivalent channel capacity of each channel, MLC technology will obtain better bit error rate and throughput performance. Therefore, the design focus of MLC technology lies in the appropriate selection of component code rate. The code rate of traditional linear block codes is relatively fixed. Generally, there are only a limited number of code rates to choose from, which makes it difficult to match the code rate of block codes with the equivalent channel capacity under different channel conditions. Unlike linear block codes, rateless codes can theoretically generate any number of groups of coded symbols based on the same group of information for transmission, thereby achieving continuous adjustment of the code rate. Obviously, compared with linear block codes, rateless codes are more likely to obtain a code rate close to the channel capacity, thereby obtaining a larger throughput and a lower bit error rate.

It should be understood that MLC divides a string of modulation symbols into m layers according to the different capacities of modulated bits in the symbols, and each layer is independently encoded.

FIG3 is a schematic diagram of the MLC process of m-order modulation. The encoding in FIG3 is introduced by taking polar code as an example. For example, for an m-order modulation, the information bit stream z to be transmitted is first converted from serial to parallel and divided into m bit streams u ₁ , u ₂ , u ₃ ... _um . Each bit stream corresponds to a bit channel under high-order modulation, and polar encoding is performed separately for the bit channel, that is, the codeword x ₁ output by the m-th encoder constitutes the m-th bit in the high-order modulation symbol. The N modulation symbols generated by the modulator (Mod) are sent to the channel for transmission. The demodulator (Dem) uses the channel receiving sequence y to demodulate the soft value v ₁ required by the first polar decoder, and then the polar decoder uses the soft value sequence v ₁ corresponding to the first stream to decode u ₁ . In order to demodulate the soft value v ₂ corresponding to the second stream, the polar code codeword x ₁ corresponding to u ₁ needs to be input into the demodulator. The demodulator uses y and x ₁ to demodulate the soft value sequence v ₂ corresponding to the second stream and inputs it into the second polar code decoder. The second polar code decoder uses the soft value sequence to decode u _2. Then the demodulator uses the codewords x ₂ and x ₁ corresponding to u ₂ and u ₁ , as well as the channel received sequence y, to demodulate the soft value sequence v ₃ corresponding to the third stream. Similarly, to demodulate the mth stream, the channel received sequence y and the codewords x ₁ to x _m of the previous m-1 polar codes need to be used.

It can be seen that MLC uses serial demodulation, and the MLC requires m encoders and m decoders.

Demodulation refers to the process of converting a modulation symbol (eg, S ₁ , S ₂ , S ₃ ... S _m ) into its corresponding bit sequence (eg, v ₁ , v ₂ , v ₃ ... v _m ). The demodulation methods can be divided into serial demodulation and parallel demodulation.

The following uses a 4-PAM symbol as an example to illustrate the serial demodulation and parallel demodulation methods respectively. Assume that a 4-PAM symbol s corresponds to two bits (v1, v2), and the symbol received by the decoder after s passes through the AWGN channel is y.

(1) Serial demodulation

In order to obtain the value of v1, the probability P( _v1 =0|y) of v1=0 and the probability P( _v1 =1|y) of v1=1 are deduced according to y, and the value of v1 is determined according to the following formula (2):

in

akin,

According to the 4-PAM example given in (1) of FIG. 2 above, when calculating the probabilities of P(v ₁ =0|y) and P(v ₁ =1|y), S ₀₀ =-3A, S ₁₀ =-A, S ₁₁ =+A, S ₀₁ =+3A. In order to ensure that the average transmission power E _s =1, that is, 1/4*(|S ₀₀ | ² +|S ₁₀ | ² +|S ₁₁ | ² +|S ₀₁ | ² )=1, we have Then use the above formula (2) to obtain the value of v ₁ .

In order to obtain the value of v ₂ , serial demodulation needs to calculate the probability P(v ₂ =0|y, v ₁ ) that v ₂ =0 and the probability P(v ₂ =1|y, v ₁ ) that v ₂ =1 under the condition of a given value of v ₁ , and then calculate the log-likelihood ratio of the above two probabilities, and then obtain the value of v ₂ according to formula (3):

If v ₁ = 0,

but

If v ₁ = 1:

but

Thus, the probabilities of P(v ₂ =0|y, v ₁ ) and P(v ₂ =1|y, v ₁ ) can be calculated, and v ₂ can be serially demodulated according to the above formula (3).

(2) Parallel Demodulation

The process of calculating v ₁ is the same as the process of serial demodulation in ( ₁ ) above. Please refer to the above introduction for details.

In the process of calculating v ₂ , the parallel demodulation does not need to use the value of v ₁ , but takes the average of all possible values of v ₁ and determines the value of v ₂ 0 according to the following formula (4):

in,

akin,

It can be seen that serial demodulation needs to first estimate the value of v ₁ based on the received symbol y, and then use the estimated value of v ₁ and y to further estimate the value of v _2. The only difference between parallel demodulation and serial demodulation is that parallel demodulation does not need to use the estimated value of v ₁ when calculating v ₂ , so v ₁ and v ₂ can be obtained at the same time and can be implemented in parallel.

It should be understood that both serial demodulation and parallel demodulation can be regarded as a process of converting a high-order modulation channel containing ^2m symbols into an m-bit channel. For example, taking 4-PAM as an example, the channel capacity of the modulation channel is I(Y; _V1 , _V2 ). Serial demodulation decomposes the modulation channel into two bit channels, of which the capacity of the first bit channel is I(Y; V ₁ ) and the capacity of the second bit channel is I(Y; V ₂ |V ₁ ). It can be proved that I(Y; V ₁ ,V ₂ )＝I(Y; V ₁ )+I(Y; V ₂ |V ₁ ), that is, serial demodulation will not cause capacity loss: as shown by the solid lines in Figure 4 , the first solid line from bottom to top is the bit channel capacity I(Y; V ₁ ) of V ₁ , the second solid line is the bit channel capacity I(Y; V ₂ |V ₁ ) of V ₂ , and the third solid line from bottom to top is the modulation channel capacity I(Y; V ₁ ,V ₂ ) under serial demodulation. Parallel demodulation also decomposes the modulation channel into two bit channels, where the capacity of the first bit channel is I(Y; V ₁ ), but the capacity of the second bit channel is I(Y; V ₂ ). Since I(Y; V ₁ , V ₂ )>=I(Y; V ₁ )+I(Y; V ₂ ), parallel demodulation will produce a certain capacity loss: as shown by the dotted lines in Figure 4 , the first dotted line from bottom to top is the bit channel capacity I(Y; V ₁ ) of V ₁ , the second dotted line is the bit channel capacity I(Y; V ₂ ) of V ₂ , and the third dotted line is the modulation channel capacity I(Y; V ₁ )+I(Y; V ₂ ) under parallel demodulation. It can be seen that parallel demodulation has a certain capacity loss compared to serial demodulation, but since parallel demodulation is simple to implement and can be parallelized, it is generally used at present.

Assume that each layer in MLC uses polar code encoding, that is, the polar code in MLC can use the double sequence construction method to determine the encoding sequence. Ordinary polar code construction generally uses a single sequence construction method. For example, there is a sequence Q of length N, and its sequence index (index) represents the reliability of the bit at each position in the polar code mother code. Assume that 0 represents the bit at that position. The reliability is the lowest, and N-1 is the highest reliability of the bit at this position. The specific value of Q[i] represents: the specific position in the coding sequence corresponding to the reliability of the i-th bit from low to high bit reliability.

For example, N=16, Q[0]=0, which means Q[0] is the 0th reliability position in the N-length sequence to be encoded, that is, the least reliable position, and Q[0]=0 is the 0th position in the N-length sequence to be encoded. Q[12]=11, which means Q[12] is the 12th reliability position in the N-length sequence to be encoded, and Q[12]=11 is the 11th position in the N-length sequence to be encoded.

To obtain K information bits of a polar code of length N1 from a sequence of length N (N1<=N), first determine the frozen position in the polar code, which includes the position where Q[i]>=N. The frozen position can be a punctured and shortened position, as well as a position where the punctured Polar code needs to be pre-frozen according to the NR protocol. Then select K positions from N-1 to 0 in the sequence that are not frozen to carry information bits.

In MLC, m polar codes can be coupled through modulation, and the serial demodulation corresponding to MLC can be regarded as a stronger polarization effect than polar codes. At present, the rate matching method of polar codes in MLC is often determined according to the code rate corresponding to each layer of coding in MLC, resulting in different rate matching methods corresponding to the number of MLC coding layers, that is, the bit positions of the rate matching corresponding to the number of coding layers cannot be aligned, further affecting the subsequent encoding and decoding performance.

FIG5 is a schematic diagram of an MLC sequence. In FIG5, taking N=16 and modulation level=4 as an example, it is a 64-length sequence. In the sequence, the slash area indicates the position of the lowest energy bit from the MLC, the horizontal area indicates the position of the second lowest energy bit from the MLC, the gray dot area is from the position of the second highest energy bit from the MLC, and the blank area is from the position of the highest energy bit from the MLC. It is preset that when the modulation order of QAM is 16, two levels are used, and the bit position is selected from the area with the lowest reliability and the second lowest reliability in FIG5; it is preset that when the modulation order of QAM is 64, three levels are used, and the corresponding bit position is selected from the area with the lowest reliability, the second lowest reliability, and the second highest reliability in FIG5; it is preset that when the modulation order of QAM is 256, four levels are used, and all areas in FIG5 are optional. If the number of I/Q independent symbols is insufficient, each area must be selected. For example, for QAM16, N=8, the position numbers are 0-7, 16-23 to be compared with the value of the Q sequence.

Based on the MLC sequence shown in Figure 5, assuming that the number of symbols to be transmitted is not an integer power of 2, when rate matching is required, the same number of bits are generally rate matched (punctured or truncated) for each coding layer in the MLC. Further, the natural order + puncturing method is uniformly used for rate matching for each coding layer in the MLC, or the natural order + truncation method is uniformly used for rate matching. Finally, the Gaussian approximation is used for construction.

For example, if the rate matching is performed by natural order + puncturing, assuming that X symbols need to be punctured, the symbols at the 0th position to the X-1th position are punctured; if the rate matching is performed by natural order + truncation, assuming that X symbols need to be punctured, the symbols at the N-Xth position to the N-1th position are truncated.

When the above method is often used to rate match MLC, the rate matching method corresponding to the number of coding layers in MLC is related to the bit rate of each layer. In MLC, the bit rates corresponding to each coding layer may be different, resulting in different rate matching methods used by each coding layer, resulting in different bit positions of rate matching of each coding layer, that is, the positions of rate matching of each coding layer in MLC cannot be aligned, resulting in reduced encoding and decoding performance.

Based on the above problems, the present application provides a method for polar code rate matching in an MLC scenario, which can improve encoding and decoding performance.

FIG6 is a schematic diagram of a process of polar code rate matching method provided in an embodiment of the present application. The method may include the following steps:

601. The first device determines a second symbol number n' based on the first symbol number n.

Herein, n' is an integer power of 2, and n' is greater than or equal to n, and n is a positive integer.

It should be understood that the first symbol number n is allocated by the system according to channel resources, and the specific value of n is not limited in this application.

It should also be understood that the modulation order in the present application corresponds to the number of coding layers in MLC. For example, if the modulation order corresponding to the sequence is M, then the number of coding layers in MLC is M.

It should also be understood that the first sequence is a sequence preset by the system, and the first sequence corresponds to the number of symbols N and the modulation order M, that is, the length of the first sequence can be expressed as (N*M), wherein the specific values of N and M are not limited in this application.

It should also be understood that the first device determines the second symbol number n' based on the first symbol number n, and the second symbol number n' is a positive integer of an integer power of 2 determined according to the first symbol number n. For example, if the first symbol number n is 22, the second symbol number n' may be 32, 64, etc.; if the first symbol number n is 6, the second symbol number n' may be 8, 16, 32, etc.

602. The first device determines a first position set according to the first symbol number n and the second symbol number n'.

The first position set includes first bit positions corresponding to (n'-n) symbols.

In one possible implementation, the first device determines a second position set based on a first symbol number n, a second symbol number n’, and a second sequence, the second position set including a bit position corresponding to the nth symbol to a bit position corresponding to the (n’-1)th symbol in the second sequence, and the second position set includes second bit positions corresponding to the (n’-n) symbols; the first device performs bit index reverse (BIV) on the second bit positions corresponding to the (n’-n) symbols to determine the first position set.

As an example, assume that the first symbol number n=22, the number of symbols corresponding to the first sequence N=64, and the modulation order M=4. First, the first device determines the second symbol number n'=32 according to the first symbol number n. The first device pre-freezes the bits corresponding to (64-32) symbols in the first sequence according to n=22 and n'=32 to obtain a second sequence, and the pre-frozen bit positions cannot be used to carry information bits. The first device determines a first position set according to the first symbol number n, the second symbol number n' and the second sequence, and the first position set includes the bit position corresponding to the 22nd symbol to the bit position corresponding to the 31st symbol. Since the second symbol number is n'=32, the bit width of the index corresponding to the symbol is 5 bits. The bit corresponding to the 22nd symbol to the bit position corresponding to the 31st symbol, each with a bit width of 5 bits, is expanded in binary, such as: (10110) (10111) (11000) (11001) (11010) (11011) (11100) (11101) (11110) (11111). The first device performs bit reverse order on the bit positions corresponding to the above 10 symbols (or referred to as the second position set) to obtain a first position set. The first position set is: (01101), (11101), (00011), (10011), (01011), (11011), (00111), (10111), (01111), (11111). The first device pre-freezes the first bit position included in the first position set for indicating the bit position, that is, the first device pre-freezes the bit corresponding to the 13th symbol, the bit corresponding to the 29th symbol, the bit corresponding to the 3rd symbol, the bit corresponding to the 19th symbol, the bit corresponding to the 11th symbol, the bit corresponding to the 27th symbol, the bit corresponding to the 7th symbol, the bit corresponding to the 23rd symbol, the bit corresponding to the 15th symbol, and the bit corresponding to the 31st symbol, and the bit positions corresponding to the 10 symbols. The first position set is shown in FIG7, and the gray part is the position of the pre-frozen bit corresponding to the symbol in the first position set.

In another possible implementation, the first device determines a first position set based on a first symbol number n, a second symbol number n’, and a second sequence, wherein a first bit position corresponding to the (n’-n)th symbol in the first position set is the bit position corresponding to the nth symbol to the bit position corresponding to the (n’-1)th symbol determined after sub-block interleaving of the bit positions corresponding to the second sequence.

As an example, assume that the first symbol number n=22, the number of symbols corresponding to the first sequence N=64, and the modulation order M=4. First, the first device determines the second symbol number n'=32 according to the first symbol number n. The first device pre-freezes the bits corresponding to (64-32) symbols in the first sequence according to n=22 and n'=32 to obtain a second sequence, and the pre-frozen bit positions cannot be used to carry information bits. Assume that the second sequence is (0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31), and the first device performs sub-block interleaving on the bit positions corresponding to the second sequence. For example, after the first device performs sub-block interleaving on the bit positions corresponding to the second sequence, the first device obtains: I = (0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28, 27, 29, 30, 31). The first device determines the first position set according to the first symbol number n, the second symbol number n' and the second sequence. The first position set includes the bit position corresponding to the 22nd symbol to the bit position corresponding to the 31st symbol determined after the sub-block interleaving of the second sequence, that is, the first position set includes I ₂₂ =15, I ₂₃ =23, I ₂₄ =24…I ₃₀ =30, I ₃₁ =31 in I, and the first position set includes the bit positions corresponding to the 10 symbols, and the bit positions corresponding to the 10 symbols respectively indicate the bit position corresponding to the 15th symbol in the second sequence, the bit position corresponding to the 23rd symbol,…, the bit position corresponding to the 31st symbol. The first position set is shown in FIG8, and the gray part is the position of the pre-frozen bit corresponding to the symbol in the first position set.

In another possible implementation, the first device determines a first position set based on the first symbol number n, the second symbol number n’ and the code rate Ri, and the first bit position corresponding to the (n’-n)th symbol in the first position set is the bit position corresponding to the nth symbol to the bit position corresponding to the (n’-1)th symbol determined after sub-block interleaving of the bit positions corresponding to the second sequence, or the first bit position corresponding to the (n’-n)th symbol in the first position set is the bit position corresponding to the 0th symbol to the bit position corresponding to the (n’-n-1)th symbol determined after sub-block interleaving of the bit positions corresponding to the second sequence.

Here, Ri is the ratio of the number ki of information bits corresponding to the i-th modulation order in the second sequence to the first number of symbols n, 0≤i≤M-1.

It should be understood that the code rate Ri is determined according to the number ki of information bits included in the i-th modulation order among the M modulation orders and the number of bits of the first symbol number. Wherein, the number of information bits included in the M modulation orders is K.

It should also be understood that the K information bits are preset by the system, and the specific value of K is not limited in this application.

It should also be understood that the modulation order M corresponds to the number of coding layers in MLC, that is, the modulation order is M, that is, the number of coding layers in MLC level = M. The code rate Ri is the ratio between the number of information bits ki corresponding to the number of coding layers and the first symbol number n.

Optionally, the (n'-n) symbols included in the first position set correspond to the first bit position, which may be the bit position corresponding to the nth symbol determined after sub-block interleaving based on the rate matching method to determine that the first bit position is the bit position corresponding to the second sequence. The bit position is set to the bit position corresponding to the (n'-1)th symbol, or the first bit position is the bit position corresponding to the 0th symbol to the bit position corresponding to the (n'-n-1)th symbol determined after sub-block interleaving of the bit position corresponding to the second sequence.

The rate matching method is different, and the bit position of the rate matching is also different. For example, the first bit position may include the bit position corresponding to the 0th symbol to the bit position corresponding to the (n'-n-1)th symbol determined after the bit position corresponding to the second sequence is interleaved by sub-blocks; or the bit position corresponding to the (n'-1)th symbol to the bit position corresponding to the (n'-n)th symbol determined after the bit position corresponding to the second sequence is interleaved by sub-blocks.

For example, the Ri corresponding to the i-th modulation order can be used to determine the rate matching method corresponding to the i-th modulation order. For example, when Ri is greater than the first threshold, the rate matching method corresponding to the i-th modulation order is determined to be truncation; when Ri is less than or equal to the first threshold, the rate matching method corresponding to the i-th modulation order is determined to be puncturing. When the rate matching method is truncation, the bit position corresponding to the 0th symbol to the bit position corresponding to the (n’-n-1)th symbol after sub-block interleaving of the bit position corresponding to the second sequence is used as the first bit position in the first position set; when the rate matching method is puncturing, the bit position corresponding to the (n’-1)th symbol to the bit position corresponding to the (n’-n)th symbol after sub-block interleaving of the bit position corresponding to the second sequence is used as the first bit position in the first position set.

As an example, assume that the first symbol number n=22, the number of symbols corresponding to the first sequence N=64, and the modulation order M=4. First, the first device determines the second symbol number n'=32 according to the first symbol number n. According to n'=32, the first device pre-freezes the bits corresponding to (64-32) symbols in the first sequence to obtain the second sequence. According to n'=32, the sub-block size is determined to be n'/32=1bit. That is, in NR, the code block of the polar code is divided into 32 blocks. Assume that the second sequence is (0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31), and the first device performs sub-block interleaving on the bit positions corresponding to the second sequence. For example, after the first device performs sub-block interleaving on the bit positions corresponding to the second sequence, the result is: I = (0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28, 27, 29, 30, 31). The first device determines the rate matching mode corresponding to the i-th modulation order according to the code rate Ri corresponding to the i-th modulation order. Assuming that Ri is less than or equal to the first threshold, the puncturing method is selected for rate matching, that is, the bit positions corresponding to the symbols I ₀ =0, I ₁ =1, I ₂ =2, I ₃ =4…I ₈ =16, I ₉ =9 are used as pre-frozen bit positions (first bit positions), wherein the bit positions corresponding to the 10 symbols of the i-th modulation order are the first bit positions; assuming that Ri is greater than the first threshold, the truncation method is selected for rate matching, and the bit positions corresponding to the symbols I ₂₂ =15, I ₂₃ =23, I ₂₄ =24…I ₃₀ =30, I ₃₁ =31 are selected as pre-frozen bit positions (first bit positions), wherein the bit positions corresponding to the 10 symbols of the i-th modulation order are the first bit positions. As shown in FIG9 , assuming that the code rate R0 corresponding to level 0 is less than or equal to the first threshold, and the code rates R1, R2 and R3 corresponding to level 1, level 2 and level 3 are all greater than or equal to the first threshold, the gray part is the position of the pre-freeze bit corresponding to the symbol in the first position set.

603. The first device pre-freezes the bit indicated by the first bit position in the second sequence to obtain a third sequence.

The third sequence is a pre-frozen sequence related to polar code encoding.

It should be understood that the first device pre-freezes bits corresponding to (N-n') symbols in the first sequence according to the second symbol number n' to obtain the second sequence.

The first sequence is a sequence preset by the system, and the first sequence corresponds to the number of symbols N and the modulation order M, that is, the length of the first sequence can be expressed as (N*M). The specific values of N and M are not limited in this application.

For example, the number of symbols corresponding to the first sequence preset by the system is N=64, the modulation order is M=4, and the length of the first sequence is 256. Assuming that the first symbol number n=22, the first device determines the second symbol number n'=32 based on the first symbol number n=22. The first device pre-freezes the bits corresponding to (64-32) symbols in the first sequence according to the second symbol number n'=32 to obtain a second sequence. The second sequence is a sequence obtained after pre-freezing the bit positions corresponding to 32 symbols in the first sequence.

It should also be understood that the first device pre-freezes the bit position corresponding to the corresponding symbol in the second sequence according to the first bit position included in the first position set in the second sequence to obtain the third sequence. The third sequence is a pre-freeze sequence related to polar code encoding. That is, the third sequence can be used as a rate matching sequence in the process of encoding and modulating the information bit by the first device.

The method shown in FIG6 may further include the following steps:

The first device allocates K information bits to non-prefrozen bits corresponding to M modulation orders in the third sequence according to the third sequence. The first device encodes each of the coding layers corresponding to the modulation order M of the third sequence to obtain M n'-length codewords; the first device modulates the M n'-length codewords to obtain n' symbols; the first device uses the bits corresponding to the modulation order with the highest reliability in the third sequence as a rate matching sequence; the first device selects n symbols from the n' symbols as transmission symbols according to the rate matching sequence and transmits them.

It should be understood that the first device allocates the K information bits to the non-pre-frozen bits corresponding to the M modulation orders in the third sequence. The M modulation orders correspond to M coding layers, and the first device encodes each of the M coding layers to obtain M n'-length codewords. The first device then modulates the M n'-length codewords to obtain n' symbols. The first device selects bits corresponding to the modulation order with the highest reliability from the third sequence as a rate matching sequence. Based on the rate matching sequence, the first device selects n symbols from the n' symbols as transmission symbols for transmission.

As an example, in combination with the example in FIG. 7 above, the first device allocates K information bits to level0, level1, level2 and level3, and the first device encodes level0, level1, level2 and level3 to obtain 4 codewords of length 32. The first device modulates the 4 32-length codewords to obtain 32 symbols. For example, 2 bits are selected from the 4 32-length codewords to map to the I path and Q path of the 0th QAM256 symbol, 2 bits are selected from the 4 32-length codewords to map to the I path and Q path of the 1st QAM256 symbol, ..., 2 bits are selected from the 4 32-length codewords to map to the I path and Q path of the 31st QAM256 symbol. The first device selects 22 symbols from the 32 symbols as transmission symbols for transmission. For example, according to the rate matching method in FIG. 7 , it is determined that symbols at positions 0, 1, 2, 4, 5, 6, 8, 9, 10, 12, 14, 16, 17, 18, 20, 21, 22, 24, 25, 26, 28, and 30 are sent as transmission symbols.

It should be understood that 2 bits are selected from 4 32-bit long code words to map the I path and Q path of the QAM256 symbol, wherein the 2 bits can be any 2 bits in the 4 32-bit long code words, such as the 0th bit and the 2nd bit, the 0th bit and the 1st bit, or other bits, which are not limited in this application. Among them, the 2 bits used to map the I path and Q path of the 0th QAM256 symbol, the 2 bits used to map the I path and Q path of the 1st QAM256 symbol, ..., the 2 bits used to map the I path and Q path of the 31st QAM256 symbol are all in different positions in the 4 32-bit long code words.

As another example, in combination with the example in FIG. 8 above, the first device allocates K information bits to level0, level1, level2, and level3, and the first device encodes level0, level1, level2, and level3 to obtain four codewords of length 32. The first device modulates the four 32-length codewords to obtain 32 symbols. For example, 2 bits are selected from the four 32-length codewords to map to the I path and Q path in the 0th QAM256 symbol, 2 bits are selected from the four 32-length codewords to map to the I path and Q path in the 1st QAM256 symbol, ..., 2 bits are selected from the four 32-length codewords to map to the I path and Q path in the 31st QAM256 symbol. The first device selects 22 symbols from the 32 symbols as transmission symbols for transmission. For example, according to the rate matching method in FIG8 , it is determined that the symbols at positions 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16, 17, 18, 19, 20, 21, and 22 are sent as transmission symbols.

As another example, in combination with the example in FIG. 9 above, the first device allocates K information bits to level0, level1, level2 and level3, and the first device encodes level0, level1, level2 and level3 to obtain 4 codewords of length 32. The first device modulates the 4 32-length codewords to obtain 32 symbols. For example, 2 bits are selected from the 4 32-length codewords to map to the I path and Q path of the 0th QAM256 symbol, 2 bits are selected from the 4 32-length codewords to map to the I path and Q path of the 1st QAM256 symbol, ..., 2 bits are selected from the 4 32-length codewords to map to the I path and Q path of the 31st QAM256 symbol. The first device selects 22 symbols from the 32 symbols as transmission symbols for transmission. For example, according to the rate matching method in FIG. 9 , it is assumed that the reliabilities corresponding to level0, level1, level2 and level3 are respectively: level0<level1<level2<level3 from low to high, wherein the numbers of information bits carried on level0, level1, level2 and level3 are k0, k1, k2 and k3 respectively, wherein k0<k1<k2<k3, and the code rate corresponding to level3 is the largest, that is, the rate matching method corresponding to level3 is truncation. According to the rate matching mode corresponding to the coding layer level 3 with the highest reliability, 22 symbols are selected from the 32 symbols, that is, the bit positions corresponding to the modulation order with the highest reliability in the first position set are selected as the rate matching positions, that is, the bit positions corresponding to the symbols I ₂₂ =15, I ₂₃ =23, I ₂₄ =24 ... I ₃₀ =30, I ₃₁ =31 are selected as the rate matching positions, and the symbols at the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th, 7th, 8th, 9th, 10th, 11th, 12th, 13th, 14th, 16th, 17th, 18th, 19th, 20th, 21st, 22nd bits are sent as transmission symbols.

It can be understood that in the method provided in the present application, the first device can first perform coding modulation according to K information bits, M modulation orders and the second symbol number n', and obtain n' symbols. The first device then selects the bits corresponding to the modulation order with the highest reliability from the third sequence as the rate matching sequence, and selects n symbols from the n' symbols as transmission symbols for transmission. That is, the method provided in the present application can first perform coding modulation, and then perform rate matching to obtain n transmission symbols for transmission.

The method shown in FIG6 may further include the following steps:

The first device allocates K information bits to non-prefrozen bits corresponding to M modulation orders in the third sequence according to the third sequence; the first device encodes each of the coding layers corresponding to the modulation order M of the third sequence to obtain M n'-length codewords; the first device uses the third sequence as a rate matching sequence to obtain M n-length transmission sequences. The first device sends n transmission symbols, and the n transmission symbols are modulated according to the M n-length transmission sequences.

It should be understood that the first device allocates K information bits to non-prefrozen bits corresponding to M modulation orders in the third sequence. The M modulation orders correspond to M coding layers, and the first device encodes each of the M coding layers to obtain M n'-length codewords. The first device uses the third sequence as a rate matching sequence for M n-length transmission sequences. Among them, the M modulation orders correspond to The rate matching method may refer to the introduction of step 602 in Fig. 6. The first device modulates the M n-length transmission sequences to obtain n transmission symbols, and transmits them.

As an example, in combination with the example in FIG. 9 above, the first device allocates K information bits to level0, level1, level2 and level3, and encodes level0, level1, level2 and level3 to obtain 4 codewords with a length of 32. According to the example in FIG. 9 , the codewords at positions 0, 1, 2, 3, 4, 5, 6, 7, 8, and 16 in the coding result corresponding to level 0 are deleted to obtain the 0th rate matching sequence; the codewords at positions 15, 23, 24, 25, 26, 27, 28, 29, 30, and 31 in the coding result corresponding to level 1 are deleted to obtain the 1st rate matching sequence; the codewords at positions 15, 23, 24, 25, 26, 27, 28, 29, 30, and 31 in the coding result corresponding to level 2 are deleted to obtain the 2nd rate matching sequence; the codewords at positions 15, 23, 24, 25, 26, 27, 28, 29, 30, and 31 in the coding result corresponding to level 3 are deleted to obtain the 3rd rate matching sequence. The first device maps the 0th codeword in the 0th rate matching sequence, the 1st rate matching sequence, the 2nd rate matching sequence, and the 3rd rate matching sequence to the 1st QAM256 symbol, the 2nd codeword to the 2nd QAM256 symbol, ..., the 21st codeword to the 21st QAM256 symbol. The first device sends the 21 symbols as transmission symbols.

It can be understood that in the method provided in the present application, the first device can first encode according to K information bits, M modulation orders and the second symbol number n' to obtain M n'-length codewords. The first device then performs rate matching on the M n' codewords to obtain M n-length sequences. Further, the first device modulates the M n-length sequences to obtain n transmission symbols, and transmits them. That is, the method provided in the present application can first perform encoding, then rate matching, and finally modulate the sequence obtained after rate matching to obtain n transmission symbols for transmission.

Based on the above first device, n transmission symbols are determined, and the n transmission symbols are sent as transmission symbols to the second device. Accordingly, the second device receives the n transmission symbols from the first device, and decodes and demodulates the n transmission symbols to obtain K information bits, as follows:

The second device receives n transmitted symbols, and serially demodulates the n transmitted symbols layer by layer according to the number of coding layers corresponding to the modulation order M, to obtain M n-length rate matching information sequences to be decoded. The second device performs rate matching on the M n-length rate matching information sequences to be decoded according to the first bit position in the first position set to obtain M n'-length information sequences to be decoded. The second device decodes the M n'-length information sequences to be decoded layer by layer according to the number of coding layers corresponding to the modulation order M, thereby obtaining ki information bits corresponding to each coding layer number, K is a positive integer. The K information bits are information bits obtained by the second device according to decoding and demodulation of the n transmitted symbols.

It should be understood that the second device receives n transmitted symbols, and serially demodulates the n transmitted symbols layer by layer according to the number of coding layers corresponding to the modulation order M, to obtain M n-length rate matching information sequences to be decoded. Among them, the second device obtains the coding codeword corresponding to the i-th layer according to the coding process for the rate matching information sequence to be decoded corresponding to the i-th layer in the number of coding layers. The second device brings the coded codeword obtained by the i-th layer into the demodulation process of the i+1-th layer of the coding layer number as the input quantity for serial demodulation of the i+1-th layer. Among them, the second device serially demodulates the number of coding layers layer by layer to obtain M n-length rate matching information sequences to be decoded. For the specific process, please refer to the detailed description of serial demodulation in the above-mentioned MLC, and please refer to the description in the above-mentioned Figure 3 for details, which will not be repeated here.

It should also be understood that the method by which the second device determines the first position set and the method by which the third sequence is determined are similar to the method by which the first device determines the first position set and the third sequence in steps 601 to 603 in FIG. 6 above, and are not described in detail here.

In one possible implementation, after receiving n transmitted symbols from the first device, the second device serially demodulates the n transmitted symbols layer by layer according to the number of coding layers corresponding to the modulation order M, and obtains M n-length rate-matched information sequences to be decoded. The second device performs rate-matching on the M n-length rate-matched information sequences to be decoded according to the first bit position corresponding to the highest reliability layer in the first position set, thereby obtaining M n'-length information sequences to be decoded. The second device decodes the M n'-length information sequences to be decoded layer by layer according to the number of coding layers corresponding to the modulation order M, and obtains K information bits, which are composed of ki information bits corresponding to each layer in the M coding layers.

Specifically, assuming that the code rate of the i-th layer in MLC is less than the first threshold, then when the second device solves the rate matching, the second device fills in "0" for the corresponding first bit position in the first position set; assuming that the code rate of the i-th layer in MLC is greater than or equal to the first threshold, then when the second device solves the rate matching, the second device fills in an infinite value, for example, positive infinity or negative infinity, for the corresponding first bit position in the first position set.

In another possible implementation, after receiving n transmitted symbols from the first device, the second device serially demodulates the n transmitted symbols layer by layer according to the number of coding layers corresponding to the modulation order M, and obtains M n-length rate matching information sequences to be decoded. The second device performs rate matching on the M n-length rate matching information sequences to be decoded according to the first bit position in the first position set corresponding to the i-th coding layer number in the number of coding layers corresponding to the modulation order M, thereby obtaining M n'-length information sequences to be decoded. The device decodes the M n'-length to-be-decoded information sequences layer by layer according to the number of coding layers corresponding to the modulation order M, and obtains K information bits, which are composed of ki information bits corresponding to each layer in the M number of coding layers.

In the process of serial demodulation, when the second device demodulates the i-th layer in the MLC, the second device performs rate matching according to the first bit position corresponding to the i-th layer in the first position set, thereby obtaining a codeword of length n'. Specifically, assuming that the code rate of the i-th layer in the MLC is less than the first threshold, the second device fills "0" in the corresponding first bit position in the first position set when performing rate matching; when the code rate of the i-th layer in the MLC is greater than or equal to the first threshold, the second device fills an infinite value, for example, positive infinity, or negative infinity, in the corresponding first bit position in the first position set when performing rate matching.

The method proposed in the present application is described in detail above. As an example, a simulation diagram of the symbol signal-to-noise ratio under the same number of information bits, number of first symbols and code rate is given below based on the method proposed in the present application.

FIG. 10 is a schematic diagram of a BLER simulation.

It should be understood that FIG10 is based on the method shown in FIG6 above, and is a change in the symbol signal-to-noise ratio given by combining the number of information bits K, the number of first symbols N, and the code rate R. MLC_TYPE0 in FIG10 indicates that the first position set is obtained by reversing the bits of the second position set in FIG6, and the first bit position in the first position set is used as the rate matching position; MLC_TYPE1 indicates that the first bit position corresponding to each number of coding layers is determined by comparing the relationship between the code rate and the first threshold in FIG6, and the bit position corresponding to the modulation order with the highest reliability in the third sequence is used as the rate matching sequence, and rate matching is performed after modulation.

As shown in FIG10 , the black solid line and the gray solid line represent a simulation diagram using the number of information bits K=539, the number of first symbols N=600, and R=0.90. It can be seen that under the same parameters, the symbol signal-to-noise ratio using the MLC_TYPE1 method is significantly lower than the symbol signal-to-noise ratio using the MLC_TYPE0 method.

As shown in FIG10 , the black dotted line and the gray dotted line represent a simulation diagram using the number of information bits K=67, the number of first symbols N=75, and R=0.89. It can be seen that under the same parameters, the symbol signal-to-noise ratio using the MLC_TYPE1 method is significantly lower than the symbol signal-to-noise ratio using the MLC_TYPE0 method.

FIG. 11 is a schematic diagram of another BLER simulation.

It should be understood that FIG11 is based on the method shown in FIG6 above, and is a variation of the symbol signal-to-noise ratio given by combining the number of information bits K, the number of first symbols N, and the code rate R. MLC_TYPE0 in FIG11 indicates that the first position set is obtained by reversing the bits of the second position set in FIG6, and the first bit position in the first position set is used as the rate matching position; MLC_TYPE1 indicates that the first bit position corresponding to each number of coding layers is determined by comparing the relationship between the code rate and the first threshold in FIG6, and the bit position corresponding to the modulation order with the highest reliability in the third sequence is used as the rate matching sequence.

As shown in FIG11 , the black solid line and the gray solid line represent a simulation diagram using the number of information bits K=1845, the number of first symbols N=700, and R=2.64. It can be seen that under the same parameters, the symbol signal-to-noise ratio using the MLC_TYPE1 method is significantly lower than the symbol signal-to-noise ratio using the MLC_TYPE0 method.

As shown in FIG11 , the black dotted line and the gray dotted line represent a simulation diagram using the number of information bits K=232, the number of first symbols N=88, and R=2.64. It can be seen that under the same parameters, the symbol signal-to-noise ratio using the MLC_TYPE1 method is significantly lower than the symbol signal-to-noise ratio using the MLC_TYPE0 method.

According to the simulation schematic diagrams shown in Figures 10 and 11 above, under the same parameters, the present application provides a method for determining the first bit position corresponding to each coding layer number by comparing the relationship between the code rate and the first threshold, and using the bit position corresponding to the modulation order with the highest reliability in the third sequence as the encoding and decoding method corresponding to the rate matching sequence. The symbol signal-to-noise ratio is significantly better than other methods.

It is understood that the steps in the above figures are only exemplary and not strictly limited. In addition, the sequence numbers of the above processes do not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

It can also be understood that some coding sequence names are involved in the various embodiments of the present application, and their naming does not limit the protection scope of the embodiments of the present application.

It can also be understood that some optional features in the embodiments of the present application may not depend on other features in some scenarios, or may be combined with other features in some scenarios, without limitation.

It can also be understood that in the above-mentioned various method embodiments, the methods and operations implemented by the first device can also be implemented by components (such as chips or circuits) that can be implemented by the first device, without limitation.

Corresponding to the methods given in the above-mentioned method embodiments, the embodiments of the present application also provide corresponding devices, which include modules for executing the corresponding modules in the above-mentioned method embodiments. The modules can be software, hardware, or a combination of software and hardware. It is understood that the technical features described in the above method embodiments are also applicable to the following device embodiments.

FIG12 is a schematic block diagram of a communication device 1200 provided in the present application. As shown in FIG12 , the communication device 1200 includes a processing unit 1210 and a communication unit 1220. The device 1200 can implement the steps or processes corresponding to those performed by the first device in the above method embodiment, wherein the processing unit 1210 is used to perform the processing-related operations of the first device in the above method embodiment, and the communication unit 1220 is used to perform the sending-related operations of the first device in the above method embodiment. For example, each unit of the communication device 1200 is used to implement the following functions:

In one possible implementation, the processing unit 1210 is used to determine the second symbol number n' based on the first symbol number n, where n'≥n, and n' is an integer power of 2, and n is a positive integer; the processing unit 1210 is also used to pre-freeze the bits corresponding to (N-n') symbols in the first sequence according to the second symbol number n' to obtain a second sequence, where the first sequence corresponds to the number of symbols N and the modulation order M, where N≥n', and N and M are both positive integers; the processing unit 1210 is also used to determine a third sequence according to the first symbol number n and the second sequence, where the third sequence is a pre-frozen sequence related to polar code encoding.

In another possible implementation, the processing unit 1210 is used to determine the second symbol number n' based on the first symbol number n, where n'≥n, and n' is an integer power of 2, and n is a positive integer; the processing unit 1210 is also used to pre-freeze the bits corresponding to (N-n') symbols in the first sequence according to the second symbol number n' to obtain a second sequence, where the first sequence corresponds to the number of symbols N and the modulation order M, where N≥n', and N and M are both positive integers; the processing unit 1210 is also used to determine a third sequence according to the first symbol number n and the second sequence, where the third sequence is a pre-frozen sequence related to polar code decoding.

In each embodiment of the communication device 1200 corresponding to the transmitting end, the processing unit 1210 is used to perform the processing and/or operation implemented by the first device in addition to the sending and receiving actions. The communication unit 1220 is used to perform the receiving (or inputting) action of the first device, and/or, to perform the sending (or outputting) action of the first device.

It should be understood that the device 1200 herein is embodied in the form of a functional unit. The term "unit" herein may refer to an application specific integrated circuit (ASIC), an electronic circuit, a processor (e.g., a shared processor, a dedicated processor, or a group processor, etc.) and a memory for executing one or more software or firmware programs, a combined logic circuit, and/or other suitable components that support the described functions.

The apparatus 1200 of each of the above schemes has the function of implementing the corresponding steps performed by the first device in the above method. The function can be implemented by hardware, or by hardware executing the corresponding software implementation. The hardware or software includes one or more modules corresponding to the above functions; for example, the communication unit can be replaced by a transceiver (for example, the sending unit in the communication unit can be replaced by a transmitter, and the receiving unit in the communication unit can be replaced by a receiver), and other units, such as the processing unit, can be replaced by a processor to respectively perform the sending and receiving operations and related processing operations in each method embodiment.

In addition, the communication unit may also be a transceiver circuit (for example, it may include a receiving circuit and a transmitting circuit), and the processing unit may be a processing circuit. In an embodiment of the present application, the device 1200 may be the first device in the aforementioned embodiment, or may be a chip or a chip system, for example, a system on chip (SoC), wherein the communication unit may be an input/output circuit, a communication interface, and the processing unit may be a processor or a microprocessor or an integrated circuit integrated on the chip. This is not limited here.

FIG13 is a schematic structural diagram of a communication device 1300 provided in the present application. As shown in FIG13 , the communication device 1300 includes: one or more processors 1310, one or more memories 1320, and one or more communication interfaces 1330. The processor 1310 is used to control the communication interface 1330 to send and receive signals, the memory 1320 is used to store a computer program, and the processor 1310 is used to call and run the computer program from the memory 1320, so that the communication device 1200 performs the processing performed by the transmitting end or the receiving end in each method embodiment of the present application.

For example, the processor 1310 may have the function of the processing unit 1210 shown in Figure 8, and the communication interface 1330 may have the function of the communication unit 820 shown in Figure 12. Specifically, the processor 1310 may be used to execute the processing or operation performed by the communication device, and the communication interface 1330 is used to execute the sending and/or receiving operation of the communication device.

Optionally, the memory and processor in the above-mentioned device embodiments may be physically independent units, or the memory may be integrated with the processor, which is not limited in the present application.

In addition, the present application also provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed on a computer, the operations and/or processing performed by the first device in each method embodiment of the present application are executed.

In addition, the present application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and/or processing performed by the first device in each method embodiment of the present application are executed.

In addition, the present application also provides a chip, which includes a processor, a memory for storing computer programs is set independently of the chip, and the processor is used to execute the computer program stored in the memory, so that a device equipped with the chip performs the operations and/or processing performed by the first device in any method embodiment.

Furthermore, the chip may further include a communication interface. The communication interface may be an input/output interface, or an interface circuit, etc. Furthermore, the chip may further include the memory.

Optionally, the processor may be one or more, the memory may be one or more, and the memory may be one or more.

In addition, the present application also provides a communication device (for example, a chip or a chip system), including a processor and a communication interface, according to the operation and/or processing performed by the first device in any of the aforementioned method embodiments, the communication interface is used to receive (or referred to as input) message bits to be encoded, and the processor encodes the message bits to be encoded. Optionally, the communication interface is also used to send (or referred to as output) data and/or information processed by the processor.

In addition, the present application also provides a communication device, comprising at least one processor, wherein the at least one processor is coupled to at least one memory, and the at least one processor is used to execute a computer program or instruction stored in the at least one memory, so that the communication device performs the operations and/or processing performed by the first device in any method embodiment.

In addition, the present application also provides a communication system, including the first device in the method embodiment of the present application.

The memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DRRAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

The method provided in the above embodiment can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product may include one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated.

In order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, numbers such as "first" and "second" are used to distinguish the same or similar items with substantially the same functions and effects. Those skilled in the art can understand that numbers such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

In the embodiments of the present application, "at least one" means one or more, and "more" means two or more. "And/or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and/or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character "/" generally indicates that the associated objects before and after are in an "or" relationship.

Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only illustrative, for example, the division of the units is only a logical function. In actual implementation, there may be other ways of division, for example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not performed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, which may be electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

Claims (17)

A method for rate matching of Polar codes, comprising: Based on the first symbol number n, determine a second symbol number n', n'≥n, and n' is an integer power of 2, and n is a positive integer; Determine a first position set according to the first symbol number n and the second symbol number n', where the first position set includes first bit positions corresponding to (n'-n) symbols; In the second sequence, the bit indicated by the first bit position is pre-frozen to obtain a third sequence, wherein the third sequence is a pre-frozen sequence related to polar code encoding, The second sequence is a sequence obtained by pre-freezing bits corresponding to (N-n’) symbols in the first sequence according to the second symbol number n’, and the first sequence corresponds to the symbol number N and the modulation order M, N≥n’, and N and M are both positive integers. The method according to claim 1, characterized in that the determining the first position set according to the first symbol number n and the second symbol number n' comprises: Determine a second position set according to the first symbol number n, the second symbol number n' and the second sequence, the second position set including a bit position corresponding to the nth symbol to a bit position corresponding to the (n'-1)th symbol in the second sequence, and the second position set including second bit positions corresponding to the (n'-n)th symbol; The second bit positions corresponding to the (n’-n) symbols are bit reversed to determine the first position set. The method according to claim 1, characterized in that the determining the first position set according to the first symbol number n and the second symbol number n' comprises: The first position set is determined based on the first symbol number n, the second symbol number n’ and the second sequence, and the first bit position corresponding to the (n’-n)th symbol in the first position set is the bit position corresponding to the nth symbol to the bit position corresponding to the (n’-1)th symbol determined after sub-block interleaving of the bit positions corresponding to the second sequence. The method according to claim 1, characterized in that the determining the first position set according to the first symbol number n and the second symbol number n' comprises: The first position set is determined according to the first symbol number n, the second symbol number n' and the code rate Ri, the first bit position corresponding to the (n'-n)th symbol in the first position set is the bit position corresponding to the nth symbol to the bit position corresponding to the (n'-1)th symbol determined after sub-block interleaving of the bit position corresponding to the second sequence, or the first bit position corresponding to the (n'-n)th symbol in the first position set is the bit position corresponding to the 0th symbol to the bit position corresponding to the (n'-n-1)th symbol determined after sub-block interleaving of the bit position corresponding to the second sequence, Among them, the Ri is the ratio of the number ki of information bits corresponding to the i-th modulation order in the second sequence to the first number of symbols n, 0≤i≤M-1. The method according to any one of claims 1 to 4, characterized in that the method further comprises: According to the third sequence, allocating K information bits to non-pre-frozen bits corresponding to M modulation orders in the third sequence; Encode each layer of the coding layers corresponding to the modulation order M of the third sequence to obtain M codewords of length n′; Modulating the M n'-length codewords to obtain n' symbols; Using the bit position corresponding to the modulation order with the highest reliability in the third sequence as a rate matching sequence; According to the rate matching sequence, n symbols are selected from the n' symbols as transmission symbols for transmission. The method according to any one of claims 1 to 4, characterized in that the method further comprises: According to the third sequence, allocating K information bits to non-pre-frozen bits corresponding to M modulation orders in the third sequence; Encode each layer of the coding layers corresponding to the modulation order M of the third sequence to obtain M codewords of length n′; Using the third sequence as a rate matching sequence, obtaining M codewords of length n according to the M codewords of length n, n transmission symbols are sent, where the n transmission symbols are modulated according to the M n-length codewords. A method for rate matching of Polar codes, comprising: Based on the first symbol number n, determine a second symbol number n', n'≥n, and n' is an integer power of 2, and n is a positive integer; Determine a first position set according to the first symbol number n and the second symbol number n', where the first position set includes first bit positions corresponding to (n'-n) symbols; In the second sequence, the bit indicated by the first bit position is pre-frozen to obtain a third sequence, wherein the third sequence is a pre-frozen sequence related to polar code decoding, The second sequence is a sequence obtained by pre-freezing bits corresponding to (N-n’) symbols in the first sequence according to the second symbol number n’, and the first sequence corresponds to the symbol number N and the modulation order M, N≥n’, and N and M are both positive integers. The method according to claim 7, characterized in that the determining the first position set according to the first symbol number n and the second symbol number n' comprises: Determine a second position set according to the first symbol number n, the second symbol number n' and the second sequence, the second position set including a bit position corresponding to the nth symbol to a bit position corresponding to the (n'-1)th symbol in the second sequence, and the second position set including second bit positions corresponding to the (n'-n)th symbol; The second bit positions corresponding to the (n’-n) symbols are bit reversed to determine the first position set. The method according to claim 7, characterized in that the determining the first position set according to the first symbol number n and the second symbol number n' comprises: The first position set is determined based on the first symbol number n, the second symbol number n’ and the second sequence, and the first bit position corresponding to the (n’-n)th symbol in the first position set is the bit position corresponding to the nth symbol to the bit position corresponding to the (n’-1)th symbol determined after sub-block interleaving of the bit positions corresponding to the second sequence. The method according to claim 7, characterized in that the determining the first position set according to the first symbol number n and the second symbol number n' comprises: The first position set is determined according to the first symbol number n, the second symbol number n' and the code rate Ri, the first bit position corresponding to the (n'-n)th symbol in the first position set is the bit position corresponding to the nth symbol to the bit position corresponding to the (n'-1)th symbol determined after sub-block interleaving of the bit position corresponding to the second sequence, or the first bit position corresponding to the (n'-n)th symbol in the first position set is the bit position corresponding to the 0th symbol to the bit position corresponding to the (n'-n-1)th symbol determined after sub-block interleaving of the bit position corresponding to the second sequence, Among them, the Ri is the ratio of the number ki of information bits corresponding to the i-th modulation order in the second sequence to the first number of symbols n, 0≤i≤M-1. The method according to any one of claims 7 to 10, characterized in that the method further comprises: Receiving n transmitted symbols, and serially demodulating the n transmitted symbols layer by layer according to the number of coding layers corresponding to the modulation order M, to obtain M n-length rate matching information sequences to be decoded; According to the bit position with the highest reliability in the first position set, rate matching is performed on the M n-length to-be-decoded information sequences to obtain M n′-length to-be-decoded information sequences; The M n'-length codewords are decoded layer by layer according to the number of coding layers corresponding to the modulation order M, to obtain ki information bits corresponding to the i-th layer in the number of coding layers, where: K is a positive integer. The method according to any one of claims 7 to 10, characterized in that the method further comprises: Receiving n transmitted symbols, and serially demodulating the n transmitted symbols layer by layer according to the number of coding layers corresponding to the modulation order M, to obtain M n-length rate matching information sequences to be decoded; According to the first bit position in the first position set corresponding to the i-th coding layer number in the coding layer number corresponding to the modulation order M, rate matching is performed on the M n-length codewords to obtain M n'-length information sequences to be decoded; Decoding the M n'-length codewords layer by layer according to the number of coding layers corresponding to the modulation order M to obtain ki information bits corresponding to the i-th coding layer number, K is a positive integer. A communication device, characterized in that it comprises a module or unit for executing the method according to any one of claims 1 to 6, or a module or unit for executing the method according to any one of claims 7 to 12. A communication device, characterized in that it comprises at least one processor, wherein the at least one processor is coupled to at least one memory, and the at least one processor is used to execute a computer program or instruction stored in the at least one memory so that the communication device performs the method as described in any one of claims 1 to 6, or so that the communication device performs the method as described in any one of claims 7 to 12. A chip, characterized in that it comprises a processor and a communication interface, wherein the communication interface is used to receive a sequence to be encoded and send the sequence to be encoded to the processor, wherein the processor is according to the method according to any one of claims 1 to 6, or The processor is according to the method of any one of claims 7 to 12. A computer-readable storage medium, characterized in that the computer-readable storage medium stores computer instructions, which, when executed on a computer, enable the method as claimed in any one of claims 1 to 6, or the method as claimed in any one of claims 7 to 12. A computer program product, characterized in that the computer program product comprises computer program code, and when the computer program code is run on a computer, the method according to any one of claims 1 to 6 is performed, or the method according to any one of claims 7 to 12 is performed.