P A T E N T Docket No. QS2090 OPTOELECTRONIC, THERMOELECTRIC, PHOTONIC, MATERIALS AND DEVICES, FABRICATED ON THE BACK SIDE SURFACE OF CMOS WAFERS Cross Reference To Related Applications [0001] The present application claims priority to U.S. Provisional Patent Application No. 63/588,669, filed October 6, 2023, entitled “OPTOELECTRONIC, THERMOELECTRIC, PHOTONIC, MATERIALS AND DEVICES, FABRICATED ON THE BACK SIDE SURFACE OF CMOS WAFERS,” the disclosure thereof incorporated by reference herein in its entirety. Field [0002] The disclosed technology relates generally to semiconductors, and more particularly some embodiments relate to CMOS image sensors. Background [0003] CMOS Image Sensors (CIS) with Back Side Illumination (BSI), have light-sensing devices (e.g., photodiodes) receiving light through the back side of the silicon wafer, after thinning the wafer. Current state-of-the-art wafers with BSI may incorporate epitaxial silicon layers grown/deposited on the front side of the wafer, before the fabrication of CMOS devices. CIS BSI is the only technology in high volume manufacturing in which the starting silicon wafer is thinned, and the back side surface is further processed, for trench isolation between adjacent pixels, formation of pinning layers, and for fabrication of color filters and microlenses. Summary [0004] Embodiments of the present invention pertain to optoelectronic, thermoelectric, and photonic devices monolithically integrated with CMOS technology. Embodiments of the present invention pertain to the fabrication of light-absorbing devices, light-emitting devices, light- modulating devices, light-waveguiding devices, nonlinear photonic materials, optical combs/microcombs, photon frequency conversion devices; thermoelectric devices for the cooling of optoelectronic devices and for energy harvesting; optoelectronic, photonic, and phononic metamaterials, via the incorporation of epitaxially grown layers on the back side surface of a thinned substrate, opposite to that on which CMOS devices are fabricated (i.e., the front side surface). Embodiments of the present invention pertain also to the monolithic integration of 2D and 3D metaoptics materials and devices, to focus light, separate light, and
P A T E N T Docket No. QS2090 route light according to parameters such as wavelength, polarization, etc., at the pixel level and/or at the system level. [0005] Embodiments of the present invention concern CMOS wafers with back-side devices (BSD), which may be optoelectronic and/or thermoelectric. Some examples are described for CMOS Image Sensors (CIS); however, the disclosed technologies are not limited to image sensing. [0006] In some embodiments of the present invention, heterojunction epitaxial layers are pseudomorphically grown/deposited on the back side of a CMOS silicon wafer (which may be a CIS BSI wafer), after wafer thinning, and said heterojunction epitaxial layers are electrically and/or optically coupled to CMOS devices fabricated on the front side of the wafer. Before the pseudomorphic growth of the heterojunction layers, the back side surface of the thinned wafer may be processed to comprise multiple regions with different crystallographic orientations. This enables the pseudomorphic heterojunction layers to be strained to multiple surface crystallographic orientations. Multiple epitaxial growths of diverse heterojunction layers, to enable a variety of different devices, is enabled by the capability to perform at low temperature, surface cleaning, preparation, and epitaxial growth, for example, below 500 °C, or preferably below 400 °C. [0007] These heterojunction layers are preferably made of, but not restricted to, group-IV elements (C, Si, Ge, Sn, Pb), in the forms of random alloys and/or ordered alloys, and/or quantum wells, and/or superlattices, and/or resonant tunneling structures. These heterojunction layers may also be processed into nanostructures, such as quantum dots, lateral and/or vertical quantum wires (nanowires), superlattice nanowires, quantum dots embedded in nanowires, superlattice quantum dots embedded in nanowires, etc. These materials and/or nanostructured layers include conventional semiconductor materials, elements, and alloys, with indirect and/or direct bandgaps, the latter being much more efficient at light absorption and light emission. Said epitaxial materials may also include metamaterials with topological properties, such as 3D topological insulators, 3D topological semimetals, etc. Materials incorporating elements from other columns of the periodic table may be used, either as doping impurities or as components of alloys, and/or quantum wells, and/or quantum dots, and/or superlattices, for electronic and/or phononic and/or photonic band structure engineering purposes. [0008] Said epitaxial layers/materials may be part of optoelectronic devices to provide charge multiplication (i.e., gain), or to absorb or emit light, or waveguide light, or modulate light, or amplify light, or to change photon frequency/energy (i.e., upconvert or down convert). The
P A T E N T Docket No. QS2090 aforementioned materials, metamaterials, and devices may be used to handle light across a very wide range of the electromagnetic spectrum, including Gamma rays, X-rays, Ultra-Violet, Near- Ultra-Violet (NUV), Visible, Near Infra-Red (NIR), Short Wavelength Infra-Red (SWIR), Middle Wavelength Infra-Red (MWIR), Long Wavelength Infra-Red (LWIR), Very Long Wavelength Infra- Red (VLWIR), Far Infra-Red (FIR), and TeraHertz. This is possible because metamaterials comprising group-IV elements, from the lightest (carbon) to the heaviest (lead), enable different types of physics regarding light-matter interactions, including photoabsorption and photoemission. [0009] The embodiments depicted in the figures according to the disclosed technologies, show examples of devices fabricated and integrated as part of 2D arrays of pixels, because it illustrates the case with more constraints, in terms of geometry and size/pitch. Naturally, any of these embodiments may more easily be made outside the 2D array, for example, at its periphery. Brief Description of the Drawings [0010] The present disclosure, in accordance with one or more various embodiments, is described in detail with reference to the following figures. The figures are provided for purposes of illustration only and merely depict typical or example embodiments. [0011] FIG.1 is a schematic drawing with a 3D view of a prior art CMOS BSI device having a 2x2 pixel array. [0012] FIG.2 is a schematic drawing with a 3D view of a CMOS BSI device having a 2x2 pixel array according to some embodiments of the disclosed technologies. [0013] FIG.3 is a schematic drawing with a 3D view of another CMOS BSI device having a 2x2 pixel array according to some embodiments of the disclosed technologies. [0014] FIG.4 is a schematic drawing with a 3D view of another CMOS BSI device having a 2x2 pixel array with epitaxial heterojunction layers grown/deposited on ultrathin substrates with different crystallographic orientations, according to some embodiments of the disclosed technologies. [0015] FIG.5 is a schematic drawing with a 3D view of a CMOS BSI device based on the device of FIG 4 according to some embodiments of the disclosed technologies. separate photoabsorption and charge multiplication (i.e., gain) regions. [0016] FIG.6 is an exemplary qualitative band alignment plot.
P A T E N T Docket No. QS2090 [0017] FIG.7A shows a schematic band alignment plot depicting the photoabsorption of Ultra- Violet (UV) photons in silicon in a conventional CIS BSI, including UV photoelectrons trapped near the back side surface by a potential barrier. [0018] FIG.7B shows a schematic band alignment plot depicting the photoabsorption of Ultra- Violet (UV) photons in silicon in an epitaxial p+ SiGeC alloy layer with graded composition and doping concentration, according to some embodiments of the disclosed technologies. [0019] FIG.8 is a schematic drawing with a 3D view of a CMOS BSI device with a 2x2 pixel array, in which pixels and have direct ohmic contacts to the epitaxial films 131 and 132, respectively, according to some embodiments of the disclosed technologies. [0020] FIG.9 is a schematic drawing with a 3D view of a CMOS BSI device having a 2x2 array of pixels with epitaxial heterojunction layers grown/deposited on ultrathin substrates with different crystallographic orientations, comprising separate photoabsorption and charge multiplication (i.e., gain) regions, according to some embodiments of the disclosed technologies. [0021] FIG.10 is a schematic drawing with a 3D view of a CMOS BSI device with a 2x2 pixel array with epitaxial heterojunction active regions and resonant enhancement structures, according to some embodiments of the disclosed technologies. [0022] FIG.11 is a schematic drawing with a 3D view of a CMOS BSI device with a 2x2 pixel array for photoabsorption or photoemission (e.g., LED/LASER), according to some embodiments of the disclosed technologies. [0023] FIG.12 is a schematic drawing with a 3D view of a CMOS BSI device with a 2x2 pixel array for photoabsorption or photoemission, according to some embodiments of the disclosed technologies. [0024] FIG.13 is a schematic drawing with a 3D view of a CMOS BSI device with a 2x2 pixel array, based on the CMOS BSI device of FIG.5, according to some embodiments of the disclosed technologies. [0025] FIG.14 is a schematic drawing with a 3D view of a CMOS BSI device with a 2x2 pixel array, based on the CMOS BSI device of FIG.9, according to some embodiments of the disclosed technologies. [0026] FIG.15 is a schematic drawing with a 3D view of a CMOS BSI device with a 2x2 pixel array, based on the CMOS BSI device of FIG.14, according to some embodiments of the disclosed technologies.
P A T E N T Docket No. QS2090 [0027] FIG.16 is a schematic drawing with a 3D view of a CMOS BSI device with a 2x2 pixel array, based on the CMOS BSI device of FIG.15, depicting a planarized 2D array of GRIN lenses, according to some embodiments of the disclosed technologies. [0028] FIG.17 is a schematic drawing with a 3D view of a CMOS BSI device with a 2x2 pixel array, based on the CMOS BSI device of FIG.16, according to some embodiments of the disclosed technologies. [0029] FIG.18 is a schematic drawing with a 3D view of a CMOS BSI device with a 4x4 pixel array, based on the CMOS BSI device of FIG.17, depicting the integration of a 3D metaoptics layer for a flat system lens, which may be a system-level GRIN lens. [0030] FIG.19 is a schematic drawing with a 3D view of a CMOS BSI device with a 2x2 pixel array including Vertical Cavity Surface Emitting LASERS (VCSELs) that are optically coupled through waveguides, according to some embodiments of the disclosed technologies. [0031] FIG.20A is a schematic representation of a CMOS BSI device with an 8x82D array of light-sensing pixels and light-emitting pixels arranged in a first pattern, according to some embodiments of the disclosed technologies. [0032] FIG.20B is a schematic representation of a CMOS BSI device with an 8x82D array of light-sensing pixels and light-emitting pixels arranged in a second pattern, according to some embodiments of the disclosed technologies. [0033] FIG.20C is a schematic representation of a CMOS BSI device with an 8x82D array of light-sensing pixels and light-emitting pixels arranged in a third pattern, according to some embodiments of the disclosed technologies. [0034] FIG.20D is a schematic representation of a CMOS BSI device with an 8x82D array of light-sensing pixels and light-emitting pixels arranged in a fourth pattern, according to some embodiments of the disclosed technologies. [0035] FIGs.21.1-21.30 illustrate a process for fabricating a CMOS-integrated optoelectronic and/or thermoelectric device using a first process integration architecture, according to some embodiments of the disclosed technologies. [0036] FIGs.22.1-22.29 illustrate a process for fabricating a CMOS-integrated optoelectronic and/or thermoelectric device using a second process integration architecture, according to some embodiments of the disclosed technologies. [0037] FIGs.23.1-23.38 illustrate a process for fabricating a CMOS-integrated optoelectronic and/or thermoelectric device using a third process integration architecture, according to some embodiments of the disclosed technologies.
P A T E N T Docket No. QS2090 [0038] FIGs.24.1-24.88 illustrate a process for fabricating a CMOS-integrated optoelectronic and/or thermoelectric device using a fourth process integration architecture, according to some embodiments of the disclosed technologies. [0039] FIG.25A illustrates a first example of a single-chip “System of LiDAR Systems”, according to some embodiments of the disclosed technologies. [0040] FIG.25B illustrates a second example of a single-chip “System of LiDAR Systems”, according to some embodiments of the disclosed technologies. [0041] FIG.26 is a schematic with a 3D view of a parallel optical processing system, according to some embodiments of the disclosed technologies. [0042] FIG.27A is a plot of the 20-atom cell used to calculate ab-initio the band structure of Ge
2Sn
2C strained to Si (001). [0043] FIG.27B is a plot of the band structure of Ge
2Sn
2C strained to Si (001), showing a direct band-gap. [0044] FIG. 28A is a schematic drawing with a 3D view of Fiber-Coupled Optical (FCO) communications system, according to some embodiments of the disclosed technologies. [0045] FIG. 28B is a schematic drawing with a 3D view of the system of FIG. 28A with lenses added. [0046] FIG.29 shows an example of an XR system in the form of eyeglasses, according to some embodiments of the disclosed technologies. [0047] FIG.30 shows an example of an under-display 3D sensing system. [0048] FIG.31 is a flowchart illustrating a process for fabricating a CMOS-integrated optoelectronic and/or thermoelectric device, according to some embodiments of the disclosed technologies. [0049] FIGs.32A,B depict a flowchart illustrating a process for fabricating a CMOS-integrated optoelectronic and/or thermoelectric device using the first process integration architecture, according to some embodiments of the disclosed technologies. [0050] FIGs.33A-D depict a flowchart illustrating a process for fabricating a CMOS-integrated optoelectronic and/or thermoelectric device using the first process integration architecture, according to some embodiments of the disclosed technologies. [0051] FIGs.34A,B depict a flowchart illustrating a process for fabricating a CMOS-integrated optoelectronic and/or thermoelectric device using the second process integration architecture, according to some embodiments of the disclosed technologies.
P A T E N T Docket No. QS2090 [0052] FIGs.35A-E depicts flowchart illustrating a process for fabricating a CMOS-integrated optoelectronic and/or thermoelectric device using the second process integration architecture, according to some embodiments of the disclosed technologies. [0053] FIGs.36A,B depict a flowchart illustrating a process for fabricating a CMOS-integrated optoelectronic and/or thermoelectric device using the third process integration architecture, according to some embodiments of the disclosed technologies. [0054] FIGs.37A-F depict a flowchart illustrating a process for fabricating a CMOS-integrated optoelectronic and/or thermoelectric device using the third process integration architecture, according to some embodiments of the disclosed technologies. [0055] FIGs.38A,B depict a flowchart illustrating a process for fabricating a CMOS-integrated optoelectronic and/or thermoelectric device using the fourth process integration architecture, according to some embodiments of the disclosed technologies. [0056] FIGs.39A-L depict a flowchart illustrating a process for fabricating a CMOS-integrated optoelectronic and/or thermoelectric device using the fourth process integration architecture, according to some embodiments of the disclosed technologies. [0057] FIG. 40 is a flowchart illustrating a first process for fabricating a FCO communications system, according to some embodiments of the disclosed technologies. [0058] FIG.41 is a flowchart illustrating a second process for fabricating a FCO communications system, according to some embodiments of the disclosed technologies. [0059] FIG. 42A is a schematic drawing with a 3D view of Free-Space Optical (FSO) communications system, according to some embodiments of the disclosed technologies. [0060] FIG. 42B is a schematic drawing with a 3D view of the system of FIG. 42A with lenses added. [0061] FIG. 43 is an example computing component that may be used to implement various features of embodiments described in the present disclosure. [0062] FIG.44 is a schematic drawing with a 3D view of a CMOS BSI device with a 2x2 pixel array for photoabsorption or photoemission, according to some embodiments of the disclosed technologies. [0063] The figures are not exhaustive and do not limit the present disclosure to the precise form disclosed.
P A T E N T Docket No. QS2090 Detailed Description [0064] Current state-of-the-art CIS-BSI products are made through the 3D wafer-scale integration of multiple wafers, each comprising semiconductor devices optimized for a particular functionality: for example, a wafer with pixels (photodiodes and basic pixel-circuitry), with color filters and microlenses, another wafer with pixel transistors (for analog and/or digital circuitry), another wafer with digital signal processing, another wafer with memory elements, etc. The process architectures described herein cover the process steps performed on the wafer with pixels (i.e., the wafer), which are independent of the processing and functionality of the other wafers with circuitry that may be wafer-level 3D integrated with the wafer. [0065] In the drawings, the reference numbers refer to the elements listed below. [0066] 100 – CMOS silicon wafer. [0067] 101 – Front side of CMOS wafer. [0068] 102 – Back side of CMOS wafer. [0069] 103 – Photodiode (PD) implant (n-type). [0070] 104 – Threshold (VT) implant (n-type). [0071] 105 – Floating Diffusion (FD) implant (n-type). [0072] 106 – Pinning Layers (p-type). [0073] 107 – Deep trench Isolation (DTI). [0074] 108 – CMOS device, typically a N-MOSFET. [0075] 109 – Metal Optical Reflector. [0076] 110 – Anti-Reflection Coating (ARC). [0077] 111 – Light Beam. [0078] 112 – Pixel #1 (Blue). [0079] 113 – Pixel #2 (Green). [0080] 114 – Pixel #3 (Green). [0081] 115 – Pixel #4 (Red). [0082] 116 – Superlattice. [0083] 117 – Interface layer. [0084] 118 – Pinning layer.
P A T E N T Docket No. QS2090 [0085] 119 – New Pixel#2 (SWIR). [0086] 120 – Insulator #1. [0087] 121 – Epitaxially deposited silicon. [0088] 122 – Insulator #2. [0089] 123 – Insulator #3, such as silicon nitride, for example. [0090] 124 – Metal Optical Reflector. [0091] 125 – Pixel #1. [0092] 126 – Pixel #2. [0093] 127 – Pixel #3. [0094] 128 – Pixel #4. [0095] 129 – Etch marker layer #1. [0096] 130 – Etch marker layer #2. [0097] 131 – Epitaxial Film #1. [0098] 132 – Epitaxial Film #2. [0099] 133 – Epitaxial Film #3. [00100] 134 – Epitaxial Film #4. [00101] 135 – Silicon layer with (110) crystallographic orientation. [00102] 136 – Silicon layer with (111) crystallographic orientation. [00103] 137 – Interfacial layer #1. [00104] 138 – Interfacial layer #2. [00105] 139 – Interfacial layer #3. [00106] 140 – Interfacial layer #4. [00107] 141 – Gain layers. [00108] 142 – Defect-generated electrons trapped near surface by potential barrier. [00109] 143 – SiGeC interfacial layer. [00110] 144 – Energy. [00111] 145 – Distance.
P A T E N T Docket No. QS2090 [00112] 146 – Valence Band Maximum. [00113] 147 – Conduction Band Minimum. [00114] 148 – Fermi level. [00115] 149 – Electrons. [00116] 150 – P-type SiGeC epitaxially deposited film. [00117] 151 – UV photoelectrons trapped near surface by potential barrier. [00118] 152 – Electron photo-generated by UV light. [00119] 153 – NWELL. [00120] 154 – PWELL. [00121] 155 – NMOS. [00122] 156 – PMOS. [00123] 157 – Silicide. [00124] 158 – Pre-Metal Dielectric. [00125] 159 – Metal. [00126] 160 – Insulator, for example silicon oxide. [00127] 161 – NMOS source/drain junction. [00128] 162 – PMOS source/drain junction. [00129] 163.1 – First Epsilon-Near-Zero (ENZ) material as half-cavity of laser. [00130] 163.2 – Second Epsilon-Near-Zero (ENZ) material as half-cavity of laser. [00131] 164 – Active region of laser. [00132] 165.1 – First dielectric material as half-cavity of laser. [00133] 165.2 – Second dielectric material as half-cavity of laser. [00134] 166 – N-type region to inject electrons into active region of laser. [00135] 167 – P-type region to inject holes into active region of laser. [00136] 168.1 – First mirror layers. [00137] 168.2 – Second mirror layers. [00138] 168.3 – Third mirror layers.
P A T E N T Docket No. QS2090 [00139] 169 – Nanowire core region, epitaxially deposited and n-type doped. [00140] 170 – Nanowire shell layer, epitaxially deposited and p-type doped. [00141] 171 – Electro-Optic Modulator (EOM). [00142] 172 – N-type Thermo-Electric Converter (TEC). [00143] 173 – P-type TEC. [00144] 174 – N-type epitaxial thin layer. [00145] 175 – Highly conductive layer. [00146] 176 – Pixel-level GRIN lens. [00147] 177 – Pixel-level 3D Metaoptics for Wavelength & Polarization Routing [00148] 178 – Pixel for Red & Polarization #1. [00149] 179 – Pixel for Red & Polarization #2. [00150] 180 – Pixel for Green & Polarization #1. [00151] 181 – Pixel for Green & Polarization #2. [00152] 182 – System-level 3D Metaoptics Flat Lens. [00153] 183 – Waveguide optically coupling multiple lasers. [00154] 184 – Pixel with photodiode for light sensing. [00155] 185 – Pixel with laser for light emission. [00156] 186 – N-type region to extract electrons from active region of photodiode. [00157] 187 – P-type region to extract holes from active region of photodiode. [00158] 188 – Active region of photodiode. [00159] 200 – Package substrate. [00160] 201 – CMOS die. [00161] 202 – VCSELs. [00162] 203 – Large 2D array of VCSELs. [00163] 204 – VCSELs inside the main 2D array, but outside the image circle of the GRIN lens. [00164] 205 – Monolithically integrated GRIN lens, with image circle inscribed inside a large 2D array of light-sensing pixels and/or vertical emitting lasers, optically coupled via
P A T E N T Docket No. QS2090 waveguides but electrically biased independently (i.e., powered), capable of beam steering. The 2D array can have any of the layouts shown in figures 20A, 20B, 20C, 20D. [00165] 206 – GRIN lens having a telephoto aperture. [00166] 207 – GRIN lens having a prime/main aperture. [00167] 208 – GRIN lens having a wide aperture. [00168] 209 – GRIN lens having a fisheye aperture. [00169] 210 – GRIN lens designed for imaging Visible+SWIR wavelengths. [00170] 211 – GRIN lens designed for imaging MWIR wavelengths. [00171] 212 – GRIN lens designed for imaging LWIR wavelengths. [00172] 220 – Light-sensing pixels. [00173] 221 – 2D array of light-sensing pixels. [00174] 222 – Buffer layer. [00175] 223 – Vertical Emitting Lasers. [00176] 224 – 2D array of vertical emitting lasers. [00177] 225 – Phase mask(s). [00178] 226 – Stack of masks. [00179] 240 – Second wafer. [00180] 241 – Optical fiber. [00181] 242 – Tip of fiber core. [00182] 243 – Light-sensing element. [00183] 244 – Hole through second wafer 240. [00184] 245 – Lens. [00185] 246 – Lens. [00186] 250 – Glasses’ plastic and/or metal frame [00187] 251 – See-through lenses showing overlayed information in visible wavelengths. [00188] 252 – System-on-chip. [00189] 253 – CMOS RGB+SWIR Camera. [00190] 255 – Display bezel of portable device
P A T E N T Docket No. QS2090 [00191] 256 – Display [00192] 257 – Under-display system-on-chip SWIR 3D sensing system. [00193] 300 – Silicon substrate. [00194] 301 – Front side of CMOS wafer. [00195] 302 – Back side of CMOS wafer. [00196] 303 – First Wafer Holder/Carrier. [00197] 304 – Silicon layer with (110) crystallographic orientation. [00198] 305 – Silicon layer with (111) crystallographic orientation. [00199] 306 – Silicon Oxide (SiO2). [00200] 307 – Silicon Nitride (Si3N4). [00201] 308 – Epitaxial Layers – composition #1. [00202] 309 – Epitaxial Layers – composition #2. [00203] 310 – Epitaxial Layers – composition #3. [00204] 311 – Epitaxial Layers – composition #4. [00205] 312 – Epitaxial Layers – composition #5. [00206] 313 – Second Wafer Holder/Carrier. [00207] 314 – Shallow Trench Isolation (STI). [00208] 315 – Photodiode Implant (n-type for a p-type doped wafer). [00209] 316 – Pinning layer implant (p-type for a n-type photodiode). [00210] 317 – Gate of MOSFET (NMOS for a n-type photodiode implant), also known as Transfer Gate. [00211] 318 – Threshold Implant (VT) for NMOS. [00212] 319 – Spacer (typically silicon nitride). [00213] 320 – Floating Diffusion (FD). [00214] 321 – Pre-Metal Dielectric Layer. [00215] 322 – Contact to gate of MOSFET. [00216] 323 – Contact to Floating Diffusion. [00217] 324 – Complete Metallization Stack.
P A T E N T Docket No. QS2090 [00218] 325 – Circuit Wafer. [00219] 326 – Deep trench. [00220] 327 – Epitaxially deposited pinning layer (p-type). [00221] 328 – Anti-Reflection Coating (ARC). [00222] 329 – Conventional color filter dyes. [00223] 330 – Conventional polymeric microlens. [00224] 331 – First opening. [00225] 332 – Second opening. [00226] 333 – Third opening. [00227] 334 – Fourth opening. [00228] 335 –Deep Trench Isolation (DTI). [00229] 336 – Metal Optical Reflector. [00230] 337 – First epitaxially grown charge multiplication region. [00231] 338 – First epitaxially grown photo-absorption region. [00232] 339 – Second epitaxially grown charge multiplication region. [00233] 340 – Second epitaxially grown photo-absorption region, patterned into a nanowire or a quantum dot. [00234] 341 – Epitaxial layers comprising lowly n-type doped film and highly doped n-type film, followed by the p-type thermoelectric converter layers. [00235] 342 – Epitaxial layers comprising lowly n-type doped film and highly doped n-type film, followed by the n-type thermoelectric converter layers. [00236] 343 – Fifth opening. [00237] 344 – Sixth opening. [00238] 345 – Epitaxial p-type thermoelectric converter layers. [00239] 346 – Epitaxial n-type thermoelectric converter layers. [00240] 347 – Metal contacts to the p-type and n-type thermoelectric converters. [00241] 348 – Metal lines. [00242] 349 – Metal-Dielectric layer stack.
P A T E N T Docket No. QS2090 [00243] 350 – Patterned Metal-Dielectric layer stack forming pixel-level GRIN microlenses. [00244] 351 – Pixel-level 3D MetaOptics Color and Polarization Routing. [00245] 352 – System-level 3D MetaOptics Flat Lens. [00246] 353.1 – Pixel #1 (FIG.23) [00247] 353.2 – Pixel #2 (FIG.23) [00248] 353.3 – Pixel #3 (FIG.23) [00249] 353.4 – Pixel #4 (FIG.23) [00250] 354.1 – Pixel #1 (FIG.24) [00251] 354.2 – Pixel #2 (FIG.24) [00252] 354.3 – Pixel #3 (FIG.24) [00253] 354.4 – Pixel #4 (FIG.24) [00254] 354.5 – Pixel #5 (FIG.24) [00255] 360 – N-Well region. [00256] 361 – P-Well region. [00257] 362 – Highly n-type doped region. [00258] 363 – Highly p-type doped region. [00259] 364 – Source/Drain regions of NMOS. [00260] 365 – Source/Drain regions of PMOS. [00261] 366 – Threshold Implant (VT) for NMOS. [00262] 367 – Threshold Implant (VT) for PMOS. [00263] 368 – Gate of NMOS. [00264] 369 – Gate of PMOS. [00265] 370 – Silicide regions. [00266] 371 – Metal contacts to the Source/Drain regions of NMOS and PMOS. [00267] 372 – Metal contacts to the Gates NMOS and PMOS. [00268] 373 – Metal interconnects between silicide at the surface of source/drain regions of MOSFETs, and silicide at the surface of regions that will become metal-filled trenches to provide electrical connections between MOSFET devices made on the top surface of the wafer
P A T E N T Docket No. QS2090 and optoelectronic and/or thermoelectric devices fabricated on the bottom surface of the back- side thinned wafer. [00269] 374 – P+ pinning layer. [00270] 375 – Epitaxially grown layers. [00271] 376 – Epitaxially grown layers. [00272] 377 – Epitaxially grown layers. [00273] 378 – Epitaxially grown layers. [00274] 379 – Epitaxially grown layer. [00275] 380 – Patterned epitaxial layers into a nanowire (forming a core). [00276] 381 – P+ pinning layer. [00277] 382 – Mirror layers. [00278] 383 – Nanotrench. [00279] 384 – Photoresist. [00280] 385 – Top DBR (mirror) layers. [00281] 386 – Electro-Optic Modulator (EOM) layers. [00282] 387 – Middle DBR (mirror) layers. [00283] 388 – Top Half-Cavity. [00284] 389 – Laser active layers. [00285] 390 – Notch into active region of laser, formed by lateral selective etch. [00286] 391 – Bottom Half-Cavity. [00287] 392 – Selective epitaxial layer, highly p-type doped. [00288] 393 – Selective epitaxial layer, highly n-type doped. [00289] 394 – Quantum dot active laser region. [00290] 395 – Trenches etched through dielectric layers. [00291] 396 – Selective etch of Bottom DBR (mirror) layers. [00292] 397 – Lateral selective etch of bottom DBR (mirror) layers. [00293] 398 – Holes to p-type layers. [00294] 399 – Holes to n-type layers.
P A T E N T Docket No. QS2090 [00295] 400 – P-type doped layers. [00296] 401 – N-type doped layers. [00297] 402 – Contact hole to first side of EOM. [00298] 403 – Metal fill of contact hole 402. [00299] 404 – Contact hole to second side, opposite to first side, of the EOM. [00300] 405 – Metal fill of contact hole 404. [00301] 406 – Contact holes. [00302] 407 – Metal fill of contact holes 406. [00303] 408 – Contact holes. [00304] 409 – Oxidized epitaxial layer. [00305] 410 – Metal fill of contact holes 408. [00306] 411 – Contact hole. [00307] 412 – Metal fill of contact hole 411. [00308] 413 – Contact hole. [00309] 414 – Metal fill of contact hole 413. [00310] 415 – Contact holes. [00311] 416 – Metal fill of contact holes 415. [00312] 417 – Deep trenches. [00313] 418 – Metal fill of deep trenches 417. [00314] 419 – Trenches into SiO2 to define metal interconnects. [00315] 420 – Metal fill of trenches 420. [00316] FIG.1 is a schematic drawing with a 3D view of a prior art CMOS BSI device having a 2x2 pixel array. Recent reviews of the state-of-art in CIS BSI technology may be found in the following references: Y. Oike, "Evolution of Image Sensor Architectures With Stacked Device Technologies", in IEEE Transactions on Electron Devices, vol. 69, no. 6, pp. 2757-2765, June 2022, DOI: 10.1109/TED.2021.3097983; S. -G. Wuu, H. -L. Chen, H. -C. Chien, P. Enquist, R. M. Guidash and J. McCarten, "A Review of 3-Dimensional Wafer Level Stacked Back side Illuminated CMOS Image Sensor Process Technologies", in IEEE Transactions on Electron Devices, vol.69, no. 6, pp. 2766-2778, June 2022, DOI: 10.1109/TED.2022.3152977; and Springer Handbook of
P A T E N T Docket No. QS2090 Semiconductor Devices, 2023, Editors: M. Rudan, R. Brunetti, S. Reggiani, Chapter 18, “Silicon Sensors”, Section 18.11.3, “CMOS Image Sensor: A Complete Solution”. ISBN 978-3-030-79826- 0. DOI: 10.1007/978-3-030-79827-7. [00317] Previous disclosures described methods of fabrication of epitaxially grown heterojunction layers for photoabsorption and/or gain, on the front side of CMOS substrates for Front Side Illumination (FSI) with a number of variations in different aspects of either the process flow or of layouts for the active region on which the epitaxial films were to be grown. Examples of such disclosures include U.S. Patents No. 6,943,051; 7,265,006; 8,816,443; 7,521,737; 8,120,079; 8,963,169; 8,963,169; 9,640,616; and 10,756,227. In all of these disclosures, the epitaxial layers are grown on the front side of the CMOS substrate, i.e., the side on which CMOS devices are fabricated, for FSI imagers. Back Side Illumination with the epitaxial layers grown on the front side of the CMOS substrate were disclosed in U.S. Patent No. 7,153,720, by using ultrathin film (fully-depleted) silicon-on-insulator substrates, in which the silicon wafer providing support for the thin buried oxide and top ultrathin silicon layer, is replaced by a substrate transparent to the wavelengths of interest, for example, visible light. The methods of fabrication of the disclosed technologies may include current state-of-the-art fabrication technologies (equipment and process chemistries). For example, these technologies may include low- temperature process steps, including in-situ cleaning and conditioning of the substrate surface prior to epitaxial growth, the epitaxial growth itself, as well as patterning, cleaning, and passivation of outer surfaces of epitaxially grown layers, as well as silicide formation, etc. The low-temperature processing may be enabled by the pre-epitaxy cleaning and conditioning of the surface being performed in chambers mounted in cluster platforms shared with the epitaxial growth chambers. Process steps with these characteristics are standard in current leading edge CMOS processing, from FinFET CMOS technology, to future CMOS technologies such as Gate All Around (GAA) Nanosheet FETs and Vertical-Transport FETs. The low-temperature cleaning and epitaxial growth may enable sequential multiple cleaning and epitaxial growth runs without disturbing existing layers or devices, either on the front side or on the back side of the wafer. [00318] In standard wafers, the desired amount of light absorbed in the pixels, in particular for the longer wavelengths in the Near-Infra-Red (NIR) range, determines the depth of the photodiode and therefore the final thickness of the wafer (after wafer thinning). If an epitaxial photoabsorption layer possesses a combination of thickness and coefficient of absorption such that all light is absorbed within it, then the wafer bulk is no longer useful for photoabsorption, and its thickness is no longer constrained by it. This is true for wavelengths that silicon may absorb,
P A T E N T Docket No. QS2090 and naturally the silicon bulk wafer is not relevant for the absorption of light with wavelengths longer than the cut off wavelength of silicon, i.e., longer than ~1.1 μm. [00319] As with standard CIS FSI, CIS BSI also uses p-type pinning layers surrounding the n-type photodiode region to suppress leakage currents generated at crystal surfaces and interfaces from entering the photoabsorption region. In this disclosure the same polarities are assumed for those regions, but it would be apparent to one skilled in the relevant arts to reverse the doping polarities, which would require the transfer gate, reset transistor, source-follower and row-select transistors to be PMOS instead of NMOS. Actually PMOS-based CIS pixels have the advantage of lower leakage currents than NMOS-based CIS, due to the lower mobility of holes compared to electrons. [00320] DEVICES [00321] FIG.2 is a schematic drawing with a 3D view of a CMOS BSI device having a 2x2 pixel array according to some embodiments of the disclosed technologies. The CMOS BSI device may include a CMOS silicon wafer 100 having a front side 101 and a back side 102. The CMOS silicon wafer 100 may be p-type doped after thinning wafer from the back side 102. At least one CMOS device 108 may be fabricated on the front side 101 of the CMOS silicon wafer 100. The CMOS device 108 may be an N-MOSFET. In the example of FIG.2, there are four CMOS devices 108, one for each pixel, and each CMOS device 108 includes a threshold (VT) implant (n-type) 104, a floating diffusion (FD) implant (n-type) 105, and pinning layers (p-type) 106. [00322] The pixels may include at least one optoelectronic and/or thermoelectric device 119. The CMOS BSI device may include at least one electrical connecting region electrically coupling the at least one optoelectronic and/or thermoelectric device 119 and the at least one CMOS device 108. In the example of FIG. 2, one electrical connecting region may include a photodiode (PD) implant (n-type) 103 and an epitaxially deposited interface layer 117, and another electrical connecting region may include pinning layers 106 (p-type) and a p-type pinning layer 118. The pinning layer 118 may be epitaxially deposited on surfaces of epitaxial layers 116 and the back side 102 of the wafer 100. [00323] In the example of FIG.2, the optoelectronic and/or thermoelectric device 119 is a pixel having a heterojunction layer epitaxially grown/deposited on the back side of thinned wafer for photoabsorption of Short Wavelength Infra-Red (SWIR). This SWIR pixel 119 may have a photoabsorption region 116. The photoabsorption region 116 may be a group-IV superlattice, epitaxially gown on the back side 102 of the substrate 100. In FIG. 2, the remaining pixels are conventional RGB pixels 112, 114, and 115.
P A T E N T Docket No. QS2090 [00324] An interface layer 117 may be epitaxially deposited between the back side 102 of the silicon substrate 100 and the superlattice 116. The interface layer 117 may adjust the band offsets such that photo-generated carriers may smoothly travel from the epitaxial heterojunction photoabsorbing layer 116 to the silicon substrate 100. An insulator 120 that is transparent to visible wavelengths may cover the RGB pixels 112, 114, and 115 in order to create a planar surface on which a conventional color filter array and microlenses may be made. For example, the insulator 120 may be a dielectric such as silicon oxide. [00325] FIG.3 is a schematic drawing with a 3D view of another CMOS BSI device having a 2x2 pixel array according to some embodiments of the disclosed technologies. As in FIG.2, the device of FIG.3 may include Red, Green, Blue, and SWIR pixels 112, 114, 115, and 119, and the SWIR pixel 119 may have a photoabsorption region 116 that is a group-IV superlattice. The planarization of the back side surface 102 may be obtained by the growth of epitaxial silicon films 122 on the pixels that are to absorb visible wavelengths, and by depositing silicon oxide between the epitaxial films 116 and 121. The silicon epitaxial film 121 grown on the pixels for the visible range may be replaced by other group-IV materials with better optoelectronic performance, as described elsewhere in this disclosure. [00326] The pseudomorphic film of an alloy and the pseudomorphic film of a superlattice, having the same number of atoms of each chemical species, such as Si, Ge and C, may have very different band structures, and thus optoelectronic properties, because of different spatial/geometric locations of the different chemical species of atoms. Depending on the crystallographic orientation of the silicon surface on which they are pseudomorphically grown, even the exact same alloy composition or superlattice composition, may have very different band structures and therefore optoelectronic properties. These topics were discussed in U.S. Patent No.9,640,616, “Superlattice materials and applications”, and in C. Augusto, L. Forester, "Novel Si–Ge–C superlattices and their applications”; Solid-State Electr., Vol.110, 2015, pages 1-9, DOI: 10.1016/j.sse.2015.01.019. For the same reasons explained in this reference, the same effects also occur for pseudomorphic alloy or superlattice films incorporating Sn and/or Pb. [00327] Consequently, it is desirable to have multiple crystallographic orientations available for epitaxial growth, because they offer a wider range of band structure and band offset engineering. The growth of pseudomorphic films on surfaces of different crystallographic orientations may be performed separately for each crystallographic orientation, in which case each epitaxial growth may be done for a different composition (i.e., alloys, and/or quantum wells, and/or resonant tunneling structures, and/or superlattices). On the other hand, it may happen
P A T E N T Docket No. QS2090 that a film of the exact same composition may have desirable properties when pseudomorphically grown on multiple crystallographic orientations. In that case it may be possible, and perhaps advantageous, to perform the epitaxial growth simultaneously on multiple crystallographic orientations. [00328] Silicon wafers having surfaces with multiple crystallographic orientations became a topic of relevance in the mid-2000’s, as illustrated by the following references: Q. Ouyang et al., “Investigation of CMOS devices with embedded SiGe source/drain on hybrid orientation substrates”, VLSI Symp. Tech. Dig., pages 28-29, 2005; DOI: 10.1109/.2005.1469199; C. D. Sheraw et al., “Dual stress liner enhancement in hybrid orientation technology”, VLSI Symp. Tech. Dig., pages 12-13, 2005; DOI: 10.1109/.2005.1469192; and M. Yang et al., “Hybrid- orientation technology (HOT): Opportunities and challenges”. IEEE Trans. Electr. Dev., vol. 53, pages 965-978, 2006; DOI: 10.1109/TED.2006.872693. [00329] All previous work on producing surfaces with different crystallographic orientations had the purpose of taking advantage of different surface orientations with higher electron or hole mobilities to improve the performance of N-MOSFET and P-MOSFET, respectively. Currently, standard CMOS processing, including CIS, both for front side and back side illumination, only uses silicon wafers with (001) surface orientation. [00330] Additional surface orientations for the epitaxial growth of strained films may be added by low-temperature bonding of ultrathin silicon layers with the desired crystallographic orientations. Conceptually, an additional layer that is bonded to the back side of the standard wafer may have an arbitrary surface orientation, but most likely the key useful additional orientations are the (110) and (111) surface orientations. The present disclosure also describes how to integrate different surfaces of different crystallographic orientations on the back side of wafers, for subsequent epitaxial growth of pseudomorphic films. In the context of the disclosed technologies, this is a desirable optional feature, but not a requirement. [00331] A few different approaches were developed for the fabrication of multiple- orientation substrates on the front side of a wafer, and conceptually any of those may also be used for the back side of wafers. For sake of simplicity, in the exemplary process flows of the disclosed technologies only one method is illustrated, in which ultrathin crystalline silicon layers are bonded, without interfacial oxides or any other insulating layers, to the back side of the CMOS substrate. These ultrathin layers may be just a few nanometers thick, for example 10 nm or less. To simplify subsequent processing, these layers may already have a desirable doping concentration before bonding to the back side of the CMOS substrate. Since in current CIS technology the photodiodes are typically n-type doped, these layers with different
P A T E N T Docket No. QS2090 crystallographic orientations may also be lightly n-type doped, with a lower concentration than the n-type doping of the photodiode in the original wafer. But these layers may also be lightly p- type doped, with the precise doping concentration determined for each specific photodiode doping level near the back side surface. It should be understood that the back side of the wafer cannot have a p-type pinning layer between the n-type doping of the photodiode and the epitaxial layers grown on its surface, or the ultrathin layers with different crystallographic orientations. [00332] The exemplary process flows, using starting substrates with (0 0 1) surface orientation, describe the inclusion of two additional layers: one layer with (110), and the other with (111) surface orientation. For practical reasons, the number of layers must be finite, but each specific crystallographic orientation is arbitrary. In current state-of-the-art ultrathin (fully- depleted) silicon-on-insulator (FD-SOI) substrates, the top silicon film may be less than 10 nm thick. FD-SOI wafers are formed by first splitting away an ultrathin layer from a bulk wafer, and then bonding it to a silicon oxide layer on top of another wafer having normal thickness. Consequently, the disclosed splitting and bonding of ultrathin (e.g., 10 nm thick or less) silicon layers to the back side of the thinned CMOS wafer may make use of existing technology. [00333] It may happen that the bonding strength between the silicon wafer substrate and the substrate layers with different orientations is weaker than the bonding strength between the latter and the epitaxial heterojunction layers grown on them. Should this be the case, there may be some slippage at the interface between the wafer substrate and substrate layers with different orientations, thereby lowering the level of strain in the epitaxial heterojunction layers. This effect may be counteracted by growing a film of silicon, before growing the epitaxial heterojunction layers, with sufficient thickness to maintain the strain level in the heterojunction layers, as if they were grown on a thick bulk substrate with the desired crystallographic orientation. [00334] FIG.4 is a schematic drawing with a 3D view of another CMOS BSI device having a 2x2 pixel array with epitaxial heterojunction layers grown/deposited on ultrathin substrates with different crystallographic orientations, according to some embodiments of the disclosed technologies. The device may have two additional silicon substrate layers 135 and 136 with (11 0) and (1 1 1) crystallographic orientations, respectively, in which different pixels have the epitaxial pseudomorphic growth of device layers performed on the Si (001), or the Si (110), or the Si (111) surface orientations. In order to enable highly selective etches of ultrathin substrates needed to grow epitaxial device layers on other ultrathin substrates with different crystallographic orientations, epitaxial etch marker layers 129 and 130 may be included between each ultrathin substrate with a different crystallographic orientation. Note some elements in FIG. 4 are cut away to show internal details of the device.
P A T E N T Docket No. QS2090 [00335] The epitaxial layers may also be used to form the charge multiplication (gain) regions of avalanche photo-diodes (APDs), or form the gain region of devices making use of the gain mechanism described in U.S. Patent No. 10,756,227 “Electrical Devices making use of counterdoped junctions”, or the gain described in J. T. Teherani, “The Auger FET- a Novel Device Concept for Subthermal Switching”, IEEE Electr. Dev. Techn. and Manuf. Conference, Invited Paper 8C-1 (2018). DOI: 10.1109/EDTM.2018.8421442, or Resonant Tunneling Diodes (RTD) photodetectors, which have been shown to be capable of single-photon detection at room temperature, as discussed in the following reference, and references therein: F. Rothmayr et al., “Resonant Tunneling Diodes: Mid-Infrared Sensing at Room Temperature”, Nanomaterials, 12, 1024 (2022). DOI: 10.3390/nano12061024. [00336] FIG.5 is a schematic drawing with a 3D view of a CMOS BSI device based on the device of FIG 4 according to some embodiments of the disclosed technologies, showing separate photoabsorption and charge multiplication (i.e., gain) regions. The photoabsorption regions 103, 131, 132, 133, and 134 are grown after and on top of the gain regions 141, which are epitaxially grown on the silicon substrates 100 and incorporate the interface layers 137, 138, 139, and 140 to adjust the band offsets, and therefore these specific interface layers are omitted from this figure. The gain layers 141 may be of the kind described in the aforementioned U.S. Patent No. 10,756,227, between the photoabsorption region and the charge collection region (i.e., n- type doped photodiode region) in the CIS BSI pixel. Note some elements in FIG.5 are cut away to show internal details of the device. [00337] Photoabsorption layers of materials other than silicon may have bandgaps different from silicon’s. Consequently, there may be band offsets with respect to silicon. Actually, even if the bandgap was exactly the same as silicon’s, there may still be type-II or type- III band offsets. A smooth band-edge alignment between a non-silicon photoabsorption material and a silicon substrate may be obtained by inserting an interfacial transition layer including group-IV alloys with a compositional gradient. For a photoabsorption whose band alignment with silicon is of type-I (i.e., nested inside silicon’s bandgap), as is the case for several Si-Ge-C superlattices with direct bandgaps, the transition layer may be composed of SiGe and/or SiGeC. The composition of the transition layer may be linearly graded or stepwise graded (with step length much smaller than the wavelength of light), the latter with a step height that is comparable or smaller than the thermal noise level (k
BT) at target temperature of operation, which at room temperature is around 25 meV. [00338] FIG. 6 is an exemplary qualitative band alignment plot. In FIG. 6, the horizontal axis 145 represents distance, while the vertical axis 144 represents energy. The plot
P A T E N T Docket No. QS2090 schematically depicts the conduction band edge 147 and the valence band edge 146 of the n- type silicon CIS BSI, including the p+ pinning layer 118 at the front side surface 101, the band edges of an undoped or lightly p-type doped superlattice photoabsorption region 116, the undoped or lightly p-type doped interfacial transition layers 137, 138, 139, and 140 between the region of the silicon substrate 100 having the PD implant 103 and the superlattice 116, and the transition layers 143 between the superlattice 116 and a silicon p+ silicon pinning layer 118, capping the superlattice layers. Also shown is the Fermi level 148, electrons 149 in a potential well, and a defect-generated electron 142 trapped near the surface 101 by a potential barrier. It is trivial to generate the band alignment plot for the reverse doping polarities and photo- generated charge carriers. [00339] When there is a gain region between the photoabsorption region and the photodiode implant in the bulk, interface layers may be used to provide the desired band alignments between the photoabsorption region and the gain region, and between the gain region and the photodiode implanted region in the bulk. In the drawing figures, when there is a gain region, such as those described in aforementioned U.S. Patent No.10,756,227, the gain region may include the interfacial layers to adjust the band offsets between the photoabsorption region and the silicon bulk substrate in order to provide a smooth band edge between these regions for the photo-generated carriers. [00340] Image sensing in the Ultra-Violet (UV) range may also benefit from epitaxially grown films on silicon. Silicon has an extremely high coefficient of absorption for UV light, which is absorbed within just a few nanometers from the photodiode surface. This characteristic is a problem due to the existence of surface states and defects that cause carrier recombination, and thus loss of signal. This problem is in part caused by the typical doping profiles, and thus electrical potential profiles, produced by doping through ion-implantation and annealing. These doping profiles have gaussian shapes, which means that photogenerated carriers closer to the surface are confined there by a potential barrier, blocking them from reaching the charge collection region. [00341] This problem may be solved with doping and heterojunction profiles produced by low-temperature epitaxial growth, which may have much larger doping gradients, with monotonic variation. An example of such a doping profile may have an extremely large doping level at the surface and have a thickness of just a few nanometers (e.g., less than 3nm), thereby providing Fermi-level pinning at the surface, and monotonically lower the doping level away from the surface, towards the bulk. Such a profile would shield the bulk from the surface defects and
P A T E N T Docket No. QS2090 would allow photogenerated carriers within a few nanometers from the surface (generated by UV light) to be driven by a built-in electric field towards the regions of charge collection and readout. [00342] FIG.7A shows a schematic band alignment plot depicting the photoabsorption of Ultra-Violet (UV) photons in silicon in a conventional CIS BSI, including UV photoelectrons 151 trapped near the back side surface 102 by a potential barrier. [00343] FIG.7B shows a schematic band alignment plot depicting the photoabsorption of Ultra-Violet (UV) photons in silicon in an epitaxial p+ SiGeC alloy layer 150 with graded composition and doping concentration, according to some embodiments of the disclosed technologies. This arrangement generates a triangular potential profile, such that the side of the p+ SiGeC layer 150 with wider bandgap is the one closest to the back side surface 102 and the side with the narrower bandgap is the one interfacing with the front side surface 101. This potential profile enables efficient extraction of photoelectrons 152 generated by UV near the back side surface 102. As shown, with epitaxial p+ SiGeC layer 150 there is no potential barrier so all UV photoelectrons 152 drift along the conduction band minimum 147 towards the potential well due to the heterojunction built-in electric field. [00344] The graded composition and doping concentration in the epitaxial SiGeC layer 150 are qualitatively similar to that of the base region in typical n-p-n SiGe or SiGeC HBTs in BiCMOS technology. The triangular/trapezoidal potential profile that produces a built-in electric field to drive the electrons from the interface with the n-type Emitter, across the p-type Base, towards the n-type Collector, is the type of potential profile needed to drive the photoelectrons generated by UV near the p-type doped surface, towards n-type photodiode implant. [00345] As already mentioned, group-IV direct bandgap materials are very desirable to significantly increase the performance of light-absorption devices, such as photodiodes. At the same time, direct bandgap materials enable efficient light-emitting devices (LEDs) and LASERs that may be monolithically integrated with CMOS to form light-emitting pixels side-by-side with light-receiving pixels. At the same time, sophisticated heterojunction engineering also enables electromagnetic metamaterials having novel properties to absorb and/or emit electromagnetic radiation across multiple frequency ranges. [00346] ^ƅ^èĺIJťŘĺīīĖIJČ^ ťēô^ıÍČIJôťĖè^ŕôŘıôÍæĖīĖťƅ^ ^̕^^ ÍIJî^ ťēô^ ŘôÍī^ ŕÍŘť^ ĺċ^ ťēô^îĖôīôèťŘĖè^ ŕôŘıĖťťĖŽĖťƅ^^̎
r), new functionalities become possible. A few types of metamaterials include: [00347] A) Negative-index metamaterials (NIM) or "left-handed media", where the negative index of refraction arises from simultaneously negative permittivity and negative permeability are also known as double negative metamaterials or double negative materials (DNG).
P A T E N T Docket No. QS2090 [00348] B) Single negative (SNG) metamaterials have either negative relative permittivity ^̎r) or negative relative permeability (μr), but not both. They act as metamaterials when combined with a different, complementary SNG, jointly acting as a DNG. Epsilon negative media (ENG) îĖŜŕīÍƅ^ Í^ IJôČÍťĖŽô^ ̎r while μr is positive. Mu-negative media (MNG) îĖŜŕīÍƅ^ Í^ ŕĺŜĖťĖŽô^ ̎r and negative μr. Gyrotropic or gyromagnetic materials exhibit this characteristic. [00349] C) Hyperbolic MetaMaterials (HMMs) behave as a metal for certain polarization or direction of light propagation and behave as a dielectric for the other due to the negative and positive permittivity tensor components, giving extreme anisotropy. HMMs have showed various potential applications, such as sensing, reflection modulator, imaging, optical beam-steering, enhanced plasmon resonance effects. [00350] D) Electromagnetic bandgap metamaterials (EBG or EBM) control light propagation. This is accomplished either with photonic crystals (PC) or left-handed materials (LHM). [00351] E) Any of the above may be patterned and structured to form 3D chiral metamaterials. [00352] HMMs have optical phase diagrams showing that they may behave as an effective dielectric (^
^, ^
צ > 0), effective metal (^
^, ^
צ < 0), or exhibit Type-I hyperbolic character (^
^ > 0, ^
צ < 0), or Type-II hyperbolic character (^
^ < 0, ^
צ > 0), where ^
צ
denote in-plane and out-of-plane effective medium dielectric functions, respectively. The frequency dependent optical properties of an HMM depend on the ratio of the thicknesses of the conducting layers to non-conducting (dielectric) layers (i.e., the fill factor) as well as the optical properties of the conductive layers and dielectric layers. HMMs consisting of alternating layers of non-conducting and conducting layers are straightforward to fabricate with group-IV materials. HMM may be realized by alternating planar layers of epitaxially compatible materials, such as undoped semiconductor layers with positive bandgap and highly doped semiconductor layers, or semiconductor layers with negative bandgap (i.e., semimetals) which would not need doping. [00353] Several Group-IV superlattices strained to Si surfaces enable the realization of strain-balanced HMM layers by alternating undoped semiconductor layers (with positive bandgap) and semiconductor layers with negative bandgap. HMM layers may be used to enhance optoelectronic properties such as light absorption, emission, and waveguiding. These optoelectronic capabilities are particularly relevant for the longer wavelengths, such as MWIR, LWIR, VLWIR, FIR, and TeraHertz. At the same time, the ability to enhance the optoelectronic properties is dependent on the plasmon frequencies of the HMM layers, which are intrinsic properties of materials.
P A T E N T Docket No. QS2090 [00354] The maximum plasmon frequencies in the (natural) materials used so far in metamaterials have limited the maximum photon frequency (or energy) for which it has been possible to engineer metamaterials. However, the maximum plasmon frequency in metamaterials may be engineered to surpass the plasmon frequency of the constituent (natural) materials of the metamaterial’s layers, as it has been shown in the following references: K. Li et al., “Ballistic Metamaterials” Adv. Opt. Mater.8, 2070098 (2020). DOI: 10.1364/OPTICA.402891; A. J. Muhowski et al., "Extending plasmonic response to the mid-wave infrared with all-epitaxial composites", Opt. Lett.47, 973-976 (2022). DOI: 10.1364/OL.445482. [00355] Another route to increase the maximum plasmon frequencies for metamaterials is through effective mass engineering in superlattices. As described in the following reference, it is possible to engineer electronic superlattices with highly anisotropic masses, including zero longitudinal mass and infinite in-plane mass: M. G. Silveirinha and N. Engheta, “Transformation Electronics: Tailoring the Effective Mass of Electrons”; Phys. Rev. B 86161104(R) (2012), DOI: 10.1103/PhysRevB.86.161104. [00356] The availability of metamaterials with maximum plasmon frequencies in the SWIR range, such as 1550 nm, enables the realization of resonant cavities for 1550nm LASERs in which the length of the cavity may be many times smaller than the wavelength of light, as explained in the following reference: N. Engheta, “An Idea for Thin Subwavelength Cavity Resonators Using Metamaterials With Negative Permittivity and Permeability”, IEEE Antennas and Wireless Propagation Letters, Vol.1 (2002). DOI: 10.1109/LAWP.2002.802576. [00357] HMMs have several advantages over conventional photodiodes for sensing MWIR, LWIR and longer wavelengths. In the absence of large excitonic binding energies, photodiodes need to have bandgaps smaller than the photon energy, which for MWIR and LWIR photons means very small bandgaps. Consequently, at room temperature the intrinsic carrier concentrations are very large, as are the dark-currents in p-n junctions or p-i-n junctions. This is the reason why photodetectors for MWIR and LWIR typically need to be cooled well below room temperature, thereby making them unsuitable for a variety of applications. One important disadvantage of conventional photodiodes is that the scaling down of lateral dimensions is limited by diffraction, and the scaling of the absorption depth (i.e., thickness of the photoabsorption layers) is also restricted by the wavelength. The following references provide overviews of HMM technologies that may overcome these limitations of conventional light- sensing devices: L. Nordin and D. Wasserman, “Epitaxial mid-IR nanophotonic optoelectronics”, Appl Phys. Lett., Vol 120, No.22. DOI: 10.1063/5.0086774.
P A T E N T Docket No. QS2090 [00358] In addition, metamaterials/metasurfaces with near-zero index of refraction may suppress/eliminate reflection at the interface between air (or a dielectric with a low refraction index) and the photonic device layers, such as the group-IV epitaxial layers. These metamaterials may be wavelength-selective or broadband, and may be polarization sensitive or insensitive. Perfect absorbers may provide extraordinary performance for Gated Image Sensing and to light- sensors in systems such as LiDARs, and have been demonstrated recently for arbitrary wavefronts: Y. Slobodkin et al., “Massively degenerate coherent perfect absorber for arbitrary wavefronts”, SCIENCE 25, Vol 377, Issue 6609 pp. 995-998 (2022). DOI: 10.1126/science.abq8103. [00359] Direct bandgap materials may also host excitons, which increase the oscillator strength, and the quantum efficiency of light absorption and/or light emission. Excitons may also be hosted in type-II heterojunctions, in which electrons and holes reside in spatially different layers, thereby increasing the exciton lifetime. It should be noted that band-to-band (i.e., interband) transitions across type-II heterojunction are indirect in real space but may be direct in k-space if the band extrema on both sides of the heterojunction are at the same k-point (the gamma point, for example). Excitons enable a given material, with a given bandgap, to absorb photons with energy smaller than that of the bandgap. The exciton binding energy determines how much smaller the photon energy may be, and therefore, larger exciton biding energies enable photoabsorption of longer wavelengths (for the same bandgap). Engineering materials with larger exciton binding energies is an alternative path to sensing longer wavelengths, while not decreasing the bandgap, and thus not increasing dark-current. [00360] As mentioned earlier, some group-IV superlattices may have negative bandgaps, i.e., are semimetals. Some superlattices are topologically non-trivial semimetals, such as Dirac or Weyl semimetals, and others are topological insulators, with a gapped bulk and gapless surface stages (i.e., metallic surfaces). Such types of topological materials have been reported to have properties similar to those of HMMs, and therefore may be used as a single material, or as the conductive material in a stack alternating with positive, direct, or indirect, bandgap semiconducting layers. These materials exhibit a variety of unconventional properties, such as the Bulk PhotoVoltaic Effect (BPVE), which may be significant in non-centrosymmetric crystals. Many group-IV superlattice crystals are non-centrosymmetric crystals and consequently may exhibit BPVE, in which the photovoltage (i.e., the open-circuit voltage caused by the light- absorption) may be larger than the bandgap by several orders of magnitude, depending on the thickness of the photoabsorbing material. A recent review of BPVE was written by: Z. Dai and A. M. Rappe, "Recent progress in the theory of bulk photovoltaic effect", Chem. Phys. Rev.4, 011303
P A T E N T Docket No. QS2090 (2023). DOI: 10.1063/5.0101513. Non-centrosymmetric crystals also exhibit the Pockels effect, in which the application of an electric field across the material, changes the index of refraction, which can be used for phase modulation of light. [00361] The BPVE produces a current flow in homogeneous non-centrosymmetric crystals, without the need for an internal electric field, like the one produced by doping gradients in conventional semiconductor pn-junctions. The lack of need for internal (or external) electric fields to extract photo-current, or to sense a photo-voltage, may lead to light-sensing devices without significant dark-currents, which are inevitable in conventional semiconductor pn- junction photodiodes. BPVE also enables light-sensing with topological semimetals, as has been pointed out in the following publication: T. Morimoto, N. Nagaosa, Topological nature of nonlinear optical effects in solids. Sci. Adv.2, e1501524 (2016). DOI: 10.1126/sciadv.1501524. Topological semimetals may provide light-sensing from the TeraHertz range to the visible range. [00362] In addition, the use of topological materials such as Weyl Semi-Metals enables the orbital photo-galvanic effect (OPGE) and the direct detection of the topological charge of the orbital angular momentum (OAM) of light. See for example the following reference: J. Lai et al., “Direct Light Orbital Angular Momentum Detection in Mid-Infrared Based on the Type-II Weyl Semimetal TaIrTe4”. Adv. Mater.2022, 34, 2201229. DOI: 10.1002/adma.202201229. [00363] The photoabsorption signal generated inside these materials needs to be handled differently from that generated inside conventional semiconductors. Topological insulators have metallic surface states and topological semimetals have bulk metallic states, and therefore pinning layers are not applicable. Also, in both cases extracting the photo- generated charges through an interface with a semiconductor, e.g., silicon, would be similar to flowing current from a metal to a semiconductor across a Schottky junction. Therefore, for these types of materials extracting photo-generated charges is best done with highly doped semiconductors or with direct metal (or silicide) contacts or with suitable work-functions. Consequently, extracting the photogenerated current through the photodiode doped region inside the typical CIS BSI pixel is not suitable. Direct ohmic contacts to one or all terminals of these materials and devices need to be made at the pixel level, as described elsewhere in this disclosure. The pixel level contact may be made with a contact trench through the thinned wafer substrate, from the bottom surface to the top surface of the substrate in CMOS devices. The fabrication of this trench is similar to the fabrication of deep trench isolation structures, but the trenches may have larger lateral dimensions, and consequently lower aspect ratios, which makes the fabrication easier. The end point at the top surface of the substrate needs to be a region/material that is a good electrical conductor such as a metal or a silicide that is connected
P A T E N T Docket No. QS2090 to an in-pixel MOSFET device. The pixel readout circuitry may be similar to that used for standard CIS pixels or for other photo-sensing materials, such as colloidal quantum dots or heterogeneously integrated InGaAs photodiodes, for example. [00364] FIG.8 is a schematic drawing with a 3D view of a CMOS BSI device with a 2x2 pixel array, in which pixels 125 and 126 have direct ohmic contacts to the epitaxial films 131 and 132, respectively, according to some embodiments of the disclosed technologies. Note some elements in FIG.8 are cut away to show internal details of the device. [00365] In the case of epitaxial film 131, the ohmic contacts are made to lateral surfaces, while for epitaxial film 132, the contacts are made to the bottom and top surfaces of the film. The ohmic contacts reach the CMOS circuitry made on the front side surface 101 of the CIS BSI substrate through deep trench contacts. The pixel and contact configurations shown are suitable for photodetectors incorporating topological insulators, or topological semimetals, or BPVE materials/devices, or metamaterials in which the mÍČIJôťĖè^ŕôŘıôÍæĖīĖťƅ^^̕^^ÍIJîϯĺŘ^ťēô^ŘôÍī^ŕÍŘť^ ĺċ^ ťēô^ îĖôīôèťŘĖè^ ŕôŘıĖťťĖŽĖťƅ^ ^̎
r) that have negative values. These pixels and contact configurations are also to be used with light-emitting layers and electro-optic modulator layers. [00366] Topological materials with nonlinear optical properties may be used for higher harmonic generation, such as second harmonic generation (SHG), third harmonic generation (THG), etc. These properties, i.e., photon frequency/energy up-conversion, may be taken advantage of by placing such types of topological material in tandem with a conventional LASER. In the context of the disclosed technologies, this tandem arrangement may be achieved in a very straightforward manner, by epitaxially growing the group-IV alloy or superlattice material that possesses the nonlinear optical properties directly on the LASER layers (for Vertical Cavity Surface Emitting Lasers – VCSELs) or side-by-side for Edge-Emitting LASERs. [00367] Patterning the epitaxially grown films into nanostructures is an option that enables the fabrication of devices with different features and properties than those made with bulk-like materials. This scenario is depicted in FIG. 9, which presents a schematic with a 3D view of a CMOS BSI device having a 2x2 array of pixels with epitaxial heterojunction layers grown/deposited on ultrathin substrates with different crystallographic orientations, comprising separate photoabsorption and charge multiplication (i.e., gain) regions, according to some embodiments of the disclosed technologies. Note some elements in FIG.9 are cut away to show internal details of the device. In pixel 126, both the photoabsorption region 132 and the gain region 141 are shaped into vertical nanowires. In pixel 125, only the photoabsorption region 131 is shaped into a vertical nanowire, whereas the gain region 141 is not. The subsequent epitaxial deposition of the pinning layer 118 over the nanowire structures of pixels 126 and 126 leads to
P A T E N T Docket No. QS2090 the formation of vertical nanowire core/shell structures. Pixels 127 and 128 are not patterned into nanostructures. The gain regions 131, 132, 133, and 134, which may be epitaxially grown on the silicon substrates 100, may incorporate the interface layer 137 to adjust band offsets. [00368] FIG.10 is a schematic drawing with a 3D view of a CMOS BSI device with a 2x2 pixel array with epitaxial heterojunction active regions and resonant enhancement structures, according to some embodiments of the disclosed technologies. These regions and structures may be used for photoabsorption or photoemission, and may include a stack of layers that are not epitaxially compatible with each other. Note some elements in FIG.10 are cut away to show internal details of the device. [00369] The CMOS BSI device may include a CMOS silicon wafer 100 having a front side 101 and a back side 102. At least one CMOS device may be fabricated on the front side 101 of the CMOS silicon wafer 100. In the example of FIG.10, there are eight CMOS devices, two for each pixel. For each pixel, the CMOS BIS device includes an NMOS device 155 and a PMOS device 156. The NMOS device 155 may include a threshold (VT) implant (n-type) 104, silicide 157, and an NMOS source/drain junction 161. The PMOS device 156 may include a threshold (VT) implant (n- type) 104, silicide 157, and a PMOS source/drain junction 162. [00370] The pixels may include at least one optoelectronic and/or thermoelectric device. In the example of FIG.10, the optoelectronic and/or thermoelectric devices may include pixels 125 and 126, which may include epitaxial films 131 and 132, respectively. [00371] The CMOS BSI device may include at least one electrical connecting region electrically coupling the at least one optoelectronic and/or thermoelectric device 119 and the at least one CMOS device 108. In the example of FIG. 2, one electrical connecting region may include a photodiode (PD) implant (n-type) 103 and an epitaxially deposited interface layer 117, and another electrical connecting region may include pinning layers 106 (p-type) and a p-type pinning layer 118. [00372] In Pixel 126, the stack comprises a first mirror layer 168.1, a first dielectric layer 165.1, a first contact layer 166 (for example n-type doped), an active layer 164 at the center of the stack, a second contact layer (for example p-type doped) 167, a second dielectric layer 165.2, and a second mirror layer 168.2. In pixel 125 the stack comprises a first mirror layer 168.1, a first epsilon-near-zero (ENZ) layer 163.1, a first contact layer 166 (for example n-type doped), an active layer 164 at the center of the stack, a second contact layer 167 (for example p-type doped), a second ENZ layer 163.2, and a second mirror layer 168.2. The ENZ layers enable deep subwavelength cavities. The regions identified as mirrors 168.1 and 168.2 may be formed by just
P A T E N T Docket No. QS2090 a metal film, or by a stack of layers forming Distributed Bragg Reflectors (DBR). The dielectric layers 165.1 and 165.2 may be silicon. [00373] The CMOS BSI device may include at least one electrical connecting region electrically coupling the at least one optoelectronic and/or thermoelectric device and the at least one CMOS device 108. In the example of FIG.10, each electrical connecting region may include silicide 157 and metal 159 to electrically connect contact layers 166 and 167 with NMOS device 155 and PMOS device 156, respectively. [00374] FIG.11 is a schematic drawing with a 3D view of a CMOS BSI device with a 2x2 pixel array for photoabsorption or photoemission (e.g., LED/LASER), according to some embodiments of the disclosed technologies. Note some elements in FIG. 11 are cut away to show internal details of the device. [00375] Pixel 125 has a vertical nanowire that may include three different epitaxially grown regions: an n-type doped cladding layer 166, an undoped active region 164, and a p-type doped cladding layer 167. The undoped active region 164 may comprise one or multiple quantum wells. Deep metal contacts 159, separate to the core and the shell regions, connect to the CMOS devices made on the top surface 101 of the substrate 100. [00376] Pixel 126 has a vertical core/shell nanowire structure, for photoabsorption or photoemission (LED/LASER). It comprises a core (active) region 169 with mirror layers 168.1 and 168.2 at both ends for resonant enhancement, and a shell region 170 that is grown on the side walls and bottom surface of the nanowire core region 169. The core region 169 may be an epitaxial film grown on a silicon substrate layer, and may be a homogeneous material, or an alloy, or a set of decoupled quantum wells, or a set of coupled quantum wells (i.e., superlattice). Deep metal contacts 159, separate to the core and the shell regions, connect to the CMOS devices made on the top surface 101 of the substrate 100. The regions 168 identified as mirror may be formed by just a metal film, or by a stack of layers forming Distributed Bragg Reflectors (DBR). [00377] Nano-structuring may be used to enhance the performance of these devices, through a reduction of the cross section of the photodiode, by patterning the photodiode to form a vertical nanowire photodiode, while still absorbing light from impinging over the entire pixel area. This may be accomplished by having an optical device (i.e., a pixel-level microlens) that is able to focus the light impinging on the entire area of the pixel into a deep subwavelength spot that is smaller than the cross section of the nanowire photodiode. This solution not only reduces the dark-current but also the junction capacitance of the photodiode, thereby enabling higher frequency response to modulated optical signals. Also, because the electric field of light may be very concentrated in a small 3D region of the photodiode, the overall thickness of the light
P A T E N T Docket No. QS2090 absorbing region of the photodiode may also be significantly reduced. This reduction in thickness (i.e., the optical path length inside the absorption region) may easily be a factor of 10x compared to the thickness needed in a conventional photodiode which is traversed by light propagating as a plane wave. For example, with a 1 μm x 1 μm pixel pitch, and a microlens capable of focusing the light beam to a vertical nanowire photodiode with a 20 nm x 20 nm cross section, the reduction in cross section of the photodiode, and therefore of dark-current is 1/0.0004, i.e., a factor of 2,500x. If the thickness of the absorption region may be reduced by a factor of 10x, then the overall dark-current may be reduced by a factor of 25,000x, i.e., more than four orders of magnitude, over a “bulk-type” photodiode made of the same material. Furthermore, a plasmonic layer may be formed on top of the epitaxial layer before patterning it into a nanowire, thereby enhancing the local electromagnetic field of light and improving the deep subwavelength sensing capability. The plasmonic layer may be a thin layer of a metal, typically Gold, Silver, Aluminum, or it may be a group-IV material, for example a superlattice, with a negative bandgap. [00378] Direct bandgap materials and devices enable a compound pixel, combining light- sensing and light-emission capabilities. A 2D array of such compound pixels may be very useful for LiDAR, because the light emitted would go through the same optics that gathers light for image-sensing, and also because it would be possible to perform free-space beam forming, with control in the time domain and/or frequency domain, and/or phase domain. This type of beam forming requires the pitch of the compound pixels to be small, i.e., of the order of half of the wavelength of light emitted from the compound pixel. For wavelengths such as 1.55 μm, this requires the compound pixel pitch to be on the order of 0.75 μm, while the commercial leading edge CIS BSI pixel pitch is 0.56 μm. See for example the following reference: https://semiconductor.samsung.com/us/newsroom/tech-blog/the-worlds-smallest-high- definition-pixels-how-samsung-electronics-developed-the-isocell-hp3-image-sensor/. [00379] It should be noted that only a full monolithic integration of LASERs on the back side of a CMOS substrate (with control circuitry on the front side) enables such a beam forming concept, in which compound pixels include light-sensing and light-emission. Heterogeneous integration of discrete light-emitters with CMOS are being pursued at a R&D level, in which light from a single light-emitter is split and waveguided into a 2D array, where beam forming is performed by pixel-level phase modulators. [00380] This may be accomplished with embodiments of the disclosed technologies more easily than with heterogeneous integration of discrete components made with non-CMOS compatible materials. Furthermore, the embodiment shown for pixel 126 of FIG.12 provides the ultimate solution, in which a single epitaxial growth run may grow the layers for a VCSEL and for
P A T E N T Docket No. QS2090 a vertical Electro-Optic Modulator (EOM), sharing a DBR region in-between them. In the fourth integration process described below, pixel 353.5 shows the fabrication of these devices as a single pixel in a 2D array of pixels. This is the ultimate solution in terms of size/compactness, perfect alignment between the two devices, minimal capacitance losses, etc. By having the VCSEL’s cavities optically coupled through topological waveguide to all other VCSELs in the 2D array, and by having individually biased (i.e., powered) EOMs, it is possible to perform free-space optical power addition from all VCSELs in the 2D array (as if they were a single VCSEL), as well as beam steering. The VCSEL + EOM devices shown in FIG.12, pixel 126, are patterned as vertical nanowires, but by patterning the dielectric layers surrounding these devices (not shown), it is possible to form a photonic crystal around the nanowire. [00381] FIG. 12 is a schematic drawing with a 3D view of a CMOS BSI device with a 2x2 pixel array for photoabsorption or photoemission, according to some embodiments of the disclosed technologies. Note some elements in FIG.12 are cut away to show internal details of the device. [00382] Pixel 125 has a vertical nanowire LED/LASER structure that may include a stack of layers that may not be epitaxially compatible with each other. The stack may include a first mirror layer 168.1, a first dielectric layer 165.1, an active layer 164 at the center of the layer stack (where light emission takes place), a left contact layer 166 (n-type doped) to the active region 164, a right contact layer 167 (p-type doped) to the active region 164, a second dielectric layer 165.2, and a second mirror layer 168.2. The dielectric layers 165.1 and 165.2 may be replaced with epsilon-near-zero (ENZ) layers 163.1 and 163.2 to form deep subwavelength cavities. The active region 164 may be a quantum dot made of a homogeneous material (such as a single element or an alloy), or a set of decoupled quantum wells, or a set of coupled quantum wells (i.e., superlattice). [00383] Pixel 126 may be a vertical nanowire of a stacked VCSEL+EOM, in which the VCSEL layers are epitaxially grown first and comprise a first mirror layer 168.1, a first half-cavity 165.1, an active region 164 (where light emission takes place), a left contact layer 166 (n-type doped) to the active region, a right contact layer 167 (p-type doped) to the active region, a second half-cavity 165.2, and a second mirror layer 168.2 of VCSEL that is shared with the EOM 171. The EOM 171 may include the active region 171 (where electro-optic light modulation takes place), the lateral metal contacts 159 to the active region 171, and a third mirror layer 168.3 (where light exits the EOM 171). The lateral contacts 166 and 167 may be made with the same metals or metals with significantly different work functions. The half-cavity regions 165.1 and 165.2 of the VCSEL may be made with dielectrics or with ENZ layers. The active region 164 at the center of the
P A T E N T Docket No. QS2090 VCSEL may be a quantum dot made of a homogeneous material (such as a single element or an alloy), or a set of decoupled quantum wells, or a set of coupled quantum wells (i.e., superlattice). The active region at the center of the EOM 171 may be a group-IV non-centrosymmetric crystal, which may be a superlattice shaped into a superlattice nanowire or a superlattice quantum dot. Deep metal contacts 159 to the active region 164 of the VCSEL, separate to the p-type and for n- type lateral layers 166 and 167 may connect to the CMOS devices made on the top surface 101 of the substrate 100. Deep metal contacts 159 to the EOM active region 164 connect to the CMOS devices made on the top surface 101 of the substrate 100 (not shown). The EOM may have thin silicon oxide on side walls facing metal contacts, to prevent large leakage current across the EOM material. [00384] FIG.43 is a schematic drawing with a 3D view of a CMOS BSI device with a 2x2 pixel array for photoabsorption or photoemission, according to some embodiments of the disclosed technologies. This device is similar to the device of FIG. 12, except in pixel 126 the integrated Laser+EOM is replaced with a LASER and photodiode. In the example of FIG.43, the pixel 126 includes the active region 188 of the photodiode, an N-type region 186 to extract electrons from the active region 188 of the photodiode, and a P-type region to extract holes from the active region 187 of the photodiode. [00385] 1.1 Process Integration Architectures [00386] All integration architectures disclosed herein may take advantage of current leading edge CIS BSI architectures. Standard CIS BSI technology has been exclusively developed and optimized for image-sensing, across the wavelength spectrum absorbed by silicon. Because of its high performance and high-volume manufacturing, it may be the platform onto which new image-sensing capabilities presented here are added, namely sensing across the entire IR range (NIR, SWIR, MWIR, LWIR, VLWIR, FIR), and also in the UV and TeraHertz ranges, by utilizing a variety of different heterojunction epitaxial layers and device types, making use of different device physics. In addition to image-sensing, the aforementioned variety of epitaxial layers and device types may also include layers and devices for light-emission, as well as other devices including light-modulators, waveguides, higher harmonic generators, etc. [00387] In CMOS technology, the common definition of Front-End-Of-Line (FEOL), is the set of process steps performed before executing the set of process steps to fabricate silicide and multiple-level metal interconnects, the latter being what is commonly defined as Back-End-Of- Line (BEOL). [00388] For all process flows based on bulk wafers, the epitaxial growth on the back side of a wafer may only be done after the wafer has been thinned, as is standardly done, before the
P A T E N T Docket No. QS2090 fabrication of color filters and microlenses. Consequently, if the epitaxial growth was to be performed early in the fabrication of CMOS devices (on the front side of the wafer), before completion of FEOL, then this flow would require the execution of multiple FEOL process steps on a wafer that has already been thinned. This may be done by bonding the thinned wafer to a temporary mechanical substrate (usually called a wafer carrier). [00389] Although the epitaxial films may be composed of just silicon with particular doping profiles defined by dopant incorporation during the epitaxial growth, the maximum benefit of growing epitaxial films on the back side surface of a CMOS wafer may be obtained when the epitaxial layers comprise, not only doping impurities, but also other materials that may be grown pseudomorphically on silicon surfaces. Among these, the easiest ones are composed of group-IV elements, as part of random alloys, and/or ordered alloys, and/or quantum wells, and/or superlattices. Consequently, the epitaxial films may have some amount of strain, which may place restrictions on the maximum thickness of the epitaxial films, and on the temperature budget after the epitaxial growth. However, with judicious chosen composition profiles, it is possible to achieve strain-balance, in which case the limitation of a small critical thickness is removed. A strain-balanced crystalline cell comprises multiple atomic planes, in which some are tensile strained while others are compressively strained, such that the overall crystalline cell is nearly lattice-matched to the lattice constant of the surface on which it is pseudomorphically grown, and consequently has a very large critical thickness. [00390] The insertion of the epitaxial layers in the fabrication flow may take place at different stages, depending on a variety of factors, one of the most important being the thermal budget during and after the epitaxial growth (until the end of processing). The maximal thermal budget for CMOS processing depends on the CMOS technology nodes, which may be linked to specific device designs and technologies, such as planar CMOS, FinFET CMOS, Gate All Around (GAA) Nanosheet CMOS, Vertical Transport CMOS, etc. The historic trend has been a continued reduction in the thermal budget with each new generation of CMOS device architecture and technology. [00391] However, CIS uses planar CMOS technology for the Transfer-Gate and other transistors, in which, the doping profiles are made by ion implantation and rapid thermal annealing at high temperatures. However, it is also possible to make doping profiles by ion implantation and annealing at low temperature, as was demonstrated in the following reference: K. Kanemoto et al., “Minimization of BF2+-Implantation Dose to Reduce the Annealing Time for Ultra-Shallow Source/Drain Junction Formation below 600°C” 1998 Jpn. J. Appl. Phys.371166. DOI: 10.1143/JJAP.37.1166.
P A T E N T Docket No. QS2090 [00392] Consequently, an integration architecture that has the fabrication of planar CMOS devices in wafers after the epitaxial growth of heterojunction films strained to silicon is feasible if low temperature annealing is adopted. [00393] The thermal budgets are also directly dependent on the equipment and the physio-chemical processes used to process the wafers. An important example is the thermal budget related to the epitaxy of group-IV materials, such as SiGe and SiGeC alloys, using single- wafer chemical vapor deposition (CVD) reactors, which are the most common type of epitaxial equipment and processes used in production of leading-edge CMOS and SiGe (and/or SiGeC) BiCMOS. For decades, this equipment and processes required the preparation of the surface of a silicon wafer with a high temperature anneal (for example around 900 °C), before performing the epitaxial growth of these alloys. With the need to have very sharp doping profiles and control of layer thickness in FinFETs and GAA Nanosheet FETs, the epitaxial growth equipment and processes evolved to have in-situ cleaning chambers in cluster tools, which enabled a drastic reduction in temperature for the surface cleaning and preparation to less than 200 °C. Similarly, the temperature during epitaxial growth has also been lowered, partly helped by the use of different precursors that enabled maintaining the growth rates at lower temperatures. [00394] The advances made towards low-temperature processing, before, during, and after, epitaxy of group-IV materials, are also useful for low-temperature treatment of active area surfaces, such that they become mono-terrace surfaces. For mono-terrace active areas isolated with standard methods, such as shallow trench isolation, there are edges at the perimeter of the active area, but within the top surface of the active area there is only one terrace and therefore no steps between terraces. Mono-terrace surfaces are the ideal starting point for the epitaxial growth of complex heterojunction profiles, and in particular short-period superlattices. With self- limiting epitaxial growth, progressing in a layer-by-layer fashion, the growth front should continue to be a mono-terrace. [00395] A path being pursued to increase device density (e.g., CMOS circuitry) is 3D sequential integration of processed wafers. This consists in the fabrication, i.e., monolithic integration, of additional layers of CMOS devices on top of a first layer of CMOS devices, the latter having already at least one metallization layer, designated as an intermediate BEOL layer (iBEOL). This requires processing done at temperatures below 500 °C, including the epitaxial growth of Si, Si
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y alloys, including highly doped p-type and n-type layers. The following reference provide examples of such processing: C. Fenouillet-Beranger et al., "A ^ôŽĖôſ^ĺċ^[ĺſ^^ôıŕôŘÍťŪŘô^^ŘĺèôŜŜ^aĺîŪīôŜ^[ôÍîĖIJČ^^ŕ^ ťĺ^ ťēô^>ĖŘŜť^ ^Ѷ^^^^е^^^^īÍIJÍŘ^>"^iI^
P A T E N T Docket No. QS2090 CMOS Devices for 3-D Sequential Integration", IEEE Transactions on Electron Devices, vol.68, no.7, pp.3142-3148, July 2021, DOI: 10.1109/TED.2021.3084916. [00396] Furthermore, there are experimental results indicating that, at least for certain group-IV materials, there are precursors that enable epitaxial growth at even lower temperatures, in the range of 160 °C to 250 °C, as reported in the following reference: Chi Xu, Ting Hu, Dhruve A. Ringwala, et al., “Gas source molecular epitaxy of Ge
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10 and Ge
5H
12 hydrides”, J. Vac. Sci. Technol. A 39, 063411 (2021); DOI: 10.1116/6.0001253. [00397] The three process integration architectures described below provide alternative frameworks for the growth and patterning of epitaxial layers in the back side of CIS BSI wafers. These process integration architectures insert said epitaxial growth at three very distinct points in the process flow of a CIS process. However, within those frameworks there are several options for the epitaxial growth itself: blanket versus selective, and if selective, with or without lateral overgrowth. The choice of the type of epitaxial growth impacts the 3D structure of the hard mask for the epitaxial growth, and also the patterning of the epitaxial films after the growth. The choice of the type of epitaxial growth is constrained by the spacing between openings in the hard mask for the epitaxial growth, and also by the existing topography on the surface. Selective epitaxial growth (SEG) may be performed in scenarios in which blanket epitaxial growth cannot, and therefore SEG is the preferred method, and the one shown in the figures for the process flows. [00398] In the first process integration architecture, the epitaxial growth, and optional bonding of ultrathin substrate layers with different crystallographic orientations, on the back side of the wafer, is performed before processing of CMOS devices on the front side of the wafer. [00399] In the second process integration architecture, the epitaxial growth, and optional bonding of ultrathin substrate layers with different crystallographic orientations, on the back side of the wafer, is performed after FEOL processing of CMOS devices on the front side of the wafer, but before processing of BEOL, and even before silicide, on the front side of the wafer. [00400] In the third process integration architecture, the epitaxial growth, and optional bonding of thin layers with different crystallographic orientations, on the back side of the wafer, is performed after FEOL and BEOL processing of CMOS devices on the front side of the wafer. This integration architecture is simpler to execute, has fewer risks regarding the integrity of the epitaxial heterojunction layers, and has minimal interaction (if any) with the processing of standard CIS BSI wafers. [00401] The fourth process integration architecture shares most of the features of the third process architecture, and the main difference is the fabrication of direct metal contacts
P A T E N T Docket No. QS2090 from the CMOS devices on the front side of the wafer to device layers fabricated on the back side of the wafer. This architecture is preferred to contact LEDs, LASERs, as well as topological insulators, topological semimetals, and non-centrosymmetric crystals exhibiting the Bulk PhotoVoltaic Effect (BPVE). [00402] 1.2 Process Integration of Multiple Crystallographic Orientation Substrates [00403] The availability of surfaces with more than one crystallographic orientation may be achieved in multiple ways. For sake of simplicity, in the process architectures and flows described herein, only one method of making multi-orientation surfaces is described, in which ultrathin layers with different surface orientations are directly bonded at low temperature onto the back side of the wafer. The bonding joins semiconductor surface to semiconductor surface, without interfacial dielectric layers. Subsequently, the ability to perform epitaxial growth on surfaces with different orientations requires the etching of one or more of these bonded layers with different orientations to uncover the buried surface with the desired (different) orientation. For the cases in which the epitaxial growth of the device layers is made on the last crystallographic surface, the complete stack of additional substrate orientation layers, and associated marker layers for etching, should not cause any significant impact on electron and/or hole transport crossing this stack of layers to reach the photodiode implant in the wafer substrate. [00404] In order not to rely on etching selectivity between different crystallographic orientations of the same material (silicon), prior to the bonding of each layer with a particular orientation, an ultrathin marker layer may be grown, composed of Ge, or SiGe, or SiGeC, just a few nanometers thick (less than 2nm for example), with sufficient Ge and/or Ge and C percentages, such that there is a large enough chemical contrast, for etching purposes, with respect to silicon. With these features in place, a highly selective etch between Si and the Ge or SiGe or SiGeC layer, may be obtained. Likewise, such an arrangement also allows for a highly selective etch of Ge or SiGe or SiGeC with respect to silicon. This type of highly selective dry etch is a key process step for the fabrication of Gate All Around (GAA) Nanosheet MOSFETs, and consequently is a standard process step in high-volume manufacturing of GAA Nanosheet CMOS technology. The growth of the marker layers for etching may be done either on the wafer surface (or last ultrathin substrate bonded to the surface) or on the surface of the substrate with new orientation to be bonded, before it is processed into an ultrathin film. [00405] Standard CIS BSI has n-type photodiodes, with p-type pinning layers and NMOS pixel transistors, and consequently electrons are the type of charge carrier that needs to travel from the epitaxial layer across the ultrathin marker layers positioned between the different
P A T E N T Docket No. QS2090 crystallographic orientation layers. It is well known that SiGe layers, even with large Ge concentrations, do not pose a significant potential barrier, with respect to silicon, for electrons to travel across them, and the same may be said for SiGeC with low C concentration. This is the reason why SiGe and SiGeC layers may be used in the Base of SiGe (SiGeC) n-p-n HBTs in BiCMOS. For p-type photodiodes, with n-type pinning layers and PMOS pixel transistors, holes are the type of charge carrier that needs to travel from the epitaxial layer across the SiGe (or SiGeC) interfacial layers positioned between the different crystallographic orientations. A smooth crossing of these interfacial layers for holes may be achieved through the judicious choice of chemical composition (i.e., Ge and C content) and layer thickness, such that even if a very narrow quantum well for holes exists, the first quantized level in said quantum well has an eigenvalue that is roughly aligned with the band edges of silicon, and thus holes are not captured by the quantum well. [00406] The uncovering of the surfaces with multiple orientations for simultaneous epitaxial growth on all different orientations, may be done in at least two alternative options: [00407] Option #1. After the bonding of the last layer with a different surface orientation, and before the epitaxial growth of the actual device layers, perform patterning of the last bonded surface orientation layer, to uncover the surface of the surface orientation layer immediately underneath it, selectively etch silicon, stopping on the ultrathin marker layers underneath it (which have a different surface orientation). The selective etch of the ultrathin marker layers may be done at this stage, or later, just before the epitaxial growth of the actual device layers on that surface. In the process flows described herein, it is be assumed that the selective etch of the marker layers is done just before the epitaxial growth of the actual device layers, but the marker layers are not shown in the drawings. The patterning and selective etches may be repeated until the last surface orientation, i.e., original wafer substrate, is uncovered. Once all the surface orientations for epitaxial growth are uncovered, then deposit a silicon oxide layer that should be as at least as thick as the thickest device layer to be grown, followed by the deposition of a thin silicon nitride layer. The next steps are patterning steps to define the epitaxial growth of actual device layers on different pixels, which may have different surface orientations. This option enables the easy selection of areas, which may have different surface orientations, and that are supposed to receive simultaneously the deposition of the exact same epitaxial active layers. [00408] Option #2. After the bonding of the last layer with a different surface orientation, deposit a silicon oxide film with a thickness that is at least as thick as the thickest device layer to be epitaxially grown. Deposit a thin silicon nitride layer. Perform patterning and etch of nitride and oxide, stopping on the last bonded silicon layer. This may be followed by epitaxial growth of
P A T E N T Docket No. QS2090 active layers, or it may be followed by selective etch of multiple silicon and marker layers, until the desired surface for the epitaxial growth of the actual device layers is reached. This option also enables the easy selection of areas, which may have different surface orientations, and that are supposed to receive simultaneously the exact same epitaxial active layers. With this option, additional patterning steps may expose all surfaces selected to receive the same epitaxial device layers, which may include multiple surface orientations. [00409] The uncovering of the surfaces of different orientations for epitaxial growths which are separate for each orientation may be done as described next. Again, for sake of simplicity, it is assumed that there is a total of three different crystallographic orientations, (00 1) substrate, (110) first bonded layer, and (111) second bonded layer. The order in which the different surface orientations are exposed, and the separate epitaxial growths are executed, is arbitrary. [00410] After the bonding of the last layer with a different surface orientation, deposit a silicon oxide film with a thickness that is at least as thick as the thickest device layer to be epitaxially grown. Deposit a thin silicon nitride layer. [00411] For epitaxial growth on the (111) crystallographic surface layer, the patterned etch step should remove the dielectric layers, and expose the (111) layer surface. After surface preparation, execute the epitaxial growth of layers. [00412] For epitaxial growth on the (110) crystallographic surface layer, the patterned etch step should remove the dielectric layers, and the stack of layers associated with (111) surface and associated marker layers, exposing the (1 1 0) layer surface. After surface preparation, execute the epitaxial growth of layers. [00413] For epitaxial growth on (001) substrate surface, the patterned etch step should remove the dielectric layers, and the stack of layers associated with (1 1 0) and the (1 1 1) surfaces and associated marker layers, exposing the (0 0 1) substrate surface. After surface preparation, execute the epitaxial growth of layers. [00414] An “Epitaxial Module” comprises several process steps, before and after the epitaxial growth of the layers that may form the device regions. There may be several variations on a number of details surrounding these steps, starting with the hard masks for the epitaxy, which may be a stack of dielectrics, with the possibility of engineering parameters such as the thickness of each dielectric, the lateral dimensions and geometry of each dielectric in the stack, etc. The epitaxial layers may be meant for a photoabsorption region, a photo-emission region, an electro-optic modulator region, a waveguiding region, a light-confinement region, a light- reflection region, etc., in which case the specific composition and/or doping profiles may be
P A T E N T Docket No. QS2090 different for each device type, and there may be multiple epitaxial growths on one or multiple surfaces with the same or different crystallographic orientations. [00415] The complexity of the steps prior to the epitaxial growth depends on several factors, such as how many devices to be made, how many epitaxial growth steps are to be performed for each device, and how many surfaces need to be available for each epitaxial growth run, etc., as well as requirements regarding etching into the substrate (back side of wafer) prior to epitaxy, along with the dimensions and complexity of the structures to etch into the substrate. Likewise, the complexity of the steps after the epitaxial growth also depend on how many epitaxial growth steps are to be made, how many surface orientations need to be available, and possible requirements to etch into the epitaxial films after epitaxy, along with dimensions and complexity of structures to etch into the epitaxial films. [00416] The lateral dimensions of the opening in the hard mask for epitaxy may be very close to those of the corresponding pixel area, and after epitaxy, it is possible to pattern the epitaxial film into nanostructures, such as lateral and/or vertical nanowires, quantum dots, etc. The patterning of the hard mask for epitaxy may also have the desired final geometric shapes and nanoscale dimensions. [00417] An additional option for the epitaxial growth includes SEG of layers up to the surface of the hard mask for epitaxy, followed by SEG with lateral overgrowth, to make a T-shaped structure. In this case the initial opening in the hard mask for epitaxy would have to be substantially smaller than the pixel size, such that the regions produced by lateral overgrowth would still be within the pixel dimensions. For epitaxy of layers with specific heterojunction and/or doping profiles, for example a group-IV superlattice, the lateral overgrowth may produce the same profiles in 3D, thus producing the same band structure and optoelectronic properties omnidirectionally. [00418] An additional option for the epitaxial growth includes SEG of layers inside and up to the surface of the hard mask for epitaxy, followed by removal of the hard mask and additional epitaxial growth on the sidewalls of the first epitaxial layers, thereby enabling core-shell radial heterojunction compositions and/or doping gradients. The outer layer (shell) may be P-type doped and therefore may be electrically connected to a P-type pinning layer of the whole pixel, while the central part (the core) may be n-type doped and electrically connected to the N-type doping in the substrate (i.e., the standard CIS photodiode). The diameter of the initial pillar determines whether it is a nanowire or a microwire, with the associated differences in optoelectronic properties, and ease of manufacturing.
P A T E N T Docket No. QS2090 [00419] The epitaxially grown films may also incorporate “sacrificial layers” which may be subsequently etched away. The space left behind by this etching may not be filled, or it may be filled with dielectrics, or metals, or a combination of dielectrics and metals, depending on the desired functionality. This processing enables the fabrication of a variety of structures, such as optical cavities with bottom and top metal mirrors, 3D photonic crystals, etc., which make possible the fabrication of resonant structures, for light emission, and/or light absorption, and/or electrooptic light modulation. At the end, these structures may form a stack of layers that are not epitaxially compatible with each other, but that are possible to fabricate through the replacement of “sacrificial layers” that are compatible with the epitaxial growth of the key active layers. [00420] The thickness of the CIS BSI substrate to achieve sufficiently good quantum efficiency of absorption of visible wavelengths is typically around 3 microns. It may be several microns thicker for the purpose of improving light absorption in the NIR range. Consequently, the distance between the back side where light penetrates the substrate and the front side surface of the wafer where the CMOS devices are fabricated, exceeds the thickness of the epitaxial layers for a conventional cavity and Distributed Bragg Reflectors (DBRs) for the 1550nm wavelength, for example. The epitaxial growth on the back side of the CIS BSI substrate of a set of layers for DBR + Cavity + DBR may result in an undesirably large topography. [00421] The topography problem may be solved by first etching away a significant thickness of the CIS BSI substrate, before the epitaxial growth of the set of layers for DBR + Cavity + DBR. The etching of the active area into the substrate would restrict the surface orientation (for the epitaxial growth) to be that of the substrate, typically the (001) orientation. The feasibility of this integration scheme depends on whether the substrate surface after etching is suitable for subsequent epitaxial growth. Also, if this etch and epitaxial growth were to take place in arbitrary locations within the 2D array of compound pixels, additional constraints may arise from the pixel pitch and lateral dimensions of the resonant cavity-enhanced device. [00422] The fabrication of integrated LASERs may be done with resonant structures that may have subwavelength dimensions, such as cavities made of the aforementioned ENZ layers, and which are described in this disclosure. [00423] 1.3 Integration of New Photoabsorption Devices [00424] In addition to the type of growth, the choice of the epitaxial layer structure also determines the processing before and after the epitaxial growth. For example, for photo- absorbing devices, the epitaxial layers may consist of just a gain region that is fairly thin, for
P A T E N T Docket No. QS2090 example less than 200 nm thick, and in which case most of the photoabsorption takes place in the bulk silicon, underneath the epitaxial layers. [00425] In a first scenario, the epitaxial layers may consist of a photoabsorption region, preferably with a direct bandgap, to allow high quantum efficiency of photoabsorption. [00426] In a second scenario, the epitaxial layers combine a photoabsorption region and a gain region placed between the substrate and the epitaxial photoabsorption region. [00427] In a third scenario, the photoabsorption regions and/or gain regions are not just band-structure engineered in the vertical direction, i.e., the direction of epitaxial growth, but also in other directions, including through lateral etching and/or epitaxial lateral overgrowth, or through nanostructured regions which may take the form of vertical or lateral wires (nanowires or quantum-wires) and/or dots (quantum-dots), and/or antidots. [00428] The number of possible variations and permutations between all factors is too large for all to be represented in the drawing figures, and for that reason, the drawings for the process flows present only a few particular sets of factors. [00429] In the case of a 2D-array of pixels, if there is only one epitaxial growth of device layers, for example, to enable SWIR sensing, for a fraction of all pixels, or for all pixels in the array, then that growth is going to take place on a flat surface, and the restrictions on the hard mask for epitaxy are few, and the epitaxial growth may be selective or blanket. On the other hand, if multiple epitaxial growth runs are to take place in adjacent pixels, then the topography present after the first growth run may make blanket growth more difficult or impossible. Consequently, in a scenario of multiple epitaxial growth runs, only Selective Epitaxial Growth (SEG) is practical, and for this reason it is the one used in the figures. Also, in the process flows and drawings, it is assumed that Deep Trench Isolation (DTI) executed from the back side was done before the epitaxial growths. Although DTI may also be executed after the epitaxial growth, executing it before the epitaxial growth helps in keeping the baseline CIS BSI process uncoupled from the process steps associated with the epitaxial growth module, which includes some steps before and some steps after the epitaxial growth itself. [00430] The DTI structures are for the isolation, electrically and optically, of adjacent pixel cells. This is an issue for the fabrication of 2D arrays of any type of independent/isolated (electrically and optically) optoelectronic devices, not just CIS pixels. As already mentioned, in current state-of-the-art CIS BSI technology, these trenches are fabricated from the back side, with increasingly higher aspect-ratios as pixel size/pitch gets smaller, but the height of the pixel, i.e., the thickness of the wafer after thinning, remains constant in order to keep the same quantum efficiency of absorption. Although there are methods to increase the optical path inside
P A T E N T Docket No. QS2090 the same thickness of silicon, for example, with features that enhance the scattering of light inside the volume of the pixel, so far these techniques do not completely compensate scaling down the thickness of silicon to the same extent by which pixel size/pitch has been scaled down. [00431] Pinning regions/layers for CIS BSI technology may be fabricated at low- temperatures with in-situ doped epitaxial silicon layers deposited at low temperature on the side walls of trenches and on the back surface of the wafer. They may also be made with the low- temperature deposition of dielectric films with high permittivity (i.e., high-k dielectrics) which contain a high density of negative fixed charges, thereby inducing positive charges in the silicon near the surface of the trench. [00432] In addition, the deposition of a metal film inside the trenches, encapsulated by thin dielectric layers, provides optical isolation by reflecting back to the same pixel those photons arriving with large angles of incidence. These process steps and features may be equally applied to isolate pixels with the epitaxial films of embodiments of the present invention. [00433] Electrically conducting pinning layers may also be fabricated for photodiodes comprising epitaxial layers that are patterned into mesa-type structures. This concept was described for several variations of FSI photodiodes/pixels comprising epitaxial layers in U.S. Patent No. 9,640,616, “Superlattice materials and applications”, figures 8D-8R, figures 9A-9J. This alternative method to fabricate an electrically conducting pinning layer by growing/depositing an epitaxial pinning layer enables, not only in-situ doping during the growth/deposition of the pinning layer, but also for the pinning layer to have a chemical composition that may be adjusted to form a heterojunction at the external surfaces of the mesa- type structures, which may be useful to optimize the performance of the photodiode. [00434] The epitaxially deposited pinning layer may incorporate multiple layers with different compositions, with layer-by-layer control of the composition. This may be achieved with self-limited growth of each atomic plane, which is sometimes designated as digital epitaxy. For example, the composition of the first epitaxially deposited layer may be selected to optimize the electric field in the photoabsorption region surrounded by the pinning layer, and the composition of the last epitaxially deposited layer, for example silicon, may be selected to completely encapsulate all non-silicon materials, thereby facilitating a good passivation by a dielectric, such as silicon oxide or silicon oxynitride, subsequently grown or deposited also at low temperature. [00435] It should be noted that recent advances in doping of group-IV materials has enabled extremely high doping concentrations, as exemplified in the following reference: H. Xu et al., “300 mm Wafer-scale In-situ CVD Growth Achieving 5.1×10
-10 ˣ-cm2 P-Type Contact Resistivity: Record 2.5×10
21 cm
-3 Active Doping and Demonstration on Highly-Scaled 3D
P A T E N T Docket No. QS2090 Structures”. 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits). DOI: 10.1109/VLSITechnologyandCir46769.2022.9830220. [00436] To put these doping concentrations in perspective, if one assumes that active doping corresponds to all doping, (i.e., all dopants are electrically active), a doping concentration of 2.5×10
21 cm
-3 represents 5% of silicon’s atomic density (~5x10
22 cm
-3). Alternatively, the pinning layer might have optoelectronic properties such that doping is not required, for example by epitaxially growing a pinning layer that is a semimetal with a suitable band alignment or Schottky barrier height with respect to the epitaxially grown photoabsorption region. [00437] Techniques currently used to increase the photoabsorption in bulk silicon, such as texturing the surface of the photodiode, may also be applied to the epitaxially grown photodiode layers of the disclosed technologies. In embodiments of the present invention, the texturing of the photodiode’s epitaxial layers would take place before the epitaxial deposition of the pinning layer. [00438] For epitaxial layers that comprise efficient photoabsorption layers for the wavelength ranges of interest, the thinned silicon substrate of the wafer does not contribute to photoabsorption, and consequently may be much thinner than the standard thicknesses, which are typically 3 μm or thicker. In the limit, the thinned CIS BSI substrate, may be just a few hundreds of nanometers thick, or less, depending on the CMOS technology/generation fabricated on the front side of the wafer. Thinning the wafer to much thinner levels, for example less than 1μm, apart from decreasing charge carrier collection times, has the advantage of making the deep trench isolation process much easier in that it may reduce the aspect ratio of the trenches, and thus make it easier to etch and fill the trenches with other materials. In turn, this makes it easier to decrease the pixel’s lateral dimensions, i.e., the pixel pitch. Decreasing the thickness of the active layers, while achieving a desired quantum efficiency of absorption, also improves radiation hardening of the photosensitive regions. [00439] The above discussion applies to any wavelength range, including the visible range, provided that the epitaxial film epitaxially grown on the back side of the wafer has a larger coefficient of absorption than silicon for the wavelength of interest, including the visible range, while not changing significantly the dark current. This may be achieved with epitaxially grown materials with positive direct bandgaps whose magnitude is similar to, or larger than, the bandgap of silicon. Consequently, the disclosed technologies enable more aggressive lateral downscaling of pixel dimensions (i.e., smaller pixel pitch) by reducing the aspect ratio of the isolation trenches between adjacent pixels, i.e., by reducing the pixel height, i.e., the distance between the top surface of the wafer, where the Transfer-Gate transistors are made, and the
P A T E N T Docket No. QS2090 back side surface, where light penetrates the photoabsorption regions. An example of a material that is nearly lattice matched to silicon, is the ordered alloy Ge
2Sn
2C which has a direct band-gap of 0.885 eV when strained to Si (001). [00440] FIG.27A is a plot of the 20-atom cell used to calculate ab-initio both the band structure and the coefficient of absorption. The structural relaxation for an epitaxial pseudomorphic condition, produced a lattice constant along the direction of epitaxial growth of 5.45378 Å. The ratio of this value in relation to silicon is 5.45378 / 5.43100 = 1.0042, i.e., this material is almost perfectly lattice matched to silicon. In this plot the “c” axis is the direction of epitaxial growth, while “a” and “b” are the in-plane directions parallel to the substrate surface. [00441] FIG.27B is a plot of the band structure calculated with a pseudo-potential plane-wave code, using a pseudo-potential for Sn that includes 3d electrons, which if not included would produce a very different, and erroneous, result. The Tran-Blaha exchange and correlation potential (F. Tran, P. Blaha, Phys. Rev. Lett., 102, 226401, (2009).DOI: 10.1103/PhysRevLett.102.226401) was used with the c-parameter fixed at 1.04, instead of internally calculated. These are the parameter settings for which the calculations produce results very close to experimental data for Si, Ge, Si
1-xGe
x and Si
1-yC
y alloys, as shown in C. Augusto, L. Forester, "Novel Si–Ge–C superlattices and their applications”; Solid- State Electr., Vol.110, 2015, pages 1-9, DOI: 10.1016/j.sse.2015.01.019, and also for Sn. In this plot the arrows point to the 0.885 eV direct band-gap at the Gamma point. Using the Local Density Function (LDA), the band-gap is also direct but has a magnitude of 0.617 eV. [00442] 1.4 Integration of Photo-Emission Devices [00443] As already mentioned, the epitaxial growth enables the fabrication of group-IV alloys, and/or quantum-wells, and/or superlattices with direct bandgaps on the back side of CIS BSI wafers. These materials may be used for light absorption with much higher efficiency than indirect band-gap materials, such as Si or Ge or alloys such as Si
1-x-yGe
xC
y. The slope of the coefficient of absorption of some superlattices with direct bandgaps is comparable with the slope of the coefficient of absorption of reference III-V materials, such as GaAs, InP, and InGaAs, and therefore the gain factor for light emission should be also comparable. This means that LEDs and LASERs made with these group-IV alloys, and/or quantum-wells, and/or superlattices direct band-gap materials, should have high efficiency, comparable to the efficiency of similar devices made with the aforementioned III-V reference materials. The fabrication of LASERs on the back side of a CMOS wafer presents novel possibilities in terms of the fabrication of vertical and lateral cavities with high quality factors, and monolithic integration with light-sensing devices, light- modulating devices, light-waveguiding devices, nonlinear photonic materials, optical combs/microcombs, photon frequency conversion devices, etc., on the same focal plane.
P A T E N T Docket No. QS2090 [00444] The processing for photoemission devices comprises the active layer for light emission, and may also comprise the formation of resonant structures along the vertical direction, such as conventional Fabry-Perot cavities with dielectric mirrors, or photonic crystal cavities, or metaldielectric cavities with nanoscopic sizes, or cavities formed by bound states in the continuum (BICs), combined with in-plane photonic bandgaps resulting in 3D light confinement, also known as miniaturized BICs (mini-BICs). See for example the following reference: Y. Ren, et al., “Low-threshold nanolasers based on miniaturized bound states in the continuum”, Sci. Adv. 8, eade8817 (2022). DOI: 10.1126/sciadv.ade8817. [00445] The patterning of epitaxial layers forming quantum wells (with band offsets of type-I or type-II or type-III), into nanowires, forms quantum-dots embedded in the nanowire, which are prime candidates for single-photon emitters at room-temperature, in particular, when combined with engineered dielectric environments, is discussed in the following reference: Y. Kan, S. I. Bozhevolnyi, Advances in Metaphotonics Empowered Single Photon Emission. Adv. Optical Mater.2023, 11, 2202759. DOI: 10.1002/adom.202202759. [00446] The patterning of the epitaxial layers and/or the fabrication of photonic metamaterials, or metasurfaces, generate topography and consequently, a planarization step may be needed between the fabrication of different types of devices. Planarization, consisting of a low-temperature deposition of dielectrics followed by chemical mechanical polishing (CMP), is a mature technology, widely used in FEOL and BEOL in CMOS. [00447] If the thickness of the silicon CSI BSI bulk after thinning is decoupled from the light absorption requirement, then other engineering parameters may be optimized. For example, the thickness of the thinned wafer may be optimized for the purpose of making resonant structures (e.g., a Fabry-Perot cavity), in which this thickness would roughly correspond to the length of a half-cavity, while the thickness of the epitaxial layers would approximately correspond to the length of the other half-cavity. Such types of cavities may be used for Resonant Cavity-Enhanced Photodiodes (with or without gain) and for Vertical Cavity Surface Emitting LASERS (VCSELs). [00448] Conventional VCSELs made of III-V materials are Fabry-Perot type LASER systems with distributed Bragg Reflectors (DBRs) placed at each end of the cavity. DBRs consist of a series of layers with different refractive indices, in which the thickness of each layer is the optical length of a quarter of the emission wavelength. DBRs are epitaxially grown using semiconductor material combinations with sufficiently different refractive indices, such as GaAs and Al
xGa
1-xAs.
P A T E N T Docket No. QS2090 [00449] In conventional III-V VCSELs, the cavity material and the DBR materials must be epitaxially compatible with the materials where light emission occurs. This places severe constraints on the composition of the layers forming the cavity and DBRs. For DBRs, this is detrimental because it is desirable to have the largest possible contrast in refractive index between the quarter wavelength pairs forming the DBR. The larger that contrast, the fewer pairs are needed to achieve a certain reflectivity. Typically, DBRs are much thicker than the cavity layers, and reducing their thickness reduces the time needed for their epitaxial growth, increases yield, decreases topography, etc. The same problem occurs with group-IV alloys. [00450] Consequently, it would be extremely beneficial to VCSELs to enable cavity and DBR materials with very large differences in index of refraction, which may not be epitaxially compatible with the light-emitting layers. The technology developed for Nanosheet Gate All Around (GAA) MOSFETs provides a solution that enables the fabrication of cavities and/or DBRs with materials that are not epitaxially compatible with silicon and that don’t need to be monocrystalline, in contrast to the light emitting layers that are pseudomorphically grown on silicon surfaces. The fabrication of Nanosheet GAA MOSFETs includes the epitaxial (pseudomorphic) growth of long-period superlattice layers, alternating Si and SiGe, for example. Highly selective dry etch of Si against SiGe and/or of SiGe against Si allows the highly selective removal of layers of a particular composition from the superlattice stack. The goal is to include sacrificial layers during the epitaxial growth of the layers that may be used as channel materials of the MOSFETs. The empty space left after the selective etch of the sacrificial layers may then be filled with materials that are not possible to be epitaxially incorporated into the stack, including the High-K gate dielectrics, SiO
2, Si
3N
4, as well as the gate metal electrodes and silicides, provided that all processing is performed at low temperatures, e.g., less than 500 °C. The epitaxial stack may include layers with additional compositions whose etching would be selective against the etch of Si and SiGe, and which would be resistant against the etch of Si and SiGe. For example, the layers may have compositions that include Carbon and Tin, and/or Carbon and Lead, which are nearly lattice-matched to silicon. The existence of a third layer in the long-period superlattice allows for additional engineering options regarding the materials for cavity and DBRs. Depending on the exact compositions and strain levels of the sacrificial layers, the thickness of each layer may be tens to hundreds of nanometers. [00451] This new method of fabricating cavities and/or DBRs offers the possibility to make the total thickness (height) of the full VCSEL (light-emission layers, cavity and DBRs) to be much smaller (for the same wavelength) than the total thickness of conventional III-V VCSELs. The method just described is largely independent of the composition and structure or dimensions of
P A T E N T Docket No. QS2090 the active region, i.e., light-emitting layers, which may be type-I or type-II or type-III heterojunctions with fairly large lateral dimensions, or heterojunctions with mesoscopic lateral dimensions, forming quantum-dots embedded in a nanowire, or a nanowire with a radial gradient of composition, forming a double core/shell structure, etc. [00452] Recent developments in photonics have demonstrated that it is possible to have highly asymmetric light emission (and perfect light absorption) along a direction, without having a mirror at the opposite end, as presented in the following reference: H. Zhou et al., "Perfect single-sided radiation and absorption without mirrors". Optica 3, no.10 (2016): 1079-1086. DOI: 10.1364/OPTICA.3.001079. [00453] VCSELs based on highly asymmetric photonic properties are preferable to conventional VCSEL technology, based on DBRs, because the latter, when implemented with conventional semiconductors, result in thicknesses that are much larger than the active medium (e.g., a quantum well), which is detrimental to factors such as the time to epitaxially grow the DBRs, as well as yield and topography for monolithic integration with CMOS. VCSELs and other photonic devices, based on highly asymmetric photonic properties would also be desirable for vertically stacking two or more of such devices, such as a laser and electro-optic modulator, or a laser and a photodiode layer enabling laser feedback interferometry. [00454] A silicon cavity is only suitable for wavelengths that silicon cannot absorb, as would be the case for IR wavelengths longer than ~ 1.1μm, such as the 1550 nm wavelength, for example. For shorter wavelengths that are absorbed by silicon, the cavity would have to be made of wider band-gap materials, which may include SiO
2 and/or Si
3N
4, since these are standard materials used in silicon/CMOS processing. In VCSELS in which the cavity material is a semiconductor material, the ohmic contacts are typically made to the end faces of the two half- cavities, with one half-cavity being n-type doped and the other being p-type doped. However, using insulator materials such as SiO
2 and/or Si
3N
4 for cavity materials requires the ohmic contacts to be made directly to the light-emitting layers. The fourth process integration architecture described below shows one solution to provide lateral ohmic contacts to the light-emitting layers that bypass the half-cavities made of insulator materials. [00455] Furthermore, it is straightforward to deposit and pattern metal films on the front side of the wafer, positioned immediately above, and aligned with, the top surface of the cavity. Likewise, it is straightforward to deposit and pattern a metallic film after the epitaxial growth of the second half-cavity. The patterning of the metallic films enables additional enhancements of electromagnetic waves and their interaction with matter, which enable optical devices, including cavities, with subwavelength dimensions, in all 3 spatial directions, which may or may not rely
P A T E N T Docket No. QS2090 on surface-plasmon polaritons. For example, there are metaldielectric structures that may manipulate light at subwavelength scales that do not rely on plasmons, and are low-loss. See for example, the following reference: X. Xiao et al., “Extraordinarily Transparent Metaldielectrics for Infrared and Terahertz Applications”, Adv. Photonics Res., 3: 2200190 (2022). DOI: 10.1002/adpr.202200190. [00456] The etching of the active area on which the epitaxial growth of the device layers is going to take place also shortens the resistive path between the circuitry made on the top surface of the substrate and the devices epitaxially grown on the back side of the substrate. This is particularly relevant for light-emitting devices, in which the overall efficiency strongly benefits from low-resistivity electrical contacts. Associated with lower resistivity is lower heat generation, which facilitates the management of thermal dissipation. [00457] The preferred solution of contacting light emitting devices with very low resistivity is through the fabrication of pixel-level deep contacts for both terminals of the light-emitting device. The process steps for these deep contacts are based on the process steps used to fabricate deep trench isolation from the back side, with a major advantage that the lateral dimensions may be significantly larger than those of the isolation trenches, thus reducing the aspect ratio for trench etching and trench filling. Similar to deep trench isolation, the lateral walls of the contact trenches are first passivated, followed by the deposition of a thin insulating layer (e.g., SiO
2) on the sidewalls, followed by filling the contact hole with a good conducting material, such as a highly doped semiconductor (amorphous or poly-crystalline), a silicide, or preferably a metal. [00458] The key difference between the isolation trench and the contact trench is that for the former, the end of the trench near the top surface of the substrate is an isolation region (e.g., a shallow trench isolation region), while for the latter, the end of the trench near the top surface of the substrate is a conducting material, such as a silicide or a metal. For the contact trench, the deposition of an insulating material (e.g., SiO
2) on the sidewalls inside the trench is followed by an etchback to make insulating sidewall spacers, and remove said insulating material from the silicide or metal at the end of the trench near the top surface of the substrate. [00459] Multiple deep trench contacts may be made inside the same pixel, depending on the needs of specific devices. Other devices might require one in-pixel contact to a terminal, while the other terminal may be contacted through a common metal line. For example, the pinning layer of photodiodes may be contacted through a metal mesh aligned and running over the deep trench isolation between adjacent pixels. The metal mesh may have electrical
P A T E N T Docket No. QS2090 connections with the circuitry made on the top side of the substrate, via deep trench contacts made at the periphery of the 2D array of pixels. [00460] The preferred solution for the fabrication of resonant structures, and patterned resonant structures forming photonic crystals, of which some have topological properties, is with small thickness structures using metamaterials, on the surface of the back side of the substrate, instead of epitaxially growing conventional structures inside an etched pixel. Similarly, the preferred solution for the fabrication of low resistance ohmic contacts to light-emitting devices is to have pixel-level deep trench metal contacts to all terminals of the light-emitting device. [00461] 1.5 Integration Of Other Devices/Functionalities [00462] 1.5.1. VCSOA [00463] What has been described for the fabrication of VCSELs is also applicable to similar devices such as the Vertical-Cavity Semiconductor Optical Amplifier (VCSOA). VCSOAs must be operated below threshold and therefore require reduced mirror reflectivities, while also requiring anti-reflection design elements at the end faces. These anti-reflection elements may be made of optical metamaterials with Near-Zero-Epsilon, which may have zero reflection. A variety of group-IV superlattices are noncentrosymmetric crystals, thereby possessing nonlinear optical properties, and thus may also be used for optical parametric amplification, as well as photon frequency conversion. A VCSOA may be vertically stacked on top of a VCSEL for an extremely compact arrangement with perfect alignment between the two devices and therefore minimized light- coupling losses. [00464] 1.5.2. Thermoelectric Devices [00465] Pixel-level thermoelectric converters (TECs), useful for cooling and/or energy harvesting, may be achieved with group-IV superlattices epitaxially grown, within the same pixel, adjacent to the most temperature-sensitive active layers of a device, such as the light-sensing layers of a photodiode. Cooling of light-sensing regions in photodiodes is extremely important in order to reduce the intrinsic carrier concentration and therefore reduce dark-current. This is particularly important in semiconductors with smaller bandgaps, needed to sense longer wavelengths in the infra-red. It may also be useful for silicon, or even wider band-gap materials, when under very weak illumination conditions and/or larger electric fields. Consequently, in- pixel thermoelectric cooling monolithically integrated adjacent to the light-sensing region may reduce dark-current and improve performance for sensing SWIR, MWIR, LWIR and FIR, ranges. It may also be a crucial factor for cooling gain regions in avalanche photodiodes or CEP photodiodes. Cooling is also very important for devices such as avalanche photodiodes (APDs)
P A T E N T Docket No. QS2090 operating in the Geiger mode for single-photon detection. In-pixel thermoelectric cooling on the back side of CIS BSI wafers cannot be achieved with materials that cannot be monolithically integrated with silicon or that require relaxed buffer layers for their epitaxial growth. [00466] FIG.13 is a schematic drawing with a 3D view of a CMOS BSI device with a 2x2 pixel array, based on the CMOS BSI device of FIG. 5, according to some embodiments of the disclosed technologies. In FIG. 13, pixel 127 has additional layers epitaxially grown/deposited over the bottom surface of the p-type pinning layer 118, and includes a n-type layer 174 to electrically decouple the p-type pinning layer 118 from the additional layers. The additional layers include a highly conductive layer 175, which may be highly doped n-type, or a highly doped n- type and highly doped p-type, to enable high ambipolar conductivity, or a group-IV superlattice with negative bandgap (i.e., a semimetal). The n-type layer 174 and the highly conductive layer 175 cover nearly the entire bottom surface of the pinning layer 118. Two complimentary thermoelectric devices 172 and 173 are contacted by separate metal lines 159, which are connected to CMOS circuitry at the periphery of the 2D array of pixels for controlling the operation of the thermoelectric devices 172 and 173. The thermoelectric devices 172 and 173 may be p- type and n-type thermoelectric converter (TEC) nanowires, respectively. [00467] FIG. 14 is a schematic drawing with a 3D view of a CMOS BSI device with a 2x2 pixel array, based on the CMOS BSI device of FIG. 9, according to some embodiments of the disclosed technologies. FIG.14 shows pixel-level thermoelectric devices 172 and 173 fabricated on the back side 102 of the silicon wafer 100 for pixels 125 and 126, side-by-side and in very close proximity with vertical nanowire optoelectronic and photonic devices 131 and 132. The thermoelectric devices 172 and 173 may be p-type and n-type thermoelectric converter (TEC) epitaxial vertical nanowires, respectively. The thermoelectric device layers 172 and 173 are epitaxially grown on top of the p-type pinning layer 118. The CAMO BIS device includes an n-type layer 174 to electrically decouple the p-type pinning layer 118 from the additional layers. The additional layers include a highly conductive layer 175, which may be highly doped n-type, or a highly doped n-type and highly doped p-type, to enable high ambipolar conductivity, or a group- IV superlattice with negative bandgap (i.e., a semimetal). The two complimentary thermoelectric devices 172 and 173 are contacted by separate metal lines 159, which are connected to CMOS circuitry at the periphery of the 2D array of pixels for controlling the operation of the thermoelectric devices 172 and 173. [00468] It is known that Si/Ge superlattices have superior thermoelectric properties, such as the Seebeck and Peltier effects, to those of SiGe random alloys. The addition of other chemical elements (other than Si and Ge) from the group-IV column is certain to increase phonon
P A T E N T Docket No. QS2090 scattering and thus lower thermal conductivity, and improve said properties. Alternating epitaxial layers consisting of different chemical species form superlattices that may profoundly alter both the electron and phonon properties. Epitaxial layers comprising alternating isotopically pure layers of the same chemical species form a superlattice for phonons, and in general would not substantially modify the electronic properties. For thermoelectric devices made of epitaxial layers it is straightforward to incorporate layers that are isotopically pure, and incorporate multiple isotopes of the same chemical species, in the same layer or different layers, for one or more chemical species, and therefore make use of isotope engineering to maximize performance. The current disclosure describes how to monolithically integrate group-IV materials that are epitaxially compatible with silicon on the back side of CIS BSI wafers. [00469] 1.5.3 Color Filters & Color Routers [00470] In standard CMOS BSI, the passivation of the back side surface is followed by the fabrication of color filters and microlenses. Conventional color filters are made of organic dyes. Conventional microlenses are made of clear (no color) transparent polymers, neither of which may withstand temperatures above 250 °C, and hence the temperatures required for the fabrication of CMOS devices (FEOL) or of metal interconnects (BEOL). Recent developments in optical/photonic metamaterials allow the replacement of color filters with wavelength separation and routing, which has advantages over color filtering, and which may be fabricated with conventional semiconductor materials and processes. An example of this new capability is described in the following reference: M. Miyata et al., “Full-color-sorting metalenses for high- sensitivity image sensors”, Optica 8(12), 1596-1604 (2021). DOI: 10.1364/OPTICA.444255. [00471] Other examples, using different materials, include: X. Zou et al. “Pixel-level Bayer-type colour router based on metasurfaces”, Nat. Commun. 13, 3288 (2022). DOI: 10.1038/s41467-022-31019-7; and Bo Han Chen, et al., “GaN Metalens for Pixel-Level Full-Color Routing at Visible Light”, Nano Letters 17 (10), 6345-6352 (2017). DOI: 10.1021/acs.nanolett.7b03135. [00472] Similarly, there are also “polarization routers”, as presented in the following references: N. A. Rubin et al., “Matrix Fourier optics enables a compact full-Stokes polarization camera”, Science 365, eaax1839 (2019). DOI: 10.1126/science.aax1839; and Y. Bao, F. Nan, J. Yan, J. et al., “Observation of full-parameter Jones matrix in bilayer metasurface”, Nat Commun 13, 7550 (2022). DOI: 10.1038/s41467-022-35313-2. [00473] The term metasurface is usually applied to subwavelength microstructures and nanostructures fabricated by patterning dielectric films deposited on a substrate. The level of functionality and performance may be increased by fabricating complex surfaces and 3D
P A T E N T Docket No. QS2090 structures, by: (1) using grayscale lithography; and/or (2) patterning not a single dielectric material, but a stack of multiple dielectric materials, with individual thicknesses ranging from a few nanometers to more than one micron, with good etching selectivity against each other; and/or (3) performing multiple patterning steps on each of possible multiple stacks of materials, to form ever more complex 3D geometries. The options just mentioned may be fabricated using standard CMOS dielectrics and process steps, and enable the additional monolithic integration of more optical layers/devices/functionalities. [00474] Other technologies to fabricate complex 3D geometries for optical devices may potentially be simpler and lower cost, such as two-photon polymerization, which typically uses materials, such as polymers, which do not allow the fabrication of additional monolithically integrated optical layers/devices/functionalities. The 3D structures fabricated by two-photon polymerization offer important functionality that in 2D-only structures require the stacking of multiple 2D metasurfaces, as shown in the following reference: Roberts, G., Ballew, C., Zheng, T. et al.3D-patterned inverse-designed mid-infrared metaoptics. Nat. Commun.14, 2768 (2023). DOI: 10.1038/s41467-023-38258-2. [00475] These wavelength and polarization routers may be monolithically integrated with embodiments of the present invention, through either (1) low-temperature wafer-bonding of the main CIS BSI wafer and a layer with the already fabricated 2D or 3D metaoptics; or (2) a direct fabrication on the same substrate of the CIS BSI wafer. It is important to note that the total thickness of the 3D metaoptics is on the order of a few wavelengths (for example, up to 10x the wavelength) of the light being manipulated. For even longer wavelengths, such as LWIR, this translates into a total thickness up to 100 μm, and for SWIR, a total thickness up to 30 μm. [00476] Whereas the references given above for the wavelength routing are focused on visible light, and how to replace the conventional Bayer filter 2D array, embodiments of the disclosed technologies applies such concepts to all the wavelengths that may be sensed with the materials and devices described in this document, and which may cover the spectrum from UV, Visible, NIR, SWIR, MWIR, LWIR, FIR, to TeraHertz. In the context of the disclosed technologies, the concept of “full color pixel” may include any number of the wavelength ranges just mentioned. Also, the lateral dimensions of such a “full color pixel” are not necessarily constrained by any of these wavelengths, since the metasurface separating and routing the different wavelengths, as well as the sensing devices, may operate with physical principles that allow them to have subwavelength dimensions. The fabrication of these metasurfaces may include the subwavelength patterning of a single dielectric, such as SiO
2, Si
3N
4, TiO
2, HfO
2, ZrO
2, etc., or layer stacks incorporating several of these dielectrics in a variety of thickness ranges.
P A T E N T Docket No. QS2090 [00477] 1.5.4 Pixel-Level Lenses (I.E., Microlenses) [00478] Regarding the replacement of conventional polymeric microlenses, there are also options with metamaterials as well as conventional optical lenses, such as Gradient-Index (GRIN) lenses. The flat top and bottom surfaces of GRIN lenses enable them to be made on top of planarized surfaces, and also to have additional layers fabricated on top of them. The fabrication of an all-dielectric or metaldielectric GRIN lens, monolithically integrated on top of the heterojunction epitaxial layers, is also described herein in the third process integration architecture . This process is compatible with conventional semiconductor processing, the flat top and bottom surfaces allowing the fabrication of additional photonic devices on top of the GRIN lens, for example metasurface/metaoptics devices such as color routers, polarization routers, and flat system metalenses. [00479] FIG. 15 is a schematic drawing with a 3D view of a CMOS BSI device with a 2x2 pixel array, based on the CMOS BSI device of FIG. 14, according to some embodiments of the disclosed technologies. FIG. 15 depicts the integration of pixel level Gradient Refractive Index (GRIN) lenses 176, which may be all-dielectric or metaldielectric, coupling light into the nanowire light-sensors or out of the light-emitters and light-modulators of the CMOS BSI device. [00480] FIG. 16 is a schematic drawing with a 3D view of a CMOS BSI device with a 4x4 pixel array, based on the CMOS BSI device of FIG.15, depicting the planarized 2D array of GRIN lenses 176, according to some embodiments of the disclosed technologies. [00481] The monolithic fabrication of GRIN lenses into a CMOS BSI wafer benefits from the possibility of depositing dielectric materials, by Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD), with a large difference in refractive index, with extreme precision in thickness and radial composition profiles, and thus a gradient of refractive index. For example, across the visible spectrum, the two most common dielectric materials used in silicon CMOS processing, SiO
2 and Si
3N
4, have refractive indices of 1.46 and 2.05, respectively, thus resulting in a difference of 0.59, a variation of more than 40% with respect to the material with the lowest value (SiO
2). The two materials are miscible and may be combined to form a composite material, silicon oxynitride (SiON), whose composition may be varied from pure SiO
2 to Si
3N
4, thereby allowing for a very large continuous gradient in the refractive index. It should be kept in mind that the processing of these two materials in CMOS technology is extremely well controlled, such that atomic-layer thickness control is routinely achieved in the deposition and etching of these two materials. The variation in composition, and thus of refractive index, may be continuous or stepwise, and the overall refractive index radial variation (i.e., profile) may be arbitrary, including linear, parabolic, etc. Other CMOS-compatible dielectric materials, such as TiO
2, or HfO
2, or
P A T E N T Docket No. QS2090 ZrO
2, etc., or layer stacks incorporating several of these dielectrics, may also be used, separately or together with SiO
2 and Si
3N
4. The set of materials forming the layers for the GRIN lens may be changed as a function of the desired wavelength range. [00482] As mentioned earlier, a GRIN lens may incorporate metals to form metaldielectric materials to enable focusing of light to deep subwavelength spots, without relying on plasmonic effects and thus having low losses. Focusing light to deep subwavelength spots is a key enabler to improve photodiodes in general, and in particular for IR wavelengths at room temperature, which have smaller bandgaps, and therefore larger intrinsic carrier concentrations, and thus larger dark-currents. The longer the wavelength to sense, the smaller the bandgap of the photodiode’s absorption region, and the larger the intrinsic carrier concentrations and dark currents. An example of deep subwavelength focusing is given in the following reference, for a case in which the light propagates parallel to the substrate surface: Y. Zhu, W. Yuan, H. Sun, and Y. Yu, “Broadband Ultra-Deep Sub-Diffraction-Limit Optical Focusing by Metallic Graded-Index (MGRIN) Lenses”, Nanomaterials 7, 221 (2017). DOI: 10.3390/nano7080221. [00483] GRIN lenses may have complex profiles for the refractive index, and perform sophisticated manipulation of optical beams, as demonstrated in the following two references: Chao He, et al., “Complex vectorial optics through gradient index lens cascades”, Nat Commun 10, 4264 (2019). DOI: 10.1038/s41467-019-12286-3; and Yijie Shen, et al., “Topologically controlled multiskyrmions in photonic gradient-index lenses”, DOI: 10.48550/arXiv.2304.06332. [00484] In the following, three methods for the fabrication of pixel-level monolithically integrated 2D arrays of GRIN pixel-level microlenses are described. By default, the GRIN microlenses may be circular, with the spacing at the corners between adjacent microlenses being filled with a low refractive-index material, but other geometric shapes are possible, including a square microlens. [00485] A first method of creating a radial gradient in refractive index is to deposit a hard mask material (or stack of materials) on a flat surface, and pattern it by etching a hole into it, for each pixel, whose diameter may define the diameter of the pixel-level GRIN microlens. For a 2D array of GRIN lenses on a wafer, there is a 2D array of such holes; their diameter and spacing is determined by the patterning step of said hard mask material. The circular GRIN microlens is formed through multiple cycles of deposition and etchback of layers with varying composition, i.e., varying refractive index, which may include not only multiple dielectric layers, with varying thicknesses, but also multiple metal layers, also with varying thicknesses. The multiple cycles of depositions and etchback form spacer-like layers on the inside walls of the circular holes, accruing thickness from the periphery to the center, i.e., from the original internal side wall of the
P A T E N T Docket No. QS2090 circular hole in the hard mask material, to the center of said hole. With this fabrication method, the GRIN lens is grown radially from the periphery to the center. [00486] For purely dielectric layers, the control of layer composition is such that the first layers have the smallest refractive index, and the last layers have the largest refractive index, i.e., the index of refraction increases toward the center of the lens. The reason for the etchback steps is due to the blanket deposition of the dielectric layers also depositing material at the bottom of the hole and top of the hard mask. The material at the top of the hard mask may be removed by CMP, but the one at the bottom of the hole cannot be removed after the hole has been completely filled. It might be possible to accommodate the material deposited at the bottom of the hole because the gradient in refraction index along the vertical direction provides a smooth variation from the central part of the GRIN lens to the interface (where the refractive index has its lowest value) with the top of the light-sensing or light-emitter layers. [00487] A second method of creating a radial gradient in refractive index on a flat surface is to first form a pillar of the material with the largest refractive index at the center of the GRIN microlens. The diameter of this pillar should be much smaller than the shortest wavelength to be manipulated by the GRIN microlens, and depending on the patterning capabilities, the pillar may have diameters as small as a few tens of nanometers, or even smaller. Similar to the first method, the microlens is formed through multiple cycles of deposition and etchback of layers with varying composition, i.e., varying refractive index, which may include not only multiple dielectric layers, with varying thicknesses, but also multiple metal layers, also with varying thicknesses. With this method the GRIN microlens is grown radially from the center to periphery. For purely dielectric layers, the control of layer composition is such that the first layers have the largest refractive index and the last layers have the smallest refractive index. Without etchback steps, the deposited material may accumulate not only at the top of the pillars but also laterally at the surface adjacent to the base of the pillars. It might be possible to accommodate the material deposited on the bottom surface, and the material accumulated at the top of the pillars may be removed subsequently by a CMP step. [00488] A third method of fabrication of pixel-level GRIN microlenses, enabling more complex gradients in the refractive index, is to deposit on a flat surface a stack of layers, which may include several dielectrics as well as metals. A radial gradient in the refractive index is then created by lithography and etching the stack of layers with geometric shapes having deep subwavelength dimensions and deep subwavelength spacings between shapes. The geometric shapes may be as simple as pixel-level concentric rings, with varying radius, width and pitch, or concentric spirals, or any arbitrary shape possible to produce by standard lithography, or by gray-
P A T E N T Docket No. QS2090 scale lithography, and etching, etc. Also, by using etch selectivity between the different materials present in the deposited stack of layers, it is possible to under-etch laterally some layers versus others, thereby generating 3D shapes. It is also possible to have addition conformal deposition of dielectrics and metals to create even more complex 3D structures. It is also possible to have non-conformal deposition of additional stacks of layers, preserving the previously formed air- gapped 3D structures, which in turn may also be patterned into 3D structures. A version of this third method is described herein in the third process integration architecture . [00489] The field of metasurfaces/metaoptics is progressing quickly towards a multitude of functionalities, most of which may be implemented via the fabrication of all-dielectric nanostructures, which may be patterned with standard lithography and etching equipment and processes used in CMOS technology. The resolution and alignment accuracy to previous patterned features of standard lithography tools used in advanced CMOS far exceed the requirements to fabricate deep subwavelength optical/nanophotonic features having lateral dimensions below 20nm, which are much smaller than the wavelength of near-visible ultraviolet (NUV) light, visible light, and orders of magnitude smaller wavelengths than IR light. The thickness of homogeneous all-dielectric structures is typically around 1 μm, or hundreds of nanometers, and may be further reduced by having heterogeneous all-dielectric structures, consisting of a stack of dielectrics with sufficiently different refractive indices. [00490] The methods of fabrication described above may be adapted to make a 2D array of GRIN microlenses, in which each GRIN microlens is placed over multiple pixels, which may be grouped in small 2D arrays, to form a light field camera. It is also possible to have the light field camera lenses fabricated on top, i.e., cascaded, with the pixel-level GRIN microlenses placed over a single pixel. Multiple GRIN microlenses may be disposed individually and/or in a 1D array and/or in a 2D array. [00491] In conventional CMOS image sensors, both FSI and BSI, the polymeric microlenses are fabricated after the fabrication of the color filters. By replacing the polymeric microlenses with the all-dielectric and/or metaldielectric GRIN microlenses, which have flat surfaces, and by replacing the conventional color filters with nanophotonic wavelength/color routers, the pixel-level color router should be fabricated after the GRIN microlenses, both fully monolithically integrated on the same substrate of the photodiodes. [00492] By making the nanophotonic all-dielectric structures with dielectrics that have refractive indices sufficiently different from that of SiO
2, it becomes possible to use SiO
2 as a planarizing material to fill the empty spaces between nanophotonic structures. In turn, planarized surfaces allow the easy fabrication of additional metasurfaces on the same substrate,
P A T E N T Docket No. QS2090 all monolithically integrated on the original CMOS BSI substrate. This allows the stacking of different metasurfaces to cascade different functionalities, or to implement functionalities that require the stacking of multiple metasurfaces. Some metasurfaces provide system-level functionalities, whereas others may be implemented at the pixel level, for example, color routing (replacing the RGGB color filters) and polarization routing. [00493] FIG.17 is a schematic drawing with a 3D view of a CMOS BSI device with a 4x4 pixel array, based on the CMOS BSI device of FIG. 16, according to some embodiments of the disclosed technologies. FIG. 17 depicts the integration of pixel-level 3D metaoptics layer for wavelength/color routing 177, on top of 2x2 Jones matrix metasurface for each color, on top of the GRIN lenses 176 and 2D array of pixels. FIG.17 also shows the 2x2 Jones matrix metasurfaces for Red, Green, Blue and SWIR, each main color having 4 subpixels for capturing polarization information. For example, 178 and 179 are 2 of the 2x2 Jones matrix metasurfaces, for one color, for instance Red, and 180 and 181 are also 2 of the 2x2 Jones matrix metasurfaces, for another color. [00494] 1.5.5 System-level Metalenses. [00495] The system lens may also be a flat metalens, in which case it may be monolithically fabricated on the same substrate, i.e., the starting CMOS BSI wafer, or after bonding the back side of the CMOS BSI wafer to a transparent substrate with a thickness that matches the back focal distance of the metalens. [00496] If the system lens has a fixed focal distance and a fixed zoom factor, it is possible to fabricate multiple CMOS image sensors with different system lenses, all on the same chip. This is possible for image sensors with lateral dimensions small enough that multiple sensors would fit inside the maximum die size possible for a given lithography tool. It is worth noting that many CMOS image sensors for X-rays have lateral dimensions that far exceed the maximum die size of typical lithography tools, “stitching together” several adjacent die. This solution is commonly known as “field stitching”. [00497] The largest market for CMOS image sensors is mobile devices, which typically have CMOS image sensors with lateral dimensions much smaller than the maximum die size possible with lithography used for leading edge CMOS. Therefore, it would be possible to fabricate, for example, four 2D arrays of pixels, each 2D array of pixels having a different flat metalens, as the system lens, with different zoom factors. Alternatively, or in addition, it would be possible to fabricate 2D arrays of pixels, each 2D array of pixels having a different flat metalens made of materials to focus different wavelength ranges, enabling multiple cameras on the same chip, some for Visible+SWIR, others for MWIR, others for LWIR, etc., and different zoom factors for each of the different wavelength ranges.
P A T E N T Docket No. QS2090 [00498] FIG.18 is a schematic drawing with a 3D view of a CMOS BSI device with a 4x4 pixel array, based on the CMOS BSI device of FIG.17, depicting the integration of a 3D metaoptics layer for a flat system lens 182, which may be a system-level GRIN lens. [00499] The fabrication of GRIN lenses and the other optical photonic devices described herein in the third process integration architecture may also be applied to the first, second, and fourth process integration architectures. GRIN lenses may be made for different wavelength ranges, through the judicious choice of dielectrics, for an all-dielectric GRIN lens, or of dielectrics and metals for metaldielectric GRIN lenses. This enables perfect co-registration of multiple cameras, i.e., multiple sets of lenses and 2D arrays of pixels with light-sensing elements, for different wavelength ranges. For example, cameras for UV, Visible, SWIR, MWIR and LWIR, may all be made adjacent to each other, with perfect co-registration. If a single GRIN lens (all-dielectric or metaldielectric) is able to form images on the same focal plane for all selected wavelength ranges, then a single 2D array of multi-spectral pixels may also be made, comprising subpixels for each of the different wavelength ranges. [00500] 1.5.6 Compound Pixels With Light-Sensing Subpixels And Light-Emitting Subpixels [00501] The fabrication of light-absorbing and light-emitting devices may be done side- by-side, within the same 2D focal plane array, which is the most complex integration case. The fabrication of 2D arrays of just light-absorbing devices or 2D arrays of just light-emitting devices, utilizes a subset of steps of the more complex flow. [00502] The fabrication of multiple LASERs distributed over a certain area may be used to decrease heat generation per unit of area or volume, and yet have a coherent LASER with power addition from all LASERs, with the coherently combined optical power of the beam approximates the total optical power of the outputs from the multiple lasers, by making a topological photonic insulator vertical cavity LASER array, as reported in the following reference: Dikopoltsev, A. et al., “Topological insulator vertical-cavity laser array”, Science 373, 1514–1517 (2021). DOI: 10.1126/science.abj2232. [00503] When the vertical cavity LASERs (VCSELs) are electrically biased (i.e., powered) independently in optically coupled photonic-crystal cavities, functions such beam-steering by phase modulation are possible, as shown in the following reference: H. Dave et al., "Static and Dynamic Properties of Coherently-Coupled Photonic-Crystal Vertical-Cavity Surface-Emitting Laser Arrays", IEEE Journal of Selected Topics in Quantum Electronics, vol. 25, no. 6, pp. 1-8, Nov.-Dec.2019, Art no.1700208, DOI: 10.1109/JSTQE.2019.2917551.
P A T E N T Docket No. QS2090 [00504] In addition, VCSELs with individual cavities may also be coupled via waveguides to obtain collective coherence and beam steering, as described in the following reference: J. C. Shih et al., "High-Brightness VCSEL Arrays With Inter-Mesa Waveguides for the Enhancement of Efficiency and High-Speed Data Transmission", IEEE Journal of Selected Topics in Quantum Electronics, vol.28, no.1: Semiconductor Lasers, pp.1-11, Jan.-Feb.2022, Art no.1501211, DOI: 10.1109/JSTQE.2021.3106910. [00505] The disclosed technologies allow the fabrication of 2D arrays of light-emitting pixels with subwavelength size/pitch, in which the active region of each light-emitting diode or LASER is nano-sized and independently electrically biased (i.e., powered), and in which the photonic crystal cavity of individual light-emitters may be optically coupled to the cavities of all other light-emitters in the 2D array by waveguides to enable coherent emission. Said waveguides may comprise one or more dielectrics and may also be patterned to form photonic crystal waveguides, with or without topological properties. Lastly these light-emitting pixels may be paired with light-sensing pixels to form compound pixels, and to form 2D arrays of compound pixels, as schematically represented in FIG.19 and FIGs.20A, 20B, 20C, and 20D. The patterning of the waveguides to form photonic crystals, with or without topological properties, is not shown in FIG.19. The LASERs depicted in FIG.19 are similar to those depicted in pixel 126 of FIG.12, and their fabrication is described herein in the fourth process integration architecture. The fabrication of 2D arrays of light-emitting pixels with subwavelength size/pitch depends on the wavelength of light to be emitted and what is the state-of-the-art in terms of commercially available CIS BSI pixel size/pitch, the latter being currently around 0.6μm, which is significantly smaller than the wavelengths in the SWIR range, such as 1.55μm, for example. [00506] FIG. 19 is a schematic drawing with a 3D view of a CMOS BSI device with a 2x2 pixel array including VCSELs that are optically coupled through waveguides, according to some embodiments of the disclosed technologies. In the example of FIG. 19, pixels 126 and 127 are light-sensing pixels and pixels 125 and 128 are light-emitting pixels. The light-emitting pixels 125 and 128 include VCSELs. The VCELs are optically coupled by one or more waveguides 183, and are electrically biased (i.e., powered) independently. The one or more waveguides 183 may be patterned into a photonic crystal, with or without topological (photonic) properties. [00507] FIG.20A is a schematic representation of a CMOS BSI device with an 8x82D array of light-sensing pixels and light-emitting pixels arranged in a first pattern, according to some embodiments of the disclosed technologies. In the example of FIG. 20A, half of the pixels are light-sensing pixels 184, and the other half are light-emitting pixels 185. The light-sensing pixels
P A T E N T Docket No. QS2090 184 and/or the light-emitting pixels 185 may be compound pixels. The light-sensing pixels 184 may be photodiodes. The light-emitting pixels 185 may be lasers. [00508] The light-sensing pixels 184 and the light-emitting pixels 185 are disposed in the array such that the light-sensing pixels 184 and the light-emitting pixels 185 alternate in a checkerboard pattern. Optical waveguides, shown as broken lines, may couple individual cavities of adjacent light-emitting pixels 185 along diagonals of the checkerboard pattern. The light-emitting pixels 185 may be electrically biased (i.e., powered) independently, enabling coherent lasing from all light-emitting pixels 185 in the 2D array. [00509] The optical waveguides may be made of one or more dielectrics. The dielectrics may be made of silicon nitride, or just silicon (for photon energies smaller than the bandgap of silicon), and patterned to form photonic crystals, with or without, topological (photonic) properties. [00510] FIG.20B is a schematic representation of a CMOS BSI device with an 8x82D array of light-sensing pixels and light-emitting pixels arranged in a second pattern, according to some embodiments of the disclosed technologies. In the example of FIG.20B, some of the pixels are light-sensing pixels 184, and some are light-emitting pixels 185. The light-sensing pixels 184 and/or the light-emitting pixels 185 may be compound pixels. The light-sensing pixels 184 may be photodiodes. The light-emitting pixels 185 may be lasers. [00511] One or more of the light-sensing pixels 184 may be disposed in a central portion of the array. The light-emitting pixels 185 may be disposed an outer portion of the array. Optical waveguides, shown as broken lines, may couple individual cavities of adjacent light-emitting pixels 185 along diagonals of the pattern. The light-emitting pixels 185 may be electrically biased (i.e., powered) independently, enabling coherent lasing from all light-emitting pixels 185 in the 2D array. [00512] The waveguides may be made of one or more dielectrics. The dielectrics may be made of silicon nitride, or just silicon (for photon energies smaller than the bandgap of silicon), and patterned to form photonic crystals, with or without, topological (photonic) properties. [00513] FIG.20C is a schematic representation of a CMOS BSI device with an 8x82D array of light-sensing pixels and light-emitting pixels arranged in a third pattern, according to some embodiments of the disclosed technologies. In the example of FIG.20C, some of the pixels are light-sensing pixels 184, and some are light-emitting pixels 185. The light-sensing pixels 184 and/or the light-emitting pixels 185 may be compound pixels. The light-sensing pixels 184 may be photodiodes. The light-emitting pixels 185 may be lasers.
P A T E N T Docket No. QS2090 [00514] One or more of the light-sensing pixels 184 may be disposed in a central portion of the array. The light-emitting pixels 185 may be disposed an outer portion of the array. Optical waveguides, shown as broken lines, may couple individual cavities of adjacent light-emitting pixels 185 along rows and columns of the pattern. The light-emitting pixels 185 may be electrically biased (i.e., powered) independently, enabling coherent lasing from all light-emitting pixels 185 in the 2D array. [00515] The waveguides may be made of one or more dielectrics. The dielectrics may be made of silicon nitride, or just silicon (for photon energies smaller than the bandgap of silicon), and patterned to form photonic crystals, with or without, topological (photonic) properties. [00516] FIG.20D is a schematic representation of a CMOS BSI device with an 8x82D array of light-sensing pixels and light-emitting pixels arranged in a fourth pattern, according to some embodiments of the disclosed technologies. In the example of FIG. 20D, one of the pixels is a light-sensing pixel 184, and the rest are light-emitting pixels 185. The light-sensing pixel 184 and/or the light-emitting pixels 185 may be compound pixels. The light-sensing pixel 184 may be a photodiode. The light-emitting pixels 185 may be lasers. [00517] The light-sensing pixel 184 may be disposed in a central portion of the array. One or more of the light-emitting pixels 185 may be disposed an outer portion of the array. Optical waveguides, shown as broken lines, may couple individual cavities of adjacent light-emitting pixels 185 along diagonals of the pattern. The light-emitting pixels 185 may be electrically biased (i.e., powered) independently, enabling coherent lasing from all light-emitting pixels 185 in the 2D array. [00518] The waveguides may be made of one or more dielectrics. The dielectrics may be made of silicon nitride, or just silicon (for photon energies smaller than the bandgap of silicon), and patterned to form photonic crystals, with or without, topological (photonic) properties. [00519] A 2D array of optically coupled but electrically independent LASERs that may be coherently combined, for example, for beam steering, has significant advantages over a 2D array of phase modulators, each working on an optical beam that was split from a single LASER. For example, heat generation and dissipation are distributed over the entire 2D array, instead of being concentrated in a single spot, as is the case for a single LASER whose power has to be split among all pixels in the 2D array. For large 2D arrays, for example, 2,048 x 2,048 (4 million pixels), when structural defects and fabrication variability may affect a few individual LASERs in the 2D array, there should not be a catastrophic failure of coherency, as might occur in the case of a single LASER, because:
P A T E N T Docket No. QS2090 [00520] 1) A few bad LASERs in a large 2D array represent a small fraction of the total optical power; [00521] 2) The larger the number of LASERs in the 2D array, the less relevant each individual LASER is for the operation of the array, and consequently the less relevant defective LASERs are in the 2D array; [00522] 3) The optoelectronic testing of the 2D array of pixels/LASERs enables the identification of bad devices, which may be electrically controlled individually, i.e., may be simply turned off, or may be electrically controlled to compensate the operational deviation caused by the structural defects or fabrication variability; [00523] 4) The calibration of the 2D array of pixels/LASERs may be done only once, or may be repeated over time intermittently in case of drift with time in the deviation; and [00524] 5) Periodic self-test and calibration enables the compensation of deviations in any pixel/LASER in the 2D array, even if not caused by structural defects or fabrication variability. [00525] 1.5.7. Electro-Optic Modulators [00526] Electro-Optic Modulators (EOM) are important photonic elements to modulate phase, frequency, amplitude, or polarization of LASERs, including the generation of frequency combs. These are fundamental building blocks for silicon photonics platforms, and frequency- modulated continuous wave (FMCW) LiDARs. [00527] Embodiments of the disclosed technologies enable a straightforward fabrication of monolithically integrated EOMs because a variety of decoupled quantum wells and coupled quantum wells (i.e., superlattices) are noncentrosymmetric crystals, and thus have nonlinear optical properties, some possessinČ^ŗŪÍîŘÍťĖè^èĺıŕīôƄ^ôīôèťŘĖè^ŜŪŜèôŕťĖæĖīĖťƅϠ^̠^^^Ϡ^ſēĖīô^ĺťēôŘŜ^ ŕĺŜŜôŜŜĖIJČ^èŪæĖè^èĺıŕīôƄ^ôīôèťŘĖè^ŜŪŜèôŕťĖæĖīĖťƅϠ^̠^^^^ [00528] A fundamental advantage of the EOM of the disclosed technologies is their epitaxial compatibility with silicon, group-IV quantum wells and superlattices that are used to fabricate the light-emitting regions and cavities of LASERs, thereby enabling an EOM to be fabricated directly on top of a VCSEL. [00529] In the case of a vertically stacked VCSEL+EOM, the top mirror of the VCSEL (the more leaky mirror) may be the bottom mirror of the EOM, as shown in FIG.12, pixel 126, whose fabrication is described in the fourth process integration architecture for pixel 535.5. Such degree of integration goes well beyond the current state-of-the-art, described in the following references: A. Shams-Ansari, et al., "Electrically pumped laser transmitter integrated on thin-film lithium niobate", Optica 9, 408-411 (2022). DOI: 10.1364/OPTICA.448617; and X. Zhang, et al.;
P A T E N T Docket No. QS2090 “Heterogeneous integration of III–V semiconductor lasers on thin-film lithium niobite platform by wafer bonding”, Appl. Phys. Lett.20 February 2023; 122 (8): 081103. DOI: 10.1063/5.0142077. [00530] 1.5.8. LiDAR System-on-Chip [00531] The features described above may be used to fabricate a LiDAR system in which there is a 2D array of VCSELs integrated within the 2D array of SWIR pixels, and additionally there are LASERs also made outside the 2D array, and outside the image circle of the system lens, such that the light emitted by these LASERs is not coupled to the system lens, and provides the type of LASER illumination system found in conventional LiDAR systems. Such a system may utilize these features in complementary ways to increase the information obtained about the 3D space to be mapped. [00532] The application of the disclosed technologies to LiDARs may have several different embodiments. Conventional LIDARs require heterogeneous integration of materials that cannot be monolithically integrated. Well-known examples are III-V compound semiconductor LASERs, and nonlinear optical materials such as lithium niobate (LiNbO
3) for the fabrication of optical combs, in order to have a wide range of wavelengths with small wavelength gaps between them. As already mentioned, some of the group-IV superlattices, described in the aforementioned U.S. Patent No. 9,640,616, “Superlattice materials and applications”, have direct band-gaps and may replace the III-V semiconductors in LASERs and photodiodes, while others have topological properties which may be used to fabricate optical combs and therefore offer the functionality of lithium niobate. Consequently, these superlattices enable the fully monolithically integrated fabrication of the photonic building blocks needed for the photonic circuits for the LiDAR described in the following reference: R. Chen, H. Shu, B. Shen, et al. Breaking the temporal and frequency congestion of LiDAR by parallel chaos. Nat. Photon. 17, 306–314 (2023). DOI: 10.1038/s41566-023-01158-4. [00533] Embodiments of the disclosed technologies also provide the photonic building blocks needed for the photonic circuits for the LiDAR described in the following reference: G. Qian, et al. "Quantum Induced Coherence Light Detection and Ranging", Phys. Rev. Lett. 131, 033603 (2023). DOI: 10.1103/PhysRevLett.131.033603. [00534] The group-IV superlattices that are topological materials, such as topological insulators or topological semimetals, may be used for second harmonic generation, i.e., to generate outgoing photons with the double of the frequency of impinging photons. Then the outgoing photons may be split into two entangled photons, with the same energy or with different energies. When the entangled photons have the same energy, through spontaneous parametric
P A T E N T Docket No. QS2090 down conversion (SPDC), each of the entangled photons have energy identical to that of the originally created photons by a LASER, before the second harmonic generation. That LASER may be inside or outside a 2D array of compound pixels, and if inside such a 2D array, may be inside or outside the image circle of a monolithically integrated GRIN lens. One of these entangled photons serves as the reference and the other photon serves as the probe, which is directed towards the object. The reference beam and the probe beam reflected by the object may go through a nonlinear crystal, such as a group-IV superlattice that is a topological material, where they interfere and subsequently are both detected by light-sensors. The light-sensing elements for the reference and probe beams, after interference, may be inside or outside a 2D array of pixels, and if inside such a 2D array, may be inside or outside the image circle of a monolithically integrated GRIN lens. [00535] Taking a step further in functionality, the disclosed technologies may be used to fabricate all-solid-state complete optical systems. Such systems may include a “System of LiDAR Systems”, in which several LiDARs are monolithically integrated on the same die, each with a GRIN system lens with different apertures, providing complementary capabilities. For example, one GRIN lens may be a wide-angle lens, another may be the prime or standard lens, and another may be a telephoto lens. [00536] FIG.25A illustrates a first example of a single-chip “System of LiDAR Systems”, according to some embodiments of the disclosed technologies. The example of FIG. 25A may include multiple cameras having perfect co-registration, with lenses having different optical designs. [00537] FIG. 25B illustrates a second example of a single-chip “System of LiDAR Systems”, according to some embodiments of the disclosed technologies. The example of FIG. 25B may include cameras with multiple wavelength ranges, such as MWIR and LWIR for example, either with passive imaging 2D arrays or with LiDARs with LASERs operating in additional wavelength ranges. [00538] The examples of FIGs.25A and 25B may include several features. A single CMOS die 201 may be mounted on a package substrate 200. A large 2D array of VCSELs 203 may be capable of beam-steering, and may not be coupled to a lens. One or more VCSELs 202 may be formed outside the main 2D arrays of VCSELs 203. VCSELs 204 may be disposed inside the main 2D array 203, but outside the image circle of a GRIN lens, and therefore not optically coupled to the lens.
P A T E N T Docket No. QS2090 [00539] A monolithically integrated GRIN lens 205 with image circle inscribed inside the large 2D array of light-sensing pixels and/or vertical emitting lasers, optically coupled via waveguides but electrically biased (i.e., powered) independently, capable of beam steering. The 2D array can have any of the layouts shown in FIGs.20A, 20B, 20C, and 20D. Other GRIN lenses may include any of the following: a GRIN lens having a telephoto aperture 206, a GRIN lens having a prime/main aperture 207, a GRIN lens having a wide aperture 208, a GRIN lens having a fisheye aperture 209, a GRIN lens designed for imaging Visible+SWIR wavelengths 210, a GRIN lens designed for imaging MWIR wavelengths 211, and a GRIN lens designed for imaging LWIR wavelengths 212. [00540] Alternatively, one set of LASERs, inside or outside the image circle of a GRIN lens, may be used to implement a Time-of-Flight (ToF) LiDAR, while another set of LASERs (on the same chip) may be employed to implement a Frequency-Modulated Continuous Wave (FMCW) type of LiDAR. [00541] In another alternative, one GRIN system lens may be optimized for the visible range, while another may be optimized for the MWIR and another for the LWIR ranges. Perfect co- registration of multiple cameras, each for a different wavelength range, benefits not only passive imaging, but also ranging. The present disclosure describes how to make UV, Visible, SWIR, MWIR, LWIR, pixels and integrated GRIN system lenses, providing more complementary wavelength sensing capabilities than the HADAR (Heat-assisted detection and ranging) described in the following reference: F. Bao, X. Wang, S. H. Sureshbabu et al., “Heat-assisted detection and ranging”, Nature 619, 743–748 (2023). DOI: 10.1038/s41586-023-06174-6. [00542] For both FIGs. 25A and 25B, the configurations in which a GRIN lens is aligned with a 2D array of vertical emitting lasers, preferably larger than the image circle of the GRIN lens, 3D mapping can be obtained without scanning. In an analogy with conventional digital cameras, such a system can be operated in a “rolling shutter” mode, in which each row of lasers in the 2D array is switched On/Off sequentially by a short pulse signal, or operated in a “global shutter” mode, in which all lasers in the 2D array are switched On/Off simultaneously by a short pulse signal. Naturally the “global shutter” mode requires the ability to handle the electrical power needed to switch On simultaneously all lasers in the 2D array, which may be done when each laser has a CMOS switch in close proximity, forming active-matrix systems, i.e., 2D arrays of light- emitting pixels, in which each light-emitting pixel has its own control circuitry, for example as shown in FIGs. 10, 11, and 12. FIG.19 shows an active-matrix of interspersed active pixels for light-sensing and active pixels for light-emission. A smaller size/pitch of light-emitting active
P A T E N T Docket No. QS2090 pixels, while keeping the dimensions of the 2D array the same, increases the spatial resolution of the illumination for 3D mapping. A smaller size/pitch of light-sensing active pixels, increases the spatial resolution of the image formed by the light rays reflected back and captured by the lens. [00543] For the LiDARs shown in FIGs.25A and 25B, the angular coverage for 3D mapping is determined by the (GRIN) lens. Wide-angle lenses, and in particular the fisheye lens, provides an angular coverage larger than what is possible with a solid-state scanning system. Wide-angle lenses also cause foreground objects to seem much more prominent than background objects, which can be an advantage for a LiDAR in certain circumstances. [00544] In the “System of LiDAR Systems” of FIGs.25A and 25B, the GRIN system lenses may be fabricated directly on the back side of the CIS BSI substrate, as exemplified in the third process integration architecture, or may be integrated through 3D wafer-level bonding. The lateral dimensions of the configuration shown in FIGs.25A and 25B depend on the size of the 2D arrays of compound pixels. As already mentioned, if the lateral dimensions exceed the field size of the lithography tool (for example a DUV scanner), it is possible to maintain the single-chip configuration through “field stitching”, in which adjacent fields are merged, and which has been used to make CMOS Image Sensors, in particular for X-ray image sensing. Such technology has enabled wafer-level chips, as demonstrated by Cerebras Systems, Inc. Ultimately, the disclosed technologies enable the fabrication, on a single-chip, of the components needed for different types of LiDAR (e.g., ToF and FMCW), which may operate in the same or different wavelength ranges, and which may operate simultaneously or in a time-interleaved fashion, in which the LASER beams may be coupled to integrated lenses or not. [00545] 1.5.9 Parallel Optical Processing System [00546] The disclosed technologies enable fabrication and use of a parallel optical processing system. The system may be formed by 3D wafer-level monolithic integration of 2D arrays of vertical emitting lasers monolithically integrated with CMOS, 2D array of light-sensing pixels monolithically integrated with CMOS, 2D arrays of passive metaoptical elements performing a fixed functions, and/or 2D arrays of active metaoptical elements integrated with CMOS, in which the functions of these elements may be dynamically changed through the CMOS devices. The layers with metaoptical elements, either passive or active, may be placed in between the layer with vertical emitting lasers and the layer with light-sensing pixels. [00547] The passive metaoptical elements may be incorporated as a single layer, or cascaded as a multitude of layers to improve the performance of a single function or to perform
P A T E N T Docket No. QS2090 a sequence of different functions. With passive metaoptical layers, one of the layers includes an optical computer executing a fixed program. Likewise, the active metaoptical elements may also be incorporated as a single layer, or cascaded as a multitude or layers to improve the performance of a single function or to perform a sequence of different functions. With active metaoptical layers, one of the layers includes a programmable optical computer capable of executing different functions through software control of the active metaoptical layers. The metaoptical layers may include dielectric features whose thickness is close to the half the wavelength of the light traversing them. [00548] Examples of functions executable with the passive and/or active metaoptical layers include: [00549] - light diffraction, for “Diffractive Computing”, which includes Deep Neural Networks and computational imaging (i.e., a camera without a system lens and without electronic digital signal processing); [00550] - phase diffusion, [00551] - polarization transformation, [00552] - phase to intensity transformation, [00553] - quantitative phase imaging and phase recovery, [00554] - space to spectral transformation (e.g., using multiwavelength illumination), [00555] - hologram reconstruction, and [00556] - class specific linear transformations. [00557] One type of active metaoptical elements is a Pockels effect material and/or stack of materials, monolithically integrated with CMOS, whose index of refraction can be changed through the application of an electric field. As already mentioned, epitaxial group-IV heterojunction layers may be non-centrosymmetric crystals, which inherently exhibit the Pockels effect, thus enabling active metaoptical elements to be monolithically integrated with CMOS according to the present invention. [00558] FIG. 26 is a schematic with a 3D view of a parallel optical processing system, according to some embodiments of the disclosed technologies. The system of FIG. 26 may include any of the following features: light-sensing pixels 220, a 2D array of light-sensing pixels 221, a buffer layer 222, VCSELs 223, a 2D array of VCSELs 224, one or more phase masks 225, and a stack of masks 226. The 2D array of light-sensing pixels 221 and the 2D array of VCSELs
P A T E N T Docket No. QS2090 224 may be integrated with CMOS. The buffer layer 222 may be fabricated of a dielectric transparent to the wavelength(s) of operation. The stack of masks 226 may include phase masks, phase diffusers, phase-to-spectral converters, and polarization transformers, capable of performing a variety of functions. [00559] 1.5.10. Photonic Compass On A Chip [00560] A photonically integrated chip-scale ring laser gyroscope capable of measuring the Earth’s rotation was described in the following reference: Y.-H. Lai et al., “Earth rotation measured by a chip-scale ring laser gyroscope”, Nat. Photonics 14, 345–349 (2020). DOI: 10.1038/s41566-020-0588-y. [00561] The principle of operation is that when the gyroscope’s axis is oriented towards north and south, the round-trip travel time of the clockwise and counterclockwise laser modes is different due to Earth’s rotation. This difference changes the frequency splitting of the cavity modes, allowing transduction of rotation into a frequency measurement. In contrast, orienting the gyroscope axis along the east and west directions induces no rotation along the gyroscope axis, and these orientations are used as a control measurement. [00562] The fabrication of a 2-axis gyroscope, with axis directions forming a 90 degree angle between each other, enables the simultaneous measurements in each axis. When one axis is aligned with the North-South direction, there is a frequency to be measured, while the other axis is necessarily oriented along the East-West direction, and there is no signal produced. Any other orientation that is not equivalent may produce frequency signals for each axis, which may be used to calculate the orientation of the gyroscope. Therefore, such configuration for a 2-axis gyroscope enables a photonic compass capable of indicating the direction of the true geographic north pole, not the magnetic pole. [00563] This photonic compass may be fabricated (i.e., monolithically integrated), aligned with the vertical and horizontal edges of the 2D array of pixels (having electronic global shutter pixels), or compound pixels (having electronic global shutter pixels), and provide geographic orientation data at a particular time when light was detected and/or when light was emitted. For example, it may be used in passive imaging, to provide metadata about geographic orientation for each frame. It may also be used in LiDARs to provide additional information regarding the orientation of the LiDAR system when light was emitted and when light was sensed, for ToF LiDARs, or when changes occurred to any parameter in FMCW LiDARs.
P A T E N T Docket No. QS2090 [00564] This photonic compass may complement a magnetic compass or GPS signal, or replace a magnetic compass if magnetic disturbances render it unreliable, or replace GPS signals if they are not available. [00565] 1.5.11. Photonic Gyroscope On A Chip [00566] Embodiments of the present invention enable the monolithic integration of LASERs, Photodiodes, including single-photon detection capabilities, group-IV epitaxial layer stacks that form epsilon near-zero regions/materials, as wells as group-IV superlattice materials that are noncentrosymmetric crystals, having topological properties, and significant large ŗŪÍîŘÍťĖè^ ĺIJīƅ^ ̠^^^Ϡ^ ÍIJîϯĺŘ^ èŪæĖè^ ̠^^^^ IJĺIJīĖIJôÍŘ^ ĺŕťĖèÍī^ ŘôŜĺIJÍťĺŘŜϠ^ ſēôŘô^ ̠^ ĖŜ^ ťēô^ complex electric susceptibility. [00567] This variety of materials and metamaterials with nonlinear optical properties enables the construction of photonic devices with deep subwavelength dimensions and spacings, between adjacent devices, yet maintaining very high-quality factors. These properties enable the fabrication of a 3-axis optical gyroscope on a single chip, monolithically integrated with CMOS and the simple or compound pixels of the disclosed technologies. ^ēô^̠^^^^IJĺIJīĖIJôÍŘ^ optical resonators possible with the aforementioned group-IV epitaxial materials enable the giant gain of several orders of magnitude in responsivity reported in the following reference: J. M.^Silver^et al, “Nonlinear enhanced microresonator gyroscope”, Optica^8(9), 1219–1226 (2021). DOI: 10.1364/OPTICA.426018. [00568] The aforementioned materials and metamaterials with exceptional optical properties enable also the implementation of a fully monolithically integrated version of the gyroscope capable of very large improvements in detection over the shot-noise limit of linear gyroscopes with comparable dimensions and power requirements, described in the following reference: a^^ ^ŪIJϠ^a^^ [ĺIJêÍŘϠ^ «^^ XĺŽÍIJĖŜϠ^ ¾^^ [ĖIJϠ^ ЊbĺIJīĖIJôÍŘ^aŪīťĖ-Resonant Cavity Quantum Photonics Gyroscopes Quantum Light Navigation”. DOI: 10.48550/arXiv.2307.12167. [00569] Applications of such 3-axis gyroscope, apart from the fundamental navigational information, may include passive imaging as well as LiDAR systems to provide information about movement in any direction. When integrated with an image sensor it enables the adjustment of the timing of readout of photo-current or the integration time of said photo-current, such that the signal in a frame is acquired in a time interval during which there is no movement. For image sensing with single-photon detection and readout, each readout process stores a 1-bit plane, and the selection of 1-bit planes that are added to form a frame may be constrained by the detection of motion, of the camera or of objects in the field of view, either of which may induce
P A T E N T Docket No. QS2090 image blurring in conventional image sensing and video. Therefore, such an integrated gyroscope enables the acquisition of images or video that are free from motion-induced blurring. [00570] When integrated with a LiDAR, likewise it enables signal acquisition (e.g., images) free of motion artifacts, and also the control of light emission such that motion artifacts are also avoided. [00571] 1.5.12. Augmented Reality, Virtual Reality, Passthrough Virtual Reality, Systems [00572] The disclosed technologies may be applied to Augmented Reality (AR), Virtual Reality (VR), and Passthrough Virtual Reality (PVR), and to devices AR, VR, and PVR, including Glasses, Goggles, Helmets, and similar devices, to enhance key capabilities necessary to improve user experience. [00573] For example, eye-tracking (or gaze-tracking) may be done by analysis of the iris structure. The detail of that structure depends on iris color and the wavelength range used to capture an image of said structure. For light colored eyes, an image in the visible range captures the most details, but for dark colored eyes, the most detail is revealed in the SWIR range. Like NIR illumination, SWIR illumination does not excite the pupil, and therefore the iris structure is not affected by the pupil dynamics, but the safety levels for SWIR illumination allow for much higher intensity, which in turn enables higher signal-to-noise ratios and higher framerates, and thus faster and more precise gaze-tracking. Also, longer wavelengths (e.g., SWIR versus NIR and Visible) travel further into the multiple layers forming the iris, thereby capturing more information about its morphology. [00574] Consequently, the ideal camera for gaze-tracking has RGB and SWIR pixels, for simultaneous capture of images across these wavelengths. Since AR/VR/PVR systems are extremely sensitive to size, weight, and power consumption of all components, the disclosed technologies enable the fabrication of such image sensors and cameras with the smallest pixel size, highest resolution, smallest camera size, lowest weight and lowest power consumption and dissipation, at the lowest manufacturing cost. [00575] Another gaze-tracking technique, complementary to the previous ones, can also be implemented with the disclosed technologies: laser feedback interferometry enabling the determination of Doppler shifts between the irradiated laser beam and the backscattered beam. The current invention enables an extremely compact integration of a photodiode into the reflector layers of the LASER, opposite to the reflector layers that allow the light beam to exit the laser cavity. Such arrangement shares similarities with the integration of an electro-optical modulator with a laser, as described in the fourth process integration architecture for pixel 535.5, with the key difference being
P A T E N T Docket No. QS2090 that photodiode layer/layers are inserted into the mirror layers fabricated before the fabrication of the first half-cavity, the active region, the second half-cavity, and the mirror layers from which the light beam exits the laser cavity. The photo-generated electrical signal in the photodiode layer/layers needs to be readout by the CMOS devices made on the top surface of the wafer. [00576] The monolithic co-integration of multi-spectral light-sensing pixels and light- emitting pixels enables multispectral video capture of the eye fundus. Obtaining a large Field Of View (FOV) in fundus photography has been historically a technical challenge. One way to obtain a large FOV is described in the following reference: T. Son, J. Ma, D. Toslak, et al., “Light color efficiency-balanced trans-palpebral illumination for widefield fundus photography of the retina and choroid”. Sci Rep 12, 13850 (2022). DOI: 10.1038/s41598-022-18061-7. [00577] The present invention may greatly enhance trans-palpebral illumination, because of the longer penetration through skin of the longer wavelengths of SWIR. The same advantages of using longer wavelength ranges apply to the sensors used in the method, which requires IR cameras for corneal imaging, described in the following reference: C. Lander, M. Löchtefeld, A. Krüger, “hEYEbrid: A hybrid approach for mobile calibration-free gaze estimation”. Proc. ACM Interact. Mobile Wearable Ubiquitous Technol.2018, 1, 149. DOI: 10.1145/3161166. [00578] The advantages of the RGB+SWIR image sensors and cameras for optimal capturing of iris structure and morphology for any iris color are also extremely valuable for biometric identification. [00579] The “world cameras” mounted on the AR/VR/PVR systems may also take advantage of RGB+SWIR image sensors, given the additional information captured in this wavelength range. Actually, AR/VR/PVR systems may also benefit from cameras covering additional wavelength ranges, such as Gamma-rays, X-rays, UV, MWIR and LWIR, and TeraHertz, provided that they may be made with the very strict constraints regarding size, weight, power consumption/dissipation, etc., which the disclosed technologies enable. [00580] Last but not least, the LiDAR-on-a-Chip described above may also be used in AR/VR/PVR systems because it complies with the restrictions regarding size, weight, power consumption/dissipation, etc., and therefore the possibility of incorporation into AR/VR/PVR systems. [00581] 1.5.13. Optical Contactless Blood Pressure Measurement [00582] A variety of health conditions are associated with, or caused by, high systemic blood pressure. Therefore, monitoring of systemic blood pressure in real time in a non-intrusive
P A T E N T Docket No. QS2090 manner is of high value. It has been shown that systemic blood pressure may be obtained through optical contactless means, through photoplethysmography and holographic laser Doppler imaging. Because of the ubiquity of image sensors in personal mobile devices, the most convenient wavelengths to use are those possible to detect with CMOS image sensors that cover the visible range and NIR ranges. [00583] Given that the light penetration depth increases with increasing wavelengths in the NIR/SWIR range, the additional information provided by wavelengths in the SWIR range may significantly improve imaging of the blood flow through arteries, veins, and microcirculation in microvessels, which include terminal arterioles, metarterioles, capillaries, and venules. Consequently, this may also increase the performance and reliability of blood pressure measurement. Therefore, light-sensing and light-emitting devices in the SWIR range of the embodiments of the present invention provide low-cost, small-size, low-weight and low-power characteristics necessary for incorporation in consumer devices and enable photoplethysmography and holographic laser Doppler imaging in said SWIR range. [00584] In view of the above, contactless measurement of blood pressure may be measured through video sequences in the SWIR range of particular skin spots, for example in the face, with future consumer devices that incorporate the SWIR image sensors and light emitters of the embodiments of the present invention, for example Augmented Reality (AR) glasses. [00585] 1.5.14. Drones [00586] The very strict constraints regarding size, weight, power consumption/dissipation, etc., which the disclosed technologies enable for multispectral image sensing, on-chip LiDAR, etc., in AR/VR/PVR systems, makes them also extremely valuable for any type of drone in which size, weight, power consumption/dissipation are of critical importance, such as autonomous flying drones. [00587] 1.5.15. Fiber-Coupled Optical (FCO) Communications System [00588] FIG.28A is a schematic drawing with a 3D view of Fiber-Coupled Optical (FCO) communications system, according to some embodiments of the disclosed technologies. The system may be based on the devices of FIG.20B, or 20C, or 20D. [00589] FIG. 28B is a schematic drawing with a 3D view of the system of FIG. 28A with lenses 245 and 246 added. Each of the lenses 245 and 246 may be conventional, or metaoptics flat-lenses, or metaoptics diffractive elements for computational photography.
P A T E N T Docket No. QS2090 [00590] The vertical emitting lasers 228 may be disposed around the light-sensing element 243. The light-sensing element 243 may be a photodiode or waveguide. The light-sensing element 243 may be a 2D array of photodiodes. The photodiodes may be coherently combined by being optically coupled through waveguides. The photodiodes may be electrically biased independently to enable beam steering. The dimensions of the light-sensing element 243, as well as the dimensions and number of independent vertical emitting lasers 228 in the outer region, are engineering parameters. These dimensions may be larger than the dimensions of the field size of the lithography tool by using field stitching. [00591] Standard photonic I/O connectors are generally made at the edge of diced chips. The connectors have optical fibers that are placed on V-grooves and optically aligned and coupled to waveguides which guide light from/to photonic components on the chip such as beam splitters, lasers, photodiodes, modulators, etc. Mechanical misalignments between waveguides and fibers and fiber-to-fiber connections are responsible for the coupling losses of photonic connections, and are notable causes of low efficiency. These losses are only compensated by increasing the optical power output of the lasers. [00592] A wafer-level photonic circuit may also have edge photonic connectors, after dicing the round edges into straight edges, for a square shape for example, and connectors mounted at certain positions along the straight edges. [00593] On the other hand, with beam steering of an array of vertical emitting lasers, it becomes possible to discover the best coupling to a fiber and thus minimize losses and therefore minimize the laser power consumption to establish reliable communications. This enables a new approach to optically couple fibers to on-chip photodiodes and vertical emitting lasers, enabling two-way communications via a single fiber. The coupling may also be one-way, for in-coupling a beam into the photonic circuit or for out-coupling a beam out of the photonic circuit. [00594] The new approach employs 3D wafer-to-wafer bonding between a first wafer with photodiodes, vertical emitting lasers, GRIN lenses and other photonic components, and a second wafer with GRIN lenses on a first side and holes with optical fibers on the second side. The following provides a description of how to fabricate such a Fiber-Coupled Optical (FCO) communications system. [00595] A typical single-mode optical fiber has a core diameter between 8 and 10.5 μm ÍIJî^ Í^ èīÍîîĖIJČ^ îĖÍıôťôŘ^ ĺċ^ ^^^^ ̕ı^ See https://en.wikipedia.org/wiki/Single- mode_optical_fiber#cite_note-arcelect-7.
P A T E N T Docket No. QS2090 [00596] For 3D wafer-to-wafer bonding the alignment precision may be less than 1 μm (and even less than 0.1 μm, see for example reference: H. Mitsuishi et al., "50 nm Overlay Accuracy for Wafer-to-wafer Bonding by High-precision Alignment Technologies," 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2023, pp. 1664-1671. DOI: 10.1109/ECTC51909.2023.00283. Therefore, the dimensions of the photodiode can be around the diameter of the fiber core (less than 11 μm) plus the alignment precision. [00597] Consequently, the light-sensing element 243 may have lateral dimensions such as 15μm x 15μm, which is more than large enough to capture the laser beam coming from the fiber 241, even without a lens (e.g., a GRIN lens) at the end of the fiber core tip 242, provided that the distance between the tip 242 and the light-sensing element 243 is just a few microns, as it may be with the proposed technology. [00598] A GRIN lens 245 may be monolithically integrated and centered with the hole 244 into which the fiber 241 will be mechanically inserted, further ensuring that the beam coming from the fiber 241 will have little to no dispersion. Furthermore, a GRIN lens 246 may be monolithically integrated and centered on the light-sensing element 243, thus ensuring that there will be little to no losses. [00599] Now two processes are described for fabricating a FCO communications system. Other processes may mix aspects of either or both of these processes. [00600] FIG. 40 is a flowchart illustrating a first process 4000 for fabricating a FCO communications system, according to some embodiments of the disclosed technologies. The process 4000 may be employed to fabricate the devices disclosed herein with reference to FIGs. 28A,B. The elements of process 4000 are presented in one arrangement. However, it should be understood that one or more elements of the process may be performed in a different order, in parallel, omitted entirely, and the like. Furthermore, the process 4000 may include other elements in addition to those presented. [00601] Referring to FIG. 40, the process 4000 may include fabrication of the first wafer 200, at 4002. This subprocess may include fabrication of a GRIN lens 246, monolithically integrated over the light-sensing element 243. The GRIN lens 246 may have a diameter larger than the diagonal of the light-sensing element 243. [00602] Referring to FIG. 40, the process 4000 may include fabrication of the second wafer 240, at 4004. This subprocess may include fabrication of a GRIN lenses 245 and 246 on a first side of a bare silicon wafer, for example according to the process flows described herein, at 4006. These GRIN lenses 245 and 246 may be made through a radial gradient of composition,
P A T E N T Docket No. QS2090 and may be made with SiO
2 and Si
3N
4, or SiO
2 and other dielectrics used in CMOS such as HfO
2, ZrO
2, ZrHfO
2, Al
2O
3, etc. For infra-red wavelengths that silicon cannot absorb, such as 1310 nm and 1550 nm, silicon, and/or amorphous-silicon and/or polysilicon may also be used as a waveguide material. The top crystalline silicon layer of Silicon-On-Insulator (SOI) wafers is commonly used as a waveguide in silicon photonics. The single-crystalline silicon of a backside- thinned wafer can also be viewed as a “silicon-on-insulator” material, because portions of the front side of the wafer may be covered with SiO
2. The final thickness of the backside-thinned wafer may be engineered, depending on the application, may be several micrometers thick, and may also be reduced to tens of nanometers. [00603] The radial gradient in composition of the GRIN lenses 245 and 246 may include an almost continuous variation between Si and SiO
2 or Si and Si
3N
4, for example. A Metallic Graded-Index (MGRIN) lens may be used, enabling deep sub-diffraction-limit optical focusing, in which case the diameter of the light-sensing element 243 may be significantly reduced, with the main limitation coming from the 3D wafer-to-wafer alignment. The space between GRIN lenses 245 and 246 should be filled with a dielectric such as SiO
2, and consequently the GRIN lenses 245 and 246 should be made with other dielectrics with significantly larger dielectric constants than SiO
2. The resulting surface may be planar, and a chemical mechanical polishing step may be added. Optionally, a film of SiO
2 may be deposited before the fabrication of the GRIN lenses 245 and 246. This film of SiO
2 may be just a few nanometers thick. [00604] This GRIN lenses 245 and 246 may in fact be dual-function lenses, to first focus the light beam coming out of the fiber, to reduce its diameter, and then to collimate the beam with a reduced diameter. [00605] The fabrication of the second wafer 240 may include patterned etch of through- wafer holes 244, at 4008. The holes 244 may be from second side of bare wafer, i.e., the side opposite to the side on which GRIN lenses 245 were made. The holes 244 may be centered with the center of the GRIN lenses 245 and 246. The etching of the second silicon wafer 240 may be highly selective against SiO
2 and other dielectrics, and may stop once the SiO
2 layer is reached (i.e., a self-limiting etch process). [00606] The process 4000 may include bonding of the second wafer 240 to first wafer 200, at 4010. Here the GRIN lenses 245 of the second wafer 240 may be positioned over and aligned with the GRIN lenses 246 of the first wafer 200, with good alignment between the centers of the GRIN lenses of both wafers.
P A T E N T Docket No. QS2090 [00607] The optical fiber 241 may be inserted into the etched hole 244 from the second side of the second wafer 240. In order to prevent a mechanical contact between the fiber 241 and the GRIN lens 245, which likely would damage the core of the fiber, the side walls of the hole 244 may be slightly tapered, with the diameter of the hole 244 at the surface where the fiber 241 is inserted being larger than the diameter of the fiber 241, and the diameter of the hole 244 at the interface with the GRIN lens 245 being smaller than the diameter of the fiber 241. If in order to achieve the required accuracy of the hole diameter near the GRIN lens 244 the bare wafer 240 needs to be thinner than the standard thickness, then either before or after the fabrication of the GRIN lenses 245, the wafer 240 may be thinned prior to the patterned etch of the holes 244. [00608] FIG. 41 is a flowchart illustrating a second process 4100 for fabricating a FCO communications system, according to some embodiments of the disclosed technologies. The process 4100 may be employed to fabricate the devices disclosed herein with reference to FIGs. 28A,B. The elements of process 4100 are presented in one arrangement. However, it should be understood that one or more elements of the process may be performed in a different order, in parallel, omitted entirely, and the like. Furthermore, the process 4100 may include other elements in addition to those presented. [00609] Referring to FIG. 41, the process 4100 may include fabrication of the first wafer 200, at 4102. This embodiment includes no fabrication of a GRIN lens. [00610] The process 4100 may include fabrication of the second wafer 240, at 4104. This embodiment includes no fabrication of a GRIN lens. [00611] The fabrication of the second wafer 240 may include patterned etch of through- wafer holes 244, at 4106. The holes 244 may be from second side of bare wafer, i.e., the side opposite to the side on which GRIN lenses 245 were made. The holes 244 may be centered with the center of the light-sensing element 243. The etching of the second silicon wafer 240 may be highly selective against SiO
2 and other dielectrics, and may stop once the SiO
2 layer is reached (i.e., a self-limiting etch process). [00612] The process 4000 may include bonding of the second wafer 240 to first wafer 200, at 4108. Here the hole 244 of the second wafer 240 may be positioned over and aligned with the light-sensing element 243 of the first wafer 200, with good alignment between the centers of the holes 244 and light-sensing element 243. [00613] After either of the processes 4000 and 4100 described above, the bonded wafers 200 and 240 may undergo wafer-level packaging.
P A T E N T Docket No. QS2090 [00614] For the case of a full wafer circuit, before inserting the optical fibers 241 into the holes 244, the packaging of the wafers 200 and 240 may have a whole-wafer mechanical packaging shell, which provides positional stability after the fibers 241 are inserted into the holes 244. [00615] For the case in which the bonded wafers 200 and 240 will be singulated into an individual die, then each die may have its own mechanical packaging shell, which provides positional stability after the fibers 241 are inserted into the holes 244. [00616] The fibers 241 inserted into the holes 244 may be fairly short, and may be inserted into standard connectors, or may be without connectors. [00617] The processes 4000 and 4100 described above do not require conventional FC connectors. And Instead of a photodiode 243, a waveguide patterned to be a grating coupler may be used. [00618] 1.5.16. XR Eyeglasses [00619] AR/VR/MR technologies are now often referred to under the umbrella term XR, which is short for Extended Reality. FIG. 29 shows an example of an XR system in the form of eyeglasses, according to some embodiments of the disclosed technologies. Referring to FIG.29, the eyeglasses may include forward-looking cameras, 3D ranging systems, and projection systems, operating across multiple wavelengths, including SWIR. The eyeglasses may also include backward-looking cameras, 3D ranging systems, and projection systems, including eye- tracking systems and oculus. In the example of FIG. 29, camera 252 may be a system-on-chip with any of a SWIR camera, a SWIR LiDAR, and a SWIR holographic image projector. SWIR images and holograms may be captured to see with SWIR image sensors. In the example of FIG. 29, camera 253 may be a CMOS RGB+SWIR camera, with photodiodes having CEP gain to improve image capture in ultra-low light conditions for all wavelengths. [00620] 1.5.17. Under-Display 3D Sensing System [00621] FIG. 30 shows an example of an under-display 3D sensing system. The system may include a display 256 mounted within a display bezel 255 of a portable device., comprising a 2D array of pixels. The system may include aa under-display system-on-chip SWIR 3D sensing system mounted underneath the display 256. [00622] PROCESSES
P A T E N T Docket No. QS2090 [00623] 2.0 High-level Process [00624] FIG. 31 is a flowchart illustrating a process 3100 for fabricating a CMOS- integrated optoelectronic and/or thermoelectric device, according to some embodiments of the disclosed technologies. The process 3100 may be employed to fabricate the devices disclosed herein. The elements of process 3100 are presented in one arrangement. However, it should be understood that one or more elements of the process may be performed in a different order, in parallel, omitted entirely, and the like. Furthermore, the process 3100 may include other elements in addition to those presented. [00625] Referring to FIG. 31, the process 3100 may include providing a CMOS silicon wafer having a front side and a back side, at 3102. [00626] Referring again to FIG.31, the process 3100 may include fabricating at least one CMOS device on the front side of the CMOS silicon wafer, at 3104. [00627] Referring again to FIG. 31, the process 3100 may include monolithically integrating at least one optoelectronic and/or thermoelectric device on the back side of the CMOS silicon wafer, at 3106. This subprocess may include pseudomorphically growing at least one heterojunction epitaxial layer such that the at least one heterojunction epitaxial layer is strained to one or more crystallographic orientations of silicon. [00628] Referring again to FIG.31, the process 3100 may include electrically coupling the at least one optoelectronic and/or thermoelectric device to the at least one CMOS device, at 3108. [00629] Below, four exemplary process integration architectures are described. The processes may be employed to fabricate the devices disclosed herein. The elements of the processes are presented in one arrangement. However, it should be understood that one or more elements of the processes may be performed in a different order, in parallel, omitted entirely, and the like. Furthermore, the processes may include other elements in addition to those presented. These process integration architectures are described with reference to FIGs.21-24. In the drawings for the process integration architectures the acronyms TG, FD, DTI, stand for Transfer Gate, Floating Diffusion, Deep Trench isolation, respectively. [00630] The drawings for the fourth process integration architecture (FIGs. 24.1-24.88) show pixels with both NMOS and PMOS inside the same pixel, for the purpose of illustrating the more complex configuration. However, each pixel could have just one MOSFET, or could have multiple NMOS or multiple PMOS devices.
P A T E N T Docket No. QS2090 [00631] The devices whose fabrication is described for the third and fourth process integration architectures can be made side-by-side. One example, shown in FIG.8, provides a 3D perspective of an array of 2x2 pixels in which 2 pixels have devices fabricated according to the third process integration architecture, and 2 pixels have devices made according to the fourth process integration architecture. Another example, shown in FIG.19, provides a 3D perspective of an array of 2x2 pixels in which 2 pixels comprise photodiodes for light-sensing, and 2 pixels comprise LASERs, optically coupled to each other by a waveguide, while being electrically biased (i.e., powered) independently. [00632] Regarding the fourth process integration architecture and the fabrication of a stacked VCSEL+EOM in pixel 354.5, the contacts to the EOM device are only partially shown. The preferred solution has the contacts of the EOM device to CMOS devices on the front side of the wafer being made along the direction perpendicular to the plane of the 2D cross section shown in the drawing. [00633] 2.1 First Process Integration Architecture [00634] In the first process integration architecture, the epitaxial growth, and the optional bonding of ultrathin substrate layers with different crystallographic orientations, on the back side of the wafer, are performed before processing of CMOS devices on the front side of the wafer. [00635] For this process integration architecture, the entire CMOS fabrication, FEOL+BEOL, should be executed at temperatures that are low enough to avoid causing damage to the epitaxially grown layers. A safe CMOS maximum processing temperature would be the maximum temperature reached during the epitaxial growth itself. Because defining such a temperature is dependent on the particular levels of strain (i.e., composition) and doping profiles of the epitaxial films, for the purpose of providing an exemplary value, this maximum temperature may be assumed to be 500 °C or less. Therefore, this process integration architecture would require the MOSFET devices to be made with low-temperature process steps, for example, 500°C or less. Multiple variants of this process architecture can be derived by making trivial modifications to the sequence and/or order of process steps and modules. [00636] FIGs.32A,B depict a flowchart illustrating a process 3200 for fabricating a CMOS- integrated optoelectronic and/or thermoelectric device using the first process integration architecture, according to some embodiments of the disclosed technologies. Note operations 3102-3120 take place prior to starting standard CMOS FEOL processing. [00637] Referring to FIG. 32A, the process 3200 may include, before executing FEOL, bonding the front side of the wafer to a first mechanical substrate (e.g., a "wafer carrier"), at 3202.
P A T E N T Docket No. QS2090 The first mechanical substrate may be covered with any interface layer that is suitable for the purposes of bonding and debonding, and is compatible with the wafer thinning steps and the process steps related to the epitaxial growth. [00638] The process 3200 may include thinning of the back side of the wafer, at 3204. [00639] The process 3200 may include bonding of one or more ultrathin substrate layers of silicon with different crystallographic orientations to the back side of the thinned wafer, at 3206. [00640] The process 3200 may include patterning of the back side of wafer to expose selected crystallographic orientations, at 3208. [00641] The process 3200 may include executing the "Epitaxial Module" described above one or more times, at 3210. [00642] The process 3200 may include executing, one or more times, patterning steps, depositions, etches, etc., to nanostructure the epitaxially grown films and/or to fabricate devices incorporating said epitaxial films, at 3212. [00643] The process 3200 may include executing deep trench isolation from the back side of the wafer, forming pinning layers on the sidewalls of trenches, and optical isolation with deposition of metal inside the isolation trenches, at 3214. [00644] The process 3200 may include performing wafer-level planarization of the back side of the wafer, at 3216. [00645] Referring to FIG.32B, the process 3200 may include bonding of the back side of the wafer to a second mechanical substrate, at 3218. [00646] The process 3200 may include debonding the first mechanical substrate from the front side of the wafer, at 3220. [00647] The process 3200 may include executing FEOL and BEOL on the front side of the wafer, at 3222. [00648] The process 3200 may include bonding the front side of the wafer to a circuitry wafer, at 3222.3D hybrid Cu-Cu bonding may be used for the bonding, at 3224. [00649] The process 3200 may include debonding the second mechanical substrate from the back side of the wafer, at 3226.
P A T E N T Docket No. QS2090 [00650] The process 3200 may include fabrication of color filters and microlenses, at 3228. The color filters and microlenses may be conventional color filters and conventional microlenses. [00651] The process 3200 may include fabrication of non-conventional GRIN microlenses, wavelength (e.g., color) routers and/or all-dielectric or metaldielectric optical/photonic devices, at 3230. The metaldielectric optical/photonic devices may include polarization routers, a system flat lens, and the like. [00652] The process 3200 may include wafer-level packaging, at 3232. [00653] FIGs. 21.1-21.30 illustrate a process for fabricating a CMOS-integrated optoelectronic and/or thermoelectric device using the first process integration architecture, according to some embodiments of the disclosed technologies. [00654] FIGs.33A-D depict a flowchart illustrating a process 3300 for fabricating a CMOS- integrated optoelectronic and/or thermoelectric device using the first process integration architecture, according to some embodiments of the disclosed technologies. Note operations 3202-3254 take place prior to starting standard CIS FEOL processing. Process 3300 is now described with reference to FIGs.21.1-21.30. [00655] Referring to FIG.21.1, the process 3300 may include bonding the front side 301 of the wafer 300 to a first wafer carrier 303, at 3302 (FIG. 33A). The process 3300 may include thinning of the back side 302 of the wafer 300, exposing an n-type lowly doped surface, at 3304 (FIG.33A). The process 3300 may include bonding an ultrathin n-type lowly doped silicon layer 304 having (110) surface orientation, at 3306 (FIG.33A). The ultrathin layer 304 may be around 10 nm thick. If this optional bonding takes place, then an optional epitaxial growth of another ultrathin layer (e.g., 2 nm or less) of Ge or SiGe or SiGeC alloy with high-Ge percentage may be performed to provide sufficient chemical contrast for selective etching of a pure silicon layer. [00656] Referring to FIG.21.2, the process 3300 may include bonding the ultrathin n-type lowly doped silicon layer 305 having (111) surface orientation to ultrathin layer 304, at 3308 (FIG. 33A). The ultrathin layer 305 may be around 10 nm thick. If this optional bonding takes place, then an optional epitaxial growth of ultrathin layer (e.g., 2 nm or less) of Ge or SiGe or SiGeC (not shown) alloy with high-Ge percentage may be performed to provide sufficient chemical contrast for selective etching of a pure silicon layer.
P A T E N T Docket No. QS2090 [00657] Referring to FIG. 21.3, the process 3300 may include deposition of a first dielectric 306 (e.g., SiO
2) upon ultrathin layer 305 to serve as a hard mask for etching, at 3310 (FIG.33A). [00658] Referring to FIG.21.4, the process 3300 may include patterned etch of dielectric 306 and ultrathin substrate 305 with (111) surface orientation, stopping on a marker layer on ultrathin substrate 304 with (110) surface orientation, at 3312 (FIG.33A). The process 3300 may include selective etch of dielectric 306 against silicon, at 3314 (FIG.33A). When dielectric 306 is SiO
2, the selective etch may be against silicon. The process 3300 may include deposition of the first dielectric 306 (e.g., SiO
2) to serve as a hard mask for etching, at 3316 (FIG.33A). [00659] Referring to FIG.21.5, the process 3300 may include patterned etch of dielectric 306 and ultrathin substrate 304 with (110) surface orientation, stopping on a marker layer on the substrate 300, which has (001) surface orientation, at 3318 (FIG.33A). The process 3300 may include selective etch of dielectric 306, at 3320 (FIG. 33B). When dielectric 306 is SiO
2, the selective etch may be against silicon. [00660] Referring to FIG.21.6, the process 3300 may include deposition of dielectric 306 (e.g., SiO
2) and a thin film of a second dielectric 307, which may be a different material than dielectric 306 (e.g., Si
3N
4), at 3322 (FIG.33B). The combined thickness of these two films 306 and 307 may be approximately the thickness of the epitaxial films to be grown, for example 1 μm. [00661] Referring to FIG.21.7, the process 3300 may include patterned etch of dielectric films 306 and 307, which may be selective against Si, stopping on ultrathin substrate 305 with (1 11) surface orientation, to form a first opening 331, at 3324 (FIG.33B). [00662] Referring to FIG. 21.8, the process 3300 may include deposition and etchback, which may be selective against Si, of the second thin dielectric film 307 (e.g., Si
3N
4), to form spacers covering side walls of the first opening 331, at 3326 (FIG.33B). [00663] Referring to FIG.21.9, the process 3300 may include selective epitaxial growth of a film 308 strained to Si (111) in the first opening 331, at 3328 (FIG.33B). [00664] Referring to FIG.21.10, the process 3300 may include deposition of a thin film of the second dielectric 307 (e.g., Si
3N
4), at 3330 (FIG.33B). [00665] Referring to FIG.21.11, the process 3300 may include patterned etch of dielectric films 306 and 307, which may be selective against Si, stopping on ultrathin substrate 304 with (1 10) surface orientation, to form a second opening 332, at 3332 (FIG.33B).
P A T E N T Docket No. QS2090 [00666] Referring to FIG.21.12, the process 3300 may include deposition and etchback, which may be selective against Si, of second thin dielectric film 307 (e.g., Si
3N
4), to form spacers covering the side walls of the second opening 332, at 3334 (FIG.33B). [00667] Referring to FIG.21.13, the process 3300 may include selective epitaxial growth of a film 309 strained to Si (110) in the second opening 332, at 3336 (FIG.33B). [00668] Referring to FIG.21.14, the process 3300 may include deposition of a thin film of the second dielectric 307 (e.g., Si
3N
4), at 3338 (FIG.33C). [00669] Referring to FIG.21.15, the process 3300 may include patterned etch of dielectric films 306 and 307, which may be selective against Si, stopping on substrate with (001) surface orientation to form a third cavity 333, at 3340 (FIG.33C). [00670] Referring to FIG.21.16, the process 3300 may include deposition and etchback, which may be selective against Si, of the second dielectric film 307 (e.g., Si
3N
4), to form spacers covering the side walls of the third cavity 333, at 3342 (FIG.33C). [00671] Referring to FIG.21.17, the process 3300 may include selective epitaxial growth of a film 310 strained to Si (001) in the third cavity 333, at 3344 (FIG.33C). [00672] Referring to FIG.21.18, the process 3300 may include selective etch, which may be against Si, of the thin films 306 and 307 (e.g., Si
3N
4, SiO
2 and again Si
3N
4), at 3346 (FIG.33C). [00673] Referring to FIG. 21.19, the process 3300 may include deposition of the first dielectric 306 (e.g., SiO
2) and planarization of the back side 302 of the wafer 300, at 3348 (FIG. 33C). [00674] Referring to FIG. 21.20, the process 3300 may then include deposition of a thin film of the second dielectric 307 (e.g., Si
3N
4), at 3350 (FIG. 33C). The process 3300 may then include bonding of the back side 303 of the wafer 300 to a second wafer carrier 313, at 3352 (FIG. 33C). [00675] Referring to FIG.21.21, the process 3300 may include debonding/removal of the first wafer carrier 303 to expose the front side 301 of the wafer 300, at 3354 (FIG.33C). [00676] Referring to FIG.21.22, the process 3300 may include executing CMOS FEOL & BEOL processing on the front side 301 of the wafer 300, which may include Cu bumps for 3D wafer-scale integration, at 3356 (FIG. 33C). This figure shows the typical Transfer-Gate 317 N- MOSFETs, threshold implant (VT) 318, Floating Diffusion implant 320, Photo-Dipde (PD) implant 315, top surface pinning layer 316, spacers 319, metal contact to the Transfer-Gate 322, metal contact to
P A T E N T Docket No. QS2090 Floating Diffusion 323, shallow trench isolation (STI) 314, Pre-Metal Dielectric layer (321), and full metallization stack 324. [00677] Referring to FIG.21.23, the process 3300 may include wafer-on-wafer 3D hybrid Cu-Cu bonding of the wafer 300 with a CMOS circuitry wafer 325 (which may include Cu bumps), at 3358 (FIG.33D). [00678] Referring to FIG.21.24, the process 3300 may include debonding/removal of the second wafer carrier 313 to expose the passivation layer of the back side 302 of the wafer 300, made of the second dielectric 307 (e.g., Si
3N
4) on epitaxial films, at 3360 (FIG.33D). [00679] Referring to FIG.21.25, the process 3300 may include creating a deep trench 326 by patterned etch of deep trench isolation, through the Si
3N
4, SiO
2 between epitaxial films, stopping on shallow trench isolation made on the front side 301 of the wafer 300, at 3362 (FIG. 33D). [00680] Referring to FIG.21.26, the process 3300 may include selective etch of dielectrics 306 and 307, (e.g., Si
3N
4 and SiO
2) between epitaxial films 308, 309, and 310, to form a fourth cavity 334, at 3364 (FIG.33D). [00681] Referring to FIG.21.27, the process 3300 may include epitaxial deposition, at low temperature, of pinning layer 327, which may be p-type, surrounding the epitaxial mesa structures 308, 309, and 310, and along the sidewalls of the deep trenches 326, at 3366 (FIG. 33D). [00682] Referring to FIG. 21.28, the process 3300 may include deposition of the first dielectric 306 (e.g., SiO
2) and wafer-level planarization, at 3368 (FIG.33D). [00683] Referring to FIG.21.29, the process 3300 may include deposition of passivation and/or anti-reflection coating (ARC) 328, at 3370 (FIG.33D). [00684] Referring to FIG.21.30, the process 3300 may include fabrication of color filters 329 and microlenses 330, at 3372 (FIG.33D). The color filters 329 and microlenses 330 may be conventional. [00685] 2.2 Second Process Integration Architecture [00686] In the second process integration architecture, the epitaxial growth, and optional bonding of ultrathin substrate layers with different crystallographic orientations, on the back side of the wafer, is performed after FEOL processing of CMOS devices on the front side of the wafer, but before processing of BEOL, and even before silicide, on the front side of the wafer.
P A T E N T Docket No. QS2090 [00687] By performing the epitaxial growth after most of the FEOL processing, stopping just before silicide formation, the FEOL steps before the epitaxial growth on the back side of the wafer can be executed at conventional temperatures, not constrained by the strain and doping profiles in the epitaxial layers. Only silicide formation needs to be done at low temperature, which has been standard in FinFET CMOS technologies, for example with nickel silicide. With the current state of the art surface preparation for epitaxial growth, and the epitaxial growth itself being performed at low temperatures, for example below 500 °C, the processing on the back side of the wafer is compatible with the existence of current and future CMOS device technology on the front side of the wafer. Multiple variants of this process architecture can be derived by making trivial modifications to the sequence and/or order of process steps and modules. [00688] FIGs.34A,B depict a flowchart illustrating a process 3400 for fabricating a CMOS- integrated optoelectronic and/or thermoelectric device using the second process integration architecture, according to some embodiments of the disclosed technologies. [00689] Referring to FIG.34A, the process 3400 may include executing FEOL on the front side of the wafer, stopping just before silicide, at 3402. [00690] The process 3400 may include bonding the front side of the wafer to a first wafer carrier, at 3404. The wafer carrier may be covered with any interface layer that is suitable for the purposes of bonding and debonding, having compatibility with the wafer thinning steps and the process steps related to the epitaxial growth. [00691] The process 3400 may include thinning of the back side of the wafer, at 3406. [00692] The process 3400 may include executing deep trench isolation from the back side, forming pinning layers on the side walls of trenches, and optical isolation, at 3408. [00693] The process 3400 may include bonding one or multiple ultrathin layers of silicon with different crystallographic orientations to the back side of the thinned wafer, at 3410. [00694] The process 3400 may include patterning the back side of wafer to expose selected crystallographic orientations, at 3412. [00695] The process 3400 may include executing the "Epitaxial Module" described above one or more times, at 3414. [00696] The process 3400 may include execute one or more patterning steps, depositions and etches, etc., to nanostructure the epitaxially grown films, and/or to fabricate devices incorporating said epitaxial films, at 3416.
P A T E N T Docket No. QS2090 [00697] Referring to FIG.34B, the process 3400 may include wafer-level planarization of back side, at 3418. [00698] The process 3400 may include fabrication of other BSI devices, at 3420. These devices may include non-conventional microlenses, such as the GRIN microlenses described earlier, color routers, polarization routers, as well as other optional all-dielectric or metaldielectric optical/photonic devices, and that are compatible with subsequent processing (FEOL and BEOL) on the front side of the wafer. [00699] The process 3400 may include bonding the back side of the wafer to a transparent substrate, at 3422. [00700] The process 3400 may include debonding of the first wafer carrier from the front side of the wafer, at 3424. [00701] The process 3400 may include executing, on the front side of the wafer, the rest of FEOL, including silicide, and BEOL, at 3426. [00702] The process 3400 may include bonding the front side of the wafer with a circuitry wafer, preferably with 3D hybrid Cu-Cu bonding, at 3428. [00703] The process 3400 may include fabrication of color filters and microlenses, at 3430. The color filters and microlenses may be conventional. [00704] The process 3400 may include wafer-level packaging, at 3432. [00705] FIGs. 22.1-22.29 illustrate a process for fabricating a CMOS-integrated optoelectronic and/or thermoelectric device using the second process integration architecture, according to some embodiments of the disclosed technologies. [00706] FIGs.35A-E depicta flowchart illustrating a process 3500 for fabricating a CMOS- integrated optoelectronic and/or thermoelectric device using the second process integration architecture, according to some embodiments of the disclosed technologies. Process 3500 is now described with reference to FIGs.22.1-22.29. [00707] The process 3500 may include starting FEOL, at 3502 (FIG.35A). FEOL may be a standard CMOS process. The process 3500 may include stopping FEOL just before silicide formation, at 3504 (FIG.35A). The process 3500 may include bonding of the front side 301 of the wafer 300 to a first wafer carrier 303, at 3506 (FIG.35A). The process 3500 may include thinning of the back side 302 of the wafer 300, at 3508 (FIG.35A). FIG.22.1 illustrates the result of these processes.
P A T E N T Docket No. QS2090 [00708] The process 3500 may include bonding of an ultrathin n-type lowly doped silicon layer 304 having (110) surface orientation, at 3510 (FIG. 35A). The ultrathin layer 304 may be around 10 nm thick. If this optional bonding takes place, then an optional epitaxial growth of ultrathin layer (e.g., 2 nm or less) of Ge or SiGe or SiGeC alloy with high-Ge percentage may be performed to provide sufficient chemical contrast for selective etching of a pure silicon layer. [00709] Referring to FIG. 22.2, the process 3500 may include bonding of an ultrathin n- type lowly doped silicon layer 305 having (1 1 1) surface orientation, at 3512 (FIG. 35A). The ultrathin layer 305 may be around 10 nm thick. If this optional bonding takes place, then an optional epitaxial growth of ultrathin layer (e.g., 2 nm or less) of Ge or SiGe or SiGeC (not shown in figures) alloy with high-Ge percentage may be performed to provide sufficient chemical contrast for selective etching of a pure silicon layer. [00710] Referring to FIG. 22.3, the process 3500 may include deposition of a first dielectric 306 (e.g., SiO
2) to serve as a hard mask for etching, at 3514 (FIG.35A). [00711] Referring to FIG. 22.4, the process 3500 may include patterned etch of the first dielectric 306 and the ultrathin substrate 305 with (1 1 1) surface orientation, stopping on a marker layer on the ultrathin substrate with 304 (110) surface orientation, at 3516 (FIG.35A). [00712] The process 3500 may include selective etch of the first dielectric 306 (SiO
2), which may be against silicon, at 3518 (FIG.35A). [00713] The process 3500 may include deposition of the first dielectric 306 (e.g., SiO
2) to serve as a hard mask for etching, at 3520 (FIG.35B). [00714] Referring to FIG.22.5, the process 3500 may include patterned etch of the first dielectric 306 and the ultrathin substrate 304 with (1 1 0) surface orientation, stopping on a marker layer on the substrate 300 with (001) surface orientation, at 3522 (FIG.35B). [00715] The process 3500 may include selective etch of the first dielectric 306 (e.g., SiO
2), which may be against silicon, at 3524 (FIG.35B). [00716] Referring to FIG. 22.6, the process 3500 may include deposition of the first dielectric 306 (e.g., SiO
2) and a thin film of a second dielectric 307, which may be a different material (e.g., Si
3N
4) than dielectric 306, at 3526 (FIG.35B). The combined thickness of these two films 306 and 307 may be approximately the thickness of the epitaxial films to be grown, for example 1 μm.
P A T E N T Docket No. QS2090 [00717] Referring to FIG. 22.7, the process 3500 may include patterned etch of the dielectric films 306 and 307, which may be selective against Si, stopping on the ultrathin substrate 305 with (111) surface orientation, to form a first opening 331, at 3528 (FIG.35B). [00718] Referring to FIG. 22.8, the process 3500 may include deposition and etchback, which may be selective against Si, of the second dielectric film 307 (e.g., Si
3N
4), to form spacers covering the side walls of the first opening 331, at 3530 (FIG.35B). [00719] Referring to FIG.22.9, the process 3500 may include selective epitaxial growth of a film 308 strained to Si (111) in the first opening 331, at 3532 (FIG.35B). [00720] Referring to FIG.22.10, the process 3500 may include deposition of a thin film of the second dielectric 307 (e.g., Si
3N
4), at 3534 (FIG.35B). [00721] Referring to FIG. 22.11, the process 3500 may include patterned etch of the dielectric films 306 and 307, which may be selective against Si, stopping on the ultrathin substrate 304 with (110) surface orientation, to form a second opening 332, at 3536 (FIG.35C). [00722] Referring to FIG.22.12, the process 3500 may include deposition and etchback, which may be selective against Si, of the second thin dielectric film 307 (e.g., Si
3N
4), to form spacers covering the side walls of the second opening 332, at 3538 (FIG.35C) [00723] Referring to FIG.22.13, the process 3500 may include selective epitaxial growth of a film 309 strained to Si (110) in the second opening 332, at 3540 (FIG.35C). [00724] Referring to FIG.22.14, the process 3500 may include deposition of a thin film of the second dielectric 307 (i.e., Si
3N
4), at 3542 (FIG.35C). [00725] Referring to FIG. 22.15, the process 3500 may include patterned etch of the dielectric films 306 and 307, which may be selective against Si, stopping on substrate with (00 1) surface orientation, to form a third cavity 333, at 3544 (FIG.35C). [00726] Referring to FIG.22.16, the process 3500 may include deposition and etchback, which may be selective against Si, of a thin film of the second dielectric 307 (e.g., Si
3N
4), to form spacers covering the side walls of the third cavity 333, at 3546 (FIG.35C). [00727] Referring to FIG.22.17, the process 3500 may include selective epitaxial growth of a film 310 strained to Si (001) in the third cavity 333, at 3548 (FIG.35C). [00728] Referring to FIG.22.18, the process 3500 may include selective etch, which may be against Si, of the dielectric films 306 and 307 (e.g., Si
3N
4, SiO
2 and again Si
3N
4), at 3550 (FIG. 35C).
P A T E N T Docket No. QS2090 [00729] Referring to FIG. 22.19, the process 3500 may include deposition of the first dielectric 306 (e.g., SiO
2) and planarization of the back side 302 of the wafer 300, at 3552 (FIG. 35D). [00730] The process 3500 may include deposition of a thin film of the second dielectric 307 (e.g., Si
3N
4), at 3554 (FIG.35D). [00731] Referring to FIG.22.20, the process 3500 may include bonding the back side 302 of the wafer 300 to a second wafer carrier 313, at 3556 (FIG.35D). [00732] Referring to FIG.22.21, the process 3500 may include debonding/removal of the first wafer carrier 303, to expose the front side 301 of the wafer 300, at 3558 (FIG.35D). [00733] Referring to FIG. 22.22, the process 3500 may include executing silicide formation & BEOL processing on the front side 301 of the wafer 300, including Cu bumps for 3D wafer-scale integration, at 3560 (FIG.35D). [00734] The process 3500 may include wafer-on-wafer 3D hybrid Cu-Cu bonding of the wafer 300 with a CMOS circuitry wafer 325 (also with Cu bumps), at 3562 (FIG.35D). [00735] Referring to FIG.22.23, the process 3500 may include debonding/removal of the second wafer carrier 313 to expose the passivation layer of the back side 302 of the wafer 300, made of the second dielectric 307 (e.g., Si
3N
4) on epitaxial films, at 3564 (FIG.35D). [00736] Referring to FIG.22.24, the process 3500 may include creating a deep trench 326 patterned etch of deep trench isolation, through the Si
3N
4, SiO
2 between epitaxial films, stopping on shallow trench isolation made on the front side 301 of the wafer 300, at 3566 (FIG.35D). [00737] Referring to FIG. 22.25, the process 3500 may include selective etch of the dielectrics 306 and 307 (e.g., Si
3N
4 and SiO
2) between epitaxial films 308, 309, and 310, to form a fourth cavity 334, at 3568 (FIG.35D). [00738] Referring to FIG.22.26, the process 3500 may include epitaxial deposition, at low temperature, of pinning layer 327, which may be p-type, surrounding the epitaxial mesa structures 308, 309, and 310, and along the sidewalls of the deep trenches 326, at 3570 (FIG. 35E). [00739] Referring to FIG. 22.27, the process 3500 may include deposition of the first dielectric 306 (e.g., SiO
2) and wafer-level planarization, at 3572 (FIG.35E). [00740] Referring to FIG.22.28, the process 3500 may include deposition of passivation and/or anti-reflection coating (ARC) 328, at 3574 (FIG.35E).
P A T E N T Docket No. QS2090 [00741] Referring to FIG.22.29, the process 3500 may include fabrication of color filters 329 and microlenses 330, at 3576 (FIG. 35E). The color filters and microlenses may be conventional. [00742] 2.3 Third Process Integration Architecture [00743] The third process integration architecture, the epitaxial growth, and optional bonding of thin layers with different crystallographic orientations, on the back side of the wafer, is performed after FEOL and after BEOL processing of CMOS devices on the front-side of the wafer. Compared with the other integration architectures, this integration architecture is simpler to execute, has fewer risks regarding the integrity of the epitaxial heterojunction layers, and has minimal interaction (if any) with the processing of standard CIS BSI wafers. [00744] This process architecture assumes that the processing related to formation of the epitaxial films, and subsequent processing, on the back side of the wafer, can be executed at temperatures that are low enough to be done after BEOL on the front side of the wafer. As mentioned earlier, an exemplary value for such a low temperature could be below 500 °C. This low temperature enables the standard processing of FEOL and BEOL of a CIS-BSI process, and even (optionally) after 3D hybrid Cu-Cu bonding of the front side of the wafer to a circuitry wafer. Since the processing associated with the epitaxial films is done after execution of FEOL & BEOL, it can be immediately followed by formation of conventional color filters and/or conventional microlenses, or non-conventional GRIN microlenses, color filters or color routers, as well as other optional all-dielectric or metaldielectric optical/photonic devices, such as polarization routers and flat system lenses. Multiple variants of this process architecture can be derived by making trivial modifications to the sequence of process modules and order of process steps. [00745] FIGs.36A,B depict a flowchart illustrating a process 3600 for fabricating a CMOS- integrated optoelectronic and/or thermoelectric device using the third process integration architecture, according to some embodiments of the disclosed technologies. [00746] Referring to FIG.36A, the process 3600 may include executing FEOL on the front side of the wafer, at 3602. [00747] The process 3600 may include executing BEOL on the front side of the wafer, at 3604. [00748] The process 3600 may include permanent 3D hybrid Cu-Cu bonding of the front side of wafer to a circuitry wafer, at 3606. [00749] The process 3600 may include thinning of the back side of the wafer, at 3608.
P A T E N T Docket No. QS2090 [00750] The process 3600 may include executing standard BSI back side processing on the back side surface of substrate, stopping before formation of a pinning layer, at 3610. The BSI back side processing may include deep trench isolation, pinning layer on side walls inside deep trenches, and optical isolation inside deep trenches. [00751] The process 3600 may include bonding of one or multiple ultrathin layers of silicon with different crystallographic orientations to the back side of the thinned wafer, at 3612. [00752] The process 3600 may include patterning the back side of the wafer to expose selected crystallographic orientations, at 3614. [00753] The process 3600 may include executing the "Epitaxial Module" described above one or more times, at 3616. [00754] Referring to FIG.36B, the process 3600 may include executing patterning steps, depositions, and etches one or more times to nanostructure the epitaxially grown films, and/or to fabricate devices incorporating said epitaxial films, at 3618. [00755] The process 3600 may include patterning steps, depositions and etches, to fabricate BSI devices, at 3620. The BIS devices may include resonant cavity structures, light- absorption devices, and the like. [00756] The process 3600 may include wafer-level planarization of the back side of the wafer, at 3622. [00757] The process 3600 may include fabrication of color filters and microlenses, at 3624. The color filters and microlenses may be conventional. [00758] The process 3600 may include fabrication of other BSI devices, at 3626. These devices may include non-conventional microlenses, color routers, as well as other optional all- dielectric or metaldielectric optical/photonic devices, such as polarization routers and system flat lenses. [00759] The process 3600 may include wafer-level packaging, at 3628. [00760] FIGs. 23.1-23.38 illustrate a process for fabricating a CMOS-integrated optoelectronic and/or thermoelectric device using the third process integration architecture, according to some embodiments of the disclosed technologies. [00761] FIGs.37A-F depict a flowchart illustrating a process 3700 for fabricating a CMOS- integrated optoelectronic and/or thermoelectric device using the third process integration
P A T E N T Docket No. QS2090 architecture, according to some embodiments of the disclosed technologies. Process 3700 is now described with reference to FIGs.23.1-23.38. [00762] Referring to FIG. 23.1, the process 3700 may include executing standard processing of the BSI wafer 300, including permanent 3D hybrid Cu-Cu bonding of the front side 301 of the wafer 300 to a circuitry wafer 325, and thinning the back side 302 of the wafer 300, at 3702 (FIG.37A). [00763] The process 3700 may include executing standard BSI back side processing, stopping before formation of a pinning layer on the back side surface of substrate, at 3704 (FIG. 37A). The standard BSI back side processing may include deep trench isolation, pinning layer on side walls inside deep trenches, and optical isolation inside the deep trenches. [00764] The process 3700 may include bonding of an ultrathin n-type lowly doped silicon layer 304 having (110) surface orientation, at 3706 (FIG. 37A). The ultrathin layer 304 may be around 10 nm thick. If this optional bonding takes place, then an optional epitaxial growth of ultrathin layer (e.g., 2 nm or less) of Ge or SiGe or SiGeC alloy with high-Ge percentage may be performed to provide sufficient chemical contrast for selective etching of a pure silicon layer. [00765] Referring to FIG. 23.2, the process 3700 may include bonding of an ultrathin n- type lowly doped silicon layer 305 having (1 1 1) surface orientation, at 3708 (FIG. 37A). The ultrathin layer 305 may be around 10 nm thick. If this optional bonding takes place, then an optional epitaxial growth of ultrathin layer (e.g., 2 nm or less) of Ge or SiGe or SiGeC (not shown in figures) alloy with high-Ge percentage may be performed to provide sufficient chemical contrast for selective etching of a pure silicon layer. [00766] Referring to FIG. 23.3, the process 3700 may include deposition of a first dielectric 306 (e.g., SiO
2) to serve as a hard mask for etching, at 3710 (FIG.37A). [00767] Referring to FIG. 23.4, the process 3700 may include patterned etch of the dielectric 306 and the ultrathin substrate 305 with (1 1 1) surface orientation, stopping on a marker layer on the ultrathin substrate 304 with (110) surface orientation, at 3712 (FIG. 37A). The process 3700 may include selective etch of the first dielectric 306 (e.g., SiO
2), which may be against silicon, at 3714 (FIG.37A). The process 3700 may include deposition of the first dielectric 306 (e.g., SiO
2) to serve as hard mask for etching, at 3716 (FIG.37A). [00768] Referring to FIG. 23.5, the process 3700 may include patterned etch of the first dielectric 306 and the ultrathin substrate 305 with (1 1 0) surface orientation, stopping on a marker layer on the substrate with (001) surface orientation, at 3718 (FIG.37B).
P A T E N T Docket No. QS2090 [00769] The process 3700 may include selective etch of the first dielectric 306 (e.g., SiO
2), which may be against silicon, at 3720 (FIG.37B). [00770] Referring to FIG. 23.6, the process 3700 may include deposition of the first dielectric 306 (e.g., SiO
2) and a thin film of a second dielectric 307, which may be a different material (e.g., Si
3N
4) than dielectric 306, at 3722 (FIG.37B). The combined thickness of these two films may be approximately the thickness of the epitaxial films to be grown, for example 1 μm. [00771] Referring to FIG. 23.7, the process 3700 may include patterned etch of the dielectric films 306 and 307, which may be selective against Si, stopping on ultrathin substrate 305 with (111) surface orientation, to form a first opening 331, at 3724 (FIG.37B). [00772] Referring to FIG. 23.8, the process 3700 may include deposition and etchback, which may be selective against Si, of the thin film of the second dielectric 307 (e.g., Si
3N
4), to form spacers covering the side walls of the first opening 331, at 3726 (FIG.37B). [00773] Referring to FIG.23.9, the process 3700 may include selective epitaxial growth of a film 308 strained to Si (111) in the first opening 331, at 3728 (FIG.37B). The film 308 may include a separate photo-absorption region and a charge multiplication region. [00774] Referring to FIG.23.10, the process 3700 may include deposition of a thin film of the second dielectric 307 (e.g., Si
3N
4), at 3730 (FIG.37B). [00775] Referring to FIG. 23.11, the process 3700 may include patterned etch of the dielectric films 306 and 307, which may be selective against Si, stopping on ultrathin substrate 304 with (110) surface orientation, to form a second opening 332, at 3732 (FIG.37B). [00776] Referring to FIG.23.12, the process 3700 may include deposition and etchback, which may be selective against Si, of the thin film of the second dielectric 307 (e.g., Si
3N
4), to form spacers covering the side walls of the second opening 332, at 3734 (FIG.37C). [00777] Referring to FIG.23.13, the process 3700 may include selective epitaxial growth of a film 309 strained to Si (110) in the second opening 332, at 3736 (FIG.37C). The film 309 may include a separate photo-absorption region and a charge multiplication region. [00778] Referring to FIG.23.14, the process 3700 may include deposition of a thin film of the second dielectric 307 (i.e., Si
3N
4), at 3738 (FIG.37C). [00779] Referring to FIG. 23.15, the process 3700 may include patterned etch of the dielectric films 306 and 307, which may be selective against Si, stopping on the substrate with (0 01) surface orientation, to form a third cavity 333, at 3740 (FIG.37C).
P A T E N T Docket No. QS2090 [00780] Referring to FIG.23.16, the process 3700 may include deposition and etchback, which may be selective against Si, of a thin film of the second dielectric 307 (e.g., Si
3N
4), to form spacers covering the side walls of the third cavity 333, at 3742 (FIG.37C). [00781] Referring to FIG.23.17, the process 3700 may include selective epitaxial growth of a film 310 strained to Si (001) in the third cavity 333, at 3744 (FIG. 37C). The film 310 may include a photo-absorption region. [00782] Referring to FIG.23.18, the process 3700 may include selective etch, which may be against Si, of the dielectric films 306 and 307 (e.g., Si
3N
4, SiO
2 and again Si
3N
4), at 3746 (FIG. 37C). [00783] Referring to FIG.23.19, the process 3700 may include patterning of the epitaxial films 337 and 338 in the first pixel 353.1 to form a nanowire of both the photo-absorption region 338 and the charge multiplication region 337, at 3748 (FIG.37C). An alternative to the nanowire is a quantum dot. [00784] Referring to FIG.23.20, the process 3700 may include patterning of the epitaxial films in the second pixel 353.2 to form a nanowire of the photo-absorption region 340, with no patterning of the charge multiplication region 339, at 3750 (FIG. 37D). An alternative to the nanowire is a quantum dot. [00785] Referring to FIG. 23.21, the process 3700 may include epitaxial deposition of a highly doped p-type pinning layer 327 over all pixels 125-127 including those without epitaxial layers, at 3752 (FIG.37D). [00786] Referring to FIG. 23.22, the process 3700 may include deposition of the first dielectric 306 (e.g., SiO
2) and planarization of the back side 302 of the wafer 300, at 3754 (FIG. 37D). [00787] The process 3700 may include deposition of the first dielectric 306 (e.g., SiO
2) and a thin film of the second dielectric 307 (e.g., Si
3N
4), at 3756 (FIG.37D). [00788] Referring to FIG. 23.23, the process 3700 may include patterning of selected pixels (e.g., pixels 353.1 and 353.2) to fabricate p-type thermoelectric converters (TECs), with selective etching of the first dielectric 306 (e.g., SiO
2) and the thin film of the second dielectric 307 (e.g., Si
3N
4), stopping on the pinning layer 327 of the selected pixels, to form first openings 343, at 3758 (FIG.37D).
P A T E N T Docket No. QS2090 [00789] Referring to FIG.23.24, the process 3700 may include deposition and etchback, which may be selective against Si, of the thin film of the second dielectric 307 (e.g., Si
3N
4), to form spacers covering the side walls of the openings 343, at 3760 (FIG.37D). [00790] Referring to FIG.23.25, the process 3700 may include selective epitaxial growth of lowly n-type doped film and highly doped n-type film 341, followed by the p-type TEC layers, at 3762 (FIG.37D). [00791] Referring to FIG.23.26, the process 3700 may include deposition of a thin film of the second dielectric 307 (e.g., Si
3N
4), at 3764 (FIG.37D). [00792] Referring to FIG. 23.27, the process 3700 may include patterning of selected pixels (e.g., pixels 125 and 126) to fabricate n-type thermoelectric converters (TECs), with selective etching of the thin film of the first dielectric 306 (e.g., SiO
2) and the thin film of the second dielectric 307 (e.g., Si
3N
4), stopping on the pinning layer 327 of selected pixels, to form second openings 344, at 3766 (FIG.37E). [00793] Referring to FIG.23.28, the process 3700 may include deposition and etchback, which may be selective against Si, of the thin film of the second dielectric 307 (e.g., Si
3N
4), to form spacers covering the side walls of the second openings 344, at 3768 (FIG.37E). [00794] Referring to FIG.23.29, the process 3700 may include selective epitaxial growth of lowly n-type doped film and highly doped n-type film 342, followed by the n-type TEC layers, at 3770 (FIG.37E). [00795] The process 3700 may include unpatterned selective etch of the second dielectric 307 (e.g., Si
3N
4) to expose the surface of the p-type TEC layers 345 and 346, while leaving some of the second dielectric 307 (e.g., Si
3N
4) thickness over the surfaces of the first dielectric 306 (e.g., SiO
2), at 3772 (FIG.37E). [00796] Referring to FIG.23.30, the process 3700 may include patterning of p-type and n- type TEC layers 345 and 346 into nanowires, at 3774 (FIG. 37E). The nanowires may have embedded quantum dots. [00797] Referring to FIG. 23.31, the process 3700 may include deposition of the first dielectric 306 (e.g., SiO
2) and planarization, using the remaining thin second dielectric 307 (e.g., Si
3N
4) as a marker layer, at 3776 (FIG.37E). [00798] Referring to FIG.23.32, the process 3700 may include selective etch of the first dielectric 306 (e.g., SiO
2) to form contact holes to the top electrode of the TECs 345 and 346, using the top of the TECs as end point markers, at 3778 (FIG.37E).
P A T E N T Docket No. QS2090 [00799] Referring to FIG.23.33, the process 3700 may include silicide formation and filling of the contact holes with metal, followed by planarization, at 3780 (FIG.37F). [00800] Referring to FIG.23.34, the process 3700 may include fabrication of metal lines 348 providing electrical connections between the thermoelectric converters 345 and 346 and control elements (not shown), at pixel-level, row-level, column-level, or matrix-level, which control the mode of operation of the thermoelectric converters, for cooling or for energy harvesting, at 3782 (FIG.37F). [00801] Referring to FIG.23.35, the process 3700 may include deposition of a thin layer of the first dielectric 306 (e.g., SiO
2) and one or more layers 349 of dielectrics and optionally also metals to fabricate pixel-level GRIN microlenses capable of focusing light to subwavelength dimensions, at 3784 (FIG.37F). [00802] Referring to FIG.23.36, the process 3700 may include patterned selective etch of geometric shapes into the one or more layers 349 deposited on the thin layer of the first dielectric 306 (e.g., SiO
2), at 3786 (FIG. 37F). The geometric shapes may be determined by the desired functionality of the pixel-level GRIN microlenses. Instead of a single deposition and patterning step cutting through all layers, it would be straightforward to have multiple deposition and patterning steps cutting through different sets of layers. [00803] Referring to FIG. 23.37, the process 3700 may include fabrication of a 3D metaoptics layer 351, at 3788 (FIG. 37F). The 3D metaoptics layer 351 may be all-dielectric or metaldielectric. The 3D metaoptics layer 351 may provide the functionality of pixel-level color routing, and/or polarization routing, etc. This layer may be fabricated separately and then bonded to the surface with the GRIN lenses already made. [00804] Referring to FIG. 23.38, the process 3700 may include fabrication of a 3D metaoptics layer 352, at 3790 (FIG. 37F). The 3D metaoptics layer 352 may be all-dielectric or metaldielectric. The 3D metaoptics layer 352 may provide the functionality of a system flat lens. This layer may be fabricated separately and then bonded to the surface of the layer 351 providing the color routing, and/or polarization routing, etc. [00805] 2.4 Fourth Process Integration Architecture [00806] The fourth process integration architecture shares many of the features of the third process architecture. The main difference is the fabrication of direct metal contacts from the CMOS devices on the front side of the wafer to device layers fabricated on the back side of the wafer. This
P A T E N T Docket No. QS2090 architecture is preferred to contact LEDs, LASERs, as well as topological insulators, topological semimetals, and non-centrosymmetric crystals exhibiting the Bulk PhotoVoltaic Effect (BPVE). [00807] Although the fourth process architecture shares most of the features of the third process architecture, there are a few significant differences that are better classified as a different process architecture. The main point of differentiation is that the charge collection from photodetectors is made through direct metal contacts to the light-sensing materials/device, instead of having the photogenerated carriers travel through a region of lowly doped silicon, as is the case with standard pinned photodiodes. This architecture is suited for light-sensing with topological insulators, topological semimetals, non-centrosymmetric crystals exhibiting the Bulk PhotoVoltaic Effect (BPVE), light-sensing with metamaterials with negative index of refraction arising from negative permittivity, or negative permeability, or both simultaneously. It is also suitable for providing electrical power to LEDs and LASERs, in which light can be emitted by different physical effects, such as band-to-band transitions, or intersubband transitions within the conduction band, or intersubband transitions within the valence band, or intersubband transitions in the conduction and valence bands, or between quantized levels in quantum wells, quantum dots, quantum dots embedded in nanowires, quantum cascade transitions, etc. It can also be immediately followed by formation of, preferably, non- conventional GRIN microlenses, color filters or color routers, as well as other optional all- dielectric or metaldielectric optical/photonic devices. Multiple variants of this process architecture can be derived by making trivial modifications to the sequence of process modules and order of process steps. [00808] FIGs.38A,B depict a flowchart illustrating a process 3800 for fabricating a CMOS- integrated optoelectronic and/or thermoelectric device using the fourth process integration architecture, according to some embodiments of the disclosed technologies. [00809] Referring to FIG.38A, the process 3800 may include executing FEOL on the front side of the wafer, at 3802. The FEOL may include NMOS and PMOS in the same pixel. [00810] The process 3800 may include executing BEOL on the front side of the wafer, at 3804. [00811] The process 3800 may include permanent 3D hybrid Cu-Cu bonding of front side of the wafer to a circuitry wafer, at 3806. The circuitry wafer may be bonded to other circuit wafers, before or after the bonding to the wafer. [00812] The process 3800 may include thinning of the back side of the wafer, at 3808.
P A T E N T Docket No. QS2090 [00813] The process 3800 may include executing standard BSI back side processing, including deep trench isolation and optical isolation inside the deep trenches, at 3810. [00814] The process 3800 may include bonding of one or multiple ultrathin layers of silicon with different crystallographic orientations to back side of thinned wafer, at 3812. [00815] The process 3800 may include patterning of the back side 302 of the wafer to expose selected crystallographic orientations, at 3814. [00816] The process 3800 may include executing the "Epitaxial Module" described above one or more times, at 3816. [00817] Referring to FIG. 38B, the process 3800 may include executing once or more patterning steps, depositions and etches, to nanostructure the epitaxially grown films, and/or to fabricate devices incorporating said epitaxial films, at 3818. [00818] The process 3800 may include patterning steps, depositions and etches, to fabricate BIS structures/devices, at 3820. For example, the structures/devices may include resonant cavity structures, light-absorption devices, light-emission devices, light-modulation devices, and the like. [00819] The process 3800 may include wafer-level planarization of the back side of the wafer, at 3822. [00820] The process 3800 may include fabrication of wavelength (e.g., color) filters and microlenses. The filters and microlenses may be conventional, at 3824. [00821] The process 3800 may include fabrication of other BSI devices, at 3826. These devices may include non-conventional GRIN microlenses and color routers, as well as other all- dielectric or metaldielectric optical/photonic devices, such as polarization routers and system flat lenses. [00822] The process 3800 may include wafer-level packaging, at 3828. [00823] FIGs. 24.1-24.88 illustrate a process for fabricating a CMOS-integrated optoelectronic and/or thermoelectric device using the fourth process integration architecture, according to some embodiments of the disclosed technologies. [00824] FIGs.39A-L depict a flowchart illustrating a process 3900 for fabricating a CMOS- integrated optoelectronic and/or thermoelectric device using the fourth process integration architecture, according to some embodiments of the disclosed technologies. Process 3900 is now described with reference to FIGs.24.1-24.88.
P A T E N T Docket No. QS2090 [00825] The process 3900 may include executing standard processing of the BSI wafer 300, including permanent 3D hybrid Cu-Cu bonding of front side of wafer to a circuitry wafer 303, and thinning the back side of the wafer 300, at 3901 (FIG.39A). [00826] Referring to FIG.24.1, the process 3900 may include executing standard BSI back side processing, stopping before formation of a pinning layer on the back side 302 surface of the wafer 300, at 3902 (FIG.39A). The standard BSI back side processing may include deep trench isolation and optical isolation inside deep trenches. [00827] The process 3900 may include bonding of an ultrathin n-type lowly doped silicon layer 304 having (110) surface orientation, at 3903 (FIG. 39A). The ultrathin layer 304 may be around 10 nm thick. If this optional bonding takes place, then an optional epitaxial growth of ultrathin layer (e.g., 2 nm or less) of Ge or SiGe or SiGeC alloy with high-Ge percentage may be performed to provide sufficient chemical contrast for selective etching of a pure silicon layer. [00828] Referring to FIG. 24.2, the process 3900 may include bonding of an ultrathin n- type lowly doped silicon layer 305 having (1 1 1) surface orientation, at 3904 (FIG. 39A). The ultrathin layer 305 may be around 10 nm thick. If this optional bonding takes place, then an optional epitaxial growth of ultrathin layer (e.g., 2 nm or less) of Ge or SiGe or SiGeC (not shown in figures) alloy with high-Ge percentage may be performed to provide sufficient chemical contrast for selective etching of a pure silicon layer. [00829] Referring to FIG. 24.3, the process 3900 may include deposition of a first dielectric 306 (e.g., SiO
2) to serve as hard mask for etching, at 3905 (FIG.39A). [00830] Referring to FIG. 24.4, the process 3900 may include patterned etch of the first dielectric 306 and the ultrathin substrate 305 with (1 1 1) surface orientation, stopping on a marker layer on the ultrathin substrate 304 with (110) surface orientation, at 3906 (FIG.39A). [00831] The process 3900 may include selective etch of the first dielectric 306 (e.g., SiO
2), which may be against silicon, at 3907 (FIG.39A). [00832] The process 3900 may include deposition of the first dielectric 306 (e.g., SiO
2) to serve as hard mask for etching, at 3908 (FIG.39A). [00833] Referring to FIG. 24.5, the process 3900 may include patterned etch of the first dielectric 306 and the ultrathin substrate 304 with (1 1 0) surface orientation, stopping on a marker layer on the substrate with (001) surface orientation, at 3909 (FIG.39B). [00834] The process 3900 may include selective etch of the dielectric 306 (e.g., SiO
2), which may be against silicon, at 3910 (FIG.39B).
P A T E N T Docket No. QS2090 [00835] Referring to FIG. 24.6, the process 3900 may include deposition of the first dielectric 306 (e.g., SiO
2) and thin film of a second dielectric 307, which may be a different material (e.g., Si
3N
4) than dielectric 306, at 3911 (FIG.39B). The combined thickness of these two films may be approximately the thickness of the epitaxial films to be grown, for example 1 μm. [00836] Referring to FIG. 24.7, the process 3900 may include patterned etch of the dielectric films 306 and 307, which may be selective against Si, stopping on the ultrathin substrate 305 with (111) surface orientation, to form a first opening 331, at 3912 (FIG.39B). [00837] Referring to FIG. 24.8, the process 3900 may include deposition and etchback, which may be selective against Si, of the thin film of the second dielectric 307 (e.g., Si
3N
4), to form spacers covering the side walls of the first opening 331, at 3913 (FIG.39B). [00838] Referring to FIG.24.9, the process 3900 may include selective epitaxial growth of a film 308 strained to Si (111) in the first opening 331, at 3914 (FIG.39B). [00839] Referring to FIG.24.10, the process 3900 may include deposition of a thin film of the second dielectric 307 (e.g., Si
3N
4), at 3915 (FIG.39B). [00840] Referring to FIG. 24.11, the process 3900 may include patterned etch of the dielectric films 306 and 307, which may be selective against Si, stopping on the ultrathin substrate 304 with (110) surface orientation, to form a second opening 332, at 3916 (FIG.39B). [00841] Referring to FIG.24.12, the process 3900 may include deposition and etchback, which may be selective against Si, of the thin film of the second dielectric 307 (e.g., Si
3N
4), to form spacers covering the side walls of the second opening 332, at 3917 (FIG.39C). [00842] Referring to FIG.24.13, the process 3900 may include selective epitaxial growth of a film 309 strained to Si (110) in the second opening 332, at 3918 (FIG.39C). [00843] Referring to FIG.24.14, the process 3900 may include deposition of a thin film of the second dielectric 307 (i.e., Si
3N
4), at 3919 (FIG.39C). [00844] Referring to FIG. 24.15, the process 3900 may include patterned etch of the dielectric films 306 and 307, which may be selective against Si, stopping on the substrate with (0 01) surface orientation, to form a third opening 333, at 3920 (FIG.39C). [00845] Referring to FIG.24.16, the process 3900 may include deposition and etchback, which may be selective against Si, of a thin film of the second dielectric 307 (e.g., Si
3N
4), to form spacers covering the side walls of the third opening 333, at 3921 (FIG.39C).
P A T E N T Docket No. QS2090 [00846] Referring to FIG.24.17, the process 3900 may include selective epitaxial growth of a film 310 strained to Si (001) in the third opening 333, at 3922 (FIG.39C). [00847] Referring to FIG.24.18, the process 3900 may include deposition of a thin film of the second dielectric (e.g., Si
3N
4), at 3923 (FIG.39C). [00848] Referring to FIG. 24.19, the process 3900 may include patterned etch of the dielectric films 306 and 307, which may be selective against Si, stopping on the ultrathin substrate with (001) surface orientation, to form a fourth opening 334, at 3924 (FIG.39C). [00849] Referring to FIG.24.20, the process 3900 may include deposition and etchback, which may be selective against Si, of a thin film of the second dielectric 307 (e.g., Si
3N
4), to form spacers covering the side walls of the fourth opening 334, at 3925 (FIG.39D). [00850] Referring to FIG.24.21, the process 3900 may include selective epitaxial growth of a film 376 strained to Si (001), at 3926 (FIG.39D). [00851] Referring to FIG.24.22, the process 3900 may include deposition of a thin film of the second dielectric 307 (e.g., Si
3N
4), at 3927 (FIG.39D). [00852] Referring to FIG.24.23, the process 3900 may include patterned etch of dielectric films, which may be selective against Si, stopping on ultrathin substrate with (0 0 1) surface orientation, to form a fifth opening 343, at 3928 (FIG.39D). [00853] Referring to FIG.24.24, the process 3900 may include deposition and etchback, which may be selective against Si, of the thin dielectric film 307 (e.g., Si
3N
4), to form spacers covering the side walls of the fifth opening 343, at 3929 (FIG.39D). [00854] Referring to FIG.24.25, the process 3900 may include selective epitaxial growth of a film 379 strained to Si (001) in the fifth opening 343, at 3930 (FIG.39D). [00855] Referring to FIG.24.26, the process 3900 may include selective etch, which may be against Si and SiO
2, of the second dielectric 307 (e.g., Si
3N
4), at 3931 (FIG.39D). [00856] Referring to FIG.24.27, the process 3900 may include deposition of a thin film of the second dielectric 307 (e.g., Si
3N
4), at 3932 (FIG.39D). [00857] Referring to FIG.24.28, the process 3900 may include patterned selective etch, which may be against Si and SiO
2, of the second dielectric 307 (e.g., Si
3N
4), at 3933 (FIG.39D). [00858] Referring to FIG.24.29, the process 3900 may include patterning of the epitaxial films in pixel 354.1 to form a nanowire 380 of both the mirror layers "DBR" and the active light emission region, at 3934 (FIG.39E).
P A T E N T Docket No. QS2090 [00859] The process 3900 may include selective epitaxial growth of a P+ pinning layer 381 on the top and side walls of the nanowire 380, as well as on the surface of the N+ layer 374, at 3935 (FIG. 39E). The P+ pinning layer 381 forms a nanowire shell for the nanowire 380. The P+ pinning layer 381 is a highly conductive layer, for example highly n-type doped, or highly p-type doped, or highly codoped, n-type and p-type, Si, and/or SiGeC alloy. (p+ if 374 is n+ doped) [00860] Referring to FIG.24.30, the process 3900 may include patterning of the P+ pinning layer 381 in pixel 354.1, at 3936 (FIG.39E). [00861] Referring to FIG. 24.31, the process 3900 may include deposition of the first dielectric 306 (e.g., SiO
2) and planarization of the back side 302 of the wafer 300, at 3937 (FIG. 39E). [00862] Referring to FIG.24.,32 the process 3900 may include selective etch, which may be against Si and SiO
2, of the second dielectric 307 (e.g., Si
3N
4), at 3938 (FIG.39E). [00863] Referring to FIG.24.33, the process 3900 may include deposition of a sacrificial layer of the first dielectric 306 (e.g., SiO
2), at 3939 (FIG.39E). The thickness of this layer may be meant to determine the thickness of another material. [00864] Referring to FIG.24.34, the process 3900 may include patterned selective etch of the first dielectric 306 (e.g., SiO
2), to form a nano-trench 383 at the centers of pixel 354.2 and pixel 354.5, at 3940 (FIG.39E). [00865] Referring to FIG.24.35, the process 3900 may include deposition and etchback of the second dielectric 307 (e.g., Si
3N
4), to fill nano-trenches in pixel 354.2 and pixel 354.5, at 3941 (FIG.39E). This could also be achieved by deposition of Si
3N
4 followed by CMP. [00866] Referring to FIG.24.36, the process 3900 may include deposition of a thin film of the second dielectric 307 (e.g., Si
3N
4), at 3942 (FIG.39E). [00867] The process 3900 may include lithography to open a trench into the epitaxial films of pixel 354.5, in which one side of the trench is aligned at the center of the trench fill of the second dielectric 307 (e.g., Si
3N
4), at 3943 (FIG.39F). [00868] Referring to FIG.24.37, the process 3900 may include patterned etch of the first and second dielectrics 306 and 307 (e.g., SiO
2 and Si
3N
4), stopping when the epitaxial films 379 of pixel 354.5 become exposed, at 3944 (FIG.39F). [00869] Referring to FIG. 24.38, the process 3900 may include selective etch of the exposed epitaxial films 379 of pixel 354.5, to form top DBR (mirror) layers 385 and Electro-Optic
P A T E N T Docket No. QS2090 Modulator (EOM) layers 386, stopping at middle DBR (mirror) layers 387, at 3945 (FIG. 39F). Photoresists strip 384. [00870] Referring to FIG. 24.39, the process 3900 may include deposition of the first dielectric 306 (e.g., SiO
2) and planarization of the back side 302 of the wafer 300, at 3946 (FIG. 39F). [00871] Referring to FIG.24.40, the process 3900 may include patterned etch of the first dielectric 306 (e.g., SiO
2), to open a trench on the right-hand sides of the nano-pillars in pixel 354.5 and pixel 354.2, stopping when the middle DBR layers 387 of pixel 354.5 and the top DBR layers 385 of pixel 354.2 become exposed, at 3947 (FIG.39F). [00872] Referring to FIG.24.41, the process 3900 may include deposition of a photoresist strip 384 followed by the etch of the top DBR (mirror) layers 385 and the top half-cavity 388 of pixel 354.2, and the middle DBR (mirror) layers 387 and top half-cavity 388 of pixel 354.5, stopping on the LASER active layers 389 in both pixels 354.2 and 354.5, at 3948 (FIG.39F). [00873] Referring to FIG.24.42, the process 3900 may include deposition and etchback, which may be selective against the epitaxial layers 309 and 379, of the thin film of the second dielectric 307 (e.g., Si
3N
4), to form spacers covering the side walls of epitaxial layers 309 and 379 and the first dielectric 306 (e.g., SiO
2), at 3949 (FIG.39F). [00874] Referring to FIG. 24.43, the process 3900 may include etch, which may include lateral over-etch, of LASER active layers 389, which may be selective against the top half-cavity 388 and the bottom half-cavity 391 of both pixels 354.2 and 354.5. Depending on the amount of over-etch, the central region may become a quantum dot, as shown, at 3950 (FIG.39G). [00875] Referring to FIG.24.44, the process 3900 may include selective epitaxial grown of a P+ doped layer 392 (e.g., Si, and/or SiGeC alloy), making a lateral point of hole injection into the central quantum dot, at 3951 (FIG.39G). The P+ doped layer 392 may be highly p-type doped. [00876] Referring to FIG. 24.45, the process 3900 may include deposition of the first dielectric 306 (e.g., SiO
2) and planarization of the back side 302 of the wafer 300, at 3952 (FIG. 39G). [00877] Referring to FIG.24.46, the process 3900 may include deposition of a thin film of the second dielectric 307 (e.g., Si
3N
4), at 3953 (FIG.39G). [00878] The process 3900 may include lithography to open trenches into the epitaxial films 387 and 385 of pixels 354.2 and 354.5, respectively, in which one side of each trench is aligned at the center of the respective nano-trench fill of the second dielectric 307 (e.g., Si
3N
4) of
P A T E N T Docket No. QS2090 pixels 354.2 and 354.5, at 3954 (FIG.39G). These trenches may be parallel to the trenches shown in FIG.24.40, and are on the opposite side of the nano-trench fill. [00879] Referring to FIG.24.47, the process 3900 may include patterned etch of the first dielectric 306 (e.g., SiO
2) and the second dielectric 307 (e.g., Si
3N
4), stopping when the epitaxial films 387 and 385 become exposed, at 3955 (FIG.39G). [00880] Referring to FIG. 24.48, the process 3900 may include depositing a photoresist strip 384, at 3956 (FIG.39G). [00881] Referring to FIG.24.49, the process 3900 may include etch of the top DBR (mirror) layers 385 and the top half-cavity 388 of pixel 354.2, and the middle DBR (mirror) layers 387 and top half-cavity 388 of pixel 354.5, stopping on the LASER active layers 389 in both pixels 354.2 and 354.5, at 3957 (FIG.39G). [00882] Referring to FIG.24.,50 the process 3900 may include deposition and etchback, which may be selective against the epitaxial layers, of a thin film of the second dielectric 307 (e.g., Si
3N
4), to form spacers covering the side walls of the epitaxial layers and the first dielectric 306 (e.g., SiO
2), at 3958 (FIG.39G). [00883] Referring to FIG. 24.51, the process 3900 may include etch, which may include lateral over-etch, of the LASER active layers 389, which may be selective against the top half- cavity 388 and the bottom half-cavity 391 of both pixels 354.2 and 354.5. Depending on the amount of over-etch, the central region may become a quantum dot, at 3959 (FIG. 39H). Depending on the amount of over-etch, the central region may become a quantum dot, as shown. [00884] Referring to FIG.24.52, the process 3900 may include selective epitaxial growth of an N+ doped layer 393 (e.g., Si, and/or SiGeC alloy), making a lateral point of electron injection into the central quantum dot, at 3960 (FIG.39H). The N+ doped layer 393 may be highly n-type doped. [00885] Referring to FIG. 24.53, the process 3900 may include deposition of the first dielectric 306 (e.g., SiO
2) and planarization of the back side 302 of the wafer 300, at 3961 (FIG. 39H). [00886] The process 3900 may include lithography to open trenches into the epitaxial films, in which each trench 395 is made alongside the walls of pixels 354.2 and 354.5, stopping on the n-type and p-type doped layers 392 and 393 (e.g., Si and/or SiGeC), at 3962 (FIG. 39H). These trenches may be parallel to the trenches shown in FIG.24.40.
P A T E N T Docket No. QS2090 [00887] Referring to FIG.24.54, the process 3900 may include patterned selective etch of dielectric films 306 and 307 for pixels 354.2 and 354.5, stopping when the epitaxial films become exposed, at 3963 (FIG.39H). [00888] Referring to FIG. 24.55, the process 3900 may include selective etch of the epitaxial layers for pixels 354.2 and 354.5, at 396, stopping on marker layers (not shown) of the substrate 300, at 3964 (FIG.39H). [00889] Referring to FIG.24.56, the process 3900 may include selective lateral etch of the bottom DBR layers and bottom half-cavity of both pixels 354.2 and 354.5, at 397, which may be against the highly doped P+ and N+ layers 392 and 393, at 3965 (FIG.39H). [00890] Referring to FIG. 24.57, the process 3900 may include deposition of the first dielectric 306 (e.g., SiO
2) and planarization of the back side 302 of the wafer 300, at 3966 (FIG. 39H). [00891] Referring to FIG.24.58, the process 3900 may include patterned selective etch of holes 398 through the films of the first dielectric 306 (e.g., SiO
2) in pixels 354.2 and 354.5, stopping on the P+ epitaxial films 392, at 3967 (FIG.39I). [00892] Referring to FIG.24.59, the process 3900 may include deposition of a photoresist strip 384 followed by selective epitaxial growth, with lateral overgrowth, of P+ doped layers 400 (e.g., Si, and/or SiGeC alloy) in pixels 354.2 and 354.5, at 3968 (FIG.39I). [00893] Referring to FIG. 24.60, the process 3900 may include deposition of the first dielectric 306 (e.g., SiO
2) and planarization of the back side 302 of the wafer 300, at 3969 (FIG. 39I). [00894] Referring to FIG.24.61, the process 3900 may include patterned selective etch of holes 399 through the first dielectric 306 (e.g., SiO
2) in pixel 354.2 and pixel 354.5, stopping on the N+ epitaxial films 393, at 3970 (FIG.39I). [00895] Referring to FIG.24.62, the process 3900 may include deposition of a photoresist strip 384 followed by selective epitaxial growth, with lateral overgrowth, of N+ doped layers 401 (e.g., Si, and/or SiGeC alloy) in pixels 354.2 and 354.5, at 3971 (FIG.39I). [00896] Referring to FIG. 24.63, the process 3900 may include deposition of the first dielectric 306 (e.g., SiO
2) and planarization of the back side 302 of the wafer 300, at 3972 (FIG. 39I). [00897] Referring to FIG.24.64, the process 3900 may include patterned selective etch of a hole 402 through the film of the first dielectric 306 (e.g., SiO
2) on the right-hand side of the
P A T E N T Docket No. QS2090 central nano-pillar in pixel 354.5, at 3973 (FIG.39I). This etch may expose the lateral surface of the EOM layers 386, stopping when a portion of the lateral surface of the middle DBR layers 387 are exposed. [00898] Referring to FIG.24.65, the process 3900 may include deposition of a photoresist strip 384 followed by deposition of metal 403 to fill hole 402, and chemical mechanical polishing (CMP), at 3974 (FIG.39J). [00899] Referring to FIG.24.66, the process 3900 may include patterned selective etch of a hole 404 through the film of the first dielectric 306 (e.g., SiO
2) on the left-hand side of the central nano-pillar in pixel 354.5, at 3975 (FIG.39J). This etch may expose the lateral surface of the EOM layers 386, stopping when a portion of the lateral surface of the middle DBR layers 387 are exposed. [00900] Referring to FIG.24.67, the process 3900 may include deposition of a photoresist strip 384 followed by deposition of metal 405 to fill the hole 404, and CMP, at 3976 (FIG.39J). [00901] Referring to FIG.24.68, the process 3900 may include patterned selective etch of contact holes 406 through the film of the first dielectric 306 (e.g., SiO
2) in both pixels 354.1 and 354.5, stopping on the P+ and N+ epitaxial films 392 and 393, at 3977 (FIG.39J). [00902] Referring to FIG.24.69, the process 3900 may include deposition of a photoresist strip 384 followed by formation of silicide and filling of the contact holes 406 with metal 407, at 3978 (FIG.39J). [00903] Referring to FIG.24.70, the process 3900 may include deposition of a thin film of the second dielectric 307 (e.g., Si
3N
4), at 3979 (FIG.39J). [00904] Referring to FIG.24.71, the process 3900 may include patterned selective etch of two trenches 408 in pixel 354.3 through the film of the first dielectric 306 (e.g., SiO
2) and most of the epitaxial film 310, to form contact trenches at opposite sides of the epitaxial film 310, at 3980 (FIG.39J). [00905] Referring to FIG.24.72, the process 3900 may include deposition and etchback, which may be selective against Si, of the thin film of the second dielectric 307 (e.g., Si
3N
4), to form spacers covering the side walls of the first dielectric 306 (e.g., SiO
2), at 3981 (FIG.39J). [00906] Referring to FIG.24.73, the process 3900 may include low-temperature oxidation of the epitaxial films at the bottom of the trenches 408, to form oxidized epitaxial layers 409, at 3982 (FIG.39K).
P A T E N T Docket No. QS2090 [00907] Referring to FIG. 24.74, the process 3900 may include selective etch of the spacers inside the trenches 408, at 3983 (FIG.39K). [00908] Referring to FIG. 24.75, the process 3900 may include formation of silicide and filling of contact holes 408 with metal 410, at 3984 (FIG.39K). [00909] Referring to FIG.24.76, the process 3900 may include patterned etch of a contact hole 411 through the first dielectric 306 (e.g., SiO
2) and epitaxial films 376 and 378 in pixel 354.4, stopping on the epitaxial N+ layer 377, at 3985 (FIG. 39K). Epitaxial films 376 and 377 may be highly conductive layers, for example highly n-type doped, or highly p-type doped, or highly codoped, n-type and p-type, Si, and/or SiGeC alloy. [00910] Referring to FIG.24.77, the process 3900 may include deposition and etchback, which may be selective against Si, of the thin film of the second dielectric 307 (e.g., Si
3N
4), to form spacers covering the side walls of contact hole 411, at 3986 (FIG.39K). [00911] Referring to FIG.24.78, the process 3900 may include formation of silicide and filling of contact hole 411 with metal 412, and CMP, at 3987 (FIG.39K). [00912] Referring to FIG.24.79, the process 3900 may include patterned selective etch of the film of the first dielectric 306 (e.g., SiO
2), stopping on the epitaxial P+ layer 378, to form a contact hole 413, at 3988 (FIG.39K). [00913] Referring to FIG. 24.80, the process 3900 may include formation of silicide and filling of the contact hole 413 with metal 414, and CMP, at 3989 (FIG.39K). [00914] Referring to FIG. 24.81, the process 3900 may include patterned selective etch through the film of the first dielectric 306 (e.g., SiO
2) in pixel 354.1, stopping on the P+ and N+ epitaxial films 381 and 374, to form contact holes 415 for hole and electron injection, at 3990 (FIG.39L). [00915] Referring to FIG.24.82, the process 3900 may include formation of silicide and filling of the contact holes 415 with metal 416, and CMP, at 3991 (FIG.39L). [00916] Referring to FIG.24.83, the process 3900 may include patterned selective etch of holes 417 through the wafer 300, stopping on silicide made on the front side 301 of the wafer 300, at 3992 (FIG.39L). [00917] Referring to FIG.24.84, the process 3900 may include filling the contact holes 417 with metal 418, and CMP, at 3993 (FIG.39L).
P A T E N T Docket No. QS2090 [00918] Referring to FIG.24.85, the process 3900 may include deposition of a film of the first dielectric 306 (e.g., SiO
2), at 3994 (FIG.39L). [00919] Referring to FIG.24.86, the process 3900 may include patterned selective etch of holes 419 through the film of the first dielectric 306 (e.g., SiO
2) film, stopping on the previously made metal contacts within each pixel, at 3995 (FIG.39L). [00920] Referring to FIG. 24.87, the process 3900 may include deposition of metal 420, and CMP, thereby making electrical contacts from the front side 301 of the wafer 300 to devices made on the back side 302 of the wafer 300, at 3996 (FIG.39L). [00921] Referring to FIG.24.88, the process 3900 may include deposition of a film of the first dielectric 306 (e.g., SiO
2), at 3997 (FIG.39L). [00922] The process 3900 may include fabrication of optical/photonic devices, such as GRIN lens, color and/or polarization routers, system flat lens, etc., as described and shown for the third process integration architecture. [00923] FIG.44 depicts a block diagram of an example computer system 4400 in which embodiments described herein may be implemented. The computer system 4400 includes a bus 4402 or other communication mechanism for communicating information, one or more hardware processors 4404 coupled with bus 4402 for processing information. Hardware processor(s) 4404 may be, for example, one or more general purpose microprocessors. [00924] The computer system 4400 also includes a main memory 4406, such as a random access memory (RAM), cache and/or other dynamic storage devices, coupled to bus 4402 for storing information and instructions to be executed by processor 4404. Main memory 4406 also may be used for storing temporary variables or other intermediate information during execution of instructions to be executed by processor 4404. Such instructions, when stored in storage media accessible to processor 4404, render computer system 4400 into a special-purpose machine that is customized to perform the operations specified in the instructions. [00925] The computer system 4400 further includes a read only memory (ROM) 4408 or other static storage device coupled to bus 4402 for storing static information and instructions for processor 4404. A storage device 4410, such as a magnetic disk, optical disk, or USB thumb drive (Flash drive), etc., is provided and coupled to bus 4402 for storing information and instructions. [00926] The computer system 4400 may be coupled via bus 4402 to a display 4412, such as a liquid crystal display (LCD) (or touch screen), for displaying information to a computer user. An input device 4414, including alphanumeric and other keys, is coupled to bus 4402 for
P A T E N T Docket No. QS2090 communicating information and command selections to processor 4404. Another type of user input device is cursor control 4416, such as a mouse, a trackball, or cursor direction keys for communicating direction information and command selections to processor 4404 and for controlling cursor movement on display 4412. In some embodiments, the same direction information and command selections as cursor control may be implemented via receiving touches on a touch screen without a cursor. [00927] The computing system 4400 may include a user interface module to implement a GUI that may be stored in a mass storage device as executable software codes that are executed by the computing device(s). This and other modules may include, by way of example, components, such as software components, object-oriented software components, class components and task components, processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuitry, data, databases, data structures, tables, arrays, and variables. [00928] In general, the word “component,” “engine,” “system,” “database,” data store,” and the like, as used herein, can refer to logic embodied in hardware or firmware, or to a collection of software instructions, possibly having entry and exit points, written in a programming language, such as, for example, Java, C or C++. A software component may be compiled and linked into an executable program, installed in a dynamic link library, or may be written in an interpreted programming language such as, for example, BASIC, Perl, or Python. It will be appreciated that software components may be callable from other components or from themselves, and/or may be invoked in response to detected events or interrupts. Software components configured for execution on computing devices may be provided or encoded on a computer readable or machine readable medium, such as a compact disc, digital video disc, flash drive, magnetic disc, or any other tangible medium, or as a digital download (and may be originally stored in a compressed or installable format that requires installation, decompression or decryption prior to execution). Such software code may be stored, partially or fully, on a memory device of the executing computing device, for execution by the computing device. Software instructions may be embedded in firmware, such as an EPROM. It will be further appreciated that hardware components may be comprised of connected logic units, such as gates and flip-flops, and/or may be comprised of programmable units, such as programmable gate arrays or processors. [00929] The computer system 4400 may implement the techniques described herein using customized hard-wired logic, one or more ASICs or FPGAs, firmware and/or program logic
P A T E N T Docket No. QS2090 which in combination with the computer system causes or programs computer system 4400 to be a special-purpose machine. According to one embodiment, the techniques herein are performed by computer system 4400 in response to processor(s) 4404 executing one or more sequences of one or more instructions contained in main memory 4406. Such instructions may be read into main memory 4406 from another storage medium, such as storage device 4410. Execution of the sequences of instructions contained in main memory 4406 causes processor(s) 4404 to perform the process steps described herein. In alternative embodiments, hard-wired circuitry may be used in place of or in combination with software instructions. [00930] The term “non-transitory media,” and similar terms, as used herein refers to any non-transitory media that store data and/or instructions that cause a machine to operate in a specific fashion. Such non-transitory media may comprise non-volatile media and/or volatile media. Non-volatile media includes, for example, optical or magnetic disks, such as storage device 4410. Volatile media includes dynamic memory, such as main memory 4406. Common forms of non-transitory media include, for example, a floppy disk, a flexible disk, hard disk, solid state drive, magnetic tape, or any other magnetic data storage medium, a CD-ROM, any other optical data storage medium, any physical medium with patterns of holes, a RAM, a PROM, and EPROM, a FLASH-EPROM, NVRAM, any other memory chip or cartridge, and networked versions of the same. [00931] Non-transitory media is distinct from but may be used in conjunction with transmission media. Transmission media participates in transferring information between non- transitory media. For example, transmission media includes coaxial cables, copper wire and fiber optics, including the wires that comprise bus 4402. Transmission media can also take the form of acoustic or light waves, such as those generated during radio-wave and infra-red data communications. [00932] The computer system 4400 also includes a communication interface 4418 coupled to bus 4402. Network interface 4418 provides a two-way data communication coupling to one or more network links that are connected to one or more local networks. For example, communication interface 4418 may be an integrated services digital network (ISDN) card, cable modem, satellite modem, or a modem to provide a data communication connection to a corresponding type of telephone line. As another example, network interface 4418 may be a local area network (LAN) card to provide a data communication connection to a compatible LAN (or a WAN component to communicate with a WAN). Wireless links may also be implemented. In any
P A T E N T Docket No. QS2090 such implementation, network interface 4418 sends and receives electrical, electromagnetic or optical signals that carry digital data streams representing various types of information. [00933] A network link typically provides data communication through one or more networks to other data devices. For example, a network link may provide a connection through local network to a host computer or to data equipment operated by an Internet Service Provider (ISP). The ISP in turn provides data communication services through the worldwide packet data communication network now commonly referred to as the “Internet.” Local network and Internet both use electrical, electromagnetic or optical signals that carry digital data streams. The signals through the various networks and the signals on network link and through communication interface 4418, which carry the digital data to and from computer system 4400, are example forms of transmission media. [00934] The computer system 4400 can send messages and receive data, including program code, through the network(s), network link and communication interface 4418. In the Internet example, a server might transmit a requested code for an application program through the Internet, the ISP, the local network and the communication interface 4418. [00935] The received code may be executed by processor 4404 as it is received, and/or stored in storage device 4410, or other non-volatile storage for later execution. [00936] Each of the processes, methods, and algorithms described in the preceding sections may be embodied in, and fully or partially automated by, code components executed by one or more computer systems or computer processors comprising computer hardware. For example, a method bay be referred to as a "computer-implemented" method. The one or more computer systems or computer processors may also operate to support performance of the relevant operations in a “cloud computing” environment or as a “software as a service” (SaaS). The processes and algorithms may be implemented partially or wholly in application-specific circuitry. The various features and processes described above may be used independently of one another, or may be combined in various ways. Different combinations and sub-combinations are intended to fall within the scope of this disclosure, and certain method or process blocks may be omitted in some implementations. The methods and processes described herein are also not limited to any particular sequence, and the blocks or states relating thereto can be performed in other sequences that are appropriate, or may be performed in parallel, or in some other manner. Blocks or states may be added to or removed from the disclosed example embodiments. The performance of certain of the operations or processes may be distributed among computer
P A T E N T Docket No. QS2090 systems or computers processors, not only residing within a single machine, but deployed across a number of machines. [00937] As used herein, a circuit might be implemented utilizing any form of hardware, or a combination of hardware and software. For example, one or more processors, controllers, ASICs, PLAs, PALs, CPLDs, FPGAs, logical components, software routines or other mechanisms might be implemented to make up a circuit. In implementation, the various circuits described herein might be implemented as discrete circuits or the functions and features described can be shared in part or in total among one or more circuits. Even though various features or elements of functionality may be individually described or claimed as separate circuits, these features and functionality can be shared among one or more common circuits, and such description shall not require or imply that separate circuits are required to implement such features or functionality. Where a circuit is implemented in whole or in part using software, such software can be implemented to operate with a computing or processing system capable of carrying out the functionality described with respect thereto, such as computer system 4400. [00938] As used herein, the term “or” may be construed in either an inclusive or exclusive sense. Moreover, the description of resources, operations, or structures in the singular shall not be read to exclude the plural. Conditional language, such as, among others, “can,” “could,” “might,” or “may,” unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and/or steps. [00939] Terms and phrases used in this document, and variations thereof, unless otherwise expressly stated, should be construed as open ended as opposed to limiting. Adjectives such as “conventional,” “traditional,” “normal,” “standard,” “known,” and terms of similar meaning should not be construed as limiting the item described to a given time period or to an item available as of a given time, but instead should be read to encompass conventional, traditional, normal, or standard technologies that may be available or known now or at any time in the future. The presence of broadening words and phrases such as “one or more,” “at least,” “but not limited to” or other like phrases in some instances shall not be read to mean that the narrower case is intended or required in instances where such broadening phrases may be absent. [00940] The foregoing description of the present disclosure has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. The breadth and scope of the present disclosure
P A T E N T Docket No. QS2090 should not be limited by any of the above-described exemplary embodiments. Many modifications and variations will be apparent to the practitioner skilled in the art. The modifications and variations include any relevant combination of the disclosed features. The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure for various embodiments and with various modifications that are suited to the particular use contemplated. It is intended that the scope of the disclosure be defined by the following claims and their equivalents.