[go: up one dir, main page]

WO2024239909A1 - 驱动电路、驱动方法和显示装置 - Google Patents

驱动电路、驱动方法和显示装置 Download PDF

Info

Publication number
WO2024239909A1
WO2024239909A1 PCT/CN2024/089966 CN2024089966W WO2024239909A1 WO 2024239909 A1 WO2024239909 A1 WO 2024239909A1 CN 2024089966 W CN2024089966 W CN 2024089966W WO 2024239909 A1 WO2024239909 A1 WO 2024239909A1
Authority
WO
WIPO (PCT)
Prior art keywords
node
electrically connected
transistor
control
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2024/089966
Other languages
English (en)
French (fr)
Inventor
汪锐
张润鑫
胡明
张手强
邱海军
翁鸿韬
黄耀
唐国强
黄智�
赵永亮
郝学光
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chongqing BOE Display Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chongqing BOE Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chongqing BOE Display Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to EP24810156.0A priority Critical patent/EP4657417A1/en
Publication of WO2024239909A1 publication Critical patent/WO2024239909A1/zh
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a driving circuit, a driving method and a display device.
  • the relevant driving circuit uses a capacitor for controlling the potential of the second node.
  • the first end of the capacitor is electrically connected to the second node, and the second end of the capacitor is electrically connected to the clock signal line through a transistor, so that the waveform of the potential of the second node can have steps caused by coupled fluctuations, resulting in high power consumption and low stability of the driving signal output.
  • the present embodiment provides a driving circuit, including a first node control circuit, a first control circuit, a second control circuit, an output node control circuit, a first energy storage circuit, and an output circuit;
  • the first node control circuit is electrically connected to the first node and is used to control the potential of the first node
  • the first control circuit is electrically connected to the set control terminal, the first voltage line and the second node respectively, and is used to control the connection or disconnection between the second node and the first voltage line under the control of the set control signal provided by the set control terminal;
  • the second control circuit is electrically connected to the first clock signal line, the second node and the second voltage line respectively, and is used to control the connection or disconnection between the second node and the second voltage line under the control of the first clock signal provided by the first clock signal line and the potential of the second node;
  • the output node control circuit is electrically connected to the first clock signal line, the second node and the first output node respectively, and is used to control the connection or disconnection between the second node and the first output node under the control of the first clock signal;
  • the first energy storage circuit is electrically connected to the second output node and is used to store electrical energy
  • the output circuit is electrically connected to the first output node, the second output node and the driving output end respectively, and is used to control the driving output end to output a driving signal under the control of the potential of the first output node and the potential of the second output node.
  • the first end of the first energy storage circuit is electrically connected to the second output node, and the second end of the first energy storage circuit is electrically connected to the driving output end.
  • the first node and the second output node are the same node; or,
  • the driving circuit also includes an on-off control circuit; the first node is connected to the second node through the on-off control circuit The output node is electrically connected; the control end of the on-off control circuit is electrically connected to the third voltage line, and the on-off control circuit is used to control the connection or disconnection between the first node and the second output node under the control of a third voltage signal provided by the third voltage line.
  • the driving circuit described in at least one embodiment of the present invention further includes an energy storage control circuit
  • the energy storage control circuit is electrically connected to the second output node, the first clock signal line and the energy storage node respectively, and is used to control the connection or disconnection between the first clock signal line and the energy storage node under the control of the potential of the second output node;
  • the first end of the first energy storage circuit is electrically connected to the second output node, and the second end of the first energy storage circuit is electrically connected to the energy storage node.
  • the first end of the first energy storage circuit is electrically connected to the second output node, and the second end of the first energy storage circuit is electrically connected to the first clock signal line.
  • the driving circuit described in at least one embodiment of the present invention further includes a third control circuit
  • the third control circuit is electrically connected to the second output node, the first output node and the fourth voltage line respectively, and is used to control the connection or disconnection between the first output node and the fourth voltage line under the control of the potential of the second output node;
  • the third control circuit is electrically connected to the first node, the first output node and the fourth voltage line respectively, and is used to control the connection or disconnection between the first output node and the fourth voltage line under the control of the potential of the first node.
  • the driving circuit described in at least one embodiment of the present invention further includes a fourth control circuit
  • the fourth control circuit is electrically connected to the first node, the fourth voltage line and the second node respectively, and is used to control the connection or disconnection between the second node and the fourth voltage line under the control of the potential of the first node.
  • the driving circuit described in at least one embodiment of the present invention further includes a second energy storage circuit; the second energy storage circuit is electrically connected to the first output node and is used to store electrical energy.
  • the second control circuit includes a first transistor and a second transistor
  • the gate of the first transistor is electrically connected to the second node, the first electrode of the first transistor is electrically connected to the second voltage line, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor;
  • a gate of the second transistor is electrically connected to the first clock signal line, and a second electrode of the second transistor is electrically connected to the second node.
  • the first control circuit includes a third transistor; the set control terminal is an input terminal;
  • the gate of the third transistor is electrically connected to the input terminal, the first electrode of the third transistor is electrically connected to the first voltage line, and the second electrode of the third transistor is electrically connected to the second node;
  • the third transistor is an oxide transistor.
  • the set control terminal is an inverting input terminal;
  • the first control circuit includes a third transistor;
  • the gate of the third transistor is electrically connected to the inverting input terminal, the first electrode of the third transistor is electrically connected to the first voltage line, and the second electrode of the third transistor is electrically connected to the second node;
  • the third transistor is a p-type transistor
  • the inverting input terminal is used to provide an inverting input signal, and the inverting input signal is inverted with the input signal provided by the input terminal.
  • the first output node is electrically connected to an inverting input terminal of an adjacent next stage, and the driving output terminal is electrically connected to an input terminal of an adjacent next stage.
  • the first energy storage circuit includes a first capacitor
  • a first end of the first capacitor is electrically connected to the second output node, and a second end of the first capacitor is electrically connected to the driving output end.
  • the first energy storage circuit includes a first capacitor
  • a first end of the first capacitor is electrically connected to the second output node, and a second end of the first capacitor is electrically connected to the first clock signal line.
  • the first energy storage circuit includes a first capacitor, and the energy storage control circuit includes a fourth transistor;
  • the first end of the first capacitor is electrically connected to the second output node; the second end of the first capacitor is electrically connected to the energy storage node;
  • a gate of the fourth transistor is electrically connected to the second output node, a first electrode of the fourth transistor is electrically connected to the energy storage node, and a second electrode of the fourth transistor is electrically connected to the first clock signal line.
  • the fourth control circuit includes a fifth transistor
  • a gate of the fifth transistor is electrically connected to the first node, a first electrode of the fifth transistor is electrically connected to the fourth voltage line, and a second electrode of the fifth transistor is electrically connected to the second node.
  • the first node control circuit is also electrically connected to the input terminal, the second node, the second clock signal line, the first clock signal line and the fourth voltage line, respectively, and is used to control the connection or disconnection between the first node and the input terminal under the control of the second clock signal provided by the second clock signal line, and to control the connection or disconnection between the first node and the fourth voltage line under the control of the first clock signal and the potential of the second node.
  • the first node control circuit includes a sixth transistor, a seventh transistor and an eighth transistor;
  • the gate of the sixth transistor is electrically connected to the second clock signal line, the first electrode of the sixth transistor is electrically connected to the input terminal, and the second electrode of the sixth transistor is electrically connected to the first node;
  • the gate of the seventh transistor is electrically connected to the first clock signal line, the first electrode of the seventh transistor is electrically connected to the fourth voltage line, and the second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor;
  • a gate of the eighth transistor is electrically connected to the second node, and a second electrode of the eighth transistor is electrically connected to the first node.
  • the third control circuit includes a ninth transistor
  • a gate of the ninth transistor is electrically connected to the second output node, a first electrode of the ninth transistor is electrically connected to the fourth voltage line, and a second electrode of the ninth transistor is electrically connected to the first output node.
  • the output node control circuit includes a tenth transistor
  • the gate of the tenth transistor is electrically connected to the first clock signal line, and the first electrode of the tenth transistor is electrically connected to the
  • the second node is electrically connected to the first output node, and the second electrode of the tenth transistor is electrically connected to the first output node.
  • the driving circuit further includes an on-off control circuit
  • the on-off control circuit includes an eleventh transistor
  • a gate of the eleventh transistor is electrically connected to the third voltage line, a first electrode of the eleventh transistor is electrically connected to the first node, and a first electrode of the twelfth transistor is electrically connected to the second output node.
  • the output circuit includes a twelfth transistor and a thirteenth transistor;
  • the gate of the twelfth transistor is electrically connected to the first output node, the first electrode of the twelfth transistor is electrically connected to the fifth voltage line, and the second electrode of the twelfth transistor is electrically connected to the driving output terminal;
  • a gate of the thirteenth transistor is electrically connected to the second output node, a first electrode of the thirteenth transistor is electrically connected to the driving output terminal, and a second electrode of the thirteenth transistor is electrically connected to a sixth voltage line.
  • an embodiment of the present invention provides a driving method, which is applied to the above-mentioned driving circuit, and the driving method includes:
  • the first node control circuit controls the potential of the first node
  • the first control circuit controls the connection or disconnection between the second node and the first voltage line under the control of the set control signal
  • the second control circuit controls the connection or disconnection between the second node and the second voltage line under the control of the first clock signal and the potential of the second node;
  • the output node control circuit controls the connection or disconnection between the second node and the first output node under the control of the first clock signal
  • the output circuit controls the driving output terminal to output a driving signal under the control of the potential of the first output node and the potential of the second output node.
  • an embodiment of the present invention provides a display device, comprising the above-mentioned driving circuit.
  • FIG1 is a structural diagram of a driving circuit according to at least one embodiment of the present invention.
  • FIG2 is a structural diagram of a driving circuit according to at least one embodiment of the present invention.
  • FIG. 3 is a structural diagram of a driving circuit according to at least one embodiment of the present invention.
  • FIG4 is a structural diagram of a driving circuit according to at least one embodiment of the present invention.
  • FIG. 5 is a structural diagram of a driving circuit according to at least one embodiment of the present invention.
  • FIG. 6 is a structural diagram of a driving circuit according to at least one embodiment of the present invention.
  • FIG. 7 is a structural diagram of a driving circuit according to at least one embodiment of the present invention.
  • FIG. 8 is a structural diagram of a driving circuit according to at least one embodiment of the present invention.
  • FIG. 9 is a structural diagram of a driving circuit according to at least one embodiment of the present invention.
  • FIG. 10 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention.
  • FIG11 is a timing diagram of operation of at least one embodiment of the driving circuit shown in FIG10 ;
  • FIG12 is a simulation operation timing diagram of at least one embodiment of the driving circuit shown in FIG10;
  • FIG. 13 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention.
  • FIG14 is a simulation operation timing diagram of at least one embodiment of the driving circuit shown in FIG13;
  • 15A is a waveform diagram of the potential of the first node N1 and the driving signal in at least one embodiment of the driving circuit shown in FIG. 10 ;
  • 15B is a waveform diagram of the potential of the first node N1, the potential of the second output node NO2, and the driving signal in at least one embodiment of the driving circuit shown in FIG. 13 ;
  • 16 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention.
  • FIG17 is a timing diagram of operation of at least one embodiment of the driving circuit shown in FIG16 ;
  • FIG. 18 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention.
  • FIG19 is a timing diagram of operation of at least one embodiment of the driving circuit shown in FIG18;
  • FIG20 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention.
  • FIG21 is a layout diagram of at least one embodiment of the driving circuit shown in FIG10;
  • FIG22 is a layout diagram of the first semiconductor layer in FIG21;
  • FIG23 is a layout diagram of the first gate metal layer in FIG21;
  • FIG24 is a layout diagram of the second gate metal layer in FIG21;
  • FIG25 is a layout diagram of the third gate metal layer in FIG21;
  • FIG26 is a layout diagram of the second semiconductor layer in FIG21;
  • FIG. 27 is a layout diagram of the source/drain metal layer in FIG. 21 .
  • the transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • one electrode is called the first electrode and the other electrode is called the second electrode.
  • the first electrode when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
  • the driving circuit described in the embodiment of the present invention includes a first node control circuit, a first control circuit, a second control circuit, an output node control circuit, a first energy storage circuit and an output circuit;
  • the first node control circuit is electrically connected to the first node and is used to control the potential of the first node
  • the first control circuit is electrically connected to the set control terminal, the first voltage line and the second node respectively, and is used to control the connection or disconnection between the second node and the first voltage line under the control of the set control signal provided by the set control terminal;
  • the second control circuit is electrically connected to the first clock signal line, the second node and the second voltage line respectively, and is used to control the connection or disconnection between the second node and the second voltage line under the control of the first clock signal provided by the first clock signal line and the potential of the second node;
  • the output node control circuit is electrically connected to the first clock signal line, the second node and the first output node respectively, and is used to control the connection or disconnection between the second node and the first output node under the control of the first clock signal;
  • the first energy storage circuit is electrically connected to the second output node and is used to store electrical energy
  • the output circuit is electrically connected to the first output node, the second output node and the driving output end respectively, and is used to control the driving output end to output a driving signal under the control of the potential of the first output node and the potential of the second output node.
  • the driving circuit described in the embodiment of the present invention controls the potential of the second node by adopting a first control circuit and a second control circuit.
  • the capacitor used to control the potential of the second node is reduced, which is conducive to achieving a narrow frame.
  • the second control circuit can control the potential of the second node to be stable.
  • the embodiment of the present invention does not use a capacitor electrically connected to the second node (the first end of the capacitor is electrically connected to the second node, and the second end of the capacitor is electrically connected to the clock signal line through a transistor), so that the waveform of the potential of the second node has no steps caused by coupling fluctuations.
  • the embodiment of the present invention can ensure the stability of the driving signal output while reducing power consumption.
  • the first node and the second output node are the same node; or,
  • the driving circuit also includes an on-off control circuit; the first node is electrically connected to the second output node through the on-off control circuit; the control end of the on-off control circuit is electrically connected to a third voltage line, and the on-off control circuit is used to control the connection or disconnection between the first node and the second output node under the control of a third voltage signal provided by the third voltage line.
  • first node and the second output node may be the same node, or the first node and the second output node may be electrically connected via an on-off control circuit.
  • the first voltage line may be a first low voltage line
  • the second voltage line may be a second low voltage line
  • the driving circuit includes a first node control circuit 11, a first control circuit 12, a second control circuit 13, an output node control circuit 14, a first energy storage circuit 15 and an output circuit 16;
  • the first node control circuit 11 is electrically connected to the first node N1 and is used to control the potential of the first node N1;
  • the first control circuit 12 is electrically connected to the set control terminal ZC, the first voltage line V1 and the second node N2 respectively, and is used to control the connection or disconnection between the second node N2 and the first voltage line V1 under the control of the set control signal provided by the set control terminal ZC;
  • the second control circuit 13 is electrically connected to the first clock signal line CKB, the second node N2 and the second voltage line V2 respectively, and is used to control the connection or disconnection between the second node N2 and the second voltage line V2 under the control of the first clock signal provided by the first clock signal line CKB and the potential of the second node N2;
  • the output node control circuit 14 is electrically connected to the first clock signal line CKB, the second node N2 and the first output node NO1 respectively, and is used to control the second node N2 to be connected to the first output node NO1 under the control of the first clock signal.
  • An output node NO1 is connected or disconnected;
  • the first energy storage circuit 15 is electrically connected to the first node N1 and is used to store electrical energy
  • the output circuit 16 is electrically connected to the first output node NO1, the node N1 and the driving output terminal O1 respectively, and is used to control the driving output terminal O1 to output a driving signal under the control of the potential of the first output node NO1 and the potential of the first node N1.
  • the second output node and the first node N1 are the same node.
  • the driving circuit includes a first node control circuit 11, a first control circuit 12, a second control circuit 13, an output node control circuit 14, a first energy storage circuit 15, an output circuit 16 and an on-off control circuit 21;
  • the first node N1 is electrically connected to the second output node NO2 through the on-off control circuit 21; the control end of the on-off control circuit 21 is electrically connected to the third voltage line V3, and the on-off control circuit 21 is used to control the connection or disconnection between the first node N1 and the second output node NO2 under the control of the third voltage signal provided by the third voltage line V3;
  • the first node control circuit 11 is electrically connected to the first node N1 and is used to control the potential of the first node N1;
  • the first control circuit 12 is electrically connected to the set control terminal ZC, the first voltage line V1 and the second node N2 respectively, and is used to control the connection or disconnection between the second node N2 and the first voltage line V1 under the control of the set control signal provided by the set control terminal ZC;
  • the second control circuit 13 is electrically connected to the first clock signal line CKB, the second node N2 and the second voltage line V2 respectively, and is used to control the connection or disconnection between the second node N2 and the second voltage line V2 under the control of the first clock signal provided by the first clock signal line CKB and the potential of the second node N2;
  • the output node control circuit 14 is electrically connected to the first clock signal line CKB, the second node N2 and the first output node NO1 respectively, and is used to control the connection or disconnection between the second node N2 and the first output node NO1 under the control of the first clock signal;
  • the output circuit 15 is electrically connected to the first output node NO1, the second output node NO2 and the driving output terminal O1 respectively, and is used to control the driving output terminal O1 to output a driving signal under the control of the potential of the first output node NO1 and the potential of the second output node NO2.
  • an on/off control circuit 21 controlled by a third voltage line V3 is disposed between the first node N1 and the second output node NO2 .
  • the third voltage line V3 may be a first low voltage line, but is not limited thereto.
  • the first end of the first energy storage circuit is electrically connected to the second output node, and the second end of the first energy storage circuit is electrically connected to the driving output end.
  • the second end of the first energy storage circuit can be electrically connected to the driving output end, but not to the clock signal line. Therefore, the potential of the second output node will not produce a step due to the coupling effect of the first energy storage circuit, and the potential of the second output node can be stabilized, thereby improving the stability of the driving signal output by the driving circuit.
  • the driving circuit described in at least one embodiment of the present invention may further include an energy storage control circuit
  • the energy storage control circuit is electrically connected to the second output node, the first clock signal line and the energy storage node respectively, and is used to control the connection or disconnection between the first clock signal line and the energy storage node under the control of the potential of the second output node;
  • the first end of the first energy storage circuit is electrically connected to the second output node, and the second end of the first energy storage circuit is electrically connected to the energy storage node.
  • the driving circuit according to at least one embodiment of the present invention further includes an energy storage control circuit 31;
  • the energy storage control circuit 31 is electrically connected to the second output node NO2, the first clock signal line CKB and the energy storage node NC respectively, and is used to control the connection or disconnection between the first clock signal line CKB and the energy storage node NC under the control of the potential of the second output node NO2;
  • a first end of the first energy storage circuit 15 is electrically connected to the second output node NO2 , and a second end of the first energy storage circuit 15 is electrically connected to the energy storage node NC.
  • the first end of the first energy storage circuit is electrically connected to the second output node, and the second end of the first energy storage circuit is electrically connected to the first clock signal line.
  • the driving circuit described in at least one embodiment of the present invention further includes a third control circuit
  • the third control circuit is electrically connected to the second output node, the first output node and the fourth voltage line respectively, and is used to control the connection or disconnection between the first output node and the fourth voltage line under the control of the potential of the second output node;
  • the fourth voltage line may be a high voltage line.
  • the third control circuit 41 is electrically connected to the first node N1, the first output node NO1 and the fourth voltage line V4 respectively, and is used to control the connection or disconnection between the first output node NO1 and the fourth voltage line V4 under the control of the potential of the first node N1.
  • the third control circuit 41 is electrically connected to the second output node NO2, the first output node NO1 and the fourth voltage line V4 respectively, and is used to control the connection or disconnection between the first output node NO1 and the fourth voltage line V4 under the control of the potential of the second output node NO2.
  • the driving circuit may further include a fourth control circuit
  • the fourth control circuit is electrically connected to the first node, the fourth voltage line and the second node respectively, and is used to control the connection or disconnection between the second node and the fourth voltage line under the control of the potential of the first node.
  • the driving circuit may further include a fourth control circuit, which controls the connection or disconnection between the second node and the fourth voltage line under the control of the potential of the first node, so as to control the potential of the second node to be a high voltage when the potential of the first node is a low voltage.
  • the driving circuit described in at least one embodiment of the present invention further includes a second energy storage circuit; the second energy storage circuit is electrically connected to the first output node and is used to store electrical energy.
  • the second control circuit includes a first transistor and a second transistor
  • the gate of the first transistor is electrically connected to the second node, the first electrode of the first transistor is electrically connected to the second voltage line, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor;
  • a gate of the second transistor is electrically connected to the first clock signal line, and a second electrode of the second transistor is electrically connected to the second node.
  • the first control circuit may include a third transistor; the set control terminal is an input terminal;
  • the gate of the third transistor is electrically connected to the input terminal, the first electrode of the third transistor is electrically connected to the first voltage line, and the second electrode of the third transistor is electrically connected to the second node;
  • the third transistor is an oxide transistor.
  • the set control terminal may be an inverting input terminal;
  • the first control circuit includes a third transistor;
  • the gate of the third transistor is electrically connected to the inverting input terminal, the first electrode of the third transistor is electrically connected to the first voltage line, and the second electrode of the third transistor is electrically connected to the second node;
  • the third transistor is a p-type transistor
  • the inverting input terminal is used to provide an inverting input signal, and the inverting input signal is inverted with the input signal provided by the input terminal.
  • the first output node is electrically connected to an inverting input terminal of an adjacent next stage, and the driving output terminal is electrically connected to an input terminal of an adjacent next stage.
  • the first energy storage circuit includes a first capacitor
  • a first end of the first capacitor is electrically connected to the second output node, and a second end of the first capacitor is electrically connected to the driving output end.
  • the first energy storage circuit includes a first capacitor
  • a first end of the first capacitor is electrically connected to the second output node, and a second end of the first capacitor is electrically connected to the first clock signal line.
  • the first energy storage circuit includes a first capacitor, and the energy storage control circuit includes a fourth transistor;
  • the first end of the first capacitor is electrically connected to the second output node; the second end of the first capacitor is electrically connected to the energy storage node;
  • the gate of the fourth transistor is electrically connected to the second output node, the first electrode of the fourth transistor is electrically connected to the energy storage node, and the second electrode of the fourth transistor is electrically connected to the first clock signal line.
  • the fourth control circuit includes a fifth transistor
  • a gate of the fifth transistor is electrically connected to the first node, a first electrode of the fifth transistor is electrically connected to the fourth voltage line, and a second electrode of the fifth transistor is electrically connected to the second node.
  • the first node control circuit is also electrically connected to the input terminal, the second node, the second clock signal line, the first clock signal line and the fourth voltage line, respectively, and is used to control the connection or disconnection between the first node and the input terminal under the control of the second clock signal provided by the second clock signal line, and to control the connection or disconnection between the first node and the fourth voltage line under the control of the first clock signal and the potential of the second node.
  • the first node control circuit can control the connection or disconnection between the first node and the input end under the control of the second clock signal, and control the connection or disconnection between the first node and the fourth voltage line under the control of the first clock signal and the potential of the second node, so as to control the potential of the first node.
  • the driving circuit may further include a fourth control circuit 71 and a second energy storage circuit 72 ;
  • the fourth control circuit 71 is electrically connected to the first node N1, the fourth voltage line V4 and the second node N2 respectively, and is used to control the connection or disconnection between the second node N2 and the fourth voltage line V4 under the control of the potential of the first node N1;
  • the second energy storage circuit 72 is electrically connected to the first output node NO1 and the fourth voltage line V4 respectively, and is used to store electrical energy;
  • the first node control circuit 11 is also electrically connected to the input terminal STV, the second node N2, the second clock signal line CK, the first clock signal line CKB and the fourth voltage line V4, respectively, and is used to control the connection or disconnection between the first node N1 and the input terminal STV under the control of the second clock signal provided by the second clock signal line CK, and to control the connection or disconnection between the first node N1 and the fourth voltage line V4 under the control of the first clock signal and the potential of the second node N2.
  • the fourth control circuit 70 can control the potential of N2 to be a high voltage when the potential of the first node N1 is a low voltage, and the second energy storage circuit 72 can maintain the potential of the first output node NO1; the first node control circuit 11 controls the potential of the first node N1 under the control of the second clock signal, the first clock signal and the potential of the second node N2.
  • the driving circuit may further include a fourth control circuit 71 and a second energy storage circuit 72 ;
  • the fourth control circuit 71 is electrically connected to the first node N1, the fourth voltage line V4 and the second node N2 respectively, and is used to control the connection or disconnection between the second node N2 and the fourth voltage line V4 under the control of the potential of the first node N1;
  • the second energy storage circuit 72 is electrically connected to the first output node NO1 and the fourth voltage line V4 respectively, and is used to store electrical energy;
  • the first node control circuit 11 is also electrically connected to the input terminal STV, the second node N2, the second clock signal line CK, the first clock signal line CKB and the fourth voltage line V4, respectively, and is used to control the connection or disconnection between the first node N1 and the input terminal STV under the control of the second clock signal provided by the second clock signal line CK, and to control the connection or disconnection between the first node N1 and the fourth voltage line V4 under the control of the first clock signal and the potential of the second node N2.
  • the driving circuit may further include a fourth control circuit 71 and a second energy storage circuit 72 ;
  • the fourth control circuit 71 is electrically connected to the first node N1, the fourth voltage line V4 and the second node N2 respectively, and is used to control the connection or disconnection between the second node N2 and the fourth voltage line V4 under the control of the potential of the first node N1;
  • the second energy storage circuit 72 is electrically connected to the first output node NO1 and the fourth voltage line V4 respectively, and is used to store electrical energy;
  • the first node control circuit 11 is also electrically connected to the input terminal STV, the second node N2, the second clock signal line CK, the first clock signal line CKB and the fourth voltage line V4, respectively, and is used to control the connection or disconnection between the first node N1 and the input terminal STV under the control of the second clock signal provided by the second clock signal line CK, and to control the connection or disconnection between the first node N1 and the fourth voltage line V4 under the control of the first clock signal and the potential of the second node N2.
  • the first node control circuit includes a sixth transistor, a seventh transistor and an eighth transistor;
  • the gate of the sixth transistor is electrically connected to the second clock signal line, and the first electrode of the sixth transistor is electrically connected to the The input terminal is electrically connected, and the second electrode of the sixth transistor is electrically connected to the first node;
  • the gate of the seventh transistor is electrically connected to the first clock signal line, the first electrode of the seventh transistor is electrically connected to the fourth voltage line, and the second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor;
  • a gate of the eighth transistor is electrically connected to the second node, and a second electrode of the eighth transistor is electrically connected to the first node.
  • the third control circuit includes a ninth transistor
  • a gate of the ninth transistor is electrically connected to the second output node, a first electrode of the ninth transistor is electrically connected to the fourth voltage line, and a second electrode of the ninth transistor is electrically connected to the first output node.
  • the output node control circuit includes a tenth transistor
  • a gate of the tenth transistor is electrically connected to the first clock signal line, a first electrode of the tenth transistor is electrically connected to the second node, and a second electrode of the tenth transistor is electrically connected to the first output node.
  • the driving circuit may further include an on-off control circuit
  • the on-off control circuit includes an eleventh transistor
  • a gate of the eleventh transistor is electrically connected to the third voltage line, a first electrode of the eleventh transistor is electrically connected to the first node, and a second electrode of the eleventh transistor is electrically connected to the second output node.
  • the output circuit includes a twelfth transistor and a thirteenth transistor;
  • the gate of the twelfth transistor is electrically connected to the first output node, the first electrode of the twelfth transistor is electrically connected to the fifth voltage line, and the second electrode of the twelfth transistor is electrically connected to the driving output terminal;
  • a gate of the thirteenth transistor is electrically connected to the second output node, a first electrode of the thirteenth transistor is electrically connected to the driving output terminal, and a second electrode of the thirteenth transistor is electrically connected to a sixth voltage line.
  • the fifth voltage line may be a high voltage line
  • the sixth voltage line may be a first low voltage line, but the present invention is not limited thereto.
  • the first node control circuit includes a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8;
  • the gate of the sixth transistor T6 is electrically connected to the second clock signal line CK, the source of the sixth transistor T6 is electrically connected to the input terminal STV, and the drain of the sixth transistor T6 is electrically connected to the first node N1;
  • the gate of the seventh transistor T7 is electrically connected to the first clock signal line CKB, the source of the seventh transistor T7 is electrically connected to the high voltage line VGH, and the drain of the seventh transistor T7 is electrically connected to the source of the eighth transistor T8;
  • the gate of the eighth transistor T8 is electrically connected to the second node N2, and the drain of the eighth transistor T8 is electrically connected to the first node N1;
  • the third control circuit includes a ninth transistor T9;
  • the gate of the ninth transistor T9 is electrically connected to the first node N1, the source of the ninth transistor T9 is electrically connected to the high voltage line VGH, and the drain of the ninth transistor T9 is electrically connected to the first output node NO1;
  • the output node control circuit includes a tenth transistor T10;
  • the gate of the tenth transistor T10 is electrically connected to the first clock signal line CKB, the source of the tenth transistor T10 is electrically connected to the second node N2, and the drain of the tenth transistor T10 is electrically connected to the first output node NO1;
  • the second control circuit includes a first transistor T1 and a second transistor T2;
  • the gate of the first transistor T1 is electrically connected to the second node N2, the source of the first transistor T1 is electrically connected to the second low voltage line VGL2, and the drain of the first transistor T1 is electrically connected to the source of the second transistor T2;
  • a gate of the second transistor T2 is electrically connected to the first clock signal line CKB, and a drain of the second transistor T2 is electrically connected to the second node N2;
  • the first control circuit includes a third transistor T3; the set control terminal is an input terminal STV;
  • the gate of the third transistor T3 is electrically connected to the input terminal STV, the source of the third transistor T3 is electrically connected to the low voltage line VGL, and the drain of the third transistor T3 is electrically connected to the second node N2;
  • the third transistor T3 is an oxide transistor
  • the first energy storage circuit includes a first capacitor C1;
  • the first end of C1 is electrically connected to the first node N1, and the second end of C1 is electrically connected to the driving output end O1;
  • the fourth control circuit includes a fifth transistor T5;
  • the gate of the fifth transistor T5 is electrically connected to the first node N1, the source of the fifth transistor T5 is electrically connected to the high voltage line VGH, and the drain of the fifth transistor T5 is electrically connected to the second node N2;
  • the second energy storage circuit includes a second capacitor C2;
  • a first end of the second capacitor C2 is electrically connected to the first output node NO1, and a second end of the second capacitor C2 is electrically connected to the high voltage line VGH;
  • the output circuit includes a twelfth transistor T12 and a thirteenth transistor T13;
  • the gate of the twelfth transistor T12 is electrically connected to the first output node NO1, the source of the twelfth transistor T12 is electrically connected to the high voltage line VGH, and the drain of the twelfth transistor T12 is electrically connected to the driving output terminal O1;
  • a gate of the thirteenth transistor T13 is electrically connected to the first node N1 , a source of the thirteenth transistor T13 is electrically connected to the driving output terminal O1 , and a drain of the thirteenth transistor T13 is electrically connected to the first low voltage line VGL.
  • T3 is an n-type transistor and T6 may be a dual-gate transistor to prevent leakage;
  • the transistors except T3 in FIG. 10 may all be p-type transistors.
  • N3 is a third node and N4 is a fourth node; the third node N3 is a connection node between T7 and T8 and the fourth node N4 is a connection node between T1 and T2 .
  • the voltage value of the first low voltage signal provided by VGL may be greater than or equal to -10V and less than or equal to -7V
  • the voltage value of the second low voltage signal provided by VGL2 may be greater than or equal to -10V and less than or equal to -7V. Equal to -7V, the voltage value of the first low voltage signal and the voltage value of the second low voltage signal may be equal or unequal.
  • a display cycle may include a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, a fifth stage t5, a sixth stage t6, a seventh stage t7 and an eighth stage t8 which are arranged in sequence;
  • STV provides a high voltage signal
  • CKB provides a high voltage signal
  • CK provides a low voltage signal
  • T6 and T3 are turned on, the potential of N2 is low voltage
  • T8 is turned on
  • T1 is turned on, the potential of N1 is high voltage
  • the potential of NO1 is high voltage
  • the potential of the driving signal output by O1 remains low voltage
  • STV provides a high voltage signal
  • CK provides a high voltage signal
  • CKB provides a low voltage signal
  • T3 is turned on, the potential of N2 is low voltage
  • T2 is turned on
  • T10 is turned on
  • the potential of NO1 is low voltage
  • T12 is turned on
  • O1 outputs a high voltage signal
  • T7 and T8 are turned on, the potential of N1 is high voltage
  • T13 is turned off;
  • STV provides a high voltage signal
  • CK provides a low voltage signal
  • CKB provides a high voltage signal
  • T6 and T3 are turned on
  • the potential of N2 is a low voltage
  • the potential of N1 is a high voltage
  • T1 is turned on
  • T2 is turned off
  • T8 is turned on
  • T7 is turned off
  • T10 is turned off
  • the potential of NO1 is maintained at a low voltage
  • T12 is turned on
  • T13 is turned off
  • O1 outputs a high voltage signal
  • STV provides a high voltage signal
  • CK provides a high voltage signal
  • CKB provides a low voltage signal
  • T3 is turned on, the potential of N2 is low voltage
  • T2 is turned on
  • T10 is turned on
  • the potential of NO1 is low voltage
  • T12 is turned on
  • O1 outputs a high voltage signal
  • T7 and T8 are turned on, the potential of N1 is high voltage
  • T13 is turned off;
  • STV provides a high voltage signal
  • CK provides a low voltage signal
  • CKB provides a high voltage signal
  • T6 and T3 are turned on
  • the potential of N2 is a low voltage
  • the potential of N1 is a high voltage
  • T1 is turned on
  • T2 is turned off
  • T8 is turned on
  • T7 is turned off
  • T10 is turned off
  • the potential of NO1 is maintained at a low voltage
  • T12 is turned on
  • T13 is turned off
  • O1 outputs a high voltage signal
  • STV provides a low voltage signal
  • CK provides a high voltage signal
  • CKB provides a low voltage signal
  • T7 is turned on
  • the potential of N2 is maintained at a low voltage
  • T8 is turned on
  • the potential of N1 is a high voltage
  • T13 is turned off
  • T10 is turned on
  • the potential of NO1 is a low voltage
  • T12 is turned on
  • O1 outputs a high voltage signal
  • STV provides a low voltage signal
  • CK provides a low voltage signal
  • CKB provides a high voltage signal
  • T6 is turned on
  • the potential of N1 is a low voltage
  • T13 is turned on
  • O1 outputs a low voltage signal
  • T9 is turned on
  • the potential of NO1 is a high voltage
  • T5 is turned on
  • the potential of N2 is a high voltage
  • STV provides a low voltage signal
  • CK provides a high voltage signal
  • CKB provides a low voltage signal
  • T6 and T3 are both turned off
  • the potential of N2 is maintained at a high voltage
  • the potential of N1 is maintained at a low voltage
  • T9 is turned on
  • the potential of NO1 is a high voltage
  • T12 is turned off
  • T13 is turned on
  • O1 outputs a low voltage signal.
  • At least one embodiment of the driving circuit shown in FIG. 10 is in operation.
  • T6 can be designed as a dual-gate transistor to prevent leakage.
  • T1 and T2 can stabilize the voltage of N2.
  • the voltage of N2 is always written by T3, and the potential of N2 is maintained at a low voltage.
  • the potential of the input signal provided by STV is set to Low, T3 is closed, but O1 needs to continuously output a high voltage signal, and T12 needs to be turned on.
  • N2 is written with a low voltage signal by T1 and T2, and T10 is turned on.
  • the potential of NO1 is a low voltage
  • T12 is turned on, and O1 outputs a high voltage signal.
  • the second end of C1 is electrically connected to the driving output end O1, and the second end of C1 is not electrically connected to the clock signal line. Therefore, the potential of N1 will not have a step due to the coupling effect of C1, and N2 is not electrically connected to the capacitor, and the potential of N2 will not have a step due to the coupling effect of the capacitor. This makes the potential of N1 and the potential of N2 more stable than that of the related driving circuit, without coupling fluctuations, and can reduce the power consumption of the driving circuit.
  • the potential waveform of N1 and the potential waveform of N2 have no steps, and the waveform of the driving signal output by the driving circuit also has no steps, which is more conducive to data writing.
  • FIG. 12 is a simulation operation timing diagram of at least one embodiment of the driving circuit shown in FIG. 10 .
  • the on-off control circuit comprises an eleventh transistor T11;
  • the gate of the eleventh transistor T11 is electrically connected to the first voltage line VGL, the source of the eleventh transistor T11 is electrically connected to the first node N1, and the drain of the eleventh transistor T11 is electrically connected to the second output node NO2;
  • T11 is a p-type transistor.
  • At least one embodiment of the driving circuit shown in FIG10 When at least one embodiment of the driving circuit shown in FIG10 is working, the charge held by C1 will leak through T6 within one frame time.
  • At least one embodiment of the driving circuit shown in FIG13 adds a voltage-stabilizing transistor (the voltage-stabilizing transistor is the eleventh transistor T11), which can stabilize the charge held by C2 and effectively improve the leakage of N1.
  • FIG. 14 is a simulation operation timing diagram of at least one embodiment of the driving circuit shown in FIG. 13 .
  • Figure 15A is a waveform diagram of the potential of the first node N1 and the driving signal in at least one embodiment of the driving circuit shown in Figure 10
  • Figure 15B is a waveform diagram of the potential of the first node N1, the potential of the second output node NO2, and the driving signal in at least one embodiment of the driving circuit shown in Figure 13.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 16 and at least one embodiment of the driving circuit shown in FIG. 10 is that T9 is removed, and the second end of C1 is electrically connected to the first clock signal line CKB instead.
  • FIG. 17 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG. 16 .
  • At least one embodiment of the driving circuit shown in FIG. 10 , at least one embodiment of the driving circuit shown in FIG. 13 , and at least one embodiment of the driving circuit shown in FIG. 16 need to be used in conjunction with LTPO (low temperature polycrystalline oxide) products.
  • LTPO low temperature polycrystalline oxide
  • T3 is a p-type transistor, and the gate of T3 is electrically connected to the inverting input terminal STV2;
  • the first output node NO1 is electrically connected to the adjacent next stage inverting input terminal STV2(n+1), and the driving output terminal O1 is electrically connected to the adjacent next stage input terminal STV(n+1);
  • the inverting input signal provided by the inverting input terminal STV2 is inverted with the input signal provided by STV.
  • At least one embodiment of the driving circuit shown in Figure 18 sets the potential of NO1 by STV2(n+1), and sets the driving signal output by O1 by STV(n+1). At least one embodiment of the driving circuit shown in Figure 18 also has no output falling edge step and is suitable for LTPS (low-temperature polycrystalline silicon) products and LTPO products.
  • LTPS low-temperature polycrystalline silicon
  • FIG. 19 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG. 18 .
  • At least one embodiment of the driving circuit shown in FIG20 further includes an energy storage control circuit
  • the energy storage control circuit includes a fourth transistor T4;
  • the first end of the first capacitor C1 is electrically connected to the second output node NO2, and the second end of the first capacitor is electrically connected to the energy storage node NC;
  • the gate of the fourth transistor T4 is electrically connected to the second output node NO2 , the source of the fourth transistor T4 is electrically connected to the energy storage node NC, and the drain of the fourth transistor T4 is electrically connected to the first clock signal line CKB.
  • T4 is a p-type transistor.
  • At least one embodiment of the driving circuit shown in Figure 20 adds a secondary pull-down unit.
  • the potential of NO2 is a low voltage
  • the potential of NO2 will be pulled down each time the potential of the first clock signal provided by CKB drops to a low level.
  • the pull-down ability of NO2 is stronger, and the driving signal output by O1 is more stable.
  • FIG. 21 is a layout diagram of at least one embodiment of the driving circuit shown in FIG. 10 .
  • the line labeled STV0 is the starting voltage line
  • the line labeled CKB is the first clock signal line
  • the line labeled CK is the second clock signal line
  • the line labeled VGL is the first low voltage line
  • the line labeled VGL2 is the second low voltage line
  • the line labeled VGH is the high voltage line.
  • Figure 22 is a layout diagram of the first semiconductor layer in Figure 21
  • Figure 23 is a layout diagram of the first gate metal layer in Figure 21
  • Figure 24 is a layout diagram of the second gate metal layer in Figure 21
  • Figure 25 is a layout diagram of the third gate metal layer in Figure 21
  • Figure 26 is a layout diagram of the second semiconductor layer in Figure 21
  • Figure 27 is a layout diagram of the source and drain metal layers in Figure 21.
  • the first semiconductor layer, the first gate metal layer, the second gate metal layer, the second semiconductor layer, the third gate metal layer and the source-drain metal layer are arranged in sequence along a direction away from the substrate.
  • the first active pattern is labeled A01
  • the second active pattern is labeled A02
  • the active pattern is labeled A6 of T6;
  • the upper half of A01 and the upper half of A02 serve as active patterns of T12, and the lower half of A01 and the lower half of A02 serve as active patterns of T13.
  • the first semiconductor layer may be made of polysilicon.
  • G12 is the gate of T12
  • G13 is the gate of T13
  • C1a is the first electrode plate of C1
  • C2a is the first electrode plate of C2 .
  • the second electrode plate of C1 is labeled C1b
  • the second electrode plate of C2 is labeled C2b
  • the second electrode plate of C2 is labeled G31 is the first gate of T3.
  • the reference numeral G32 is the second gate electrode of T3 .
  • the active pattern labeled A3 is T3.
  • the second semiconductor layer may be made of IGZO (Indium Gallium Zinc Oxide).
  • the line labeled STV0 is the starting voltage line
  • the line labeled CKB is the first clock signal line
  • the line labeled CK is the second clock signal line
  • the line labeled VGL is the first low voltage line
  • the line labeled VGL2 is the second low voltage line
  • the line labeled VGH is the high voltage line.
  • T3 may be a dual-gate transistor, but is not limited thereto.
  • T3 is set as a dual gate transistor.
  • the driving circuit includes only two capacitors, and the number of capacitors used is reduced, which can reduce the space occupied by the driving circuit.
  • the driving method described in the embodiment of the present invention is applied to the above-mentioned driving circuit, and the driving method includes:
  • the first node control circuit controls the potential of the first node
  • the first control circuit controls the connection or disconnection between the second node and the first voltage line under the control of the set control signal
  • the second control circuit controls the connection or disconnection between the second node and the second voltage line under the control of the first clock signal and the potential of the second node;
  • the output node control circuit controls the connection or disconnection between the second node and the first output node under the control of the first clock signal
  • the output circuit controls the driving output terminal to output a driving signal under the control of the potential of the first output node and the potential of the second output node.
  • the display device described in the embodiment of the present invention includes the above-mentioned driving circuit.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种驱动电路、驱动方法和显示装置。该驱动电路包括第一节点控制电路（11）、第一控制电路（12）、第二控制电路（13）、输出节点控制电路（14）、第一储能电路（15）和输出电路（16）；第一控制电路（12）在置位控制信号的控制下，控制第二节点（N2）与第一电压线（V1）之间连通或断开；第二控制电路（13）在第一时钟信号（CKB）和第二节点（N2）的电位的控制下，控制第二节点（N2）与第二电压线（V2）之间连通或断开；输出节点控制电路（14）在第一时钟信号（CKB）的控制下，控制第二节点（N2）与第一输出节点（N01）之间连通或断开。能够在降低功耗的前提下，保证驱动信号输出稳定性。

Description

驱动电路、驱动方法和显示装置
相关申请的交叉引用
本申请主张在2023年5月25日在中国提交的中国专利申请号No.202310597420.1的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种驱动电路、驱动方法和显示装置。
背景技术
相关的驱动电路采用了用于控制第二节点的电位的电容，该电容的第一端与第二节点电连接，该电容的第二端通过晶体管与时钟信号线电连接，进而能够使得第二节点的电位的波形会有耦合波动而产生的台阶，功耗大，并驱动信号输出稳定性低。
发明内容
在一个方面中，本实施例提供了一种驱动电路，包括第一节点控制电路、第一控制电路、第二控制电路、输出节点控制电路、第一储能电路和输出电路；
所述第一节点控制电路与第一节点电连接，用于控制第一节点的电位；
所述第一控制电路分别与置位控制端、第一电压线和第二节点电连接，用于在所述置位控制端提供的置位控制信号的控制下，控制所述第二节点与所述第一电压线之间连通或断开；
所述第二控制电路分别与第一时钟信号线、所述第二节点和第二电压线电连接，用于在所述第一时钟信号线提供的第一时钟信号和所述第二节点的电位的控制下，控制所述第二节点与所述第二电压线之间连通或断开；
所述输出节点控制电路分别与第一时钟信号线、所述第二节点和第一输出节点电连接，用于在所述第一时钟信号的控制下，控制所述第二节点与所述第一输出节点之间连通或断开；
所述第一储能电路与第二输出节点电连接，用于储存电能；
所述输出电路分别与所述第一输出节点、所述第二输出节点和驱动输出端电连接，用于在所述第一输出节点的电位和所述第二输出节点的电位的控制下，控制所述驱动输出端输出驱动信号。
可选的，所述第一储能电路的第一端与所述第二输出节点电连接，所述第一储能电路的第二端与所述驱动输出端电连接。
可选的，所述第一节点与所述第二输出节点为同一节点；或者，
所述驱动电路还包括通断控制电路；所述第一节点通过所述通断控制电路与所述第二 输出节点电连接；所述通断控制电路的控制端与第三电压线电连接，所述通断控制电路用于在所述第三电压线提供的第三电压信号的控制下，控制所述第一节点与所述第二输出节点之间连通或断开。
可选的，本发明至少一实施例所述的驱动电路还包括储能控制电路；
所述储能控制电路分别与所述第二输出节点、所述第一时钟信号线和储能节点电连接，用于在所述第二输出节点的电位的控制下，控制所述第一时钟信号线与所述储能节点之间连通或断开；
所述第一储能电路的第一端与所述第二输出节点电连接，所述第一储能电路的第二端与所述储能节点电连接。
可选的，所述第一储能电路的第一端与所述第二输出节点电连接，所述第一储能电路的第二端与第一时钟信号线电连接。
可选的，本发明至少一实施例所述的驱动电路还包括第三控制电路；
所述第三控制电路分别与所述第二输出节点、所述第一输出节点和第四电压线电连接，用于在所述第二输出节点的电位的控制下，控制所述第一输出节点与所述第四电压线之间连通或断开；或者，
所述第三控制电路分别与所述第一节点、所述第一输出节点和第四电压线电连接，用于在所述第一节点的电位的控制下，控制所述第一输出节点与所述第四电压线之间连通或断开。
可选的，本发明至少一实施例所述的驱动电路还包括第四控制电路；
所述第四控制电路分别与所述第一节点、第四电压线和所述第二节点电连接，用于在所述第一节点的电位的控制下，控制所述第二节点与所述第四电压线之间连通或断开。
可选的，本发明至少一实施例所述的驱动电路还包括第二储能电路；所述第二储能电路与所述第一输出节点电连接，用于储存电能。
可选的，所述第二控制电路包括第一晶体管和第二晶体管；
所述第一晶体管的栅极与所述第二节点电连接，所述第一晶体管的第一极与所述第二电压线电连接，所述第一晶体管的第二极与所述第二晶体管的第一极电连接；
所述第二晶体管的栅极与所述第一时钟信号线电连接，所述第二晶体管的第二极与所述第二节点电连接。
可选的，所述第一控制电路包括第三晶体管；所述置位控制端为输入端；
所述第三晶体管的栅极与所述输入端电连接，所述第三晶体管的第一极与所述第一电压线电连接，所述第三晶体管的第二极与所述第二节点电连接；
所述第三晶体管为氧化物晶体管。
可选的，所述置位控制端为反相输入端；所述第一控制电路包括第三晶体管；
所述第三晶体管的栅极与所述反相输入端电连接，所述第三晶体管的第一极与所述第一电压线电连接，所述第三晶体管的第二极与所述第二节点电连接；
所述第三晶体管为p型晶体管；
所述反相输入端用于提供反相输入信号，所述反相输入信号与输入端提供的输入信号反相。
可选的，所述第一输出节点与相邻下一级反相输入端电连接，所述驱动输出端与相邻下一级输入端电连接。
可选的，所述第一储能电路包括第一电容；
所述第一电容的第一端与所述第二输出节点电连接，所述第一电容的第二端与所述驱动输出端电连接。
可选的，所述第一储能电路包括第一电容；
所述第一电容的第一端与所述第二输出节点电连接，所述第一电容的第二端与所述第一时钟信号线电连接。
可选的，所述第一储能电路包括第一电容，所述储能控制电路包括第四晶体管；
所述第一电容的第一端与所述第二输出节点电连接；所述第一电容的第二端与所述储能节点电连接；
所述第四晶体管的栅极与所述第二输出节点电连接，所述第四晶体管的第一极与所述储能节点电连接，所述第四晶体管的第二极与所述第一时钟信号线电连接。
可选的，所述第四控制电路包括第五晶体管；
所述第五晶体管的栅极与所述第一节点电连接，所述第五晶体管的第一极与所述第四电压线电连接，所述第五晶体管的第二极与所述第二节点电连接。
可选的，所述第一节点控制电路还分别与输入端、第二节点、第二时钟信号线、第一时钟信号线和第四电压线电连接，用于在所述第二时钟信号线提供的第二时钟信号的控制下，控制所述第一节点与所述输入端之间连通或断开，在所述第一时钟信号和所述第二节点的电位的控制下，控制所述第一节点与所述第四电压线之间连通或断开。
可选的，所述第一节点控制电路包括第六晶体管、第七晶体管和第八晶体管；
所述第六晶体管的栅极与所述第二时钟信号线电连接，所述第六晶体管的第一极与所述输入端电连接，所述第六晶体管的第二极与所述第一节点电连接；
所述第七晶体管的栅极与所述第一时钟信号线电连接，所述第七晶体管的第一极与所述第四电压线电连接，所述第七晶体管的第二极与所述第八晶体管的第一极电连接；
所述第八晶体管的栅极与所述第二节点电连接，所述第八晶体管的第二极与所述第一节点电连接。
可选的，所述第三控制电路包括第九晶体管；
所述第九晶体管的栅极与所述第二输出节点电连接，所述第九晶体管的第一极与所述第四电压线电连接，所述第九晶体管的第二极与所述第一输出节点电连接。
可选的，所述输出节点控制电路包括第十晶体管；
所述第十晶体管的栅极与所述第一时钟信号线电连接，所述第十晶体管的第一极与所 述第二节点电连接，所述第十晶体管的第二极与所述第一输出节点电连接。
可选的，所述驱动电路还包括通断控制电路；
所述通断控制电路包括第十一晶体管；
所述第十一晶体管的栅极与所述第三电压线电连接，所述第十一晶体管的第一极与所述第一节点电连接，所述第十二晶体管的第一极与所述第二输出节点电连接。
可选的，所述输出电路包括第十二晶体管和第十三晶体管；
所述第十二晶体管的栅极与所述第一输出节点电连接，所述第十二晶体管的第一极与第五电压线电连接，所述第十二晶体管的第二极与所述驱动输出端电连接；
所述第十三晶体管的栅极与所述第二输出节点电连接，所述第十三晶体管的第一极与所述驱动输出端电连接，所述第十三晶体管的第二极与第六电压线电连接。
在第二个方面中，本发明实施例提供一种驱动方法，应用于上述的驱动电路，所述驱动方法包括：
第一节点控制电路控制第一节点的电位；
第一控制电路在置位控制信号的控制下，控制第二节点与第一电压线之间连通或断开；
第二控制电路在第一时钟信号和所述第二节点的电位的控制下，控制所述第二节点与第二电压线之间连通或断开；
输出节点控制电路在所述第一时钟信号的控制下，控制所述第二节点与第一输出节点之间连通或断开；
输出电路在所述第一输出节点的电位和第二输出节点的电位的控制下，控制驱动输出端输出驱动信号。
在第三个方面中，本发明实施例提供一种显示装置，包括上述的驱动电路。
附图说明
图1是本发明至少一实施例所述的驱动电路的结构图；
图2是本发明至少一实施例所述的驱动电路的结构图；
图3是本发明至少一实施例所述的驱动电路的结构图；
图4是本发明至少一实施例所述的驱动电路的结构图；
图5是本发明至少一实施例所述的驱动电路的结构图；
图6是本发明至少一实施例所述的驱动电路的结构图；
图7是本发明至少一实施例所述的驱动电路的结构图；
图8是本发明至少一实施例所述的驱动电路的结构图；
图9是本发明至少一实施例所述的驱动电路的结构图；
图10是本发明至少一实施例所述的驱动电路的电路图；
图11是图10所示的驱动电路的至少一实施例的工作时序图；
图12是图10所示的驱动电路的至少一实施例的仿真工作时序图；
图13是本发明至少一实施例所述的驱动电路的电路图；
图14是图13所示的驱动电路的至少一实施例的仿真工作时序图；
图15A是图10所示的驱动电路的至少一实施例中的第一节点N1的电位和驱动信号的波形图；
图15B是图13所示的驱动电路的至少一实施例中的第一节点N1的电位、第二输出节点NO2的电位和驱动信号的波形图；
图16是本发明至少一实施例所述的驱动电路的电路图；
图17是图16所示的驱动电路的至少一实施例的工作时序图；
图18是本发明至少一实施例所述的驱动电路的电路图；
图19是图18所示的驱动电路的至少一实施例的工作时序图；
图20是本发明至少一实施例所述的驱动电路的电路图；
图21是图10所示的驱动电路的至少一实施例的布局图；
图22是图21中的第一半导体层的布局图；
图23是图21中的第一栅金属层的布局图；
图24是图21中的第二栅金属层的布局图；
图25是图21中的第三栅金属层的布局图；
图26是图21中的第二半导体层的布局图；
图27的图21中的源漏金属层的布局图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本发明实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
本发明实施例所述的驱动电路包括第一节点控制电路、第一控制电路、第二控制电路、输出节点控制电路、第一储能电路和输出电路；
所述第一节点控制电路与第一节点电连接，用于控制第一节点的电位；
所述第一控制电路分别与置位控制端、第一电压线和第二节点电连接，用于在所述置位控制端提供的置位控制信号的控制下，控制所述第二节点与所述第一电压线之间连通或断开；
所述第二控制电路分别与第一时钟信号线、所述第二节点和第二电压线电连接，用于在所述第一时钟信号线提供的第一时钟信号和所述第二节点的电位的控制下，控制所述第二节点与所述第二电压线之间连通或断开；
所述输出节点控制电路分别与第一时钟信号线、所述第二节点和第一输出节点电连接，用于在所述第一时钟信号的控制下，控制所述第二节点与所述第一输出节点之间连通或断开；
所述第一储能电路与第二输出节点电连接，用于储存电能；
所述输出电路分别与所述第一输出节点、所述第二输出节点和驱动输出端电连接，用于在所述第一输出节点的电位和所述第二输出节点的电位的控制下，控制所述驱动输出端输出驱动信号。
本发明实施例所述的驱动电路通过采用第一控制电路和第二控制电路，以控制第二节点的电位，相比于相关的驱动电路，减少采用了用于控制第二节点的电位的电容，利于实现窄边框，并且，在本发明实施例中，第二控制电路能够控制第二节点的电位稳定，本发明实施例未采用与第二节点电连接的电容(该电容的第一端与第二节点电连接，该电容的第二端通过晶体管与时钟信号线电连接)，进而能够使得第二节点的电位的波形无由于耦合波动而产生的台阶，本发明实施例能够在降低功耗的前提下，保证驱动信号输出稳定性。
在本发明至少一实施例中，所述第一节点与所述第二输出节点为同一节点；或者，
所述驱动电路还包括通断控制电路；所述第一节点通过所述通断控制电路与所述第二输出节点电连接；所述通断控制电路的控制端与第三电压线电连接，所述通断控制电路用于在所述第三电压线提供的第三电压信号的控制下，控制所述第一节点与所述第二输出节点之间连通或断开。
在具体实施时，所述第一节点和所述第二输出节点可以为同一节点，或者，在第一节点和第二输出节点之间可以通过通断控制电路电连接。
可选的，所述第一电压线可以为第一低电压线，所述第二电压线可以为第二低电压线。
如图1所示，本发明实施例所述的驱动电路包括第一节点控制电路11、第一控制电路12、第二控制电路13、输出节点控制电路14、第一储能电路15和输出电路16；
所述第一节点控制电路11与第一节点N1电连接，用于控制第一节点N1的电位；
所述第一控制电路12分别与置位控制端ZC、第一电压线V1和第二节点N2电连接，用于在所述置位控制端ZC提供的置位控制信号的控制下，控制所述第二节点N2与所述第一电压线V1之间连通或断开；
所述第二控制电路13分别与第一时钟信号线CKB、所述第二节点N2和第二电压线V2电连接，用于在所述第一时钟信号线CKB提供的第一时钟信号和所述第二节点N2的电位的控制下，控制所述第二节点N2与所述第二电压线V2之间连通或断开；
所述输出节点控制电路14分别与第一时钟信号线CKB、所述第二节点N2和第一输出节点NO1电连接，用于在所述第一时钟信号的控制下，控制所述第二节点N2与所述第 一输出节点NO1之间连通或断开；
所述第一储能电路15与第一节点N1电连接，用于储存电能；
所述输出电路16分别与所述第一输出节点NO1、所述一节点N1和驱动输出端O1电连接，用于在所述第一输出节点NO1的电位和所述第一节点N1的电位的控制下，控制所述驱动输出端O1输出驱动信号。
在图1所示的至少一实施例中，所述第二输出节点与第一节点N1为同一节点。
如图2所示，本发明实施例所述的驱动电路包括第一节点控制电路11、第一控制电路12、第二控制电路13、输出节点控制电路14、第一储能电路15、输出电路16和通断控制电路21；
所述第一节点N1通过所述通断控制电路21与第二输出节点NO2电连接；所述通断控制电路21的控制端与第三电压线V3电连接，所述通断控制电路21用于在所述第三电压线V3提供的第三电压信号的控制下，控制所述第一节点N1与所述第二输出节点NO2之间连通或断开；
所述第一节点控制电路11与第一节点N1电连接，用于控制第一节点N1的电位；
所述第一控制电路12分别与置位控制端ZC、第一电压线V1和第二节点N2电连接，用于在所述置位控制端ZC提供的置位控制信号的控制下，控制所述第二节点N2与所述第一电压线V1之间连通或断开；
所述第二控制电路13分别与第一时钟信号线CKB、所述第二节点N2和第二电压线V2电连接，用于在所述第一时钟信号线CKB提供的第一时钟信号和所述第二节点N2的电位的控制下，控制所述第二节点N2与所述第二电压线V2之间连通或断开；
所述输出节点控制电路14分别与第一时钟信号线CKB、所述第二节点N2和第一输出节点NO1电连接，用于在所述第一时钟信号的控制下，控制所述第二节点N2与所述第一输出节点NO1之间连通或断开；
所述第一储能电路15与第二输出节点NO2电连接，用于储存电能；
所述输出电路15分别与所述第一输出节点NO1、所述第二输出节点NO2和驱动输出端O1电连接，用于在所述第一输出节点NO1的电位和所述第二输出节点NO2的电位的控制下，控制所述驱动输出端O1输出驱动信号。
在图2所示的至少一实施例中，第一节点N1与第二输出节点NO2之间设置有由第三电压线V3控制的通断控制电路21。
可选的，所述第三电压线V3可以为第一低电压线，但不以此为限。
在本发明至少一实施例中，所述第一储能电路的第一端与所述第二输出节点电连接，所述第一储能电路的第二端与所述驱动输出端电连接。
在具体实施时，所述第一储能电路的第二端可以与驱动输出端电连接，而不与时钟信号线电连接，因此，第二输出节点的电位不会由于第一储能电路的耦合作用而产生台阶，能够稳定第二输出节点的电位，进而提升所述驱动电路输出的驱动信号的稳定性。
本发明至少一实施例所述的驱动电路还可以包括储能控制电路；
所述储能控制电路分别与所述第二输出节点、所述第一时钟信号线和储能节点电连接，用于在所述第二输出节点的电位的控制下，控制所述第一时钟信号线与所述储能节点之间连通或断开；
所述第一储能电路的第一端与所述第二输出节点电连接，所述第一储能电路的第二端与所述储能节点电连接。
在本发明至少一实施例中，所述驱动电路还可以包括储能控制电路，所述储能控制电路在第二输出节点的电位的控制下，控制第一时钟信号线与储能节点之间连通或断开。
如图3所示，在图2所示的驱动电路的至少一实施例的基础上，本发明至少一实施例所述的驱动电路还包括储能控制电路31；
所述储能控制电路31分别与所述第二输出节点NO2、所述第一时钟信号线CKB和储能节点NC电连接，用于在所述第二输出节点NO2的电位的控制下，控制所述第一时钟信号线CKB与所述储能节点NC之间连通或断开；
所述第一储能电路15的第一端与所述第二输出节点NO2电连接，所述第一储能电路15的第二端与所述储能节点NC电连接。
本发明图3所示的驱动电路的至少一实施例在工作时，当NO1的电位为低电压，并每当CKB提供的第一时钟信号的电位被置低时，NO1的电位均会被下拉，使得输出电路包括的复位晶体管完全开启，使得所述驱动电路输出的驱动信号更加稳定。
可选的，所述第一储能电路的第一端与所述第二输出节点电连接，所述第一储能电路的第二端与第一时钟信号线电连接。
在具体实施，所述第一储能电路可以分别与第二输出节点和第一时钟信号线电连接。
本发明至少一实施例所述的驱动电路还包括第三控制电路；
所述第三控制电路分别与所述第二输出节点、所述第一输出节点和第四电压线电连接，用于在所述第二输出节点的电位的控制下，控制所述第一输出节点与所述第四电压线之间连通或断开；或者，
所述第三控制电路分别与所述第一节点、所述第一输出节点和第四电压线电连接，用于在所述第一节点的电位的控制下，控制所述第一输出节点与所述第四电压线之间连通或断开。
在具体实施时，所述像素电路还可以包括第三控制电路，第三控制电路可以在第二输出节点的电位或第一节点的电位的控制下，控制第一输出节点与第四电压线之间连通或断开，以在所述第二输出节点的电位和/或所述第一节点的电位为低电压信号时，控制所述第一输出节点的电位为高电压。
可选的，所述第四电压线可以为高电压线。
如图4所示，在图1所示的驱动电路的至少一实施例的基础上，本发明至少一实施例所述的驱动电路还可以包括第三控制电路41；
第三控制电路41分别与第一节点N1、第一输出节点NO1和第四电压线V4电连接，用于在所述第一节点N1的电位的控制下，控制所述第一输出节点NO1与所述第四电压线V4之间连通或断开。
如图5所示，在图2所示的驱动电路的至少一实施例的基础上，本发明至少一实施例所述的驱动电路还可以包括第三控制电路41；
第三控制电路41分别与第二输出节点NO2、第一输出节点NO1和第四电压线V4电连接，用于在所述第二输出节点NO2的电位的控制下，控制所述第一输出节点NO1与所述第四电压线V4之间连通或断开。
如图6所示，在图3所示的驱动电路的至少一实施例的基础上，本发明至少一实施例所述的驱动电路还可以包括第三控制电路41；
第三控制电路41分别与第一节点N1、第一输出节点NO1和第四电压线V4电连接，用于在所述第一节点N1的电位的控制下，控制所述第一输出节点NO1与所述第四电压线V4之间连通或断开。
在本发明至少一实施例中，所述驱动电路还可以包括第四控制电路；
所述第四控制电路分别与所述第一节点、第四电压线和所述第二节点电连接，用于在所述第一节点的电位的控制下，控制所述第二节点与所述第四电压线之间连通或断开。
在具体实施时，所述驱动电路还可以包括第四控制电路，第四控制电路在第一节点的电位的控制下，控制第二节点与第四电压线之间连通或断开，以在第一节点的电位为低电压时，控制第二节点的电位为高电压。
本发明至少一实施例所述的驱动电路还包括第二储能电路；所述第二储能电路与所述第一输出节点电连接，用于储存电能。
可选的，所述第二控制电路包括第一晶体管和第二晶体管；
所述第一晶体管的栅极与所述第二节点电连接，所述第一晶体管的第一极与所述第二电压线电连接，所述第一晶体管的第二极与所述第二晶体管的第一极电连接；
所述第二晶体管的栅极与所述第一时钟信号线电连接，所述第二晶体管的第二极与所述第二节点电连接。
在本发明至少一实施例中，所述第一控制电路可以包括第三晶体管；所述置位控制端为输入端；
所述第三晶体管的栅极与所述输入端电连接，所述第三晶体管的第一极与所述第一电压线电连接，所述第三晶体管的第二极与所述第二节点电连接；
所述第三晶体管为氧化物晶体管。
在本发明至少一实施例中，所述置位控制端可以为反相输入端；所述第一控制电路包括第三晶体管；
所述第三晶体管的栅极与所述反相输入端电连接，所述第三晶体管的第一极与所述第一电压线电连接，所述第三晶体管的第二极与所述第二节点电连接；
所述第三晶体管为p型晶体管；
所述反相输入端用于提供反相输入信号，所述反相输入信号与输入端提供的输入信号反相。
在本发明至少一实施例中，所述第一输出节点与相邻下一级反相输入端电连接，所述驱动输出端与相邻下一级输入端电连接。
可选的，所述第一储能电路包括第一电容；
所述第一电容的第一端与所述第二输出节点电连接，所述第一电容的第二端与所述驱动输出端电连接。
可选的，所述第一储能电路包括第一电容；
所述第一电容的第一端与所述第二输出节点电连接，所述第一电容的第二端与所述第一时钟信号线电连接。
在本发明至少一实施例中，所述第一储能电路包括第一电容，所述储能控制电路包括第四晶体管；
所述第一电容的第一端与所述第二输出节点电连接；所述第一电容的第二端与所述储能节点电连接；
所述第四晶体管的栅极与所述第二输出节点电连接，所述第四晶体管的第一极与所述储能节点电连接，所述第四晶体管的第二极与所述第一时钟信号线电连接，
可选的，所述第四控制电路包括第五晶体管；
所述第五晶体管的栅极与所述第一节点电连接，所述第五晶体管的第一极与所述第四电压线电连接，所述第五晶体管的第二极与所述第二节点电连接。
在本发明至少一实施例中，所述第一节点控制电路还分别与输入端、第二节点、第二时钟信号线、第一时钟信号线和第四电压线电连接，用于在所述第二时钟信号线提供的第二时钟信号的控制下，控制所述第一节点与所述输入端之间连通或断开，在所述第一时钟信号和所述第二节点的电位的控制下，控制所述第一节点与所述第四电压线之间连通或断开。
在具体实施时，第一节点控制电路可以在第二时钟信号的控制下，控制所述第一节点与所述输入端之间连通或断开，在所述第一时钟信号和所述第二节点的电位的控制下，控制所述第一节点与所述第四电压线之间连通或断开，以控制所述第一节点的电位。
如图7所示，在图4所示的驱动电路的至少一实施例的基础上，本发明至少一实施例所述的驱动电路还可以包括第四控制电路71和第二储能电路72；
所述第四控制电路71分别与所述第一节点N1、第四电压线V4和所述第二节点N2电连接，用于在所述第一节点N1的电位的控制下，控制所述第二节点N2与所述第四电压线V4之间连通或断开；
所述第二储能电路72分别与所述第一输出节点NO1和第四电压线V4电连接，用于储存电能；
所述第一节点控制电路11还分别与输入端STV、第二节点N2、第二时钟信号线CK、第一时钟信号线CKB和第四电压线V4电连接，用于在所述第二时钟信号线CK提供的第二时钟信号的控制下，控制所述第一节点N1与所述输入端STV之间连通或断开，在所述第一时钟信号和所述第二节点N2的电位的控制下，控制所述第一节点N1与所述第四电压线V4之间连通或断开。
本发明图7所示的驱动电路的至少一实施例在工作时，第四控制电路70可以在所述第一节点N1的电位为低电压时，控制N2的电位为高电压，第二储能电路72能够维持第一输出节点NO1的电位；第一节点控制电路11在第二时钟信号、第一时钟信号和第二节点N2的电位的控制下，控制第一节点N1的电位。
如图8所示，在图5所示的驱动电路的至少一实施例的基础上，本发明至少一实施例所述的驱动电路还可以包括第四控制电路71和第二储能电路72；
所述第四控制电路71分别与所述第一节点N1、第四电压线V4和所述第二节点N2电连接，用于在所述第一节点N1的电位的控制下，控制所述第二节点N2与所述第四电压线V4之间连通或断开；
所述第二储能电路72分别与所述第一输出节点NO1和第四电压线V4电连接，用于储存电能；
所述第一节点控制电路11还分别与输入端STV、第二节点N2、第二时钟信号线CK、第一时钟信号线CKB和第四电压线V4电连接，用于在所述第二时钟信号线CK提供的第二时钟信号的控制下，控制所述第一节点N1与所述输入端STV之间连通或断开，在所述第一时钟信号和所述第二节点N2的电位的控制下，控制所述第一节点N1与所述第四电压线V4之间连通或断开。
如图9所示，在图6所示的驱动电路的至少一实施例的基础上，本发明至少一实施例所述的驱动电路还可以包括第四控制电路71和第二储能电路72；
所述第四控制电路71分别与所述第一节点N1、第四电压线V4和所述第二节点N2电连接，用于在所述第一节点N1的电位的控制下，控制所述第二节点N2与所述第四电压线V4之间连通或断开；
所述第二储能电路72分别与所述第一输出节点NO1和第四电压线V4电连接，用于储存电能；
所述第一节点控制电路11还分别与输入端STV、第二节点N2、第二时钟信号线CK、第一时钟信号线CKB和第四电压线V4电连接，用于在所述第二时钟信号线CK提供的第二时钟信号的控制下，控制所述第一节点N1与所述输入端STV之间连通或断开，在所述第一时钟信号和所述第二节点N2的电位的控制下，控制所述第一节点N1与所述第四电压线V4之间连通或断开。
可选的，所述第一节点控制电路包括第六晶体管、第七晶体管和第八晶体管；
所述第六晶体管的栅极与所述第二时钟信号线电连接，所述第六晶体管的第一极与所 述输入端电连接，所述第六晶体管的第二极与所述第一节点电连接；
所述第七晶体管的栅极与所述第一时钟信号线电连接，所述第七晶体管的第一极与所述第四电压线电连接，所述第七晶体管的第二极与所述第八晶体管的第一极电连接；
所述第八晶体管的栅极与所述第二节点电连接，所述第八晶体管的第二极与所述第一节点电连接。
可选的，所述第三控制电路包括第九晶体管；
所述第九晶体管的栅极与所述第二输出节点电连接，所述第九晶体管的第一极与所述第四电压线电连接，所述第九晶体管的第二极与所述第一输出节点电连接。
可选的，所述输出节点控制电路包括第十晶体管；
所述第十晶体管的栅极与所述第一时钟信号线电连接，所述第十晶体管的第一极与所述第二节点电连接，所述第十晶体管的第二极与所述第一输出节点电连接。
在本发明至少一实施例中，所述驱动电路还可以包括通断控制电路；
所述通断控制电路包括第十一晶体管；
所述第十一晶体管的栅极与所述第三电压线电连接，所述第十一晶体管的第一极与所述第一节点电连接，所述第十一晶体管的第二极与所述第二输出节点电连接。
可选的，所述输出电路包括第十二晶体管和第十三晶体管；
所述第十二晶体管的栅极与所述第一输出节点电连接，所述第十二晶体管的第一极与第五电压线电连接，所述第十二晶体管的第二极与所述驱动输出端电连接；
所述第十三晶体管的栅极与所述第二输出节点电连接，所述第十三晶体管的第一极与所述驱动输出端电连接，所述第十三晶体管的第二极与第六电压线电连接。
在本发明至少一实施例中，所述第五电压线可以为高电压线，所述第六电压线可以为第一低电压线，但不以此为限。
如图10所示，在图7所示的驱动电路的至少一实施例的基础上，
所述第一节点控制电路包括第六晶体管T6、第七晶体管T7和第八晶体管T8；
所述第六晶体管T6的栅极与所述第二时钟信号线CK电连接，所述第六晶体管T6的源极与所述输入端STV电连接，所述第六晶体管T6的漏极与所述第一节点N1电连接；
所述第七晶体管T7的栅极与所述第一时钟信号线CKB电连接，所述第七晶体管T7的源极与高电压线VGH电连接，所述第七晶体管T7的漏极与所述第八晶体管T8的源极电连接；
所述第八晶体管T8的栅极与所述第二节点N2电连接，所述第八晶体管T8的漏极与所述第一节点N1电连接；
所述第三控制电路包括第九晶体管T9；
所述第九晶体管T9的栅极与第一节点N1电连接，所述第九晶体管T9的源极与高电压线VGH电连接，所述第九晶体管T9的漏极与所述第一输出节点NO1电连接；
所述输出节点控制电路包括第十晶体管T10；
所述第十晶体管T10的栅极与所述第一时钟信号线CKB电连接，所述第十晶体管T10的源极与所述第二节点N2电连接，所述第十晶体管T10的漏极与所述第一输出节点NO1电连接；
所述第二控制电路包括第一晶体管T1和第二晶体管T2；
所述第一晶体管T1的栅极与所述第二节点N2电连接，所述第一晶体管T1的源极与所述第二低电压线VGL2电连接，所述第一晶体管T1的漏极与所述第二晶体管T2的源极电连接；
所述第二晶体管T2的栅极与所述第一时钟信号线CKB电连接，所述第二晶体管T2的漏极与所述第二节点N2电连接；
所述第一控制电路包括第三晶体管T3；所述置位控制端为输入端STV；
所述第三晶体管T3的栅极与所述输入端STV电连接，所述第三晶体管T3的源极与低电压线VGL电连接，所述第三晶体管T3的漏极与所述第二节点N2电连接；
所述第三晶体管T3为氧化物晶体管；
所述第一储能电路包括第一电容C1；
C1的第一端与第一节点N1电连接，C1的第二端与所述驱动输出端O1电连接；
所述第四控制电路包括第五晶体管T5；
所述第五晶体管T5的栅极与所述第一节点N1电连接，所述第五晶体管T5的源极与高电压线VGH电连接，所述第五晶体管T5的漏极与所述第二节点N2电连接；
所述第二储能电路包括第二电容C2；
所述第二电容C2的第一端与第一输出节点NO1电连接，所述第二电容C2的第二端与高电压线VGH电连接；
所述输出电路包括第十二晶体管T12和第十三晶体管T13；
所述第十二晶体管T12的栅极与所述第一输出节点NO1电连接，所述第十二晶体管T12的源极与高电压线VGH电连接，所述第十二晶体管T12的漏极与所述驱动输出端O1电连接；
所述第十三晶体管T13的栅极与所述第一节点N1电连接，所述第十三晶体管T13的源极与所述驱动输出端O1电连接，所述第十三晶体管T13的漏极与第一低电压线VGL电连接。
在图10所示的驱动电路的至少一实施例中，T3为n型晶体管，T6可以为双栅晶体管，以防止漏电；
图10中的除了T3之外的晶体管可以都为p型晶体管。
在图10所示的驱动电路的至少一实施例中，N3为第三节点，N4为第四节点；第三节点N3为T7与T8之间的连接节点，第四节点N4为T1和T2之间的连接节点。
在本发明至少一实施例中，VGL提供的第一低电压信号的电压值可以大于或等于-10V而小于或等于-7V，VGL2提供的第二低电压信号的电压值可以大于或等于-10V而小于或 等于-7V，第一低电压信号的电压值与第二低电压信号的电压值可以相等，也可以不相等。
如图11所示，本发明如10所示的驱动电路的至少一实施例在工作时，显示周期可以包括先后设置的第一阶段t1、第二阶段t2、第三阶段t3、第四阶段t4、第五阶段t5、第六阶段t6、第七阶段t7和第八阶段t8；
在第一阶段t1，STV提供高电压信号，CKB提供高电压信号，CK提供低电压信号，T6和T3打开，N2的电位为低电压，T8打开，T1打开，N1的电位为高电压，NO1的电位为高电压，O1输出的驱动信号的电位保持为低电压；
在第二阶段t2，STV提供高电压信号，CK提供高电压信号，CKB提供低电压信号，T3打开，N2的电位为低电压，T2打开，T10打开，NO1的电位为低电压，T12打开，O1输出高电压信号；T7和T8打开，N1的电位为高电压，T13关断；
在第三阶段t3，STV提供高电压信号，CK提供低电压信号，CKB提供高电压信号，T6和T3打开，N2的电位为低电压，N1的电位为高电压，T1打开，T2关断，T8开启，T7关断，T10关断，NO1的电位维持为低电压，T12打开，T13关断，O1输出高电压信号；
在第四阶段t4，STV提供高电压信号，CK提供高电压信号，CKB提供低电压信号，T3打开，N2的电位为低电压，T2打开，T10打开，NO1的电位为低电压，T12打开，O1输出高电压信号；T7和T8打开，N1的电位为高电压，T13关断；
在第五阶段t5，STV提供高电压信号，CK提供低电压信号，CKB提供高电压信号，T6和T3打开，N2的电位为低电压，N1的电位为高电压，T1打开，T2关断，T8开启，T7关断，T10关断，NO1的电位维持为低电压，T12打开，T13关断，O1输出高电压信号；
在第六阶段t6，STV提供低电压信号，CK提供高电压信号，CKB提供低电压信号，T7打开，N2的电位维持为低电压，T8打开，N1的电位为高电压，T13关断，T10打开，NO1的电位为低电压，T12打开，O1输出高电压信号；
在第七阶段t7，STV提供低电压信号，CK提供低电压信号，CKB提供高电压信号，T6打开，N1的电位为低电压，T13打开，O1输出低电压信号，T9打开，NO1的电位为高电压，T5打开，N2的电位为高电压；
在第八阶段t8，STV提供低电压信号，CK提供高电压信号，CKB提供低电压信号，T6和T3都关断，N2的电位维持为高电压，N1的电位维持为低电压，T9打开，NO1的电位为高电压，T12关断，T13打开，O1输出低电压信号。
图10所示的驱动电路的至少一实施例在工作时，
在O1输出低电压信号时，C1维持的N1的电位会通过T6漏电，可以将T6设计为双栅晶体管，以防止漏电；
T1和T2可以对N2进行稳压，在第一阶段t1至第五阶段t5，N2的一直由T3写入低电压信号，N2的电位维持为低电压，而在第六阶段t6，STV提供的输入信号的电位被置 低，T3关闭，但O1需要持续输出高电压信号，需要T12开启，此时N2由T1和T2写入低电压信号，T10开启，此时，NO1的电位为低电压，T12打开，O1输出高电压信号。
在图10所示的驱动电路的至少一实施例中，C1的第二端与驱动输出端O1电连接，C1的第二端不与时钟信号线电连接，因此，N1的电位不会由于C1的耦合作用而具有台阶，并N2并不与电容电连接，N2的电位也不会由于电容的耦合作用而具有台阶，使得N1的电位和N2的电位相较于相关的驱动电路更加稳定，无耦合波动，又可以降低驱动电路的功耗，同时在第七阶段t7，N1的电位波形和N2的电位波形无台阶，驱动电路输出的驱动信号的波形也无台阶，更利于数据写入。
图12是图10所示的驱动电路的至少一实施例的仿真工作时序图。
图13所示的驱动电路的至少一实施例与图10所示的驱动电路的至少一实施例的区别在于：增设了通断控制电路；
所述通断控制电路包括第十一晶体管T11；
所述第十一晶体管T11的栅极与所述第一电压线VGL电连接，所述第十一晶体管T11的源极与所述第一节点N1电连接，所述第十一晶体管T11的漏极与第二输出节点NO2电连接；
T11为p型晶体管。
图10所示的驱动电路的至少一实施例在工作时，C1保持的电荷在一帧时间内会经过T6漏电，图13所示的驱动电路的至少一实施例增加稳压晶体管(该稳压晶体管为第十一晶体管T11)，可以稳定C2保持的电荷，可以有效改善N1的漏电。
图14是图13所示的驱动电路的至少一实施例的仿真工作时序图。
图15A是图10所示的驱动电路的至少一实施例中的第一节点N1的电位和驱动信号的波形图，图15B是图13所示的驱动电路的至少一实施例中的第一节点N1的电位、第二输出节点NO2的电位和驱动信号的波形图。
如图15B所示，图13所示的驱动电路的至少一实施例在工作时，N1的电位不会因为漏电而升高。
图16所示的驱动电路的至少一实施例与图10所示的驱动电路的至少一实施例的区别在于：去除了T9，C1的第二端改为与第一时钟信号线CKB电连接。
图17是图16所示的驱动电路的至少一实施例的工作时序图。
图10所示的驱动电路的至少一实施例、图13所示的驱动电路的至少一实施例和图16所示的驱动电路的至少一实施例需要搭配LTPO(低温多晶氧化物)产品使用。
图18所示的驱动电路的至少一实施例与图10所示的驱动电路的至少一实施例的区别如下：
T3为p型晶体管，T3的栅极与反相输入端STV2电连接；
所述第一输出节点NO1与相邻下一级反相输入端STV2(n+1)电连接，所述驱动输出端O1与相邻下一级输入端STV(n+1)电连接；
所述反相输入端STV2提供的反相输入信号与STV提供的输入信号反相。
图18所示的驱动电路的至少一实施例在工作时，由STV2(n+1)对NO1的电位进行置位，由STV(n+1)对O1输出的驱动信号进行置位，图18所示的驱动电路的至少一实施例同样无输出下降沿台阶，且适用于LTPS(低温多晶硅)产品和LTPO产品。
图19是图18所示的驱动电路的至少一实施例的工作时序图。
图20所示的驱动电路的至少一实施例与图13所示的驱动电路的至少一实施例的区别在于：
图20所示的驱动电路的至少一实施例还包括储能控制电路；
所述储能控制电路包括第四晶体管T4；
所述第一电容C1的第一端与第二输出节点NO2电连接，所述第一电容的第二端与储能节点NC电连接；
所述第四晶体管T4的栅极与所述第二输出节点NO2电连接，所述第四晶体管T4的源极与所述储能节点NC电连接，所述第四晶体管T4的漏极与所述第一时钟信号线CKB电连接。
在图20所示的驱动电路的至少一实施例中，T4为p型晶体管。
图20所示的驱动电路的至少一实施例增加了二次下拉单元，当NO2的电位为低电压时，在每次CKB提供的第一时钟信号的电位下降为低电平时，NO2的电位均会被下拉，对NO2的下拉能力更强，O1输出的驱动信号更稳定。
图21是图10所示的驱动电路的至少一实施例的布局图。
在图21中，标号STV0的为起始电压线，标号为CKB的为第一时钟信号线，标号为CK的为第二时钟信号线，标号为VGL的为第一低电压信号，标号为VGL2的为第二低电压线，标号为VGH的为高电压线。
图22是图21中的第一半导体层的布局图，图23是图21中的第一栅金属层的布局图，图24是图21中的第二栅金属层的布局图，图25是图21中的第三栅金属层的布局图，图26是图21中的第二半导体层的布局图，图27的图21中的源漏金属层的布局图。
在具体实施时，第一半导体层、第一栅金属层、第二栅金属层、第二半导体层、第三栅金属层和源漏金属层沿着远离衬底基板的方向依次排列。
在图22中，标号为A01的为第一有源图形，标号为A02的为第二有源图形，标号为A6的为T6的有源图形；
A01的上半部分和A02的上半部分作为T12的有源图形，A01的下半部分和A02的下半部分作为T13的有源图形。
可选的，第一半导体层可以由多晶硅制成。
在图23中，标号为G12的为T12的栅极，标号为G13的为T13的栅极，标号为C1a的为C1的第一极板，标号为C2a的为C2的第一极板。
在图24中，标号为C1b的为C1的第二极板，标号为C2b的为C2的第二极板，标号 为G31的为T3的第一栅极。
在图25中，标号为G32的为T3的第二栅极。
在图26中，标号为A3的为T3的有源图形。可选的，所述第二半导体层可以由IGZO(氧化铟镓锌)制成。
在图27中，标号STV0的为起始电压线，标号为CKB的为第一时钟信号线，标号为CK的为第二时钟信号线，标号为VGL的为第一低电压信号，标号为VGL2的为第二低电压线，标号为VGH的为高电压线。
在本发明至少一实施例中，T3可以为双栅晶体管，但不以此为限。
由于Oxide(氧化物)工艺问题，双栅能够使得氧化物晶体管的特性更加稳定，因此将T3设置为双栅晶体管。
在本发明至少一实施例中，所述驱动电路仅包含两个电容，减少采用的电容的个数，可以减小驱动电路占用的空间。
本发明实施例所述的驱动方法，应用于上述的驱动电路，所述驱动方法包括：
第一节点控制电路控制第一节点的电位；
第一控制电路在置位控制信号的控制下，控制第二节点与第一电压线之间连通或断开；
第二控制电路在第一时钟信号和所述第二节点的电位的控制下，控制所述第二节点与第二电压线之间连通或断开；
输出节点控制电路在所述第一时钟信号的控制下，控制所述第二节点与第一输出节点之间连通或断开；
输出电路在所述第一输出节点的电位和第二输出节点的电位的控制下，控制驱动输出端输出驱动信号。
本发明实施例所述的显示装置包括上述的驱动电路。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (24)

  1. 一种驱动电路，包括第一节点控制电路、第一控制电路、第二控制电路、输出节点控制电路、第一储能电路和输出电路；
    所述第一节点控制电路与第一节点电连接，用于控制第一节点的电位；
    所述第一控制电路分别与置位控制端、第一电压线和第二节点电连接，用于在所述置位控制端提供的置位控制信号的控制下，控制所述第二节点与所述第一电压线之间连通或断开；
    所述第二控制电路分别与第一时钟信号线、所述第二节点和第二电压线电连接，用于在所述第一时钟信号线提供的第一时钟信号和所述第二节点的电位的控制下，控制所述第二节点与所述第二电压线之间连通或断开；
    所述输出节点控制电路分别与第一时钟信号线、所述第二节点和第一输出节点电连接，用于在所述第一时钟信号的控制下，控制所述第二节点与所述第一输出节点之间连通或断开；
    所述第一储能电路与第二输出节点电连接，用于储存电能；
    所述输出电路分别与所述第一输出节点、所述第二输出节点和驱动输出端电连接，用于在所述第一输出节点的电位和所述第二输出节点的电位的控制下，控制所述驱动输出端输出驱动信号。
  2. 如权利要求1所述的驱动电路，其中，所述第一储能电路的第一端与所述第二输出节点电连接，所述第一储能电路的第二端与所述驱动输出端电连接。
  3. 如权利要求1所述的驱动电路，其中，所述第一节点与所述第二输出节点为同一节点；或者，
    所述驱动电路还包括通断控制电路；所述第一节点通过所述通断控制电路与所述第二输出节点电连接；所述通断控制电路的控制端与第三电压线电连接，所述通断控制电路用于在所述第三电压线提供的第三电压信号的控制下，控制所述第一节点与所述第二输出节点之间连通或断开。
  4. 如权利要求1所述的驱动电路，其中，还包括储能控制电路；
    所述储能控制电路分别与所述第二输出节点、所述第一时钟信号线和储能节点电连接，用于在所述第二输出节点的电位的控制下，控制所述第一时钟信号线与所述储能节点之间连通或断开；
    所述第一储能电路的第一端与所述第二输出节点电连接，所述第一储能电路的第二端与所述储能节点电连接。
  5. 如权利要求1所述的驱动电路，其中，所述第一储能电路的第一端与所述第二输出节点电连接，所述第一储能电路的第二端与第一时钟信号线电连接。
  6. 如权利要求1至5中任一权利要求所述的驱动电路，其中，还包括第三控制电路；
    所述第三控制电路分别与所述第二输出节点、所述第一输出节点和第四电压线电连接，用于在所述第二输出节点的电位的控制下，控制所述第一输出节点与所述第四电压线之间连通或断开；或者，
    所述第三控制电路分别与所述第一节点、所述第一输出节点和第四电压线电连接，用于在所述第一节点的电位的控制下，控制所述第一输出节点与所述第四电压线之间连通或断开。
  7. 如权利要求1至5中任一权利要求所述的驱动电路，其中，还包括第四控制电路；
    所述第四控制电路分别与所述第一节点、第四电压线和所述第二节点电连接，用于在所述第一节点的电位的控制下，控制所述第二节点与所述第四电压线之间连通或断开。
  8. 如权利要求1至5中任一权利要求所述的驱动电路，其中，还包括第二储能电路；所述第二储能电路与所述第一输出节点电连接，用于储存电能。
  9. 如权利要求1至5中任一权利要求所述的驱动电路，其中，所述第二控制电路包括第一晶体管和第二晶体管；
    所述第一晶体管的栅极与所述第二节点电连接，所述第一晶体管的第一极与所述第二电压线电连接，所述第一晶体管的第二极与所述第二晶体管的第一极电连接；
    所述第二晶体管的栅极与所述第一时钟信号线电连接，所述第二晶体管的第二极与所述第二节点电连接。
  10. 如权利要求1至5中任一权利要求所述的驱动电路，其中，所述第一控制电路包括第三晶体管；所述置位控制端为输入端；
    所述第三晶体管的栅极与所述输入端电连接，所述第三晶体管的第一极与所述第一电压线电连接，所述第三晶体管的第二极与所述第二节点电连接；
    所述第三晶体管为氧化物晶体管。
  11. 如权利要求1至5中任一权利要求所述的驱动电路，其中，所述置位控制端为反相输入端；所述第一控制电路包括第三晶体管；
    所述第三晶体管的栅极与所述反相输入端电连接，所述第三晶体管的第一极与所述第一电压线电连接，所述第三晶体管的第二极与所述第二节点电连接；
    所述第三晶体管为p型晶体管；
    所述反相输入端用于提供反相输入信号，所述反相输入信号与输入端提供的输入信号反相。
  12. 如权利要求11所述的驱动电路，其特在于，所述第一输出节点与相邻下一级反相输入端电连接，所述驱动输出端与相邻下一级输入端电连接。
  13. 如权利要求2所述的驱动电路，其中，所述第一储能电路包括第一电容；
    所述第一电容的第一端与所述第二输出节点电连接，所述第一电容的第二端与所述驱动输出端电连接。
  14. 如权利要求5所述的驱动电路，其中，所述第一储能电路包括第一电容；
    所述第一电容的第一端与所述第二输出节点电连接，所述第一电容的第二端与所述第一时钟信号线电连接。
  15. 如权利要求4所述的驱动电路，其中，所述第一储能电路包括第一电容，所述储能控制电路包括第四晶体管；
    所述第一电容的第一端与所述第二输出节点电连接；所述第一电容的第二端与所述储能节点电连接；
    所述第四晶体管的栅极与所述第二输出节点电连接，所述第四晶体管的第一极与所述储能节点电连接，所述第四晶体管的第二极与所述第一时钟信号线电连接。
  16. 如权利要求7所述的驱动电路，其中，所述第四控制电路包括第五晶体管；
    所述第五晶体管的栅极与所述第一节点电连接，所述第五晶体管的第一极与所述第四电压线电连接，所述第五晶体管的第二极与所述第二节点电连接。
  17. 如权利要求1至5中任一权利要求所述的驱动电路，其中，所述第一节点控制电路还分别与输入端、第二节点、第二时钟信号线、第一时钟信号线和第四电压线电连接，用于在所述第二时钟信号线提供的第二时钟信号的控制下，控制所述第一节点与所述输入端之间连通或断开，在所述第一时钟信号和所述第二节点的电位的控制下，控制所述第一节点与所述第四电压线之间连通或断开。
  18. 如权利要求17所述的驱动电路，其中，所述第一节点控制电路包括第六晶体管、第七晶体管和第八晶体管；
    所述第六晶体管的栅极与所述第二时钟信号线电连接，所述第六晶体管的第一极与所述输入端电连接，所述第六晶体管的第二极与所述第一节点电连接；
    所述第七晶体管的栅极与所述第一时钟信号线电连接，所述第七晶体管的第一极与所述第四电压线电连接，所述第七晶体管的第二极与所述第八晶体管的第一极电连接；
    所述第八晶体管的栅极与所述第二节点电连接，所述第八晶体管的第二极与所述第一节点电连接。
  19. 如权利要求6所述的驱动电路，其中，所述第三控制电路包括第九晶体管；
    所述第九晶体管的栅极与所述第二输出节点电连接，所述第九晶体管的第一极与所述第四电压线电连接，所述第九晶体管的第二极与所述第一输出节点电连接。
  20. 如权利要求1至5中任一权利要求所述的驱动电路，其中，所述输出节点控制电路包括第十晶体管；
    所述第十晶体管的栅极与所述第一时钟信号线电连接，所述第十晶体管的第一极与所述第二节点电连接，所述第十晶体管的第二极与所述第一输出节点电连接。
  21. 如权利要求3所述的驱动电路，其中，所述驱动电路还包括通断控制电路；
    所述通断控制电路包括第十一晶体管；
    所述第十一晶体管的栅极与所述第三电压线电连接，所述第十一晶体管的第一极与所述第一节点电连接，所述第十二晶体管的第一极与所述第二输出节点电连接。
  22. 如权利要求1至5中任一权利要求所述的驱动电路，其中，所述输出电路包括第十二晶体管和第十三晶体管；
    所述第十二晶体管的栅极与所述第一输出节点电连接，所述第十二晶体管的第一极与第五电压线电连接，所述第十二晶体管的第二极与所述驱动输出端电连接；
    所述第十三晶体管的栅极与所述第二输出节点电连接，所述第十三晶体管的第一极与所述驱动输出端电连接，所述第十三晶体管的第二极与第六电压线电连接。
  23. 一种驱动方法，应用于如权利要求1至22中任一权利要求所述的驱动电路，所述驱动方法包括：
    第一节点控制电路控制第一节点的电位；
    第一控制电路在置位控制信号的控制下，控制第二节点与第一电压线之间连通或断开；
    第二控制电路在第一时钟信号和所述第二节点的电位的控制下，控制所述第二节点与第二电压线之间连通或断开；
    输出节点控制电路在所述第一时钟信号的控制下，控制所述第二节点与第一输出节点之间连通或断开；
    输出电路在所述第一输出节点的电位和第二输出节点的电位的控制下，控制驱动输出端输出驱动信号。
  24. 一种显示装置，包括如权利要求1至22中任一权利要求所述的驱动电路。
PCT/CN2024/089966 2023-05-25 2024-04-26 驱动电路、驱动方法和显示装置 Pending WO2024239909A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP24810156.0A EP4657417A1 (en) 2023-05-25 2024-04-26 Drive circuit, driving method, and display apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202310597420.1A CN119028249A (zh) 2023-05-25 2023-05-25 驱动电路、驱动方法和显示装置
CN202310597420.1 2023-05-25

Publications (1)

Publication Number Publication Date
WO2024239909A1 true WO2024239909A1 (zh) 2024-11-28

Family

ID=93531246

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2024/089966 Pending WO2024239909A1 (zh) 2023-05-25 2024-04-26 驱动电路、驱动方法和显示装置

Country Status (3)

Country Link
EP (1) EP4657417A1 (zh)
CN (1) CN119028249A (zh)
WO (1) WO2024239909A1 (zh)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160087951A (ko) * 2015-01-14 2016-07-25 삼성디스플레이 주식회사 게이트 구동 회로
CN111933083A (zh) * 2020-08-21 2020-11-13 京东方科技集团股份有限公司 移位寄存器单元、驱动方法和显示装置
CN113421528A (zh) * 2021-06-22 2021-09-21 京东方科技集团股份有限公司 驱动电路、驱动方法和显示装置
CN113436585A (zh) * 2021-06-23 2021-09-24 京东方科技集团股份有限公司 驱动电路、驱动方法和显示装置
CN114023264A (zh) * 2021-11-29 2022-02-08 京东方科技集团股份有限公司 驱动电路、驱动模组、驱动方法和显示装置
CN114842901A (zh) * 2021-02-01 2022-08-02 京东方科技集团股份有限公司 移位寄存器单元、扫描驱动电路、显示基板和显示装置
CN114842900A (zh) * 2021-02-01 2022-08-02 京东方科技集团股份有限公司 移位寄存器单元、扫描驱动电路、显示基板和显示装置
CN114945969A (zh) * 2020-10-23 2022-08-26 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、驱动电路和显示装置
CN115691386A (zh) * 2022-10-27 2023-02-03 京东方科技集团股份有限公司 显示基板和显示装置

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160087951A (ko) * 2015-01-14 2016-07-25 삼성디스플레이 주식회사 게이트 구동 회로
CN111933083A (zh) * 2020-08-21 2020-11-13 京东方科技集团股份有限公司 移位寄存器单元、驱动方法和显示装置
CN114945969A (zh) * 2020-10-23 2022-08-26 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、驱动电路和显示装置
CN114842901A (zh) * 2021-02-01 2022-08-02 京东方科技集团股份有限公司 移位寄存器单元、扫描驱动电路、显示基板和显示装置
CN114842900A (zh) * 2021-02-01 2022-08-02 京东方科技集团股份有限公司 移位寄存器单元、扫描驱动电路、显示基板和显示装置
CN113421528A (zh) * 2021-06-22 2021-09-21 京东方科技集团股份有限公司 驱动电路、驱动方法和显示装置
CN113436585A (zh) * 2021-06-23 2021-09-24 京东方科技集团股份有限公司 驱动电路、驱动方法和显示装置
CN114023264A (zh) * 2021-11-29 2022-02-08 京东方科技集团股份有限公司 驱动电路、驱动模组、驱动方法和显示装置
CN115691386A (zh) * 2022-10-27 2023-02-03 京东方科技集团股份有限公司 显示基板和显示装置

Also Published As

Publication number Publication date
CN119028249A (zh) 2024-11-26
EP4657417A1 (en) 2025-12-03

Similar Documents

Publication Publication Date Title
JP6874261B2 (ja) Ｉｇｚｏ薄膜トランジスタのｇｏａ回路及び表示装置
CN110689858B (zh) 一种移位寄存器及其驱动方法、栅极驱动电路
CN103226981B (zh) 一种移位寄存器单元及栅极驱动电路
CN102831860B (zh) 移位寄存器及其驱动方法、栅极驱动器及显示装置
KR101944641B1 (ko) Igzo 프로세스 기반인 게이트 전극 구동회로
CN107424554A (zh) 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN111627372B (zh) 一种移位寄存器及其电路、显示面板和电子设备
US11107381B2 (en) Shift register and method for driving the same, gate driving circuit and display device
US11705048B2 (en) Shift register unit, circuit structure, gate drive circuit, drive circuit and display device
WO2022089067A1 (zh) 栅极驱动单元、栅极驱动方法，栅极驱动电路和显示装置
WO2018209937A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
JP2020527818A (ja) シフトレジスタユニット及びその駆動方法、ゲート駆動回路
CN113327537B (zh) 移位寄存器、栅极驱动电路及显示装置
CN104077992B (zh) 一种移位寄存器单元、移位寄存器、显示面板以及显示器
WO2018166215A1 (zh) 移位寄存器单元、阵列基板和显示装置
CN113421518B (zh) 移位寄存器单元、驱动方法、驱动电路和显示装置
WO2024260207A1 (zh) 驱动电路、驱动方法和显示装置
CN106991958A (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
JP2015060100A (ja) 表示装置及び駆動回路
CN104050910B (zh) 移位寄存器单元、栅极驱动电路及显示面板
WO2022262037A1 (zh) 栅极驱动电路及显示面板
WO2024260158A1 (zh) 移位寄存器、显示基板及显示装置
WO2024239909A1 (zh) 驱动电路、驱动方法和显示装置
CN103927996B (zh) 移位寄存器、栅极驱动电路及显示装置
CN110164347B (zh) 移位寄存器单元及其驱动方法、扫描驱动电路、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 24810156

Country of ref document: EP

Kind code of ref document: A1

WWP Wipo information: published in national office

Ref document number: 2024810156

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE