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WO2024212923A1 - 一种Buck型DC-DC变换器的负载电流检测电路及方法 - Google Patents

一种Buck型DC-DC变换器的负载电流检测电路及方法 Download PDF

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Publication number
WO2024212923A1
WO2024212923A1 PCT/CN2024/086573 CN2024086573W WO2024212923A1 WO 2024212923 A1 WO2024212923 A1 WO 2024212923A1 CN 2024086573 W CN2024086573 W CN 2024086573W WO 2024212923 A1 WO2024212923 A1 WO 2024212923A1
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WIPO (PCT)
Prior art keywords
current
tube
switch
voltage
source
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Ceased
Application number
PCT/CN2024/086573
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English (en)
French (fr)
Inventor
李松珂
王永寿
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Vanchip Tianjin Electronic Technology Co Ltd
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Vanchip Tianjin Electronic Technology Co Ltd
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Priority to EP24788026.3A priority Critical patent/EP4697032A1/en
Priority to KR1020257037609A priority patent/KR20260002876A/ko
Publication of WO2024212923A1 publication Critical patent/WO2024212923A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of DC power input into DC power output
    • H02M3/02Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/003Measuring mean values of current or voltage during a given time interval
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to a load current detection circuit of a Buck type DC-DC converter, and also relates to a Buck type DC-DC converter including the load current detection circuit and a corresponding load current detection method, belonging to the technical field of analog integrated circuits.
  • DC-DC converters are increasingly widely used in integrated circuits due to their high efficiency and other excellent performance.
  • Various electronic products such as smart phones and tablet computers have higher and higher requirements for DC-DC converters.
  • it is usually necessary to detect the switch current and obtain the inductor peak current for loop control and circuit protection. It is also necessary to detect the load current for precise control.
  • the detection scheme of the load current of the DC-DC converter is usually as shown in FIG1.
  • a detection resistor Rsen is connected in series on the current path of the switching power supply.
  • a voltage drop Vsen is generated.
  • the voltage drop Vsen at both ends of the detection resistor is processed by the operational amplifier OP to obtain the load current information.
  • This detection scheme consumes power due to the series connection of the detection resistor on the current path, which causes a loss in converter efficiency.
  • the temperature rise caused by the power consumption on the detection resistor will cause the resistance value of the detection resistor to change, affecting the sampling accuracy.
  • the inductor current can be measured without increasing the loss, but the equivalent series resistance of the actual inductor varies due to different models and batches of the inductor, and the detection accuracy will also be affected.
  • DCR equivalent series resistance
  • the inductor current is obtained by using the on-chip load current sampling technology, the current of the freewheeling tube must also be sampled and processed. Therefore, a freewheeling tube current detection circuit must be added on the basis of detecting the switch tube current, and the detection circuit is more complicated.
  • the primary technical problem to be solved by the present invention is to provide a load current detection circuit for a Buck type DC-DC converter.
  • Another technical problem to be solved by the present invention is to provide a load current detection Buck type DC-DC converter for measuring circuit.
  • Another technical problem to be solved by the present invention is to provide a load current detection method for a Buck type DC-DC converter.
  • a load current detection circuit of a Buck type DC-DC converter comprising a switch tube current detection unit, a freewheeling tube current compensation unit and a signal averaging processing unit; wherein,
  • the first input end of the switch tube current detection unit is coupled to the input voltage end, and the second input end is coupled to the connection node of the switch tube and the freewheeling tube, and is used to detect the switch tube current when the switch tube is turned on and the freewheeling tube is turned off, and obtain a detection current proportional to the switch tube current;
  • the first input end of the freewheeling tube current compensation unit is coupled to the output voltage end, and the second input end is coupled to the ground potential end, and the freewheeling tube compensation current proportional to the output voltage is obtained by processing the output voltage;
  • the first input end of the signal averaging processing unit is connected to the output end of the switch tube current detection unit, and the second input end is connected to the output end of the freewheeling tube current compensation unit, and is used to obtain the load current after averaging the detection current and the compensation current.
  • the switch tube current detection unit includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube, as well as a first NMOS tube, a second NMOS tube and a first inverter; wherein the source of the second PMOS tube and the source of the third PMOS tube are connected to the input voltage terminal, and the source of the first PMOS tube is connected to the connection node of the switch tube and the freewheeling tube; the gate of the first PMOS tube is connected to the first control signal terminal on the one hand, and is connected to the gate of the second PMOS tube through the first inverter on the other hand, and the drain of the first PMOS tube is connected to the second PMOS The drains of the fourth PMOS tubes are connected and then connected together with the source of the fourth PMOS tube, the drain of the fourth PMOS tube is connected to the drain of the first NMOS tube and the gate of the sixth PMOS tube, the source of the first NM
  • IP1 is the switch tube current when the switch tube is turned on
  • K1 is the switch tube current detection proportional coefficient
  • the freewheeling tube current compensation unit includes a first operational amplifier, a seventh PMOS tube, an eighth PMOS tube, and a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, and a first resistor, a second resistor and a third resistor; wherein one end of the first resistor is connected to the output voltage end, the other end of the first resistor is connected to the second resistor and the in-phase input end of the first operational amplifier, and the other end of the second resistor is connected to the ground potential end; the output end of the first operational amplifier is connected to the gate of the third NMOS tube, and the inverting input end of the first operational amplifier is connected to the source of the third NMOS tube and the third resistor, The other end of the third resistor is connected to the ground potential end; the drain of the third NMOS tube is connected to the drain of the seventh PMOS tube, the drain of the seventh PMOS tube is short-circuited to the gate and then connected to the gate of the eighth PMOS tube
  • Vout is the output voltage
  • K2 is the proportional coefficient of the compensation current to the output voltage
  • the signal averaging processing unit includes a sampling and holding module, a unit gain buffer module, a low-pass filter module, a voltage-to-current module, a first bias current source and a second bias current source; wherein,
  • the sampling and holding module generates a detection voltage according to the detection current, the compensation current and the first bias current source current; the detection voltage is buffered by the unit gain After the voltage buffering and low-pass filtering of the module and the low-pass filtering module, an average voltage is generated; after the average voltage is converted into a current signal by the voltage-to-current module, the bias current information is removed by the second bias current source current to obtain the load current.
  • the sampling and holding module is composed of a sampling resistor, a sampling capacitor, a first switch and a second switch;
  • the unit gain buffer module is composed of a second operational amplifier;
  • the low-pass filter module is composed of a filter resistor and a filter capacitor;
  • the output end of the switch tube current detection unit and the output end of the first bias current source are commonly connected to the sampling resistor and the first switch, and the other end of the sampling resistor is connected to the ground potential end;
  • the other end of the first switch is connected to the sampling capacitor, the second switch and the in-phase input end of the second operational amplifier, the other end of the sampling capacitor is connected to the ground potential end, and the other end of the second switch is connected to the output end of the freewheeling tube current compensation unit;
  • the inverting input end and the output end of the second operational amplifier are short-circuited and commonly connected to the filter resistor, the other end of the filter resistor is connected to the filter capacitor and the input end of the voltage-to-current module, and the other end of the filter capacitor is connected to the ground potential end;
  • the output end of the voltage-to-current module is connected to the input end of the second bias current source and the output end of the signal averaging processing unit, and the output end of the second bias current source is connected to the ground potential end;
  • the control end of the first switch is connected to the inverted signal end of the first control signal, and the control end of the second switch is connected to the second control signal end.
  • the change ⁇ Vsen1 of the detection voltage output by the sampling and holding module satisfies the following formula:
  • K1 is the switch tube current detection proportional coefficient
  • Rs is the resistance value of the sampling resistor
  • D1 is the duty cycle of the switch tube
  • Ts is the switching period
  • Vin is the input voltage
  • Vout is the output voltage
  • L is the inductance value of the inductor.
  • the change ⁇ Vsen2 of the detection voltage output by the sampling and holding module satisfies the following formula:
  • K2 is the proportional coefficient of the compensation current and the output voltage
  • D2 is the duty cycle of the freewheeling tube
  • Ts is the switching period
  • Cs is the capacitance value of the sampling capacitor
  • Vout is the output voltage.
  • the switch tube current detection proportionality coefficient K1 and the compensation current and output voltage proportionality coefficient K2 satisfy the following formula:
  • Cs is the capacitance value of the sampling capacitor
  • Rs is the resistance value of the sampling resistor
  • L is the inductance value of the inductor
  • K3 is the conversion ratio coefficient of the voltage-to-current module
  • Rs is the resistance value of the sampling resistor
  • a Buck type DC-DC converter comprising the above-mentioned load current detection circuit.
  • a load current detection method for a Buck type DC-DC converter is provided, which is implemented based on the above-mentioned load current detection circuit and includes the following steps:
  • the switch tube current is detected during the conduction period of the switch tube to form a detection current
  • the detection current and the bias current source generate a detection voltage proportional to the inductor current during the rising phase of the inductor current after being processed by sampling and holding;
  • the output voltage is detected during the conduction period of the freewheeling tube to form a compensation current
  • the compensation current, the detection current and the bias current source are sampled and held together to generate a detection voltage proportional to the inductor current in the decreasing phase of the inductor current;
  • the detected voltage is averaged to obtain an average voltage
  • the average voltage is converted into a current signal and then the bias current information is removed to obtain the load current.
  • the load current detection circuit of the Buck type DC-DC converter provided by the present invention Compared with the prior art, the load current detection circuit of the Buck type DC-DC converter provided by the present invention, on the one hand, by adopting the technical solution of on-chip current detection, solves the problem of sensitive parameters of external inductor components without increasing loss, and improves the reliability of the detection circuit; on the other hand, based on the switch tube current detection, Through the compensation processing of the freewheeling tube compensation current, the inductor current detection signal in the entire switching cycle is obtained, and the load current is obtained after averaging processing, so that the load current detection is realized without adding a freewheeling tube detection circuit. Therefore, the load current detection circuit of the Buck type DC-DC converter provided by the present invention has the beneficial effects of ingenious and reasonable structural design, low design cost, high detection accuracy, etc.
  • FIG1 is a diagram of a detection scheme for a load current of a DC-DC converter in the prior art
  • FIG2 is a block diagram of a load current detection circuit of a Buck type DC-DC converter provided by the present invention.
  • FIG. 3 is a schematic diagram of the inductor current of a Buck type DC-DC converter in CCM mode and FCCM mode in an embodiment of the present invention
  • FIG4 is a schematic diagram of the inductor current of a Buck type DC-DC converter in DCM mode according to an embodiment of the present invention
  • FIG5 is a schematic diagram showing a detection principle of a load current of a Buck type DC-DC converter in an embodiment of the present invention
  • FIG6 is a circuit diagram of a switch tube current detection unit in an embodiment of the present invention.
  • FIG7 is a circuit diagram of a freewheeling tube current compensation unit in an embodiment of the present invention.
  • FIG8 is a structural block diagram of a signal averaging processing unit in an embodiment of the present invention.
  • FIG9 is a circuit diagram of a signal averaging processing unit in an embodiment of the present invention.
  • FIG10 is a timing comparison diagram of a Buck type DC-DC converter operating in a CCM mode in an embodiment of the present invention
  • FIG11 is a timing comparison diagram of a Buck type DC-DC converter operating in a DCM mode in an embodiment of the present invention
  • FIG. 12 is a flowchart of the load current detection method of the Buck type DC-DC converter provided by the present invention.
  • the load current detection circuit 100 of the Buck type DC-DC converter provided by the present invention includes a switch tube current detection unit 101 , a freewheeling tube current compensation unit 102 , and a signal averaging processing unit 103 .
  • the first input terminal of the switch tube current detection unit 101 is coupled to the input voltage terminal V IN , and the second input terminal is coupled to the connection node V SW of the switch tube P1 and the freewheeling tube N1, and is used to detect the current flowing through the switch tube P1 when the switch tube P1 is turned on and the freewheeling tube N1 is turned off, and obtain a detection current Isen proportional to the current of the switch tube P1;
  • the first input terminal of the freewheeling tube current compensation unit 102 is coupled to the output voltage terminal V OUT , and the second input terminal is coupled to the ground potential terminal.
  • the freewheeling tube compensation current Icomp proportional to the output voltage is obtained by processing the output voltage.
  • the first input end of the signal averaging processing unit 103 is connected to the output end of the switch tube current detection unit 101, and the second input end is connected to the output end of the freewheeling tube current compensation unit 102, for averaging the detection current Isen and the compensation current Icomp to obtain the load current.
  • the switch tube P1 and the freewheeling tube N1 are turned on alternately during the entire switching cycle T S.
  • the switch tube P1 is turned on, and the inductor current IL increases, and its rising slope is At the D* TS moment, the switch tube P1 is turned off, and the inductor current IL reaches its peak value; during the D* TS to TS period, the freewheeling tube N1 is turned on, and the inductor current IL decreases, with a decreasing slope of Until the current switching cycle T S ends.
  • L is the inductance value
  • Ts is the switching period
  • D is the duty cycle
  • Vout is the output voltage
  • Vin is the input voltage.
  • the Buck type DC-DC converter can be divided into three working conditions, among which the change of the inductor current IL is as follows.
  • the DC-DC converter works in CCM (continuous conduction) mode, and the inductor current IL continuously includes a rising phase and a falling phase within the switching period Ts, and will not drop below zero.
  • the second working condition is a light load condition, where the DC-DC converter works in FCCM (forced continuous conduction) mode.
  • FCCM forced continuous conduction
  • the third working condition is the light load condition, where the DC-DC converter works in DCM (discontinuous conduction) mode, as shown in FIG4 . If the inductor current IL is detected to be zero-crossing, the freewheeling tube N1 is turned off to keep the inductor current IL at zero, that is, within one switching cycle, the inductor current IL includes a rising stage, a falling stage and a zero stage.
  • the total charge output to the load during the on-time of the switch tube P1 and the on-time of the freewheeling tube N1 is divided by the total switching time N*Ts to obtain the average value of the load current.
  • the basic principle of load current detection of the Buck type DC-DC converter of the present invention is as follows: within the switching cycle Ts, the inductor current IL is detected during the conduction period of the switch tube P1 and the peak value of the inductor current during this period is stored, and the peak current is compensated during the conduction period of the freewheeling tube N1, so that the compensated current signal is consistent with the change of the inductor current during the conduction period of the freewheeling tube N1, and a load current signal consistent with the inductor current in the entire switching cycle can be obtained.
  • the switch tube current detection unit 101 includes a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5 and a sixth PMOS tube MP6, as well as a first NMOS tube MN1, a second NMOS tube MN2 and a first inverter INV1.
  • the source of the second PMOS transistor MP2 and the source of the third PMOS transistor MP3 are connected to the input voltage terminal V IN , the source of the first PMOS transistor MP1 is connected to the connection node V SW of the switch transistor P1 and the freewheeling transistor N1; the gate of the first PMOS transistor MP1 is connected to the control signal DP terminal on the one hand, and is connected to the gate of the second PMOS transistor MP2 through the first inverter INV1 on the other hand; the drain of the first PMOS transistor MP1 is connected to the drain of the second PMOS transistor MP2 (node VA ) and is connected to the source of the fourth PMOS transistor MP4; the drain of the fourth PMOS transistor MP4 is connected to the drain of the first NMOS transistor MN1 and the gate of the sixth PMOS transistor MP6; the source of the first NMOS transistor MN1 is connected to the ground potential terminal, and the gate of the first NMOS transistor MN1 is connected to the bias voltage VB1 terminal; the gate of the fourth PMOS transistor MP4
  • the width-to-length ratios of the first PMOS tube MP1, the second PMOS tube MP2, and the third PMOS tube MP3 are the same, and the fourth PMOS tube MP4
  • the width-to-length ratio of the first NMOS tube MN1 and the second NMOS tube MN2 is the same as the fifth PMOS tube MP5, and the width-to-length ratio of the first NMOS tube MN1 and the second NMOS tube MN2 is the same, then the relationship between the detection current Isen at the output end and the switch tube current IP1 satisfies:
  • Ronp is the on-resistance of the switch tube P1
  • R MP3 is the on-resistance of the third PMOS tube MP3
  • I P1 is the current flowing through the switch tube when the switch tube P1 is turned on.
  • K1 is the switch tube current detection proportional coefficient.
  • the freewheeling tube current compensation unit 102 includes a first operational amplifier OA1, a seventh PMOS tube MP7, an eighth PMOS tube MP8, and a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, and a first resistor R1, a second resistor R2, and a third resistor R3.
  • one end of the first resistor R1 is connected to the output voltage terminal V OUT , the other end of the first resistor R1 is connected to the second resistor R2 and the in-phase input terminal of the first operational amplifier OA1, and the other end of the second resistor R2 is connected to the ground potential terminal;
  • the output end of the first operational amplifier OA1 is connected to the gate of the third NMOS tube MN3, the inverting input terminal of the first operational amplifier OA1 is connected to the source of the third NMOS tube MN3 and the third resistor R3, and the other end of the third resistor R3 is connected to the ground potential terminal;
  • the drain of the third NMOS tube MN3 is connected to the drain of the seventh PMOS tube MP7, and the inverting input terminal of the seventh PMOS tube MP7 is connected to the source of the third NMOS tube MN3 and the third resistor R3.
  • the drain and the gate are short-circuited and connected to the gate of the eighth PMOS tube MP8, the source of the seventh PMOS tube MP7 is connected to the source of the eighth PMOS tube MP8, the drain of the eighth PMOS tube MP8 is connected to the drain of the fourth NMOS tube MN4, the drain and the gate of the fourth NMOS tube MN4 are short-circuited and connected to the gate of the fifth NMOS tube MN5, the source of the fourth NMOS tube MN4 and the source of the fifth NMOS tube MN5 are both connected to the ground potential end, and the drain of the fifth NMOS tube MN5 is connected to the output end of the freewheeling tube current compensation unit.
  • the compensation current Icomp at the output end is proportional to the output voltage Vout. Relationship satisfaction:
  • R1, R2, and R3 are resistance values of the first resistor R1, the second resistor R2, and the third resistor R3 respectively.
  • K2 is the proportionality coefficient between the compensation current Icomp and the output voltage Vout.
  • the compensation current Icomp can characterize the rate of change of the inductor current during the conduction phase of the freewheeling tube.
  • the signal averaging processing unit 103 includes a sampling and holding module, a unit gain buffer module, a low-pass filter module, a voltage-to-current module, a first bias current source Ibias1, and a second bias current source Ibias2.
  • the output end of the switch tube current detection unit 101, the output end of the freewheeling tube current compensation unit 102, and the output end of the first bias current source Ibias1 are connected to the input end of the sampling and holding module, the output end of the sampling and holding module is connected to the input end of the unit gain buffer module, the output end of the unit gain buffer module is connected to the input end of the low-pass filter module, the output end of the low-pass filter module is connected to the input end of the voltage-to-current module, the output end of the voltage-to-current module is connected to the input end of the second bias current source Ibias2 and the output end of the signal averaging processing unit, and the output end of the second bias current source Ibias2 is connected to the ground potential end.
  • the sampling and holding module generates an output voltage Vsen according to the input detection current Isen and compensation current Icomp and the first bias current source current Ibias1, and is controlled by the switch tube control signal DP and the freewheeling tube control signal DN ; the voltage Vsen is buffered and low-pass filtered to form an average voltage Vsen_ave in the entire switching cycle; the average voltage Vsen_ave is further converted into current, and then the bias current information is removed by the second bias current source current Ibias2 to obtain the load current Isen_ave, that is, the detection current output by the load current detection circuit 100 of the Buck type DC-DC converter.
  • the low-pass filter module composed of the filter resistor and the filter capacitor has a characteristic time constant that is not less than the switching cycle of the switching power supply.
  • the specific circuit of the signal averaging processing unit 103 is shown in Figure 9, including a sampling and holding module composed of a sampling resistor Rs, a sampling capacitor Cs, a first switch S1 and a second switch S2, a unit gain buffer module composed of a second operational amplifier OA2, and a low-pass filter module composed of a filter resistor R4 and a filter capacitor C1, a voltage-to-current module, a first bias current source Ibias1 and a second bias current source Ibias2.
  • the output end of the switch tube current detection unit 101 and the output end of the first bias current source Ibias1 are connected to the sampling resistor Rs and the first switch S1, and the other end of the sampling resistor Rs is connected to the ground potential end;
  • the other end of the first switch S1 is connected to the sampling capacitor Cs, the second switch S2 and the in-phase input end of the second operational amplifier OA2, the other end of the sampling capacitor Cs is connected to the ground potential end, and the other end of the second switch S2 is connected to the output end of the freewheeling tube current compensation unit 102;
  • the inverting input end and the output end of the second operational amplifier OA2 are short-circuited and connected to the filter resistor R4, the other end of the filter resistor R4 is connected to the input end of the filter capacitor C1 and the voltage-to-current module, and the other end of the filter capacitor C1 is connected to the ground potential end;
  • the output end of the voltage-to-current module is connected to the input end of the second bias current source Ibias
  • the inductor current IL may be negative. Therefore, the input end of the sample and hold module adds a bias current Ibias1 based on the detection current Isen, so that the current signal during the period when the inductor current IL is negative can be accurately stored on the sampling capacitor Cs, so as to ensure that the load current can be accurately detected when the Buck-type DC-DC converter operates in the above three working states.
  • the working process of the signal averaging processing unit 103 is as follows:
  • V sen (K 1 *I P1 +I bias1 )*R s (6)
  • K1 is the switch tube current detection proportional coefficient
  • I P1 is the current flowing through the switch tube when the switch tube P1 is turned on
  • Ibias1 is the output current of the first bias current source Ibias1
  • Rs is the resistance value of the sampling resistor Rs.
  • the change ⁇ I of the inductor current IL during the conduction period of the switch tube P1 is:
  • D1 is the duty cycle of the switch tube P1 control signal DP
  • Ts is the switching period
  • Vout is the output voltage
  • Vin is the input voltage
  • the first switch S1 is turned off and the second switch S2 is closed.
  • the inductor peak current during the on-time of the switch tube P1 is stored on the sampling capacitor Cs.
  • the sampling capacitor Cs discharges to the freewheeling tube current compensation unit through the second switch S2.
  • the compensation current Icom draws the charge on the sampling capacitor Cs, causing the voltage Vsen to drop linearly.
  • the change ⁇ Vsen2 of the detection voltage Vsen at the output of the sampling and holding module can be obtained according to the charge conservation:
  • D2 is the duty cycle of the freewheeling tube N1 control signal DN
  • Ts is the switching period
  • Vout is the output voltage
  • Cs is the capacitance value of the sampling capacitor Cs
  • K2 is the proportional coefficient of the compensation current Icom and the output voltage Vout.
  • both the switch tube P1 and the freewheeling tube N1 are turned off in a switching cycle Ts.
  • both the first switch S1 and the second switch S2 are turned off, and the output voltage Vsen of the sampling and holding module does not change.
  • the compensation current Icom is to be able to properly compensate for the current change during the conduction period of the freewheeling tube N1
  • the current or voltage change during the conduction period of the switch tube P1 should be equal to the current or voltage change during the conduction period of the freewheeling tube N1.
  • formula 11 can be simplified as:
  • IL is the inductor current
  • Ibias1 is the output current of the first bias current source Ibias1
  • Rs is the resistance value of the sampling resistor Rs.
  • the unit gain buffer module formed by the second operational amplifier OA2 buffers the voltage Vsen and then averages it through a low-pass filter module composed of a filter resistor R4 and a filter capacitor C1 to obtain an average voltage Vsen_ave.
  • the average voltage includes current information of the first bias current source Ibias1. Therefore, after converting it into a current signal through a voltage-to-current module and then removing the bias current information through the second bias current source Ibias2, the average load current Isen_ave of the Buck type DC-DC converter can be obtained.
  • the Buck-type DC-DC converter operates in CCM mode.
  • the switch tube current detection unit 101 detects the current IP1 flowing through the switch tube P1 and generates a detection current Isen.
  • the first switch S1 is closed and the second switch S2 is turned off.
  • the signal averaging processing unit 103 converts the current detection Isen into a voltage Vsen through the sampling resistor RS and stores it on the sampling capacitor Cs.
  • the switch tube P1 is turned off and the freewheeling tube N1 is turned on, the first switch S1 is turned off and the second switch S2 is closed.
  • the compensation current Icom generated by the freewheeling tube current compensation unit 102 draws away the charge on the compensation capacitor Cs, causing the voltage Vsen to decrease linearly.
  • the compensation current Icom can properly compensate for the current change during the conduction period of the freewheeling tube N1, the voltage Vsen changes consistently with the inductor current IL during the conduction period of the freewheeling tube N1.
  • the Buck type DC-DC converter operates in the DCM mode.
  • the switch tube P1 and the freewheeling tube N1 are both turned off, the first switch S1 and the second switch S2 are both turned off.
  • the detection voltage Vsen and the inductor current IL change in the same manner during the entire switching cycle. Therefore, the load current Isen_ave can be obtained by averaging the detection voltage Vsen.
  • the switch tube current detection unit 101, the freewheeling tube current compensation unit 102 and the signal averaging processing unit 103 can also be implemented using a variety of other specific circuit structures, which will not be listed one by one in this embodiment.
  • the embodiment of the present invention further provides a Buck type DC-DC converter, which includes the above-mentioned load current detection circuit, and the detection result is used for loop control and circuit protection, etc.
  • a Buck type DC-DC converter which includes the above-mentioned load current detection circuit, and the detection result is used for loop control and circuit protection, etc.
  • the specific structure of the load current detection circuit in the Buck type DC-DC converter will not be described in detail here.
  • the load current detection circuit of the Buck type DC-DC converter provided by the present invention and the method for realizing load current detection is shown in FIG12 , and the working process in each switching cycle Ts is as follows:
  • the load current detection circuit of the Buck type DC-DC converter provided by the present invention adopts the technical solution of on-chip current detection, and solves the problem of sensitive parameters of external inductor components without increasing losses, thereby improving the reliability of the detection circuit; on the other hand, based on the detection of the switch tube current, the compensation processing of the freewheeling tube compensation current is performed to obtain the inductor current detection signal within the entire switching cycle, and the load current is obtained after averaging the signal, thereby realizing the detection of the load current without adding a freewheeling tube detection circuit. Therefore, the load current detection circuit of the Buck type DC-DC converter provided by the present invention has the beneficial effects of ingenious and reasonable structural design, low design cost, and high detection accuracy.
  • first and second are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of “plurality” is two or more, unless otherwise clearly and specifically defined.

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Abstract

一种Buck型DC-DC变换器的负载电流检测电路及方法,该负载电流检测电路包括开关管电流检测单元(101)、续流管电流补偿单元(102)和信号平均化处理单元(103)。其中,开关管电流检测单元(101)的两个输入端分别耦合于输入电压端及开关管和续流管的连接节点,用于在开关管导通、续流管关断时检测开关管电流,并得到检测电流;续流管电流补偿单元(102)的两个输入端分别耦合于输出电压端及地电位端,通过对输出电压进行处理后得到补偿电流;信号平均化处理单元(103)的两个输入端分别与开关管电流检测单元(101)和续流管电流补偿单元(102)的输出端连接,用于对检测电流和补偿电流进行平均化处理后得到负载电流。

Description

一种Buck型DC-DC变换器的负载电流检测电路及方法 技术领域
本发明涉及一种Buck型DC-DC变换器的负载电流检测电路,同时也涉及包括该负载电流检测电路的Buck型DC-DC变换器,还涉及相应的负载电流检测方法,属于模拟集成电路技术领域。
背景技术
随着集成电路技术的不断发展,DC-DC变换器以其效率高等优异性能在集成电路中的应用越来越广泛,各种电子产品如智能手机、平板计算机等,对于DC-DC变换器的要求也越来越高。在实际应用中,通常需要检测开关管电流,得到电感峰值电流用来进行环路控制及电路的保护,还需对负载电流检测以实现精确控制。
在现有技术中,通常DC-DC变换器负载电流的检测方案如图1所示,在开关电源的电流路径上串联检测电阻Rsen,当电流流经检测电阻Rsen时会产生压降Vsen,通过运算放大器OP对检测电阻两端的压降Vsen进行处理以得到负载电流信息。该检测方案由于电流路径上串联检测电阻会消耗功率,引起变换器效率的损失。同时,检测电阻上功耗引起的温升会使得检测电阻的阻值发生变化,影响采样精度。如果减小检测电阻的电阻值,其两端的压降则会比较小,运算放大器需要具备较高的精度才可对此信号进行处理。此外,如果利用电感的等效串联电阻(DCR)可以在不增加损耗的情况下完成对电感电流的测量,但是实际电感的等效串联电阻因电感的型号和批次不同而有所差异,检测精度也会受到影响。在BUCK型DC-DC变换器中,若采用芯片内负载电流采样技术得到电感电流,还需对续流管的电流进行采样并进行处理,因此还需在检测开关管电流的基础上增加续流管电流检测电路,检测电路更为复杂。
发明内容
本发明所要解决的首要技术问题在于提供一种Buck型DC-DC变换器的负载电流检测电路。
本发明所要解决的另一技术问题在于提供一种包括该负载电流检 测电路的Buck型DC-DC变换器。
本发明所要解决的又一技术问题在于提供一种用于Buck型DC-DC变换器的负载电流检测方法。
为了实现上述目的,本发明采用以下的技术方案:
根据本发明实施例的第一方面,提供一种Buck型DC-DC变换器的负载电流检测电路,包括开关管电流检测单元、续流管电流补偿单元和信号平均化处理单元;其中,
所述开关管电流检测单元的第一输入端耦合于输入电压端,第二输入端耦合于开关管和续流管的连接节点,用于在开关管导通、续流管关断时检测开关管电流,并得到与开关管电流成比例的检测电流;
所述续流管电流补偿单元的第一输入端耦合于输出电压端,第二输入端耦合于地电位端,通过对输出电压进行处理后得到与输出电压成比例的续流管补偿电流;
所述信号平均化处理单元的第一输入端与所述开关管电流检测单元的输出端连接,第二输入端与所述续流管电流补偿单元的输出端连接,用于对所述检测电流和所述补偿电流进行平均化处理后得到负载电流。
其中较优地,所述开关管电流检测单元包括第一PMOS管、第二PMOS管、第三PMOS管、第四PMOS管、第五PMOS管和第六PMOS管,以及第一NMOS管、第二NMOS管和第一反相器;其中,第二PMOS管的源极和第三PMOS管的源极与所述输入电压端连接,第一PMOS管的源极与所述开关管和所述续流管的连接节点连接;第一PMOS管的栅极一方面与第一控制信号端连接,另一方面通过第一反相器与第二PMOS管的栅极连接,第一PMOS管的漏极与第二PMOS管的漏极连接后共同与第四PMOS管的源极连接,第四PMOS管的漏极与第一NMOS管的漏极以及第六PMOS管的栅极连接,第一NMOS管的源极与地电位端连接,第一NMOS管的栅极与偏置电压端连接;第四PMOS管的栅极与第五PMOS管的栅极连接,第五PMOS管的栅极与漏极短接连接后与第二NMOS管的漏极连接,第二NMOS管的源极与地电位端连接,第二NMOS管的栅极与偏置电压端连接;第五PMOS管的源极一方面与第三PMOS管的漏极连接,另一方面与第六 PMOS管的源极连接;第三PMOS管的栅极与地电位端连接,第六PMOS管的漏极与所述开关管电流检测单元的输出端连接。
其中较优地,所述开关管电流检测单元输出的所述检测电流Isen满足如下公式:
Isen=K1*IP1
其中,IP1为开关管导通时的开关管电流,K1为开关管电流检测比例系数。
其中较优地,所述续流管电流补偿单元包括第一运算放大器、第七PMOS管、第八PMOS管,以及第三NMOS管、第四NMOS管、第五NMOS管,以及第一电阻、第二电阻和第三电阻;其中,第一电阻的一端与所述输出电压端连接,第一电阻的另一端与第二电阻及第一运算放大器的同相输入端连接,第二电阻的另一端与地电位端连接;第一运算放大器的输出端与第三NMOS管的栅极连接,第一运算放大器的反相输入端与第三NMOS管的源极及第三电阻连接,第三电阻的另一端与地电位端连接;第三NMOS管的漏极与第七PMOS管的漏极连接,第七PMOS管的漏极与栅极短接连接后与第八PMOS管的栅极连接,第七PMOS管的源极与第八PMOS管的源极连接,第八PMOS管的漏极与第四NMOS管的漏极连接,第四NMOS管的漏极与栅极短接连接后与第五NMOS管的栅极连接,第四NMOS管的源极及第五NMOS管的源极均与地电位端连接,第五NMOS管的漏极与所述续流管电流补偿单元的输出端连接。
其中较优地,所述续流管电流补偿单元输出的所述补偿电流Icomp满足如下公式:
Icomp=K2*Vout
其中,Vout为输出电压,K2为补偿电流与输出电压的比例系数。
其中较优地,所述信号平均化处理单元包括采样保持模块、单位增益缓冲模块、低通滤波模块、电压转电流模块、第一偏置电流源和第二偏置电流源;其中,
所述采样保持模块根据所述检测电流和所述补偿电流以及所述第一偏置电流源电流,产生检测电压;该检测电压经过所述单位增益缓冲 模块、所述低通滤波模块的电压缓冲和低通滤波后,产生平均电压;该平均电压通过所述电压转电流模块转变为电流信号后,再通过所述第二偏置电流源电流除去偏置电流信息,得到负载电流。
其中较优地,所述信号平均化处理单元中,所述采样保持模块由采样电阻、采样电容、第一开关和第二开关构成;所述单位增益缓冲模块由第二运算放大器构成;所述低通滤波模块由滤波电阻、滤波电容构成;其中,
所述开关管电流检测单元的输出端、及所述第一偏置电流源的输出端共同与采样电阻及第一开关连接,采样电阻的另一端与地电位端连接;第一开关的另一端与采样电容、第二开关及第二运算放大器的同相输入端连接,采样电容的另一端与地电位端连接,第二开关的另一端与所述续流管电流补偿单元的输出端连接;第二运算放大器的反相输入端与输出端短接连接后共同与滤波电阻连接,滤波电阻的另一端与滤波电容及所述电压转电流模块的输入端连接,滤波电容的另一端与地电位端连接;所述电压转电流模块的输出端与所述第二偏置电流源的输入端及所述信号平均化处理单元的输出端连接,所述第二偏置电流源的输出端与地电位端连接;
所述第一开关的控制端与所述第一控制信号的反信号端连接,所述第二开关的控制端与第二控制信号端连接。
其中较优地,在所述Buck型DC-DC变换器开关管导通、续流管关断时,所述采样保持模块输出的检测电压的变化量ΔVsen1满足如下公式:
其中,K1为开关管电流检测比例系数,Rs为采样电阻的电阻值,D1为开关管的占空比,Ts为开关周期,Vin为输入电压,Vout为输出电压,L为电感的电感值。
其中较优地,在所述Buck型DC-DC变换器开关管关断、续流管导通时,所述采样保持模块输出的检测电压的变化量ΔVsen2满足如下公式:
其中,K2为补偿电流与输出电压的比例系数,D2为续流管的占空比,Ts为开关周期,Cs为采样电容的电容值,Vout为输出电压。
其中较优地,所述开关管电流检测比例系数K1和所述补偿电流与输出电压的比例系数K2满足如下公式:
其中,Cs为采样电容的电容值,Rs为采样电阻的电阻值,L为电感的电感值。
其中较优地,所述信号平均化处理单元中,所述第一偏置电流源的输出电流Ibias1与第二偏置电流源的输出电流Ibias2满足如下公式:
Ibias1*Rs*K3=Ibias2
其中,K3为电压转电流模块的转换比例系数,Rs为采样电阻的电阻值。
根据本发明实施例的第二方面,提供一种Buck型DC-DC变换器,其中包括上述负载电流检测电路。
根据本发明实施例的第三方面,提供一种用于Buck型DC-DC变换器的负载电流检测方法,基于上述负载电流检测电路实现,包括如下步骤:
所述开关管导通期间检测开关管电流,形成检测电流;
所述检测电流和偏置电流源通过采样保持处理后,产生电感电流上升阶段与电感电流成比例的检测电压;
所述续流管导通期间检测输出电压,形成补偿电流;
所述补偿电流与所述检测电流和所述偏置电流源共同进行采样保持处理后,产生电感电流下降阶段与电感电流成比例的检测电压;
将所述检测电压经过平均化处理后得到平均电压;
将所述平均电压转化为电流信号再去除偏置电流信息后,得到负载电流。
与现有技术相比较,本发明所提供的Buck型DC-DC变换器的负载电流检测电路,一方面通过采用片内电流检测的技术方案,在未增加损耗的情况下,同时也解决了外部电感元器件参数敏感的问题,提高了检测电路的可靠性;另一方面,在开关管电流检测的基础上,通 过续流管补偿电流的补偿处理,得到整个开关周期内的电感电流检测信号,并对其进行平均化处理后得到负载电流,在无需增加续流管检测电路的情况下实现了对负载电流的检测。因此,本发明所提供的Buck型DC-DC变换器的负载电流检测电路具有结构设计巧妙合理、设计成本较低、检测精度高等有益效果。
附图说明
图1为现有技术中,DC-DC变换器负载电流的检测方案图;
图2为本发明提供的Buck型DC-DC变换器的负载电流检测电路的结构框图;
图3为本发明实施例中,CCM模式和FCCM模式下Buck型DC-DC变换器的电感电流示意图;
图4为本发明实施例中,DCM模式下Buck型DC-DC变换器的电感电流示意图;
图5为本发明实施例中,Buck型DC-DC变换器负载电流的检测原理图;
图6为本发明实施例中,开关管电流检测单元的电路原理图;
图7为本发明实施例中,续流管电流补偿单元的电路原理图;
图8为本发明实施例中,信号平均化处理单元的结构框图;
图9为本发明实施例中,信号平均化处理单元的电路原理图;
图10为本发明实施例中,Buck型DC-DC变换器工作于CCM模式的时序对照图;
图11为本发明实施例中,Buck型DC-DC变换器工作于DCM模式的时序对照图;
图12为本发明提供的Buck型DC-DC变换器的负载电流检测方法的工作流程图。
具体实施方式
下面结合附图和具体实施例对本发明的技术内容进行详细具体的说明。
如图2所示,本发明提供的Buck型DC-DC变换器的负载电流检测电路100,包括开关管电流检测单元101、续流管电流补偿单元102、信号平均化处理单元103。
开关管电流检测单元101的第一输入端耦合于输入电压端VIN,第二输入端耦合于开关管P1和续流管N1的连接节点VSW,用于在开关管P1导通、续流管N1关断时检测流过开关管P1的电流,并得到与开关管P1电流成比例的检测电流Isen;
续流管电流补偿单元102的第一输入端耦合于输出电压端VOUT,第二输入端耦合于地电位端,通过对输出电压进行处理后得到与输出电压成比例的续流管补偿电流Icomp;
信号平均化处理单元103的第一输入端与开关管电流检测单元101的输出端连接,第二输入端与续流管电流补偿单元102的输出端连接,用于对检测电流Isen和补偿电流Icomp进行平均化处理后得到负载电流。
在Buck型DC-DC变换器中,如图3所示,整个开关周期TS内开关管P1和续流管N1交替导通。在0~D*TS时段内,开关管P1导通,电感电流IL上升,其上升斜率为在D*TS时刻,开关管P1关闭,电感电流IL到达峰值;在D*TS~TS时段内,续流管N1导通,电感电流IL下降,下降斜率为直到当前开关周期TS结束。其中,L为电感值,Ts为开关周期,D为占空比,Vout为输出电压,Vin为输入电压。
依据负载电流的大小及开关管的控制方案,Buck型DC-DC变换器可以分为三种工作状况,其中电感电流IL的变化情况如下。
第一种工作状况为负载电流较大时,DC-DC变换器工作于CCM(连续导通)模式,在开关周期Ts内电感电流IL连续包含上升阶段和下降阶段,且不会下降到低于零。
第二种工作状况为轻负载情况下,DC-DC变换器工作于FCCM(强制连续导通)模式,在开关周期Ts内电感电流IL连续包含上升阶段和下降阶段,但允许下降为负值。
第三种工作状况为轻负载情况下,DC-DC变换器工作于DCM(断续导通)模式,如图4所示,若检测到电感电流IL过零则关闭续流管N1使得电感电流IL保持为零,即在一个开关周期内电感电流IL包含上升阶段、下降阶段和等于零阶段。
以上三种工作状况下,在N个开关周期Ts内,将开关管P1导通时间内和续流管N1导通时间内输出到负载的总电荷量,除以总开关时间N*Ts即可得到负载电流的平均值。
如图5所示,本发明Buck型DC-DC变换器负载电流检测的基本原理如下,在开关周期Ts内,开关管P1导通期间内检测电感电流IL并将此期间的电感电流峰值储存起来,在续流管N1导通期间对该峰值电流进行补偿处理,使得补偿后的电流信号与续流管N1导通期间电感电流变化一致,即可得到在整个开关周期内与电感电流一致的负载电流信号。
在本发明的一个实施例中,如图6所示,开关管电流检测单元101包括第一PMOS管MP1、第二PMOS管MP2、第三PMOS管MP3、第四PMOS管MP4、第五PMOS管MP5和第六PMOS管MP6,以及第一NMOS管MN1、第二NMOS管MN2和第一反相器INV1。其中,第二PMOS管MP2的源极和第三PMOS管MP3的源极与输入电压端VIN连接,第一PMOS管MP1的源极与开关管P1和续流管N1的连接节点VSW连接;第一PMOS管MP1的栅极一方面与控制信号DP端连接,另一方面通过第一反相器INV1与第二PMOS管MP2的栅极连接,第一PMOS管MP1的漏极与第二PMOS管MP2的漏极连接后(节点VA)共同与第四PMOS管MP4的源极连接,第四PMOS管MP4的漏极与第一NMOS管MN1的漏极以及第六PMOS管MP6的栅极连接,第一NMOS管MN1的源极与地电位端连接,第一NMOS管MN1的栅极与偏置电压VB1端连接;第四PMOS管MP4的栅极(节点VC)与第五PMOS管MP5的栅极连接,第五PMOS管MP5的栅极与漏极短接连接后与第二NMOS管MN2的漏极连接,第二NMOS管MN2的源极与地电位端连接,第二NMOS管MN2的栅极与偏置电压VB1端连接;第五PMOS管MP5的源极(节点VB)一方面与第三PMOS管MP3的漏极连接,另一方面与第六PMOS管MP6的源极连接;第三PMOS管MP3的栅极与地电位端连接,第六PMOS管MP6的漏极与开关管电流检测单元的输出端连接。
在开关管电流检测单元101中,假定第一PMOS管MP1、第二PMOS管MP2、第三PMOS管MP3的宽长比相同,第四PMOS管MP4 和第五PMOS管MP5宽长比相同,第一NMOS管MN1和第二NMOS管MN2宽长比相同,则输出端的检测电流Isen与开关管电流IP1的关系满足:
其中,Ronp为开关管P1的导通电阻,RMP3为第三PMOS管MP3的导通电阻,IP1为开关管P1导通时流经开关管的电流。
公式1中,取开关管电流检测比例K1=Ronp/RMP3,则检测电流Isen为:
Isen=K1*IP1                   (2)
其中,K1为开关管电流检测比例系数。
在本发明的一个实施例中,如图7所示,续流管电流补偿单元102包括第一运算放大器OA1、第七PMOS管MP7、第八PMOS管MP8,以及第三NMOS管MN3、第四NMOS管MN4、第五NMOS管MN5,以及第一电阻R1、第二电阻R2和第三电阻R3。其中,第一电阻R1的一端与输出电压端VOUT连接,第一电阻R1的另一端与第二电阻R2及第一运算放大器OA1的同相输入端连接,第二电阻R2的另一端与地电位端连接;第一运算放大器OA1的输出端与第三NMOS管MN3的栅极连接,第一运算放大器OA1的反相输入端与第三NMOS管MN3的源极及第三电阻R3连接,第三电阻R3的另一端与地电位端连接;第三NMOS管MN3的漏极与第七PMOS管MP7的漏极连接,第七PMOS管MP7的漏极与栅极短接连接后与第八PMOS管MP8的栅极连接,第七PMOS管MP7的源极与第八PMOS管MP8的源极连接,第八PMOS管MP8的漏极与第四NMOS管MN4的漏极连接,第四NMOS管MN4的漏极与栅极短接连接后与第五NMOS管MN5的栅极连接,第四NMOS管MN4的源极及第五NMOS管MN5的源极均与地电位端连接,第五NMOS管MN5的漏极与续流管电流补偿单元的输出端连接。
在续流管电流补偿单元102中,假定第七PMOS管MP7和第八PMOS管MP8的宽长比相同,第四NMOS管MN4和第五NMOS管MN5的宽长比相同,则输出端的补偿电流Icomp与输出电压Vout的 关系满足:
其中,R1、R2、R3分别为第一电阻R1、第二电阻R2和第三电阻R3的电阻值。
公式3中,取补偿电流Icomp与输出电压Vout的比例则补偿电流Icomp为
Icomp=K2*Vout                 (4)
其中,K2为补偿电流Icomp与输出电压Vout的比例系数。
由Buck型DC-DC变换器工作原理可知,在续流管导通阶段,电感电流下降斜率为Vout/L,其下降斜率与输出电压成正比关系。因此,补偿电流Icomp即可表征电感电流在续流管导通期间的变化速率。
在本发明的一个实施例中,如图8所示,信号平均化处理单元103包括采样保持模块、单位增益缓冲模块、低通滤波模块、电压转电流模块、第一偏置电流源Ibias1和第二偏置电流源Ibias2。其中,开关管电流检测单元101的输出端、续流管电流补偿单元102的输出端及第一偏置电流源Ibias1的输出端与采样保持模块的输入端连接,采样保持模块的输出端与单位增益缓冲模块的输入端连接,单位增益缓冲模块的输出端与低通滤波模块的输入端连接,低通滤波模块的输出端与电压转电流模块的输入端连接,电压转电流模块的输出端与第二偏置电流源Ibias2的输入端及信号平均化处理单元的输出端连接,第二偏置电流源Ibias2的输出端与地电位端连接。
在信号平均化处理单元103中,采样保持模块根据输入的检测电流Isen和补偿电流Icomp以及第一偏置电流源电流Ibias1,并经过开关管控制信号DP和续流管控制信号DN的控制,产生输出电压Vsen;该电压Vsen经过电压缓冲和低通滤波后,形成整个开关周期内的平均电压Vsen_ave;进一步将平均电压Vsen_ave转变为电流后,再通过第二偏置电流源电流Ibias2除去偏置电流信息,得到负载电流Isen_ave,即Buck型DC-DC变换器的负载电流检测电路100输出的检测电流。其中,由滤波电阻和滤波电容构成的低通滤波模块,其特征时间常数不小于开关电源的开关周期。
在本发明的一个实施例中,信号平均化处理单元103的具体电路如图9所示,包括由采样电阻Rs、采样电容Cs、第一开关S1和第二开关S2组成的采样保持模块,以及由第二运算放大器OA2构成的单位增益缓冲模块,以及由滤波电阻R4、滤波电容C1组成的低通滤波模块,电压转电流模块、第一偏置电流源Ibias1和第二偏置电流源Ibias2。其中,开关管电流检测单元101的输出端和第一偏置电流源Ibias1的输出端共同与采样电阻Rs及第一开关S1连接,采样电阻Rs的另一端与地电位端连接;第一开关S1的另一端与采样电容Cs、第二开关S2及第二运算放大器OA2的同相输入端连接,采样电容Cs的另一端与地电位端连接,第二开关S2的另一端与续流管电流补偿单元102的输出端连接;第二运算放大器OA2的反相输入端与输出端短接连接后共同与滤波电阻R4连接,滤波电阻R4的另一端与滤波电容C1及电压转电流模块的输入端连接,滤波电容C1的另一端与地电位端连接;电压转电流模块的输出端与第二偏置电流源Ibias2的输入端及信号平均化处理单元的输出端连接,第二偏置电流源Ibias2的输出端与地电位端连接。第一开关S1的控制端与控制信号DP的反信号端连接,第二开关S2的控制端与控制信号DN端连接。
当Buck型DC-DC变换器工作于FCCM(强制连续导通)模式时,电感电流IL可能会出现负值的情况,因此,采样保持模块的输入端在检测电流Isen的基础上增加偏置电流Ibias1,使得在电感电流IL为负值期间的电流信号能够准确储存在采样电容Cs上,以保证Buck型DC-DC变换器工作于前述三种工作状态时的负载电流均能准确检测。
信号平均化处理单元103的工作过程如下:
Buck型DC-DC变换器在开关管P1导通、续流管N1关断时,开关管控制信号DP=0、续流管控制信号DN=0,因此,第一开关S1闭合,第二开关S2关断。开关管P1的检测电流Isen和第一偏置电流Ibias1流经采样电阻Rs和采样电容Cs后,在采样保持模块输出端产生检测电压Vsen,该电压Vsen满足如下公式:
当Cs<<Ts/Rs时,上式可简化为:
Vsen=(K1*IP1+Ibias1)*Rs             (6)
其中,K1为开关管电流检测比例系数,IP1为开关管P1导通时流经开关管的电流,Ibias1为第一偏置电流源Ibias1的输出电流,Rs为采样电阻Rs的电阻值。
电感电流IL在开关管P1导通期间内变化量ΔI为:
由公式6和公式7可知,在开关管P1导通期间内,采样保持模块输出端检测电压Vsen的变化量ΔVsen1为:
其中,D1为开关管P1控制信号DP的占空比。Ts为开关周期,Vout为输出电压,Vin为输入电压。
在D1*Ts时,开关管P1关断、续流管N1导通,开关管控制信号DP=1、续流管控制信号DN=1,因此,第一开关S1关断,第二开关S2闭合。此时,开关管P1导通期间的电感峰值电流被储存在采样电容Cs上,在此后续流管N1导通期间内,采样电容Cs通过第二开关S2向续流管电流补偿单元放电,补偿电流Icom抽走采样电容Cs上的电荷使得电压Vsen线性下降。在续流管N1导通期间,依据电荷守恒可得采样保持模块输出端检测电压Vsen的变化量ΔVsen2为:
其中,D2为续流管N1控制信号DN的占空比,Ts为开关周期,Vout为输出电压,Cs为采样电容Cs的电容值,K2为补偿电流Icom与输出电压Vout的比例系数。
若Buck型DC-DC变换器工作于DCM模式时,则一个开关周期Ts内存在开关管P1与续流管N1均关断的一个阶段,此时,第一开关S1和第二开关S2均关断,采样保持模块输出端电压Vsen不发生变化。
在Buck型DC-DC变换器电路结构中,依据电感的伏秒平衡原理,可得:
若要实现补偿电流Icom能够恰当的补偿续流管N1导通期间的电流变化量,则在开关管P1导通期间的电流或电压变化量与续流管N1导通期间的电流或电压变化量应相等,根据公式8和公式9可知:
根据公式10,公式11可简化为:
由公式12可知,补偿电流与输出电压的比例系数K2与开关管电流检测比例系数K1以及采样电阻Rs、采样电容Cs应满足公式12所表达的关系。
在采用补偿电流Icom对采样保持模块输出端检测电压Vsen进行补偿后,检测电压Vsen在续流管N1导通期间与电感电流的变化趋势一致,其满足如下公式:
Vsen=(K1*IL+Ibias1)*Rs            (13)
其中,IL为电感电流,Ibias1为第一偏置电流源Ibias1的输出电流,Rs为采样电阻Rs的电阻值。
第二运算放大器OA2构成的单位增益缓冲模块,将电压Vsen缓冲输出后,再通过由滤波电阻R4、滤波电容C1组成的低通滤波模块进行平均化处理,得到平均电压Vsen_ave,该平均电压中包含第一偏置电流源Ibias1的电流信息,因此,通过电压转电流模块将其转化为电流信号后再通过第二偏置电流源Ibias2去除该偏置电流信息,即可得到Buck型DC-DC变换器的平均负载电流Isen_ave。
其中,第二偏置电流源Ibias2的输出电流Ibias2与第一偏置电流源Ibias1的输出电流Ibias1满足如下公式:
Ibias1*Rs*K3=Ibias2             (14)
其中,K3为电压转电流模块的比例系数,K3=输出电流/输入电压。
本发明提供的Buck型DC-DC变换器的负载电流检测电路中,当 Buck型DC-DC变换器工作于CCM模式或DCM模式时,其开关管控制信号DP、续流管控制信号DN、电感电流IL和电压Vsen的时序对照分别如图10和图11所示。
在图10中,Buck型DC-DC变换器工作于CCM模式,当开关管P1导通、续流管N1关断时,开关管电流检测单元101检测流经开关管P1的电流IP1并产生检测电流Isen,此时,第一开关S1闭合、第二开关S2关断,信号平均化处理单元103通过采样电阻RS将电流检测Isen转化为电压Vsen并储存在采样电容Cs上;当开关管P1关断、续流管N1导通时,第一开关S1关断、第二开关S2闭合,续流管电流补偿单元102产生的补偿电流Icom抽走补偿电容Cs上的电荷使得电压Vsen线性下降;当补偿电流Icom能够恰当的补偿续流管N1导通期间的电流变化量时,使得电压Vsen在续流管N1导通期间内与电感电流IL变化一致。
在图11中,Buck型DC-DC变换器工作于DCM模式,当开关管P1与续流管N1均关断时,第一开关S1和第二开关S2均关断。在整个开关周期内检测电压Vsen与电感电流IL变化均一致。因此,对检测电压Vsen进行平均化处理后即可得到负载电流Isen_ave。
在本发明提供的Buck型DC-DC变换器的负载电流检测电路中,开关管电流检测单元101、续流管电流补偿单元102和信号平均化处理单元103还可以采用其他多种具体电路结构实现,本实施例在此不再进行一一列举了。
本发明实施例还提供一种Buck型DC-DC变换器,其中包括上述负载电流检测电路,检测结果用于进行环路控制及电路保护等。对于该Buck型DC-DC变换器中的负载电流检测电路的具体结构,在此就不再赘述了。
本发明所提供的Buck型DC-DC变换器的负载电流检测电路,其实现负载电流检测的方法如图12所示,在每个开关周期Ts内其工作流程如下:
S1:开关管P1导通期间检测开关管电流IP1,形成检测电流Isen;
S2:检测电流Isen和偏置电流源Ibias通过采样保持处理后,产生电感电流上升阶段与电感电流成比例的检测电压Vsen;
S3:续流管N1导通期间检测输出电压Vout,形成补偿电流Icomp;
S4:补偿电流Icomp与检测电流Isen和偏置电流源Ibias共同进行采样保持处理后,产生电感电流下降阶段与电感电流成比例的检测电压Vsen;
S5:将检测电压Vsen经过平均化处理后得到平均电压Vsen_ave;
S6:将平均电压Vsen_ave转化为电流信号再去除偏置电流信息后,得到负载电流Isen_ave。
上述负载电流检测方法中,通过各单元电路元件参数的设置,使得检测电压Vsen的变化与电感电流IL的变化保持一致。
综上所述,与现有技术相比较,本发明所提供的Buck型DC-DC变换器的负载电流检测电路,一方面通过采用片内电流检测的技术方案,在未增加损耗的情况下,同时也解决了外部电感元器件参数敏感的问题,提高了检测电路的可靠性;另一方面,在开关管电流检测的基础上,通过续流管补偿电流的补偿处理,得到整个开关周期内的电感电流检测信号,并对其进行平均化处理后得到负载电流,在无需增加续流管检测电路的情况下实现了对负载电流的检测。因此,本发明所提供的Buck型DC-DC变换器的负载电流检测电路具有结构设计巧妙合理、设计成本较低、检测精度高等有益效果。
需要说明的是,上述多个实施例只是举例,各个实施例的技术方案之间可以进行组合,均在本发明的保护范围内。
此外,术语“第一”、“第二”仅用于描述目的,而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此,限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本发明的描述中,“多个”的含义是两个或两个以上,除非另有明确具体的限定。
上面对本发明所提供的Buck型DC-DC变换器的负载电流检测电路及方法进行了详细的说明。对本领域的一般技术人员而言,在不背离本发明实质内容的前提下对它所做的任何显而易见的改动,都将构成对本发明专利权的侵犯,将承担相应的法律责任。

Claims (13)

  1. 一种Buck型DC-DC变换器的负载电流检测电路,其特征在于包括开关管电流检测单元、续流管电流补偿单元和信号平均化处理单元;其中,
    所述开关管电流检测单元的第一输入端耦合于输入电压端,第二输入端耦合于开关管和续流管的连接节点,用于在开关管导通、续流管关断时检测开关管电流,并得到与开关管电流成比例的检测电流;
    所述续流管电流补偿单元的第一输入端耦合于输出电压端,第二输入端耦合于地电位端,通过对输出电压进行处理后得到与输出电压成比例的续流管补偿电流;
    所述信号平均化处理单元的第一输入端与所述开关管电流检测单元的输出端连接,第二输入端与所述续流管电流补偿单元的输出端连接,用于对所述检测电流和所述补偿电流进行平均化处理后得到负载电流。
  2. 如权利要求1所述的Buck型DC-DC变换器的负载电流检测电路,其特征在于:
    所述开关管电流检测单元包括第一PMOS管、第二PMOS管、第三PMOS管、第四PMOS管、第五PMOS管和第六PMOS管,以及第一NMOS管、第二NMOS管和第一反相器;其中,第二PMOS管的源极和第三PMOS管的源极与所述输入电压端连接,第一PMOS管的源极与所述开关管和所述续流管的连接节点连接;第一PMOS管的栅极一方面与第一控制信号端连接,另一方面通过第一反相器与第二PMOS管的栅极连接,第一PMOS管的漏极与第二PMOS管的漏极连接后共同与第四PMOS管的源极连接,第四PMOS管的漏极与第一NMOS管的漏极以及第六PMOS管的栅极连接,第一NMOS管的源极与地电位端连接,第一NMOS管的栅极与偏置电压端连接;第四PMOS管的栅极与第五PMOS管的栅极连接,第五PMOS管的栅极与漏极短接连接后与第二NMOS管的漏极连接,第二NMOS管的源极与地电位端连接,第二NMOS管的栅极与偏置电压端连接;第五PMOS管的源极一方面与第三PMOS管的漏极连接,另一方面与第六PMOS管的源 极连接;第三PMOS管的栅极与地电位端连接,第六PMOS管的漏极与所述开关管电流检测单元的输出端连接。
  3. 如权利要求2所述的Buck型DC-DC变换器的负载电流检测电路,其特征在于:
    所述开关管电流检测单元输出的所述检测电流Isen满足如下公式:
    Isen=K1*IP1
    其中,IP1为开关管导通时的开关管电流,K1为开关管电流检测比例系数。
  4. 如权利要求1所述的Buck型DC-DC变换器的负载电流检测电路,其特征在于:
    所述续流管电流补偿单元包括第一运算放大器、第七PMOS管、第八PMOS管,以及第三NMOS管、第四NMOS管、第五NMOS管,以及第一电阻、第二电阻和第三电阻;其中,第一电阻的一端与所述输出电压端连接,第一电阻的另一端与第二电阻及第一运算放大器的同相输入端连接,第二电阻的另一端与地电位端连接;第一运算放大器的输出端与第三NMOS管的栅极连接,第一运算放大器的反相输入端与第三NMOS管的源极及第三电阻连接,第三电阻的另一端与地电位端连接;第三NMOS管的漏极与第七PMOS管的漏极连接,第七PMOS管的漏极与栅极短接连接后与第八PMOS管的栅极连接,第七PMOS管的源极与第八PMOS管的源极连接,第八PMOS管的漏极与第四NMOS管的漏极连接,第四NMOS管的漏极与栅极短接连接后与第五NMOS管的栅极连接,第四NMOS管的源极及第五NMOS管的源极均与地电位端连接,第五NMOS管的漏极与所述续流管电流补偿单元的输出端连接。
  5. 如权利要求4所述的Buck型DC-DC变换器的负载电流检测电路,其特征在于:
    所述续流管电流补偿单元输出的所述补偿电流Icomp满足如下公式:
    Icomp=K2*Vout
    其中,Vout为输出电压,K2为补偿电流与输出电压的比例系数。
  6. 如权利要求1所述的Buck型DC-DC变换器的负载电流检测电路,其特征在于:
    所述信号平均化处理单元包括采样保持模块、单位增益缓冲模块、低通滤波模块、电压转电流模块、第一偏置电流源和第二偏置电流源;其中,
    所述采样保持模块根据所述检测电流和所述补偿电流以及所述第一偏置电流源电流,产生检测电压;该检测电压经过所述单位增益缓冲模块、所述低通滤波模块的电压缓冲和低通滤波后,产生平均电压;该平均电压通过所述电压转电流模块转变为电流信号后,再通过所述第二偏置电流源电流除去偏置电流信息,得到负载电流。
  7. 如权利要求6所述的Buck型DC-DC变换器的负载电流检测电路,其特征在于:
    所述信号平均化处理单元中,所述采样保持模块由采样电阻、采样电容、第一开关和第二开关构成;所述单位增益缓冲模块由第二运算放大器构成;所述低通滤波模块由滤波电阻、滤波电容构成;其中,
    所述开关管电流检测单元的输出端、及所述第一偏置电流源的输出端共同与采样电阻及第一开关连接,采样电阻的另一端与地电位端连接;第一开关的另一端与采样电容、第二开关及第二运算放大器的同相输入端连接,采样电容的另一端与地电位端连接,第二开关的另一端与所述续流管电流补偿单元的输出端连接;第二运算放大器的反相输入端与输出端短接连接后共同与滤波电阻连接,滤波电阻的另一端与滤波电容及所述电压转电流模块的输入端连接,滤波电容的另一端与地电位端连接;所述电压转电流模块的输出端与所述第二偏置电流源的输入端及所述信号平均化处理单元的输出端连接,所述第二偏置电流源的输出端与地电位端连接;
    所述第一开关的控制端与所述第一控制信号的反信号端连接,所述第二开关的控制端与第二控制信号端连接。
  8. 如权利要求6或7所述的Buck型DC-DC变换器的负载电流检测电路,其特征在于:
    在所述Buck型DC-DC变换器开关管导通、续流管关断时,所述采样保持模块输出的检测电压的变化量ΔVsen1满足如下公式:
    其中,K1为开关管电流检测比例系数,Rs为采样电阻的电阻值,D1为开关管的占空比,Ts为开关周期,Vin为输入电压,Vout为输出电压,L为电感的电感值。
  9. 如权利要求6或7所述的Buck型DC-DC变换器的负载电流检测电路,其特征在于:
    在所述Buck型DC-DC变换器开关管关断、续流管导通时,所述采样保持模块输出的检测电压的变化量ΔVsen2满足如下公式:
    其中,K2为补偿电流与输出电压的比例系数,D2为续流管的占空比,Ts为开关周期,Cs为采样电容的电容值,Vout为输出电压。
  10. 如权利要求2~9中任意一项所述的Buck型DC-DC变换器负载的电流检测电路,其特征在于:
    所述开关管电流检测比例系数K1和所述补偿电流与输出电压的比例系数K2满足如下公式:
    其中,Cs为采样电容的电容值,Rs为采样电阻的电阻值,L为电感的电感值。
  11. 如权利要求6或7所述的Buck型DC-DC变换器的负载电流检测电路,其特征在于:
    所述信号平均化处理单元中,所述第一偏置电流源的输出电流Ibias1与第二偏置电流源的输出电流Ibias2满足如下公式:
    Ibias 1*Rs*K3=Ibias2
    其中,K3为电压转电流模块的转换比例系数,Rs为采样电阻的电阻值。
  12. 一种Buck型DC-DC变换器,其特征在于包括权利要求1~11中任意一项所述的负载电流检测电路。
  13. 一种用于Buck型DC-DC变换器的负载电流检测方法,基于 权利要求1~11中任意一项所述的负载电流检测电路实现,其特征在于包括如下步骤:
    所述开关管导通期间检测开关管电流,形成检测电流;
    所述检测电流和偏置电流源通过采样保持处理后,产生电感电流上升阶段与电感电流成比例的检测电压;
    所述续流管导通期间检测输出电压,形成补偿电流;
    所述补偿电流与所述检测电流和所述偏置电流源共同进行采样保持处理后,产生电感电流下降阶段与电感电流成比例的检测电压;
    将所述检测电压经过平均化处理后得到平均电压;
    将所述平均电压转化为电流信号再去除偏置电流信息后,得到负载电流。
PCT/CN2024/086573 2023-04-10 2024-04-08 一种Buck型DC-DC变换器的负载电流检测电路及方法 Ceased WO2024212923A1 (zh)

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