WO2024138400A1 - Synchronous data processing method, and device - Google Patents

Abstract

A synchronous data processing method, comprising: sending a preset synchronization frame to a plurality of slave devices, wherein the preset synchronization frame is used for instructing each of the slave devices to enter an edge-triggered mode; sending synchronization data to the plurality of slave devices, wherein the synchronization data is used for instructing each of the slave devices to start data sampling upon the reception of a first edge of the synchronization data; receiving a transmission time, which is sent by each of the slave devices, wherein the transmission time is a total time for receiving the synchronization data, which total time is recorded by the slave device in the edge-triggered mode; calculating relative time offsets between the plurality of slave devices according to the transmission times, which are sent by the slave devices; receiving sampled data, which is returned by each of the slave devices; and processing the sampled data according to the relative time offsets, so as to obtain synchronous sampled data of the plurality of slave devices.

Description

Synchronous data processing method and device Technical Field

The present application belongs to the field of communication technology, and in particular, relates to a synchronous data processing method and device.

Background technique

The statements herein merely provide background information related to the present application and do not necessarily constitute exemplary techniques.

The current communication bus has a wide range of application scenarios, and the communication bus can be used for communication between various devices. In practical applications, in a communication bus that includes a master device control and multiple slave devices as data sampling units, the clock synchronization of data sampling of each slave device is highly required.

However, the master device and each slave device have their own clock systems, and there is a certain deviation between the clock systems, which makes it difficult for the master device to obtain highly synchronized data from the slave devices.

Summary of the invention

According to various embodiments of the present application, a synchronous data processing method, device and storage medium are provided.

In a first aspect, an embodiment of the present application provides a synchronous data processing method, which is applied to a master device, wherein the master device is communicatively connected with a plurality of slave devices, and the method includes:

Sending a preset synchronization frame to the plurality of slave devices, wherein the preset synchronization frame is used to instruct each of the slave devices to enter an edge-triggered mode;

Sending synchronization data to the multiple slave devices, wherein the synchronization data is used to instruct each of the slave devices to start data sampling when receiving a first edge of the synchronization data;

Receiving the transmission time sent by each of the slave devices, wherein the transmission time is the total time recorded by the slave device for receiving the synchronization data in the edge-triggered mode;

Calculating the relative time deviation between the plurality of slave devices according to the transmission time sent by each of the slave devices;

Receiving the sampled data returned from each of the slave devices;

The sampled data are processed according to the relative time deviation to obtain synchronous sampled data of the multiple slave devices.

In a second aspect, an embodiment of the present application provides a synchronous data processing method, which is applied to a slave device, wherein the slave device is communicatively connected to a master device, and the method includes:

In response to a preset synchronization frame sent by the master device, changing a receiving mode to an edge-triggered mode;

Starting data sampling upon receiving the first edge of the synchronization data sent by the master device to obtain sampled data;

using the total time of receiving the synchronization data in the edge-triggered mode as the transmission time, and sending the transmission time to the master device;

The sampling data is sent to the master device so that the master device calculates the relative time deviation between multiple slave devices based on the transmission time sent by each slave device, and processes the sampling data according to the relative time deviation to obtain synchronous sampling data of the multiple slave devices.

In a third aspect, an embodiment of the present application provides a synchronous data processing method, which is applied to a communication system, wherein the communication system includes a master device and multiple slave devices, and the master device is communicatively connected with the multiple slave devices, and the method includes:

The master device sends a preset synchronization frame to the multiple slave devices;

The slave device changes the receiving mode to the edge triggered mode in response to the preset synchronization frame sent by the master device;

The master device sends synchronization data to the multiple slave devices;

The slave device starts data sampling upon receiving the first edge of the synchronization data to obtain sampled data;

The slave device uses the total time of receiving the synchronization data in the edge-triggered mode as the transmission time;

The slave device sends the transmission time and the sampling data to the master device;

The master device receives the transmission time and sampling data sent by the multiple slave devices;

The master device calculates the relative time deviation between the plurality of slave devices according to the transmission time sent by each of the slave devices;

The master device processes the sampled data according to the relative time deviation to obtain the synchronous sampled data of the plurality of slave devices.

In a fourth aspect, an embodiment of the present application provides a computer device, comprising a processor and a memory, wherein the processor is configured to implement the above-mentioned synchronous data processing method when executing a computer program stored in the memory.

In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the above-mentioned synchronous data processing method is implemented.

The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

FIG. 1 is a diagram showing an application environment of a synchronous data processing method provided in an embodiment of the present application.

FIG. 2 is a flowchart of a synchronous data processing method provided in an embodiment of the present application.

FIG. 3 is a schematic diagram of signal waveforms when synchronous data is transmitted on a bus according to an embodiment of the present application.

FIG. 4 is a flow chart of calculating a relative time deviation according to an embodiment of the present application.

FIG5 is a flowchart of determining synchronous sampling data provided by an embodiment of the present application.

FIG6 is a flow chart of a synchronous data processing method provided in another embodiment of the present application.

FIG. 7 is a flow chart of trigger conditions of an edge-triggered mode provided in an embodiment of the present application.

FIG8 is a flow chart of calculating the transmission time provided in an embodiment of the present application.

FIG. 9 is a flowchart of determining the end edge of synchronization data provided in an embodiment of the present application.

FIG. 10 is a flow chart of determining the transmission time according to an embodiment of the present application.

FIG. 11 is a flow chart of a synchronous data processing method provided in yet another embodiment of the present application.

FIG. 12 is a schematic diagram of the structure of a synchronous data processing device provided in an embodiment of the present application.

FIG. 13 is a diagram showing the structure of a computer device according to an embodiment of the present application.

Detailed ways

In order to more clearly understand the above-mentioned purposes, features and advantages of the present application, the present application is described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

In the following description, many specific details are set forth to facilitate a full understanding of the present application. The described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present application.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

Communication buses have a wide range of application scenarios and can be used for communication between various devices. In practical applications, in a communication bus network topology with one master device and multiple slave devices, the clock synchronization of data sampling for each slave device is highly required. However, the master device and each slave device have their own clock systems, and there is a certain deviation between each clock system, which makes it difficult for the master device to obtain highly synchronized data from the above slave devices.

Among them, according to the type of information transmitted between various devices, the communication bus can be divided into a data bus, an address bus and a control bus, which are used to transmit data, data addresses and control signals respectively.

Taking the communication bus as RS485 bus as an example, the application environment diagram of the synchronous data processing method provided by the embodiment of the present application is illustrated in conjunction with Figure 1. The master device and multiple slave devices are connected via RS485 bus communication, and the number of slave devices is not specifically limited. The master device and each slave device are controlled by a single-chip microcomputer, and the single-chip microcomputer is provided with a respective clock system, such as a crystal oscillator. When data is transmitted between various devices via the RS485 bus, due to certain deviations between the various clock systems, it is difficult for the master device to obtain highly synchronized data from the above-mentioned slave devices.

Based on the above problems, an embodiment of the present application provides a synchronous data processing method, so that a master device can obtain highly synchronized data from each slave device.

The synchronous data processing method provided in the embodiment of the present application can be executed by a computer device, and accordingly, the synchronous data processing device runs in the computer device. FIG. 2 is a flow chart of the synchronous data processing method provided in the embodiment of the present application, and the synchronous data processing method is applied to the master device. As shown in FIG. 2, the synchronous data processing method may include the following steps S11-S16. According to different requirements, the order of the steps in the flow chart can be changed, and some can be omitted.

S11, sending a preset synchronization frame to multiple slave devices, where the preset synchronization frame is used to instruct each slave device to enter an edge-triggered mode.

In at least one embodiment of the present application, the preset synchronization frame is a data frame of a custom setting format. For example, the preset synchronization frame can include one or more bytes, each byte can include a start bit, a data bit and a stop bit, and the specific number of bits of the start bit, the data bit and the stop bit can be customized. In some embodiments, the bytes of the preset synchronization frame can also include a check bit. Taking RS485 bus communication as an example, 1 byte can include 10 bits. The master device sends the preset synchronization frame to multiple slave devices at the same time point, and the slave device changes the receiving mode to the edge triggered mode after receiving the preset synchronization frame.

It can be understood that before entering the edge-triggered mode, the slave device defaults to working in the serial port receiving mode. Taking the RS485 bus as an example, in this embodiment, the serial port receiving mode means that the RS485 bus receiving port of the slave device notifies the application to perform the corresponding operation only after receiving a complete 1-byte data. The edge-triggered mode means that when the data received by the RS485 bus receiving port of the slave device changes in level, an interrupt will be triggered, an interrupt processing function will be executed, and a corresponding operation, such as data sampling, will be performed. The level change can refer to the data changing from a high level to a low level, or the data changing from a low level to a high level.

It is understood that in some embodiments, multiple slave devices are used for data sampling, and the master device is used to obtain sampled data from each slave device. Taking the RS485 bus as an example, after the slave device samples the data, it reports the sampled data to the master device via the RS485 bus.

S12, sending synchronization data to multiple slave devices, where the synchronization data is used to instruct each slave device to start data sampling when receiving the first edge of the synchronization data.

In at least one embodiment of the present application, the master device simultaneously sends synchronization data to multiple slave devices within a preset time period, and the preset time period is a preset duration for sending synchronization data. Synchronous data refers to a preset number of bytes, and the preset number is preset. For example, the preset time period is 2 milliseconds, and the preset number can be 1000, which means that the master device will send 1000 bytes of synchronization data in the next 2 milliseconds, and the slave device will be ready to receive 1000 bytes of synchronization data at any time in the next 2 milliseconds until the reception is completed. The preset time and preset number can be set or adjusted according to needs in actual applications.

As mentioned above, each byte may include a number of bits, for example, including a start bit, a data bit, and a stop bit, wherein the start bit and the stop bit may be 1 bit, and the data bit may be 8 bits. In some embodiments, a check bit may also be included, in which case the start bit and the stop bit may be 1 bit, for example, only the start bit or only the stop bit may be set.

It can be understood that for synchronous data, the value of the bit of each byte is different. In this way, each time the current bit is entered from the previous bit, a rising edge or a falling edge will be generated, and the slave device can determine the number of bits received. In conjunction with Figure 3, the schematic diagram of the edge change of the slave device when receiving synchronous data provided by the embodiment of the present application is described. Exemplarily, before the slave device receives the synchronous data, its bus interface port is a default level, for example, a high level. When the slave device receives the start bit of the first byte of the synchronous data, the start bit is 0, then the data level changes, from a high level to a low level, and the slave device can record the falling edge at P1, which is also the first edge of the synchronous data. Afterwards, the slave device receives the first data bit 1 of the first byte of the synchronous data, and the data level changes again, from a low level to a high level, and the slave device can record the rising edge at P2, and so on, which will not be repeated here. At the first edge of the received synchronous data, the slave device triggers an interrupt and executes an interrupt processing function. Afterwards, the slave device starts data sampling and collects data from each channel.

In the embodiment of the present application, the master device sends synchronization data to each slave device, and controls each slave device to start data sampling when receiving the first edge of the synchronization data. Since the edge triggering time is extremely short, each slave device can start sampling at almost the same time, ensuring high synchronization of starting sampling by each slave device.

S13, receiving the transmission time sent by each slave device, where the transmission time is the total time recorded by the slave device for receiving synchronous data in the edge trigger mode.

In at least one embodiment of the present application, each slave device has its own clock system. When each slave device receives the start bit of the first byte of the synchronization data, it starts timing according to its own clock system, calculates the total time from the start bit of the first byte to the stop bit of the last byte, and uses the total time as the transmission time of each slave device. In this embodiment, the last stop bit is not counted. Assuming that the number of bytes of the synchronization data is 1000, and each byte includes 10 bits, the total time recorded by the slave device for receiving the synchronization data is the total time for receiving (10*1000-1) bits.

For example, if the synchronization data is 1000 bytes and there are 2 slave devices (slave device A and slave device B), slave device A starts timing when it receives the start bit of the first byte of the synchronization data, and ends timing when it receives (10*1000-1) bits, and records the timing time as T _A. Then, the total time for receiving the synchronization data recorded by slave device A is T _A. Similarly, slave device B starts timing when it receives the start bit of the first byte of the synchronization data, and ends timing when it receives (10*1000-1) bits, and records the timing time as T _B. The total time for receiving the synchronization data recorded by slave device B is T _B.

S14, calculating the relative time deviation between the multiple slave devices according to the transmission time sent by each slave device.

In at least one embodiment of the present application, since each slave device is provided with a clock system, there is a certain deviation between each clock system, so each slave device will also have a deviation according to its own clock system timing. On this basis, each slave device performs data sampling according to the agreed sampling interval, and the sampling interval of each slave device is biased, so that the moment of sampling data also has a certain deviation. However, since the deviation caused by the clock system is fixed, therefore, when receiving synchronous data, this deviation also exists. Still taking the synchronous data as 1000 bytes, the number of slave devices is 2 (slave device A and slave device B respectively) as an example, the transmission time TA recorded by slave device _A is not the same as the transmission time _TB recorded by slave device B, and there is a time deviation, which is caused by the clock system of each slave device.

In one embodiment, the relative time deviation is the time deviation of the remaining slave devices relative to the reference device calculated according to a preset relative time deviation calculation formula, with one of the multiple slave devices as the reference device. The preset relative time deviation calculation formula can be preset. Exemplarily, taking the communication bus including slave device A and slave device B as an example, the relative time deviation can refer to the time deviation of slave device A relative to slave device B, or the time deviation of slave device B relative to slave device A, which is not limited here. Assuming that the time deviation of slave device B relative to slave device A is ΔT _BA , then:

ΔT _BA =( _TB - _TA )/ _TA .

S15, receiving the sampled data returned from each slave device.

In at least one embodiment of the present application, when sampling data from a device, a DMA (Direct Memory Access) channel can be used to control an ADC (Analog-to-Digital Converter) to perform sampling to obtain sampled data. The method of using a DMA channel to control the ADC for sampling is not limited in this embodiment and can be any existing technology, which will not be described in detail here.

In one embodiment, each slave device uses the time when the interrupt is triggered and the interrupt processing function is executed as the starting time of data sampling, and sets the same sampling interval to perform data sampling. It can be understood that since the edge triggering time is very short, each slave device starts sampling at almost the same time. The sampling interval can be preset, for example, the sampling interval is 1ms, which is not limited here.

In one embodiment, after the master device sends the last byte of the synchronization data to the slave device, the synchronization process ends. Subsequently, each slave device transmits the sampled data to the master device.

It can be understood that after the synchronous data is sent, the slave device can continue to sample data, for example, perform timed sampling within a predetermined time, or continue sampling at a preset sampling interval, until the master device sends a stop sampling notification.

S16, processing the sampled data according to the relative time deviation to obtain synchronous sampled data of multiple slave devices.

In at least one embodiment of the present application, since there is a certain time deviation in the clock system between the slave devices, there is actually a deviation in the sampling interval between the slave devices, which results in that when the slave devices perform data sampling at the same starting time and the same sampling interval, the final sampled data are not synchronized. A slave device among the multiple slave devices is used as a reference device, and the sampling interval of the remaining slave devices is corrected. Then, the sampling time of each sampled data point in the sampled data relative to the starting time is corrected according to the sampling interval, and the corrected sampled data of the remaining slave devices can be obtained. At this time, the sampled data of each slave device is synchronized.

In the above-mentioned synchronous data processing method provided by the embodiment of the present application, the master device controls each slave device to enter the edge-triggered state by presetting the synchronization frame. Afterwards, the master device sends synchronization data to each slave device, and controls each slave device to start data sampling when receiving the first edge of the synchronization data. Since the edge triggering time is extremely short, each slave device can start sampling at almost the same time, so that the synchronization of sampling startup of each slave device is high. Subsequently, the master device receives the transmission time sent by each slave device, and determines the relative time deviation between each slave device according to the transmission time, and processes the sampled data of each slave device according to the relative time deviation, thereby obtaining highly synchronized data.

The following is a flow chart of calculating the relative time deviation provided by an embodiment of the present application in conjunction with FIG. 4. In some embodiments, the relative time deviation between multiple slave devices is calculated according to the transmission time sent by each slave device, including:

S140, selecting a first slave device from the slave devices, and determining a transmission time sent by the first slave device.

In one embodiment, the first slave device is a reference device. The first slave device may be selected in a designated manner or randomly. For example, if there are slave devices A and B, slave device A may be designated as the first slave device; or, a slave device may be randomly selected from slave devices A and B as the first slave device.

S141, determining the slave devices other than the first slave device among the slave devices as second slave devices, and calculating the relative time deviation between the transmission time sent by each second slave device and the transmission time sent by the first slave device.

In one embodiment, the number of the second slave devices may be one or more, which is not limited herein. The relative time deviation may be calculated by a preset relative time deviation calculation formula. Exemplarily, still taking the number of slave devices as two (slave device A and slave device B), the transmission time of slave device A is _TA , for example, _TA is 10085, and the transmission time of slave device B is _TB , for example, _TB is 99754. The relative time deviation ΔT _BA between the transmission time sent by slave device B and slave device A is ( _{TB -TA} )/ _TA , which is -1.1%. It can be understood that -1.1% means that slave device B is 1.1% slower than slave device A.

The following is a description of the process for determining synchronous sampling data provided by an embodiment of the present application in conjunction with FIG. 5. In some embodiments, the sampling data is processed according to the relative time deviation to obtain synchronous sampling data of multiple slave devices, including:

S160, determining a start time of data sampling and a first sampling interval.

In one embodiment, the starting time and sampling interval of data sampling are both pre-set, for example, the sampling interval is 1ms. The starting time of data sampling of each slave device is the same, that is, the time corresponding to the first edge of the synchronization data is received. It can be understood that for each slave device, its agreed sampling interval should be the same, but due to the clock deviation of each slave device, the actual sampling interval of each slave device has a deviation. Here, the first sampling interval refers to the sampling interval of the first slave device. When the first slave device is used as the reference device, its sampling interval is assumed to be accurate, and the sampling interval deviation of other slave devices will be corrected based on the sampling interval of the first device.

S161, determining a second sampling interval of a second slave device according to the first sampling interval and the relative time deviation.

In one embodiment, as shown above, since there is a relative time deviation between the slave devices, the actual sampling intervals between the slave devices also actually have deviations, and the second sampling interval of the second slave device needs to be determined based on the first sampling interval and the relative time deviation. The second sampling interval is the sampling interval of the second slave device corrected based on the clock of the first slave device. Exemplarily, assuming that the clock of slave device B is 1.1% slower than that of slave device A, the first sampling interval of slave device A is 100 clock cycles, and the second sampling interval of slave device B is 99 clock cycles.

S162, correcting the sampling time of each sampling data point in the sampling data of the second slave device relative to the starting time according to the second sampling interval, to obtain corrected sampling data of the second slave device.

In one embodiment, assuming that each slave device samples once every 100 slave station clocks to obtain a data sampling point, each sampled data point has a corresponding sampling time. The sampling time of each sampled data point in the sampled data of the second slave device relative to the starting time is corrected according to the second sampling interval to obtain the corrected sampled data of the second slave device.

Exemplarily, taking the number of slave devices as 2 (slave device A and slave device B), the sampling interval is set to 100 clock cycles, and each slave device samples once every 100 slave station clock cycles. It can be understood that when there is no time deviation between slave device A and slave device B, assuming that the 100th sampled data point sampled from slave device A corresponds to time A (relative to the starting time), then the 100th sampled data point sampled from slave device B should also correspond to time A, that is, the 100th sampled points of slave devices A and slave devices B correspond to the same time. However, if there is a time deviation between slave device A and slave device B, there will be a deviation in the above correspondence. Assuming that slave device A is the reference device, the time deviation of slave device B relative to slave device A is 1%, that is, the clock of slave device B is 1% slower than that of slave device A. At this time, the 100th sampled data point of slave device A, at this time A, actually corresponds to the 99th sampled data point sampled from device B. Therefore, making the 99th sampling data point of slave device B correspond to the 100th sampling data point of slave device A is actually equivalent to correcting the sampling time of the 99th sampling point of slave device B to time A. In this way, the synchronous sampling data of slave devices A and B can be obtained.

S163, determining the sampled data of the first slave device as the synchronous sampled data of the first slave device, and determining the corrected sampled data of the second slave device as the synchronous sampled data of the second slave device.

It can be understood that, with the first slave device as the reference device, the sampling data of the first slave device can be used as synchronous sampling data without correction. For the sampling data of other slave devices such as the second slave device, the sampling data obtained after correction according to the above process can be obtained as synchronous sampling data.

Fig. 6 is a flowchart of a synchronous data processing method provided in an embodiment of the present application, and the synchronous data processing method is applied to a slave device. As shown in Fig. 6, the synchronous data processing method may include the following steps S21-S24. According to different requirements, the order of the steps in the flowchart may be changed, and some may be omitted.

S21, in response to a preset synchronization frame sent by the master device, changing the receiving mode to an edge-triggered mode.

In at least one embodiment of the present application, the master device sends a preset synchronization frame to multiple slave devices at the same time point, and the slave device changes the receiving mode to the edge-triggered mode after receiving the preset synchronization frame. The edge-triggered mode means that when the level of the data received by the RS485 bus receiving port of the slave device changes, an interrupt will be triggered, an interrupt processing function will be executed, and corresponding operations, such as data sampling, will be performed. The level change can refer to the data changing from a high level to a low level, or the data changing from a low level to a high level.

S22, starting data sampling when receiving the first edge of the synchronization data sent by the master device to obtain sampled data.

In at least one embodiment of the present application, when the slave device receives the first edge of the synchronization data (i.e., the start bit of the first byte), the data level changes, and when the level of the received data changes, the slave device triggers an interrupt and executes an interrupt processing function. After that, the slave device starts data sampling and collects data from each channel.

In one embodiment, when the slave device samples data, it can use a DMA (Direct Memory Access) channel to control an ADC (Analog-to-Digital Converter) to perform sampling to obtain sampled data. The method of using a DMA channel to control an ADC for sampling is a prior art and will not be described in detail herein.

In one embodiment, each slave device triggers an interrupt and executes an interrupt processing function as the start time of data sampling, and sets the same sampling interval for data sampling. It can be understood that since the edge triggering time is very short, each slave device starts sampling at almost the same time. The sampling interval is preset, for example, the sampling interval is 1ms, which is not limited here.

In one embodiment, after the master device sends the last byte of the synchronization data to the slave device, the synchronization process ends. Subsequently, each slave device transmits the sampled data to the master device.

It can be understood that after the synchronous data is sent, the slave device can continue to sample data, for example, perform timed sampling within a predetermined time, or continue sampling at a preset sampling interval, until the master device sends a stop sampling notification.

S23, takes the total time of receiving the synchronous data in the edge trigger mode as the transmission time, and sends the transmission time to the master device.

In at least one embodiment of the present application, each slave device has its own clock system. When each slave device receives the start bit of the first byte of the synchronization data, it starts timing according to its own clock system, calculates the total time from the start bit of the first byte to the stop bit of the last byte, and uses the total time as the transmission time of each slave device. In this embodiment, the last stop bit is not counted. Assuming that the number of bytes of the synchronization data is 1000, and each byte includes 10 bits, the total time recorded by the slave device for receiving the synchronization data is the total time for receiving (10*1000-1) bits.

Exemplarily, when slave device A receives the start bit of the first byte of synchronization data, it stops timing when it receives (10*1000-1) bits and records the timing time as _TA . Then the total time for receiving synchronization data recorded by slave device A is _TA .

S24, sending the sampled data to the master device, so that the master device calculates the relative time deviation between the multiple slave devices based on the transmission time sent by each slave device, and processes the sampled data according to the relative time deviation to obtain synchronous sampled data of the multiple slave devices.

In at least one embodiment of the present application, since each slave device is provided with a clock system, there is a certain deviation between each clock system, so each slave device will also have a deviation according to its own clock system timing. On this basis, each slave device performs data sampling according to the agreed sampling interval, and the sampling interval of each slave device is biased, so that the moment of sampling data also has a certain deviation. However, since the deviation caused by the clock system is fixed, therefore, when receiving synchronous data, this deviation also exists. Still taking the synchronous data as 1000 bytes, the number of slave devices is 2 (slave device A and slave device B respectively) as an example, the transmission time TA recorded by slave device _A is not the same as the transmission time _TB recorded by slave device B, and there is a time deviation, which is caused by the clock system of each slave device.

In one embodiment, the master device uses a slave device among multiple slave devices as a reference device, and calculates the time deviation of the remaining slave devices relative to the reference device according to a preset relative time deviation calculation formula. The preset relative time deviation calculation formula is pre-set. Since there is a relative time deviation between the slave devices, there is actually a deviation in the sampling interval between the slave devices, which causes the final sampling data to be not synchronized when the slave devices perform data sampling at the same starting time and the same sampling interval. Using a slave device among multiple slave devices as a reference device, the sampling interval of the remaining slave devices is corrected, and then the sampling time of each sampling data point in the sampling data relative to the starting time is corrected according to the sampling interval, and the corrected sampling data of the remaining slave devices can be obtained. At this time, the sampling data of each slave device is synchronized.

The triggering condition of the edge triggering mode provided in the embodiment of the present application is illustrated in conjunction with FIG. 7 . After responding to the preset synchronization frame sent by the master device, the method further includes:

S210, determining a check bit corresponding to a preset synchronization frame.

In one embodiment, the preset synchronization frame may include one or more bytes, each byte may include a start bit, a data bit, and a stop bit, and the specific number of the start bit, the data bit, and the stop bit may be customized. In some embodiments, the bytes in the preset synchronization frame may also include a check bit.

S211, when the check bit meets the preset check requirement, determine that the check is correct and update the receiving mode to the edge trigger mode.

In one embodiment, before receiving the preset synchronization frame, each slave device is in a serial port receiving mode, that is, it responds to the data frame to perform the corresponding operation only after receiving the complete data frame. The check bit is used to confirm that the current preset synchronization frame has been received and received correctly. When the preset check bit meets the preset check requirement, it can be confirmed that the preset synchronization frame has been received. At this time, the slave device updates the receiving mode to the edge trigger mode. When the check bit does not meet the preset check requirement, there is no need to update the receiving mode to the edge trigger mode.

The calculation process of the transmission time provided in the embodiment of the present application is illustrated in conjunction with FIG8 , and the total time of receiving the synchronization data is calculated as the transmission time, including:

S230, determine the number of bits corresponding to the synchronization data.

In one embodiment, the synchronization data refers to a preset number of bytes, which is preset, for example, the preset number may be 1000. Each byte may include a number of bits, for example, a start bit, a data bit, and a stop bit, wherein the start bit and the stop bit may be 1 bit, and the data bit may be 8 bits. The number of bits refers to the number of bits in the synchronization data. When the synchronization data includes 1000 bytes and 1 byte includes 10 bits, the stop bit of the last byte in the synchronization data is not counted, and the number of bits is 10*1000-1.

S231, determining the end edge of the synchronization data according to the first edge of the synchronization data and the number of bits.

In one embodiment, the master device transmits the start bit of the first byte of synchronization data to each slave device as the first edge, and considers that the stop bit of the last byte of synchronization data is not included, and the 10*1000-1th bit of the synchronization data is used as the end edge.

S232, determining the time interval between the first edge received and the end edge received as the transmission time.

In one embodiment, taking the synchronization data as 1000 bytes as an example, the slave device A starts timing when receiving the start bit of the first byte of the synchronization data, and stops timing when receiving (10*1000-1) bits, and records the timing time as _TA . The total time (i.e., transmission time) for receiving the synchronization data recorded by the slave device A is _TA .

The process of determining the end edge of the synchronization data provided in the embodiment of the present application is described in conjunction with FIG. 9 . The process of determining the end edge of the synchronization data according to the first edge of the synchronization data and the number of bits includes:

S2310, when the first edge of the synchronization data is received, start a counter to accumulate the number of received edges.

In one embodiment, the edge here refers to a rising edge or a falling edge. As mentioned above, in the synchronization data, the value of each bit of each byte is different, that is, the beginning of each bit in each byte of the synchronization data is a rising edge or a falling edge. After receiving the pre-synchronization frame, the slave device enters the edge trigger mode. When the master device starts to send synchronization data, when the slave device identifies the first rising edge or falling edge, it can be confirmed that the rising edge or falling edge is the first edge of the synchronization data, and the counter is started to count. It can be understood that the type of the first edge depends on the setting of the start bit and the stop bit. For example, if the value of the start bit is set to 0 and the stop bit is 1, the first edge is a falling edge, otherwise, it is a rising edge. The counter is used to record the number of edges in the synchronization data received from the slave device. When the first edge of the synchronization data is received (taking the first edge as a falling edge as an example), the slave device enters edge triggering for the first time and starts counting from 0; when the slave device receives the second edge (taking the second edge as a rising edge as an example), the slave device enters edge triggering for the second time and the count is increased by 1, and so on. The counter can count the number of edges received, that is, the number of bits of synchronization data received.

In one embodiment, taking the synchronization data as 1000 bytes, where 1 byte contains 10 bits, a total of 10*1000 bits are contained. When the slave device receives 10*1000 edges, the number of counters is 10*1000-1.

S2311, when the count of the counter is equal to the number of bits, determine that the current edge is the end edge of the synchronization data.

In one embodiment, when the synchronization data includes 1000 bytes and 1 byte includes 10 bits, the stop bit of the last byte in the synchronization data is not counted, and the number of bits is 10*1000-1. When the count of the timer is also 10*1000-1, the current edge is determined to be the end edge of the synchronization data.

The process of determining the transmission time provided in the embodiment of the present application is described in conjunction with FIG. 10 , and determining the time interval between the first edge received and the end edge received as the transmission time includes:

S2320: When the first edge of the synchronization data is received, start the timer to start timing.

In one embodiment, the timer is used to record the time when the slave device receives the edge of the synchronization data. When the first edge of the synchronization data is received (taking the first edge as a falling edge as an example), the slave device enters edge triggering for the first time, resets the timer to 0, and starts timing.

S2321, when the end edge of the synchronization data is received, stop timing.

In one embodiment, when the synchronization data includes 1000 bytes and 1 byte includes 10 bits, the stop bit of the last byte in the synchronization data is not counted. When the end edge of 10*1000-1 is received, the timer is controlled to stop timing, and the time is recorded as T ₁ .

S2322, determine the timing time of the timer as the transmission time.

In one embodiment, the transmission time is T ₁ .

FIG11 is a flow chart of a synchronous data processing method provided in an embodiment of the present application, and the synchronous data processing method is applied to a communication system, wherein the communication system includes a master device and a plurality of slave devices, and the master device is in communication connection with the plurality of slave devices. As shown in FIG11 , the synchronous data processing method may include the following steps S31-S39, and the order of the steps in the flow chart may be changed and some may be omitted according to different requirements.

S31, the master device sends a preset synchronization frame to multiple slave devices.

S32, the slave device changes the receiving mode to the edge triggering mode in response to the preset synchronization frame sent by the master device.

S33, the master device sends synchronization data to multiple slave devices.

S34, the slave device starts data sampling upon receiving the first edge of the synchronization data to obtain sampled data.

S35, the slave device uses the total time of receiving the synchronous data in the edge trigger mode as the transmission time.

S36, the slave device sends the transmission time and sampling data to the master device.

S37, the master device receives the transmission time and sampling data sent by multiple slave devices.

S38, the master device calculates the relative time deviation between the multiple slave devices according to the transmission time sent by each slave device.

S39, the master device processes the sampled data according to the relative time deviation to obtain synchronous sampled data of multiple slave devices.

The above steps S31-S39 correspond to steps S11-S16 and steps S21-S24 respectively. For the specific implementation process, please refer to the description of the above embodiment, which will not be repeated here.

It should be understood that in the above embodiments, a certain slave device among the multiple slave devices is used as the reference device, and in some other embodiments, the master device may also be used as the reference device. When the master device is used as the reference device, the relative time deviation between the duration of the preset time period and the transmission time sent by each slave device can be calculated according to the preset time period for the master device to send synchronous data, and the sampled data of each slave device can be processed according to the relative time deviation between the master device and each slave device to obtain the synchronous sampled data of multiple slave devices.

Please refer to FIG. 12, which is a schematic diagram of the structure of the synchronous data processing device provided in an embodiment of the present application. In some embodiments, the synchronous data processing device 20 may include a plurality of functional modules composed of computer program segments. The computer program of each program segment in the synchronous data processing device 20 may be stored in the memory of the computer device 30 and executed by at least one processor to perform (see FIG. 1 for details) the function of synchronous data processing.

In this embodiment, the synchronous data processing device 20 can be divided into multiple functional modules according to the functions it performs. When the synchronous data processing device 20 is applied to the master device, the functional modules may include: a synchronous frame sending module 201, a synchronous data sending module 202, a transmission time receiving module 203, a time deviation calculation module 204, a sampled data receiving module 205, and a sampled data processing module 206. The module referred to in this application refers to a series of computer program segments that can be executed by at least one processor and can complete fixed functions, which are stored in a memory. In this embodiment, the functions of each module will be described in detail in subsequent embodiments.

The synchronization frame sending module 201 is used to send a preset synchronization frame to a plurality of slave devices, and the preset synchronization frame is used to instruct each slave device to enter an edge-triggered mode.

The synchronous data sending module 202 is used to send synchronous data to multiple slave devices. The synchronous data is used to instruct each slave device to start data sampling when receiving the first edge of the synchronous data.

The transmission time receiving module 203 is used to receive the transmission time sent by each slave device. The transmission time is the total time recorded by the slave device for receiving synchronous data in the edge trigger mode.

The time deviation calculation module 204 is used to calculate the relative time deviation between multiple slave devices according to the transmission time sent by each slave device.

The sampled data receiving module 205 is used to receive the sampled data returned by each slave device.

The sampled data processing module 206 is used to process the sampled data according to the relative time deviation to obtain synchronous sampled data of multiple slave devices.

Please refer to Fig. 13, which is a schematic diagram of the structure of a computer device 30 provided in an embodiment of the present application. In a preferred embodiment of the present application, the computer device 30 includes a memory 31, at least one processor 32, and at least one communication bus 33.

Those skilled in the art should understand that the structure of the computer device shown in FIG. 13 does not constitute a limitation of the embodiments of the present application, and may be either a bus structure or a star structure. The computer device 30 may also include more or less other hardware or software than shown in the figure, or a different component arrangement.

In some embodiments, the computer device 30 is a device that can automatically perform numerical calculations and/or information processing according to pre-set or stored instructions, and its hardware includes but is not limited to microprocessors, application-specific integrated circuits, programmable gate arrays, digital processors, and embedded devices. The computer device 30 may also include client devices, which include but are not limited to any electronic product that can interact with the client through a keyboard, mouse, remote control, touchpad, or voice-controlled device, such as a personal computer, tablet computer, smart phone, digital camera, etc.

It should be noted that the computer device 30 is only an example, and other existing or future electronic products that are suitable for the present application should also be included in the protection scope of the present application and included here by reference.

In some embodiments, a computer program is stored in the memory 31, and when the computer program is executed by at least one processor 32, all or part of the steps in the synchronous data processing method are implemented. The memory 31 includes a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), a one-time programmable read-only memory (OTPROM), an electronically erasable rewritable read-only memory (EEPROM), a compact disc (CD-ROM) or other optical disc storage, magnetic disk storage, magnetic tape storage, or any other computer-readable medium that can be used to carry or store data.

Furthermore, the computer-readable storage medium may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function, etc.; the data storage area may store data created according to the use of the computer device 30, etc.

In some embodiments, at least one processor 32 is the control core (Control Unit) of the computer device 30, and uses various interfaces and lines to connect various components of the entire computer device 30, and executes various functions and processes data of the computer device 30 by running or executing programs or modules stored in the memory 31, and calling data stored in the memory 31. For example, when at least one processor 32 executes the computer program stored in the memory, it implements all or part of the steps of the synchronous data processing method in the embodiment of the present application; or implements all or part of the functions of the synchronous data processing device. At least one processor 32 can be composed of an integrated circuit, for example, it can be composed of a single packaged integrated circuit, or it can be composed of multiple integrated circuits with the same or different functions, including one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and combinations of various control chips.

In some embodiments, at least one communication bus 33 is configured to implement connection and communication between the memory 31 and at least one processor 32, etc.

Although not shown, the computer device 30 may also include a power source (such as a battery) for supplying power to each component. Preferably, the power source may be logically connected to at least one processor 32 through a power management device, so that the power management device can manage charging, discharging, and power consumption management. The power source may also include one or more DC or AC power sources, recharging devices, power failure detection circuits, power converters or inverters, power status indicators, and other arbitrary components. The computer device 30 may also include a variety of sensors, Bluetooth modules, Wi-Fi modules, etc., which will not be repeated here.

The above-mentioned integrated unit implemented in the form of a software function module can be stored in a computer-readable storage medium. The above-mentioned software function module is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a computer device, or a network device, etc.) or a processor to execute parts of the methods of various embodiments of the present application.

In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of modules is only a logical function division, and there may be other division methods in actual implementation.

The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, and may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional module in each embodiment of the present application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional modules.

It is obvious to those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, and that the present application can be implemented in other specific forms without departing from the spirit or basic features of the present application. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-restrictive, and the scope of the present application is limited by the attached claims rather than the above description, so it is intended to include all changes that fall within the meaning and scope of the equivalent elements of the claims in the present application. Any figure mark in the claims should not be regarded as limiting the claims involved. In addition, it is obvious that the word "including" does not exclude other units or, and the singular does not exclude the plural. Multiple units or devices stated in the specification can also be implemented by one unit or device through software or hardware. The words first, second, etc. are used to indicate names, and do not indicate any particular order.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present application and are not intended to limit it. Although the present application has been described in detail with reference to the preferred embodiments, a person of ordinary skill in the art should understand that the technical solution of the present application may be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present application.

Claims (10)

A synchronous data processing method is applied to a master device, wherein the master device is communicatively connected with a plurality of slave devices, and the method comprises: Sending a preset synchronization frame to the plurality of slave devices, wherein the preset synchronization frame is configured to instruct each of the slave devices to enter an edge-triggered mode; Sending synchronization data to the plurality of slave devices, wherein the synchronization data is configured to instruct each of the slave devices to start data sampling upon receiving a first edge of the synchronization data; Receiving the transmission time sent by each of the slave devices, wherein the transmission time is the total time recorded by the slave device for receiving the synchronization data in the edge-triggered mode; Calculating the relative time deviation between the plurality of slave devices according to the transmission time sent by each of the slave devices; Receiving the sampled data returned from each of the slave devices; The sampled data are processed according to the relative time deviation to obtain synchronous sampled data of the multiple slave devices. The method according to claim 1, characterized in that the step of calculating the relative time deviation between the plurality of slave devices according to the transmission time sent by each of the slave devices comprises: Selecting a first slave device from each of the slave devices, and determining a transmission time sent by the first slave device; The slave devices other than the first slave device among the slave devices are determined as second slave devices, and the relative time deviation between the transmission time sent by each of the second slave devices and the transmission time sent by the first slave device is calculated. The method according to claim 2, wherein the processing of the sampled data according to the relative time deviation to obtain the synchronous sampled data of the plurality of slave devices comprises: Determine the starting time of data sampling and the first sampling interval; determining a second sampling interval of the second slave device according to the first sampling interval and the relative time deviation; Correcting the sampling time of each sampling data point in the sampling data of the second slave device relative to the starting time according to the second sampling interval to obtain corrected sampling data of the second slave device; The sampling data of the first slave device is determined as the synchronous sampling data of the first slave device, and the corrected sampling data of the second slave device is determined as the synchronous sampling data of the second slave device. A synchronous data processing method is applied to a slave device, wherein the slave device is communicatively connected with a master device, and the method comprises: In response to a preset synchronization frame sent by the master device, changing a receiving mode to an edge-triggered mode; Starting data sampling upon receiving the first edge of the synchronization data sent by the master device to obtain sampled data; using the total time of receiving the synchronization data in the edge-triggered mode as the transmission time, and sending the transmission time to the master device; The sampling data is sent to the master device so that the master device calculates the relative time deviation between multiple slave devices based on the transmission time sent by each slave device, and processes the sampling data according to the relative time deviation to obtain synchronous sampling data of the multiple slave devices. The method according to claim 4, characterized in that after the preset synchronization frame sent in response to the master device, the method further comprises: Determine the check bit corresponding to the preset synchronization frame; When the check bit meets the preset check requirement, it is determined that the check is correct and the receiving mode is updated to the edge triggered mode. The method according to claim 4, characterized in that the calculating the total time of receiving the synchronization data as the transmission time comprises: Determining the number of bits corresponding to the synchronization data; Determine the end edge of the synchronization data according to the first edge of the synchronization data and the number of bits; A time interval between receiving the first edge and receiving the end edge is determined as the transmission time. The method according to claim 6, characterized in that the step of determining the end edge of the synchronization data according to the first edge of the synchronization data and the number of bits comprises: When the first edge of the synchronization data is received, a counter is started to accumulate the number of edges received; When the count of the counter is equal to the bit number, the current edge is determined to be the end edge of the synchronization data. The method according to claim 7, wherein determining the time interval between receiving the first edge and the end edge as the transmission time comprises: When the first edge of the synchronization data is received, starting a timer for timing; When the end edge of the synchronization data is received, stop timing; The timing time of the timer is determined as the transmission time. A synchronous data processing method is applied to a communication system, wherein the communication system includes a master device and a plurality of slave devices, wherein the master device is communicatively connected with the plurality of slave devices, and the method includes: The master device sends a preset synchronization frame to the multiple slave devices; The slave device changes the receiving mode to the edge triggered mode in response to the preset synchronization frame sent by the master device; The master device sends synchronization data to the multiple slave devices; The slave device starts data sampling upon receiving the first edge of the synchronization data to obtain sampled data; The slave device uses the total time of receiving the synchronization data in the edge-triggered mode as the transmission time; The slave device sends the transmission time and the sampling data to the master device; The master device receives the transmission time and sampling data sent by the multiple slave devices; The master device calculates the relative time deviation between the plurality of slave devices according to the transmission time sent by each of the slave devices; The master device processes the sampled data according to the relative time deviation to obtain the synchronous sampled data of the plurality of slave devices. A computer device, characterized in that the computer device includes a processor and a memory, and the processor is used to implement the synchronous data processing method as described in any one of claims 1 to 3 when executing the computer program stored in the memory, or to implement the synchronous data processing method as described in any one of claims 4 to 8.

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