WO2024136849A1

WO2024136849A1 - Apparatus and method for serializer/deserializer forward-flow control to avoid inter-chip back pressure messaging

Info

Publication number: WO2024136849A1
Application number: PCT/US2022/053499
Authority: WO
Inventors: Ricky Lap Kei Cheung; Tao Yu; Jifeng Geng; Jianghua YING
Original assignee: Zeku, Inc.
Priority date: 2022-12-20
Filing date: 2022-12-20
Publication date: 2024-06-27

Abstract

According to one aspect of the present disclosure, a wireless device is provided. The wireless device may include a memory pool. The memory pool may be configured to maintain a plurality of uplink (UL) samples. The wireless device may include a forward-flow control (FFC) unit. The FFC unit may be configured to determine a SerDes transmit time for a UL sample from the memory pool across a SerDes to a buffer. The FFC unit may be configured to cause the memory pool to transmit the UL sample across the SerDes to the buffer at the SerDes transmit time.

Description

APPARATUS AND METHOD FOR SERIALIZER/DESERIALIZER FORWARD-FLOW CONTROL TO AVOID INTER-CHIP BACK PRESSURE MESSAGING

BACKGROUND

[1] Embodiments of the present disclosure relate to apparatus and method for wireless communication.

[2] Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, and broadcasts. In cellular communication, such as the 4th-gen eration (4G) Long Term Evolution (LTE) and the 5th- generation (5G) New Radio (NR), the 3rd Generation Partnership Project (3GPP) defines various procedures for sending uplink (UL) samples across a Serializer/Deserializer (SerDes) connection.

SUMMARY

[3] According to one aspect of the present disclosure, a wireless device is provided. The wireless device may include a memory pool. The memory pool may be configured to maintain a plurality of UL samples of a UL packet. The wireless device may include a forward-flow control (FFC) unit. The FFC unit may be configured to determine a SerDes transmit time for a UL sample from the memory pool across a SerDes to a buffer. The FFC unit may be configured to cause the memory pool to transmit the UL sample across the SerDes to the buffer at the SerDes transmit time.

[4] According to another aspect of the present disclosure, an apparatus for wireless communication of UE. The apparatus may include a radio frequency (RF) chip. The RF chip may include a resampler. The RF chip may include a buffer. The apparatus may include a baseband chip. The baseband chip may include a memory pool. The memory pool may be configured to maintain a plurality of UL samples of a UL packet. The baseband chip may include an FFC unit. The FFC unit may be configured to determine a SerDes transmit time for a UL sample from the memory pool across a SerDes to a buffer located at an RF chip. The FFC unit may be configured to cause the memory pool to transmit the UL sample across the SerDes to the buffer at the RF chip at the SerDes transmit time.

[5] According to yet another aspect of the present disclosure, a method of wireless communication of a UE is provided. The method may include maintaining, by a memory pool, a plurality of UL samples. The method may include determining, by an FFC unit, a SerDes transmit time for a UL sample from the memory pool across a SerDes to a buffer. The method may include causing, the FFC unit, the memory pool to transmit the UL sample across the SerDes to the buffer at the SerDes transmit time.

[6] These illustrative embodiments are mentioned not to limit or define the present disclosure, but to provide examples to aid understanding thereof. Additional embodiments are discussed in the Detailed Description, and further description is provided there.

BRIEF DESCRIPTION OF THE DRAWINGS

[7] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

[8] FIG. 1 illustrates a block diagram of an example apparatus that implements UL packet flow control by applying inter-chip back pressure across a Serializer/Deserializer (SerDes) between a radio frequency (RF) chip and a baseband chip.

[9] FIG. 2 illustrates an exemplary wireless network, according to some embodiments of the present disclosure.

[10] FIG. 3 illustrates a block diagram of an exemplary node, according to some embodiments of the present disclosure.

[11] FIG. 4A illustrates a detailed block diagram of an exemplary apparatus that includes a baseband chip, a RF chip, and a host chip, according to some embodiments of the present disclosure.

[12] FIG. 4B illustrates a detailed block diagram of the exemplary apparatus of FIG. 4A in which FFC is applied to avoid inter-chip back pressure across the SerDes between the RF chip and the baseband chip.

[13] FIG. 5 illustrates the various depth levels of a first-in, first-out2 (FIFO2) buffer of an RF chip, according to some embodiments of the present disclosure.

[14] FIG. 6 illustrates a timing diagram of an exemplary operation that may be performed by an FFC unit to determine a UL sample SerDes transmission time, according to some embodiments of the present disclosure.

[15] FIG. 7 illustrates a detailed block diagram of an exemplary FFC unit, according to some embodiments of the present disclosure.

[16] FIG. 8 illustrates a state diagram of the various states of an exemplary FFC unit, according to some embodiments of the present disclosure.

[17] FIG. 9 illustrates a diagram of an exemplary SerDes UL sample timing relationship, according to some embodiments of the present disclosure.

[18] FIG. 10 illustrates a graphical representation of the FIFO2 buffer’s UL sample depth, according to some embodiments of the present disclosure.

[19] FIG. 11 is a flowchart of an exemplary method of wireless communication, according to some aspects of the present disclosure.

[20] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

[21] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

[22] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” “certain embodiments,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[23] In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

[24] Various aspects of wireless communication systems will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the particular application and design constraints imposed on the overall system.

[25] The techniques described herein may be used for various wireless communication networks, such as code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, orthogonal frequency division multiple access (OFDMA) system, single-carrier frequency division multiple access (SC- FDMA) system, wireless local area network (WLAN) system, and other networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio access technology (RAT), such as Universal Terrestrial Radio Access (UTRA), evolved UTRA (E-UTRA), CDMA 2000, etc. A TDMA network may implement a RAT, such as the Global System for Mobile Communications (GSM). An OFDMA network may implement a RAT, such as LTE or NR. A WLAN system may implement a RAT, such as Wi-Fi. The techniques described herein may be used for the wireless networks and RATs mentioned above, as well as other wireless networks and RATs.

[26] SerDes is a generic term used to describe a high-speed digital interface between the RF chip and the baseband chip of a mobile device. Non-limiting examples of a SerDes connection include, e.g., the Joint Electron Device Engineering Council’s (JEDEC) current serial standard JESD204a/b/c (e.g., which has dedicated downlink (DL) and uplink (UL) connections), the M- physical layer (PHY) (e.g., which has dedicated DL and UL connections) from Mobile Industry Processor Interface (MIPI) Alliance, and Peripheral Component Interconnect (PCI) Express (PCIe) (e.g., DL and UL share a single connection), just to name a few.

[27] Depending on the RF chip design, packet traffic sent across the SerDes in either the DL or UL direction may be bursty or contiguous. In the UL direction, if bursty traffic (e.g., one packet with one-hundred in-phase, in-quadrature (IQ) samples) is used, a back pressure message may be used to regulate the flow of UL samples across SerDes to avoid buffer overflow at the FIFO2 buffer at the RF chip. For example, when the FIFO2 buffer is almost full or when the amount of UL samples it maintains reaches a threshold level, the FIFO2 buffer may send a back pressure message across the SerDes. This back pressure message may indicate that the FIFO2 buffer is almost full, and the memory pool should stop sending UL samples. Then, when the FIFO2 buffer is almost empty, it may send another back pressure message so that UL samples may be sent from the memory pool across the SerDes once again. An example of this signal flow is depicted in FIG. 1, which illustrates a system 100 that includes a baseband chip 102 and an RF chip 104.

[28] Referring to FIG. 1, baseband chip 102 includes a transmission (Tx) modulator (TxMoD) component configured to modulate IQ samples for UL transmission and a memory pool 130, which may be implemented as a buffer to hold UL samples after Tx modulation. RF chip 104 may include a frequency shifter 110, a farrow filter 114, a phase accumulator 116, a first FIFO (FIFO1) buffer 118 located in a resampler 112, a windowed overlap and add (WOLA)/cascaded integrator-comb filter (CIC) 120, and a second FIFO (FIFO2) buffer. Resampler 112 may convert bursty incoming UL samples in FIFO1 into continuous outgoing UL samples. WOLA/CIC 120 may include one or more UL components/circuits to process and upsample UL signals. SerDes 124 and a serial peripheral interface (SPI) 126 may be located between baseband chip 102 and RF chip 104.

[29] At RF chip 104, the UE has its own clock, and the base station has its own clock. Both devices assume their own clock frequency is correct, but this may not always be the case. So, the base station may measure the difference between the two and tell the UE how much to adjust its clock frequency. Resampler 112 is used to adjust this difference in clock frequency. For example, the UE may attempt to transmit 1000 IQ samples in 1ms (e.g., in 1000 clock cycles), but the base station informs the number of clock cycles is actually 1001. There is an integer part, and a fractional part, and resampler 112 adjusts the clock frequency based on this difference. In other words, when UL samples are read from a TxMoD 132, they are read a little too slowly. If the transmission continues without clock frequency adjustment by resampler 112, every 1000 clock cycles, one additional sample will be left in FIFO1 buffer 118. So FIFO1 buffer 118 slowly accumulates UL samples until it overflows due to clock inaccuracy (e.g., 1000 vs. 1001 clock cycles). For this reason, back pressure messages are sent in the downlink direction to reduce/eliminate FIFO overflow due to clock cycle inaccuracy. Various back pressure messages are illustrated in system 100 depicted in FIG. 1.

[30] For example, referring to FIG. 1, when the amount of UL samples maintained by FIFO1 buffer 118 reaches a threshold value, a first back pressure message (BP1) 101 may be sentto FIFO2 buffer 122, which stops sending UL samples to FIFO1 buffer 118. As previously mentioned, when the amount of UL samples in FIFO2 buffer 122 reaches a threshold value, a second back pressure message (BP2) 103 may be sent across SerDes 124 to stop memory pool 130 from sending UL samples. When the amount of UL samples in memory pool 130 reaches a threshold level, a third back pressure message (BP3) 105 may be sent to TxMoD 132.

[31] Sending BP2 103 across SerDes 124 has various disadvantages. These disadvantages include, e.g., signal delay uncertainty associated with the buffer of FIFO2 122, signaling overhead, power consumption, and communication mistakes in which BP2 103 may be missed or delayed, which causes various problems. For example, if DL SerDes is congested or experiences an error, BP2 103 may not be received by memory pool 130 in time to stop UL samples from being sent across SerDes 124 to FIFO2 buffer 122. Once FIFO2 buffer 122 is full, any additional UL samples received may be dropped. Dropped UL samples may cause a catastrophic failure in UL transmission.

[32] Thus, there exists an unmet need for a mechanism to control the flow of UL samples across the SerDes to avoid FIFO2 buffer sample overload without sending a back pressure message across the SerDes.

[33] To overcome these and other challenges, the present disclosure provides an exemplary forward flow control (FFC) unit in the baseband chip. The exemplary FFC unit may include an accumulator that tracks the integer part and the fractional part of the clock cycle difference to avoid any overflow or underflow of UL samples sent from the baseband chip to the RF chip. For example, the exemplary FFC unit may use the clock cycles in the UE and base station to estimate the number of samples to send from the FIFO2 through SerDes before they are needed by resampler. In this way, back pressure messages sent across the SerDes may be eliminated, while increasing the reliability of UL flow control. Additional details of the exemplary FFC unit and its exemplary operations are provided below in connection with FIGs. 2-11.

[34] FIG. 2 illustrates an exemplary wireless network 200, in which some aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure. As shown in FIG. 2, wireless network 200 may include a network of nodes, such as user equipment 202, an access node 204, and a core network element 206. User equipment 202 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Internet-of-Things (loT) node. It is understood that user equipment 202 is illustrated as a mobile phone simply by way of illustration and not by way of limitation.

[35] Access node 204 may be a device that communicates with user equipment 202, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 204 may have a wired connection to user equipment 202, a wireless connection to user equipment 202, or any combination thereof. Access node 204 may be connected to user equipment 202 by multiple connections, and user equipment 202 may be connected to other access nodes in addition to access node 204. Access node 204 may also be connected to other user equipments. When configured as a gNB, access node 204 may operate in millimeter wave (mmW) frequencies and/or near mmW frequencies in communication with the user equipment 202. When access node 204 operates in mmW or near mmW frequencies, the access node 204 may be referred to as an mmW base station. Extremely high frequency (EHF) is part of the radio frequency (RF) in the electromagnetic spectrum. EHF has a range of 30 GHz to 300 GHz and a wavelength between 1 millimeter and 10 millimeters. Radio waves in the band may be referred to as a millimeter wave. Near mmW may extend down to a frequency of 3 GHz with a wavelength of 200 millimeters. The super high frequency (SHF) band extends between 3 GHz and 30 GHz, also referred to as centimeter wave. Communications using the mmW or near mmW radio frequency band have extremely high path loss and a short range. The mmW base station may utilize beamforming with user equipment 202 to compensate for the extremely high path loss and short range. It is understood that access node 204 is illustrated by a radio tower by way of illustration and not by way of limitation.

[36] Access nodes 204, which are collectively referred to as E-UTRAN in the evolved packet core network (EPC) and as NG-RAN in the 5G core network (5GC), interface with the EPC and 5GC, respectively, through dedicated backhaul links (e.g., SI interface). In addition to other functions, access node 204 may perform one or more of the following functions: transfer of user data, radio channel ciphering and deciphering, integrity protection, header compression, mobility control functions (e.g., handover, dual connectivity), inter-cell interference coordination, connection setup and release, load balancing, distribution for non-access stratum (NAS) messages, NAS node selection, synchronization, radio access network (RAN) sharing, multimedia broadcast multicast service (MBMS), subscriber and equipment trace, RAN information management (RIM), paging, positioning, and delivery of warning messages. Access nodes 204 may communicate directly or indirectly (e.g., through the 5GC) with each other over backhaul links (e.g., X2 interface). The backhaul links may be wired or wireless.

[37] Core network element 206 may serve access node 204 and user equipment 202 to provide core network services. Examples of core network element 206 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the LTE system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 206 includes an access and mobility management function (AMF), a session management function (SMF), or a user plane function (UPF) of the 5GC for the NR system. The AMF may be in communication with a Unified Data Management (UDM). The AMF is the control node that processes the signaling between the user equipment 202 and the 5GC. Generally, the AMF provides QoS flow and session management. All user Internet protocol (IP) packets are transferred through the UPF. The UPF provides user equipment (UE) IP address allocation as well as other functions. The UPF is connected to the IP Services. The IP Services may include the Internet, an intranet, an IP Multimedia Subsystem (IMS), a PS Streaming Service, and/or other IP services. It is understood that core network element 206 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation.

[38] Core network element 206 may connect with a large network, such as the Internet 208, or another Internet Protocol (IP) network, to communicate packet data over any distance. In this way, data from user equipment 202 may be communicated to other user equipments connected to other access points, including, for example, a computer 210 connected to Internet 208, for example, using a wired connection or a wireless connection, or to a tablet 212 wirelessly connected to Internet 208 via a router 214. Thus, computer 210 and tablet 212 provide additional examples of possible user equipments, and router 214 provides an example of another possible access node.

[39] A generic example of a rack-mounted server is provided as an illustration of core network element 206. However, there may be multiple elements in the core network including database servers, such as a database 216, and security and authentication servers, such as an authentication server 218. Database 216 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 218 may handle authentication of users, sessions, and so on. In the NR system, an authentication server function (AUSF) device may be the entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 206, authentication server 218, and database 216, may be local connections within a single rack.

[40] Each element in FIG. 2 may be considered a node of wireless network 200. More detail regarding the possible implementation of a node is provided by way of example in the description of a node 300 in FIG. 3. Node 300 may be configured as user equipment 202, access node 204, or core network element 206 in FIG. 2. Similarly, node 300 may also be configured as computer 210, router 214, tablet 212, database 216, or authentication server 218 in FIG. 2. As shown in FIG. 3, node 300 may include a processor 302, a memory 304, and a transceiver 306. These components are shown as connected to one another by a bus, but other connection types are also permitted. When node 300 is user equipment 202, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 300 may be implemented as a blade in a server system when node 300 is configured as core network element 206. Other implementations are also possible.

[41] Transceiver 306 may include any suitable device for sending and/or receiving data. Node 300 may include one or more transceivers, although only one transceiver 306 is shown for simplicity of illustration. An antenna 308 is shown as a possible communication mechanism for node 300. Multiple antennas and/or arrays of antennas may be utilized for receiving multiple spatially multiplex data streams. Additionally, examples of node 300 may communicate using wired techniques rather than (or in addition to) wireless techniques. For example, access node 204 may communicate wirelessly to user equipment 202 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 206. Other communication hardware, such as a network interface card (NIC), may be included as well.

[42] As shown in FIG. 3, node 300 may include processor 302. Although only one processor is shown, it is understood that multiple processors can be included. Processor 302 may include microprocessors, microcontroller units (MCUs), digital signal processors (DSPs), applicationspecific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 302 may be a hardware device having one or more processing cores. Processor 302 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software.

[43] As shown in FIG. 3, node 300 may also include memory 304. Although only one memory is shown, it is understood that multiple memories can be included. Memory 304 can broadly include both memory and storage. For example, memory 304 may include random-access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferro-electric RAM (FRAM), electrically erasable programmable ROM (EEPROM), compact disc read-only memory (CD-ROM) or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 302. Broadly, memory 304 may be embodied by any computer-readable medium, such as a non-transitory computer-readable medium.

[44] Processor 302, memory 304, and transceiver 306 may be implemented in various forms in node 300 for performing wireless communication functions. In some embodiments, at least two of processor 302, memory 304, and transceiver 306 are integrated into a single system-on-chip (SoC) or a single system-in-package (SiP). In some embodiments, processor 302, memory 304, and transceiver 306 of node 300 are implemented (e.g., integrated) on one or more SoCs. In one example, processor 302 and memory 304 may be integrated on an application processor (AP) SoC (sometimes known as a “host,” referred to herein as a “host chip”) that handles application processing in an operating system (OS) environment, including generating raw data to be transmitted. In another example, processor 302 and memory 304 may be integrated on a baseband processor (BP) SoC (sometimes known as a “modem,” referred to herein as a “baseband chip”) that converts the raw data, e.g., from the host chip, to signals that can be used to modulate the carrier frequency for transmission, and vice versa, which can run a real-time operating system (RTOS). In still another example, processor 302 and transceiver 306 (and memory 304 in some cases) may be integrated on an RF SoC (sometimes known as a “transceiver,” referred to herein as an “RF chip”) that transmits and receives RF signals with antenna 308. It is understood that in some examples, some or all of the host chip, baseband chip, and RF chip may be integrated as a single SoC. For example, a baseband chip and an RF chip may be integrated into a single SoC that manages all the radio functions for cellular communication.

[45] Referring back to FIG. 2, in some embodiments, user equipment 202 may include an exemplary FFC unit in its baseband chip. The exemplary FFC unit may include an accumulator that tracks the number of samples to be sent based on the integer part of an accumulator, which may change dynamically due to the clock cycle difference between user equipment 202 and access node 204 to avoid an overflow or underflow of UL samples from the baseband chip to the RF chip. For example, the exemplary FFC unit may use FFC logic to estimate the number of samples needed in the radio frequency (RF) chip based on the clock cycle in equipment 202 and access node 204. By tracking the clock cycle difference using an FFC unit coupled to the memory pool, back pressure messages sent across the SerDes may be eliminated, while increasing the reliability of UL flow control and saving the power consumption of the Serdes. Additional details of the exemplary FFC unit and its exemplary operations are provided below in connection with FIGs. 4A-10.

[46] FIG. 4A illustrates a block diagram of an exemplary apparatus 400 including a baseband chip 402, an RF chip 404, and a host chip 406, according to some embodiments of the present disclosure. FIG. 4B illustrates a detailed block diagram 450 of the exemplary apparatus 400 of FIG. 4A, in which FFC is applied to avoid back pressure across the SerDes between RF chip 404 and baseband chip 402, according to some embodiments of the present disclosure. FIGs. 4A and 4B will be described together.

[47] Referring to FIG. 4A, apparatus 400 may be implemented as user equipment 202 of wireless network 200 in FIG. 2. As shown in FIG. 4A, apparatus 400 may include baseband chip 402, RF chip 404, host chip 406, and one or more antennas 410. In some embodiments, baseband chip 402 is implemented by a processor and a memory, and RF chip 404 is implemented by a processor, a memory, and a transceiver. Besides the on-chip memory 413 (also known as “internal memory,” e.g., registers, buffers, or caches) on each chip 402, 404, or 406, apparatus 400 may further include an external memory 408 (e.g., the system memory or main memory) that can be shared by each chip 402, 404, or 406 through the system/main bus. Although baseband chip 402 is illustrated as a standalone SoC in FIG. 4A, it is understood that in one example, baseband chip 402 and RF chip 404 may be integrated as one SoC or one SiP; in another example, baseband chip 402 and host chip 406 may be integrated as one SoC or one SiP; in still another example, baseband chip 402, RF chip 404, and host chip 406 may be integrated as one SoC or one SiP, as described above.

[48] In the uplink, host chip 406 may generate raw data and send it to baseband chip 402 for encoding, modulation, and mapping. Interface 411 of baseband chip 402 may receive the data from host chip 406. Baseband chip 402 may also access the raw data generated by host chip 406 and stored in external memory 408, for example, using the direct memory access (DMA). Baseband chip 402 may first encode (e.g., by source coding and/or channel coding) the raw data and modulate the coded data using any suitable modulation techniques, such as orthogonal frequency-division multiplexing (OFDM) modulation or quadrature amplitude modulation (QAM). Baseband chip 402 may perform any other functions, such as symbol or layer mapping, to convert the raw data into a signal that can be used to modulate the carrier frequency for transmission. In the uplink, baseband chip 402 may send the modulated signal to RF chip 404 via interface 411. RF chip 404, through the transmitter, may convert the modulated signal in the digital form into analog signals, i.e., RF signals, and perform any suitable front-end RF functions, such as filtering, digital pre-distortion, up-conversion, or sample-rate conversion. Antenna 410 (e.g., an antenna array) may transmit the RF signals provided by the transmitter of RF chip 404.

[49] In the downlink, antenna 410 may receive RF signals from an access node or other wireless device. The RF signals may be passed to the receiver (Rx) of RF chip 404. RF chip 404 may perform any suitable front-end RF functions, such as filtering, IQ imbalance compensation, downpaging conversion, or sample-rate conversion, and convert the RF signals (e.g., transmission) into low-frequency digital signals (baseband signals) that can be processed by baseband chip 402.

[50] Still referring to FIG. 4A, baseband chip 402 may include an exemplary FFC unit 432 (referred to hereinafter as “FFC unit 432”). FFC unit 432 may include an accumulator that tracks the number of samples based on the clocks used in apparatus 400 and a base station. Using the accumulator, baseband chip 402 may prevent an overflow or underflow of UL samples to RF chip 404. For instance, FFC unit 432 may use the SerDes start time plus FFC logic to track the number of samples needed in RF chip 404 based on the apparatus 400 and base station 204 clock cycles. By tracking the two clock cycles using FFC unit 432 coupled to memory pool 430, back pressure messages sent across the SerDes may be eliminated, while increasing the reliability of UL flow control. Additional details of FFC component unit 432 are illustrated in FIG. 4B.

[51] Referring to FIG. 4B, baseband chip 402 may include a TxMoD 434 configured to modulate IQ samples for UL transmission, memory pool 430, which may be implemented as a buffer to hold UL samples after Tx modulation, and FFC unit 432. RF chip 404 may include a frequency shifter 412, a farrow filter 416, a phase accumulator 418, a first FIFO (FIFO1) buffer 420 located in a resampler 414, a WOLA/CIC 422, and a second FIFO (FIFO2) buffer 424. Resampler 414 may convert bursty incoming UL samples in FIFO1 buffer 420 into continuous outgoing UL samples. WOLA/CIC 422 may include one or more UL components/circuits to process and upsample UL signals. SerDes 426 and an SPI 428 may be located between baseband chip 402 and RF chip 404.

[52] Still referring to FIG. 4B, FFC unit 432 may use the SerDes start time plus FFC logic for each slot to regulate traffic across SerDes 426 to avoid inter-chip back pressure messages. Instead, the semi-dynamic flow control shown in FIG. 4B is a mixture of intra-chip back pressure messages (e.g., BP1 401 and BP3 405) and FFC. FFC unit 432 ensures the FIFO2 buffer 424 is maintained at the target range to avoid accumulating UL samples up or down. After considering the resampler’s 414 clock frequency adjustment parameters indicated by the base station, a Layer 1 controller (not shown) assigns the SerDes start transfer time to the state machine of FFC unit 432. The UL sample rate of resampler 414 may match the UL sample rate that crosses the SerDes 426.

[53] FFC unit 432 may include a state machine that models several UL transmission states (see FIG. 8). Moreover, FFC unit 432 may include a status register (see FIG. 5) that tracks the integer part and the fractional part associated with clock frequency adjustment to represent the buffer level of FIFO2 buffer 424. To that end, FFC unit 432 may include an accumulator that tracks an integer part and a fractional part, which FFC unit 432 uses to predict when to transmit the next UL sample across SerDes 426.

[54] FIG. 5 illustrates a diagram of the various depth levels 500 of FIFO2 buffer 424 of RF chip 404, according to some embodiments of the present disclosure. FIG. 6 illustrates a timing diagram 600 for determining a UL sample SerDes transmission time by FFC unit 432, according to some embodiments of the present disclosure. FIG. 7 illustrates a detailed block diagram 700 of FFC unit 432, according to some embodiments of the present disclosure. FIGs. 5-7 will be described together.

[55] Referring to FIG. 5, the target depth indicated in FIG. 5 may be the target buffer depth for optimal operation of FIFO2 buffer 424. The target depth may be, e.g., 60% of the maximum amount of data that can be held by FIFO2 buffer 424.

[56] Referring to FIGs. 6 and 7, FFC unit 432 may receive various inputs, which it uses to determine when a UL sample should be sent across SerDes 426. These inputs may include, e.g., the target depth of FIFO2 buffer 424, the SerDes start time SerDes Start time in terms of the system time counter (STC) count for each transmit slot, the resampler starts time and stops time (e.g., start time/stop time), the sampling rate across SerDes (e.g., serdes sample rate), the baseband chip (e.g., baseband integrated circuit) clock rate (e.g., bbic clock rate), and UL packet size (e.g., samples_per_packet).

[57] FFC unit 432 may determine the time to send a package of samples through SerDes 426. FFC unit 432 may determine the clock length of baseband chip 402 as 1 divided by the clock rate of baseband chip 402. The phase step may be determined as the Serdes sample rate divided by baseband chip’s 402 clock rate. For example, phase step can be in U32Q31 format, which means it includes an unsigned 1 integer bit and a 31 fractional bit. An accumulator 706 accumulates phase step until an integer value is reached. Then, a carry bit is generated and sent to memory pool 430 to trigger another UL sample sent across SerDes 426. This may be calculated using firmware, software, or hardware located at FFC unit 432, for example. The number of UL samples sent to FIFO2 buffer 424 each baseband chip clock cycle may be calculated as transmitted_samples_per_bbic_clock=serdes_sample_rate/bbic_clock_rate.

[58] Referring to FIG. 7, FFC unit 432 may include a phase+per clock unit 702, an adder 704, and an accumulator 706. The phase _per_clock may be calculated and loaded into phase+per clock unit 702 in FIG. 7, for example. This fractional part U31 may be input into adder 704, while accumulator 706 inputs the integer part and the fractional part into adder 704. Accumulator 706 (with integer and fractional parts) may predict the time at which memory pool 430 transmits the subsequent UL sample across SerDes 426 to FIFIO2 buffer 424. For example, assume 10.5 clock means 1 symbol has been used. Here, the step size is 1/10.5, which is the number of UL samples sent per clock cycle. So, for every clock cycle, accumulator 706 adds 0.095. When an integer is accumulated, it means another UL sample should be sent across SerDes 426 to FIFO2 buffer 424. After the carry bit is generated and sent to memory pool 430, accumulator 706 may rest the integer part but keep the fractional part. Every clock cycle, accumulator 706 continuously accumulates. Using the same example, the first time an integer is accumulated is at eleven clock cycles, and then the second time an integer is reached will be at ten clock cycles because of the .5 fractional part. Whenever an integer of one is reached, accumulator 706 may signal to memory pool 430 to send another UL sample. Once the number of samples is enough to form a package, those samples will send as package across SerDes 426. In other words, accumulator 706 accumulates a fractional part until an integer part is reached, at which point another UL sample is sent to FIFO2 buffer 424. The number of clock cycles varies because of the fractional part, and accumulator 706 keeps the fractional part once the integer is reached. [59] FIG. 8 illustrates a state diagram of the various states 800 of FFC unit 432 of FIGs. 4A and 4B, according to some embodiments of the present disclosure. FIG. 9 illustrates a diagram of an exemplary SerDes UL sample timing relationship 900, according to some embodiments of the present disclosure. FIGs. 8 and 9 will be described together.

[60] Referring to FIG. 8, the state machine of FFC unit 432 may include, e.g., an idle state 802, a run state 804, and a stop state 806. FFC unit 432 may be in idle state 802 before the SerDes start time. Here, FIFO2 buffer 424 is empty before the first UL sample is sent across SerDes 426. The phase_per_clock may be calculated and loaded into phase+per clock unit 702 in FIG. 7, for example. The SerDes delay, the target depth of FIFO2 buffer 424, and the size of FIFO1 buffer 420 may be used to calculate the SerDes start time. This may be performed prior to when resampler 414 determines whether there is enough data in FIFO1 buffer 420 and FIFO2 buffer 424. If SerDes start time = STC time, an initial value of 0x80000000 is input into accumulator 706 to trigger memory pool 430 to send the first UL sample across SerDes 426. This value also transitions FFC unit 432 to run state 804.

[61] Referring to FIGs. 4B, 8, and 9, FFC unit 432 may transition to run state 804 after the SerDes start time is triggered. While in run state 804, FFC unit 432 may signal memory pool 430 to send a UL sample across SerDes 426. When resampler 414 begins, FIFO1 buffer 420 should be full, and the number of UL samples in FIFO2 buffer 424 should be around the target depth. After resampler 414 starts, based on its sampling rate, FFC unit 432 decides how often to cause one UL sample to be sent across SerDes 426 so that the SerDes data rate is equal or slightly higher than that of resampler 414. This may ensure the target depth of FIFO2 buffer 424 is maintained to optimize performance.

[62] In time-division duplex (TDD) mode, UL transmissions may only occur in several symbols out of a fourteen- symbol slot. Symbol usage information may be provided before the slot start. The start of UL transmission per slot are identified by the start time . FFC unit 432 may use symbol usage information to identify when samples are consumed from FIFO1 buffer 420. Based on the start-time, FFC unit 432 may calculate the corelative SerDes start time.

[63] Referring to FIGs. 4B and 8, stop state 806 may be entered at the end of a slot before returning to idle state 802 at the beginning of the following slot. In a normal transmit slot, the FFC state machine circulates each state once per slot. In some instances, zero-padding may be added to a UL packet to form a full packet if the last packet only has, e.g., 50 UL samples but a UL packet has one hundred UL samples. Here, zero-padding is added to the last packet of a slot when this happens.

[64] FIG. 10 illustrates a graphical representation 1000 of the FIFO2 buffer’s UL sample depth, according to some embodiments of the present disclosure.

[65] Referring to FIG. 10 and 9, when the SerDes start time triggers the FCC to transition from the idle state to the run state, the first package of data transfers through Serdes (assume 100 UL samples) and fills in FIFO2 buffer 424 after the delay of SerDes (at (1)). Once data in FIFO2 buffer 424 are available, FIFO1 buffer 420 starts (at (2)) to take data from FIFO2 buffer 424 until FIFO1 buffer 420 is full. In FIG 10, at time (2), the number of samples jumps to 100 after the first package is delivered, then slowly reduces 16 samples until FIFO1 is full. Here, it is assumed the size of FIFO1 buffer 420 is smaller than that of FIFO2 buffer 424. After every period of time, FFC unit 432 causes memory pool 430 to transmit package of UL samples to FIFO2 buffer 424 across SerDes 426. In FIG. 10, the number of samples jumps 100 every time the new package arrives. When resampler start time triggers, resampler 414 starts and the number of samples in FIFO2 buffer 424 reduces. The SerDes and resampler start times are calculated by software and programed to FFC unit 432 and resampler 414 based on the resampling rate, the SerDes delay, and the sizes of FIFO 1 buffer 420 and FIFO2 buffer 424.

[66] Once resampler 414 starts, it will draw data from FIFO2 buffer 424 at a constant speed (e.g., the slope of curves in FIG. 10 is constant). If FFC unit 432 sets the data throughput at SerDes interface equal to the resampler data rate, and the package size is one-hundred UL samples, when resampler draws one-hundred samples data from FIFO2, the new package of data will arrive and fills in one-hundred data samples to FIFO2 buffer 424 at almost the same time. Considering the truncation errors at the resampler phase and FFC phase step, FFC unit 432 may be configured to cause memory pool 430 to transmit data slightly faster than the resampler draws from FIFO2 buffer 424. Within one slot, the depth of FIFO2 buffer 424 increases slowly (at (6)). The last packet of data of each slot might include enough UL samples to fill the whole package (at (3)). Here, zeropadding may be added to complete the packet. Once the last package of data is sent at the end of each slot, FFC unit 432 returns to idle state 802. The accumulator will be cleared. If there is additional UL data to transmit in the next slot, the new SerDes start time will trigger the new round of FFC package transmission. If there is no UL data to transmit in the next slot, the depth of FIFO2 will be drawn continuously until it is empty (5).

[67] FIG. 11 is a flowchart of an exemplary method 1100 of wireless communication, according to some embodiments of the present disclosure. Method 1100 may be performed by an apparatus for wireless communication, e.g., such as a UE, a baseband chip, a memory pool, an FFC unit, a SerDes, a FIFO2 buffer, an accumulator, etc. Method 1100 may include steps 1102-1106, as described below. It is to be appreciated that some of the steps may be optional, and some of the steps may be performed simultaneously, or in a different order than shown in FIG. 11.

[68] Referring to FIG. 11, at 1102, the apparatus may maintain, by a memory pool, a plurality of UL samples of a UL packet for transmission over-the-air to a base station. For example, referring to FIGs. 4 A and 4B, memory pool 430, which may be implemented as a buffer to hold UL samples after Tx modulation.

[69] At 1104, the apparatus may determine, by an FFC unit, a SerDes transmit time for a UL sample from the memory pool across a SerDes to a FIFO buffer located at an RF chip. For example, referring to FIGs. 4A, 4B, and 7, FFC unit 432 may receive various inputs, which it uses to determine when a UL sample should be sent across SerDes 426 by memory pool 430. These inputs include, e.g., the target depth of FIFO2 buffer 424, the SerDes start time SerDes Start time in terms of STC count for each transmit slot, the resampler start time and stop time (e.g., start time/stop time), the sampling rate across SerDes (e.g., serdes sample rate), the baseband chip (e.g., baseband integrated circuit) clock rate (e.g., bbic clock rate), and UL packet size (e.g., samples_per_packet). FFC unit 432 may determine the SerDes packet length as the number of samples per packet divided by the SerDes sample rate. FFC unit 432 may determine the clock length of baseband chip 402 as 1 divided by the clock rate of baseband chip 402. The phase step may be determined as the clock length of baseband chip 402 divided by the SerDes packet length. For example, phase step can be in U32Q31 format, which means it is an unsigned 32 integer bit and a 31 fractional bit. An accumulator 706 accumulates phase step. Then, the time a carry is generated, a new UL sample should be sent to RF chip 404. This may be calculated using firmware located at FFC unit 432. The number of UL samples sent to FIFO2 buffer 424 each baseband chip clock cycle may be calculated as transmitted_samples_per_bbic_clock=serdes_sample_rate/bbic_clock_rate. Accumulator 706 (with integer and fractional part) may predict the time at which memory pool 430 transmits the subsequent UL sample across SerDes 426 to FIFIO2 buffer 424. For example, assumel0.5 clock means 1 symbol has been used. Here, the step size 1/10.5, which is the number of UL samples sent per clock cycle. So every clock cycle, accumulator 706 adds 0.095. When an integer is accumulated, it means one UL sample has been sent. Then, the integer part is reset, but the fractional part is kept. Using the same example, at the tenth clock cycle, accumulator 706 reaches another integer. The first time an integer is reached is at eleven clock cycles, and then the second time an integer is reached will be at ten clock cycles because of the .5 fractional part. Whenever an integer of one is reached, accumulator 706 may signal to memory pool 430 to send another UL sample across SerDes 426. In other words, accumulator 706 accumulates a fractional part until an integer part is reached, at which point another UL sample is sent to FIFO2 buffer 424. The number of clock cycles varies because of the fractional part, and accumulator 706 keeps the fractional part once the integer is reached.

[70] At 1106, the apparatus may cause, by the FFC unit, the memory pool to transmit the UL sample across the SerDes to the FIFO buffer at the RF chip at the SerDes transmit time. For example, referring to FIGs. 4A and 4B, the phase step may be determined as the clock length of baseband chip 402 divided by the SerDes packet length. For example, phase step can be in U32Q31 format, which means it is an unsigned 32 integer bit and a 31 fractional bit. An accumulator 706 accumulates phase step. Then, a carry bit is generated each time an integer value is reached, which means another UL sample should be sent to RF chip 404. This may be calculated using firmware located at FFC unit 432. The number of UL samples sent to FIFO2 buffer 424 each baseband chip clock cycle may be calculated as transmitted_samples_per_bbic_clock=serdes_sample_rate/bbic_clock_rate.

[71] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or encoded as instructions or code on a non-transitory computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computing device, such as node 300 in FIG. 3. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, HDD, such as magnetic disk storage or other magnetic storage devices, Flash drive, SSD, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system, such as a mobile device or a computer. Disk and disc, as used herein, includes CD, laser disc, optical disc, digital video disc (DVD), and floppy disk where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[72] According to one aspect of the present disclosure, a wireless device is provided. The wireless device may include a memory pool. The memory pool may be configured to maintain a plurality of UL samples of a UL packet. The wireless device may include an FFC unit. The FFC unit may be configured to determine a SerDes transmit time for a UL sample from the memory pool across a SerDes to a buffer. The FFC unit may be configured to cause the memory pool to transmit the UL sample across the SerDes to the buffer at the SerDes transmit time.

[73] In some embodiment, the FFC unit may be configured to determine the SerDes transmit time based on a target depth of the buffer, a SerDes start time, a resampler start time, a SerDes sampling rate, a baseband chip clock rate, and a UL packet size.

[74] In some embodiments, the SerDes sampling rate may match a resampler sample rate.

[75] In some embodiments, to determine the SerDes transmit time for the UL sample from the memory pool across the SerDes to the buffer, the FFC unit may be configured to accumulate a status register with a value that includes an integer part and a fractional part to represent a level of the buffer.

[76] In some embodiments, the SerDes transmit time may be determined each time an integer value is accumulated.

[77] In some embodiments, to cause the memory pool to transmit the UL sample across the SerDes to the buffer at the RF chip at the SerDes transmit time, the FFC unit may be configured to generate a carry bit that is sent to the memory pool.

[78] In some embodiments, the FFC unit may include a state machine configured to operate in an idle state, a run state, and a stop state.

[79] According to another aspect of the present disclosure, an apparatus for wireless communication of UE. The apparatus may include an RF chip. The RF chip may include a resampler. The RF chip may include a buffer. The apparatus may include a baseband chip. The baseband chip may include a memory pool. The memory pool may be configured to maintain a plurality of UL samples of a UL packet. The baseband chip may include an FFC unit. The FFC unit may be configured to determine a SerDes transmit time for a UL sample from the memory pool across a SerDes to the buffer located at the RF chip. The FFC unit may be configured to cause the memory pool to transmit the UL sample across the SerDes to the buffer at the RF chip at the SerDes transmit time.

[80] In some embodiment, the FFC unit may be configured to determine the SerDes transmit time based on a target depth of the buffer, a SerDes start time, a resampler start time, a SerDes sampling rate, a baseband chip clock rate, and a UL packet size.

[81] In some embodiments, the SerDes sampling rate may match a resampler sample rate at the RF chip.

[82] In some embodiments, to determine the SerDes transmit time for the UL sample from the memory pool across the SerDes to the buffer located at the RF chip, the FFC unit may be configured to accumulate a status register with a value that includes an integer part and a fractional part to represent a level of the buffer.

[83] In some embodiments, the SerDes transmit time may be determined each time an integer value is accumulated.

[84] In some embodiments, to cause the memory pool to transmit the UL sample across the SerDes to the buffer at the RF chip at the SerDes transmit time, the FFC unit may be configured to generate a carry bit that is sent to the memory pool.

[85] In some embodiments, the FFC unit may include a state machine configured to operate in an idle state, a run state, and a stop state.

[86] According to yet another aspect of the present disclosure, a method of wireless communication of a UE is provided. The method may include maintaining, by a memory pool, a plurality of UL samples of a UL packet. The method may include determining, by an FFC unit, a SerDes transmit time for a UL sample from the memory pool across a SerDes to a buffer located at an RF chip. The method may include causing, by the FFC unit, the memory pool to transmit the UL sample across the SerDes to the buffer at the RF chip at the SerDes transmit time.

[87] In some embodiments, the SerDes transmit time is determined based on a target depth of the buffer, a SerDes start time, a resampler start time, a SerDes sampling rate, a baseband chip clock rate, and a UL packet size.

[88] In some embodiments, the SerDes sampling rate matches a resampler sample rate at the RF chip.

[89] In some embodiments, the determining, by the FFC unit, the SerDes transmit time for the UL sample from the memory pool across the SerDes to the buffer located at the RF chip may include accumulating a status register with a value that includes an integer part and a fractional part to represent a level of the buffer.

[90] In some embodiments, the SerDes transmit time may be determined each time an integer value is accumulated.

[91] In some embodiments, the causing, by the FFC unit, the memory pool to transmit the UL sample across the SerDes to the buffer at the RF chip at the SerDes transmit time may include generating a carry bit that is sent to the memory pool. [92] The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

[93] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

[94] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[95] Various functional blocks, modules, and steps are disclosed above. The particular arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in different ways than in the examples provided above. Likewise, certain embodiments include only a subset of the functional blocks, modules, and steps, and any such subset is permitted. The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

WHAT IS CLAIMED IS:

1. A wireless device, comprising: a memory pool configured to: maintain a plurality of uplink (UL) samples of a UL packet; and a forward-flow control (FFC) unit configured to: determine a Serializer/Deserializer (SerDes) transmit time for a UL sample from the memory pool across a SerDes to a buffer; and cause the memory pool to transmit the UL sample across the SerDes to the buffer at the SerDes transmit time.

2. The wireless device of claim 1, wherein the FFC unit is configured to determine the SerDes transmit time based on a target depth of the buffer, a SerDes start time, a resampler start time, a SerDes sampling rate, a baseband chip clock rate, and a UL packet size.

3. The wireless device of claim 2, wherein the SerDes sampling rate matches a resampler sample rate.

4. The wireless device of claim 1, wherein, to determine the SerDes transmit time for the UL sample from the memory pool across the SerDes to the buffer, the FFC unit is configured to: accumulate a status register with a value that includes an integer part and a fractional part to represent a level of the buffer.

5. The wireless device of claim 4, wherein the SerDes transmit time is determined each time an integer value is accumulated.

6. The wireless device of claim 5, wherein, to cause the memory pool to transmit the UL sample across the SerDes to the buffer at the SerDes transmit time, the FFC unit is configured to: generate a carry bit that is sent to the memory pool.

7. The wireless device of claim 1, wherein the FFC unit comprises a state machine configured to operate in an idle state, a run state, and a stop state.

8. An apparatus for wireless communication of a user equipment (UE), comprising: a radio frequency (RF) chip, comprising: a resampler; and a buffer; and a baseband chip, comprising: a memory pool configured to: maintain a plurality of uplink (UL) samples of a UL packet; and a forward-flow control (FFC) unit configured to: determine a Serializer/Deserializer (SerDes) transmit time for a UL sample from the memory pool across a SerDes to the buffer located at a radio frequency (RF) chip; and cause the memory pool to transmit the UL sample across the SerDes to the buffer at the RF chip at the SerDes transmit time.

9. The apparatus of claim 8, wherein the FFC unit is configured to determine the SerDes transmit time based on a target depth of the buffer, a SerDes start time, a resampler start time, a SerDes sampling rate, a baseband chip clock rate, and a UL packet size.

10. The apparatus of claim 9, wherein the SerDes sampling rate matches a resampler sample rate at the RF chip.

11. The apparatus of claim 8, wherein, to determine the SerDes transmit time for the UL sample from the memory pool across the SerDes to the buffer located at the RF chip, the FFC unit is configured to: accumulate a status register with a value that includes an integer part and a fractional part to represent a level of the buffer.

12. The apparatus of claim 11, wherein the SerDes transmit time is determined each time an integer value is accumulated.

13. The apparatus of claim 12, wherein, to cause the memory pool to transmit the UL sample across the SerDes to the buffer at the RF chip at the SerDes transmit time, the FFC unit is configured to: generate a carry bit that is sent to the memory pool.

14. The apparatus of claim 8, wherein the FFC unit comprises a state machine configured to operate in an idle state, a run state, and a stop state.

15. A method of wireless communication of a baseband chip, comprising: maintaining, by a memory pool, a plurality of uplink (UL) samples of a UL packet; determining, by a forward-flow control (FFC) unit, a Serializer/Deserializer (SerDes) transmit time for a UL sample from the memory pool across a SerDes to a buffer located at a radio frequency (RF) chip; and causing, by the FFC unit, the memory pool to transmit the UL sample across the SerDes to the buffer at the SerDes transmit time.

16. The method of claim 15, wherein the SerDes transmit time is determined based on a target depth of the buffer, a SerDes start time, a resampler start time, a SerDes sampling rate, a baseband chip clock rate, and a UL packet size.

17. The method of claim 16, wherein the SerDes sampling rate matches a resampler sample rate.

18. The method of claim 15, wherein the determining, by the FFC unit, the SerDes transmit time for the UL sample from the memory pool across the SerDes to the buffer comprises: accumulating a status register with a value that includes an integer part and a fractional part to represent a level of the buffer.

19. The method of claim 18, wherein the SerDes transmit time is determined each time an integer value is accumulated.

20. The method of claim 19, wherein the causing, by the FFC unit, the memory pool to transmit the UL sample across the SerDes to the buffer at the RF chip at the SerDes transmit time comprises: generating a carry bit that is sent to the memory pool.