WO2024192977A1 - Circuit board and server - Google Patents

Abstract

A circuit board. The circuit board is provided with an intrusion detection circuit, and comprises: a power-off detection circuit (100), a power-on detection circuit (200), and a switch (300). One end of the switch (300) is connected to a first end (601) of the power-on detection circuit (200), and the other end of the switch (300) is grounded and is connected to a second end (602) of the power-on detection circuit (200). The first end (601) of the power-on detection circuit (200) is connected to a first end (701) of the power-off detection circuit (100), a third end (603) of the power-on detection circuit (200) is respectively connected to a second end (702) of the power-off detection circuit (100) and an internal power supply (500), and a fourth end (604) of the power-on detection circuit (200) is configured to be connected to a controller (400). A third end (703) of the power-off detection circuit (100) is connected to the controller (400), and a fourth end (704) of the power-off detection circuit (100) is grounded. The power-off detection circuit (100) is used for generating a first trigger signal when the circuit board is in a power-off state and the switch (300) is closed, and sending the first trigger signal to the controller (400) after the circuit board is powered on again. The power-on detection circuit (200) is used for generating a second trigger signal when an intrusion circuit board is in a power-on state and the switch (300) is closed, and sending the second trigger signal to the controller (400).

Description

Circuit board and server

This application claims the priority of the Chinese patent application filed with the China Patent Office on March 20, 2023, with application number 202310276081.7 and application name “A Circuit Board and Server”, all contents of which are incorporated by reference in this application.

Technical Field

The present application relates to the technical field of unpacking detection, and in particular to a circuit board provided with an unpacking detection circuit.

Background Art

As a key information processing infrastructure, servers have a variety of workplaces. When unattended, the device data needs to be secure. At the same time, the hard disk, CPU, and memory stick inside the server are all valuable assets, and the asset security of the server's internal components also needs to be ensured. When a server device is manually intruded, the background management system needs to be aware of it immediately, and it also needs to record whether the server has been intruded. Based on this, the server will be installed with mechanical locks to protect the security of the equipment inside the server. In addition, the detection of unpacking behavior is also the most direct and effective security measure.

At present, the commonly used detection method is: a physical switch linked to the server's lock, when the lock is opened, drives the mechanical switch to generate a trigger signal, triggers the INTEL server platform management chip, and records the unpacking event. However, the existing reporting mechanism is based on the CMOS register, which can only detect the unpacking behavior of the server when it is not powered on, and can only report the detection result once after power is turned on. During the power-on process of the server, since the CMOS register is set, reporting cannot continue. At this time, an additional dedicated trigger is required to detect the signal of the mechanical switch in order to realize the unpacking detection when the server is powered on.

However, the additional dedicated trigger has a high cost and requires an internal power supply to supply additional power to the dedicated trigger when it is stationary, which reduces the life of the internal battery. Therefore, there is an urgent need for a detection circuit that has a simple structure, low cost, and can perform unpacking detection on servers in any scenario.

Summary of the invention

The embodiment of the present application provides a circuit board, on which an unpacking detection circuit is provided, which can realize unpacking detection of a server in any scenario, and has a simple structure and low cost.

The embodiments of the present invention adopt the following technical solutions:

In a first aspect, an embodiment of the present application provides a circuit board, on which a box opening detection circuit is provided, and the box opening detection circuit includes:

Power-off detection circuit, power-on detection circuit and switch;

One end of the switch is connected to a first end of the power-on detection circuit, and the other end of the mechanical switch is grounded and connected to a second end of the power-on detection circuit;

The first end of the power-on detection circuit is connected to the first end of the power-off detection circuit, and the third end of the power-on detection circuit is connected to the The first terminal of the power-on detection circuit is connected to the second terminal of the power-off detection circuit and the internal power supply, and the fourth terminal of the power-on detection circuit is connected to the controller;

The third terminal of the power failure detection circuit is connected to the controller, and the fourth terminal of the power failure detection circuit is grounded;

The power-off detection circuit is used to generate a first trigger signal when the circuit board is in a power-off state and the switch is closed, and send the first trigger signal to the controller after the circuit board is powered on again to remind the user that an unpacking event has occurred. The power-off state is the state when the circuit board is not connected to an external power supply;

The power-on detection circuit is used to generate a second trigger signal when the unpacking circuit board is in a powered-on state and the switch is closed, and send the second trigger signal to the controller to remind the user that an unpacking event has occurred. The power-on state is the state when the circuit board is connected to an external power supply.

It can be seen that in this embodiment, by setting up a power-off detection circuit and a power-on detection circuit, the detection of abnormal unpacking of the server in any state can be achieved. In the power-off state, the power-on detection circuit is shielded; in the power-on state, the power-off detection circuit is shielded, thereby preventing interference between signals and improving the accuracy and reliability of detection. At the same time, the entire unpacking detection circuit is composed of basic components such as field effect transistors, diodes, and resistors. The overall structure is simple, the cost is low, and it is easy to implement. It can be used for server unpacking detection in various scenarios.

In a possible implementation, the power failure detection circuit includes:

A first resistor, a second resistor, a first field effect transistor, a PCH chip and a diode;

The gate of the first field effect tube is the first end of the power-off detection circuit, one end of the first resistor is the second end of the power-off detection circuit, the third pin of the PCH chip is the third end of the power-off detection circuit, and one end of the second resistor is the fourth end of the power-off detection circuit;

The source of the first field effect tube is connected to the cathode of the diode and the other end of the second resistor respectively;

The drain of the first field effect tube is respectively connected to the other end of the first resistor and the first pin of the PCH chip;

One end of the first resistor is connected to the second pin of the PCH chip;

The anode of the diode is connected to the external power supply.

In a possible implementation manner, the first pin of the PCH chip is an intruder pin, the second pin of the PCH chip is a power supply pin, and the third pin of the PCH chip is an LPC interface pin.

In a possible implementation manner, the first field effect transistor is an N-channel field effect transistor.

In a possible implementation, the power-on detection circuit includes:

a third resistor, a fourth resistor and a second field effect transistor;

One end of the third resistor is the first end of the power-on detection circuit, the source of the second field effect transistor is the second end of the power-on detection circuit, the other end of the third resistor is the third end of the power-on detection circuit, and the drain of the second field effect transistor is the fourth end of the power-on detection circuit;

One end of the third resistor is connected to the gate of the second field effect transistor;

The drain of the second field effect tube is connected to one end of the fourth resistor;

The other end of the fourth resistor is connected to the second power supply.

In a possible implementation manner, the second field effect transistor is an N-channel field effect transistor.

In a possible implementation, when the unpacking detection circuit is in a power-off state, the power-on detection circuit fails, and when the unpacking detection circuit is in a power-on state, the power-off detection circuit fails.

In a possible implementation manner, the third terminal of the power-off detection circuit is connected to the baseboard management controller via an enhanced serial peripheral interface bus.

In a possible implementation manner, the fourth terminal of the power-on detection circuit is connected to an interrupt pin of the baseboard management controller.

In a second aspect, an embodiment of the present application provides a server, which includes a chassis, and a circuit board as in the first aspect arranged in the chassis.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention.

FIG1 is a schematic diagram of a box opening detection system provided in an embodiment of the present invention;

FIG2 is a schematic diagram of the structure of a server provided in an embodiment of the present invention;

FIG3 is a schematic structural diagram of a physical linkage mechanism provided in an embodiment of the present invention;

FIG4 is a schematic diagram of the structure of another server provided in an embodiment of the present invention;

FIG5 is a schematic structural diagram of another physical linkage mechanism provided in an embodiment of the present invention;

FIG6 is a circuit block diagram of a box opening detection circuit provided in an embodiment of the present invention;

FIG7 is a schematic diagram of the structure of a box opening detection circuit provided in an embodiment of the present invention;

FIG. 8 is a schematic diagram of the operation of a circuit board provided in an embodiment of the present invention.

DETAILED DESCRIPTION

The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

The terms "first", "second", "third" and "fourth" in the specification, claims and drawings of this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

Reference to "embodiment" herein means that a particular feature, result, or characteristic described in conjunction with the embodiment may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

First, for ease of understanding, the relevant terms involved in this application are explained:

BMC, BaseBoard Management Controller, is used to run the operating system. It can perform some operations such as upgrading the machine firmware, checking the status of machine components, and powering on and off the device when the server is not turned on.

PCH, Platform Controller Hub, is Intel's integrated south bridge, used for X86 server platform status management and I/O (Input/Output) function expansion.

CMOS registers, Complementary Metal-Oxide-Semiconductor, are a group of registers inside the PCH, powered by a battery, used to latch data.

The power-off state refers to the state in which the server, circuit board and other devices are not connected to the external power supply. At this time, only the internal power supply in the circuit board of the server, circuit board and other devices supplies power to the CMOS register inside the PCH.

The power-on state refers to the state in which devices such as servers and circuit boards are connected to external power supplies.

Secondly, the circuit board provided in the embodiment of the present application can be used to perform unpacking detection on electronic devices in any situation. Specifically, as shown in Figure 1, Figure 1 shows a schematic diagram of an unpacking detection system provided in an embodiment of the present application. The system may include: an electronic device 10, a detection device, the detection device includes a circuit board 11, and the circuit board 11 is provided with an unpacking detection circuit and a controller (not shown in the figure), wherein the detection device can be arranged in the electronic device 10 or outside the electronic device 10.

Exemplarily, the electronic device may be a server, a switch cabinet, a power distribution cabinet, etc. This embodiment takes a server as an example. When the electronic device 10 is a server, the detection device is arranged in the server. The circuit board 11 in the detection device may be a mainboard in the server 10. The mainboard also includes: a central processing unit CPU, a memory bar, a south bridge chip PCH, a BMC chip, and other components.

In some implementations, the circuit board 11 may also be other circuit boards in the server 10, such as a hard disk backplane, a power backplane, a circuit board for PCIE card insertion, etc.

In this embodiment, the server may be a file server, a domain server, a database server, a mail server, a web server, a multimedia server, a communication server, a terminal server, an infrastructure server, a virtualization server, etc. The server may be a tower server, a rack server, a blade server, a high-density server, a cabinet server, a high-performance computing (HPC) server, a heterogeneous server, etc., and may be, but not limited to, an X86 architecture, a reduced instruction set computer (RISC) architecture, an advanced reduced instruction set machine (ARM) architecture, etc. The server is used to receive data transmitted by other devices, and process these data to generate new data and send them to the corresponding devices. The chassis/cabinet of the server 10 is provided with a lock for locking the server 10 to ensure the asset security of the internal components of the server, such as hard disk, CPU, memory bar, etc. It should be noted that one or more nodes can be placed in the chassis of the server, and a node is a minimum computing unit, that is, a node includes: a motherboard, a backplane and other components. The motherboard is provided with a central processing unit CPU, a memory bar, a south bridge chip PCH, a BMC chip and other components. The backplane can be a hard disk backplane, a PCIE card, a power backplane, etc. Multiple server chassis can be set in the server cabinet through U positions or slots.

In this embodiment, the circuit board 11 is provided with an unpacking detection circuit and a controller, and the unpacking detection circuit may include: a power-off detection circuit, a power-on detection circuit, and a switch. There is a physical linkage mechanism between the switch and the lock on the server 10. Specifically, when the lock is opened, the switch is driven to close. At the same time, the unpacking detection circuit sends a relevant signal to the controller 12.

Exemplarily, the circuit board 11 may be disposed in the server 10 near the lock 28, as shown in FIG. 2 . 2 shows a schematic diagram of the structure of a server when the circuit board 11 is a mainboard in the server 10. The lock 28 is arranged on the chassis cover 21 of the server 10, the mainboard 22 is arranged inside the server 10, a physical linkage mechanism 23 is arranged on the mainboard 22, and the upper surface of the physical linkage mechanism 23 is in close contact with the chassis cover 21.

Specifically, as shown in FIG3 , FIG3 shows a schematic diagram of the structure of a physical linkage mechanism 23 provided in the present embodiment. The linkage mechanism 23 includes: a housing 24, a button 25, a pressing piece 26 and a spring 27, wherein the housing 24 is hollow, and a hole 30 is provided on the upper surface, and the button 25 is provided through the hole 30, and one end of the pressing piece 26 is located in the cavity of the housing 24 and is connected to the pressing piece 26. The diameter of the pressing piece 26 is slightly larger than the diameter of the button hole 30, and the end of the pressing piece 26 not connected to the button 25 is connected to the spring 27, and a contact 29 is provided on the inner side of the upper surface of the housing 24. Thus, in the absence of external pressure, the elastic force of the spring 27 keeps the pressing piece 26 in contact with the pressing point 29, and when the button 25 is pressed by external pressure, the pressing piece 26 is separated from the contact 29 under the action of pressure.

Based on this, in this embodiment, the combination of the pressing piece 26 and the contact 29 can be regarded as a switch in the box opening detection circuit. The contact between the pressing piece 26 and the contact 29 is equivalent to the switch being closed, and the separation of the pressing piece 26 and the pressing point 29 is equivalent to the switch being opened.

In this embodiment, as shown in FIG. 2 , when the chassis cover 21 is not opened, since the upper surface of the physical linkage mechanism 23 is in close contact with the chassis cover 21, the chassis cover 21 presses the button 25 downward, so that the pressing piece 26 remains separated from the pressing point 29, and the switch is in an open state. When the chassis cover 21 is opened, the spring button 24 is reset and popped out under the action of the internal spring, and the pressing piece 26 contacts the contact 29, so that the switch is closed.

In another embodiment, as shown in FIG. 4 , the circuit board 11 can also be arranged near the lock 18. In this case, as shown in FIG. 5 , the lock 18 can include a locking mechanism 13, a pendulum 14 and a connecting mechanism 15. When the lock is opened, the locking mechanism 13 moves in a direction away from the server door 16, driving the connecting mechanism 15, so that the pendulum 14 also swings in a direction away from the server door 16. At the same time, a push rod 17 is arranged on the side of the pendulum 14 away from the server door 16. The push rod 17 is a physical linkage mechanism, one end of which is located on the side of the pendulum 14 away from the server door 16, and the other end is located on the side of the switch 19 on the circuit board 11, and the midpoint 20 is fixed on the server box, so that the push rod 14 can rotate around the midpoint 20. When the pendulum 14 swings in a direction away from the server door 16, it will contact the push rod 17 and push the push rod 17 in a direction away from the server door 16, thereby driving the push rod 17 to rotate, so that the other end of the push rod 17 presses the switch 19 to close the switch.

In this embodiment, the controller 12 can be a BMC or other CPLD, FPGA, MCU, etc., wherein the BMC can perform operations such as upgrading the machine firmware, checking the status of machine components, powering on and off the device, etc. when the server 10 is not turned on.

In this embodiment, the controller takes the BMC as an example. When the server 10 is in a power-off state (not connected to an external power source), at this time, if the lock is opened, the switch is closed under the drive of the physical linkage mechanism, driving the power-off detection circuit to generate a first trigger signal. Since the BMC does not work when the server 10 is powered off, the power-off detection circuit needs to be powered on again after the server 10 and the BMC starts working, so that the BMC can receive the first trigger signal to remind the user that an unpacking event has occurred.

When the server 10 is in a powered-on state (connected to an external power supply) and the BMC is in a working state, at this time, if the lock is opened, the switch is closed under the drive of the physical linkage mechanism, driving the power-on detection circuit to generate a second trigger signal, and sending the second trigger signal to the BMC in real time to remind the user that an unpacking event has occurred.

In addition, the detection device proposed in the implementation mode of the present application can also be applied to other devices with boxes or locks, such as: opening detection of safes, doors, windows, etc., and the present application does not impose any restrictions on this.

The following will take the scenario of server unpacking detection as an example to explain in detail the circuit board provided in the embodiment of the present application. In this case, the controller 12 takes the BMC as an example. At the same time, the circuit board 11 is set in the chassis of the server 10 and is the mainboard of the server. Based on this, the power-off state refers to the state in which the server 10 is not connected to the external power supply, and then the circuit board 11 set in the server 10 is also not connected to the external power supply; similarly, the power-on state refers to the state in which the server 10 is connected to the external power supply, and then the circuit board 11 set in the server 10 is also synchronously connected to the external power supply.

In this embodiment, a box opening detection circuit is provided on the circuit board 11. Referring to FIG. 6, FIG. 6 is a circuit block diagram of a box opening detection circuit provided in an embodiment of the present application. The box opening detection circuit may include: a power-off detection circuit 100, a power-on detection circuit 200, and a switch 300. Specifically, one end of the switch 300 is connected to a first end 601 of the power-on detection circuit 200, and the other end of the switch 300 is grounded and connected to a second end 602 of the power-on detection circuit 200. The first end 601 of the power-on detection circuit 200 is connected to a first end 701 of the power-off detection circuit 100, a fourth end 604 of the power-on detection circuit is connected to the BMC 400, and a third end 603 of the power-on detection circuit 200 is respectively connected to a second end 702 of the power-off detection circuit 100 and a positive electrode of an internal power supply 500. The internal power supply may be a backup power supply inside the server, such as a 3.3V battery. When the server/circuit board is not connected to an external power supply, the 3.3V battery may be used to power chips such as the PCH on the circuit board. The third terminal 703 of the power failure detection circuit 100 is connected to the BMC 400 , and the fourth terminal 704 of the power failure detection circuit 100 is grounded.

In this embodiment, the power-off detection circuit 100 is used to generate a first trigger signal when the server/circuit board is in a power-off state, that is, the server/circuit board is not connected to an external power supply, and the switch 300 is closed. After the circuit board is powered on again, the BMC starts working and receives the first trigger signal to remind the user that an unpacking event has occurred.

Exemplarily, as shown in FIG. 7, FIG. 7 is a schematic diagram of the structure of a box opening detection circuit provided in an embodiment of the present application, in which the power-off detection circuit 100 may include: a first resistor 101, a second resistor 102, a first field effect transistor 103, a PCH chip 104 and a diode 105. Among them, the resistance value of the first resistor 101 can be 1MΩ-2MΩ, one end of the first resistor 101 is the second end 702 of the power-off detection circuit 100, and is connected to the second pin of the PCH chip 104 and the positive electrode of the internal power supply 500, and the second pin of the PCH chip 104 can be a power supply pin. The other end of the first resistor 101 is connected to the drain of the first field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transi stor, MOSFET) 103. The resistance value of the second resistor 102 can be 1KΩ-10KΩ, one end of the second resistor 102 is the fourth end 704 of the power-off detection circuit 100, and the other end of the second resistor 102 is connected to the source of the first field effect transistor 103. The first field effect transistor 103 can be an N-channel field effect transistor, the gate of which is connected to the first end 701 of the power-off detection circuit 100 and the first end 601 of the power-on detection circuit 200, the source is connected to the cathode of the diode 105, and the drain is connected to the first pin of the PCH chip 104, and the first pin of the PCH chip 104 can be an intruder pin. The intruder pin is associated with the CMOS register in the PCH chip 104. When the level of the intruder pin changes, the value in the CMOS register will change from 0 to 1 to record this level change event. The third pin of the PCH chip 104 is the third end 703 of the power-off detection circuit 100 and is connected to the BMC 400. The third pin of the PCH chip 104 can be an LPC (LOW PIN COUNT) interface pin and is connected to the BMC 400 through an Enhanced Serial Peripheral Interface (ESPI) bus, and is used to transmit the information latched in the CMOS register to the BMC 400. The anode of the diode 105 is connected to the external power supply 106, and the external power supply 106 can be the power supply provided when the server is connected to the external power supply and powered on, such as the driving power supply of STBY_3V3.

As can be seen from the above, in this embodiment, the conduction of the first field effect transistor 103 is controlled by the switch 300, which then changes the level of the intruder pin of the PCH chip 104, and then generates a first trigger signal and locks it in the CMOS register. However, the CMOS register has no register address and cannot be directly accessed. The PCH chip can only actively report the information in the CMOS register once when the server is started. Therefore, after the server/circuit board is powered on, the unpacking status of the server can no longer be reported through the power-off detection circuit 100. In this regard, in this embodiment, a power-on detection circuit 200 is provided. The power-on detection circuit 200 is used to connect the server/circuit board to an external power supply and is in a powered-on state. If the switch 300 is closed, a second trigger signal is generated and the second trigger signal is sent to the BMC400 to remind the user of an unpacking event.

Exemplarily, as shown in FIG7 , the power-on detection circuit 200 may include: a third resistor 201, a fourth resistor 202, and a second field effect transistor 203. The resistance of the third resistor 201 may be 1MΩ-2MΩ, one end of the third resistor 201 is the first end 601 of the power-on detection circuit 200, and is connected to the gate of the second field effect transistor 203 and one end of the switch 300, and the other end of the third resistor 201 is the third end 603 of the power-on detection circuit 200 and is connected to the positive electrode of the internal power supply 500. The resistance of the fourth resistor 202 may be 1KΩ-10KΩ, one end of the fourth resistor 202 is connected to the drain of the second field effect transistor 203, and the other end of the fourth resistor 202 is connected to the external power supply 106. The second field effect transistor 203 may be an N-channel field effect transistor, whose source is the second end 602 of the power-on detection circuit 200 , connected to the other end of the switch 300 and grounded, and whose drain is the fourth end 604 of the power-on detection circuit 200 , connected to the BMC 400 .

The working principle of the circuit board provided by the embodiment of the application will be described below in conjunction with FIG. 7 and FIG. 8. Specifically, FIG. 8 is a schematic diagram of the working of a circuit board provided by the embodiment of the present application, wherein the first behavior is the working principle of the circuit board in the power-off state, that is, the external power supply 106 is not connected, and the circuit board is only powered by the internal power supply 500. Specifically, when the server is not connected to an external power supply, that is, the circuit board is in a power-off state, only the internal power supply 500, that is, the 3.3V backup battery drives the PCH chip in the circuit board to be in a working state. Since the server is not connected to an external power supply, at this time, the STBY voltage output by the external power supply 106 is 0, and the potential of the drain and source of the second field effect tube 203 is 0, so that the second field effect tube 203 cannot be triggered by the switch 300, and then the power-on detection circuit 200 fails. In this state, when the server unpacking behavior occurs, the lock on the server is opened, driving the switch 300 to close, driving the first field effect tube 103 to generate a first trigger signal, and the first trigger signal is stored in the CMOS register in the PCH chip 104 in the power-off state. After the server is powered on and the BMC starts working, the PCH chip will send the first trigger signal latched in the CMOS register to the BMC when the server starts, and then remind the user that the server has experienced abnormal unpacking behavior when it is not powered on.

Specifically, when the switch 300 is closed, the loop where the third resistor 201 is located is turned on, and since the resistance of the third resistor 201 is relatively large, the current flowing through the third resistor 201 is very small, approximately 0, and therefore, the voltage across the third resistor 201 can be regarded as the voltage of the internal power supply 500, which is 3.3V. At this time, the gate voltage V _G1 of the first field effect transistor 103 is 3.3V, the source voltage V _S1 is 0, and then the gate-source voltage V _GS1 of the first field effect transistor 103 is 3.3V, and the turn-on voltage V _T1 of the first field effect transistor 103 is 3V, then V _GS1 >V _T1 , the first field effect transistor 103 is turned on, and the loop where the first resistor 101 is located is turned on. Similarly, the resistance of the first resistor 101 is relatively large, and therefore, the current flowing through the first resistor 101 is very small, approximately 0, and the voltage across the first resistor 101 can be regarded as 3.3V, which is a high level, and the high level signal is the first trigger signal. At this time, the intruder pin of the PHC chip 104 inputs the first trigger signal and saves it to the register CMOS inside the PCH chip to record this unpacking event. When the server is powered on, the BMC starts up. At this time, the PCH chip 104 sends the first trigger signal latched in the CMOS register to the server through the ESPI bus. The signal is sent to the BMC to remind the user that an unpacking event has occurred during power failure. In this embodiment, due to the mechanism that the PCH chip will only report once when the server is started, and the characteristics that the COMS register has no register address and cannot be actively accessed, after the server is powered on, the power-off detection circuit 100 will not be able to implement the unpacking detection report. In this regard, in the circuit board provided in this application, after the server is powered on, the power-on detection circuit will be responsible for the unpacking detection and reporting processing of the server.

In this embodiment, the second line of FIG. 8 is the working principle of the circuit board when the power-on state is on, that is, the external power supply 106 is connected, and the circuit board is powered by the internal power supply 500 and the external power supply 106 at the same time. Specifically, when the server is connected to the external power supply, that is, the circuit board is in the power-on state, the STBY voltage output by the external power supply 106 is 3.3V, and the diode 105 is turned on, so that the source voltage V _S2 of the first field effect tube 103 is 3.3V. At this time, if the box opening event occurs, the switch 300 is closed, and the voltage across the third resistor 201 can be regarded as the voltage of the internal power supply 500, which is 3.3V. At this time, the gate voltage V _G2 of the first field effect tube 103 is 3.3V, and then the gate-source voltage V _GS2 of the first field effect tube 103 is 0V, so that the first field effect tube 103 cannot be triggered by the switch 300, and then the power-off detection circuit 100 fails. In this state, when the server is unpacked, the lock on the server is opened, driving the switch 300 to close, driving the second field effect transistor 203 to generate a second trigger signal. At the same time, the second field effect transistor 203 sends the generated second trigger signal to the BMC in real time, thereby reminding the user that the server has abnormal unpacking behavior.

Specifically, when the switch 300 is closed, the loop where the third resistor 201 is located is turned on, and since the resistance of the third resistor 201 is relatively large, the current flowing through the third resistor 201 is very small, approximately 0, and therefore, the voltages across the third resistor 201 can be regarded as the voltage of the internal power supply 500, which is 3.3V. Thus, the gate voltage V _G3 of the second field effect transistor 203 is 3.3V, and at the same time, the source voltage V _S3 of the second field effect transistor 203 is 0V, and then the gate-source voltage V _GS3 of the second field effect transistor 203 is 3.3V. The turn-on voltage V _T2 of the second field effect transistor 203 is 3V, so at this time V _GS3 >V _T2 , and the second field effect transistor 203 is turned on. The second field effect transistor 203 is connected to the interrupt pin of the BMC, and therefore, the conduction of the second field effect transistor will trigger an interrupt event of the BMC, and the interrupt event is the second trigger signal. After receiving the interrupt event, the BMC can remind the user that the server has abnormal unpacking behavior, so as to detect and report the unpacking behavior in the first time.

Specifically, in this embodiment, after receiving the first trigger signal or the second trigger signal, the BMC can generate a text prompt message indicating that the server has been unpacked, and the text prompt message pops up on the display device of the server administrator through a system pop-up window to remind the server administrator that the server has been unpacked. At the same time, the text prompt message can also be converted into voice and then played synchronously through an audio playback device to further improve the reminder efficiency.

In summary, the implementation method of the present application realizes the detection of abnormal unpacking of the server in any state by setting up a power-off detection circuit and a power-on detection circuit. In the power-off state, the power-on detection circuit is shielded; in the power-on state, the power-off detection circuit is shielded, thereby preventing interference between signals and improving the accuracy and reliability of detection. At the same time, the entire unpacking detection circuit is composed of basic components such as field effect transistors, diodes, resistors, etc. The overall structure is simple, the cost is low, and it is easy to implement, and it can be used for server unpacking detection in various scenarios.

It should be understood that the processor mentioned in the embodiments of the present application may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or crystals. Management logic devices, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

It should also be understood that the memory mentioned in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM) and direct memory bus random access memory (DRRAM).

It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, the memory (storage module) is integrated in the processor.

It should be noted that, for the above-mentioned various method implementations, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the implementations described in the specification are all optional implementations, and the actions and modules involved are not necessarily required by this application.

In the above-mentioned embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

In the several embodiments provided in this application, it should be understood that the disclosed device can be implemented in other ways. For example, the device implementation described above is only schematic, such as the division of units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit may be implemented in the form of hardware or in the form of software program modules.

If the integrated unit is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application is essentially or partly contributed to the prior art or all or part of the technical solution can be in the form of a software product. It is embodied that the computer software product is stored in a memory and includes a number of instructions for enabling a computer device (which may be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the methods of various implementation methods of the present application.

Those skilled in the art will appreciate that all or part of the steps in the various methods of the above embodiments can be completed by instructing the relevant hardware through a program, and the program can be stored in a computer-readable memory. The memory may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, etc.

The above is a detailed introduction to the implementation methods of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above implementation methods is only used to help understand the method and core idea of the present application. At the same time, for general technical personnel in this field, according to the idea of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims (10)

A circuit board, characterized in that a box opening detection circuit is provided on the circuit board, and the box opening detection circuit comprises: Power-off detection circuit, power-on detection circuit and switch; One end of the switch is connected to a first end of the power-on detection circuit, and the other end of the mechanical switch is grounded and connected to a second end of the power-on detection circuit; The first end of the power-on detection circuit is connected to the first end of the power-off detection circuit, the third end of the power-on detection circuit is connected to the second end of the power-off detection circuit and the internal power supply respectively, and the fourth end of the power-on detection circuit is used to connect to the controller; The third terminal of the power failure detection circuit is connected to the controller, and the fourth terminal of the power failure detection circuit is grounded; The power-off detection circuit is used to generate a first trigger signal when the circuit board is in a power-off state and the switch is closed, and send the first trigger signal to the controller after the circuit board is powered on again to remind the user that an unpacking event has occurred, and the power-off state is a state when the circuit board is not connected to an external power supply; The power-on detection circuit is used to generate a second trigger signal when the unpacking circuit board is in a powered-on state and the switch is closed, and send the second trigger signal to the controller to remind the user of the unpacking event. The power-on state is the state when the circuit board is connected to the external power supply. The circuit board according to claim 1, characterized in that the power failure detection circuit comprises: A first resistor, a second resistor, a first field effect transistor, a PCH chip and a diode; The gate of the first field effect transistor is the first end of the power-off detection circuit, one end of the first resistor is the second end of the power-off detection circuit, the third pin of the PCH chip is the third end of the power-off detection circuit, and one end of the second resistor is the fourth end of the power-off detection circuit; The source of the first field effect transistor is connected to the cathode of the diode and the other end of the second resistor respectively; The drain of the first field effect transistor is connected to the other end of the first resistor and the first pin of the PCH chip respectively; One end of the first resistor is connected to the second pin of the PCH chip; The anode of the diode is connected to an external power source. The circuit board according to claim 2, characterized in that The first pin of the PCH chip is an intruder pin; The second pin of the PCH chip is a power supply pin; The third pin of the PCH chip is an LPC interface pin. The circuit board according to claim 2 or 3, characterized in that The first field effect transistor is an N-channel field effect transistor. The circuit board according to claim 1, characterized in that the power-on detection circuit comprises: a third resistor, a fourth resistor and a second field effect transistor; One end of the third resistor is the first end of the power-on detection circuit, the source of the second field effect transistor is the second end of the power-on detection circuit, the other end of the third resistor is the third end of the power-on detection circuit, and the drain of the second field effect transistor is the fourth end of the power-on detection circuit; One end of the third resistor is connected to the gate of the second field effect transistor; The drain of the second field effect transistor is connected to one end of the fourth resistor; The other end of the fourth resistor is connected to the second power supply. The circuit board according to claim 5, characterized in that The second field effect transistor is an N-channel field effect transistor. The circuit board according to claim 2, characterized in that When the unpacking detection circuit is in a power-off state, the power-on detection circuit fails, and when the unpacking detection circuit is in a power-on state, the power-off detection circuit fails. The circuit board according to claim 1, characterized in that The third terminal of the power-off detection circuit is connected to the baseboard management controller via an enhanced serial peripheral interface bus. The circuit board according to claim 1, characterized in that The fourth terminal of the power-on detection circuit is connected to the interrupt pin of the baseboard management controller. A server, characterized in that the server comprises a chassis, and a circuit board as described in any one of claims 1 to 9 arranged in the chassis.