WO2024143223A1 - Product-sum operator - Google Patents

Abstract

Provided is a product-sum operator having low energy consumption and high operation accuracy.　The product-sum operator 1 is constituted of: a resistive digital/analog conversion unit 11 which includes a plurality of RDACs and converts digital values of respective elements of an input vector into analog voltages and outputs the analog voltages; a capacitive digital/analog conversion unit 12 which includes a plurality of CDACs, receives the analog voltages output from the resistive digital/analog conversion unit 11, and has capacity ratios that correspond to digital values of respective elements of a matrix and are set between input and output terminals and between output terminals and the ground; a successive comparison-type analog/digital conversion unit 13 which includes a plurality of successive comparison-type ADCs, converts a voltage of a node commonly connected to respective output terminals of the capacitive digital/analog conversion unit 12 into a digital value, and outputs the digital value; and a current consumption control unit 14 which controls current consumption of the resistive digital/analog conversion unit 11, wherein an output from the successive comparison-type analog/digital conversion unit 13 is set as an output vector.

Description

Multiply-and-accumulate unit

The present invention relates to a multiply-and-accumulate unit. More specifically, the present invention relates to a multiply-and-accumulate unit using a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC).

Digital calculations are based on multiply-and-accumulate operations. Furthermore, AI processors, which have been the subject of fierce competition in recent years, use neuro-calculation (see, for example, Non-Patent Document 1). Figure 8 is a conceptual diagram of neuro-calculation in an AI processor. Note that neuro-calculation requires many layers, but Figure 8 only shows the basic input layer, hidden layer, and output layer.

As shown in Fig. 8, product-sum operations are performed between each layer in neuro-operation. As an example, the operation between the input layer and the hidden layer is shown below. If the input layer vector is X and the connection coefficient matrix is W ⁽⁰⁾ , the hidden layer vector Y is expressed by the following formula 1.

When one element _yj of the output layer in the above formula 1 is focused on, it is expressed by the following formula 2, and it can be seen that a product-sum operation process is performed.

In a neuroprocessor, when the number of nodes in each layer is N, ^N2 product-sum operations are required in each layer. For example, in image recognition with 100 x 100 pixels, N = ¹⁰⁴ , ^N2 = ¹⁰⁸ , and 100 million product-sum operations are required per layer. For this reason, it is an urgent task for neuroprocessors to increase the operation speed while reducing the energy consumption of operations.

Figure 9 shows the configuration of a conventional multiply-accumulate calculator using digital circuits. As shown in Figure 9, in a typical conventional digital multiply-accumulate calculator, input X is input to each flip-flop (F/F) via a bus. In addition, in the multiply-accumulate calculator shown in Figure 9, multipliers (MUL) are arranged two-dimensionally, and each element of input X and each element of input W are input to each multiplier, and each element of input X is multiplied by each element of input W in the multiplier. The multiplication outputs are then input sequentially to adders (ADD) via a bus, where cumulative addition is performed.

On the other hand, the conventional digital multiply-and-accumulate unit mentioned above has problems with the calculation speed and energy consumption of the multiplier, and the calculation speed and energy consumption of the cumulative adder. In particular, the cumulative adder has issues with its slow calculation speed and high energy consumption because the output of the multiplier is sent to the cumulative adder sequentially via a bus.

In response to this, the present inventor has proposed a technique for reducing energy consumption and increasing the calculation speed by performing calculations using analog circuits (see Patent Document 1). FIG. 10 is a block diagram showing the configuration of the product-sum calculator described in Patent Document 1. The product-sum calculator 100 shown in FIG. 10 is provided with a voltage output digital-to-analog conversion unit 101 having multiple DACs, a capacitive digital-to-analog conversion unit 102 having multiple capacitive digital-to-analog converters (CDACs), and an analog-to-digital conversion unit 103 having multiple ADCs.

In this multiply-and-accumulate calculator 100, for example, two input digital value strings are input, one of which is converted to a voltage string using a resistive digital-to-analog converter (RDAC), and the other input is input to a capacitive digital-to-analog converter (CDAC). Multiplication is then performed using the CDAC, which uses the voltage as an analog input, and simultaneous addition is performed by connecting the outputs of multiple CDACs in common, and the voltage at this node is analog-to-digital converted in an ADC to obtain a digital output value.

International Publication No. 2021/171880

Kodai Ueyoshi and 4 others, "FPGA implementation of a scalable and highly parallel architecture for restricted Boltzmann machines," Circuits and Systems, 2016, vol.7, no.9, p.2132-2141

The multiply-and-accumulate calculator described in Patent Document 1 operates with lower energy and at higher speeds than a multiply-and-accumulate calculator using a digital calculator, but because a constant current flows steadily through the RDAC, it does not necessarily operate with the minimum energy consumption. In addition, conventional multiply-and-accumulate calculators using this analog circuit have the problem that energy consumption increases when analog-to-digital conversion is performed at a resolution higher than that required by the ADC, and that the parasitic capacitance at the output end of the CDAC attenuates the voltage generated at the output end, which causes a gain error in the ADC and degrades the calculation accuracy.

The present invention aims to provide a multiply-and-accumulate calculator that consumes little energy and has high calculation accuracy.

The inventor conducted research to solve the problems described above, and came to the following findings. First, the inventor discovered that energy consumption can be reduced by providing an RDAC with a current consumption control unit that controls current consumption to control the period during which the output voltage is generated, or by providing a successive approximation type ADC with a conversion count control unit that controls the number of successive approximations to set the number of successive approximations according to the required resolution. In addition, the inventor discovered that calculation accuracy can be reduced by providing an ADC with a reference voltage control unit to control the reference voltage, or by providing a coefficient control unit and a multiplier to multiply the ADC conversion value by a coefficient, thereby suppressing the occurrence of gain errors and improving calculation accuracy. Based on these findings, the inventor arrived at the present invention.

That is, the product-sum calculator according to the present invention comprises a resistive digital-to-analog conversion unit which includes a plurality of resistive digital-to-analog converters and converts the digital value of each element of an input vector into an analog voltage and outputs the analog voltage; a capacitive digital-to-analog conversion unit which includes a plurality of capacitive digital-to-analog converters and receives the analog voltage output from the resistive digital-to-analog conversion unit and sets a capacitance ratio between the input/output terminals and between the output terminal and ground corresponding to the digital value of each element of a matrix; a successive approximation type analog-to-digital conversion unit which includes a plurality of successive approximation type analog-to-digital converters and converts the voltage of a node commonly connected to each output terminal of the capacitive digital-to-analog conversion unit into a digital value and outputs the digital value; and a current consumption control unit which controls the current consumption of the resistive digital-to-analog conversion unit, and the output from the successive approximation type analog-to-digital conversion unit is an output vector.
The current consumption control section may control, for example, a generation period of an analog voltage output from the resistive digital-to-analog converter.
The product-sum calculator of the present invention may further include a conversion count control section that controls the number of successive approximations in the successive approximation type analog-to-digital conversion section.
The product-sum calculator of the present invention may further include a reference voltage control unit that controls a reference voltage of the successive approximation type analog-digital conversion unit. In this case, a capacitor that samples an input signal may be connected as the reference voltage control unit to a connection unit between the capacitive digital-to-analog converter and the input end of a comparator of the successive approximation type analog-digital conversion unit, and the capacitance value of the capacitor that samples the input signal may be controlled.
The product-sum calculator of the present invention may further include an adder that adds an offset value to an output from the successive approximation type analog-to-digital converter, and an offset control section that controls the offset value.
The product-sum calculator of the present invention may further include a multiplier that multiplies an output from the successive approximation type analog-to-digital converter by a coefficient, and a coefficient control section that controls the coefficient.

　According to the present invention, it is possible to reduce power consumption and improve calculation accuracy compared to conventional multiply-and-accumulate units using analog circuits, thereby realizing a multiply-and-accumulate unit that operates with less energy and is capable of highly accurate calculations.

FIG. 2 is a diagram illustrating a configuration of a multiply-accumulate calculator according to the first embodiment of the present invention. 11A to 11C are waveform diagrams showing a method for reducing the current consumption of each RDAC in the resistive digital-to-analog conversion unit 11. FIG. 1A is a circuit diagram showing the configuration of a successive approximation type ADC, and FIG. 1B is a conceptual diagram showing a method of reducing power consumption thereof. 3 is a circuit diagram showing an example of the configuration of a reference voltage control unit 16. FIG. 5 is a circuit diagram showing a configuration example that makes it possible to control the capacitance value of a capacitance βC shown in FIG. 4. FIG. 13 is a diagram illustrating a configuration of a multiply-add calculator according to a second embodiment of the present invention. 11A and 11B are characteristic diagrams showing degradation of calculation accuracy and compensation therefor. FIG. 1 is a conceptual diagram of neuro-computation in an AI processor. FIG. 1 is a block diagram showing a configuration of a conventional multiply-accumulate calculator using a digital circuit. FIG. 1 is a diagram showing a configuration of a multiply-add calculator described in Patent Document 1.

Below, the embodiment of the present invention will be described in detail with reference to the attached drawings. Note that the present invention is not limited to the embodiment described below.

First Embodiment
First, a multiply-accumulate calculator according to a first embodiment of the present invention will be described. Fig. 1 is a diagram showing the configuration of the multiply-accumulate calculator of this embodiment. As shown in Fig. 1, the multiply-accumulate calculator 1 of this embodiment is provided with a resistive digital-to-analog conversion unit 11 having a plurality of RDACs, a capacitive digital-to-analog conversion unit 12 having a plurality of CDACs, a successive approximation type analog-to-digital conversion unit 13 having a plurality of successive approximation type ADCs, and a current consumption control unit 14 that controls the current consumption of each RDAC of the resistive digital-to-analog conversion unit 11.

In addition, the product-sum calculator 1 of this embodiment is provided with a conversion count control unit 15 that controls the number of successive approximation operations of the successive approximation ADC, a reference voltage control unit 16 that controls the reference voltage of the successive approximation ADC, a multiplier 17 that multiplies the output of the successive approximation ADC by a coefficient, and a coefficient control unit 18 that controls the coefficient, as necessary.

[Resistive digital-to-analog conversion section 11]
The resistive digital-to-analog conversion unit 11 is composed of multiple RDACs. A vector X, each of whose elements is a multiple digital value, is input to each RDAC of the digital-to-analog conversion unit 11 via a bus. Then, in each RDAC, the digital value of each element of the vector X is converted to an analog voltage and output.

[Capacitive digital-to-analog conversion section 12]
The capacitive digital-analog conversion unit 12 is composed of a plurality of CDACs, each of which is arranged two-dimensionally. The analog voltage (output voltage) output from the resistive digital-analog conversion unit 11 and a matrix W having a plurality of digital values as elements are input to each CDAC of the capacitive digital-analog conversion unit 12. Then, a capacitance ratio corresponding to the digital value of each element of the matrix W is set between the input/output terminals and between the output terminal and ground by each CDAC.

[Successive approximation type analog-to-digital conversion section 13]
The successive approximation type analog-digital conversion unit 13 is composed of a plurality of successive approximation type ADCs. A voltage of a node commonly connected to each output terminal of the capacitive digital-analog conversion unit 12 is input to this successive approximation type analog-digital conversion unit 13, and is converted into a digital value by each successive approximation type ADC and output.

[Current consumption control unit 14]
The current consumption control unit 14 controls the current consumption of each RDAC in the resistive digital-analog conversion unit 11. The method of controlling the current consumption is not particularly limited, but for example, the current consumption of each RDAC can be controlled by adjusting the generation period of the analog voltage (output voltage) output from the resistive digital-analog converter 11.

2A to 2C are waveform diagrams showing a method for reducing the current consumption of each RDAC in the resistive digital-to-analog conversion unit 11, and show the state when the input data of the RDAC is switched. As shown in FIG. 2A, during the reset period T _RST of the CDAC, the voltage of the common output terminal of the CDAC becomes zero, and when a signal is input to the RDAC after the reset is released, a current flows through the RDAC and the voltage of the common output terminal of the CDAC rises and converges toward the final value. Since the time T ₁ is determined by the normal operation clock period, the current flowing through the RDAC continues to flow during this period as shown in FIG. 2B.

On the other hand, since the response is a step response of an RC circuit, if the set voltage is V _s and the time constant is τ, then the error voltage V _e can be expressed by the following formula 3.

From the above formula 3, it can be seen that if the time t is set to about 6τ, the error can be reduced to 1/2 of the 8-bit accuracy. This settling time is _T2 . If the ADC samples the signal at time _T2 , there is no need to generate a voltage at the common output terminal of the CDAC thereafter. Therefore, as shown in FIG. 2C, if the current of the RDAC is cut off when the settling time reaches _T2 , the current consumption of the RDAC can be reduced. In this case, the simplest current cut-off method in the RDAC is to select all input terminals to be grounded.

In this way, by providing a current consumption control unit 14 that controls the current consumption of each RDAC in the resistive digital-to-analog conversion unit 11, the power consumption of the multiply-and-accumulate unit 1 can be reduced.

[Conversion count control unit 15]
The conversion count control unit 15 controls the number of successive approximations in the successive approximation type analog-digital conversion unit 13. Fig. 3A is a circuit diagram showing the configuration of the successive approximation type ADC of the successive approximation type analog-digital conversion unit 13, and Fig. 3B is a conceptual diagram showing a method of reducing power consumption. As shown in Fig. 3A, the successive approximation type analog-digital conversion unit 13 is composed of a binary-weighted capacitance array C, a switch S for selecting a voltage to be applied to each capacitance from a ground potential or a reference voltage, a comparator for comparing voltages, and an SAR logic for controlling the successive approximation.

As shown in FIG. 3B, in the successive approximation type analog-digital conversion unit 13, the shift register basically sequentially selects the switches S ₁ to S ₅ in synchronization with the clock, and the voltage selected by the switch is determined according to the output state of the comparator. For this reason, the number of clocks according to the resolution is input, and the energy consumption is proportional to the number of clocks. On the other hand, in an AI processor, the resolution of the sum-of-products operation is not necessarily constant, and it is generally said that high resolution is required in a layer close to the input, but low resolution is sufficient in a layer close to the output. Therefore, the conversion count control unit 15 controls the number of successive approximations of the successive approximation type ADC so that it is high at high resolution and low at low resolution, thereby reducing the power consumption of the sum-of-products operation unit 1.

[Reference voltage control unit 16]
The reference voltage control unit 16 controls the reference voltage of each successive approximation type ADC in the successive approximation type analog-digital conversion unit 13 so that the gain error of the ADC is minimized. Fig. 4 is a circuit diagram showing an example of the configuration of the reference voltage control unit 16. In addition to a method of directly controlling the reference voltage itself of the successive approximation type analog-digital conversion unit 13, the reference voltage can also be controlled by connecting a capacitance βC (capacitance with a capacitance ratio β) that samples an input signal as the reference voltage control unit 16 to a connection part of the input end of a binary-weighted capacitive digital-to-analog converter (DAC) and a comparator 21 that are provided in the successive approximation type analog-digital conversion unit 13 and generate a voltage difference between an input signal and a comparison voltage, as shown in Fig. 4.

4 is adopted, first, the switch _S10 is closed, and the input signal V _inp or the input signal V _inn is selected by the switches S ₁₁ , S ₁₂ ... S _n+10 of each capacitance of the capacitive DAC, thereby sampling the input signal. Next, the switch _S10 is opened, and the capacitance C/2 of the capacitive DAC is connected to the input signal V _RP or the input signal V _RN , and the remaining capacitances C/4 ... C/2 ^N-1 are connected to the ground GND. In this case, the potential difference (Va - Vb) at the input terminals of the comparator 21 when performing the most significant bit (MSB) comparison is expressed by the following formula 4.

As a result, the reference voltage is reduced to 1/(1+β), and the gain of the ADC can be increased to reduce the gain error. Furthermore, by providing a reference voltage control unit 16 with such a configuration, the voltage generated at the output terminal due to the parasitic capacitance of the output terminal of the CDAC is attenuated without increasing power consumption, thereby reducing the calculation error that occurs as a result.

Here, the capacitance ratio β is required to be accurate. FIG. 5 is a circuit diagram showing an example of a configuration that makes it possible to control the capacitance value of the capacitance βC shown in FIG. 4. For example, the reference voltage control unit 16 is provided with a capacitance bank including a plurality of binary-weighted capacitances (βC/2 to C/64) and a plurality of switches (S ₂₁ to S ₂₆ ) as shown in FIG. 5, and the switches S ₂₁ to S ₂₆ are controlled by a switch control signal, thereby minimizing the gain error of the ADC. Note that FIG. 5 shows a configuration in which weighting is performed in binary, but the present invention is not limited to this configuration. By providing such a reference voltage control unit 16, the reference voltage can be controlled and the calculation accuracy of the product-sum calculator 1 can be improved.

[Multiplier 17, coefficient control unit 18]
The multiplier 17 multiplies the output from the successive approximation type analog-to-digital conversion unit 13 by a coefficient, and the coefficient control unit 18 controls the coefficient used in the multiplier 17. By multiplying the output by the coefficient generated by the coefficient control unit 18 using the multiplier 17, it is possible to reduce the gain error of the calculation and improve the calculation accuracy of the product-sum calculator 1.

Note that the comparison count control unit 15, reference voltage control unit 16, multiplier 17, and coefficient control unit 18 described above are not all required, and the conversion count control unit 15 may be omitted in some cases. Also, it is sufficient if either the reference voltage control unit 16 or the multiplier 17 and coefficient control unit 18 are provided.

As described above in detail, the multiply-and-accumulate calculator of this embodiment controls the current consumption of the resistive DAC by the current consumption control unit, and therefore can reduce power consumption compared to conventional multiply-and-accumulate calculators using analog circuits. In addition, by providing a reference voltage control unit and/or a multiplier and a coefficient control unit, etc. to reduce gain error, it is possible to improve the calculation accuracy compared to conventional multiply-and-accumulate calculators using analog circuits. As a result, according to the present invention, it is possible to realize a multiply-and-accumulate calculator that operates with less energy and is capable of highly accurate calculations.

Second Embodiment
Next, a multiply-accumulate calculator according to a second embodiment of the present invention will be described. Fig. 6 is a diagram showing the configuration of the multiply-accumulate calculator of this embodiment. In Fig. 6, the same components as those in the multiply-accumulate calculator 1 shown in Fig. 1 are given the same reference numerals, and detailed description of those components will be omitted in this embodiment.

As shown in FIG. 6, the product-sum calculator 10 of this embodiment includes a resistive digital-to-analog converter 11, a capacitive digital-to-analog converter 12, a successive approximation type analog-to-digital converter 13, a current consumption controller 14, a conversion count controller 15, a reference voltage controller 16, a multiplier 17, and a coefficient controller 18, as well as an adder 19 and an offset controller 20 that compensate for the offset of the successive approximation type ADC.

[Adder 19/Offset Control Unit 20]
The adder 19 adds an arbitrary value to the output value from the successive approximation type analog-digital conversion section 13 to perform offset compensation, and the offset control section 20 controls the value added by the adder 19 .

7 is a characteristic diagram showing the deterioration of calculation accuracy and its compensation, and shows the output value normalized by the full-scale value of the ADC with respect to the ideal output voltage of the CDAC. As shown in FIG. 7, ideally, if the full-scale voltage of the RDAC is _VFS and this voltage is used as the reference voltage of the ADC, the normalized output of the ADC will be 1, but in reality, the offset error _eoff and the gain will be α- _eoff , which is smaller than 1. This is because a parasitic capacitance is added to the common output terminal of the CDAC by wiring, etc., and the voltage of the common output terminal is capacitively divided. The deviation of the normalized output from 1 becomes a calculation error, so this needs to be corrected.

Therefore, in the product-sum calculator 10 of this embodiment, first, the offset control section 20 detects the offset error e _off , and the adder 19 performs offset compensation by adding the offset error e _off to the output value from each successive approximation type ADC of the successive approximation type analog-digital conversion section 13. Next, the gain error is corrected. Methods for correcting the gain error include a method of providing a reference voltage control section 16 to control the reference voltage of the comparison type ADC, and a method of providing a multiplier 17 and a coefficient control section 18, and multiplying the output value that has been offset compensated by the adder 19 and offset control section 20 by 1/(α-e _off ) as a coefficient using the multiplier 17.

In the sum-of-products calculator of this embodiment, offset compensation and gain error correction are performed on the output from the successive approximation type analog-digital conversion unit, so the accuracy of the sum-of-products calculator can be improved. Note that the configuration and effects of this embodiment other than those described above are the same as those of the first embodiment described above.

The present invention can also have the following configurations.
[1]
a resistive digital-to-analog conversion unit including a plurality of resistive digital-to-analog converters, which converts the digital value of each element of an input vector into an analog voltage and outputs the analog voltage;
a capacitive digital-to-analog conversion unit including a plurality of capacitive digital-to-analog converters, the capacitive digital-to-analog conversion unit receiving the analog voltage output from the resistive digital-to-analog conversion unit and setting a capacitance ratio between input/output terminals and between an output terminal and ground corresponding to the digital value of each element of a matrix;
a successive approximation type analog-to-digital conversion unit including a plurality of successive approximation type analog-to-digital converters, the successive approximation type analog-to-digital conversion unit converting a voltage of a node commonly connected to each output terminal of the capacitive digital-to-analog conversion unit into a digital value and outputting the digital value;
a current consumption control unit for controlling a current consumption of the resistive digital-to-analog conversion unit;
having
a multiply-accumulate calculator that uses the output from the successive approximation type analog-to-digital converter as an output vector;
[2]
The multiply-accumulate calculator according to claim 1, wherein the current consumption control unit controls a generation period of an analog voltage output from the resistive digital-to-analog converter.
[3]
The multiply-and-accumulate calculator according to claim 1 or 2, further comprising a conversion count control unit that controls the number of successive approximations in the successive approximation type analog-to-digital conversion unit.
[4]
The multiply-add calculator according to any one of [1] to [3], further comprising a reference voltage control unit that controls a reference voltage of the successive approximation type analog-to-digital conversion unit.
[5]
The multiply-and-accumulate calculator according to claim 4, wherein a capacitor that samples an input signal is connected to a connection portion of the capacitive digital-to-analog converter and the input end of the comparator of the successive approximation type analog-to-digital conversion portion as the reference voltage control portion.
[6]
The multiply-add calculator according to claim 5, wherein the capacitance value of the capacitance for sampling the input signal is controllable.
[7]
The multiply-add calculator according to any one of [1] to [6], further comprising an adder that adds an offset value to an output from the successive approximation type analog-to-digital conversion unit, and an offset control unit that controls the offset value.
[8]
The multiply-add calculator according to any one of [1] to [7], further comprising a multiplier that multiplies an output from the successive approximation type analog-to-digital conversion unit by a coefficient, and a coefficient control unit that controls the coefficient.

1, 10, 100 Product-accumulator 11 Resistive digital-to-analog conversion section 12, 102 Capacitive digital-to-analog conversion section 13 Successive approximation type analog-to-digital conversion section 14 Current consumption control section 15 Conversion count control section 16 Reference voltage control section 17 Multiplier 18 Coefficient control section 19 Adder 20 Offset control section 21 Comparator 101 Voltage output digital-to-analog conversion section 103 Analog-to-digital conversion section

Claims (8)

a resistive digital-to-analog conversion unit including a plurality of resistive digital-to-analog converters, which converts the digital value of each element of an input vector into an analog voltage and outputs the analog voltage;
a capacitive digital-to-analog conversion unit including a plurality of capacitive digital-to-analog converters, the capacitive digital-to-analog conversion unit receiving the analog voltage output from the resistive digital-to-analog conversion unit and setting a capacitance ratio between input/output terminals and between an output terminal and ground corresponding to the digital value of each element of a matrix;
a successive approximation type analog-to-digital conversion unit including a plurality of successive approximation type analog-to-digital converters, the successive approximation type analog-to-digital conversion unit converting a voltage of a node commonly connected to each output terminal of the capacitive digital-to-analog conversion unit into a digital value and outputting the digital value;
a current consumption control unit for controlling a current consumption of the resistive digital-to-analog conversion unit;
having
a multiply-accumulate calculator that uses the output from the successive approximation type analog-to-digital converter as an output vector; The multiply-accumulate calculator according to claim 1, wherein the current consumption control unit controls the generation period of the analog voltage output from the resistive digital-to-analog converter. The multiply-and-accumulate calculator according to claim 1, further comprising a conversion count control unit that controls the number of successive approximations in the successive approximation type analog-to-digital conversion unit. The multiply-and-accumulate calculator according to claim 1, further comprising a reference voltage control unit that controls the reference voltage of the successive approximation type analog-to-digital conversion unit. The multiply-and-accumulate calculator according to claim 4, wherein a capacitor that samples an input signal is connected as the reference voltage control unit to the connection between the capacitive digital-to-analog converter and the input end of the comparator of the successive approximation type analog-to-digital conversion unit. The multiply-and-accumulate calculator according to claim 5, wherein the capacitance value of the capacitance for sampling the input signal is controllable. The multiply-and-accumulate calculator according to claim 1, further comprising an adder that adds an offset value to the output from the successive approximation type analog-to-digital conversion unit, and an offset control unit that controls the offset value. The multiply-and-accumulate calculator according to claim 1 or 7, further comprising a multiplier that multiplies the output from the successive approximation type analog-to-digital conversion unit by a coefficient, and a coefficient control unit that controls the coefficient.

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