WO2024018892A1 - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

The present invention includes a substrate, and a semiconductor stacked structure disposed on the substrate. The semiconductor stacked structure includes: a multi-channel structure including a plurality of first nitride semiconductor layers; and a plurality of second nitride semiconductor layers in which a band gap is larger than that of the first nitride semiconductor layers. The first nitride semiconductor layers and the second nitride semiconductor layers are alternately disposed, and a bottommost layer is a first nitride semiconductor layer. Among the plurality of first nitride semiconductor layers included in the multi-channel structure, each of the first nitride semiconductor layers other than the first nitride semiconductor layer of the bottommost layer includes: a first region on a lower surface side that is doped with donor-type impurities; and a second region on an upper surface side that is not doped with donor-type impurities.

Description

Semiconductor device and its manufacturing method

The present disclosure relates to a semiconductor device and a method for manufacturing the same.

In this specification, Group III nitride semiconductors will be referred to as "nitride semiconductors." A group III nitride semiconductor is a group III-V semiconductor using nitrogen as a group V element. Typical examples are aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN). Generally, it can be expressed as Al _x In _y Ga _1-x-y N (0≦x≦1, 0≦y≦1, 0≦x+y≦1).

Patent Document 1 discloses a Schottky Barrier Diode that includes a nitride semiconductor. This Schottky barrier diode has a semiconductor layer stack consisting of a buffer layer formed on a substrate, an undoped GaN layer formed on the buffer layer, and a channel layer formed on the GaN layer. are doing. The channel layer is formed by alternately stacking undoped AlGaN layers and undoped GaN layers.

International Publication No. 2012/160757

In the Schottky barrier diode described in Patent Document 1, the AlGaN layer and the GaN layer included in the channel layer are composed of an undoped AlGaN layer and an undoped GaN layer, respectively. It has been found that two-dimensional electron gas is difficult to form within.

The reason why two-dimensional electron gas is difficult to form in the GaN layer in the channel layer is considered as follows. That is, due to the spontaneous polarization electric field of the AlGaN layer and the piezoelectric polarization electric field caused by the lattice mismatch between the AlGaN layer and the GaN layer, the conduction band bottom energy level on the surface side of the AlGaN layer (the side opposite to the substrate) increases (main (See the left-hand diagram of FIG. 5 of the embodiment). In the channel layer, a GaN layer is formed on the lowest AlGaN layer, and then an AlGaN layer is formed on top of the GaN layer, and so on. Therefore, in the channel layer, the conduction band bottom energy level of each of the substrate side end and the surface side end of the AlGaN layer gradually increases from the substrate side to the surface side of the channel layer. As a result, in the channel layer, the conduction band bottom energy level at the interface between the substrate side end of the AlGaN layer and the GaN layer tends to be higher than the Fermi level. This makes it difficult to generate two-dimensional electron gas.

An object of the present disclosure is to provide a semiconductor device and a method for manufacturing the same that can improve the electrical characteristics of two-dimensional electron gas in a multi-channel structure.

An embodiment of the present disclosure includes a substrate and a semiconductor stacked structure disposed on the substrate, and the semiconductor stacked structure includes a plurality of first nitride semiconductor layers and a semiconductor stacked structure that is larger than the first nitride semiconductor layer. a plurality of second nitride semiconductor layers having a large band gap, the first nitride semiconductor layers and the second nitride semiconductor layers are alternately arranged, and the bottom layer is the first nitride semiconductor layer. Among the plurality of first nitride semiconductor layers included in the multi-channel structure, the first nitride semiconductor layers other than the bottom first nitride semiconductor layer are: A semiconductor device is provided that includes a first region on a lower surface side doped with a donor type impurity and a second region on an upper surface side not doped with the donor type impurity.

With this configuration, the electrical characteristics of the two-dimensional electron gas in the multi-channel structure can be improved.

In one embodiment of the present disclosure, a plurality of a multi-channel structure forming step of forming a multi-channel structure including the first nitride semiconductor layer and a plurality of second nitride semiconductor layers; In the process of forming the first nitride semiconductor layer other than the first nitride semiconductor layer, donor-type impurities are selectively doped in the thickness direction of the first nitride semiconductor layer, thereby forming the first nitride semiconductor layer in the lowermost layer. Manufacturing a semiconductor device, wherein the first nitride semiconductor layer other than the first nitride semiconductor layer includes a first region on the lower surface side doped with a donor type impurity and a second region on the upper surface side not doped with the donor type impurity. provide a method.

With this manufacturing method, it is possible to manufacture a semiconductor device that can improve the electrical characteristics of two-dimensional electron gas in a multi-channel structure.

The above-mentioned and other objects, features, and effects of the present disclosure will be made clear by the following description of the embodiments with reference to the accompanying drawings.

FIG. 1 is a schematic plan view for explaining the configuration of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. 1, and is also a schematic cross-sectional view taken along line II-II in FIG. FIG. 3A is a cross-sectional view showing an example of the manufacturing process of the nitride semiconductor device shown in FIGS. 1 and 2. FIG. FIG. 3B is a cross-sectional view showing the next step of FIG. 3A. FIG. 3C is a cross-sectional view showing the next step of FIG. 3B. FIG. 3D is a cross-sectional view showing the next step of FIG. 3C. FIG. 3E is a cross-sectional view showing the next step from FIG. 3D. Figure 4 shows that by doping a GaAs/AlGaAs/GaAs stack with a donor in a region where the conduction band bottom energy Ec is high, a two-dimensional electron gas is formed in a region where the conduction band bottom energy Ec is low. It is an energy band diagram for explanation. Figure 5 shows that when donors are doped into the upper surface side part of the AlGaN layer and the lower surface side part of the GaN layer in the GaN/AlGaN/GaN stack, a two-dimensional electron gas with a higher density is generated in the area where the conduction band bottom energy Ec is low. It is an energy band diagram for explaining formation. FIG. 6 is an energy band diagram showing the energy distribution of the multi-channel structure in the semiconductor device according to the first embodiment. FIG. 7 shows the total number of combinations of GaN layers and AlGaN layers in a multi-channel structure and sheet carriers in the entire multi-channel structure when the doped impurity concentration in the first region of the first nitride semiconductor layer is changed. It is a graph showing the relationship with density [cm ² ]. FIG. 8 shows the total number of combinations of GaN layers and AlGaN layers in a multi-channel structure and the mobility in the entire multi-channel structure when the doped impurity concentration in the first region of the first nitride semiconductor layer is changed. It is a graph showing the relationship with [cm ² /Vs]. FIG. 9 shows the total number of combinations of GaN layers and AlGaN layers in a multi-channel structure and the sheet resistance of the entire multi-channel structure when the doped impurity concentration in the first region of the first nitride semiconductor layer is changed. It is a graph showing the relationship with [ohm/sq]. FIG. 10 is a schematic cross-sectional view for explaining the configuration of a semiconductor device according to a second embodiment of the present disclosure, and is a cross-sectional view corresponding to the cut plane of FIG. 2. FIG. 11 is an energy band diagram showing the energy distribution of the multi-channel structure in the semiconductor device according to the second embodiment. FIG. 12 is a schematic cross-sectional view for explaining the configuration of a semiconductor device according to a third embodiment of the present disclosure, and is a cross-sectional view corresponding to the cut plane of FIG. 2. FIG. 13 is a schematic plan view for explaining the configuration of a semiconductor device according to a fourth embodiment of the present disclosure. FIG. 14 is a schematic plan view for explaining the configuration of a semiconductor device according to a fifth embodiment of the present disclosure. FIG. 15 is a schematic cross-sectional view taken along the line XIV-XIV in FIG. 14. FIG. 16 is a schematic cross-sectional view for explaining the configuration of a semiconductor device according to a sixth embodiment of the present disclosure, and is a cross-sectional view corresponding to the cut plane of FIG. 2.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic plan view for explaining the configuration of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG.

For convenience of explanation, the +X direction, -X direction, +Y direction, and -Y direction shown in FIG. 1 may be used below. The +X direction is a predetermined direction along the surface of the substrate 2, and the +Y direction is a predetermined direction along the surface of the substrate 2 and perpendicular to the +X direction.

The -X direction is the opposite direction to the +X direction. The -Y direction is the opposite direction to the +Y direction. When the +X direction and the -X direction are collectively referred to, they are simply referred to as the "X direction." When the +Y direction and the -Y direction are collectively referred to, they are simply referred to as the "Y direction."

The semiconductor device 1 is a Schottky barrier diode. For example, as shown in FIG. 1, the semiconductor device 1 has a rectangular shape that is long in the X direction and has two sides parallel to the X direction and two sides parallel to the Y direction in plan view. The length of the semiconductor device 1 in the X direction in plan view is, for example, about 2 mm, and the length of the semiconductor device 1 in the Y direction is, for example, about 1 mm.

The semiconductor device 1 includes a substrate 2 having a first main surface (front surface) 2a and a second main surface (back surface) 2b, and a semiconductor stacked structure 3 formed on the first main surface 2a of the substrate 2.

In this embodiment, the substrate 2 is a Si substrate (silicon substrate) whose main material is Si. The first main surface 2a of the substrate 2 is a (111) plane. The substrate may be a 4H-SiC substrate or a 6H-SiC substrate, or may be a substrate with an off-angle.

The semiconductor stacked structure 3 includes a buffer layer 4 formed on the first main surface 2a of the substrate 2, a semi-insulating nitride semiconductor layer 5 formed on the buffer layer 4, and a semi-insulating nitride semiconductor layer 5. and a multi-channel structure 6 formed thereon.

The buffer layer 4 is a buffer layer for alleviating strain caused by the difference between the lattice constant of the semi-insulating nitride semiconductor layer 5 formed on the buffer layer 4 and the lattice constant of the substrate 2. In this embodiment, the buffer layer 4 is composed of a multilayer buffer layer in which a plurality of nitride semiconductor films are laminated. In this embodiment, the buffer layer 4 includes an AlN film 41 in contact with the first main surface 2a of the substrate 2, and an AlGaN film 42 laminated on the surface of this AlN film 41 (the surface opposite to the substrate 2). It is composed of laminated films. The thickness of the AlN film 41 is about 0.2 μm, and the thickness of the AlGaN film 42 is about 0.1 μm to 1.0 μm. The buffer layer 4 may be composed of a single AlN film or a single AlGaN film.

The semi-insulating nitride semiconductor layer 5 is provided to suppress leakage current. In this embodiment, the semi-insulating nitride semiconductor layer 5 is made of a GaN layer doped with impurities, and has a thickness of about 0.9 μm to 10 μm. The impurity is, for example, C (carbon). The concentration of impurities is, for example, 1×10 ¹⁸ cm ⁻³ or more and 1×10 ¹⁹ cm ⁻³ or less.

The multi-channel structure 6 includes a plurality of first nitride semiconductor layers 61 and 62 and a plurality of second nitride semiconductor layers 63 having a larger band gap than the first nitride semiconductor layers 61 and 62. The first nitride semiconductor layers 61 and 62 and the second nitride semiconductor layer 63 are alternately stacked. In FIG. 2, the total number of combinations of the first nitride semiconductor layers 61, 62 and the second nitride semiconductor layer 63 is three; The total number of combinations may be 2 or more, and may be 4 or more.

The plurality of first nitride semiconductor layers 61 and 62 include a bottom first nitride semiconductor layer 61 and other first nitride semiconductor layers 62. The bottom layer of multi-channel structure 6 is first nitride semiconductor layer 61 . The upper surface of each first nitride semiconductor layer 61, 62 is a Ga polar surface.

The first nitride semiconductor layers 61 and 62 are composed of Al _x Ga _1-x N (0≦x<1) layers, and the second nitride semiconductor layer 63 is composed of Al _y Ga _1-y N (0<y≦1) layers. , y>x) layers. In this case, x and y preferably satisfy the condition {y>(x+0.1)}.

Further, the first nitride semiconductor layers 61 and 62 are composed of Al _x1 Ga _y1 In _z1 N (0≦x1≦1, x1+y1+z1=1) layers, and the second nitride semiconductor layer 63 is composed of Al _x2 Ga _y2 In _z2 N It may be composed of layers (0≦x2≦1, x2+y2+z2=1). However, the band gap of the Al _x2 Ga _y2 In _z2 N layer is larger than that of the Al _x1 Ga _y1 In _z1 N layer.

In this embodiment, the first nitride semiconductor layers 61 and 62 are made of GaN layers, and the second nitride semiconductor layer 63 is made of an AlGaN layer.

The thickness of the first nitride semiconductor layer 61, which is the lowermost layer, is, for example, about 0.05 μm to 1 μm. In this embodiment, the film thickness of the lowermost first nitride semiconductor layer 61 is about 0.1 μm.

It is preferable that the film thickness of the first nitride semiconductor layer 62 other than the first nitride semiconductor layer 61 at the bottom is 10 nm or more and 50 nm or less. The thickness of the second nitride semiconductor layer 63 is preferably 10 nm or more and 50 nm or less. In this embodiment, the film thicknesses of the first nitride semiconductor layers 62 and the second nitride semiconductor layers 63 other than the first nitride semiconductor layer 61 at the bottom layer are each 25 nm.

In this embodiment, the lowermost first nitride semiconductor layer 61 is made of a non-doped GaN layer, and the other first nitride semiconductor layers 62 are selectively doped with donor-type impurities in the thickness direction. It consists of a GaN layer. The first nitride semiconductor layer 62 other than the first nitride semiconductor layer 61 in the lowermost layer has a first region 62a on the lower surface side doped with donor-type impurities and a second region 62a on the upper surface side not doped with donor-type impurities. region 62b. In FIG. 2, the first region 62a is shown with dot hatching for clarity.

It is preferable that the ratio of the thickness of the first region 62a to the thickness of the first nitride semiconductor layer 62 is 1/5 or more and 4/5 or less. In this embodiment, the ratio of the thickness of the first region 62a to the thickness of the first nitride semiconductor layer 62 is 1/2. That is, in this embodiment, the film thickness of the first region 62a and the film thickness of the second region 62b are each 12.5 nm.

The donor type impurity is, for example, Si or Ge. In this embodiment, the donor type impurity is Si. The concentration of the donor type impurity is preferably 1×10 ¹⁹ cm ⁻³ or more and 1×10 ²⁰ cm ⁻³ or less. In this embodiment, the concentration of donor type impurities is 5×10 ¹⁹ cm ⁻³ .

In this embodiment, the second nitride semiconductor layer 63 is made of a non-doped AlGaN layer.

In each of the first nitride semiconductor layers 61 and 62, two-dimensional electron gas (2DEG) is formed near the interface with the upper second nitride semiconductor layer 63, as shown by the broken line in FIG. There is. A channel is formed by this two-dimensional electron gas.

An insulating film 7 is formed on the upper surface of the semiconductor stacked structure 3. In this embodiment, the insulating film 7 is made of a SiO ₂ film. The thickness of the insulating film 7 may be about 500 Å.

A first opening 8 and a second opening 9 are formed in the insulating film 7 at intervals in the X direction. The first opening 8 and the second opening 9 penetrate the insulating film 7 in the thickness direction. The first opening 8 and the second opening 9 have a rectangular shape that is long in the Y direction when viewed from above. The second opening 9 is arranged on the +X direction side of the first opening 8 in plan view.

A first trench 10 communicating with the first opening 8 is formed in the semiconductor stacked structure 3 . The first trench 10 is dug toward the substrate 2 from the upper surface of the multi-channel structure 6 and extends halfway through the thickness of the semi-insulating nitride semiconductor layer 5 through the multi-channel structure 6 .

In this embodiment, the cross section of the first trench 10 has a rectangular shape that is long in the Y direction. In this embodiment, each side surface 10a of the first trench 10 is formed into an inclined surface such that the cross-sectional area of the first trench 10 becomes smaller as it goes downward. That is, each side surface 10a of the first trench 10 is formed into an inclined surface inclined with respect to the normal to the first main surface 2a of the substrate 2. Note that each side surface 10a of the first trench 10 may be formed substantially perpendicular to the main surface of the substrate 2.

Further, a second trench 11 communicating with the second opening 9 is formed in the semiconductor stacked structure 3 . The second trench 11 is dug toward the substrate 2 from the upper surface of the multi-channel structure 6 and extends halfway through the thickness of the semi-insulating nitride semiconductor layer 5 through the multi-channel structure 6 .

In this embodiment, the cross section of the second trench 11 has a rectangular shape that is long in the Y direction. In this embodiment, each side surface 11a of the second trench 11 is formed into an inclined surface in which the cross-sectional area of the second trench 11 decreases as it goes downward. That is, each side surface 11a of the second trench 11 is formed into an inclined surface inclined with respect to the normal to the first main surface 2a of the substrate 2. Note that each side surface 11a of the second trench 11 may be formed substantially perpendicular to the main surface of the substrate 2.

A cathode electrode 12 is formed on the insulating film 7 so as to cover the first opening 8 and make ohmic contact with the two-dimensional electron gas. The cathode electrode 12 includes a first portion 12A that covers the side surface of the first opening 8, the side surface 10A of the first trench 10, and the bottom surface of the first trench 10, and a peripheral portion of the first opening 8 on the upper surface of the insulating film 7. and a second portion 12B covering the second portion 12B. The upper end of the first portion 12A is integrally connected to the portion of the second portion 12B facing the first opening 8. The first portion 12A of the cathode electrode 12 is in contact with the inner surface (side surface 10a and bottom surface) of the first trench 10.

The cathode electrode 12 is made of, for example, a laminated film (Ti/Al/Ni/Au laminated film) in which a Ti layer, an Al layer, a Ni layer, and an Au layer are laminated in that order. The Ti/Al/Ni/Au laminated film is a laminated film with a Ti layer as the bottom layer.

An anode electrode 13 is formed on the insulating film 7 so as to cover the second opening 9 and make Schottky contact with the two-dimensional electron gas. The anode electrode 13 includes a first portion 13A that covers the side surface of the second opening 9, the side surface 11a of the second trench 11, and the bottom surface of the second trench 11, and a peripheral portion of the second opening 9 on the upper surface of the insulating film 7. and a second portion 13B covering the second portion 13B. The upper end of the first portion 13A is integrally connected to the portion of the second portion 13B facing the second opening 9. The first portion 13A of the anode electrode 13 is in contact with the inner surface (side surface 11a and bottom surface) of the second trench 11.

The anode electrode 13 is made of, for example, a laminated film (Ni/Au laminated film) in which a Ni layer and an Au layer are laminated in that order. The Ni/Au laminated film is a laminated film having a Ni layer as a lower layer and an Au layer as an upper layer. The anode electrode 13 may be composed of, for example, a laminated film (Pd/Au laminated film) in which a Pd layer and an Au layer are laminated in that order. The Pd/Au laminated film is a laminated film having a Pd layer as a lower layer and an Au layer as an upper layer.

3A to 3E are cross-sectional views illustrating an example of the manufacturing process of the semiconductor device 1, and are cross-sectional views corresponding to the cut plane of FIG. 2.

A silicon wafer (not shown) is prepared as the original substrate of the substrate 2. A plurality of element regions corresponding to a plurality of semiconductor devices (Schottky barrier diodes) 1 are arranged in a matrix on the surface of a silicon wafer. A boundary region (scribe line) is provided between adjacent element regions. The boundary region is a belt-shaped region having a substantially constant width, and is formed in a grid shape extending in two orthogonal directions. After performing necessary steps on the silicon wafer, a plurality of semiconductor devices 1 are obtained by cutting the silicon wafer along the boundary region.

First, as shown in FIG. 3A, a buffer layer 4, a semi-insulating nitride semiconductor layer 5, and a multilayer A channel structure 6 is formed. In addition, in the process of forming the first nitride semiconductor layer 62 (excluding the first nitride semiconductor layer 61 at the bottom layer) in the multi-channel structure 6, a donor type impurity is added to the lower surface side region (first region 62a). (for example, Si) is doped. Thereby, the semiconductor stacked structure 3 is formed on the first main surface 2a of the substrate 2.

Next, as shown in FIG. 3B, an insulating film 7 made of, for example, SiO ₂ is formed over the entire upper surface of the semiconductor stacked structure 3 by, for example, a plasma CVD (Plasma Enhanced Chemical Vapor Deposition) method.

Next, as shown in FIG. 3C, a first opening 8 and a second opening 9 are formed in the insulating film 7 by, for example, photolithography and etching.

Next, as shown in FIG. 3D, the semiconductor stacked structure 3 is dry-etched using the insulating film 7 as a hard mask, thereby forming the first trench 10 and the second trench 11 in the semiconductor stacked structure 3.

Next, as shown in FIG. 3E, the cathode electrode 12 is formed so as to cover the side surface of the first opening 8, the inner surface of the first trench 10, and the peripheral portion of the first trench 10 on the upper surface of the insulating film 7. It is formed.

Finally, the anode electrode 13 is formed to cover the side surface of the second opening 9, the inner surface of the second trench 11, and the surrounding area of the second trench 11 on the upper surface of the insulating film 7. A semiconductor device 1 as shown in FIG. 1 and FIG. 2 is obtained.

In the semiconductor device 1 according to the first embodiment, the first nitride semiconductor layer 62 other than the lowermost first nitride semiconductor layer 61 in the multi-channel structure 6 is a first nitride semiconductor layer on the lower surface side doped with donor-type impurities. It includes a region 62a and a second region 62b on the upper surface side which is not doped with donor type impurities. Thereby, the electrical characteristics of the two-dimensional electron gas in the multi-channel structure 6 can be improved.

With the same configuration as the semiconductor device 1 according to the first embodiment shown in FIGS. 1 and 2, the first nitride semiconductor layer 62 other than the lowest first nitride semiconductor layer 61 in the multi-channel structure 6 is A semiconductor device made of an undoped GaN layer like the first nitride semiconductor layer 61 in the lower layer will be referred to as a comparative example. Also in the comparative example, the second nitride semiconductor layer 63 in the multi-channel structure 6 is composed of an undoped AlGaN layer, similarly to the semiconductor device 1 according to the first embodiment.

In the comparative example, a two-dimensional electron gas functioning as a channel was formed in the first nitride semiconductor layer 61 at the bottom layer, but a two-dimensional electron gas was formed in the first nitride semiconductor layer 62 other than the bottom layer in the multi-channel structure 6. No two-dimensional electron gas was formed to act as a channel.

In contrast, in the first embodiment, a two-dimensional electron gas functioning as a channel is formed in the first nitride semiconductor layer 61 at the bottom layer, and the first nitride semiconductor layer in the multi-channel structure 6 other than the bottom layer A two-dimensional electron gas functioning as a channel was also formed within the physical semiconductor layer 62. Thereby, the electrical characteristics of the two-dimensional electron gas in the multi-channel structure can be improved.

In the first embodiment, the reason why a two-dimensional electron gas functioning as a channel is formed also in the first nitride semiconductor layer 62 other than the bottom layer in the multi-channel structure 6 will be explained.

As shown on the left side of FIG. 4, the energy band of a GaAs/AlGaAs/GaAs stack in which an AlGaAs layer and a GaAs layer are stacked in that order on a GaAs layer is as shown on the left side of FIG. In FIG. 4, E _C is the energy level at the bottom of the conduction band, and E _F is the Fermi level. In FIG. 5, E _C is the energy level at the bottom of the conduction band, E _V is the energy level at the top of the valence band, and E _F is the Fermi level.

In the GaAs/AlGaAs/GaAs stack, no polarization electric field is generated, so no two-dimensional electron gas is formed. As shown on the right side of FIG. 4, when a donor is doped in a region where the conduction band bottom energy E _C is high, a two-dimensional electron gas is formed in a region where the conduction band bottom energy E _C is low. In the GaAs/AlGaAs/GaAs stack, the region where the conduction band bottom energy E _C is high corresponds to AlGaAs.

On the other hand, as shown on the left side of FIG. 5, in a GaN/AlGaN/GaN laminate in which an AlGaN layer and a GaN layer are stacked in that order on a GaN layer, polarization electric fields (spontaneous polarization electric field and piezo polarization electric field) are generated. A two-dimensional electron gas is formed where the conduction band bottom energy E _C is low.

In the GaN/AlGaN/GaN stack, the upper surface side portion of the AlGaN layer and the lower surface side portion of the GaN layer are areas where the conduction band bottom energy E _C is high. Therefore, as shown on the right side of FIG. 5, when donors are doped into the upper surface side portion of the AlGaN layer and the lower surface side portion of the GaN layer, two _- dimensional Electron gas is more likely to be generated.

FIG. 6 is an energy band diagram showing the energy distribution of the multi-channel structure 6 in the semiconductor device 1 according to the first embodiment. In FIG. 6, GaN indicates the first nitride semiconductor layers 61 and 62, and AlGaN to the left of each GaN indicates the second nitride semiconductor layer 63. Also, in FIG. E _C is the energy level at the bottom of the conduction band, E _V is the energy level at the top of the valence band, E _F is the Fermi level, E _C1 is the maximum value of E _C in GaN, and E _C2 is This is the minimum value of E _C in AlGaN. The same applies to FIG. 11, which will be described later.

In FIG. 6, for clarity, the first region 62a of the first nitride semiconductor layer 62 other than the bottom layer in the multi-channel structure 6 is shown with dot hatching.

In the first embodiment, in the first nitride semiconductor layer 62 other than the bottom layer in the multi-channel structure 6, the first region 62a on the lower surface side thereof is doped with a donor type impurity. That is, in the first embodiment, a region (first region 62a) including a location where the conduction band bottom energy E _C is maximum in the first nitride semiconductor layer 62 is doped with a donor type impurity. As a result, a two-dimensional electron gas functioning as a channel is formed also in the first nitride semiconductor layer 62 other than the bottom layer in the multi-channel structure 6.

In addition, in the above-mentioned comparative example, the conduction band lower end energy level E _C of each of the substrate side end and surface side end of the AlGaN layer in FIG. 6 is different from the energy distribution of the first embodiment shown in FIG. It is thought that the energy distribution becomes gradually higher from the side to the surface side (from the right side to the left side in FIG. 6). The reason for this has already been explained in the section of the problem to be solved by the invention. Therefore, in the comparative example, it is considered that a two-dimensional electron gas functioning as a channel is not formed in the first nitride semiconductor layer 62 other than the bottom layer in the multi-channel structure 6.

FIG. 7 shows the total number of combinations (total number of combinations) of GaN layers and AlGaN layers in a multi-channel structure and the multi-channel structure when the doped impurity concentration in the first region 62a of the first nitride semiconductor layer 62 is changed. It is a graph showing the relationship with the sheet carrier density [cm ² ] in the entire channel structure.

In FIG. 7, the ▲ mark represents the measurement result when the doped impurity concentration in the first region 62a is 5×10 ¹⁸ cm ⁻³ , and the ● mark represents the measurement result when the doped impurity concentration in the first region 62a is 5×10 18 cm −3. The measurement results are shown when the doped impurity concentration in 62a is 5×10 ¹⁹ cm ⁻³ . In FIG. 7, ◆ indicates that the multi-channel structure corresponds to the bottom GaN layer (corresponding to the first nitride semiconductor layer 61) and the bottom AlGaN layer (corresponding to the bottom second nitride semiconductor layer 63). ) shows the measurement results for the case where the structure is composed of only two layers. The same applies to FIGS. 8 and 9.

From FIG. 7, when the doped impurity concentration in the first region 62a is 5×10 ¹⁸ cm ⁻³ , even if the total number of combinations of GaN layers and AlGaN layers increases, the multi-channel structure remains in the bottom layer. It can be seen that the sheet carrier density [cm ² ] in the entire multichannel structure does not increase compared to the case where the structure is composed of only the GaN layer and the bottom AlGaN layer.

On the other hand, when the doped impurity concentration in the first region 62a is 5×10 ¹⁹ cm ⁻³ , as the total number of combinations of GaN layers and AlGaN layers increases, the sheet size in the entire multi-channel structure increases. It can be seen that the carrier density [cm ² ] increases.

FIG. 8 shows the total number of combinations of GaN layers and AlGaN layers in a multi-channel structure and the total number of combinations in the entire multi-channel structure when the doped impurity concentration in the first region 62a of the first nitride semiconductor layer 62 is changed. It is a graph showing the relationship with mobility (cm ² /Vs).

From FIG. 8, it can be seen that the total number of combinations of GaN layers and AlGaN layers increases both when the doped impurity concentration in the first region 62a is 5×10 ¹⁸ cm ⁻³ and when it is 5×10 ¹⁹ cm ⁻³ . As a result, it can be seen that the mobility gradually decreases. Furthermore, when the doped impurity concentration in the first region 62a is 5×10 ¹⁹ cm ⁻³ , the mobility is higher than when the doped impurity concentration is 5×10 ¹⁸ cm ⁻³ . I understand.

FIG. 9 shows the total number of combinations of GaN layers and AlGaN layers in a multi-channel structure and the total number of combinations in the entire multi-channel structure when the doped impurity concentration in the first region 62a of the first nitride semiconductor layer 62 is changed. It is a graph showing the relationship with sheet resistance (ohm/sq).

From FIG. 9, it can be seen that when the doped impurity concentration in the first region 62a is 5×10 ¹⁸ cm ⁻³ , the sheet resistance increases as the total number of combinations of GaN layers and AlGaN layers increases. Recognize.

On the other hand, when the doped impurity concentration in the first region 62a is 5×10 ¹⁹ cm ⁻³ , the sheet resistance decreases significantly as the total number of combinations of GaN layers and AlGaN layers increases. I understand that.

As described above, when the doped impurity concentration in the first region 62a is set to 5×10 ¹⁹ cm ⁻³ , the sheet carrier concentration increases significantly as the total number of combinations of GaN layers and AlGaN layers increases. It can be seen that the sheet resistance increases and the sheet resistance decreases significantly, improving the electrical properties of the two-dimensional electron gas in the multi-channel structure.

From the measurement results shown in FIGS. 7 to 9, it can be seen that the doped impurity concentration in the first region 62a is preferably set to 1×10 ¹⁹ cm ⁻³ or more and 1×10 ²⁰ cm ⁻³ or less.

FIG. 10 is a schematic cross-sectional view showing the configuration of a semiconductor device 1A according to a second embodiment of the present invention, and is a cross-sectional view corresponding to the cut plane of FIG. 2. In FIG. 10, parts corresponding to those in FIG. 2 are designated by the same reference numerals as in FIG.

In the semiconductor device 1 according to the first embodiment described above, the first region 62a on the lower surface side of the first nitride semiconductor layer 62 other than the bottom layer in the multi-channel structure 6 is doped with a donor-type impurity. The second nitride semiconductor layer 63 within the channel structure 6 is not doped with donor type impurities.

In the semiconductor device 1A according to the second embodiment, as shown in FIG. Donor-type impurities are selectively doped into the 2-nitride semiconductor layer 63 in the thickness direction. Specifically, the second nitride semiconductor layer 63 includes a third region 63a on the lower surface side not doped with donor-type impurities and a fourth region 63b on the upper surface side doped with donor-type impurities. There is. In FIG. 10, for clarity, in addition to the first region 62a, the fourth region 63b is also shown with dot hatching. In the example of FIG. 10, the ratio of the thickness of the fourth region 63b to the thickness of the second nitride semiconductor layer 63 is 2/3.

FIG. 11 is an energy band diagram showing the energy distribution of the multi-channel structure 6 in the semiconductor device 1A according to the second embodiment.

In FIG. 11, for clarity, dot hatching is applied to the first region 62a of the first nitride semiconductor layer 62 and the fourth region 63b of the second nitride semiconductor layer 63 other than the bottom layer in the multi-channel structure 6. It is shown with a .

In the second embodiment, the region (first region 62a) including the location where the conduction band bottom energy E _C is maximum in the first nitride semiconductor layer 62 and the conduction band bottom energy E _C in the second nitride semiconductor layer 63 are described. A region (fourth region 63b) including the portion where the maximum is doped with a donor-type impurity. As a result, a two-dimensional electron gas functioning as a channel is formed also in the first nitride semiconductor layer 62 other than the bottom layer in the multi-channel structure 6.

In the semiconductor device 1A according to the second embodiment, the second nitride semiconductor layer 63 in the multi-channel structure 6 is selectively doped with donor-type impurities in the thickness direction. The entire area within the 2-nitride semiconductor layer 63 may be doped with a donor type impurity.

FIG. 12 is a schematic cross-sectional view for explaining the configuration of a semiconductor device 1B according to a third embodiment of the present disclosure, and is a cross-sectional view corresponding to the cut plane of FIG. 2. In FIG. 12, parts corresponding to those in FIG. 2 are designated by the same reference numerals as in FIG.

The semiconductor device 1B according to the third embodiment differs from the semiconductor device 1 according to the first embodiment in that the first trench 10 is not formed. In this case, the cathode electrode 12 is formed on the insulating film 7 so as to cover the first opening 8 . The cathode electrode 12 includes a first portion 12A filled in the first opening 8, and a second portion covering the upper surface of the first portion 12A and the peripheral portion of the first opening 8 on the upper surface of the insulating film 7. 12B. The upper surface of the first portion 12A is integrally connected to the lower surface of the second portion 12B. The first portion 12A is in contact with the upper surface of the multichannel structure 6 (second nitride semiconductor layer 63) exposed in the first opening 8.

Also in the semiconductor device 1B according to the third embodiment, like the semiconductor device 1A according to the second embodiment, a donor type is selectively formed in the second nitride semiconductor layer 63 in the multi-channel structure 6 in the thickness direction. It may be doped with impurities. Further, the entire second nitride semiconductor layer 63 in the multi-channel structure 6 may be doped with a donor type impurity.

FIG. 13 is a schematic plan view for explaining the configuration of a semiconductor device according to a fourth embodiment of the present disclosure. FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. 13. In FIG. 13, parts corresponding to those in FIG. 1 are designated by the same reference numerals as in FIG.

In the semiconductor device 1C according to the fourth embodiment, the structures of the second opening 9, the second trench 11, and the anode electrode 13 are different from the semiconductor device 1 according to the first embodiment.

In the semiconductor device 1C according to the fourth embodiment, a plurality of second openings 9 penetrating the insulating film 7 are formed at positions closer to the +X side of the insulating film 7 at intervals in the Y direction in a plan view. ing. Each second opening 9 has a rectangular shape that is long in the X direction when viewed from above.

A plurality of second trenches 11 are formed in the multi-channel structure 6 and communicate with each of the plurality of second openings 9. Each second trench 11 is dug toward the substrate 2 from the upper surface of the multi-channel structure 6 and extends halfway through the thickness of the semi-insulating nitride semiconductor layer 5 through the multi-channel structure 6 .

In this embodiment, the cross section of the second trench 11 has a rectangular shape that is long in the X direction. In this embodiment, each side surface 11a of the second trench 11 is formed into an inclined surface in which the cross-sectional area of the second trench 11 decreases as it goes downward. Note that each side surface 11a of the second trench 11 may be formed substantially perpendicular to the main surface of the substrate 2.

The anode electrode 13 includes, for each second opening 9, a plurality of first portions 13A that cover the second opening 9, the side surface 11a of the second trench 11 communicating therewith, and the bottom surface of the second trench 11. . Further, the anode electrode 13 includes a second portion 13B that covers a region including the peripheral portions of all the second openings 9 on the upper surface of the insulating film 7. The plurality of first portions 13A and second portions 13B are integrally connected.

Also in the semiconductor device 1C according to the fourth embodiment, like the semiconductor device 1A according to the second embodiment, a donor type is selectively formed in the second nitride semiconductor layer 63 in the multi-channel structure 6 in the thickness direction. It may be doped with impurities. Further, the entire second nitride semiconductor layer 63 in the multi-channel structure 6 may be doped with a donor type impurity.

FIG. 14 is a schematic plan view for explaining the configuration of a semiconductor device 1D according to a fifth embodiment of the present disclosure. FIG. 15 is a schematic cross-sectional view taken along line XIV-XIV in FIG. 14.

In FIG. 14, parts corresponding to those in FIG. 1 are designated with the same reference numerals as in FIG. 1. In FIG. 15, parts corresponding to those in FIG. 2 are designated by the same reference numerals as in FIG.

In the semiconductor device 1D according to the fifth embodiment, the shape of the semiconductor device 1D, the first opening 8, the second opening 9, the second trench 11, and the cathode electrode 12 are different from the semiconductor device 1 according to the first embodiment. And the structure of the anode electrode 13 is different. In the semiconductor device 1D according to the fifth embodiment, the first trench 10 is not formed.

The semiconductor device 1D has a square shape in plan view, with two sides parallel to the X direction and two sides parallel to the Y direction. The length of each side of the semiconductor device 1 in plan view is, for example, about 1 mm.

A second opening 9, which is circular in plan view, is formed in the center of the upper surface of the insulating film 7. Further, a first opening 8 having a rectangular ring shape in plan view is formed on the upper surface of the insulating film 7 so as to surround the second opening 9 . The first opening 8 may be formed in an annular shape when viewed from above. The first opening 8 and the second opening 9 penetrate the insulating film 7 in the thickness direction.

A second trench 11 communicating with the second opening 9 is formed in the semiconductor stacked structure 3 . The second trench 11 is dug toward the substrate 2 from the upper surface of the multi-channel structure 6 and extends halfway through the thickness of the semi-insulating nitride semiconductor layer 5 through the multi-channel structure 6 .

In this embodiment, the cross section of the second trench 11 is circular. In this embodiment, the second trench 11 is formed into an inverted truncated cone shape in which the cross-sectional area of the second trench 11 becomes smaller as it goes downward. Thereby, the side surface 11a of the second trench 11 is formed into an inclined surface that is inclined with respect to the normal to the first main surface 2a of the substrate 2 in a vertical cross-sectional view. Note that the second trench 11 may be formed in a cylindrical shape extending perpendicularly to the first main surface 2a of the substrate 2.

A cathode electrode 12 is formed on the insulating film 7 so as to cover the first opening 8. The cathode electrode 12 includes a first portion 12A that fills the first opening 8 and is endless in plan view. Further, the cathode electrode 12 includes a second portion 12B that is endless in plan view and covers the upper surface of the first portion 12A and the periphery of the first opening 8 on the upper surface of the insulating film 7. The first portion 12A is in contact with the upper surface of the semiconductor stacked structure 3 (second nitride semiconductor layer 63) exposed in the first opening 8. The upper surface of the first portion 12A is integrally connected to the lower surface of the second portion 12B. The cathode electrode 12 is made of, for example, a laminated film (Ti/Al/Ni/Au laminated film) in which a Ti layer, an Al layer, a Ni layer, and an Au layer are laminated in that order.

An anode electrode 13 is formed on the insulating film 7 so as to cover the second opening 9 and make Schottky contact with the two-dimensional electron gas. The anode electrode 13 includes a first portion 13A that covers the side surface of the second opening 9, the side surface 11a of the second trench 11, and the bottom surface of the second trench 11. Further, the anode electrode 13 includes a second portion 13B that is annular in plan view and covers the periphery of the second opening 9 on the upper surface of the insulating film 7. The upper end of the first portion 13A is integrally connected to the portion of the second portion 13B facing the second opening 9.

The anode electrode 13 is made of, for example, a laminated film (Ni/Au laminated film) in which a Ni layer and an Au layer are laminated in that order. The anode electrode 13 may be composed of, for example, a laminated film (Pd/Au laminated film) in which a Pd layer and an Au layer are laminated in that order.

Also in the semiconductor device 1D according to the fifth embodiment, the multi-channel structure 6 has the same configuration as the semiconductor device 1 according to the first embodiment. be effective.

Also in the semiconductor device 1D according to the fifth embodiment, like the semiconductor device 1A according to the second embodiment, a donor type is selectively formed in the second nitride semiconductor layer 63 in the multi-channel structure 6 in the thickness direction. It may be doped with impurities. Further, the entire second nitride semiconductor layer 63 in the multi-channel structure 6 may be doped with a donor type impurity.

In the semiconductor device 1D according to the fifth embodiment, the third opening 8 is connected to the first opening 8, penetrates the multi-channel structure 6, and extends halfway through the thickness of the semi-insulating nitride semiconductor layer 5. A trench may be formed. In this case, the cathode electrode 12 is configured to partially cover the inner surface of the third trench.

FIG. 16 is a schematic cross-sectional view showing the configuration of a semiconductor device 1E according to a sixth embodiment of the present invention, and is a cross-sectional view corresponding to the cut plane of FIG. 2. In FIG. 16, parts corresponding to those in FIG. 2 are designated by the same reference numerals as in FIG.

In the semiconductor device 1E according to the sixth embodiment, each second nitride semiconductor layer 63 in the multi-channel structure 6 is composed of a lower AlN layer 63D and an upper AlGaN layer 63U formed on the AlN layer 63D. has been done. The thickness of the AlN layer 63D is, for example, 1 nm or more and 2 nm or less, and the thickness of the AlGaN layer 63U is, for example, 10 nm or more and 50 nm or less.

Also in the semiconductor device 1E according to the sixth embodiment, the multi-channel structure 6 has the same configuration as the semiconductor device 1 according to the first embodiment. be effective.

Note that also in the semiconductor devices 1A to 1D according to the second embodiment, the third embodiment, the fourth embodiment, and the fifth embodiment described above, each second nitride semiconductor layer 63 in the multi-channel structure 6 is It may be configured from an AlN layer 63D and an upper AlGaN layer 63U formed on the AlN layer 63D.

Although the first to sixth embodiments of the present disclosure have been described above, the present disclosure can also be implemented in other forms. In the first to sixth embodiments described above, the second trench 11 extends halfway through the thickness of the semi-insulating nitride semiconductor layer 5 through the multi-channel structure 6; The upper surface of the semi-insulating nitride semiconductor layer 5 may be reached. Further, the second trench 11 may extend from the upper surface of the multi-channel structure 6 to halfway through the thickness of the first nitride semiconductor layer as the lowermost layer.

Furthermore, in the first, second, fourth and sixth embodiments described above, the first trench 10 extends halfway through the thickness of the semi-insulating nitride semiconductor layer 5 through the multi-channel structure 6. However, it may penetrate through the multi-channel structure 6 and reach the upper surface of the semi-insulating nitride semiconductor layer 5. Further, the first trench 10 may extend from the upper surface of the multi-channel structure 6 to part way through the thickness of the first nitride semiconductor layer as the lowermost layer.

Further, in the first to sixth embodiments described above, the lowermost first nitride semiconductor layer 61 is composed of an undoped GaN layer, but a part of the lowermost first nitride semiconductor layer 61 is made of an undoped GaN layer. The region or the entire region may be doped with a donor type impurity.

In addition to Schottky barrier diodes, the present disclosure is also applicable to high electron mobility transistors (HEMTs), thermoelectric elements, Hall elements, pressure sensors, and the like.

The features described below can be extracted from the description of this specification and drawings.

[Appendix 1-1]
a substrate (2);
a semiconductor stacked structure (3) disposed on the substrate (2);
The semiconductor stacked structure (3) includes a plurality of first nitride semiconductor layers (61, 62) and a plurality of second nitride semiconductor layers having a larger band gap than the first nitride semiconductor layers (61, 62). (63), the first nitride semiconductor layer (61, 62) and the second nitride semiconductor layer (63) are alternately arranged, and the bottom layer is the first nitride semiconductor layer (63). 61), including a multi-channel structure (6),
Among the plurality of first nitride semiconductor layers (61, 62) included in the multi-channel structure (6), first nitride semiconductor layers (62) other than the bottom first nitride semiconductor layer (61) ) is a semiconductor device including a first region (62a) on the lower surface side doped with a donor type impurity and a second region (62b) on the upper surface side not doped with the donor type impurity.

[Appendix 1-2]
The semiconductor device according to [Appendix 1-1], wherein the concentration of the donor type impurity is 1×10 ¹⁹ cm ⁻³ or more and 1×10 ²⁰ cm ⁻³ .

[Appendix 1-3]
The ratio of the thickness of the first region (62a) to the thickness of the first nitride semiconductor layer (62) having the first region (62a) is 1/5 or more and 4/5 or less 1-1] or the semiconductor device according to [Appendix 1-2].

[Appendix 1-4]
Each of the plurality of second nitride semiconductor layers (63) included in the multi-channel structure (6) has a region doped with the donor-type impurity at least in part in the thickness direction. The semiconductor device according to any one of [Appendix 1-1] to [Appendix 1-3].

[Appendix 1-5]
Each of the plurality of second nitride semiconductor layers (63) included in the multi-channel structure (6) includes a third region layer (63a) on the lower surface side which is not doped with donor type impurities, and a third region layer (63a) on the lower surface side which is not doped with donor type impurities; The semiconductor device according to [Appendix 1-4], including a fourth region (63b) on the upper surface side doped with an impurity.

[Appendix 1-6]
The first nitride semiconductor layer (61, 62) is made of an Al _x Ga _1-x N (0≦x<1) layer,
Any one of [Appendix 1-1] to [Appendix 1-5], wherein the second nitride semiconductor layer (63) is made of an Al _y Ga _1-y N (0<y≦1, y>x) layer. The semiconductor device described.

[Appendix 1-7]
The semiconductor device according to [Appendix 1-6], wherein the x and the y satisfy the condition {y>(x+0.1)}.

[Appendix 1-8]
The first nitride semiconductor layer (61, 62) is made of a GaN layer,
The semiconductor device according to [Appendix 1-7], wherein the second nitride semiconductor layer (63) is made of an AlGaN layer.

[Appendix 1-9]
The semiconductor device according to any one of [Appendix 1-1] to [Appendix 1-8], wherein the upper surface of the first nitride semiconductor layer (61, 62) is a Ga polar surface.

[Appendix 1-10]
The semiconductor device according to any one of [Appendix 1-1] to [Appendix 1-9], wherein the donor type impurity is Si or Ge.

[Appendix 1-11]
Among the plurality of first nitride semiconductor layers (61, 62), each of the first nitride semiconductor layers (62) other than the bottom first nitride semiconductor layer (61) has a thickness of 10 nm or more and 50 nm. The following is
The semiconductor device according to any one of [Appendix 1-1] to [Appendix 1-10], wherein the film thickness (63) of each of the second nitride semiconductors is 10 nm or more and 50 nm or less.

[Appendix 1-12]
The method according to any one of [Appendix 1-1] to [Appendix 1-11], comprising a cathode electrode (12) and an anode electrode (13) arranged at a distance from each other on the semiconductor stacked structure (3). Semiconductor equipment.

[Appendix 1-13]
a first trench dug from the upper surface of the multi-channel structure (6) and extending through the multi-channel structure (6) or to a mid-thickness portion of the lowermost first nitride semiconductor layer (61); (10) and
The first trench (10) is spaced apart and is dug from the top surface of the multi-channel structure (6) and penetrates the multi-channel structure (6), or a second trench (11) extending to a mid-thickness portion of the semiconductor layer (61);
The cathode electrode (12) is formed to contact a side surface of the first trench (10) and is in ohmic contact with a two-dimensional electron gas formed within the multi-channel structure (6);
The anode electrode (13) is formed to contact the side surface of the second trench (11) and is in Schottky contact with the two-dimensional electron gas formed within the multi-channel structure (10). Supplementary Note 1-12].

[Appendix 1-14]
The semiconductor stacked structure includes a buffer layer formed on the substrate, and a semi-insulating nitride semiconductor layer formed on the buffer layer,
The semiconductor device according to any one of [Appendix 1-1] to [Appendix 1-13], wherein the multi-channel structure is formed on the semi-insulating nitride semiconductor layer.

[Appendix 1-15]
The first nitride semiconductor layer (61, 62) is made of a GaN layer,
[Appendix 1-1], wherein the second nitride semiconductor layer (63) consists of a lower AlN layer (63D) and an upper AlGaN layer (63U) formed on the AlN layer (63D). The semiconductor device according to any one of [Appendix 1-5].

[Appendix 1-16]
A first nitride semiconductor layer (61, 62) and a second nitride semiconductor layer (63) having a larger band gap than the first nitride semiconductor layer (61, 62) are alternately formed on the substrate (2). a multi-channel structure forming step of forming a multi-channel structure (6) including a plurality of first nitride semiconductor layers (61, 62) and a plurality of second nitride semiconductor layers (63) by stacking the layers. including,
In the multi-channel structure step, in the process of forming the first nitride semiconductor layer (62) other than the first nitride semiconductor layer (61) in the lowermost layer, the first nitride semiconductor layer (62) is The donor type impurity is selectively doped in the thickness direction, whereby the first nitride semiconductor layer (62) other than the first nitride semiconductor layer (61) at the bottom layer is doped with the donor type impurity. A method for manufacturing a semiconductor device, the method comprising: a first region (61A) on the lower surface side, and a second region (61b) on the upper surface side, which is not doped with the donor-type impurity.

[Appendix 1-17]
A buffer layer forming step of forming a buffer layer (4) on the substrate (2), which is a step performed before the multi-channel structure step;
A step performed before the multi-channel structure step and after the buffer layer forming step, including a step of forming a semi-insulating nitride semiconductor layer (5) on the buffer layer (4),
The method for manufacturing a semiconductor device according to [Appendix 1-16], wherein the multi-channel structure (6) is formed on the semi-insulating nitride semiconductor layer (5).

Although the embodiments of the present disclosure have been described in detail above, these are only specific examples used to clarify the technical content of the present disclosure, and the present disclosure should not be construed as limited to these specific examples. Rather, the scope of the disclosure is limited only by the claims appended hereto.

This application corresponds to Japanese Patent Application No. 2022-117299 filed with the Japan Patent Office on July 22, 2022, and the entire disclosures of those applications are hereby incorporated by reference.

1, 1A, 1B, 1C, 1D, 1E Semiconductor device 2 Substrate 2a First main surface 2b Second main surface 3 Semiconductor stacked structure 4 Buffer layer 5 Semi-insulating nitride semiconductor layer 6 Multi-channel structure 7 Insulating film 8 First Opening 9 Second opening 10 First trench 10a Side surface 11 Second trench 11a Side surface 12 Cathode electrode 12A First portion 12B Second portion 13 Anode electrode 13A First portion 13B Second portion 41 AlN film 42 AlGaN film 61, 62 First nitride semiconductor layer 62a First region 62b Second region 63 Second nitride semiconductor layer 63a Third region 63b Fourth region 63D AlN layer 63U AlGaN layer

Claims (17)

A substrate and
a semiconductor stacked structure disposed on the substrate;
The semiconductor stacked structure includes a plurality of first nitride semiconductor layers and a plurality of second nitride semiconductor layers having a larger band gap than the first nitride semiconductor layers, and the first nitride semiconductor layer and the second nitride semiconductor layer have a larger band gap than the first nitride semiconductor layers. and a multi-channel structure in which second nitride semiconductor layers are alternately arranged, and the bottom layer is the first nitride semiconductor layer,
Among the plurality of first nitride semiconductor layers included in the multi-channel structure, the first nitride semiconductor layers other than the bottom first nitride semiconductor layer are doped with donor-type impurities on the lower surface side. and a second region on the upper surface side which is not doped with the donor type impurity. The semiconductor device according to claim 1, wherein the concentration of the donor type impurity is 1×10 ¹⁹ cm ⁻³ or more and 1×10 ²⁰ cm ⁻³ . The semiconductor device according to claim 1, wherein a ratio of the thickness of the first region to the thickness of the first nitride semiconductor layer having the first region is 1/5 or more and 4/5 or less. 2. Each of the plurality of second nitride semiconductor layers included in the multi-channel structure has a region doped with the donor type impurity at least in part in the thickness direction. Semiconductor equipment. Each of the plurality of second nitride semiconductor layers included in the multi-channel structure has a third region on the lower surface side which is not doped with the donor type impurity, and a fourth region on the upper surface side where the donor type impurity is doped. The semiconductor device according to claim 4, comprising a region. The first nitride semiconductor layer is made of an Al _x Ga _1-x N (0≦x<1) layer,
6. The semiconductor device according to claim 1, wherein the second nitride semiconductor layer is an Al _y Ga _1-y N (0<y≦1, y>x) layer. The semiconductor device according to claim 6, wherein the x and the y satisfy the condition {y>(x+0.1)}. the first nitride semiconductor layer is made of a GaN layer,
8. The semiconductor device according to claim 7, wherein the second nitride semiconductor layer is made of an AlGaN layer. The semiconductor device according to any one of claims 1 to 5, wherein the upper surface of the first nitride semiconductor layer is a Ga polar surface. The semiconductor device according to any one of claims 1 to 5, wherein the donor type impurity is Si or Ge. Among the plurality of first nitride semiconductor layers, each of the first nitride semiconductor layers other than the bottom first nitride semiconductor layer has a thickness of 10 nm or more and 50 nm or less,
The semiconductor device according to claim 1, wherein each of the second nitride semiconductors has a film thickness of 10 nm or more and 50 nm or less. The semiconductor device according to any one of claims 1 to 5, comprising a cathode electrode and an anode electrode that are spaced apart from each other on the semiconductor stacked structure. a first trench dug from the top surface of the multi-channel structure and extending through the multi-channel structure or to an intermediate thickness of the lowermost first nitride semiconductor layer;
The first trench is spaced apart from the first trench, is dug from the top surface of the multi-channel structure, and extends through the multi-channel structure or to a mid-thickness portion of the first nitride semiconductor layer that is the lowest layer. Includes a second trench,
the cathode electrode is formed in contact with an inner surface of the first trench and is in ohmic contact with a two-dimensional electron gas formed within the multi-channel structure;
13. The semiconductor device according to claim 12, wherein the anode electrode is formed so as to be in contact with the inner surface of the second trench, and is in Schottky contact with the two-dimensional electron gas formed within the multi-channel structure. The semiconductor stacked structure includes a buffer layer formed on the substrate, and a semi-insulating nitride semiconductor layer formed on the buffer layer,
6. The semiconductor device according to claim 1, wherein the multi-channel structure is formed on the semi-insulating nitride semiconductor layer. the first nitride semiconductor layer is made of a GaN layer,
6. The semiconductor device according to claim 1, wherein the second nitride semiconductor layer includes a lower AlN layer and an upper AlGaN layer formed on the AlN layer. By alternately stacking a first nitride semiconductor layer and a second nitride semiconductor layer having a larger band gap than the first nitride semiconductor layer on the substrate, a plurality of the first nitride semiconductor layers and a multi-channel structure forming step of forming a multi-channel structure including a plurality of second nitride semiconductor layers;
In the multi-channel structure step, in the process of forming the first nitride semiconductor layers other than the first nitride semiconductor layer in the lowermost layer, a donor type is selectively formed in the thickness direction of the first nitride semiconductor layer. The first nitride semiconductor layer other than the first nitride semiconductor layer at the bottom layer is doped with an impurity, and the first nitride semiconductor layer other than the first nitride semiconductor layer in the lowermost layer is doped with a first region on the lower surface side doped with the donor type impurity and a first region doped with the donor type impurity. and a second region on the upper surface side where the upper surface is not covered. A step performed before the multi-channel structure step, a buffer layer forming step of forming a buffer layer on the substrate;
A step performed before the multi-channel structure step and after the buffer layer forming step, comprising a step of forming a semi-insulating nitride semiconductor layer on the buffer layer,
17. The method of manufacturing a semiconductor device according to claim 16, wherein the multi-channel structure is formed on the semi-insulating nitride semiconductor layer.

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