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WO2024012329A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2024012329A1
WO2024012329A1 PCT/CN2023/105911 CN2023105911W WO2024012329A1 WO 2024012329 A1 WO2024012329 A1 WO 2024012329A1 CN 2023105911 W CN2023105911 W CN 2023105911W WO 2024012329 A1 WO2024012329 A1 WO 2024012329A1
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WO
WIPO (PCT)
Prior art keywords
line
lead
data
lines
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2023/105911
Other languages
English (en)
French (fr)
Inventor
何翼
王蓉
董向丹
何帆
颜俊
樊聪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US18/692,846 priority Critical patent/US20240431163A1/en
Priority to GB2406575.7A priority patent/GB2627595A/en
Priority to DE112023003096.0T priority patent/DE112023003096T5/de
Publication of WO2024012329A1 publication Critical patent/WO2024012329A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
    • H10H29/14—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00 comprising multiple light-emitting semiconductor components
    • H10H29/142—Two-dimensional arrangements, e.g. asymmetric LED layout

Definitions

  • This article relates to but is not limited to the field of display technology, and specifically refers to a display substrate and a display device.
  • OLED Organic light emitting diodes
  • QLED Quantum-dot Light Emitting Diodes
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • this embodiment provides a display substrate, including: a substrate, a plurality of sub-pixels, a plurality of first data lines, a plurality of second data lines, a plurality of first data connection lines, and a plurality of second data connection lines. , a plurality of first data lead-out lines, a plurality of second data lead-out lines, a plurality of lead-out adapter lines and at least one first power line.
  • the substrate includes a display area and a frame area, and the frame area includes a first frame area located on one side of the display area.
  • the display area has a first boundary close to the first frame area, the frame area has a second boundary and a third boundary, the second boundary and the third boundary are located at the first boundary in a first direction. both sides.
  • a plurality of sub-pixels, a plurality of first data lines, a plurality of second data lines, a plurality of first data connection lines and a plurality of second data connection lines are located in the display area.
  • the plurality of first data lines and the plurality of second data lines are configured to provide data signals to the plurality of sub-pixels.
  • the plurality of first data connection lines extend along a first direction
  • the plurality of first data lines, the plurality of second data lines and the plurality of second data connection lines extend along a second direction
  • the first direction is related to The second direction crosses.
  • the plurality of first data lines are electrically connected to the plurality of second data connection lines through the plurality of first data connection lines.
  • the plurality of first data lines are located on a side of the plurality of second data lines and the plurality of second data connection lines close to the second boundary or the third boundary in the first direction.
  • a plurality of first data lead-out lines, a plurality of second data lead-out lines, a plurality of lead-out adapter lines and at least one first power line are located in the first frame area.
  • the plurality of first data lead-out lines are electrically connected to the plurality of second data connection lines, and the plurality of second data lead-out lines are electrically connected to the plurality of second data lines.
  • the at least one first power line is configured to provide power signals to the plurality of sub-pixels.
  • At least one first data lead-out line among the plurality of first data lead-out lines includes: a first lead-out line and a second lead-out line, and the first lead-out line is electrically connected to the second lead-out line through the lead-out adapter line. connection, the first lead-out line is electrically connected to the second data connection line, the lead-out adapter line at least partially extends along the first direction, and the second lead-out line is located in the first direction.
  • the second data lead-out line is close to one side of the second boundary or the third boundary. An orthographic projection of at least one of the plurality of lead-out adapter lines on the substrate overlaps an orthographic projection of the first power line on the substrate.
  • the first power line at least includes: a first wiring line; the first wiring line has a plurality of openings, and the connection position of the first lead-out line and the lead-out adapter line is at the An orthographic projection of the substrate is located within a range of the orthographic projection of the opening.
  • At least part of the line segments of the first data lead-out line and at least part of the line segments of the second data lead-out line are located on a side of the first trace close to the substrate, so The lead-out transfer line is located on a side of the first trace away from the substrate.
  • At least an organic insulation layer is provided between the lead-out transfer line and the first trace.
  • the first lead-out wire is electrically connected to the lead-out adapter wire through a first connection electrode, the first connection electrode is located in the opening, and the first connection electrode is on the lining.
  • the orthographic projection of the bottom does not overlap with the orthographic projection of the first trace on the substrate.
  • the first connection electrode and the first wiring are in the same layer structure.
  • the orthographic projection of the first data lead-out line and the second data lead-out line on the substrate overlaps with the orthographic projection of the first trace on the substrate.
  • the first power line further includes: a second trace located on a side of the first trace away from the substrate, the second trace being connected to the first trace Electrically connected, the orthographic projection of the second trace on the substrate does not overlap with the orthographic projection of the opening of the first trace on the substrate.
  • the second trace and the lead-out adapter line have a same-layer structure.
  • At least one insulation layer is provided between the first trace and the second trace, and at least part of the first trace is in direct contact with the second trace, so The second trace covers at least part of the boundary of the at least one insulation layer in an orthographic projection of the substrate.
  • the at least one insulating layer includes: an inorganic insulating layer and an organic insulating layer, and the inorganic insulating layer is located on a side of the organic insulating layer close to the substrate.
  • the display substrate has a first centerline in the first direction.
  • the plurality of first data lines are located on a side of the plurality of second data lines and the plurality of second data connection lines away from the first center line in the first direction.
  • the two lead-out lines are located on a side of the second data lead-out line away from the first center line in the first direction.
  • the display area includes: a first area and a second area located on both sides of the first center line.
  • the second data connection line electrically connected to the first data line far away from the first center line is located near the first center line electrically connected to the first data line.
  • the second data connection line is close to the side of the first center line.
  • the display area includes: a first area and a second area located on both sides of the first center line; within the first area or the second area, away from the first center
  • the second data connection line electrically connected to the first data line of the line is located on a side away from the first center line and the second data connection line electrically connected to the first data line close to the first center line.
  • the lead-out adapter wire electrically connected to the first lead-out wire close to the first center line, and the lead-out adapter wire electrically connected to the first lead-out wire located away from the first center line is close to the lead-out adapter wire. side of the display area.
  • the lead-out adapter wire electrically connected to the first lead-out wire located close to the first center line, and the lead-out adapter wire electrically connected to the first lead-out wire located away from the first center line are further away from the first lead-out wire. side of the display area.
  • the plurality of lead-out patch lines are symmetrical about the first centerline.
  • the first frame area at least includes: along a direction away from the display area.
  • the first fan-out area, the bending area, the second fan-out area and the first circuit area are arranged in sequence; the first circuit area at least includes a test circuit; the first power line and the lead-out adapter line are at least located on the Second fan-out area.
  • the first lead-out line and the second lead-out line are located in the second fan-out area.
  • connection position of the second lead-out line and the lead-out adapter line does not overlap with the orthographic projection of the substrate on the substrate and the first power line on the substrate.
  • connection position of the second lead-out wire and the lead-out adapter wire is located on a side of the first power line away from the bending area.
  • this embodiment provides a display device including the display substrate as described above.
  • Figure 1 is a schematic structural diagram of a display device according to at least one embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of a display substrate according to at least one embodiment of the present disclosure
  • FIG. 3 is a schematic cross-sectional structural diagram of a display area of a display substrate according to at least one embodiment of the present disclosure
  • Figure 4 is a schematic diagram of wiring of a display substrate according to at least one embodiment of the present disclosure.
  • Figure 5 is an example diagram of wiring of a display substrate according to at least one embodiment of the present disclosure.
  • Figure 6 is a partial wiring diagram of the second fan-out area according to at least one embodiment of the present disclosure.
  • Figure 7 is a partial schematic diagram of the first frame area of at least one embodiment of the present disclosure.
  • Figure 8 is a schematic diagram of the first data lead-out line and the second data lead-out line in Figure 7;
  • Figure 9 is a partial schematic diagram of the first source and drain metal layer in Figure 7;
  • Figure 10 is a partial schematic diagram of the second source and drain metal layer in Figure 7;
  • Figure 11 is a partial schematic diagram of the bending area and the second fan-out area in Figure 7;
  • Figure 12 is a partial enlarged schematic diagram of area A2 in Figure 11;
  • Figure 13A is a partially enlarged schematic view of the second fan-out area after forming the second gate metal layer in Figure 12;
  • Figure 13B is a partially enlarged schematic view of the second fan-out area after forming the first source and drain metal layer in Figure 12;
  • Figure 13C is a partially enlarged schematic diagram of the second fan-out area after forming the seventh insulating layer in Figure 12;
  • Figure 14A is a partial enlarged schematic diagram along the P-P' direction in Figure 12;
  • Figure 14B is a partial enlarged schematic diagram along the Q-Q’ direction in Figure 12;
  • Figure 14C is a partially enlarged schematic diagram along the U-U’ direction in Figure 12;
  • Figure 15 is a schematic diagram of the connection between the lead-out adapter wire and the second lead-out wire according to at least one embodiment of the present disclosure
  • Figure 16 is another wiring schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • Figure 17 is another wiring schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • Figure 18 is a partial schematic diagram of the second fan-out area in Figure 16 or Figure 17;
  • Figure 19 is a resistance change curve diagram of multiple data lead-out lines in the first frame area
  • FIG. 20 is a resistance change curve diagram of multiple data lead lines in the first frame area after resistance compensation.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • element having some electrical function There is no particular limitation on the "element having some electrical function” as long as it can transmit electrical signals between connected components.
  • elements with some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with multiple functions.
  • a transistor refers to an element including at least three terminals: a gate, a drain, and a source.
  • a transistor has a channel region between a drain (drain electrode terminal, drain region, or drain electrode) and a source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the gate can also be called the control electrode.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not strictly speaking. They can be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances. There can be leading angles, arc edges, deformations, etc.
  • FIG. 1 is a schematic structural diagram of a display device according to at least one embodiment of the present disclosure.
  • the display device may include: a timing controller, a data driver, a scan driver, a light emitting driver, and a display substrate.
  • the timing controller is connected to the data driver, scan driver and light-emitting driver respectively.
  • the data driver is respectively connected to a plurality of data lines (for example, D1 to Dn)
  • the scan driver is respectively connected to a plurality of scan lines (for example, S1 to Sm)
  • the light emitting driver is respectively connected to a plurality of light emitting control lines (for example, E1 to Eo). connect.
  • n, m and o can be natural numbers.
  • the display substrate includes a pixel array, and the pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include: a pixel circuit and a light-emitting element connected to the pixel circuit.
  • the pixel circuit can be connected to the scanning line, the light emission control line and the data line respectively.
  • the timing controller may provide grayscale values and control signals suitable for specifications of the data driver to the data driver, and may provide clock signals, scan start signals, etc. suitable for specifications of the scan driver.
  • the scan driver can provide a clock signal, a light emission control start signal, and the like suitable for the specifications of the light emitting driver to the light emitting driver.
  • the data driver may generate data voltages to be provided to the data lines D1, D2, D3, . . . and Dn using the grayscale values and control signals received from the timing controller.
  • the data driver may sample grayscale values using a clock signal and apply data voltages corresponding to the grayscale values to the data signal lines D1 to Dn in units of pixel rows.
  • the scan driver may generate scan signals to be provided to the scan lines S1, S2, S3, . . . and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller.
  • the scan driver may sequentially provide scan signals having on-level pulses to the scan lines S1 to Sm.
  • the scan driver may be configured in the form of a shift register, and may generate the scan signal in a manner that sequentially transmits a scan start signal provided in the form of an on-level pulse to a next-stage circuit under the control of a clock signal .
  • the light-emitting driver may generate light-emitting control signals to be provided to the light-emitting control lines E1, E2, E3, . . .
  • the light-emitting driver may sequentially provide emission signals with off-level pulses to the light-emitting control lines E1 to Eo.
  • the light-emitting driver may be configured in the form of a shift register, and the light-emitting control may be generated in a manner that sequentially transmits a light-emitting control start signal provided in the form of an off-level pulse to a next-stage circuit under the control of a clock signal Signal.
  • FIG. 2 is a schematic structural diagram of a display substrate according to at least one embodiment of the present disclosure.
  • the display substrate may include: a display area 100 and a frame area located around the display area 100 .
  • the frame area may include: a first frame area 200 located on one side of the display area 100 and a second frame area 300 located on other sides of the display area 100 .
  • the first frame area 200 and the second frame area 300 are connected and surround the display area 100 .
  • the display area 100 may be a flat area including a plurality of sub-pixels Pxij that constitute a pixel array.
  • the plurality of sub-pixels Pxij may be configured to display dynamic pictures or still images.
  • the display area 100 may be called an effective area (AA, Active Area).
  • the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as curled, bent, folded, or rolled.
  • the display area 100 has a first boundary B1 close to the first frame area 200 , a sixth boundary B6 , a seventh boundary B7 , and an eighth boundary B8 close to the second frame area 300 .
  • the first boundary B1 may be connected between the sixth boundary B6 and the seventh boundary B7
  • the eighth boundary B8 may be connected between the sixth boundary B6 and the seventh boundary B7.
  • the first boundary B1 and the eighth boundary B8 may be opposite along the second direction Y
  • the sixth boundary B6 and the seventh boundary B7 may be opposite along the first direction X.
  • the sixth boundary B6 and the seventh boundary B7 may be located on both sides of the first boundary B1 in the first direction X.
  • the border area may have a second boundary B2, a third boundary B3, a fourth boundary B4 and Fifth border B5.
  • the fourth boundary B4 may be connected between the second boundary B2 and the third boundary B3, and the fifth boundary B5 may be connected between the second boundary B2 and the third boundary B3.
  • the second boundary B2 and the third boundary B3 are opposite to each other in the first direction X, and the second boundary B2 and the third boundary B3 may be located on both sides of the first boundary B1 in the first direction X.
  • the first frame area 200 may include a first fan-out area 201 , a bending area 202 , and a second fan-out area sequentially arranged along the second direction Y away from the display area 100 .
  • the first fan-out area 201 may be connected to the display area 100 and at least include a plurality of data fan-out lines configured to connect data lines of the display area 100 in a fan-out wiring manner.
  • the bending area 202 is connected between the first fan-out area 201 and the second fan-out area 203.
  • the bending area 202 may include a composite insulating layer provided with grooves and is configured to bind the second fan-out area 203 to The pin area 207 is bent to the back of the display area 100 .
  • the second fan-out area 203 may at least include a plurality of data fan-out lines led out in a fan-out wiring manner.
  • the second fan-out area 203 is connected between the bending area 202 and the first circuit area 204.
  • the first circuit area 204 may include: an anti-static circuit and a test circuit.
  • the anti-static circuit may be configured to prevent electrostatic damage to the display substrate by eliminating static electricity.
  • the test circuit may be configured to provide data test signals to the data lines of the display area 100 .
  • the third fan-out area 205 may at least include a plurality of data fan-out lines led out in the form of fan-out wiring.
  • the third fan-out area 205 is connected between the first circuit area 204 and the driver chip area 206 .
  • the driver chip area 206 may be provided with an integrated circuit (IC), and the integrated circuit may be configured to be connected to a plurality of data fan-out lines in the third fan-out area 205 .
  • the bonding pin area 207 may include: multiple bonding pads (Bonding Pads), and the bonding pads may be configured to be bonded to an external flexible circuit board (FPC, Flexible Printed Circuit). Connection traces may be provided between the driver chip area 206 and the pin binding area 207.
  • the second frame area 300 may include: a second circuit area, a power line area, a crack dam area, and a cutting area sequentially arranged along the first direction X away from the display area 100 .
  • the first direction X intersects the second direction Y.
  • the first direction X is perpendicular to the second direction Y.
  • the second circuit area is connected to the display area 100 and may include at least a gate driving circuit connected to the first scanning line, the second scanning line and the light emission control line to which the pixel circuit in the display area 100 is connected.
  • the power line area is connected to the second circuit area and may at least include a frame power lead extending in a direction parallel to the edge of the display area and connected to the cathode in the display area 100 .
  • the crack dam area is connected to the power line area and may include at least a plurality of cracks provided on the composite insulation layer.
  • the cutting area is connected to the crack dam area and may at least include cutting grooves provided on the composite insulating layer.
  • the cutting grooves are configured such that after all film layers of the display substrate are prepared, the cutting equipment cuts along the cutting grooves respectively.
  • the first fan-out area 201 in the first frame area 200 and the power line area in the second frame area 300 may be provided with first isolation dams and second isolation dams.
  • the first isolation dams and The second isolation dam may extend in a direction parallel to the edge of the display area to form an annular structure surrounding the display area 100 .
  • the edge of the display area is the edge of the display area 100 close to the first frame area 200 or the second frame area 300 .
  • the display substrate may include a plurality of pixel units arranged in a matrix. At least one pixel unit may include three sub-pixels emitting different colors. For example, one pixel unit may include: red sub-pixels, green sub-pixels and blue sub-pixels. Alternatively, at least one pixel unit may include four sub-pixels, for example, may include: a red sub-pixel, a blue sub-pixel and two green sub-pixels, or may include a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel. pixels. Each sub-pixel may include a pixel circuit and a light emitting element.
  • the pixel circuit can be connected to the scan line, the data line and the light-emitting control line respectively.
  • the pixel circuit can be configured to receive the data voltage transmitted by the data line and output the corresponding current to the light-emitting element under the control of the scan line and the light-emitting control line.
  • the light-emitting element in each sub-pixel is respectively connected to the pixel circuit of the sub-pixel, and the light-emitting element is configured to emit light of corresponding brightness in response to the current output by the pixel circuit of the sub-pixel.
  • the shape of the light-emitting element of the sub-pixel may be rectangular, rhombus, pentagon or hexagon.
  • the light-emitting elements of the three sub-pixels can be arranged horizontally, vertically or vertically.
  • a pixel unit includes four sub-images
  • the light-emitting elements of the four sub-pixels can be arranged in a diamond shape to form an RGBG pixel arrangement, or they can be arranged in a horizontal parallel arrangement, a vertical parallel arrangement or a square arrangement.
  • the present disclosure is not limited here.
  • FIG. 3 is a schematic cross-sectional structural diagram of a display area of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 3 illustrates the structure of three sub-pixels in the display area 100.
  • the display substrate may include: a substrate 101 , a circuit structure layer 102 , a light-emitting structure layer 103 and a packaging structure layer sequentially disposed on the substrate 101 104.
  • the display substrate may include other film layers, such as touch structure layers, etc., which are not limited in this disclosure.
  • substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the circuit structure layer 102 of each sub-pixel may include a pixel circuit composed of a plurality of transistors and storage capacitors.
  • the light-emitting structure layer 103 of each sub-pixel may at least include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303 and a cathode 304.
  • the anode 301 is connected to the pixel circuit
  • the organic light-emitting layer 303 is connected to the anode 301
  • the cathode 304 is connected to the organic light-emitting layer 303.
  • the packaging structure layer 104 may include a stacked first packaging layer 401, a second packaging layer 402, and a third packaging layer 403.
  • the first packaging layer 401 and the third packaging layer 403 may be made of inorganic materials
  • the second packaging layer 402 may be made of Organic material
  • the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to form an inorganic material/organic material/inorganic material stack structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.
  • the organic light emitting layer 303 may include an emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), and an electron blocking layer (EBL). , hole blocking layer (HBL), electron transport layer (ETL) and electron injection layer (EIL).
  • EML emitting layer
  • HIL hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • EIL electron injection layer
  • one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer and electron injection layer of all sub-pixels may be connected together through a common layer. Layers, the light-emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated from each other.
  • the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • T in the above circuit structure refers to the thin film transistor
  • C refers to the capacitor
  • the number in front of T represents the number of thin film transistors in the circuit
  • the number in front of C represents the number of capacitors in the circuit.
  • the plurality of transistors in the pixel circuit may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the product yield.
  • the plurality of transistors in the pixel circuit may include P-type transistors and N-type transistors.
  • the plurality of transistors in the pixel circuit may employ low-temperature polysilicon thin film transistors, or may employ oxide thin film transistors, or may employ low-temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of low-temperature polysilicon thin film transistors uses low temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of oxide thin film transistors uses oxide semiconductor (Oxide).
  • LTPS Low Temperature Poly-Silicon
  • oxide semiconductor Oxide
  • Low-temperature polysilicon thin film transistors and oxide thin film transistors are integrated on a display substrate, that is, LTPS+Oxide (LTPO for short)
  • the display substrate can take advantage of the advantages of both to achieve low-frequency driving, reduce power consumption, and improve display quality.
  • the plurality of transistors of the pixel circuit include low-temperature polysilicon thin film transistors and oxide thin film transistors.
  • the circuit structure layer may include: a first semiconductor layer, a first insulating layer, a first gate metal layer, a second insulating layer, a second gate metal layer, and a first gate metal layer sequentially disposed on the substrate.
  • the first semiconductor layer may include an active layer of a low temperature polysilicon thin film transistor of the pixel circuit.
  • the first gate metal layer may include: a gate electrode of a low-temperature polysilicon thin film transistor of the pixel circuit and one of the electrodes of the storage capacitor.
  • the second gate metal layer may include: another electrode of the storage capacitor of the pixel circuit.
  • the second semiconductor layer may include an active layer of an oxide thin film transistor of the pixel circuit. No.
  • the tri-gate metal layer may include: a gate electrode of an oxide thin film transistor of the pixel circuit.
  • the first source and drain metal layer may include: a plurality of connection electrodes.
  • the second source and drain metal layer may include: an anode connection electrode.
  • the anode connecting electrode of the second source-drain metal layer can be electrically connected to the corresponding anode of the light-emitting structure layer through the via hole opened in the eighth insulating layer.
  • the first to sixth insulating layers may be inorganic insulating layers, and the seventh and eighth insulating layers may be organic insulating layers, which may also be called flat layers.
  • this embodiment is not limited to this.
  • the first frame area usually includes a first fan-out area, a bending area, a second fan-out area, a first circuit area, a third fan-out area, a driving area, and a first fan-out area, a bending area, a second fan-out area, a driving area, and a first fan-out area. Chip area and bonded pin area.
  • the width of the first frame area (the length along the first direction X) is smaller than the width of the display area (the length along the first direction
  • the area can be introduced into a wider display area using the fanout wiring method.
  • the greater the width difference between the display area and the first frame area the more diagonal leads in the fan-shaped area, and the gap between the driver chip area and the display area.
  • data connection lines can be set in the display area, so that the data lead-out line of the first frame area is electrically connected to the data line through the data connection line, which can effectively reduce the length of the first fan-out area, thereby greatly reducing the size of the lower frame area.
  • the size of the border In order to improve the above situation, data connection lines can be set in the display area, so that the data lead-out line of the first frame area is electrically connected to the data line through the data connection line, which can effectively reduce the length of the first fan-out area, thereby greatly reducing the size of the lower frame area.
  • the size of the border In order of transferring the data lines through the data connection lines, the order of the data lead-out lines in the first frame area will be disrupted, so that the order of the data lead-out lines in the first frame area is different from the data in the display area.
  • the order of the lines makes it incompatible with conventional integrated circuits, and there are problems such as sudden changes in the resistance of the data signal transmission lines.
  • Embodiments of the present disclosure provide a display substrate, including: a substrate, a plurality of sub-pixels, a plurality of first data lines, a plurality of second data lines, a plurality of first data connection lines, a plurality of second data connection lines, a plurality of A plurality of first data lead-out lines, a plurality of second data lead-out lines, a plurality of lead-out adapter lines and a first power line.
  • the substrate includes a display area and a frame area, and the frame area includes a first frame area located on one side of the display area.
  • the display area has a first border close to the first frame area, and the frame area has a second border and a third border, and the second border and the third border are located on both sides of the first border in the first direction.
  • a plurality of sub-pixels, a plurality of first data lines, a plurality of second data lines, a plurality of first data connection lines and a plurality of second data connection lines are located in the display area.
  • the plurality of first data lines and the plurality of second data lines are configured to provide data signals to the plurality of sub-pixels.
  • the plurality of first data connection lines extend along the first direction, and the plurality of first data lines, the plurality of second data lines and the plurality of second data connection lines extend along the second direction.
  • the first direction intersects the second direction, for example, the first direction is perpendicular to the second direction.
  • the plurality of first data lines are electrically connected to the plurality of second data connection lines through the plurality of first data connection lines.
  • the plurality of first data lines are located on a side of the plurality of second data lines and the plurality of second data connection lines close to the second boundary or the third boundary in the first direction.
  • a plurality of first data lead-out lines, a plurality of second data lead-out lines, a plurality of lead-out adapter lines and at least one first power line are located in the first frame area.
  • a plurality of first data lead-out lines are electrically connected to a plurality of second data connection lines.
  • the plurality of second data lead-out lines are electrically connected to the plurality of second data lines.
  • At least one first power line is configured to provide power signals to the plurality of sub-pixels.
  • At least one first data lead-out line among the plurality of first data lead-out lines includes: a first lead-out line and a second lead-out line.
  • the first lead-out wire is electrically connected to the second lead-out wire through the lead-out adapter wire.
  • the first lead-out line is electrically connected to the second data connection line.
  • the lead-out transfer line extends at least partially along the first direction, and the second lead-out line is located on a side of the second data lead-out line close to the second boundary or the third boundary in the first direction.
  • An orthographic projection of at least one of the plurality of lead-out adapter lines on the substrate overlaps an orthographic projection of the first power line on the substrate.
  • the display substrate provided in this embodiment uses a lead-out adapter wire to electrically connect the first lead-out line and the second lead-out line in the first frame area to adjust the order of the first data lead-out line and the second data lead-out line along the first direction, so that The order of providing data signals or test data signals in the first frame area is consistent with the order of the first data lines and the second data lines in the display area to achieve compatibility with conventional integrated circuits, thereby saving costs. Moreover, the resistance mutation of the data signal transmission line can be improved to a certain extent.
  • the first power line may at least include: a first trace.
  • the first trace has a plurality of openings, and the connection position of the first lead-out line and the lead-out adapter line in the orthographic projection of the substrate may be located within the orthographic projection range of the openings in the substrate.
  • the first wiring of the first power line is designed to be dug to realize the arrangement of the lead-out adapter wire, which can reduce the impact on the first power line.
  • At least part of the line segments of the first data lead-out line and at least part of the line segments of the second data lead-out line may be located on a side of the first trace close to the substrate, and the lead-out transfer line may be located on the first trace. The side of the line away from the substrate.
  • the orthographic projection of the lead-out transfer line on the substrate may overlap with the orthographic projection of the multiple data lead-out lines on the substrate.
  • the first trace of the first power line is used to isolate the data lead-out line and the lead-out transfer line. , which can effectively prevent crosstalk between traces.
  • At least an organic insulation layer may be provided between the lead-out adapter wire and the first trace of the first power supply wire.
  • the dielectric layer between the lead-out adapter wire and the first trace of the first power line can be increased, as follows: It is beneficial to reduce the parasitic capacitance between the two.
  • the first lead-out wire may be electrically connected to the lead-out adapter wire through the first connection electrode.
  • the first connection electrode may be located in the opening of the first trace, and the orthographic projection of the first connection electrode on the substrate and the orthographic projection of the first trace of the first power line on the substrate may not overlap.
  • the first connection electrode and the first wiring may have the same layer structure.
  • this embodiment is not limited to this.
  • the first lead-out wire may be directly electrically connected to the lead-out adapter wire.
  • the first power line may further include: a second trace located on a side of the first trace away from the substrate.
  • the second trace is electrically connected to the first trace, and the orthographic projection of the second trace on the substrate does not overlap with the orthographic projection of the opening of the first trace on the substrate.
  • the area where the opening of the first wiring is provided is the connection area between the lead-out adapter wire and the first lead-out wire.
  • the first power line can be double-connected.
  • Layer routing For example, the second trace and the lead-out transition line may have the same layer structure.
  • the first frame area may at least include: a first fan-out area, a bending area, a second fan-out area, and a first circuit area that are sequentially arranged in a direction away from the display area.
  • the first circuit area includes at least a test circuit.
  • the first power cord and the lead-out adapter cord may be located at least in the second fan-out area.
  • arranging the lead-out adapter line on the side of the first circuit area close to the display area is helpful to adjust the order of the first data lead-out line and the second data lead-out line, thereby making it compatible with conventional integrated circuits and reducing costs.
  • the lead-out adapter line and the first power line may be located at least in the first fan-out area to implement sequential adjustment of the first data lead-out line and the second data lead-out line.
  • FIG. 4 is a schematic diagram of wiring of a display substrate according to at least one embodiment of the present disclosure.
  • the display area 100 may include: a plurality of first data lines 11 and a plurality of second data lines 12 extending along the second direction Y.
  • the first data line 11 may be electrically connected to a plurality of sub-pixels Pxij arranged along the second direction Y, and is configured to provide data signals to the plurality of sub-pixels Pxij.
  • the second data line 12 may be electrically connected to a plurality of sub-pixels Pxij arranged along the second direction Y, and is configured to provide data signals to the plurality of sub-pixels Pxij.
  • the plurality of first data lines 11 and the plurality of second data lines 12 may be arranged along the first direction X.
  • the plurality of first data lines 11 may be located outside the plurality of second data lines 12 in the first direction X.
  • the plurality of first data lines 11 are located on one side of the plurality of second data lines 12 close to the second boundary B2 and the third boundary B3 in the first direction X.
  • the display substrate may have a first centerline OO' in the first direction X.
  • the plurality of second data lines 12 may be located on one side of the plurality of first data lines 11 close to the first center line OO'.
  • the display area 100 may further include: a plurality of first data connection lines 13 extending along the first direction X and a plurality of second data connection lines 14 extending along the second direction Y.
  • Multiple first data lines 11 The plurality of first data connection lines 13 can be electrically connected to a plurality of first data connection lines 13 in a one-to-one correspondence, and the plurality of first data connection lines 13 can be electrically connected to a plurality of second data connection lines 14 in a one-to-one correspondence.
  • a first data line 11 can be electrically connected to a second data connection line 14 through a first data connection line 13 .
  • first data connection line 13 is electrically connected to the first data line 11
  • second data connection line 14 is electrically connected to the second data connection line 14 .
  • the second data connection line 14 may be located on a side of the electrically connected first data line 11 close to the first center line OO' in the first direction X.
  • the second data connection line 14 may be inserted between the plurality of second data lines 12 in the first direction X.
  • one second data connection line 14 may be arranged at intervals of four second data lines 12 in the first direction X.
  • this embodiment is not limited to this.
  • the display area 100 may include: a first area (eg, left half area) 100a and a second area (eg, right area) 100b located on both sides of the first center line OO'.
  • the length of the first data connection line 13 electrically connected to the first data line 11 far away from the first center line OO' may be longer than the length of the first data line 13 close to the first center line OO'. The length of the first data connection line 13 to which the line 11 is electrically connected.
  • the first data connection line 13 electrically connected to the first data line 11 far away from the first center line OO' may be located in the second direction Y close to the first data line 11 electrically connected to the first center line OO'.
  • a data connection line 13 is located away from the lower edge of the display area 100 .
  • the first region 100a and the second region 100b may be generally symmetrical about the first centerline OO'.
  • this embodiment is not limited to this.
  • the second data connection line 14 electrically connected to the first data line 11 away from the first center line OO' is in the first area 100a or the second area 100b.
  • the length of the second data connection line 14 electrically connected to the first data line 11 far away from the first center line OO' along the second direction Y may be greater than the length of the second data connection line 14 electrically connected to the first data line 11 close to the first center line OO'.
  • the length of the second data connection line 14 along the second direction Y may be greater than the length of the second data connection line 14 electrically connected to the first data line 11 close to the first center line OO'.
  • the plurality of first data lines 11 are arranged in order from the edge to the center along the first direction
  • the arrangement order of the second data connection lines 14 along the first direction X from the edge to the center is reversed.
  • the switching method of the first data line 11 shown in this example can be called a reverse insertion method.
  • the first data line 11 , the second data line 12 and the second data connection line 14 may have the same layer structure, for example, they may all be located on the second source-drain metal layer; the first data connection line 13 may be located on the first Source and drain metal layers.
  • this embodiment is not limited to this.
  • the first data line 11, the second data line 12 and the second data connection line 14 may be located on the first source-drain metal layer, and the first data connection line 13 may be located on the second source-drain metal layer.
  • the first data line 13 may be located on the first gate metal layer, the second gate metal layer, or the third gate metal layer.
  • the first fan-out area 201 may include: a plurality of first data fan-out lines 21 and a plurality of second data fan-out lines 22 .
  • the first data fan-out line 21 may be electrically connected to the second data connection line 14 extending to the first fan-out area 201 .
  • the second data fan-out line 22 may be electrically connected to the second data line 12 extending to the first fan-out area 201 .
  • the plurality of first data fan-out lines 21 may be interspersed between the plurality of second data fan-out lines 22 in the first direction X.
  • the arrangement order of the plurality of first data fan-out lines 21 and the plurality of second data lines 22 may be consistent with the arrangement order of the plurality of second data lines 12 and the plurality of second data connection lines 14 in the display area 100 .
  • one first data fan-out line 21 may be arranged at intervals of four second-numbered fan-out lines 22 in the first direction X.
  • this embodiment is not limited to this.
  • first data fan-out line 21 and the second data fan-out line 22 of the first fan-out area 201 may be located on the first gate metal layer or the second gate metal layer. Two adjacent data fan-out lines can be located on different conductive layers.
  • first data line 11 close to the left and right edges of the display area 100 from the display area 100 to the first fan-out area 201 through the first data connection line 13 and the second data connection line 14, it can be achieved
  • the first data lines 11 and the second data lines 12 at the edge of the display area 100 are collectively drawn out, thereby reducing the arrangement space occupied by the data fan-out lines in the first fan-out area 201 and reducing the size of the first fan-out area 201 length, reducing the size of the bottom border.
  • the bending area 202 may include: a plurality of first bending connection lines 23 and a plurality of second bending connection lines 24 .
  • the first bending connection line 23 and the second bending connection line 24 may extend along the second direction Y.
  • the first bending connection line 23 may be electrically connected to the first data fan-out line 21
  • the second bending connection line 24 may be electrically connected to the second data fan-out line 22 .
  • the arrangement sequence of the plurality of first bending connection lines 23 and the plurality of second bending connection lines 24 along the first direction The arrangement order of X can be consistent.
  • the second fan-out area 203 may include: a plurality of third data fan-out lines 25 , a plurality of fourth data fan-out lines 26 , and a plurality of lead-out transfer lines 27 .
  • the fourth data fan-out line 26 may be electrically connected to the second bending connection line 24 .
  • the third data fan-out line 25 may be electrically connected to the first bending connection line 23 .
  • the third data fan-out line 25 and the fourth data fan-out line 26 may extend to the first circuit area.
  • the third fan-out area may include: a plurality of fifth data fan-out lines 29 and a plurality of sixth data fan-out lines 28 .
  • the fifth data fan-out line 29 may be electrically connected to the third data fan-out line 25
  • the sixth data fan-out line 28 may be electrically connected to the fourth data fan-out line 26 .
  • the fifth data fan-out line 29 and the sixth data fan-out line 28 can be extended to the driver chip area 206 to be electrically connected to the connection pins of the driver chip area 206, and subsequently to be electrically connected to the integrated circuit.
  • the first data lead-out line may include: a first data fan-out line 21 , a first bent connection line 23 , a third data fan-out line 25 and a fifth data fan-out line 29 .
  • the second data lead-out line may include: a second data fan-out line 22 , a second bent connection line 24 , a fourth data fan-out line 26 and a sixth data fan-out line 28 .
  • FIG. 5 is an example diagram of wiring of a display substrate according to at least one embodiment of the present disclosure.
  • the first data lead line L1 is closest to the edge of the display substrate, and the first data lead line L2 is closest to the first center line. OO'.
  • the remaining first data lead-out lines are located between the first data lead-out lines L1 and L2.
  • the first data lead-out line L1 is electrically connected to the first data line 11
  • the first data lead-out line L2 is electrically connected to the first data line 11
  • 11 is close to the side of the first center line OO'
  • the first data line 11 electrically connected to the first data lead-out line L1 is provided with a plurality of first data lines 11 on the side away from the first center line OO', close to the first center
  • a plurality of second data lines 12 and a plurality of second data connection lines 14 are provided on one side of the line OO'.
  • the third data fan-out line 25 of the first data lead-out line L2 may be electrically connected to the lead-out adapter line 27 by extending at least along the first direction X.
  • the lead-out adapter line 27, the third data fan-out line 25 of the first data lead-out line L2 can be electrically connected to the fifth data fan-out line 29 close to the edge of the first frame area.
  • the third data fan-out line 25 of the first data lead-out line L1 may be electrically connected to the lead-out adapter line 27.
  • the third data fan-out line 25 of the first data lead-out line L1 may It is electrically connected to the fifth data fan-out line 29 away from the edge of the first frame area.
  • the sequence of the plurality of first data lead-out lines in the first fan-out area 201, the bending area 202 and the second fan-out area 203 near the bend area 202 is different from the order of the plurality of first data lead-out lines in the second fan-out area.
  • the order in the area of the area 203 close to the first circuit area 204 and the area of the third fan-out area 205 is reversed.
  • the plurality of lead-out adapter lines 27 may be substantially symmetrical about the first center line OO'.
  • FIG. 6 is a partial wiring diagram of the second fan-out area according to at least one embodiment of the present disclosure.
  • Figure 6 is a partial wiring diagram of area A1 in Figure 5.
  • the third data fan-out line 25 of the second fan-out area may include: a first lead-out line 251 and a second lead-out line 252 .
  • the first lead-out wire 251 and the second lead-out wire 252 may be electrically connected through the lead-out adapter wire 27 .
  • the lead-out adapter wire 27 may first extend along the first direction X, and then extend along the second direction Y toward a side away from the display area.
  • the lead-out adapter wire 27 may be of zigzag type.
  • the second lead-out line 252 of a third data fan-out line 25 may be located on a side of the first lead-out line 251 away from the first center line in the first direction X.
  • a first dummy wire 253 is also provided along the extension direction of the second direction Y, and the first dummy wire 253 is disconnected from the first lead-out wire 251 .
  • the fourth data fan-out line 26 of the second fan-out area may include: a third lead-out line 261 and a fourth lead-out line 262 .
  • the third lead-out line 261 may be electrically connected to the fourth lead-out line 262.
  • the third lead wire 261 may be electrically connected to the fourth lead wire 262 through a connection electrode.
  • this embodiment is not limited to this.
  • the third lead wire 261 and the fourth lead wire 262 may be an integral structure; or the third lead wire 261 may be directly electrically connected to the fourth lead wire 262 .
  • the plurality of second lead-out lines 252 may be located on a side of the plurality of fourth lead-out lines 262 close to the edge of the first frame area in the first direction X.
  • the arrangement order of the plurality of first lead lines 251 and the plurality of fourth data fan-out lines 26 along the first direction X may be the same as that of the plurality of third lead lines 261 .
  • a bending connection line 23 and a plurality of second bending connection lines 24 are arranged in the same order along the first direction
  • the arrangement order in the first direction X may be consistent with the arrangement order along the first direction X of the plurality of first data lines 11 and the plurality of second data lines 12 in the display area 100 .
  • the lead-out adapter wire 27 can be used to jumper the third data fan-out line 25, and the transmission sequence of the data signals can be adjusted, so that the transmission sequence of the data signals is consistent with the arrangement of the first data line and the second data line in the display area.
  • the layout sequence is consistent to adapt to conventional integrated circuits.
  • FIG. 7 is a partial schematic diagram of the first frame area according to at least one embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of the first data lead-out line and the second data lead-out line in FIG. 7 .
  • FIG. 7 and FIG. 8 only take several first data lead-out lines and second data lead-out lines as examples for illustration.
  • FIG. 9 is a partial schematic diagram of the first source and drain metal layer in FIG. 7 .
  • FIG. 10 is a partial schematic diagram of the second source-drain metal layer in FIG. 7 .
  • the first frame area may also include: a first power line 41 and a second power line 42 . At least part of the first power line 41 and at least part of the second power line 42 may be located in the second fan-out area 203 .
  • the first power line 41 can extend from the second fan-out area 203 along the second direction Y, bypassing the first circuit area 204 and the driver chip area 206 to the bonding pin area 207, and connects with the first power line in the bonding pin area 207.
  • the power pins are electrically connected.
  • the second power line 42 may be located on opposite sides of the first power line 41 in the first direction X.
  • the second power line 42 may, for example, be substantially symmetrical about a first centerline extending in the second direction Y.
  • the second power line 42 may extend from the second fan-out area 203 to the bonding pin area 207 along the second direction Y, and be electrically connected to the second power pin in the bonding pin area 207 .
  • the first power line 41 may be configured to continuously provide a high-level signal
  • the second power line 42 may be configured to continuously provide a low-level signal.
  • the lead-out adapter wire 27 may be located in the second fan-out area 203 , and two ends of the lead-out adapter wire 27 may be electrically connected to the first lead-out wire 251 and the second lead-out wire 252 respectively.
  • the orthographic projection of the plurality of lead-out transfer lines 27 on the substrate may overlap with the orthographic projection of the first power line 41 on the substrate.
  • the front projection of the first power line 41 on the substrate may overlap with the front projection of the plurality of first lead lines 251 on the substrate.
  • the connection position of the lead-out transfer line 27 and the second lead-out line 252 may not overlap with the front projection of the first power line 41 on the substrate.
  • the first lead wire 251 away from the edge of the first frame area along the first direction may be electrically connected to the lead-out adapter wire 27 away from the bending area 202 .
  • the first fan-out area 201 may also include: a first power connection line 31 and a second power connection line 32 .
  • the second power connection line 32 may be located on opposite sides of the first power connection line 31 in the first direction X.
  • the second power connection line 32 may extend along the edge of the display area 100 to the second frame area, and be electrically connected to the frame power lead in the second frame area.
  • the second power connection line 32 may be located on the first source-drain metal layer.
  • the first power connection line 31 can be electrically connected to a plurality of high potential power lines in the display area to provide power to the display.
  • the pixel circuits of multiple sub-pixels in the display area provide high-level power signals.
  • the first power connection line 31 may include: stacked fifth traces 311 and sixth traces 312 .
  • the fifth wiring 311 may be located on the first source-drain metal layer
  • the sixth wiring 312 may be located on the second source-drain metal layer.
  • the fifth trace 311 may have a plurality of first ventilation holes
  • the sixth trace 312 may have a plurality of second ventilation holes
  • the front projection of the first ventilation hole and the second ventilation hole on the substrate may be Rectangle, such as rounded rectangle.
  • the orthographic projection of the second vent hole on the substrate may overlap with the orthographic projection of the first vent hole on the substrate.
  • the fifth wiring 311 is provided with a plurality of first ventilation holes, which is beneficial to the gas discharge of the seventh insulating layer (the seventh insulation layer 507 in FIG. 14A to 14C) during the preparation process.
  • the sixth wiring 312 is provided with a plurality of first ventilation holes.
  • the second ventilation hole is conducive to the gas removal of the eighth insulating layer (not shown) during the preparation process and prevents film explosion.
  • the fifth trace 311 may be electrically connected to the sixth trace 312 through a plurality of via holes opened in the seventh insulation layer.
  • this embodiment is not limited to this.
  • the bending area 202 may further include: a plurality (eg, three) of third power connection lines 33 and a plurality (eg, four) of fourth power connection lines 34 .
  • the third power connection line 33 and the fourth power connection line 34 may have the same layer structure, for example, both are located on the second source-drain metal layer.
  • the third power connection line 33 may be electrically connected to the fifth wiring 311 of the first power connection line 31 .
  • the fourth power connection line 34 can be electrically connected to the second power connection line 32 .
  • the first power line 41 may include: stacked first traces 411 and second traces 412 .
  • the first wiring 411 may be located on the first source-drain metal layer
  • the second wiring 412 may be located on the second source-drain metal layer.
  • the first wiring 411 and the second wiring 412 are electrically connected.
  • the second wiring 412 and the third power connection line 33 may have an integrated structure.
  • the second power line 42 may include: stacked third traces 421 and fourth traces 422 .
  • the third wiring 421 may be located on the first source-drain metal layer
  • the fourth wiring 422 may be located on the second source-drain metal layer.
  • the third trace 421 and the fourth trace 422 may be electrically connected.
  • the fourth wiring 422 and the fourth power connection line 34 may have an integrated structure.
  • this embodiment is not limited to this.
  • FIG. 11 is a partial schematic view of the bending area and the second fan-out area in FIG. 7 .
  • FIG. 12 is a partially enlarged schematic diagram of area A2 in FIG. 11 .
  • FIG. 13A is a partially enlarged schematic view of the second fan-out area after forming the second gate metal layer in FIG. 12 .
  • FIG. 13B is a partially enlarged schematic diagram of the second fan-out area after forming the first source-drain metal layer in FIG. 12 .
  • FIG. 13C is a partially enlarged schematic diagram of the second fan-out area after forming the seventh insulating layer (the seventh insulating layer 507 in FIGS. 14A to 14C ) in FIG. 12 .
  • Figure 14A is a partial enlarged schematic diagram along the P-P' direction in Figure 12.
  • Figure 14B is a partial enlarged schematic diagram along the Q-Q' direction in Figure 12.
  • Figure 14C is a partial enlarged schematic diagram along the U-U' direction in Figure 12.
  • the first lead-out lines 251 of the third data fan-out lines may be interspersed with a plurality of fourth data fan-out lines 26 in the first direction X. between.
  • one first lead-out line 251 may be arranged at intervals between four fourth data fan-out lines 26 .
  • the second fan-out area also includes: a first dummy trace 253 aligned with the first lead-out line 251 in the second direction Y.
  • the first lead-out wire 251 and the first dummy wire 253 have the same layer structure, and they are disconnected.
  • the first dummy trace 253 may extend along the second direction Y to edges of the second fan-out area and the first circuit area.
  • the first dummy trace 253 may extend along the second direction Y to the starting position of the second lead-out line 252 .
  • the first dummy wire 253 is disconnected from the second lead wire 252 and has no electrical connection.
  • Two adjacent lines among the plurality of first lead-out lines 251 and the plurality of fourth data fan-out lines 26 may be located on different conductive layers. For example, as shown in FIG.
  • a first lead-out line 251 may be located on the first gate metal layer, and two fourth data fan-out lines 26 adjacent to the first lead-out line 251 may be located on the second gate metal layer.
  • the first lead-out line 251 and the fourth data fan-out line 26 can be arranged using two conductive layers, and adjacent traces are located on different conductive layers, which can achieve a compact arrangement of adjacent traces, which is beneficial to reducing
  • the layout space of the traces can also reduce the interference between adjacent traces.
  • the first trace 411 of the first power line may have a plurality of openings K1 .
  • the orthographic projection of the opening K1 on the substrate may be a rectangle, such as a rounded rectangle. exist In the first direction X from the edge of the first frame area toward the center, the distance between the plurality of openings and the bending area may gradually decrease.
  • the first connection electrode 61 may be disposed in the opening K1 of the first trace 411 .
  • the front projection of the first connection electrode 61 on the substrate may be located in the opening K1 and does not overlap with the front projection of the first wiring 411 on the substrate.
  • the first wiring 411 and the first connection electrode 61 may be in the same layer structure, for example, located on the first source-drain metal layer. As shown in FIG. 14B , the first connection trace 61 can pass through a plurality (for example, four) first via holes V1 opened in the fifth insulating layer 505 and a third via hole V1 located in the first gate metal layer (or the second gate metal layer). An outgoing wire 251 is electrically connected.
  • the fifth insulating layer 505 , the fourth insulating layer 504 , the third insulating layer 503 and the second insulating layer 502 in the first via hole V1 can be removed to expose the surface of the first lead wire 251 .
  • the second trace 412 of the first power line and the lead-out transition line 27 may be in the same layer structure, for example, may be located on the second source-drain metal layer. layer.
  • the lead-out adapter wire 27 may extend at least along the first direction X. For example, it may first extend along the first direction connect.
  • the lead-out transfer line 27 can be electrically connected to the first connection electrode 61 located on the first source-drain metal layer through the second via hole V2.
  • the sixth insulating layer 506 and the seventh insulating layer 507 in the second via hole V2 can be removed to expose the surface of the first connection electrode 61 .
  • the front projection of the lead-out adapter line 27 on the substrate overlaps with the front projection of the first trace 411 of the first power line on the substrate.
  • the first step can be realized. Minimize the impact on the first power line during the transfer process of the lead wire.
  • the second fan-out area may further include: a plurality of second dummy traces 63 extending along the first direction X.
  • the second dummy trace 63 may be located between adjacent lead-out transfer lines 27 in the first direction X.
  • the second dummy wire 63 may be adjacent to the lead-out transfer line 27 , and the second dummy wire 63 may be located on a side of the lead-out transfer line 27 away from the display area.
  • the plurality of lead-out transfer lines 27 may be located on a side of the first trace 411 of the first power line away from the substrate 101 , and the plurality of first lead-out lines 251 and the fourth The data fan-out line 26 may be located on a side of the first trace 411 close to the substrate 101 .
  • the first wiring 411 of the first power line can be used to isolate the lead-out adapter line 27 from the plurality of first lead-out lines 251 and the fourth data fan-out lines 26, which can effectively prevent crosstalk between the wirings.
  • using the first power line to isolate the lead-out adapter cable can isolate the pair of AC signals transmitted by the lead-out adapter cable.
  • the influence of the DC signal transmitted below the first trace can also be isolated from the influence of the AC signal transmitted below the first trace on the DC signal transmitted by the lead-out adapter cable.
  • a seventh insulation layer 507 and a sixth insulation layer 506 may be provided between the lead-out adapter wire 27 and the first trace 411 of the first power supply wire.
  • the seventh insulation layer 507 may be an organic insulation layer
  • the sixth insulation layer 506 may be an inorganic insulation layer.
  • the sixth insulating layer 506 may have a first groove V4 , and the sixth insulating layer 506 in the first groove V4 may be removed.
  • the seventh insulating layer 507 may be provided with a second groove V3, and the seventh insulating layer 507 in the second groove V3 may be removed.
  • the orthographic projection of the first groove V4 on the substrate 101 may be located within the orthographic projection range of the first trace 411 on the substrate 101 , and the orthographic projection of the second groove V3 on the substrate 101 is within the same range as the first trace 411 .
  • the orthographic projections of the lines 411 on the substrate 101 may partially overlap.
  • the seventh insulation layer 507 in the area on the side of the first trace 411 away from the display area may be removed.
  • the orthographic projection of the second trace 412 of the first power line on the substrate 101 and the orthographic projection of the edge of the sixth insulating layer 506 on the substrate 101 can be There is overlap to cover the boundary of the sixth insulating layer 506 .
  • the orthographic projection of the second trace 412 on the substrate 101 may overlap with the orthographic projection of the edge of the seventh insulation layer 507 on the substrate 101 .
  • the second trace 412 and the first trace 411 may directly contact each other in the overlapping area of the first groove V4 and the second groove V3.
  • the first power line adopts a double-layer wiring design, and the second wiring can cover part of the remaining boundaries of the seventh insulation layer and the sixth insulation layer, which can effectively reduce the risk of film peeling (Peeling). .
  • the first power line adopts a single-layer wiring design in the transition area between the first lead wire 251 and the lead adapter wire 27 .
  • the first power line may adopt a single-layer wiring design. Double-layer wiring design, and the first wiring 411 and the second wiring 412 may be in direct contact at least partially.
  • the second power line 42 may adopt a double-layer wiring design (ie, include stacked third wiring 421 and fourth wiring 422 ). At least parts of the third trace 421 and the fourth trace 422 may be in direct contact. At the edge of the orthographic projection of the third trace 421 and the fourth trace 422, the orthographic projection of the fourth trace 422 on the substrate may cover the edge of the sixth insulating layer, and cover at least part of the edge of the seventh insulating layer, so as to Effectively reduce the risk of film peeling.
  • the connection method of the third trace and the fourth trace of the second power line can be substantially the same as the connection method of the first trace and the second trace of the first power line, so the details will not be described again.
  • FIG. 15 is a schematic diagram of the connection between the lead-out adapter wire and the second lead-out wire according to at least one embodiment of the present disclosure.
  • the lead-out transfer line 27 located on the second source-drain metal layer can be connected to the second connection located on the first source-drain metal layer through via holes opened in the seventh insulating layer and the sixth insulating layer.
  • Electrode 62 is electrically connected.
  • the second connection electrode 62 may be electrically connected to the second lead line 252 located on the first gate metal layer through a via hole opened from the fifth insulating layer to the second insulating layer.
  • the second connection electrode 62 may be electrically connected to the second lead-out line 252 located on the second gate metal layer through via holes opened in the fifth insulating layer to the third insulating layer.
  • the connection position of the lead-out transfer line 27 and the second lead-out line 252 may not overlap with the front projection of the first power line on the substrate.
  • the connection position of the lead-out adapter wire 27 and the second lead-out wire 252 may be located on the side of the first power line away from the bending area.
  • this embodiment is not limited to this.
  • the connection position of the lead-out adapter wire 27 and the second lead-out wire 252 may be located on a side of the first power line close to the bending area.
  • the first wiring of the first power line may also have a plurality of openings, and the second connection electrode may be located in the openings to achieve electrical connection with the second lead-out wire and the lead-out adapter wire.
  • the structure of the display substrate is illustrated below through the preparation process of the display substrate.
  • the "patterning process" mentioned in this disclosure includes processes such as coating of photoresist, mask exposure, development, etching, and stripping of photoresist for metal materials, inorganic materials, or transparent conductive materials.
  • organic materials it includes Processes such as coating of organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition.
  • Coating can use any one or more of spraying, spin coating, and inkjet printing.
  • Etching can use dry etching and wet etching. Any one or more of them are not limited by this disclosure.
  • Thin film refers to a thin film produced by depositing, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer.” If the "thin film” requires a patterning process during the entire production process, it will be called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • a and B are of the same layer structure” mentioned in this disclosure means that A and B are formed at the same time through the same patterning process, or the distance between the surfaces of A and B close to the substrate and the substrate is basically the same, or A The surface of B and B close to the substrate is in direct contact with the same film layer.
  • the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A” or "the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the orthographic projection of A. within the bounds of A, or the bounds of the orthographic projection of A overlap with the bounds of the orthographic projection of B.
  • the preparation process of the display substrate may include the following operations.
  • the substrate may be a flexible substrate.
  • the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier.
  • the materials of the first flexible material layer and the second flexible material layer can be polyimide (PI), polyp Ethylene phthalate (PET) or surface-treated polymer soft film and other materials, the first inorganic material layer and the second inorganic material layer can be made of silicon nitride (SiNx) or silicon oxide (SiOx), etc.
  • the first inorganic material layer and the second inorganic material layer may also be called barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-si).
  • a-si amorphous silicon
  • the first semiconductor layer is deposited on the substrate, and the first semiconductor film is patterned through a patterning process to form a first semiconductor layer disposed on the substrate.
  • the first semiconductor layer may include an active layer of a low-temperature polysilicon thin film transistor located in a pixel circuit of the display area.
  • the first gate metal layer may at least include: a gate electrode of a low-temperature polysilicon thin film transistor of the pixel circuit in the display area and one of the electrodes of the storage capacitor, and a plurality of first data lines in the first fan-out area of the first frame area.
  • the second gate metal layer may include at least: another electrode of the storage capacitor of the pixel circuit in the display area, a plurality of first data fan-out lines and a plurality of second data in the first fan-out area of the first frame area.
  • adjacent traces among the plurality of first data fan-out lines and the plurality of second data fan-out lines in the first fan-out area may be located on different conductive layers.
  • Adjacent traces among the plurality of third data fan-out lines and the plurality of fourth data fan-out lines in the second fan-out area may be located on different conductive layers.
  • Adjacent traces among the plurality of fifth data fan-out lines and the plurality of sixth data fan-out lines in the third fan-out area may be located on different conductive layers.
  • a second semiconductor layer In some examples, on the substrate on which the foregoing pattern is formed, a third insulating film and a second semiconductor film are sequentially deposited, the second semiconductor film is patterned through a patterning process, a third insulating layer is formed and the third insulating film is disposed on the substrate. layer on the second semiconductor layer.
  • the second semiconductor layer may include a gate electrode of an oxide thin film transistor of a pixel circuit in the display area.
  • the third gate metal layer may at least include: a gate electrode of an oxide thin film transistor located in the pixel circuit of the display area.
  • a fifth insulating film is deposited on the substrate with the foregoing pattern formed, and a fifth insulating layer is formed through a patterning process; subsequently, a fourth metal film is deposited, and a first source and drain metal layer is formed through a patterning process.
  • the fifth insulating layer in the display area may be provided with a plurality of via holes, for example, the surface of the first semiconductor layer, the first gate metal layer, the second gate metal layer, the third gate metal layer or the second semiconductor layer may be exposed. For example, at least part of the first to fifth insulating layers in the bending area of the first frame area are removed.
  • the first source-drain metal layer may include: a plurality of connection electrodes of the pixel circuit in the display area and a plurality of first data connection lines, and a first power connection line of the first fan-out area of the first frame area. Five traces and a second power connection line, a plurality of first connection electrodes located in the second fan-out area, a plurality of second connection electrodes, a first trace of the first power line and a third trace of the second power line .
  • a sixth insulating film is deposited, and a sixth insulating layer is formed through a patterning process; subsequently, a seventh insulating film is coated, and a seventh insulating layer is formed through a patterning process; and then , deposit a fifth metal film, and form a second source-drain metal layer through a patterning process; then, apply an eighth insulating film, and form an eighth insulating layer through a patterning process.
  • the second source-drain metal layer may include: a plurality of first data lines located in the display area, a plurality of second data lines and a plurality of second data connection lines, and a first fan-out located in the first frame area.
  • the sixth wiring of the first power connection line in the bending area, the first bending connection line, the second bending connection line, the third power connection line and the fourth power connection line located in the bending area, and the second fan-out The lead-out adapter cable of the area, the second trace of the first power cable, and the fourth trace of the second power cable.
  • the circuit structure layer can be prepared in the display area of the substrate.
  • a first conductive film is deposited on the substrate on which the foregoing pattern is formed, and the first conductive film is patterned through a patterning process to form an anode layer.
  • the anode layer includes anodes of a plurality of light emitting elements.
  • the anode can be electrically connected to the pixel circuit through a via hole opened in the eighth insulation layer.
  • the pixel definition film is coated, and the pixel definition layer is formed through masking, exposure, and development processes.
  • the pixel definition layer of the display area has a plurality of pixel openings exposing the anode layer.
  • an organic light-emitting layer and a cathode layer are sequentially formed in the display area.
  • the organic light-emitting layer is formed in the pixel opening to connect the organic light-emitting layer to the anode.
  • the cathode is formed on the pixel definition layer and connected to the organic light-emitting layer.
  • the packaging structure layer may include a stack structure of inorganic material/organic material/inorganic material.
  • the material of the first semiconductor layer may include polysilicon.
  • the material of the second semiconductor layer may include metal oxide.
  • the first gate metal layer, the second gate metal layer, the third gate metal layer, the first source-drain metal layer and the second source-drain metal layer can be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al ) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, Such as Mo/Cu/Mo, etc.
  • the first to sixth insulating layers may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite. layer.
  • the seventh insulating layer and the eighth insulating layer may be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate.
  • the pixel definition layer can be made of organic materials such as polyimide, acrylic or polyethylene terephthalate.
  • the anode layer can be made of reflective materials such as metal, and the cathode can be made of transparent conductive materials. However, this embodiment is not limited to this.
  • the structure of the display substrate and its preparation process in this embodiment are only illustrative. In some examples, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs.
  • the preparation process of this exemplary embodiment can be implemented using currently mature preparation equipment and is well compatible with existing preparation processes. The process is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield rate.
  • the display substrate provided in this embodiment can use lead-out adapter lines to adjust the transmission sequence of data signals, so that the order of providing data signals or test data signals in the first frame area is consistent with the order of the first data lines and the second data lines in the display area. consistent and reduce impact on the first power line.
  • the wiring method of the data lead-out lines in this example is beneficial to improving the sudden change of wiring resistance.
  • crosstalk between data signals can be effectively prevented.
  • FIG. 16 is another wiring schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • the second data connection line 14 electrically connected to the first data line 11 away from the first center line OO' is in the first area 100a or the second area 100b.
  • the second data connection line 14 electrically connected to the first data line 11 close to the first center line OO' may be located on a side away from the first center line OO'.
  • the plurality of first data lines 11 are arranged sequentially along the first direction X from the edge to the center.
  • the arrangement sequence from the edge to the center along the first direction The switching method of the first data line 11 shown in this example can be called a positive sequence insertion method.
  • the second data connection line 14 electrically connected to the first data line 11 away from the first center line OO' is along the second direction.
  • the length Y may be smaller than the length along the second direction Y of the second data connection line 14 electrically connected to the first data line 11 close to the first center line OO'.
  • the first data connection line 13 electrically connected to the first data line 11 far away from the first center line OO' may be located in the second direction Y close to the first data line 11 electrically connected to the first center line OO'.
  • a data connection line 13 is close to one side of the lower edge of the display area 100 .
  • the third data fan-out line 25 located in the second fan-out area 203 may include a first lead-out line and a second lead-out line, and the first lead-out line and the second lead-out line may be switched by lead-out lines.
  • Wiring 27 is electrically connected.
  • the lead-out adapter wire 27 electrically connected to the first lead-out wire close to the first center line OO' can be located far away from the lead-out adapter wire 27 electrically connected to the first lead-out wire OO' in the second direction Y.
  • the lead-out transfer line 27 in the second fan-out area 203 may overlap with the front projection of the first power line on the substrate.
  • FIG. 17 is another wiring schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • the second data connection line 14 electrically connected to the first data line 11 away from the first center line OO' is along the second direction.
  • the length of Y may be greater than the length of the second data connection line 14 along the second direction Y to which the first data line 11 close to the first center line OO' is electrically connected.
  • the first data connection line 13 electrically connected to the first data line 11 far away from the first center line OO' may be located in the second direction Y close to the first data line 11 electrically connected to the first center line OO'.
  • a data connection line 13 is located away from the lower edge of the display area 100 .
  • the remaining structure of the display substrate of this embodiment is substantially the same as that of the embodiment shown in FIG. 16 .
  • Fig. 18 is a partial schematic diagram of the second fan-out area in Fig. 16 or 17.
  • the third data fan-out line 25 located in the second fan-out area 203 may include a first lead-out line and a second lead-out line, and the first lead-out line and the second lead-out line may They are electrically connected through lead-out adapter wires 27 .
  • the lead-out adapter wire 27 electrically connected to the first lead-out wire close to the first center OO' may be located far away from the first center line OO' in the second direction Y.
  • the lead-out adapter wire 27 electrically connected to the first lead-out wire OO' can be located away from the bend.
  • the switching method of the first data line shown in this example is a positive sequence insertion method.
  • the lead-out transfer line 27 may overlap with the front projection of the first power line 41 on the substrate in the second fan-out area 203 .
  • the first power line 41 may include first wiring lines 411 and second wiring lines 412 .
  • the first trace 411 may have a plurality of openings, and the connection position of the lead-out transfer line 27 and the first lead-out line may be located within the opening in the orthographic projection of the substrate without overlapping the first trace 411 .
  • the first power line 41 may adopt a double-layer wiring structure of the first wiring 411 and the second wiring 412 .
  • FIG. 19 is a resistance change curve diagram of multiple data lead-out lines in the first frame area.
  • FIG. 20 is a resistance change curve diagram of multiple data lead lines in the first frame area after resistance compensation.
  • the abscissa in Figures 19 and 20 represents the number of the data lead-out lines along the first direction, and the ordinate represents the resistance value.
  • the curve L11 represents the resistance change of the data lead-out line after the display substrate adopts the reverse-sequence insertion method in the first frame area and uses the lead-out adapter line as shown in FIG. 4 .
  • Curve L12 represents the resistance change of the data lead-out line after the display substrate using the forward-sequence interpolation method is transferred by the lead-out transfer line in the first frame area as shown in FIG. 16 or FIG. 17 .
  • Curve L13 represents the resistance change of the data lead-out line after the display substrate using the reverse-sequence insertion method does not use the lead-out adapter wire in the first frame area but uses the updated integrated circuit. It can be seen from Figure 19 that the resistance jump conditions from small to large are: curve L11, curve L12 and curve L13.
  • curve L11 when performing resistance compensation, curve L11 requires fewer points to be compensated, and the resistance difference is small (for example, only 166 ⁇ ), which is easy to compensate and requires less compensation space. Conducive to display substrate The lower border is narrowed.
  • curve L12 since no lead-out adapter wire is used to perform a jumper design on the first data lead-out line, the first data lead-out line is interspersed in the second data lead-out line, and the positions are relatively scattered, resulting in a huge workload of resistance compensation.
  • Curve L13 requires more compensation points and a larger resistance difference (for example, the maximum difference is about 983 ⁇ ), requiring a larger compensation space.
  • the curve L21 represents the change of the data lead-out line after resistance compensation after the data lead-out line is transferred using the lead-out adapter line in the first frame area as shown in Figure 4, using the reverse order insertion method.
  • Curve L22 represents the change of the data lead-out line after the resistance compensation is performed after the data lead-out line is transferred by the lead-out adapter line in the first frame area as shown in FIG. 16 or FIG. 17 using the positive sequence insertion method.
  • the transition of curve L21 is smoother than that of curve L22. Therefore, the solution of using the lead-out transfer line for the display substrate using the reverse sequence insertion method in the first frame area is better than the solution using the forward sequence insertion method.
  • the display substrate is transferred using lead-out transfer lines in the first frame area. This embodiment is not limited to the resistance compensation method adopted.
  • the display substrate of the embodiment of the present disclosure can be applied in a display device with a pixel circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display ( QDLED), etc., this disclosure is not limited here.
  • a pixel circuit such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display ( QDLED), etc.
  • An embodiment of the present disclosure also provides a display device, which may include the aforementioned display substrate.
  • the display device may be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • the embodiments of the present invention are not limited thereto.

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Abstract

一种显示基板，包括：显示区域（100）和边框区域，边框区域包括位于显示区域（100）一侧的第一边框区域（200）。显示区域（100）包括：多个子像素（Pxij）、多条第一数据线（11）、多条第二数据线（12）、多条第一数据连接线（13）以及多条第二数据连接线（14）。多条第一数据线（11）通过多条第一数据连接线（13）与多条第二数据连接线（14）电连接。第一边框区域（200）包括：多条第一数据引出线（L1，L2）、多条第二数据引出线、多条引出转接线（27）以及至少一条第一电源线（41）。第一数据引出线（L1，L2）包括：第一引出线（251）和第二引出线（252）。第一引出线（251）通过引出转接线（27）与第二引出线（252）电连接。至少一条引出转接线（27）在衬底的正投影与第一电源线（41）在衬底（101）的正投影存在交叠。

Description

显示基板及显示装置
本申请要求于2022年7月15日提交中国专利局、申请号为202210836718.9、发明名称为“显示基板及显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及显示装置。
背景技术
有机发光二极管(OLED，Organic Light Emitting Diode)和量子点发光二极管(QLED，Quantum-dot Light Emitting Diodes)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示基板及显示装置。
一方面，本实施例提供一种显示基板，包括：衬底、多个子像素、多条第一数据线、多条第二数据线、多条第一数据连接线、多条第二数据连接线、多条第一数据引出线、多条第二数据引出线、多条引出转接线以及至少一条第一电源线。衬底包括：显示区域和边框区域，边框区域包括位于所述显示区域一侧的第一边框区域。所述显示区域具有靠近所述第一边框区域的第一边界，所述边框区域具有第二边界和第三边界，所述第二边界和第三边界在第一方向上位于所述第一边界的两侧。多个子像素、多条第一数据线、多条第二数据线、多条第一数据连接线以及多条第二数据连接线位于所述显示区域。所述多条第一数据线和所述多条第二数据线被配置为向所述多个子像素提供数据信号。所述多条第一数据连接线沿第一方向延伸，所述多条第一数据线、多条第二数据线和多条第二数据连接线沿第二方向延伸，所述第一方向与第二方向交叉。所述多条第一数据线通过所述多条第一数据连接线与所述多条第二数据连接线电连接。所述多条第一数据线在所述第一方向上位于所述多条第二数据线和所述多条第二数据连接线靠近所述第二边界或所述第三边界的一侧。多条第一数据引出线、多条第二数据引出线、多条引出转接线以及至少一条第一电源线位于所述第一边框区域。所述多条第一数据引出线与所述多条第二数据连接线电连接，所述多条第二数据引出线与所述多条第二数据线电连接。所述至少一条第一电源线被配置为向所述多个子像素提供电源信号。所述多条第一数据引出线中的至少一条第一数据引出线包括：第一引出线和第二引出线，所述第一引出线通过所述引出转接线与所述第二引出线电连接，所述第一引出线与所述第二数据连接线电连接，所述引出转接线至少部分沿所述第一方向延伸，所述第二引出线在所述第一方向上位于所述第二数据引出线靠近所述第二边界或第三边界的一侧。多条引出转接线中的至少一条引出转接线在所述衬底的正投影与所述第一电源线在所述衬底的正投影存在交叠。
在一些示例性实施方式中，所述第一电源线至少包括：第一走线；所述第一走线具有多个开口，所述第一引出线与所述引出转接线的连接位置在所述衬底的正投影位于所述开口在所述衬底的正投影范围内。
在一些示例性实施方式中，所述第一数据引出线中的至少部分线段和所述第二数据引出线中的至少部分线段位于所述第一走线靠近所述衬底的一侧，所述引出转接线位于所述第一走线远离所述衬底的一侧。
在一些示例性实施方式中，所述引出转接线与所述第一走线之间至少设置有机绝缘层。
在一些示例性实施方式中，所述第一引出线通过第一连接电极与所述引出转接线电连接，所述第一连接电极位于所述开口内，所述第一连接电极在所述衬底的正投影与所述第一走线在所述衬底的正投影没有交叠。
在一些示例性实施方式中，所述第一连接电极与所述第一走线为同层结构。
在一些示例性实施方式中，所述第一数据引出线和所述第二数据引出线在所述衬底的正投影与所述第一走线在所述衬底的正投影存在交叠。
在一些示例性实施方式中，所述第一电源线还包括：位于所述第一走线远离所述衬底一侧的第二走线，所述第二走线与所述第一走线电连接，所述第二走线在所述衬底的正投影与所述第一走线的开口在所述衬底的正投影没有交叠。
在一些示例性实施方式中，所述第二走线与所述引出转接线为同层结构。
在一些示例性实施方式中，所述第一走线与所述第二走线之间设置有至少一个绝缘层，所述第一走线的至少部分与所述第二走线直接接触，所述第二走线在所述衬底的正投影覆盖所述至少一个绝缘层的边界的至少部分。
在一些示例性实施方式中，所述至少一个绝缘层包括：无机绝缘层和有机绝缘层，所述无机绝缘层位于所述有机绝缘层靠近所述衬底的一侧。
在一些示例性实施方式中，所述显示基板在所述第一方向上具有第一中心线。所述多条第一数据线在所述第一方向上位于所述多条第二数据线和所述多条第二数据连接线远离所述第一中心线的一侧，所述多条第二引出线在所述第一方向上位于所述第二数据引出线远离所述第一中心线的一侧。
在一些示例性实施方式中，所述显示区域包括：位于所述第一中心线两侧的第一区域和第二区域。在所述第一区域或第二区域内，远离所述第一中心线的第一数据线所电连接的第二数据连接线，位于靠近所述第一中心线的第一数据线电连接的第二数据连接线靠近所述第一中心线的一侧。
在一些示例性实施方式中，所述显示区域包括：位于所述第一中心线两侧的第一区域和第二区域；在所述第一区域或第二区域内，远离所述第一中心线的第一数据线所电连接的第二数据连接线，位于靠近所述第一中心线的第一数据线电连接的第二数据连接线远离所述第一中心线的一侧。
在一些示例性实施方式中，靠近所述第一中心线的第一引出线所电连接的引出转接线，位于远离所述第一中心线的第一引出线所电连接的引出转接线靠近所述显示区域的一侧。
在一些示例性实施方式中，靠近所述第一中心线的第一引出线所电连接的引出转接线，位于远离所述第一中心线的第一引出线所电连接的引出转接线远离所述显示区域的一侧。
在一些示例性实施方式中，所述多条引出转接线关于所述第一中心线对称。
在一些示例性实施方式中，所述第一边框区域至少包括：沿着远离所述显示区域的方 向依次设置的第一扇出区、弯折区、第二扇出区以及第一电路区；所述第一电路区至少包括测试电路；所述第一电源线和引出转接线至少位于所述第二扇出区。
在一些示例性实施方式中，所述第一引出线和第二引出线位于所述第二扇出区。
在一些示例性实施方式中，所述第二引出线与所述引出转接线的连接位置在所述衬底的正投影与所述第一电源线在所述衬底的正投影没有交叠。
在一些示例性实施方式中，所述第二引出线与所述引出转接线的连接位置位于所述第一电源线远离所述弯折区的一侧。
另一方面，本实施例提供一种显示装置，包括如上所述的显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开至少一实施例的一种显示装置的结构示意图；
图2为本公开至少一实施例的一种显示基板的结构示意图；
图3为本公开至少一实施例的显示基板的显示区域的剖面结构示意图；
图4为本公开至少一实施例的显示基板的走线示意图；
图5为本公开至少一实施例的显示基板的走线示例图；
图6为本公开至少一实施例的第二扇出区的局部走线示意图；
图7为本公开至少一实施例的第一边框区域的局部示意图；
图8为图7中的第一数据引出线和第二数据引出线的示意图；
图9为图7中第一源漏金属层的局部示意图；
图10为图7中第二源漏金属层的局部示意图；
图11为图7中弯折区和第二扇出区的局部示意图；
图12为图11中区域A2的局部放大示意图；
图13A为图12中形成第二栅金属层后的第二扇出区的局部放大示意图；
图13B为图12中形成第一源漏金属层后的第二扇出区的局部放大示意图；
图13C为图12中形成第七绝缘层后的第二扇出区的局部放大示意图；
图14A为图12中沿P-P’方向的局部放大示意图；
图14B为图12中沿Q-Q’方向的局部放大示意图；
图14C为图12中沿U-U’方向的局部放大示意图；
图15为本公开至少一实施例的引出转接线与第二引出线之间的连接示意图；
图16为本公开至少一实施例的显示基板的另一走线示意图；
图17为本公开至少一实施例的显示基板的另一走线示意图；
图18为图16或图17中第二扇出区的局部示意图；
图19为第一边框区域的多条数据引出线的电阻变化曲线图；
图20为第一边框区域的多条数据引出线进行电阻补偿之后的电阻变化曲线图。
详述
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏极、沟道区域以及源极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。另外，栅极还可以称为控制极。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本说明书中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。在本说明书中，“大致相同”是指数值相差10％以内的情况。
图1为本公开至少一实施例的一种显示装置的结构示意图。如图1所示，显示装置可以包括：时序控制器、数据驱动器、扫描驱动器、发光驱动器和显示基板。时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接。数据驱动器分别与多个数据线(例如，D1到Dn)连接，扫描驱动器分别与多个扫描线(例如，S1到Sm)连接，发光驱动器分别与多个发光控制线(例如，E1到Eo)连接。其中，n、m和o可以是自然数。显示基板包括像素阵列，像素阵列可以包括多个子像素Pxij，i和j可以是自然数。至少一个子像素Pxij可以包括：像素电路和与像素电路连接的发光元件。像素电路可以分别与扫描线、发光控制线和数据线连接。
在一些示例性实施例中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发光控制起始信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号。发光驱动器可以通过从时序控制器接收时钟信号、发光控制起始信号等来产生将提供到发光控制线E1、E2、E3、……和Eo的发光控制信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光控制线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发光控制起始信号传输到下一级电路的方式产生发光控制信号。
图2为本公开至少一实施例的一种显示基板的结构示意图。如图2所示，显示基板可以包括：显示区域100、位于显示区域100周边的边框区域。边框区域可以包括：位于显示区域100一侧的第一边框区域200以及位于显示区域100其它侧的第二边框区域300。第一边框区域200和第二边框区域300连通围绕在显示区域100的四周。在一些示例中，显示区域100可以是平坦的区域，包括组成像素阵列的多个子像素Pxij，多个子像素Pxij可以被配置为显示动态图片或静止图像，显示区域100可以称为有效区域(AA，Active Area)。在一些示例中，显示基板可以采用柔性基板，因而显示基板可以是可变形的，例如卷曲、弯曲、折叠或卷起。
在一些示例中，如图2所示，显示区域100具有靠近第一边框区域200的第一边界B1、靠近第二边框区域300的第六边界B6、第七边界B7和第八边界B8。第一边界B1可以连接在第六边界B6和第七边界B7之间，第八边界B8可以连接在第六边界B6和第七边界B7之间。第一边界B1和第八边界B8可以沿第二方向Y相对，第六边界B6和第七边界B7可以沿第一方向X相对。第六边界B6和第七边界B7在第一方向X上可以位于第一边界B1的两侧。边框区域可以具有第二边界B2、第三边界B3、第四边界B4和 第五边界B5。第四边界B4可以连接在第二边界B2和第三边界B3之间，第五边界B5可以连接在第二边界B2和第三边界B3之间。第二边界B2和第三边界B3在第一方向X上相对，第二边界B2和第三边界B3在第一方向X上可以位于第一边界B1的两侧。
在一些示例性实施例中，如图2所示，第一边框区域200可以包括沿着远离显示区域100的第二方向Y依次设置的第一扇出区201、弯折区202、第二扇出区203、第一电路区204、第三扇出区205、驱动芯片区206和绑定引脚区207。第一扇出区201可以连接到显示区域100，至少包括多条数据扇出线，多条数据扇出线被配置为以扇出走线方式连接显示区域100的数据线。弯折区202连接在第一扇出区201和第二扇出区203之间，弯折区202可以包括设置有凹槽的复合绝缘层，被配置为使第二扇出区203至绑定引脚区207弯折到显示区域100的背面。第二扇出区203可以至少包括以扇出走线方式引出的多条数据扇出线。第二扇出区203连接在弯折区202和第一电路区204之间。第一电路区204可以包括：防静电电路和测试电路。防静电电路可以被配置为通过消除静电防止显示基板的静电损伤。测试电路可以配置为给显示区域100的数据线提供数据测试信号。第三扇出区205可以至少包括以扇出走线方式引出的多条数据扇出线。第三扇出区205连接在第一电路区204和驱动芯片区206之间。驱动芯片区206可以设置集成电路(IC，Integrated Circuit)，集成电路可以被配置为与第三扇出区205的多条数据扇出线连接。绑定引脚区207可以包括：多个绑定焊盘(Bonding Pad)，绑定焊盘可以被配置为与外部的柔性线路板(FPC，Flexible Printed Circuit)绑定连接。驱动芯片区206和绑定引脚区207之间可以设置有连接走线。
在一些示例性实施例中，第二边框区域300可以包括：沿着远离显示区域100的第一方向X依次设置的第二电路区、电源线区、裂缝坝区和切割区。第一方向X与第二方向Y交叉，例如，第一方向X垂直于第二方向Y。第二电路区连接到显示区域100，可以至少包括栅极驱动电路，栅极驱动电路与显示区域100中像素电路所连接的第一扫描线、第二扫描线和发光控制线连接。电源线区连接到第二电路区，可以至少包括边框电源引线，边框电源引线沿着平行于显示区域边缘的方向延伸，与显示区域100中的阴极连接。裂缝坝区连接到电源线区，可以至少包括在复合绝缘层上设置的多个裂缝。切割区连接到裂缝坝区，可以至少包括在复合绝缘层上设置的切割槽，切割槽被配置为在显示基板的所有膜层制备完成后，切割设备分别沿着切割槽进行切割。
在一些示例性实施例中，第一边框区域200中的第一扇出区201和第二边框区域300中的电源线区可以设置有第一隔离坝和第二隔离坝，第一隔离坝和第二隔离坝可以沿着平行于显示区域边缘的方向延伸，形成环绕显示区域100的环形结构。显示区域边缘是显示区域100靠近第一边框区域200或者第二边框区域300一侧的边缘。
在一些示例性实施方式中，显示基板可以包括以矩阵方式排布的多个像素单元。至少一个像素单元可以包括出射不同颜色的三个子像素。例如，一个像素单元可以包括：红色子像素、绿色子像素和蓝色子像素。或者，至少一个像素单元可以包括四个子像素，例如可以包括：红色子像素、蓝色子像素和两个绿色子像素，或者，可以包括红色子像素、绿色子像素、蓝色子像素和白色子像素。每个子像素可以包括像素电路和发光元件。例如，像素电路可以分别与扫描线、数据线和发光控制线连接，像素电路可以被配置为在扫描线和发光控制线的控制下，接收数据线传输的数据电压，向发光元件输出相应的电流。每个子像素中的发光元件分别与所在子像素的像素电路连接，发光元件被配置为响应所在子像素的像素电路输出的电流发出相应亮度的光。在一些示例中，子像素的发光元件的形状可以是矩形状、菱形、五边形或六边形。当一个像素单元包括三个子像素时，三个子像素的发光元件可以采用水平并列、竖直并列或品字等方式排列。当一个像素单元包括四个子像 素时，四个子像素的发光元件可以采用钻石形(Diamond)方式排列，形成RGBG像素排列，或者可以采用水平并列、竖直并列或正方形等方式排列。然而，本公开在此不做限定。
图3为本公开至少一实施例的显示基板的显示区域的剖面结构示意图。图3示意了显示区域100中三个子像素的结构。在一些示例中，如图3所示，在垂直于显示基板的方向上，显示基板可以包括：衬底101、依次设置在衬底101上的电路结构层102、发光结构层103以及封装结构层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如触控结构层等，本公开在此不做限定。
在一些示例性实施例中，如图3所示，衬底101可以是柔性基底，或者可以是刚性基底。每个子像素的电路结构层102可以包括由多个晶体管和存储电容构成的像素电路。每个子像素的发光结构层103可以至少包括阳极301、像素定义层302、有机发光层303和阴极304，阳极301与像素电路连接，有机发光层303与阳极301连接，阴极304与有机发光层303连接，有机发光层303在阳极301和阴极304驱动下出射相应颜色的光线。封装结构层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，形成无机材料/有机材料/无机材料叠层结构，可以保证外界水汽无法进入发光结构层103。
在一些示例性实施例中，有机发光层303可以包括发光层(EML)以及如下任意一层或多层：空穴注入层(HIL)、空穴传输层(HTL)、电子阻挡层(EBL)、空穴阻挡层(HBL)、电子传输层(ETL)和电子注入层(EIL)。在一些示例中，所有子像素的空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层中的一层或多层可以是各自连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是相互隔离的。
在一些示例性实施例中，像素电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。其中，上述电路结构中的T指的是薄膜晶体管，C指的是电容，T前面的数字代表电路中薄膜晶体管的数量，C前面的数字代表电路中电容的数量。在一些示例中，像素电路中的多个晶体管可以是P型晶体管，或者可以是N型晶体管。像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示基板的工艺难度，提高产品的良率。在另一些示例中，像素电路中的多个晶体管可以包括P型晶体管和N型晶体管。
在一些示例中，像素电路中的多个晶体管可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，即LTPS+Oxide(简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在一些示例，以像素电路的多个晶体管包括低温多晶硅薄膜晶体管和氧化物薄膜晶体管为例。在垂直于显示基板的方向上，电路结构层可以包括：依次设置在衬底上的第一半导体层、第一绝缘层、第一栅金属层、第二绝缘层、第二栅金属层、第三绝缘层、第二半导体层、第四绝缘层、第三栅金属层、第五绝缘层、第一源漏金属层、第六绝缘层、第七绝缘层、第二源漏金属层和第八绝缘层。在一些示例中，第一半导体层可以包括：像素电路的低温多晶硅薄膜晶体管的有源层。第一栅金属层可以包括：像素电路的低温多晶硅薄膜晶体管的栅极以及存储电容的其中一个电极。第二栅金属层可以包括：像素电路的存储电容的另一个电极。第二半导体层可以包括：像素电路的氧化物薄膜晶体管的有源层。第 三栅金属层可以包括：像素电路的氧化物薄膜晶体管的栅极。第一源漏金属层可以包括：多个连接电极。第二源漏金属层可以包括：阳极连接电极。第二源漏金属层的阳极连接电极可以通过第八绝缘层开设的过孔与发光结构层的对应的阳极电连接。在一些示例中，第一绝缘层至第六绝缘层可以为无机绝缘层，第七绝缘层和第八绝缘层可以为有机绝缘层，还可以称为平坦层。然而，本实施例对此并不限定。
随着OLED显示技术的发展，消费者对显示产品显示效果的要求越来越高，极窄边框成为显示产品发展的新趋势，因此边框的窄化甚至无边框设计在OLED显示产品设计中越来越受到重视。一种显示基板中，第一边框区域通常包括沿着远离显示区域的方向依次设置的第一扇出区、弯折区、第二扇出区、第一电路区、第三扇出区、驱动芯片区和绑定引脚区。由于第一边框区域的宽度(沿第一方向X的长度)小于显示区域的宽度(沿第一方向X的长度)，第一边框区域中集成电路和绑定焊盘的信号线需要通过扇出区以扇出(Fanout)走线方式才能引入到较宽的显示区域，显示区域与第一边框区域的宽度差距越大，扇形区中斜向引出线越多，驱动芯片区与显示区域之间的距离就越大，因而第一扇形区占用空间较大，导致第一边框区域的窄化设计难度较大。为了改善上述情况，可以在显示区域内设置数据连接线，使得第一边框区域的数据引出线通过数据连接线与数据线电连接，可以有效减小第一扇出区的长度，从而大大缩减下边框的尺寸。然而，在通过数据连接线对数据线进行转接的过程中，第一边框区域内的数据引出线的顺序会被打乱，使得第一边框区域的数据引出线的顺序不同于显示区域的数据线的顺序，导致无法兼容常规集成电路，而且存在数据信号的传输走线的电阻突变等问题。
本公开实施例提供一种显示基板，包括：衬底、多个子像素、多条第一数据线、多条第二数据线、多条第一数据连接线、多条第二数据连接线、多条第一数据引出线、多条第二数据引出线、多条引出转接线以及第一电源线。衬底包括：显示区域和边框区域，边框区域包括位于显示区域一侧的第一边框区域。显示区域具有靠近第一边框区域的第一边界，边框区域具有第二边界和第三边界，第二边界和第三边界在第一方向上位于第一边界的两侧。多个子像素、多条第一数据线、多条第二数据线、多条第一数据连接线以及多条第二数据连接线位于显示区域。多条第一数据线和多条第二数据线被配置为向多个子像素提供数据信号。多条第一数据连接线沿第一方向延伸，多条第一数据线、多条第二数据线和多条第二数据连接线沿第二方向延伸。第一方向与第二方向交叉，例如，第一方向垂直于第二方向。多条第一数据线通过多条第一数据连接线与多条第二数据连接线电连接。多条第一数据线在第一方向上位于多条第二数据线和多条第二数据连接线靠近第二边界或第三边界的一侧。多条第一数据引出线、多条第二数据引出线、多条引出转接线以及至少一条第一电源线位于第一边框区域。多条第一数据引出线与多条第二数据连接线电连接。多条第二数据引出线与多条第二数据线电连接。至少一条第一电源线被配置为向多个子像素提供电源信号。多条第一数据引出线中的至少一条第一数据引出线包括：第一引出线和第二引出线。第一引出线通过引出转接线与第二引出线电连接。第一引出线与第二数据连接线电连接。引出转接线至少部分沿第一方向延伸，第二引出线在第一方向上位于第二数据引出线靠近第二边界或第三边界的一侧。多条引出转接线中的至少一条引出转接线在衬底的正投影与第一电源线在衬底的正投影存在交叠。
本实施例提供的显示基板，在第一边框区域利用引出转接线电连接第一引出线和第二引出线，来调整第一数据引出线和第二数据引出线沿第一方向的顺序，使得第一边框区域内的数据信号或测试数据信号的提供顺序与显示区域内的第一数据线和第二数据线的顺序保持一致，以实现对常规集成电路的兼容，从而节省成本。而且，可以在一定程度上改善数据信号的传输走线的电阻突变情况。
在一些示例性实施方式中，第一电源线至少可以包括：第一走线。第一走线具有多个开口，第一引出线与引出转接线的连接位置在衬底的正投影可以位于开口在衬底的正投影范围内。在本示例中，对第一电源线的第一走线进行挖孔设计来实现引出转接线排布，可以降低对第一电源线的影响。
在一些示例性实施方式中，第一数据引出线中的至少部分线段和第二数据引出线中的至少部分线段可以位于第一走线靠近衬底的一侧，引出转接线可以位于第一走线远离衬底的一侧。在本示例中，引出转接线在衬底的正投影与多条数据引出线在衬底的正投影可以存在交叠，利用第一电源线的第一走线来隔离数据引出线和引出转接线，可以有效防止走线之间的相互串扰。
在一些示例性实施方式中，引出转接线与第一电源线的第一走线之间至少可以设置有机绝缘层。在本示例中，通过在引出转接线和第一电源线的第一走线之间设置有机绝缘层，可以增大引出转接线和第一电源线的第一走线之间的介质层，有利于减少两者之间的寄生电容。
在一些示例性实施方式中，第一引出线可以通过第一连接电极与引出转接线电连接。第一连接电极可以位于第一走线的开口内，第一连接电极在衬底的正投影与第一电源线的第一走线在衬底的正投影可以没有交叠。例如，第一连接电极与第一走线可以为同层结构。然而，本实施例对此并不限定。例如，第一引出线可以与引出转接线直接电连接。
在一些示例性实施方式中，第一电源线还可以包括：位于第一走线远离衬底一侧的第二走线。第二走线与第一走线电连接，且第二走线在衬底的正投影与第一走线的开口在衬底的正投影没有交叠。在本示例中，第一走线设置开口的区域为引出转接线与第一引出线的连接区域，在引出转接线与第一引出线的连接区域之外的区域，第一电源线可以采用双层走线。例如，第二走线与引出转接线可以为同层结构。
在一些示例性实施方式中，第一边框区域至少可以包括：沿着远离显示区域的方向依次设置的第一扇出区、弯折区、第二扇出区以及第一电路区。第一电路区至少包括测试电路。第一电源线和引出转接线至少可以位于第二扇出区。本示例中，在第一电路区靠近显示区域一侧设置引出转接线，有利于调整第一数据引出线和第二数据引出线的顺序，从而兼容常规的集成电路，降低成本。而且，有利于实现下边框的窄化。在另一些示例中，引出转接线和第一电源线可以至少位于第一扇出区，来实现对第一数据引出线和第二数据引出线的顺序调整。
下面通过一些示例对本实施例的方案进行举例说明。
图4为本公开至少一实施例的显示基板的走线示意图。在一些示例中，如图4所示，显示区域100可以包括：沿第二方向Y延伸的多条第一数据线11和多条第二数据线12。第一数据线11可以与沿第二方向Y排布的多个子像素Pxij电连接，被配置为给多个子像素Pxij提供数据信号。第二数据线12可以与沿第二方向Y排布的多个子像素Pxij电连接，被配置为给多个子像素Pxij提供数据信号。多条第一数据线11和多条第二数据线12可以沿第一方向X排布。例如，多条第一数据线11在第一方向X上可以位于多条第二数据线12的外侧。如图2和图4所示，多条第一数据线11在第一方向X上位于多条第二数据线12靠近第二边界B2和第三边界B3的一侧。显示基板在第一方向X上可以具有第一中心线OO’。多条第二数据线12可以位于多条第一数据线11靠近第一中心线OO’的一侧。
在一些示例中，如图4所示，显示区域100还可以包括：沿第一方向X延伸的多条第一数据连接线13和沿第二方向Y延伸的多条第二数据连接线14。多条第一数据线11 可以与多条第一数据连接线13一一对应电连接，多条第一数据连接线13可以与多条第二数据连接线14一一对应电连接。一条第一数据线11可以通过一条第一数据连接线13与一条第二数据连接线14电连接。例如，第一数据连接线13的一端与第一数据线11电连接，另一端与第二数据连接线14电连接。第二数据连接线14在第一方向X上可以位于所电连接的第一数据线11靠近第一中心线OO’的一侧。第二数据连接线14可以在第一方向X上插设在多条第二数据线12之间。例如，在第一方向X上间隔四条第二数据线12可以排布一条第二数据连接线14。然而，本实施例对此并不限定。
在一些示例中，如图4所示，显示区域100可以包括：位于第一中心线OO’两侧的第一区域(例如，左半区域)100a和第二区域(例如，右边区域)100b。在第一区域100a或第二区域100b内，远离第一中心线OO’的第一数据线11所电连接的第一数据连接线13的长度可以大于靠近第一中心线OO’的第一数据线11所电连接的第一数据连接线13的长度。远离第一中心线OO’的第一数据线11所电连接的第一数据连接线13，在第二方向Y上可以位于靠近第一中心线OO’的第一数据线11所电连接的第一数据连接线13远离显示区域100的下边缘的一侧。例如，第一区域100a和第二区域100b可以关于第一中心线OO’大致对称。然而，本实施例对此并不限定。
在一些示例中，如图4所示，在第一区域100a或第二区域100b内，远离第一中心线OO’的第一数据线11所电连接的第二数据连接线14，在第一方向X上可以位于靠近第一中心线OO’的第一数据线11所电连接的第二数据连接线14靠近该第一中心线OO’的一侧。远离第一中心线OO’的第一数据线11所电连接的第二数据连接线14沿第二方向Y的长度，可以大于靠近第一中心线OO’的第一数据线11所电连接的第二数据连接线14沿第二方向Y的长度。在本示例中，以显示区域100的第一区域100a为例，多条第一数据线11沿第一方向X从边缘到中心的排布顺序与所述多条第一数据线11转接的第二数据连接线14沿第一方向X从边缘到中心的排布顺序是相反的。本示例所示的第一数据线11的转接方式可以称为逆序插序方式。
在一些示例中，第一数据线11、第二数据线12和第二数据连接线14可以为同层结构，例如可以均位于第二源漏金属层；第一数据连接线13可以位于第一源漏金属层。然而，本实施例对此并不限定。例如，第一数据线11、第二数据线12和第二数据连接线14可以为位于第一源漏金属层，第一数据连接线13可以位于第二源漏金属层。或者，第一数据线13可以位于第一栅金属层、第二栅金属层或者第三栅金属层。
在一些示例中，如图4所示，第一扇出区201可以包括：多条第一数据扇出线21和多条第二数据扇出线22。第一数据扇出线21可以与延伸至第一扇出区201的第二数据连接线14电连接。第二数据扇出线22可以与延伸至第一扇出区201的第二数据线12电连接。多条第一数据扇出线21在第一方向X上可以穿插设置在多条第二数据扇出线22之间。多条第一数据扇出线21和多条第二数据线22的排布顺序与显示区域100内的多条第二数据线12和多条第二数据连接线14的排布顺序可以一致。例如，在第一方向X上间隔四条第二数扇出出线22可以排布一条第一数据扇出线21。然而，本实施例对此并不限定。
在一些示例中，第一扇出区201的第一数据扇出线21和第二数据扇出线22可以位于第一栅金属层或第二栅金属层。相邻两条数据扇出线可以位于不同导电层。
本示例中，通过将显示区域100内靠近左右两侧边缘的第一数据线11通过第一数据连接线13和第二数据连接线14从显示区域100引出至第一扇出区201，可以使得显示区域100的边缘位置的第一数据线11与第二数据线12集中引出，从而可以减小第一扇出区201的数据扇出线所占用的排布空间，减小第一扇出区201的长度，缩减下边框尺寸。
在一些示例中，如图4所示，弯折区202可以包括：多条第一弯折连接线23和多条第二弯折连接线24。第一弯折连接线23和第二弯折连接线24可以沿第二方向Y延伸。第一弯折连接线23可以与第一数据扇出线21电连接，第二弯折连接线24可以与第二数据扇出线22电连接。多条第一弯折连接线23和多条第二弯折连接线24沿第一方向X的排布顺序与多条第一数据扇出线21和多条第二数据扇出线22沿第一方向X的排布顺序可以一致。
在一些示例中，如图4所示，第二扇出区203可以包括：多条第三数据扇出线25、多条第四数据扇出线26以及多条引出转接线27。第四数据扇出线26可以与第二弯折连接线24电连接。第三数据扇出线25可以与第一弯折连接线23电连接。第三数据扇出线25和第四数据扇出线26可以延伸至第一电路区。
在一些示例中，如图4所示，第三扇出区可以包括：多条第五数据扇出线29和多条第六数据扇出线28。第五数据扇出线29可以与第三数据扇出线25电连接，第六数据扇出线28可以与第四数据扇出线26电连接。第五数据扇出线29和第六数据扇出线28可以延伸至驱动芯片区206，以便与驱动芯片区206的连接引脚电连接，后续实现与集成电路电连接。
在本示例中，第一数据引出线可以包括：第一数据扇出线21、第一弯折连接线23、第三数据扇出线25以及第五数据扇出线29。第二数据引出线可以包括：第二数据扇出线22、第二弯折连接线24、第四数据扇出线26以及第六数据扇出线28。
图5为本公开至少一实施例的显示基板的走线示例图。在一些示例中，以第一中心线OO’的左侧区域为例，如图5所示，第一数据引出线L1最靠近显示基板的边缘，第一数据引出线L2最靠近第一中心线OO’。其余第一数据引出线位于第一数据引出线L1和L2之间。
在一些示例中，如图5所示，在显示区域100的第一区域内，第一数据引出线L1电连接的第一数据线11，位于第一数据引出线L2电连接的第一数据线11靠近第一中心线OO’的一侧；第一数据引出线L1电连接的第一数据线11远离第一中心线OO’的一侧设置有多条第一数据线11，靠近第一中心线OO’的一侧设置多条第二数据线12和多条第二数据连接线14。
在一些示例中，如图5所示，在第二扇出区203内，第一数据引出线L2的第三数据扇出线25可以与引出转接线27电连接，通过至少沿第一方向X延伸的引出转接线27，第一数据引出线L2的第三数据扇出线25可以与靠近第一边框区域边缘的第五数据扇出线29电连接。第一数据引出线L1的第三数据扇出线25可以与引出转接线27电连接，通过至少沿第一方向X延伸的引出转接线27，第一数据引出线L1的第三数据扇出线25可以与远离第一边框区域边缘的第五数据扇出线29电连接。多条第一数据引出线在第一扇出区201、弯折区202和第二扇出区203的靠近弯折区202区域内的顺序，与多条第一数据引出线在第二扇出区203的靠近第一电路区204的区域内、第三扇出区205区域内的顺序是相反的。多条引出转接线27可以关于第一中心线OO’大致对称。
图6为本公开至少一实施例的第二扇出区的局部走线示意图。图6为图5中区域A1的局部走线示意图。在一些示例中，如图6所示，第二扇出区的第三数据扇出线25可以包括：第一引出线251和第二引出线252。第一引出线251和第二引出线252可以通过引出转接线27电连接。引出转接线27可以先沿第一方向X延伸，再沿第二方向Y向远离显示区域一侧延伸。引出转接线27可以为折线型。一条第三数据扇出线25的第二引出线252可以在第一方向X位于第一引出线251远离第一中心线的一侧。在第一引出线251 沿第二方向Y的延伸方向上还设置有第一虚设走线253，第一虚设走线253与第一引出线251断开。通过设置第一虚设走线253可以保证走线均一性。
在一些示例中，如图6所示，第二扇出区的第四数据扇出线26可以包括：第三引出线261和第四引出线262。第三引出线261可以与第四引出线262电连接。例如，第三引出线261可以通过连接电极与第四引出线262电连接。然而，本实施例对此并不限定。例如，第三引出线261和第四引出线262可以为一体结构；或者，第三引出线261可以与第四引出线262直接电连接。多条第二引出线252在第一方向X上可以位于多条第四引出线262靠近第一边框区域的边缘的一侧。
在一些示例中，如图4至图6所示，多条第一引出线251和多条第四数据扇出线26的第三引出线261沿第一方向X的排布顺序可以与多条第一弯折连接线23和多条第二弯折连接线24沿第一方向X的排布顺序一致，多条第二引出线252和多条第四数据扇出线26的第四引出线262沿第一方向X的排布顺序可以与显示区域100内的多条第一数据线11和多条第二数据线12沿第一方向X的排布顺序一致。本示例利用引出转接线27可以对第三数据扇出线25进行跳线转接，可以调整数据信号的传输顺序，从而使得数据信号传输顺序与显示区域的第一数据线和第二数据线的排布顺序一致，以便适配常规的集成电路。
图7为本公开至少一实施例的第一边框区域的局部示意图。图8为图7中的第一数据引出线和第二数据引出线的示意图。图7和图8中仅以若干条第一数据引出线和第二数据引出线为例进行示意。图9为图7中第一源漏金属层的局部示意图。图10为图7中第二源漏金属层的局部示意图。
在一些示例中，如图7所示，第一边框区域还可以包括：第一电源线41和第二电源线42。第一电源线41的至少部分和第二电源线42的至少部分可以位于第二扇出区203。第一电源线41可以从第二扇出区203沿第二方向Y绕过第一电路区204和驱动芯片区206延伸至绑定引脚区207，与绑定引脚区207内的第一电源引脚电连接。第二电源线42可以在第一方向X上位于第一电源线41的相对两侧。第二电源线42例如可以关于沿第二方向Y延伸的第一中心线大致对称。第二电源线42可以从第二扇出区203沿第二方向Y延伸至绑定引脚区207，并与绑定引脚区207内的第二电源引脚电连接。例如，第一电源线41可以被配置为持续提供高电平信号，第二电源线42可以被配置为持续提供低电平信号。
在一些示例中，如图7和图8所示，引出转接线27可以位于第二扇出区203，引出转接线27的两端可以分别电连接第一引出线251和第二引出线252。多条引出转接线27在衬底的正投影与第一电源线41在衬底的正投影可以存在交叠。第一电源线41在衬底的正投影与多条第一引出线251在衬底的正投影可以存在交叠。引出转接线27与第二引出线252的连接位置在衬底的正投影与第一电源线41在衬底的正投影可以没有交叠。
在一些示例中，如图7和图8所示，沿第一方向X远离第一边框区域边缘的第一引出线251可以与靠近弯折区202的引出转接线27电连接，沿第一方向X靠近第一边框区域边缘的第一引出线251可以与远离弯折区202的引出转接线27电连接。
在一些示例中，如图7所示，第一扇出区201还可以包括：第一电源连接线31和第二电源连接线32。第二电源连接线32在第一方向X上可以位于第一电源连接线31的相对两侧。第二电源连接线32可以沿着显示区域100的边缘延伸至第二边框区域，并与第二边框区域内的边框电源引线电连接。如图9所示，第二电源连接线32可以位于第一源漏金属层。第一电源连接线31可以与显示区域内的多条高电位电源线电连接，以便给显 示区域内的多个子像素的像素电路提供高电位电源信号。在一些示例中，第一电源连接线31可以包括：叠设的第五走线311和第六走线312。第五走线311可以为位于第一源漏金属层，第六走线312可以位于第二源漏金属层。在一些示例中，第五走线311可以具有多个第一透气孔，第六走线312可以具有多个第二透气孔，第一透气孔和第二透气孔在衬底的正投影可以为矩形，例如圆角矩形。第二透气孔在衬底的正投影可以与第一透气孔在衬底的正投影存在交叠。第五走线311通过设置多个第一透气孔，有利于制备过程中第七绝缘层(如图14A至图14C内的第七绝缘层507)的气体排出，第六走线312通过设置多个第二透气孔，有利于制备过程中第八绝缘层(图未示)的气体排除，防止发生爆膜。第五走线311可以通过第七绝缘层开设的多个过孔与第六走线312电连接。然而，本实施例对此并不限定。
在一些示例中，如图7至图10所示，弯折区202还可以包括：多个(例如三个)第三电源连接线33和多个(例如，四个)第四电源连接线34。第三电源连接线33和第四电源连接线34可以为同层结构，例如均位于第二源漏金属层。第三电源连接线33可以与第一电源连接线31的第五走线311电连接。第四电源连接线34可以第二电源连接线32电连接。
在一些示例中，如图7至图10所示，第一电源线41可以包括：叠设的第一走线411和第二走线412。例如，第一走线411可以位于第一源漏金属层，第二走线412可以位于第二源漏金属层。第一走线411与第二走线412电连接。第二走线412与第三电源连接线33可以为一体结构。第二电源线42可以包括：叠设的第三走线421和第四走线422。例如，第三走线421可以位于第一源漏金属层，第四走线422可以位于第二源漏金属层。第三走线421和第四走线422可以电连接。第四走线422与第四电源连接线34可以为一体结构。然而，本实施例对此并不限定。
图11为图7中弯折区和第二扇出区的局部示意图。图12为图11中区域A2的局部放大示意图。图13A为图12中形成第二栅金属层后的第二扇出区的局部放大示意图。图13B为图12中形成第一源漏金属层后的第二扇出区的局部放大示意图。图13C为图12中形成第七绝缘层(如图14A至图14C内的第七绝缘层507)后的第二扇出区的局部放大示意图。图14A为图12中沿P-P’方向的局部放大示意图。图14B为图12中沿Q-Q’方向的局部放大示意图。图14C为图12中沿U-U’方向的局部放大示意图。
在一些示例中，如图12至图13A所示，在第二扇出区，第三数据扇出线的第一引出线251可以在第一方向X上穿插设置在多条第四数据扇出线26之间。例如，四条第四数据扇出线26之间可以间隔排布一条第一引出线251。第二扇出区还包括：在第二方向Y上与第一引出线251对齐的第一虚设走线253。第一引出线251与第一虚设走线253为同层结构，且两者断开。例如，第一虚设走线253可以沿第二方向Y延伸至第二扇出区和第一电路区的边缘。或者，第一虚设走线253可以沿第二方向Y延伸至第二引出线252的起始位置处。第一虚设走线253与第二引出线252断开，没有电连接。通过设置第一虚设走线253可以确保第二扇出区的走线均一性。多条第一引出线251和多条第四数据扇出线26中相邻两条走线可以位于不同导电层。例如，如图14A所示，一条第一引出线251可以位于第一栅金属层，该条第一引出线251相邻的两条第四数据扇出线26可以位于第二栅金属层。在本示例中，第一引出线251和第四数据扇出线26可以利用两个导电层排布，且相邻走线位于不同导电层，可以实现相邻走线的紧凑排布，有利于减少走线的排布空间，而且可以减少相邻走线之间的干扰。
在一些示例中，如图12至图13B所示，在第二扇出区，第一电源线的第一走线411可以具有多个开口K1。例如，开口K1在衬底的正投影可以为矩形，比如圆角矩形。在 第一方向X上从第一边框区域的边缘向中心的方向上，多个开口与弯折区之间的距离可以逐渐减小。第一走线411的开口K1内可以设置第一连接电极61。第一连接电极61在衬底的正投影可以位于开口K1内，并与第一走线411在衬底的正投影没有交叠。第一走线411和第一连接电极61可以为同层结构，例如位于第一源漏金属层。如图14B所示，第一连接走线61可以通过第五绝缘层505开设的多个(例如四个)第一过孔V1与位于第一栅金属层(或第二栅金属层)的第一引出线251电连接。第一过孔V1内的第五绝缘层505、第四绝缘层504、第三绝缘层503和第二绝缘层502可以被去掉，暴露出第一引出线251的表面。
在一些示例中，如图12至图13C所示，在第二扇出区，第一电源线的第二走线412与引出转接线27可以为同层结构，例如可以位于第二源漏金属层。引出转接线27可以至少沿第一方向X延伸，例如可以先沿第一方向X朝第二引出线一侧延伸，再沿第二方向Y向远离显示区域一侧延伸至与第二引出线电连接。引出转接线27可以通过第二过孔V2与位于第一源漏金属层的第一连接电极61电连接。如图14B所示，第二过孔V2内的第六绝缘层506和第七绝缘层507可以被去掉，暴露出第一连接电极61的表面。引出转接线27在衬底的正投影与第一电源线的第一走线411在衬底的正投影存在交叠。在本示例中，通过对第一电源线的第一走线411进行挖开口设计，使得引出转接线27与第一引出线251的连接位置的正投影位于所述开口内，可以在实现第一引出线的转接过程中最小化对第一电源线的影响。
在一些示例中，如图12所示，第二扇出区还可以包括：沿第一方向X延伸的多条第二虚设走线63。第二虚设走线63在第一方向X上可以位于相邻引出转接线27之间。在第二方向Y上，第二虚设走线63可以与引出转接线27相邻，第二虚设走线63可以位于引出转接线27远离显示区域的一侧。通过设置第二虚设走线63可以实现第二扇出区的引出转接线的排布均一性，而且可以改善制备工艺对位于边缘处的引出转接线的影响。
在一些示例中，如图12和图14A所示，多条引出转接线27可以位于第一电源线的第一走线411远离衬底101的一侧，多条第一引出线251和第四数据扇出线26可以位于第一走线411靠近衬底101的一侧。利用第一电源线的第一走线411可以将引出转接线27与多条第一引出线251和第四数据扇出线26隔离开，可以有效防止走线之间的相互串扰。以红色子像素和蓝色子像素接收的数据信号为交流信号，绿色子像素接收的数据信号为直流信号为例，利用第一电源线隔离引出转接线，可以隔离引出转接线传输的交流信号对第一走线的下方传输的直流信号的影响，还可以隔离第一走线下方传输的交流信号对引出转接线传输的直流信号的影响。
在一些示例中，如图12和图14A所示，引出转接线27和第一电源线的第一走线411之间可以设置有第七绝缘层507和第六绝缘层506。例如，第七绝缘层507可以为有机绝缘层，第六绝缘层506可以为无机绝缘层。通过设置第七绝缘层507可以起到平坦化作用，有利于增加工艺良率，而且通过增加引出转接线27和第一走线411之间的介质层，可以有利于减少两者之间的寄生电容，减少相互之间的影响。
在一些示例中，如图12、图13C和图14C所示，第六绝缘层506可以开设有第一凹槽V4，第一凹槽V4内的第六绝缘层506可以被去掉。第七绝缘层507可以开设有第二凹槽V3，第二凹槽V3内的第七绝缘层507可以被去掉。在本示例中，第一凹槽V4在衬底101的正投影可以位于第一走线411在衬底101的正投影范围内，第二凹槽V3在衬底101的正投影与第一走线411在衬底101的正投影可以部分交叠，例如，第一走线411远离显示区域一侧区域内的第七绝缘层507可以被去掉。在第一电源线所在区域内，第一电源线的第二走线412在衬底101的正投影与第六绝缘层506的边缘在衬底101的正投影可 以存在交叠，以包覆第六绝缘层506的边界。第二走线412在衬底101的正投影与第七绝缘层507的边缘在衬底101的正投影可以存在交叠。第二走线412和第一走线411在第一凹槽V4和第二凹槽V3的交叠区域可以直接接触。本示例中，第一电源线采用双层走线设计，且第二走线可以对保留的第七绝缘层和第六绝缘层的部分边界进行包覆，可以有效减少膜层剥离(Peeling)风险。
在一些示例中，如图7至图11所示，在第一引出线251和引出转接线27的转接区域，第一电源线采用单层走线设计，在其余区域第一电源线可以采用双层走线设计，且第一走线411和第二走线412可以至少部分直接接触。
在一些示例中，如图7至图10所示，第二电源线42可以采用双层走线设计(即包括叠设的第三走线421和第四走线422)。第三走线421和第四走线422的至少部分可以直接接触。在第三走线421和第四走线422的正投影的边缘，第四走线422在衬底的正投影可以覆盖第六绝缘层的边缘，并覆盖第七绝缘层的至少部分边缘，以有效减少膜层剥离风险。第二电源线的第三走线和第四走线的连接方式与第一电源线的第一走线和第二走线的连接方式可以大致相同，故于此不再赘述。
图15为本公开至少一实施例的引出转接线与第二引出线之间的连接示意图。在一些示例中，如图15所示，位于第二源漏金属层的引出转接线27可以通过第七绝缘层和第六绝缘层开设的过孔与位于第一源漏金属层的第二连接电极62电连接。第二连接电极62可以通过第五绝缘层至第二绝缘层开设的过孔与位于第一栅金属层的第二引出线252电连接。或者，第二连接电极62可以通过第五绝缘层至第三绝缘层开设的过孔与位于第二栅金属层的第二引出线252电连接。引出转接线27与第二引出线252的连接位置在衬底的正投影与第一电源线在衬底的正投影可以没有交叠。引出转接线27与第二引出线252的连接位置可以位于第一电源线远离弯折区的一侧。然而，本实施例对此并不限定。在另一些示例中，引出转接线27与第二引出线252的连接位置可以位于第一电源线靠近弯折区的一侧。又如，第一电源线的第一走线还可以开设多个开口，第二连接电极可以位于所述开口内，以实现与第二引出线和引出转接线的电连接。
下面通过显示基板的制备过程对显示基板的结构进行举例说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B为同层结构”是指，A和B通过同一次图案化工艺同时形成，或者A和B靠近衬底一侧的表面与衬底的距离基本相同，或者A和B靠近衬底一侧的表面与同一个膜层直接接触。膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在一些示例性实施方式中，显示基板的制备过程可以包括如下操作。
(1)、提供衬底。在一些示例中，衬底可以为柔性衬底。例如，柔性衬底可以包括在玻璃载板上叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对 苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一无机材料层和第二无机材料层还可以称之为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。然而，本实施例对此并不限定。
(2)、形成第一半导体层。在一些示例中，在衬底上沉积第一半导体薄膜，通过图案化工艺对第一半导体薄膜进行图案，形成设置在衬底上的第一半导体层。例如，第一半导体层可以包括：位于显示区域的像素电路的低温多晶硅薄膜晶体管的有源层。
(3)、形成第一栅金属层。在一些示例中，在形成前述图案的衬底上，依次沉积第一绝缘薄膜和第一金属薄膜，通过图案化工艺对第一金属薄膜进行图案化，形成第一绝缘层以及设置在第一绝缘层上的第一栅金属层。例如，第一栅金属层可以至少包括：位于显示区域的像素电路的低温多晶硅薄膜晶体管的栅极以及存储电容的其中一个电极、位于第一边框区域的第一扇出区的多条第一数据扇出线和多条第二数据扇出线、位于第二扇出区的多条第三数据扇出线和多条第四数据扇出线、以及位于第三扇出区的多条第五数据扇出线和多条第六数据扇出线。
(4)、形成第二栅金属层。在一些示例中，在形成前述图案的衬底上，依次沉积第二绝缘薄膜和第二金属薄膜，通过图案化工艺对第二金属薄膜进行图案化，形成第二绝缘层和设置在第二绝缘层上的第二栅金属层。例如，第二栅金属层可以至少包括：位于显示区域的像素电路的存储电容的另一个电极、位于第一边框区域的第一扇出区的多条第一数据扇出线和多条第二数据扇出线、位于第二扇出区的多条第三数据扇出线和多条第四数据扇出线、以及位于第三扇出区的多条第五数据扇出线和多条第六数据扇出线。在本示例中，第一扇出区的多条第一数据扇出线和多条第二数据扇出线中的相邻走线可以位于不同导电层。第二扇出区的多条第三数据扇出线和多条第四数据扇出线中的相邻走线可以位于不同导电层。第三扇出区的多条第五数据扇出线和多条第六数据扇出线中的相邻走线可以位于不同导电层。
(5)、形成第二半导体层。在一些示例中，在形成前述图案的衬底上，依次沉积第三绝缘薄膜和第二半导体薄膜，通过图案化工艺对第二半导体薄膜进行图案化，形成第三绝缘层和设置在第三绝缘层上的第二半导体层。例如，第二半导体层可以包括：位于显示区域的像素电路的氧化物薄膜晶体管的栅极。
(6)、形成第三栅金属层。在一些示例中，在形成前述图案的衬底上，依次沉积第四绝缘薄膜和第三金属薄膜，通过图案化工艺对第三金属薄膜进行图案化，形成第四绝缘层和设置在第四绝缘层上的第三栅金属层。例如，第三栅金属层可以至少包括：位于显示区域的像素电路的氧化物薄膜晶体管的栅极。
(7)、形成第一源漏金属层。在一些示例中，在形成前述图案的衬底上，沉积第五绝缘薄膜，通过图案化工艺形成第五绝缘层；随后，沉积第四金属薄膜，通过图案化工艺形成第一源漏金属层。显示区域的第五绝缘层可以开设有多个过孔，例如可以暴露出第一半导体层、第一栅金属层、第二栅金属层、第三栅金属层或第二半导体层的表面。例如，第一边框区域的弯折区域的第一绝缘层至第五绝缘层中的至少部分被去掉。第一边框区域的第二扇出区的第五绝缘层开设有多个过孔，例如可以暴露出第一栅金属层或第二栅金属层的表面。例如，第一源漏金属层可以包括：位于显示区域的像素电路的多个连接电极以及多条第一数据连接线、位于第一边框区域的第一扇出区的第一电源连接线的第五走线和第二电源连接线、位于第二扇出区的多条第一连接电极、多个第二连接电极、第一电源线的第一走线以及第二电源线的第三走线。
(8)、形成第二源漏金属层。在一些示例中，在形成前述图案的衬底上，沉积第六绝缘薄膜，通过图案化工艺形成第六绝缘层；随后，涂覆第七绝缘薄膜，通过图案化工艺形成第七绝缘层；随后，沉积第五金属薄膜，通过图案化工艺形成第二源漏金属层；随后，涂覆第八绝缘薄膜，通过图案化工艺形成第八绝缘层。在一些示例中，第二源漏金属层可以包括：位于显示区域的多条第一数据线、多条第二数据线和多条第二数据连接线、位于第一边框区域的第一扇出区的第一电源连接线的第六走线、位于弯折区的第一弯折连接线、第二弯折连接线、第三电源连接线和第四电源连接线、以及位于第二扇出区的引出转接线、第一电源线的第二走线以及第二电源线的第四走线。
至此，在衬底的显示区域可以制备完成电路结构层。
(9)、形成发光结构层。在一些示例中，在形成前述图案的衬底上，沉积第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成阳极层。阳极层包括多个发光元件的阳极。阳极可以通过第八绝缘层开设的过孔与像素电路电连接。随后，涂覆像素定义薄膜，通过掩膜、曝光、显影工艺，形成像素定义层。显示区域的像素定义层开设有暴露出阳极层的多个像素开口。随后，在显示区域依次形成有机发光层和阴极层。有机发光层形成在像素开口内，实现有机发光层与阳极连接。阴极形成在像素定义层上，与有机发光层连接。
(10)、形成封装结构层。在一些示例中，封装结构层可以包括无机材料/有机材料/无机材料的叠层结构。
在一些示例中，第一半导体层的材料可以包括多晶硅。第二半导体层的材料可以包括金属氧化物。第一栅金属层、第二栅金属层、第三栅金属层、第一源漏金属层和第二源漏金属层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层至第六绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第七绝缘层和第八绝缘层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。阳极层可以采用金属等反射材料，阴极可以采用透明导电材料。然而，本实施例对此并不限定。
本实施例的显示基板的结构及其制备过程仅仅是一种示例性说明。在一些示例中，可以根据实际需要变更相应结构以及增加或减少构图工艺。本示例性实施例的制备工艺可以利用目前成熟的制备设备即可实现，可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本实施例提供的显示基板可以利用引出转接线来调整数据信号的传输顺序，使得第一边框区域的数据信号或测试数据信号的提供顺序与显示区域的第一数据线和第二数据线的顺序一致，并降低对第一电源线的影响。而且，本示例的数据引出线的走线方式有利于改善走线电阻突变情况。另外，通过第一电源线对数据扇出线和引出转接线进行隔离，可以有效防止数据信号之间的相互串扰。
图16为本公开至少一实施例的显示基板的另一走线示意图。在一些示例中，如图16所示，在第一区域100a或第二区域100b内，远离第一中心线OO’的第一数据线11所电连接的第二数据连接线14，在第一方向X上，可以位于靠近第一中心线OO’的第一数据线11所电连接的第二数据连接线14远离该第一中心线OO’的一侧。在本示例中，以显示区域的第一区域100a为例，多条第一数据线11沿第一方向X从边缘到中心的排布顺 序与所述多条第一数据线11转接的第二数据连接线14沿第一方向X从边缘到中心的排布顺序是相同的。本示例所示的第一数据线11的转接方式可以称为正序插序方式。
在一些示例中，如图16所示，在第一区域100a或第二区域100b内，远离第一中心线OO’的第一数据线11所电连接的第二数据连接线14沿第二方向Y的长度，可以小于靠近第一中心线OO’的第一数据线11所电连接的第二数据连接线14沿第二方向Y的长度。远离第一中心线OO’的第一数据线11所电连接的第一数据连接线13，在第二方向Y上可以位于靠近第一中心线OO’的第一数据线11所电连接的第一数据连接线13靠近显示区域100的下边缘的一侧。
在一些示例中，如图16所示，位于第二扇出区203的第三数据扇出线25可以包括第一引出线和第二引出线，第一引出线和第二引出线可以通过引出转接线27电连接。靠近第一中心线OO’的第一引出线所电连接的引出转接线27，在第二方向Y上可以位于远离第一中心线OO’的第一引出线所电连接的引出转接线27远离弯折区域202的一侧。引出转接线27在第二扇出区203可以与第一电源线在衬底的正投影存在交叠。
图17为本公开至少一实施例的显示基板的另一走线示意图。在一些示例中，如图17所示，在第一区域100a或第二区域100b内，远离第一中心线OO’的第一数据线11所电连接的第二数据连接线14沿第二方向Y的长度，可以大于靠近第一中心线OO’的第一数据线11所电连接的第二数据连接线14沿第二方向Y的长度。远离第一中心线OO’的第一数据线11所电连接的第一数据连接线13，在第二方向Y上可以位于靠近第一中心线OO’的第一数据线11所电连接的第一数据连接线13远离显示区域100的下边缘的一侧。本实施例的显示基板的其余结构与图16所示的实施例大致相同。
图18为图16或图17中第二扇出区的局部示意图。在一些示例中，如图16至图18所示，位于第二扇出区203的第三数据扇出线25可以包括第一引出线和第二引出线，第一引出线和第二引出线可以通过引出转接线27电连接。靠近第一中心OO’的第一引出线所电连接的引出转接线27，在第二方向Y上可以位于远离第一中心线OO’的第一引出线所电连接的引出转接线27远离弯折区域202的一侧。本示例所示的第一数据线的转接方式为正序插序方式。引出转接线27在第二扇出区203可以与第一电源线41在衬底的正投影存在交叠。第一电源线41可以包括第一走线411和第二走线412。第一走线411可以具有多个开口，引出转接线27和第一引出线的连接位置在衬底的正投影可以位于所述开口内，与第一走线411没有交叠。在没有排布引出转接线27的区域，第一电源线41可以采用第一走线411和第二走线412的双层走线结构。
关于本实施例的显示基板的其余结构，可以参照前述实施例的说明，故于此不再赘述。
图19为第一边框区域的多条数据引出线的电阻变化曲线图。图20为第一边框区域的多条数据引出线进行电阻补偿之后的电阻变化曲线图。图19和图20中的横坐标表示数据引出线沿第一方向的编号，纵坐标表示电阻值。
在一些示例中，如图19所示，曲线L11表示如图4所示采用逆序插序方式的显示基板在第一边框区域利用引出转接线进行转接后的数据引出线的电阻变化。曲线L12表示如图16或图17所示采用正序插序方式的显示基板在第一边框区域利用引出转接线进行转接后的数据引出线的电阻变化。曲线L13表示采用逆序插序方式的显示基板不在第一边框区域利用引出转接线而是利用更新的集成电路后的数据引出线的电阻变化。由图19可见，电阻跳变情况从小到大依次为：曲线L11、曲线L12和曲线L13。
在一些示例中，如图19所示，在进行电阻补偿时，曲线L11所需补偿的点位较少，且电阻差值较小(例如仅166Ω)，易于补偿，需求的补偿空间较小，有利于显示基板的 下边框收窄。曲线L12，由于没有采用引出转接线对第一数据引出线进行跳线设计，使得第一数据引出线穿插在第二数据引出线中，位置较为分散，导致电阻补偿的工作量巨大。曲线L13所需补偿的点位较多，且电阻差值较大(例如最大差值约为983Ω)，需求的补偿空间较大。
在一些示例中，如图20所示，曲线L21表示如图4所示采用逆序插序方式的显示基板在第一边框区域利用引出转接线进行转接后的数据引出线进行电阻补偿后的变化。曲线L22表示如图16或图17所示采用正序插序方式的显示基板在第一边框区域利用引出转接线进行转接后的数据引出线进行电阻补偿后的变化。由图20可见，曲线L21的过渡比曲线L22更为平滑，因此，采用逆序插序方式的显示基板在第一边框区域利用引出转接线进行转接的方案，优于采用正序插序方式的显示基板在第一边框区域利用引出转接线进行转接的方案。本实施例对于采用的电阻补偿方式并不限定。
在一些示例中，本公开实施例的显示基板可以应用于具有像素电路的显示装置中，如OLED、量子点显示(QLED)、发光二极管显示(Micro LED或Mini LED)或量子点发光二极管显示(QDLED)等，本公开在此不做限定。
本公开实施例还提供一种显示装置，显示装置可以包括前述的显示基板。在一些示例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本发明实施例并不以此为限。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (22)

  1. 一种显示基板，包括：
    衬底，包括：显示区域和边框区域，所述边框区域包括：位于所述显示区域一侧的第一边框区域；所述显示区域具有靠近所述第一边框区域的第一边界，所述边框区域具有第二边界和第三边界，所述第二边界和第三边界在第一方向上位于所述第一边界的两侧；
    多个子像素，位于所述显示区域；
    多条第一数据线、多条第二数据线、多条第一数据连接线以及多条第二数据连接线，位于所述显示区域；所述多条第一数据线和所述多条第二数据线被配置为向所述多个子像素提供数据信号；所述多条第一数据连接线沿第一方向延伸，所述多条第一数据线、所述多条第二数据线和所述多条第二数据连接线沿第二方向延伸，所述第一方向与第二方向交叉；所述多条第一数据线通过所述多条第一数据连接线与所述多条第二数据连接线电连接；所述多条第一数据线在所述第一方向上位于所述多条第二数据线和所述多条第二数据连接线靠近所述第二边界或所述第三边界的一侧；
    多条第一数据引出线、多条第二数据引出线、多条引出转接线以及至少一条第一电源线，位于所述第一边框区域；所述多条第一数据引出线与所述多条第二数据连接线电连接，所述多条第二数据引出线与所述多条第二数据线电连接，所述至少一条第一电源线被配置为向所述多个子像素提供电源信号；
    所述多条第一数据引出线中的至少一条第一数据引出线包括：第一引出线和第二引出线，所述第一引出线通过所述引出转接线与所述第二引出线电连接，所述第一引出线与所述第二数据连接线电连接，所述引出转接线至少部分沿所述第一方向延伸，所述第二引出线在所述第一方向上位于所述第二数据引出线靠近所述第二边界或所述第三边界的一侧；
    所述多条引出转接线中的至少一条引出转接线在所述衬底的正投影与所述第一电源线在所述衬底的正投影存在交叠。
  2. 根据权利要求1所述的显示基板，其中，所述第一电源线至少包括：第一走线；所述第一走线具有多个开口，所述第一引出线与所述引出转接线的连接位置在所述衬底的正投影位于所述开口在所述衬底的正投影范围内。
  3. 根据权利要求2所述的显示基板，其中，所述第一数据引出线中的至少部分线段和所述第二数据引出线中的至少部分线段位于所述第一走线靠近所述衬底的一侧，所述引出转接线位于所述第一走线远离所述衬底的一侧。
  4. 根据权利要求2或3所述的显示基板，其中，所述引出转接线与所述第一走线之间至少设置有机绝缘层。
  5. 根据权利要求2至4中任一项所述的显示基板，其中，所述第一引出线通过第一连接电极与所述引出转接线电连接，所述第一连接电极位于所述开口内，所述第一连接电极在所述衬底的正投影与所述第一走线在所述衬底的正投影没有交叠。
  6. 根据权利要求5所述的显示基板，其中，所述第一连接电极与所述第一走线为同层结构。
  7. 根据权利要求2至6中任一项所述的显示基板，其中，所述第一数据引出线和所述第二数据引出线在所述衬底的正投影与所述第一走线在所述衬底的正投影存在交叠。
  8. 根据权利要求2至7中任一项所述的显示基板，其中，所述第一电源线还包括：位于所述第一走线远离所述衬底一侧的第二走线，所述第二走线与所述第一走线电连接， 所述第二走线在所述衬底的正投影与所述第一走线的开口在所述衬底的正投影没有交叠。
  9. 根据权利要求8所述的显示基板，其中，所述第二走线与所述引出转接线为同层结构。
  10. 根据权利要求8或9所述的显示基板，其中，所述第一走线与所述第二走线之间设置有至少一个绝缘层，所述第一走线的至少部分与所述第二走线直接接触，所述第二走线在所述衬底的正投影覆盖所述至少一个绝缘层的边界的至少部分。
  11. 根据权利要求10所述的显示基板，其中，所述至少一个绝缘层包括：无机绝缘层和有机绝缘层，所述无机绝缘层位于所述有机绝缘层靠近所述衬底的一侧。
  12. 根据权利要求1至11中任一项所述的显示基板，其中，所述显示基板在所述第一方向上具有第一中心线；所述多条第一数据线在所述第一方向上位于所述多条第二数据线和所述多条第二数据连接线远离所述第一中心线的一侧，所述多条第二引出线在所述第一方向上位于所述第二数据引出线远离所述第一中心线的一侧。
  13. 根据权利要求12所述的显示基板，其中，所述显示区域包括：位于所述第一中心线两侧的第一区域和第二区域；在所述第一区域或第二区域内，远离所述第一中心线的第一数据线所电连接的第二数据连接线，位于靠近所述第一中心线的第一数据线电连接的第二数据连接线靠近所述第一中心线的一侧。
  14. 根据权利要求12所述的显示基板，其中，所述显示区域包括：位于所述第一中心线两侧的第一区域和第二区域；在所述第一区域或第二区域内，远离所述第一中心线的第一数据线所电连接的第二数据连接线，位于靠近所述第一中心线的第一数据线电连接的第二数据连接线远离所述第一中心线的一侧。
  15. 根据权利要求12所述的显示基板，其中，靠近所述第一中心线的第一引出线所电连接的引出转接线，位于远离所述第一中心线的第一引出线所电连接的引出转接线靠近所述显示区域的一侧。
  16. 根据权利要求12所述的显示基板，其中，靠近所述第一中心线的第一引出线所电连接的引出转接线，位于远离所述第一中心线的第一引出线所电连接的引出转接线远离所述显示区域的一侧。
  17. 根据权利要求12所述的显示基板，其中，所述多条引出转接线关于所述第一中心线对称。
  18. 根据权利要求1至17中任一项所述的显示基板，其中，所述第一边框区域至少包括：沿着远离所述显示区域的方向依次设置的第一扇出区、弯折区、第二扇出区以及第一电路区；所述第一电路区至少包括测试电路；所述第一电源线和引出转接线至少位于所述第二扇出区。
  19. 根据权利要求18所述的显示基板，其中，所述第一引出线和第二引出线位于所述第二扇出区。
  20. 根据权利要求19所述的显示基板，其中，所述第二引出线与所述引出转接线的连接位置在所述衬底的正投影与所述第一电源线在所述衬底的正投影没有交叠。
  21. 根据权利要求19所述的显示基板，其中，所述第二引出线与所述引出转接线的连接位置位于所述第一电源线远离所述弯折区的一侧。
  22. 一种显示装置，包括如权利要求1至21中任一项所述的显示基板。
PCT/CN2023/105911 2022-07-15 2023-07-05 显示基板及显示装置 Ceased WO2024012329A1 (zh)

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