[go: up one dir, main page]

WO2024007435A1 - Panneau d'affichage - Google Patents

Panneau d'affichage Download PDF

Info

Publication number
WO2024007435A1
WO2024007435A1 PCT/CN2022/115997 CN2022115997W WO2024007435A1 WO 2024007435 A1 WO2024007435 A1 WO 2024007435A1 CN 2022115997 W CN2022115997 W CN 2022115997W WO 2024007435 A1 WO2024007435 A1 WO 2024007435A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
signal connection
via hole
display panel
connection section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2022/115997
Other languages
English (en)
Chinese (zh)
Inventor
张春鹏
鲜于文旭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Publication of WO2024007435A1 publication Critical patent/WO2024007435A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present application relates to the field of display technology, and in particular to a display panel.
  • An embodiment of the present application provides a display panel for increasing the proportion of the display area of the front body of the display panel.
  • An embodiment of the present application provides a display panel, which includes:
  • the display functional layer includes a pixel driving circuit layer and a light-emitting functional layer.
  • the pixel driving circuit layer is arranged on the signal transmission layer.
  • the light-emitting functional layer is arranged on the pixel driving circuit layer away from the signal transmission layer. layer side.
  • the display panel further includes a first signal connection line, the first signal connection line is located in the display area, and the first signal connection line is used to connect all the pixel driving circuit layer and the signal transmission layer.
  • the first signal connection line includes a connected first signal connection section, a second signal connection section and a third signal connection section;
  • the display panel includes a first signal connection section. hole, a second via hole and a third via hole, the first signal connection section is arranged in the first via hole, the second signal connection section is arranged in the second via hole, and the third signal connection section is arranged in the first via hole.
  • the signal connection section is arranged in the third via hole.
  • the signal transmission layer also includes a plurality of first power supply lines, a plurality of second power supply lines, a plurality of reset signal lines, an array test pad and a plurality of fan-shaped traces; among which
  • the first signal connection section is connected to the gate drive circuit, the first power supply line, the second power supply line, the reset signal line, the array test pad or the sector line.
  • the third signal connection section is connected to the pixel driving circuit layer.
  • the display panel further includes a second signal connection line, the second signal connection line is located in the display area, and the second signal connection line is used to connect all the pixel driving circuit layer and the signal transmission layer.
  • the second signal connection line includes a connected fourth signal connection section, a fifth signal connection section and a sixth signal connection section;
  • the display panel includes a fourth signal connection section. hole, a fifth via hole and a sixth via hole, the fourth signal connection section is arranged in the fourth via hole, the fifth signal connection section is arranged in the fifth via hole, and the sixth signal connection section is arranged in the fifth via hole.
  • the signal connection section is arranged in the sixth via hole.
  • the signal transmission layer also includes a plurality of first power supply lines, a plurality of second power supply lines, a plurality of reset signal lines, an array test pad and a plurality of fan-shaped traces; among which
  • the fourth signal connection section is connected to the gate drive circuit, the first power supply line, the second power supply line, the reset signal line, the array test pad or the sector line.
  • the sixth signal connection section is connected to the pixel driving circuit layer.
  • the display panel further includes a first connection terminal and a second connection terminal;
  • the gate driving circuit includes a first thin film transistor, and the first thin film transistor includes a first thin film transistor.
  • An active layer, a first gate electrode, a second gate electrode, a first source electrode and a first drain electrode, the signal transmission layer also includes:
  • a substrate, the first active layer is disposed on the substrate;
  • a first gate insulating layer is provided on the substrate, the first gate is provided on the substrate, and the first connection terminal and the first gate are in the same layer and made of the same material;
  • a second gate insulating layer is provided on the first gate insulating layer.
  • the second gate insulating layer covers the first gate and the first connection terminal.
  • the second gate and the first connecting terminal are The second connection terminal is provided on the second gate insulating layer, and the second gate and the second connection terminal are in the same layer and made of the same material;
  • a first interlayer insulating layer is provided on the second gate insulating layer, and the first interlayer insulating layer covers the second gate and the second connection terminal, and the first via hole passes through The first interlayer insulating layer and the second gate insulating layer, the first signal connection section is connected to the first connection terminal through the first via hole, and the fourth via hole penetrates the a first interlayer insulating layer, the fourth signal connection section is connected to the second connection terminal through the fourth via hole, and the first source electrode and the first drain electrode pass through the first contact hole and the first drain electrode respectively.
  • the second contact hole is connected to the first active layer;
  • a second interlayer insulating layer is provided on the first interlayer insulating layer.
  • the second via hole penetrates the second interlayer insulating layer.
  • the second signal connection section passes through the second via hole and the second interlayer insulating layer.
  • the first signal connection section is connected, the fifth via hole penetrates the second interlayer insulating layer, and the fifth signal connection section is connected to the fourth signal connection section through the fifth via hole.
  • the display panel further includes a third connection terminal and a fourth connection terminal;
  • the pixel driving circuit layer includes:
  • a second active layer is provided on the base layer
  • An insulating layer is provided on a side of the second active layer away from the base layer, the sixth via hole penetrates the insulating layer and the base layer, and the sixth signal connection section passes through the sixth via hole and the base layer.
  • the fifth signal connection section is connected;
  • a third gate is provided on a side of the insulating layer away from the second active layer.
  • the third connection terminal is connected to the sixth signal connection section and is in the same layer and material as the third gate. ;
  • An interlayer dielectric layer is provided on a side of the third gate away from the insulating layer.
  • the third via hole penetrates the interlayer dielectric layer, the insulating layer and the base layer.
  • the third signal is connected to the second signal connection section through the third via hole;
  • the second source electrode and the second drain electrode are disposed on the interlayer dielectric layer and pass through the third contact hole and the fourth contact hole and the second contact hole respectively.
  • the active layer is connected, the fourth connection terminal and the second source are in the same layer and material, the fourth connection terminal is connected to the third signal connection section;
  • a planarization layer is provided on the interlayer dielectric layer.
  • the signal transmission layer further includes a light-shielding layer, the light-shielding layer is provided on the second interlayer insulating layer, and the light-shielding layer is connected to the second interlayer insulating layer through a via hole.
  • the first drain electrode is connected, and the orthographic projection of the light-shielding layer on the substrate covers the orthographic projection of the second active layer on the substrate.
  • the display panel further includes a seventh via hole that penetrates part of the insulation layer of the signal transmission layer;
  • the signal transmission layer also includes a connection Traces and connection pads, the connection pads are provided on a side of the substrate away from the first interlayer insulating layer, the connection traces are provided in the seventh via hole, the connection traces One end of the connection line is connected to the connection pad, and the other end of the connection line is connected to the pixel driving circuit layer.
  • the display panel further includes a driver chip, the driver chip is disposed on a side of the substrate away from the first interlayer insulating layer, and the driver chip and the Connection pad connection.
  • the pixel driving circuit layer includes a pixel driving circuit, which includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor. , a second capacitor and an organic light-emitting diode; wherein the first transistor is a driving thin film transistor.
  • embodiments of the present application also provide a display panel, which includes a display area, and the display panel includes:
  • the display functional layer includes a pixel driving circuit layer and a light-emitting functional layer.
  • the pixel driving circuit layer is arranged above the signal transmission layer.
  • the light-emitting functional layer is arranged on the pixel driving circuit layer away from the signal transmission layer. layer side;
  • a driver chip is located on the side of the signal transmission layer away from the display function layer.
  • the display panel further includes a first signal connection line, the first signal connection line is located in the display area, and the first signal connection line is used to connect all the pixel driving circuit layer and the signal transmission layer.
  • the first signal connection line includes a connected first signal connection section, a second signal connection section and a third signal connection section;
  • the display panel includes a first signal connection section. hole, a second via hole and a third via hole, the first signal connection section is arranged in the first via hole, the second signal connection section is arranged in the second via hole, and the third signal connection section is arranged in the first via hole.
  • the signal connection section is arranged in the third via hole.
  • the signal transmission layer also includes a plurality of first power supply lines, a plurality of second power supply lines, a plurality of reset signal lines, an array test pad and a plurality of fan-shaped traces; among which
  • the first signal connection section is connected to the gate drive circuit, the first power supply line, the second power supply line, the reset signal line, the array test pad or the sector line.
  • the third signal connection section is connected to the pixel driving circuit layer.
  • the display panel further includes a second signal connection line, the second signal connection line is located in the display area, and the second signal connection line is used to connect all the pixel driving circuit layer and the signal transmission layer.
  • the second signal connection line includes a connected fourth signal connection section, a fifth signal connection section and a sixth signal connection section;
  • the display panel includes a fourth signal connection section. hole, a fifth via hole and a sixth via hole, the fourth signal connection section is arranged in the fourth via hole, the fifth signal connection section is arranged in the fifth via hole, and the sixth signal connection section is arranged in the fifth via hole.
  • the signal connection section is arranged in the sixth via hole.
  • the fourth signal connection section is connected to the gate drive circuit, the first power supply line, the second power supply line, and the reset signal line. lines, the array test pads or the fan-shaped traces, and the sixth signal connection section is connected to the pixel driving circuit layer.
  • An embodiment of the present application provides a display panel, which includes a display area.
  • the display panel includes a signal transmission layer and a display function layer. Among them, the signal transmission layer is located in the display area.
  • the signal transmission layer includes the gate drive circuit.
  • the display functional layer includes a pixel driving circuit layer and a light-emitting functional layer.
  • the pixel driving circuit layer is arranged on the signal transmission layer.
  • the light-emitting functional layer is arranged on the side of the pixel driving circuit layer away from the signal transmission layer.
  • the signal transmission layer for transmitting signals to the display functional layer is arranged below the display functional layer.
  • the signal transmission layer corresponds to the display area. That is to say, the embodiment of the present application will be used to drive the pixels of the display area.
  • the metal traces that provide signals from the circuit are set in the display area. Therefore, the signal transmission layer does not occupy the space of the non-display area, increasing the proportion of the display area of the display surface of the display panel, thereby realizing a narrow frame or frameless design and improving user experience.
  • Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • Figure 2 is a schematic cross-sectional structural diagram of a display panel provided by an embodiment of the present application.
  • Figure 3 is a schematic structural diagram of the signal transmission layer provided by the embodiment of the present application.
  • Figure 4 is a schematic structural diagram of a display function layer provided by an embodiment of the present application.
  • FIG. 5 is a circuit diagram of a pixel driving circuit of the pixel driving circuit layer provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a method for manufacturing a display panel according to an embodiment of the present application.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features.
  • features defined as “first” and “second” may explicitly or implicitly include one or more of the described features.
  • “plurality” means two or more than two, unless otherwise explicitly and specifically limited.
  • An embodiment of the present application provides a display panel. Each is explained in detail below. It should be noted that the order of description of the following embodiments does not limit the preferred order of the embodiments.
  • An embodiment of the present application provides a display panel, which includes a display area.
  • the display panel includes a signal transmission layer and a display function layer.
  • the signal transmission layer is located in the display area.
  • the signal transmission layer includes the gate drive circuit.
  • the display functional layer includes a pixel driving circuit layer and a light-emitting functional layer.
  • the pixel driving circuit layer is arranged on the signal transmission layer.
  • the light-emitting functional layer is arranged on the side of the pixel driving circuit layer away from the signal transmission layer.
  • the signal transmission layer for transmitting signals to the display function layer is arranged below the display function layer.
  • the signal transmission layer corresponds to the display area, so that the signal transmission layer does not occupy the space of the non-display area and improves the display of the display panel.
  • the proportion of the display area of the screen can be adjusted to achieve a narrow bezel or bezel-less design and improve the user experience.
  • the frame area of the display panel is provided with a gate driving circuit and metal wiring.
  • the gate driving circuit and metal wiring occupy a large proportion of the front screen of the display panel, making the screen of the display panel The proportion of the display area is too small to achieve a truly narrow bezel design.
  • Embodiments of the present application provide a display panel for increasing the proportion of the display area of the display surface of the display panel, thereby achieving a narrow frame or frameless design and improving user experience.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic cross-sectional structural diagram of a display panel provided by an embodiment of the present application.
  • the display panel 100 includes a display area AA.
  • the display panel 100 includes a signal transmission layer 10 , a display function layer 20 and a first signal connection line 40 .
  • the signal transmission layer 10 is located in the display area AA.
  • the signal transmission layer 10 includes a gate driving circuit 102 .
  • the display functional layer 20 includes a pixel driving circuit layer 20a and a light-emitting functional layer 20b.
  • the pixel driving circuit layer 20a is provided above the signal transmission layer 10, and the light-emitting functional layer 20b is provided on a side of the pixel driving circuit layer 20a away from the signal transmission layer 10.
  • the first signal connection line 40 is used to connect the signal transmission layer 10 and the pixel driving circuit layer 20a.
  • the signal transmission layer 10 for transmitting signals to the display function layer 20 is arranged below the display function layer 20 so that the signal transmission layer 10 is located in the display area AA. Therefore, the signal transmission layer does not occupy the space of the non-display area. , increasing the proportion of the display area AA of the display panel 100, thereby achieving a narrow frame or frameless design, improving the taste of the display panel 100, and thus improving the user experience.
  • the first signal connection line 40 is located in the display area AA.
  • the display panel 100 further includes a second signal connection line 50 , and the second signal connection line 50 is located in the display area.
  • the second signal connection line 50 is used to connect the pixel driving circuit layer 20a and the signal transmission layer 10.
  • the first signal connection line 40 includes a first signal connection section 401, a second signal connection section 402 and a third signal connection section 403.
  • the second signal connection line 50 includes a connected fourth signal connection section 501 , a fifth signal connection section 502 and a sixth signal connection section 503 .
  • the display panel 100 includes a first via hole h1, a second via hole h2, a third via hole h3, a fourth via hole h4, a fifth via hole h5, and a sixth via hole h6.
  • the first signal connection section 401 is provided in the first via hole h1
  • the second signal connection section 402 is provided in the second via hole h2
  • the third signal connection section 403 is provided in the third via hole h3.
  • the fourth signal connection section 501 is provided in the fourth via hole h4
  • the fifth signal connection section 502 is provided in the fifth via hole h5, and the sixth signal connection section 503 is provided in the sixth via hole h6.
  • the display panel 100 further includes a first connection terminal a1, a second connection terminal a2, a third connection terminal a3 and a fourth connection terminal a4.
  • the first connection terminal a1 is connected to the first signal connection section 401
  • the fourth connection terminal a4 is connected to the third signal connection section 403
  • the second connection terminal a2 is connected to the fourth signal connection section 501
  • the third connection terminal a3 and The sixth signal connection section 503 is connected.
  • the signal transmission layer 10 also includes a plurality of first power traces 110 , a plurality of second power traces 111 , a plurality of reset signal traces 113 , array test pads 114 and a plurality of sector traces 115 .
  • the first signal connection section 401 is connected to the gate driving circuit 102, the first power supply line 110, the second power supply line 111, the reset signal line 113, the array test pad 114 or the sector line 115.
  • the third signal connection section 403 is connected to the pixel driving circuit layer 20a.
  • the output ends of the gate drive circuit 102, the first power supply line 110, the second power supply line 111, the reset signal line 113, the array test pad 114 or the sector line 115 are connected to the first connection terminal a1
  • the corresponding signal is transmitted through the first signal connection line 40
  • the fourth connection terminal a4 is connected to the corresponding transistor or metal line of the pixel driving circuit layer 20a, thereby realizing signal transmission.
  • the fourth signal connection section 501 connects the gate driving circuit 102 , the first power supply trace 110 , the second power supply trace 111 , the reset signal trace 113 , the array test pad 114 or the sector trace 115 .
  • the sixth signal connection section 503 is connected to the pixel driving circuit layer 20a. Specifically, the output ends of the gate drive circuit 102, the first power supply line 110, the second power supply line 111, the reset signal line 113, the array test pad 114 or the sector line 115 are connected to the second connection terminal a2, The corresponding signal is transmitted through the second signal connection line 50, and the third connection terminal a3 is connected to the corresponding transistor or metal line of the pixel driving circuit layer 20a, thereby realizing signal transmission.
  • the first power supply line 110, the second power supply line 111, the reset signal line 113, the array test pad 114 and the plurality of sector lines 115 are all arranged below the display function layer 20. And all correspond to the display area AA. At this time, there is no need to set up a non-display area for placing metal traces, and the frameless design of the display panel 100 is realized, a true full screen is realized, and the user experience is greatly improved.
  • the fan-shaped traces 115 may be metal traces used to lead out the data lines of the pixel driving circuit layer, but are not limited to this.
  • the gate driving circuit 102 includes a first thin film transistor structure 102a.
  • the first thin film transistor structure 102a includes a first active layer 1021, a first gate electrode 1022, a second gate electrode 1023, a first source electrode 1024 and a first drain electrode 1025.
  • the signal transmission layer 10 also includes a substrate 101, a first gate insulating layer 103, a second gate insulating layer 104, a first interlayer insulating layer 105 and a second interlayer insulating layer 106.
  • the first gate insulating layer 103 is provided on the substrate 101 .
  • the first gate electrode 1022 is disposed on the substrate 101, and the first connection terminal a1 and the first gate electrode 1022 are in the same layer and made of the same material.
  • the second gate insulating layer 104 is provided on the first gate insulating layer 103 .
  • the second gate insulating layer 104 covers the first gate 1022 and the first connection terminal a1.
  • the second gate electrode 1023 and the second connection terminal a2 are disposed on the second gate insulating layer 104.
  • the second gate electrode 1023 and the second connection terminal a2 are of the same layer and made of the same material.
  • the first interlayer insulating layer 105 is disposed on the second gate insulating layer 104, and the first interlayer insulating layer 105 covers the second gate 1023 and the second connection terminal a2.
  • the first via hole h1 penetrates the first interlayer insulating layer 105 and the second gate insulating layer 104, and the first signal connection section 401 is connected to the first connection terminal a1 through the first via hole h1.
  • the fourth via hole h4 penetrates the first interlayer insulating layer 105, and the fourth signal connection section 501 is connected to the second connection terminal a2 through the fourth via hole h4.
  • the first source electrode 1024 and the first drain electrode 1025 are connected to the first active layer 1021 through the first contact hole cnt1 and the second contact hole cnt2 respectively.
  • the second interlayer insulating layer 106 is disposed on the first interlayer insulating layer 105 , and the second via hole h2 penetrates the second interlayer insulating layer 106 .
  • the second signal connection section 402 is connected to the first signal connection section 401 through the second via hole h2.
  • the fifth via hole h5 penetrates the second interlayer insulating layer 106, and the fifth signal connection section is connected to the fourth signal connection section through the fifth via hole.
  • the thin film transistor of the gate driving circuit 102 may be a bottom gate thin film transistor, a top gate thin film transistor or a double gate thin film transistor.
  • the gate driving circuit 102 is a double gate thin film transistor.
  • a gate type thin film transistor is described as an example, but is not limited thereto.
  • the first active layer 1021 is a low temperature polysilicon active layer.
  • Low Temperature Polysilicon (Low Temperature Polysilicon) Poly-Silicon (LTPS) technology is another new technology in the field of flat panel displays, the next generation technology after amorphous silicon (a-Si).
  • Low-temperature polysilicon display panels have the advantages of faster electron mobility, smaller film circuit area, higher resolution, lower power consumption, and higher stability.
  • FIG. 4 is a schematic structural diagram of a display function layer provided by an embodiment of the present application.
  • the pixel driving circuit layer 20a includes a base layer 201, a second active layer 202, a third gate electrode 204, an insulating layer 203, a third gate electrode 204, an interlayer dielectric layer 205, a second source electrode 206, a second drain electrode 207 and Planarization layer 208.
  • the base layer 201 is disposed on a side of the second interlayer insulating layer 106 away from the first interlayer insulating layer 105 .
  • the second active layer 202 is disposed on a side of the base layer 201 away from the second interlayer insulating layer 106, and the orthographic projection of the second active layer 202 on the substrate 101 is located within the orthographic projection of the light shielding layer 108 and the substrate 101. .
  • the insulating layer 203 is disposed on a side of the second active layer 202 away from the base layer 201 .
  • the sixth via hole h6 penetrates the insulating layer 203 and the base layer 201 , and the sixth signal connection section 503 is connected to the fifth signal connection section 502 through the sixth via hole h6 .
  • the third gate 204 is disposed on a side of the insulating layer 203 away from the second active layer 202 .
  • the third connection terminal a3 is connected to the sixth signal connection section 503 and is in the same layer and material as the third gate electrode 204 .
  • the interlayer dielectric layer 205 is disposed on the side of the third gate 204 away from the insulating layer 203 .
  • the third via hole h3 penetrates the interlayer dielectric layer 205, the insulating layer 203 and the base layer 201, and the third signal connection section 403 is connected to the second signal connection section 402 through the third via hole h3.
  • the pixel driving circuit layer 20a has a third contact hole cnt3 and a fourth contact hole cnt4.
  • the third contact hole cnt3 and the fourth contact hole cnt4 penetrate the interlayer dielectric layer 205 .
  • the second source electrode 206 and the second drain electrode 207 are disposed on the interlayer dielectric layer 205 and are connected to the second active layer 202 through the third contact hole cnt3 and the fourth contact hole cnt4 respectively.
  • the fourth connection terminal a4 and the second source electrode 206 are in the same layer and made of the same material, and the fourth connection terminal a4 is connected to the third signal connection section 403 .
  • the planarization layer 208 is disposed on the interlayer dielectric layer 205 and covers the second source electrode 206 and the second drain electrode 207 .
  • the first signal connection line 40 and the second signal connection line 50 in the embodiment of the present application are formed in the process of forming the metal wiring required for the display panel 100. There is no need to introduce additional processes and reduce the cost of the display panel 100. production costs.
  • the second active layer 202 is a metal oxide active layer.
  • the material of the second active layer 202 may be selected from indium gallium zinc oxide.
  • Metal oxide semiconductors have the characteristics of large mobility, high on-state current, better switching characteristics, and better uniformity. They can be suitable for applications that require fast response and large current, such as high frequency, high resolution, and large size. Displays and organic light-emitting displays, etc.
  • the light-emitting functional layer 20b includes an anode 210, a pixel definition layer 209, a light-emitting layer 211 and a cathode 212.
  • the anode 210 is connected to the second drain electrode 207 through a via hole.
  • the pixel definition layer 209 has openings, and the openings of the pixel definition layer 209 expose the surface of the anode 210 .
  • the light emitting layer 211 is disposed within the opening of the pixel defining layer 209 .
  • the cathode 212 is disposed on the side of the light-emitting layer 211 away from the anode 210 .
  • the signal transmission layer 10 further includes a light-shielding layer 108 .
  • the light-shielding layer 108 is disposed on a side of the second interlayer insulating layer 106 away from the first interlayer insulating layer 105 , and the light-shielding layer 108 is connected to the first drain electrode 1025 through a via hole.
  • the orthographic projection of the light shielding layer 108 on the substrate 101 covers the orthographic projection of the second active layer 202 on the substrate 101 .
  • the light-shielding layer 108 can be used to reduce the electromagnetic interference of the signal transmission layer 10 to the display function layer 20, and can block the interference caused by the substrate 101.
  • the external light incident from the side improves the stability of the display panel 100 .
  • the display panel 100 further includes a seventh via hole h7 that penetrates part of the insulating layer of the signal transmission layer 10 .
  • the signal transmission layer 10 also includes connection traces 107 and connection pads 109 .
  • the connection pads 109 are provided on a side of the substrate 101 away from the first interlayer insulating layer 105 .
  • the connection trace 107 is provided in the seventh via hole h7, one end of the connection trace h7 is connected to the connection pad 109, and the other end of the connection trace 107 is connected to the pixel driving circuit layer 20a.
  • the seventh via hole h7 penetrates the first interlayer insulating layer 106 , the second gate insulating layer 104 , the first gate insulating layer 103 and the substrate 101 .
  • connection traces 107 are used to connect the data lines on the pixel driving circuit layer 20a to the connection pads 109, but are not limited thereto.
  • the display panel 100 also includes a driver chip 30 .
  • the driver chip 30 is provided with a connection pad 109 on a side away from the substrate 101 .
  • the driving chip 30 is used to drive the display panel 100 to emit light.
  • the driver chip 30 is bound to the side of the signal transmission layer 10 away from the display function layer 20 , that is, the driver chip 30 is bound to the back side.
  • the driver chip 30 is bound to the display panel by bending. Compared with the arrangement method on the back of the display panel 100 , the frame of the display panel 100 is further reduced, and the proportion of the display area AA of the display surface of the display panel 100 is increased.
  • connection pads 109 include chip connection pads and test connection pads.
  • the embodiments of the present application do not limit the arrangement of the connection pads and the test connection pads.
  • the gate driving circuit 102 corresponds to the outer edge of the display area AA.
  • the first power supply trace 110 is provided outside the gate driving circuit 102 .
  • the second power trace 111 is provided on a side close to the connection pad 109 .
  • the reset signal wiring 113 is provided inside the gate driving circuit 102 .
  • the array test pad 114 is disposed on a side of the second power trace 111 away from the connection pad 109 .
  • the fan-shaped trace 115 is provided between the second power trace 111 and the connection pad 109 for connecting the second power trace 111 and the connection pad 109 .
  • the substrate 101 includes an inorganic layer 1011, a first flexible substrate layer, a first barrier layer 1013 and a second barrier layer 1014 that are stacked in sequence.
  • the first active layer 1021 is provided on the second barrier layer 1014.
  • the connection pad 109 is provided on a side of the inorganic layer 1011 away from the first flexible substrate layer 1012 .
  • the material of the first flexible substrate layer 1012 may include PI (polyimide), PET (polyethylene naphthalate), PEN (polyethylene naphthalate), PC (polyethylene naphthalate), Carbonate), PES (polyethersulfone), PAR (aromatic fluorotoluene containing polyarylate) or PCO (polycyclic olefin).
  • the inorganic layer 1011, the first barrier layer 1013, and the second barrier layer 1014 are composed of one or a stack structure of two or more of silicon-containing nitride, silicon-containing oxide, or silicon-containing oxynitride.
  • the pixel driving circuit layer 20a includes a pixel driving circuit
  • the pixel driving circuit may include a 3T1C type pixel driving circuit, a 4T2C type pixel driving circuit, a 5T2C type pixel driving circuit, or a 6T1C type pixel driving circuit.
  • FIG. 5 is a circuit diagram of a pixel driving circuit of the pixel driving circuit layer provided by an embodiment of the present application.
  • the pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first capacitor C1, a second capacitor C2, and an organic light emitting diode OLED.
  • Each transistor is a P-type thin film transistor.
  • the first transistor T1 is a driving thin film transistor.
  • the gate of the first transistor T1 is electrically connected to one end of the first capacitor (C1) through the first node (A).
  • the source of the first transistor T1 is connected to the second power line. 111 positive voltage.
  • the drain of the first transistor T1 is electrically connected to the anode of the organic light emitting diode OLED.
  • the gate of the second transistor T2 is connected to the nth scan signal SCAN(n) corresponding to the row of the pixel driving circuit, the source of the second transistor T2 is connected to the data signal data, and the drain of the second transistor T2 is connected to the second scan signal SCAN(n).
  • Node B is electrically connected to the other end of the first capacitor C1.
  • the gate of the third transistor T3 is connected to the n+1 scan signal SCAN(n+1) corresponding to the next row of the pixel driving circuit, and the source of the third transistor T3 is electrically connected to the second node B.
  • the drain is connected to the base reference voltage Vref.
  • the gate of the fourth transistor T4 is connected to the nth scan signal SCAN(n) corresponding to the row of the pixel driving circuit.
  • the source of the fourth transistor T4 is electrically connected to the first node A.
  • the drain of the fourth transistor T4 Electrically connected to the anode of the organic light emitting diode OLED.
  • One end of the first capacitor C1 is electrically connected to the first node A, and the other end is electrically connected to the second node B.
  • One end of the second capacitor C2 is electrically connected to the first node A, and the other end is electrically connected to the second power trace 111 .
  • the anode of the organic light-emitting diode OLED is electrically connected to the drain of the first transistor T1 and the drain of the fourth transistor T4, and the cathode is electrically connected to the first power trace 110.
  • the pixel driving circuit provided by the present invention adopts a 4T2C structure. Compared with the existing pixel driving circuit, it only needs to set scanning signals to control the corresponding thin film transistors, which not only plays a compensation role, but also reduces the number of control signals and simplifies The circuit structure is simplified and the cost is reduced.
  • inventions of the present application also provide a method for manufacturing a display panel, please refer to Figure 6 .
  • the manufacturing method of the display panel includes the following steps:
  • Step B001 Provide a signal transmission layer, which is located in the display area of the display panel.
  • the step of providing the signal transmission layer includes providing a flexible substrate, and then providing the connection pad 109 on the flexible substrate.
  • the inorganic layer 1011 and the first flexible substrate layer 1012 are sequentially provided on the flexible substrate 1015.
  • the gate driving circuit 102 is disposed on the first flexible substrate layer 1012 to form a signal transmission layer.
  • the signal transmission layer further includes a plurality of first power supply traces, a plurality of second power supply traces, a plurality of reset signal traces, array test pads and a plurality of sector traces.
  • Step B002 Set a display function layer on the signal transmission layer.
  • the display function layer includes a pixel driving circuit layer and a light-emitting function layer.
  • the pixel driving circuit layer is arranged on the signal transmission layer.
  • the light-emitting functional layer is arranged on the side of the pixel driving circuit layer away from the signal transmission layer.
  • step B003 the flexible substrate 1015 is peeled off using laser peeling, mechanical peeling, dissolution peeling, or other methods to expose the connection pad.
  • Step B003 Bind the driver chip to the connection pad to complete the production of the display panel.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

L'invention concerne un panneau d'affichage (100) comprenant une zone d'affichage (AA). Le panneau d'affichage (100) comprend en outre une couche de transmission de signal (10) et une couche fonctionnelle d'affichage (20) ; la couche de transmission de signal (10) est située dans la zone d'affichage (AA), et comprend un circuit d'attaque de grille (102) ; et la couche fonctionnelle d'affichage (20) comprend une couche de circuit d'attaque de pixel (20a) et une couche fonctionnelle électroluminescente (20b) ; la couche de circuit d'attaque de pixel (20a) est disposée au-dessus de la couche de transmission de signal (10), et la couche fonctionnelle électroluminescente (20b) est disposée sur le côté de la couche de circuit d'attaque de pixel (20a) qui est éloigné de la couche de transmission de signal (10).
PCT/CN2022/115997 2022-07-05 2022-08-30 Panneau d'affichage Ceased WO2024007435A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210793443.5A CN115207054B (zh) 2022-07-05 2022-07-05 显示面板
CN202210793443.5 2022-07-05

Publications (1)

Publication Number Publication Date
WO2024007435A1 true WO2024007435A1 (fr) 2024-01-11

Family

ID=83580626

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/115997 Ceased WO2024007435A1 (fr) 2022-07-05 2022-08-30 Panneau d'affichage

Country Status (2)

Country Link
CN (1) CN115207054B (fr)
WO (1) WO2024007435A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115732514A (zh) * 2022-11-14 2023-03-03 武汉华星光电半导体显示技术有限公司 显示模块及显示面板
CN115811913B (zh) * 2022-11-22 2025-11-11 武汉华星光电半导体显示技术有限公司 一种显示面板及显示装置
CN115955862A (zh) * 2023-01-31 2023-04-11 华映科技（集团）股份有限公司 一种无边框柔性显示面板结构及制作方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110010627A (zh) * 2019-04-12 2019-07-12 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN111341814A (zh) * 2020-03-11 2020-06-26 深圳市华星光电半导体显示技术有限公司 显示面板及显示面板的制作方法
CN111768700A (zh) * 2020-06-22 2020-10-13 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
CN113013209A (zh) * 2021-02-19 2021-06-22 京东方科技集团股份有限公司 一种显示面板及其制备方法、显示装置
CN114078927A (zh) * 2020-08-13 2022-02-22 三星显示有限公司 显示面板、其制造方法及包括显示面板的显示设备
CN114203778A (zh) * 2021-11-30 2022-03-18 长沙惠科光电有限公司 有源矩阵oled显示面板及其制备方法
US20220181431A1 (en) * 2020-12-04 2022-06-09 Lg Display Co., Ltd. Display device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4490650B2 (ja) * 2002-04-26 2010-06-30 東芝モバイルディスプレイ株式会社 Ｅｌ表示装置の駆動方法、およびｅｌ表示装置
US9588549B2 (en) * 2014-02-28 2017-03-07 Semiconductor Energy Laboratory Co., Ltd. Electronic device
CN107248521B (zh) * 2017-06-19 2020-01-31 深圳市华星光电半导体显示技术有限公司 Amoled背板结构
CN111584587B (zh) * 2020-05-20 2023-09-01 京东方科技集团股份有限公司 一种显示面板及其制备方法和拼接屏
CN112068372A (zh) * 2020-09-10 2020-12-11 深圳市华星光电半导体显示技术有限公司 阵列基板及显示面板
CN113192988A (zh) * 2021-04-23 2021-07-30 深圳市华星光电半导体显示技术有限公司 一种显示器件

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110010627A (zh) * 2019-04-12 2019-07-12 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN111341814A (zh) * 2020-03-11 2020-06-26 深圳市华星光电半导体显示技术有限公司 显示面板及显示面板的制作方法
CN111768700A (zh) * 2020-06-22 2020-10-13 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
CN114078927A (zh) * 2020-08-13 2022-02-22 三星显示有限公司 显示面板、其制造方法及包括显示面板的显示设备
US20220181431A1 (en) * 2020-12-04 2022-06-09 Lg Display Co., Ltd. Display device
CN113013209A (zh) * 2021-02-19 2021-06-22 京东方科技集团股份有限公司 一种显示面板及其制备方法、显示装置
CN114203778A (zh) * 2021-11-30 2022-03-18 长沙惠科光电有限公司 有源矩阵oled显示面板及其制备方法

Also Published As

Publication number Publication date
CN115207054B (zh) 2024-12-27
CN115207054A (zh) 2022-10-18

Similar Documents

Publication Publication Date Title
US11063108B2 (en) Organic light emitting diode array substrate and electronic device
CN114023801A (zh) 一种显示基板及其制作方法、显示装置
WO2020207466A1 (fr) Substrat matriciel et son procédé de fabrication, panneau d'affichage et appareil d'affichage
WO2024007435A1 (fr) Panneau d'affichage
CN115132763B (zh) Tft基板、显示模组及电子设备
WO2020150900A1 (fr) Panneau d'affichage, dispositif d'affichage et procédé de fabrication de panneau d'affichage
US20240038783A1 (en) Display device and manufacturing method thereof
CN115394201B (zh) 显示面板和显示装置
CN115425063B (zh) 显示面板和显示装置
KR102562902B1 (ko) 표시장치
US20250174183A1 (en) Display panel and display device
WO2023245676A9 (fr) Circuit d'attaque de pixel et procédé d'attaque associé, panneau d'affichage et appareil d'affichage
CN117276288A (zh) 阵列基板及显示面板
CN117855222A (zh) 驱动背板及其制作方法、显示面板、显示装置
WO2022057542A1 (fr) Fond de panier d'afficheur et son procédé de production, et dispositif d'affichage
CN114627803B (zh) 显示面板、像素驱动电路及显示装置
CN115249717B (zh) Tft基板、显示模组及电子设备
US12133425B2 (en) Display device
WO2024000273A9 (fr) Écran d'affichage et appareil d'affichage
CN119815922B (zh) 驱动背板和显示面板
US12154910B1 (en) Display panels including metal layer having fan-out segment and display terminals including the same
WO2023206278A1 (fr) Panneau d'affichage et son procédé de fabrication, et appareil d'affichage
US20230154930A1 (en) Display panel and display device
KR20230007578A (ko) 표시 장치 및 표시 장치의 제조 방법
US20260033088A1 (en) Display panel and display device

Legal Events

Date Code Title Description
NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 22949999

Country of ref document: EP

Kind code of ref document: A1