WO2024099552A1

WO2024099552A1 - Signal locking method

Info

Publication number: WO2024099552A1
Application number: PCT/EP2022/081287
Authority: WO
Inventors: Henrik FREDRIKSSON; Pallavi PALIWAL
Original assignee: Telefonaktiebolaget LM Ericsson AB
Current assignee: Telefonaktiebolaget LM Ericsson AB
Priority date: 2022-11-09
Filing date: 2022-11-09
Publication date: 2024-05-16
Anticipated expiration: 2025-05-09

Abstract

A method and device for locking and tracking a received signal. The method comprisesreceiving a configuration signal, the configuration signal having a configuration frequency and configuration phase. The method additionally comprises obtaining, from a local oscillator, a local oscillator signal having a local oscillator frequency and calculating a frequency variation, wherein the frequency variation is the difference between the configuration frequency and the local oscillator frequency. The method further comprises setting a receiver frequency using the local oscillator frequency and the frequency variation to lock the receiver frequency to the configuration frequency. The method also comprises calculating a phase variation, wherein the phase variation is the difference between the configuration phase and a configuration predetermined reference phase, and setting a receiver phase correction using the calculated phase variation. In addition, the method comprises receiving a data signal at the receiver frequency, the data signal having a data signal symbol rate and comprising a first data symbol and a second data symbol, each symbol having an associated phase, and processing the data signal using an analogue-to-digital converter. Processing the data signal using the analogue-to-digital converter comprises calculating a corrected first data symbol phase using the receiver phase correction and the phase associated with the first data symbol, and calculating a data phase variation, wherein the data phase variation is the difference between the corrected first data symbol phase and a data predetermined reference phase. Processing the data signal using the analogue-to-digital converter further comprises updating the receiver phase correction using the data phase variation and decoding the second data symbol using the updated receiver phase correction.

Description

SIGNAL LOCKING METHOD

The project leading to this application has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 876124.

Technical Field

Embodiments described herein relate to a method and device for locking and tracking a received signal, in particular method and device for locking and tracking a received signal using an analogue to digital converter (ADC).

Background

In traditional digital communication systems, digital communication between integrated circuits may be done by sending high and low voltages over an electrical wire (known as Pulse Amplitude Modulation-2 (PAM2) modulation). In prior attempts to improve the performance of these links, solutions have included increasing the data-rates by directly increasing the rate at which data is sent or upgrading the modulation scheme to PAM4. Both of these solutions can result in issues with signal integrity, which have typically been addressed by active equalizing techniques. Although these techniques may enable improved data rates, they may also have the associated costs of increased circuit complexity, power requirements, and electrical channel bandwidth requirements. Such solutions also may require redundant coding to generate guaranteed signal activity in order to ensure symbol time locking.

With radio link methodology, for example frequency translated narrow-band modulated signalling, the channel characteristic requirements may be significantly different to traditional wire digital links. Frequency translated modulated digital signalling has been suggested and used with these techniques, which may provide benefits in spectrum efficiency and improved channel characteristics. This may also result in simplified transceiver circuitry and improved efficiency compared to traditional radio transceivers.

In order to achieve higher data rates when using low order modulation such as PAM2 or PAM4 modulation, the low order modulation techniques as described above typically require high symbol rates and therefore wide signal bandwidths. This may prevent the use of radio electronics tuning and matching techniques to improve electrical channel properties. Instead, signal integrity may be ensured by compensating for channel imperfection over the very large used bandwidth with active equalization techniques. In existing systems, bitrate and timing synchronization has been achieved using signal activity in order to guarantee that, redundant coding has been used. This may create additional signalling complexity, and reduce the useful to transmitted bit-rates ratio. Furthermore, previous frequency translating methods may assume no frequency deviation of the mixing (or frequency translation) signals between when the signal was transmitted and when the signal was received. This assumption is often untrue in a real scenario. An example of such a method can be found in “A 7.5-mW 10-Gb/s 16-QAM wireline transceiver with carrier synchronization and threshold calibration for mobile inter-chip communications in 16-nm FinFET” by Du et al, available at: https://dl.acm.org/doi/10.1145/3313231.3352381 as of 21 June 2022.

Previous work regarding the problems discussed above may include receiver architecture with carrier frequency, phase, and symbol phase detection. Such systems may be limited to periodic training symbol tracking and dedicated receiver detection paths, such as those discussed in US 4574244 A. These features may limit system flexibility and introduce inter- receiver-path matching problems. In other previous work, the detection of phase may require more than one extra ADC bit, amplitude tracking may not be present, phase rotation to the correct phase may not be described, and the phase locked loop (PLL) loop filter may be done in the analogue domain. Furthermore, in existing solutions, the PLL frequency locking range may be limited as only the phase of the received signal is used in the locking loop.

Summary

Previously, wide-range locking with a variable phase detection mechanism is not commonly used in the context of clock recovery using ADC based detection. It is an object of the present disclosure to provide methods and devices for locking and tracking a received signal which at least partially addresses one or more of the challenges discussed above. In particular, it is an object of the present disclosure to provide methods and devices for locking and tracking a received signal that may enable efficient, low power and cost, receiver implementation of carrier based digital communication systems. The system enables frequency and phase locking to an incoming modulated signal which may enable efficient detection of the receiver data.

The present disclosure provides a method for locking and tracking a received signal. The method comprises receiving a configuration signal, the configuration signal having a configuration frequency and configuration phase. The method additionally comprises obtaining, from a local oscillator (LO) a LO signal having a LO frequency and calculating a frequency variation, wherein the frequency variation is the difference between the configuration frequency and the LO frequency. The method further comprises setting a receiver frequency using the LO frequency and the frequency variation to lock the receiver frequency to the configuration frequency. The method also comprises calculating a phase variation, wherein the phase variation is the difference between the configuration phase and a configuration predetermined reference phase, and setting a receiver phase correction using the calculated phase variation. That is, the method may comprise correcting the LO signal using the receiver phase correction to set a receiver frequency, thereby changing the phase of the signal into the ADC. In addition, the method comprises receiving a data signal at the receiver frequency, processing the data signal using an ADC to generate a digital data signal, the digital data signal having a data signal symbol rate and comprising a first data symbol and a second data symbol, each symbol having an associated phase, and processing the digital data signal. Processing the digital data signal comprises calculating a corrected first data symbol phase using the receiver phase correction and the phase associated with the first data symbol, and calculating a data phase variation, wherein the data phase variation is the difference between the corrected first data symbol phase and a data predetermined reference phase. Processing the data signal further comprises updating the receiver phase correction using the data phase variation and decoding the second data symbol using the updated receiver phase correction. By determining frequency and phase locking using an incoming modulated signal, there may be reduced requirements on symbol activity, for example by eliminating the need for redundant coding overhead. Embodiments of the present disclosure ensure both frequency translation accuracy and symbol rate accuracy with no overhead in terms of clock reference channels.

Embodiments of the present disclosure may provide tracking mechanisms over a channel using a modulated carrier, enabling radio matching and channel flatness techniques as an alternative way of mitigation inter-symbol interference compared to equalization techniques. The methods disclosed herein may make use of a symbol detection ADC as the phase lock loop phase error detector, reducing the impact of clock and receiver path delay uncertainties and improving the likelihood that the correct symbol is present at the point of detection. In addition, the methods disclosed herein use the phase lock loop output frequency both as a frequency translating reference and symbol rate reference, which may eliminate the need for minimum switching activity or encoding overhead. Embodiments of the present invention may also provide an increased frequency locking range. After initial locking, the method may be run in the background during normal data transmission, reducing the need for regular transmission interruption to keep the link phase-locked. The ADC detection functionality may also used for background symbol amplitude tracking. The present disclosure also provides a device for locking and tracking a received signal. The device comprises a frequency error detector, a phase frequency detector and an ADC. The device is configured to receive a configuration signal using a serial link, the configuration signal having a configuration frequency and configuration phase. The device is further configured to obtain, from a LO, a LO signal having a LO frequency. The device is additionally configured to receive a data signal at the receiver frequency. The frequency error detector is configured to calculate a frequency variation, wherein the frequency variation is the difference between the configuration frequency and the LO frequency, and set a receiver frequency using the LO frequency and the frequency variation to lock the receiver frequency to the configuration frequency. The phase frequency detector is configured to calculate a phase variation, wherein the phase variation is the difference between the configuration phase and a configuration predetermined reference phase and set a receiver phase correction using the calculated phase variation. The ADC is configured to process the data signal to generate a digital data signal, the digital data signal having a data signal symbol rate and comprising a first data symbol and a second data symbol, each symbol having an associated phase. The device is further configured to calculate a corrected first data symbol phase using the receiver phase correction and the phase associated with the first data symbol, and calculate a data phase variation, wherein the data phase variation is the difference between the corrected first data symbol phase and a data predetermined reference phase. The device is further configured to update the receiver phase correction using the data phase variation, and decode the second data symbol using the updated receiver phase correction. The device may provide analogous benefits to the method as discussed above.

Brief Description of Drawings

The present disclosure is described, by way of example only, with reference to the following figures, in which:-

Figure 1 is a flowchart of a method for locking and tracking a received signal in accordance with disclosed embodiments;

Figure 2 is a schematic diagram of a device in accordance with disclosed embodiments;

Figure 3 is a flowchart depicting an embodiment for setting the receiver frequency in accordance with disclosed embodiments;

Figure 4 is a schematic diagram of a device comprising a ripple counter in accordance with disclosed embodiments; Figure 5 is a schematic diagram of a device comprising a cartesian to polar encoder in accordance with disclosed embodiments;

Figure 6 is a schematic diagram of a device comprising a bang-bang encoder in accordance with disclosed embodiments;

Figure 7 is a flowchart depicting an embodiment for switching modes of error detection in accordance with disclosed embodiments.

Detailed Description

For the purpose of explanation, details are set forth in the following description in order to provide a thorough understanding of the embodiments disclosed. It will be apparent, however, to those skilled in the art that the embodiments may be implemented without these specific details or with an equivalent arrangement.

Aspects of embodiments provide signal locking and tracking devices and methods (for the present disclosure example, for a digital PLL) through the use of phase tracking. In particular, embodiments of may provide a method to lock and track modulated signals using quadrature amplitude modulation (QAM), for example QAM-4, QAM-16, and QAM-64, in low interference transmission systems. Embodiments of the disclosure may enable frequency and phase locking to an incoming modulated signal, which may provide efficient detection of the receiver data.

Methods and devices according to the present disclosure may use a known and fixed ratio between the carrier frequency and symbol rate. With this, the signal receiver path may be used as a part of a PLL loop to achieve a frequency lock and to stay locked to the transmitter carrier and symbol frequencies. The method may use a symbol detecting ADC to generate an error regarding the received signal. The method may then lock the received signal to the correct phase using the generated error, enabling direct decoding of QAM modulated data using an ADC. Embodiments of the present disclosure therefore may provide a large frequency locking range by using a base-band frequency counting mechanism during initial locking. After locking is achieved, for example by using a known symbol, the system may then detect the phase of the received signal during normal data-transmission in the background with no need for further periodic relocking or data edge detection as required in prior solutions, that would interrupt continuous and deterministic data transmissions.

Figure 1A and Figure 1 B (collectively Figure 1) are flowcharts of a method for locking and tracking a received signal according to embodiments of the present disclosure. Figure 2 is a schematic diagram showing a device 201 in accordance with aspects of the embodiments. The device may perform the method of Figure 1.

The device may be a digital phase locked loop (DPLL). The DPLL may be connected to a receiver path, and may comprise a mixer 203, filter 204 and symbol detection ADC 206. The filter 204 may be a baseband filter.

In Step S101 of the Figure 1 method, as shown in Figure 1A, the device 201 receives a configuration signal. The configuration signal may have a configuration frequency and a configuration phase. The configuration frequency of the configuration signal may be measured. The configuration signal may be received, for example, by a serial link 202 connected to the device 201. The configuration signal may comprise a plurality of symbols, each having a symbol frequency and a symbol phase. Each of the plurality of symbols may have the same symbol frequency and the same symbol phase. That is, the configuration signal may be a constant symbol at a carrier frequency on an input-output (I/O) link. The device 201 may comprise a baseband filter 204 for noise filtering, for example by suppression the sum frequency from a mixer 203. The configuration signal may be downconverted into an in- phase/quadrature (l/Q) signal by the mixer 203.

In Step S102 of the Figure 1 method, the device receives a local oscillator (LO) signal. The LO signal has an associated LO frequency. The device may be configured to receive the LO signal using a mixer 203. The mixer 203 may be fed a LO frequency controlled by a receiver PLL structure 215. Alternatively, the device 201 may obtain the LO frequency from any suitable local oscillator. The device, and more specifically the mixer 203 of the device, may translate any incoming or received frequency by performing a frequency translation function, such as down mixing. For example, in embodiments of the present disclosure there may be a fixed relationship between the receiver frequency (that is, the corrected LO frequency) and symbol rate. Thus, locking and tracking the LO frequency by setting a receiver frequency may also ensure tracking of the symbol rate. The ADC sampling rate may be the same as the symbol rate, and thus the symbol rate may be determined by a frequency divider 207.

In Step S103 of the Figure 1 method, the device 201 calculates a frequency variation or frequency error. The frequency variation may be the difference between the configuration frequency and the LO frequency. In Step S104 of the Figure 1 method, the device 201 sets a receiver frequency. Steps S103 and S104 as depicted in Figure 1A may be undertaken by a frequency error detector 205 of the device 201 . The lead/lag phase of the downconverted l/Q signal may represent the sign of frequency error in the receiver LO. Setting the receiver frequency may be achieved using the LO frequency and the frequency variation to lock the receiver frequency to the configuration frequency.

Taking a look at a specific example, a received signal can be expressed in the form A cos )t + B sin a , where A and B are amplitude coefficients, oa is the angular frequency associated with the received signal and t is the time associated with the received signal. Using standard trigonometric identities, the mixer 203 may calculate the sum and difference between the configuration signal or input signal and the LO signal. Specifically, the configuration signal may be considered to be cos a and the LO signal taken to be cos b. Trigonometric identities that can be used by the mixer to process the configuration signal and LO signal include cos(a — b) + cos(a + b)) cos(a) x cos(b) = - - - and

The filter 204 may then suppress the sum of configuration signal cos a and LO signal cos b. The mixer 203 may be a complex values mixer, wherein the inputs are cos oa_LOt in a first branch of the mixer and sin oa_LOt in a second branch of the mixer, wherein oa_LO is the angular frequency associated with the LO frequency. The mixer 203 may therefore identify a full set of phases of the configuration signal, that is, all values of A and B wherein the configuration signal is expressed in the form A cos art + B sin cat.

The configuration signal can also be expressed in complex form using known identities. Thus, for an configuration signal cos oat, after filtering by the filter 204 the mixer will have cos (o> -

aa_L0)t in the first branch and - |sin (o> - aa_L0)t in the second branch, wherein aa is the input angular frequency and oa_LO is the LO angular frequency.

The device, acting as an initial locking mechanism, may use the signals after filtering to adjust the LO angular frequency oa_LO to match input angular frequency oa such that oa_LO = aa. oa_LO is generated in a quadrature digitally controlled oscillator (QDCO) 212 and the frequency associated with oa_LO may be controlled by the digital part of the PLL structure 210, 211 , 213, 214. The order for the receiver frequency to be calculated, the frequency variation may be converted from the analogue domain (that is, the signal output from filter 204) to the digital domain. This conversion may be done in one of three ways, depending on the size of the frequency variation and the accuracy needed to lock to the correct phase. For large frequency differences, error detector 205 may be used. For example, the zero crossings of cos (o> - )_L0)t may be

counted for a fixed time period, wherein the number of crossings is a measure or indicator of the frequency variation. Because there may be no difference in the number of counted zero crossings for the case that

> a>_L0, a further method of detecting whether is greater or smaller than a>_L0 may also be needed in order to ensure that the frequency variation generated by the QDCO 212 is correct. Thus, error detector 205 may also compare or sample the - 1 sin (o> - )_L0)t signal with the zero crossings of the cos(o> - a>_L0) t signal, with the sign

of the - |sin (o> - )_L0)t signal indicating whether a> is greater or smaller than a>_L0.

When the frequency variation is small, there may be no zero crossings to count within the fixed time period and thus another method for frequency variation detection may be needed. In such a case, a phase frequency detector 208 may be used to determine the frequency variation. For example, the phase frequency detector 208 may be a polar-to-cartesian converter. When the output of the QDCO 212 is aligned with the reconfiguration signal or input signal, for example as postulated by a test-pattern based on the output of phase frequency detector 208, sign error tracking can be performed using bang-bang encoder 209.

The method steps detailed above for locking the receiver frequency may be iterative. That is, the process for locking the receiver frequency may be an iterative process. Figure 1 presents one method of operation wherein no iterative process is undertaken, however each of the method steps presented therein may be repeated individually or in combination in order to form an iterative process.

Figure 3 is a flowchart depicting an embodiment for setting the receiver frequency. Calculating the frequency variation may comprise determining a coarse frequency variation using a coarse varactor bank and determining a fine frequency variation using a fine varactor bank. Setting the receiver frequency may comprise applying the coarse frequency variation and the fine frequency variation.

As detailed above, the device 201 may comprise a frequency error detector 205, and the frequency error detector 205 may comprise an asynchronous comparator and a baseband frequency counter. The baseband frequency counter may produce a baseband signal in the receiver. The baseband signal in the receiver may correspond to the frequency difference between the local oscillator frequency and the configuration frequency. The receiver PLL structure 215 may therefore use the frequency error detector 205 to generate an error to use as an input to its loop filter.

Based on the loop gain controller (210) output, the device may activate different forms of error detection to lock to accurate phase and frequency. Figure 3 highlights the state machine used by the gain controller. When the device is activated, as shown in Step S301 of Figure 3, the frequency error detector 205 may be activated for locking the receiver frequency (Rx frequency) to lock to configuration or transmitted frequency (Tx frequency) with coarse resolution (for example, with DCO gain of 20MHz/LSB). As discussed above, in the case where the frequency variation (or phase error) can not be tracked using baseband frequency counter or error detector 205, the loop needs to switch to phase frequency detector 208 for frequency variation detection (Step S302 of Figure 3). In the case where the phase frequency detector 208 is a cartesian-to-polar converter 208, the cartesian to polar encoder based detection can track the phasor movement on an l/Q plot, for example as presented in Figure 5 and Figure 6B. This may be appropriate, for example, for the input error signal having frequency less than ff_ the Nyquist rate is the sampling frequency of the digital system). The cartesian

to polar encoder may be activated when the input frequency error f_err is an order of 10 times lower than the sampling frequency ff of the digital part of the system. The cartesian-to-polar b converter 208 may aid the device to lock to the receiver frequency and configuration frequency with a finer resolution (e.g. DCO gain of 20KHz/LSB), for example where the instantaneous frequency error is limited by the DCO quantization. The gain controller 210 may use mechanisms like tracking the average frequency control word (FCW) over consequtive sampling instants, to determine when the receiver frequency has locked to the training or configuration signal. When the average or mean value of the FCW has stabilized, the gain controller 210 may then activate bang-bang detector 209, for the receiver frequency to be able to track the estimated frequency and phase of incoming signals (Step S303 of Figure 3). The bang-bang encoder 209 may be a l/Q constellation based bang-bang encoder. During the training phase, in case of change in the frequency of incoming signal, the state machine could switch back to the detection using baseband frequency counter when frequency error f_err between the receiver frequency and configuration frequency is greater than the system sampling frequency ff/b (Step S304 of Figure 3). The system may use hysteresis-like condition to switch between baseband frequency detector 205 and cartesion-to-polar encoder 208, so as to maintain loop stability. The baseband frequency counter may be a ripple counter. Figure 4 (comprising Figure 4A, Figure 4B, Figure 4C and Figure 4D) depicts an embodiment comprising a ripple counter. As shown in Figure 4, the ripple counter may operate as a frequency detector on the asynchronous comparator output (doutmidasyncl/doutmidasyncQ) of baseband signal. Figure 4A is a schematic diagram showing an embodiment in which a ripple counter is used as a frequency detector. Figure 4B illustrates a scenario when a valid error has been detected by the ripple counter, for example detecting a zero crossing of an l/Q signal. Figure 4C illustrates a scenario of the lead/lag phase of an l/Q signal being captured using a D-flipflop. For example, in the case where the Q-signal is leading the l-signal as depicted in Figure 4C, it is indicated that the frequency correction has to be applied in the negative direction. The frequency error magnitude (count<n:0>) and sign (error_sigri) information can be reset in each feedback clock dycl (ff/b) used as reference (ref_clk), using edge detector operating on a higher frequency clock (LO_clk), as shown in Figure 4D.

In step S105 of the Figure 1 method, the device 201 calculates a phase variation. The device 201 may comprise a phase frequency detector 208 that is configured to calculate the phase variation. The phase variation may be the difference between the configuration phase and a configuration predetermined reference phase. In step S106 of the Figure 1 method, the device 201 sets a receiver phase correction. The phase frequecy detector 208 of the device 201 may be additionally configured to set the receiver phase correction. The step of setting the receiver phase correction may use the calculated phase variation. According to some embodiments of the present disclosure, the configuration predetermined reference phase may be obtained from system configuration information of the receiver. The configuration predetermined reference phase may be 45 degrees. Alternatively, the receiver could obtain the configuration predetermined reference phase through other means, such as a transmission received using the serial link 202.

In addition to locking the receiver frequency, the device 201 may lock to a receiver phase or the phase of an incoming training symbol, such that the baseband-l and -Q signals are in quadrature. This allows for constellation diagrams to be generated, such as those depicted in Figure 5 and Figure 6 (comprising Figure 6A and Figure 6B). The l/Q signal based phase frequency detector and its transfer characteristics are highlighted in Figure 5. As shown in Figure 5, phase frequency detector 208 and/or bang-bang encoder 209 may comprise a cartesian to polar encoder that may generate a constellation diagram. The cartesian to polar encoder may be a comparator and multiplexer-based encoder. The magnitude of an l/Q signal may be represented using an ADC output with 15 detection levels as illustrated in Figure 5A. For example, for QAM modulation of type QAM-X where X is any of 4/16/64, there will

constellations in the I domain and

constellations in the Q domain. In order to detect

constellation levels, the device should be configured to have V - 1 detection levels. For phase and amplitude tracking there should to be an additional

detection levels. Thus, in total for each of the I and Q paths respectively there needs to be 2V - 1 detection levels. For example, for QAM-64 one ADC with 15 detection levels will be needed for the l-path of an l/Q signal and one ADC with 15 detection levels will be needed for the Q-path of the l/Q signal. Thus, an ADC output with 15 detection levels allows for detecting all constellation levels present for a QAM-64 modulation. This equation can also be used to determine the required number of detection levels for other QAM modulations, such as QAM- 256 and QAM-1024.

The cartesian to polar encoder may then digitize the signal by calculating the quadrant location of the signal in an l-Q plot, as shown in Figure 5B. The quadrant location of the digitized signal in the l-Q plot may be identified in each reference clock cycle (f_f/ ). The direction of l/Q signal movement across different quadrants of l-Q plot, in consecutive reference clock cycles, may indicate the sign of frequency correction that is required. If the l/Q signal is traversing across the polar coordinates in clockwise direction, the frequency may need to be increased with Q- signal leading l-signal. Similarly, the l/Q polar coordinates traversing in anti-clockwise direction, may indicate I leads Q, and the frequency may need to be decreased to reach the right phase.

Steps S101 to S106 as depicted in Figure 1A may be considered a ’’training phase”, while steps S107 to S114 may be considered a ’’data phase”. In step S101 of the training phase, the device 201 may receive a configuration signal. The configuration signal may have a configuration frequency and a configuration phase. The configuration frequency of the configuration signal may be measured. The configuration signal may be received, for example, by a serial link 202 connected to the device 201. The configuration signal may comprise a plurality of symbols, each having a symbol frequency and a symbol phase. Each of the plurality of symbols may have the same symbol frequency and the same symbol phase. That is, the configuration signal may be a constant symbol at a carrier frequency on an input-output (I/O) link. During the training phase, base-band frequency counting and full rotation base-band phase rotation ensure an improved frequency locking range. During the training phase, a constant (l,Q) symbol of (1 ,1), for example, may be transmitted on the link for the receiver PLL to lock, or to receive as the configuration signal. For an (I ,Q) symbol of (1 ,1), the configuration phase is 45 degrees, which is depicted as a configuration phase or reference phase of 45 degrees on the l-Q plot in Figure 5B. During the locking process, while l/Q signal is traversing across different coordinates, the correction that is applied by the phase detector is presented as arrows in Figure 5B. The sign of phase or frequency correction may be updated only while the (I ,Q) signal traverses first quadrant, to aid the Rx PLL getting locked to the reference phase or configuration phase as depicted in Figure 5B. The direction of (l,Q) coordinate movement may be captured by comparing quadrant change from a previous clock cycle to a current clock cycle.

In step S107 of the Figure 1 method, the device 201 receives a data signal. The device 201 may be configured to receive this data signal via a serial link 202. The data signal may be received at the reciever frequency. The data signal may have a data signal symbol rate and may comprise a first data symbol and a second data symbol, each symbol having an associated phase. The data transmission may be initiated on the serial link after the receiver PLL 215 or device 201 is locked to the training or configuration symbol. Alternatively, data transmission may be initiated on the serial link after the receiver PLL 215 or device 201 is locked to the configuration phase.

In step S108 of the Figure 1 method, the device 201 processes the data signal using an ADC to produce a digital data signal. In step S109 of the Figure 1 method, the device 201 processes the digital data signal. A flowchart of an embodiment of the processing of the digital data signal process is depicted in Figure 1 B, comprising steps S111 to S114. This method may be performed by a bang-bang encoder 209, as depicted in Figure 6A. The bang-bang encoder 209 may be, or may form part of, an ADC.

The device 201 may further comprise a loop gain controller 210, in order to control the filter gain. This may ensure that the device 201 can operate with different phase detectors.

The device may also further comprise a low pass filter 211 , a quadrature digitally controlled oscillator 212, and a ZA modulator 213 to produce an LO signal. The ZA modulator may improve the signal from a digital core oscillator (DCO). For example, the ZA modulator output signal may be used to control the DCO output when the DCO acts as an LO. The DCO output may consist of a sine and cosine signal (two signals in quadrature configuration, as detailed above) which are multiplied with the configuration signal by mixer 203. However, alternatives to the use of a DCO are also envisaged; for example, generating the quadrature LO signals can be done by a DCO generating a single at twice the LO frequency, followed by a quadrature divider or quadrature digitally controlled oscillator 212. The quadrature digitally controlled oscillator 212 may generate a quadrature signal for frequency translation of the incoming signal. Alternatively, a charge pump, analogue loop filter and voltage controlled oscillator can be used instead of the low pass filter 211 , quadrature digitally controlled oscillator 212, and ZA modulator 213 to generate a quadrature LO signal.

The device 201 may comprise a multiplexer 214, which controls the signal being processed for each stage of the method being performed. For example, the multiplexer 214 may select the output from the baseband frequency counter when the coarse varactor bank is active. The multiplexer 214 may select the output from the phase frequency detector 208 when the fine varactor bank is active. The multiplexer 214 may select the output from the bang-bang encoder 209 when the device 201 is processing a data signal.

In step S111 of the Figure 1 method, the device 201 calculates a corrected first data symbol phase. The first data symbol phase may be calculated using the receiver phase correction and the phase associated with the first data symbol. In Step S112 of the Figure 1 method, the device 201 calculates a data phase variation. This data phase variation may be the difference between the corrected first data symbol phase and a data predetermined reference phase. In step S113 of the Figure 1 method, the device 201 updates the receiver phase correction. This may be updated using the data phase variation. In Step S114 of the Figure 1 method, the device 201 decodes the second data symbol using the updated receiver phase correction.

As depicted in Figure 6B, the l/Q plot of a received data signal can be partitioned into reference thresholds around ideal constellation points, with the number of thresholds dependent on whether QAM-4/16/64 is activated as the multi-level signaling on the serial link. Based on the l-Q coordinates of the received data symbol being processed, its angular error around the ideal constellation point can be estimated and the phase up/down correction for the corresponding reference bin can be applied. The l-Q coordinates of the received data symbol corresponds to the data symbol phase, and the coordinates of the ideal constellation point corresponds to the data predetermined reference phase. The data predetermined reference phase may be selected from a plurality of known reference phases, wherein the plurality of reference phases form the set of available constellation points as depicted on the associated constellation diagram. The set of available constellation points may be predetermined. The data predetermined reference phase may be selected as the closest constellation point to the received data symbol phase. For illustrative purposes, Figure 6 depicts signal and phase detection for different modulation steps. In each of the constellation diagrams of Figure 6B, the dotted lines depict ’’dead zones” between possible constellation points. These dead zones form points at which an ideal constellation point may not be determined. Thus, the blue dotted lines in Figure 6B represent the thresholds where the decisions on which data-information the current received symbol is changes. That is, a comparison between the data signal and the threshold lines allow for a determination as to which constellation point the data signal best corresponds to. In order to determine where an incoming data signal lies with respect to the threshold lines, the ADC may have another set of comparison levels which compare the data signal with the expected level of the constellation points. In some embodiments, first the reuslts from comparing the data signal with the data reference values or threshold values (blue dotted lines) are used to determine the most likely received constellation point data. Then, the comparison results from comparing the data signal to the particular expected points (the constellation points) are used to estimate the sign of the phase error or phase correction. In the case where a data signal falls on a blue dotted line, or if the comparision between the data signal constellation point results in a difference of (0,0), the detection cannot determine the sign of the phase error and the dat signal is considered to be in a detection dead-zone.

By way of example, consider the QAM-4 mode part of Figure 6B: for the case where the data recovery part of the ADC processing the data signal detects the signal to be [1=1 , Q=1], the recovered symbol is identified as [11], In addition, the I and Q received data can be compared to the reference value of a constellation point as depicted in Figure 6B. If the data from these comparisons show [l=0, Q=1] then the detected data point are identified as too low in phase (indicated as a counterclockwise arrow in Figure 6B). If the constellation point comparison instead shows [1=1 , Q=0] then the detected data point are identified as too high in phase (indicated as a clockwise arrow in Figure 6B). For the case the received data signal is determined to be [l=0, Q=0] or [1=1 , Q=1], the result is interpreted as in a dead zone for phase error detection. Note that the interpretation of low and high phase depends on where in the constellation diagram the detected data is found.

For the QAM-16 case in Figure 6B, the a received data symbol with [1=1 , Q=0] may be determined to be too low phase (marked counterclockwise) and [l=0, Q=1] represent too high phase (marked clockwise). The interpretation of dead zone will also differ depending on detected constellation. For the QAM-64 example in Figure 6B, the center-bits or [Q=7], in the implemented scaling, may represent a detecting of too low phase regardless of constellation point I result. Similarly, [Q=5] may represent detecting a too high phase regardless of I result in the QAM-64 example in Figure 6B. Generally, it is only the constellation points found in the diagonal of the constellation diagram that experience the dead-zone in terms of phase detection capability. The interpretation of low or high phase error may be done by mapping the ADC-I and ADC-Q results (of data-reference threshold bits and constellation point bits) words to low-phase, high-phase, or no detected phase error in a truth-table. Based on the limited number of possible combinations (ADC-I and ADC-Q inputs), this can be implemented more efficiently in standard digital logic gates.

The switching of the Rx DPLL across different modes of error detection, varactor banks and associated variable loop gain is summarized in Figure 7. On power-up, the coarse varactor bank may be controlled by a Type-1 loop. The coarse varactor bank may have a resolution of 20MHz/LSB. The locking of fine varactor bank may be governed using type-2 loop and the discussed ADC based phase detectors. The fine varactor bank may operate with a resolution of 200kHz/LSB.

For bang-bang encoder to more accurately estimate the incoming symbol and its associated angular error, the ADC may present output on full-scale. Thus, an amplitude tracker may be used at the ADC output to correct the scaling and common-mode within the ADC. The ADC amplitude tracking may work as a type-1 loop within the receiver, and may operate on a smaller bandwidth in comparison to that of the PLL, to avoid hindrance in the clock recovery operation.

In an embodiment of the present disclosure, the first data symbol may comprise a first in-phase component and a first quadrature component, the first in-phase component may have a first in-phase amplitude and the first quadrature component may have a first quadrature amplitude. In such embodiments, the method as depicted in Figure 1 may optionally comprise comparing the first in-phase amplitude to an in-phase predetermined reference amplitude and calculating an in-phase amplitude variation. The in-phase amplitude variation may be the difference between the first in-phase amplitude and the in-phase predetermined reference amplitude. The method may additionally comprise comparing the first quadrature amplitude to a quadrature predetermined reference amplitude and calculating a quadrature amplitude variation. The quadrature amplitude variation may be the difference between the first quadrature amplitude and the quadrature predetermined reference amplitude. Further, the method may comprise setting a receiver amplitude correction using the in-phase amplitude variation and quadrature amplitude variation and decoding the second data symbol using the receiver amplitude correction. Device 202 may comprise an amplitude error detector configured to perform additional steps detailed above. The device may comprise at least four comparators. At least two comparators may be configured to measure the first in-phase amplitude. At least two comparators may be configured to measure the first quadrature amplitude. One of each pair of comparators may be used to randomly select a constellation point to speculatively compare the data signal to, and the other of each pair of comparators may be used to compare the threshold line with the data signal. Alternatively, more than two comparators may be used for each comparison stage (for example, for higher order modulations). Setting a receiver amplitude correction using the in-phase amplitude variation and quadrature amplitude variation may comprise adjusting a gain of the received signal or adjusting an amplitude detection level in the ADC.

The device 201 may further comprise a frequency divider 207. The frequency divider 207 may be configured to set a relationship between the LO frequency and the data signal symbol rate. That is, the locking structure of device 201 locks the receiver frequency and receiver phase correction to incoming data using a fixed relationship between LO frequency and data symbol frequency. Thus, dedicated tracking mechanism that are used in prior art devices and introduce coding overhead to guarantee enough symbol transitions for tracking to take please are avoided and replaced by a frequency divider 207; unnecessary coding overhead can therefore be avoided. This may be done during the training phase or after a data signal is received.

As well as a locking structure, the device 201 can additionally be used as a PLL.

In general, the various exemplary embodiments may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device, although the disclosure is not limited thereto. While various aspects of the exemplary embodiments of this disclosure may be illustrated and described as block diagrams, flow charts, or using some other pictorial representation, it is well understood that these blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.

As such, it should be appreciated that at least some aspects of the exemplary embodiments of the disclosure may be practiced in various components such as integrated circuit chips and modules. It should thus be appreciated that the exemplary embodiments of this disclosure may be realized in an apparatus that incorporates an integrated circuit, where the integrated circuit may comprise circuitry (as well as possibly firmware) for embodying at least one or more of a data processor, a digital signal processor, baseband circuitry and radio frequency circuitry that are configurable so as to operate in accordance with the exemplary embodiments of this disclosure.

References in the present disclosure to “one embodiment”, “an embodiment” and so on, indicate that the embodiment described may include a particular feature, structure, or characteristic, but it is not necessary that every embodiment includes the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to implement such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

It should be understood that, although the terms “first”, “second” and so on may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element, without departing frOom the scope of the disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed terms.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising”, “has”, “having”, “includes” and/or “including”, when used herein, specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components and/ or combinations thereof. The terms “connect”, “connects”, “connecting” and/or “connected” used herein cover the direct and/or indirect connection between two elements.

The present disclosure includes any novel feature or combination of features disclosed herein either explicitly or any generalization thereof. Various modifications and adaptations to the foregoing exemplary embodiments of this disclosure may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings. However, any and all modifications will still fall within the scope of the non-limiting and exemplary embodiments of this disclosure. For the avoidance of doubt, the scope of the disclosure is defined by the claims.

Claims

1. A method for a device to lock and track a received signal, the method comprising: receiving a configuration signal (S101), the configuration signal having a configuration frequency and configuration phase; obtaining, from a local oscillator, LO, a LO signal having a LO frequency (S102); calculating a frequency variation (S103), wherein the frequency variation is the difference between the configuration frequency and the LO frequency; setting a receiver frequency (S104) using the LO frequency and the frequency variation to lock the receiver frequency to the configuration frequency; calculating a phase variation (S105), wherein the phase variation is the difference between the configuration phase and a configuration predetermined reference phase; setting a receiver phase correction (S106) using the calculated phase variation; receiving a data signal (S107) at the receiver frequency; and processing the data signal (S108) using an analogue to digital converter, ADC, to generate a digital data signal, the digital data signal having a data signal symbol rate and comprising a first data symbol and a second data symbol, each symbol having an associated phase; and processing the digital data signal (S109), wherein processing the digital data signal comprises: calculating a corrected first data symbol phase (S111) using the receiver phase correction and the phase associated with the first data symbol; calculating a data phase variation (S112), wherein the data phase variation is the difference between the corrected first data symbol phase and a data predetermined reference phase; updating the receiver phase correction (S113) using the data phase variation; and decoding the second data symbol (S114) using the updated receiver phase correction.

2. A method as claimed in Claim 1, wherein the first data symbol comprises a first in-phase component and a first quadrature component, the first in-phase component having a first in- phase amplitude and the first quadrature component having a first quadrature amplitude, and wherein the method further comprises: comparing the first in-phase amplitude to an in-phase predetermined reference amplitude; calculating an in-phase amplitude variation, wherein the in-phase amplitude variation is the difference between the first in-phase amplitude and the in-phase predetermined reference amplitude; comparing the first quadrature amplitude to a quadrature predetermined reference amplitude; calculating a quadrature amplitude variation, wherein the quadrature amplitude variation is the difference between the first quadrature amplitude and the quadrature predetermined reference amplitude; setting a receiver amplitude correction using the in-phase amplitude variation and quadrature amplitude variation; and decoding the second data symbol using the receiver amplitude correction.

3. A method as claimed in Claim 2, wherein the method further comprises: measuring the first in-phase amplitude using at least two comparators; and measuring the first quadrature amplitude using at least two further comparators.

4. A method as claimed in either of Claims 2 or 3, wherein setting a receiver amplitude correction using the in-phase amplitude variation and quadrature amplitude variation comprises: adjusting a gain of the received signal or adjusting an amplitude detection level in the ADC.

5. A method as claimed in any preceding claim, wherein calculating a frequency variation comprises: determining a coarse frequency variation using a coarse varactor bank; determining a fine frequency variation using a fine varactor bank; and wherein the step of setting the receiver frequency comprises applying the coarse frequency variation and the fine frequency variation.

6. A method as claimed in any preceding claim, wherein the method further includes: obtaining the configuration predetermined reference phase from system configuration information of the receiver.

7. A method as claimed in Claim 6, wherein the configuration predetermined reference phase is 45 degrees.

8. A method as claimed in any preceding claim, wherein the configuration signal comprises a plurality of symbols, each symbol having a symbol frequency and a symbol phase.

9. A method as claimed in Claim 8, wherein each of the plurality of symbols has the same symbol frequency and the same symbol phase.

10. A method as claimed in any preceding claim, wherein the method is implemented in a digital phase locked loop, DPLL, locking structure (215) of the receiver device.

11. A method as claimed in claim 10, wherein the method further comprises: measuring the configuration frequency of the configuration signal.

12. A method as claimed in any preceding claim, wherein the method further comprises: setting a relationship between the LO frequency and the data signal symbol rate.

13. A method as claimed in any preceding claim, wherein the data predetermined reference phase is selected from a plurality of known data phases.

14. A device to lock and track a received signal (201), the device (201) comprising a frequency error detector (205), a phase frequency detector (208) and an analogue-to-digital converter, ADC (206), wherein: the device (201) is configured to receive a configuration signal using a serial link (202), the configuration signal having a configuration frequency and configuration phase, obtain from a local oscillator, LO, a LO signal having a LO frequency, and receive a data signal at the receiver frequency; the frequency error detector (205) is configured to calculate a frequency variation, wherein the frequency variation is the difference between the configuration frequency and the LO frequency, and set a receiver frequency using the LO frequency and the frequency variation to lock the receiver frequency to the configuration frequency; the phase frequency detector (208) is configured to calculate a phase variation, wherein the phase variation is the difference between the configuration phase and a configuration predetermined reference phase and set a receiver phase correction using the calculated phase variation; and the ADC (206) is configured to process the data signal to generate a digital data signal, the digital data signal having a data signal symbol rate and comprising a first data symbol and a second data symbol, each symbol having an associated phase; and wherein the device (201) is further configured to calculate a corrected first data symbol phase using the receiver phase correction and the phase associated with the first data symbol, calculate a data phase variation, wherein the data phase variation is the difference between the corrected first data symbol phase and a data predetermined reference phase, update the receiver phase correction using the data phase variation, and decode the second data symbol using the updated receiver phase correction.

15. A device (201) as claimed in Claim 14, wherein the first data symbol comprises a first in- phase component and a first quadrature component, the first in-phase component having a first in-phase amplitude and the first quadrature component having a first quadrature amplitude, and wherein the device further comprises an amplitude error detector, the amplitude error detected being configured to: compare the first in-phase amplitude to an in-phase predetermined reference amplitude; calculate an in-phase amplitude variation, wherein the in-phase amplitude variation is the difference between the first in-phase amplitude and the in-phase predetermined reference amplitude; compare the first quadrature amplitude to a quadrature predetermined reference amplitude; , calculate a quadrature amplitude variation, wherein the quadrature amplitude variation is the difference between the first quadrature amplitude and the quadrature predetermined reference amplitude; set a receiver amplitude correction using the in-phase amplitude variation and quadrature amplitude variation; and decode the second data symbol using the receiver amplitude correction.

16. A device (201) as claimed in Claim 15, wherein the device comprises at least four comparators and wherein: at least two comparators are configured to measure the first in-phase amplitude; and at least two comparators are configured to measure the first quadrature amplitude.

17. A device (201) as claimed in either of Claims 15 and 16, wherein the amplitude error detector is further configured to adjust a gain of the received signal or adjusting an amplitude detection level in the ADC (206).

18. A device (201) as claimed in any of Claims 14 to 17, wherein the device further comprises a coarse varactor bank and a fine varactor bank, and wherein the frequency error detector is further configured to determine a coarse frequency variation using the coarse varactor bank, determine a fine frequency variation using the fine varactor bank, and apply the coarse frequency variation and the fine frequency variation.

19. A device (201) as claimed in any of Claims 14 to 18, wherein the serial link (202) is further configured to obtain the configuration predetermined reference phase from system configuration information of the receiver.

20. A device (201) as claimed in Claim 19, wherein the configuration predetermined reference phase is 45 degrees.

21. A device (201) as claimed in any of Claims 14 to 20, wherein the configuration signal comprises a plurality of symbols, each symbol having a symbol frequency and a symbol phase.

22. A device (201) as claimed in Claim 21, wherein each of the plurality of symbols has the same symbol frequency and the same symbol phase.

23. A device (201) as claimed in any of Claims 14 to 22, wherein the device is a digital phase locked loop, DPLL, locking structure (215) of a receiver device.

24. A device (201) as claimed in Claim 23, wherein the device is further configured to measure the configuration frequency of the configuration signal.

25. A device (201) as claimed in any of Claims 14 to 24, wherein the device further comprises a frequency divider (207), wherein the frequency divider (207) is configured to set a relationship between the LO frequency and the data signal symbol rate.

26. A device (201) as claimed in any of Clams 14 to 25, wherein the device (201) is further configured to select the data predetermined reference phase from a plurality of known data phases.