WO2024093383A1

WO2024093383A1 - Buffer status report

Info

Publication number: WO2024093383A1
Application number: PCT/CN2023/108965
Authority: WO
Inventors: Xiaoying Xu; Mingzeng Dai; Lianhai WU; Yibin ZHUO
Original assignee: Lenovo Beijing Ltd
Current assignee: Lenovo Beijing Ltd
Priority date: 2023-07-24
Filing date: 2023-07-24
Publication date: 2024-05-10
Anticipated expiration: 2026-01-24

Abstract

Various aspects of the present disclosure relate to network entities and methods for supporting buffer status report. In one aspect, a UE determines whether uplink data of at least one logical channel which belongs to at least one logical channel group (LCG) becomes unavailable to a medium access control (MAC) entity of the UE. If the UE determines whether the uplink data becomes unavailable, the UE triggers at least one first Buffer Status Report (BSR) for the at least one logical channel or for the at least one LCG. Each of the at least one first BSR indicates a first buffer size of one of the at least one LCG is equal to zero.

Description

BUFFER STATUS REPORT

TECHNICAL FIELD

The present disclosure relates to wireless communications, and more specifically to an apparatus and a method for supporting buffer status report.

BACKGROUND

A wireless communications system may include one or multiple network communication devices, such as base stations, which may be otherwise known as an eNodeB (eNB) , a next-generation NodeB (gNB) , or other suitable terminology. Each network communication devices, such as a base station may support wireless communications for one or multiple user communication devices, which may be otherwise known as user equipment (UE) , or other suitable terminology. The wireless communications system may support wireless communications with one or multiple user communication devices by utilizing resources of the wireless communication system (e.g., time resources (e.g., symbols, slots, subframes, frames, or the like) or frequency resources (e.g., subcarriers, carriers) . Additionally, the wireless communications system may support wireless communications across various radio access technologies including third generation (3G) radio access technology, fourth generation (4G) radio access technology, fifth generation (5G) radio access technology, among other suitable radio access technologies beyond 5G (e.g., sixth generation (6G) ) .

Extended Reality (XR) , including augmented reality (AR) and virtual reality (VR) , as well as cloud gaming, presents a new promising category of connected devices, applications, and services. XR applications typically requires high throughput and low latency, and have a big packet size, variable data packet size and arrival jitter.

To reuse a padding buffer status report (BSR) with a buffer size of zero as implicit end of data burst (EoDB) indicator for a radio access network (RAN) does not work in some cases. For example, a base station does not determine the buffer size becomes zero for a logical channel group (LCG) according to a received BSR without buffer size of zero for an LCG. For another example, if a UE does not report a BSR, the base station does not determine the buffer size becomes zero for an LCG.

SUMMARY

The present disclosure relates to UEs and methods that support buffer status report. With the methods, a base station can determine a buffer size of at least one logical channel or for at least one LCG becomes zero.

Some implementations of a UE described herein may include: determining whether uplink data of at least one logical channel which belongs to at least one LCG becomes unavailable to a medium access control (MAC) entity of the UE; and based on determining that the uplink data becomes unavailable, triggering at least one first BSR for the at least one logical channel or for the at least one LCG, each of the at least one first BSR indicating a first buffer size of one of the at least one LCG is equal to zero.

In some implementations, the UE is configured to determine that the uplink data becomes unavailable by detecting at least one end of at least one data burst of the at least one logical channel.

In some implementations, the at least one first BSR comprises at least one dedicated BSR.

In some implementations, a first priority of the at least one dedicated BSR is above, equal to or below a second priority of a regular BSR or a periodic BSR.

In some implementations, a first priority of the at least one dedicated BSR is above, equal to or below a second priority of a padding BSR.

In some implementations, the UE is further configured to: based on determining that only one first LCG has data available for transmission, transmit a second BSR in a Short BSR format for the first LCG via the transceiver to a base station, the second BSR comprising a second buffer size which is equal to non-zero.

In some implementations, the second BSR comprises one of the following: a regular BSR, a periodic BSR, or a padding BSR.

In some implementations, the UE is further configured to: based on determining that none of the at least one LCG has data available for transmission, transmit a second BSR in a Short BSR format for one of the at least one LCG via the transceiver to a base station, the second BSR comprising a second buffer size which is equal to zero.

In some implementations, the UE is configured to trigger the at least one first BSR by triggering the at least one first BSR based on determining the following: the uplink data becomes unavailable; and no triggered third BSR indicates the first buffer size is equal to zero.

In some implementations, the UE is further configured not to cancel the triggered at least one first BSR based on determining that an uplink grant can accommodate all pending data available for transmission but is not sufficient to additionally accommodate a MAC control element (CE) and a subheader of the MAC CE, the MAC CE comprising the triggered at least one first BSR.

In some implementations, the UE is configured to determine whether the uplink data of the at least one logical channel which belongs to the at least one LCG becomes unavailable by: receiving, via the transceiver from a base station, a configuration for the least one logical channel or the at least one LCG; and determining whether the uplink data becomes unavailable based on the configuration.

Some implementations of a UE described herein may include: determining a first CG for an autonomous transmission of first delay information, the first delay information indicating first remaining time of a PDCP discard timer; determining a first time point of the autonomous transmission as a first reference time; and determining the first delay information based on a value of the PDCP discard timer and the first reference time.

In some implementations, the UE is further configured to: determine a second CG for an initial transmission of second delay information, the second delay information indicating second remaining time of the PDCP discard timer; determine a second time point of the initial transmission as a second reference time; and determine the second delay information based on the value of the PDCP discard timer and the second reference time.

In some implementations, the UE is further configured to: generate a medium access control (MAC) protocol data unit (PDU) including the second delay information; deliver the MAC PDU and the second CG to an identified hybrid automatic repeat request (HARQ) process; instruct the HARQ process to initiate a first new transmission of the MAC PDU; and cancel the first new transmission.

In some implementations, the UE is further configured to: determine a third CG for a previous autonomous transmission of third delay information, the third delay information indicating third remaining time of the PDCP discard timer; determine a third time point of the previous autonomous transmission as a third reference time; and determine the third delay information based on the value of the PDCP discard timer and the third reference time.

In some implementations, the UE is further configured to: obtain the MAC PDU from the identified hybrid automatic repeat request (HARQ) process of the third CG based on determining that none of at least one physical uplink shared channel (PUSCH) transmission of the MAC PDU has been completely performed; update the MAC PDU with the third delay information; deliver the MAC PDU and the third CG to the identified HARQ process; instruct the HARQ process to initiate a second new transmission of the MAC PDU; and cancel the second new transmission.

In some implementations, the UE is further configured to: obtain the MAC PDU from the identified HARQ process of the first CG based on determining that none of at least one PUSCH transmission of the MAC PDU has been completely performed; update the MAC PDU with the first delay information; and transmit the MAC PDU via the transceiver to a base station.

In some implementations, the UE is further configured to: obtain a MAC PDU from an identified HARQ process based on determining that a CG previous to the first CG was deprioritized.

In some implementations, the UE is configured to determine the first delay information by: based on determining that a first triggered report for the third delay information has not been cancelled, determining the first delay information.

In some implementations, the UE is further configured to: based on determining that a first triggered report for the third delay information has been cancelled, trigger a second report for the first delay information for autonomous transmission over the first CG.

In some implementations, the first CG, the second CG and the third CG are associated with a single HARQ process identity.

Some implementations of a UE described herein may include: determining a status report format for at least one BSR for at least one LCG; and transmitting, to a base station, the at least one BSR in the status report format.

In some implementations, the UE is configured to determine the status report format by: determining a first status report format as the status report format, the first status report format comprising a first field and a second field, the first field being related to a first buffer size of the at least one LCG, and the second field being related to delay information for the at least one LCG, the delay information indicating remaining time of a packet data convergence protocol (PDCP) discard timer.

In some implementations, the first status report format further comprises a third field, and the third field indicates whether the second field is present or not.

In some implementations, the first status report format further comprises a fourth field, and the fourth field indicates whether the first field is present or not.

In some implementations, the UE is configured to determine the first status report format as the status report format by: based on determining that the UE is configured to report the delay information, determining the first status report format as the status report format.

In some implementations, the UE is configured to determine the first status report format as the status report format by: based on determining that the at least one LCG has the delay information available for transmission, determining the first status report format as the status report format.

In some implementations, the UE is configured to determine the first status report format as the status report format by: based on determining that the at least one LCG has data available for transmission and the at least one LCG is configured to report the delay information, determining the first status report format as the status report format.

In some implementations, the UE is configured to determine the status report format by determining a second status report format as the status report format, the second status report format comprising a first field and comprising none of a second field and a third field, the first field being related to a buffer size of the at least one LCG.

In some implementations, the UE is configured to determine the second status report format as the status report format by: based on determining that the at least one LCG has data available for transmission and all of the at least one LCG has no delay information for the at least one LCG available for transmission, determining the second status report format as the status report format, the delay information indicating remaining time of a PDCP discard timer.

In some implementations, the UE is configured to determine the second status report format as the status report format by: based on determining that the at least one LCG has data available for transmission and all of the at least one LCG is not configured to report delay information for the at least one LCG available for transmission, determining the second status report format as the status report format, the delay information indicating remaining time of a PDCP discard timer.

In some implementations, the UE is configured to determine the second status report format as the status report format by: based on determining that an uplink grant is not sufficient to accommodate a first status report format but sufficient to accommodate the second status report format, the first status report format comprising the first field and a second field, the second field being related to delay information for the at least one LCG, the delay information indicating remaining time of a PDCP discard timer.

In some implementations, the at least one LCG comprises a first LCG and a second LCG, a first priority of the first LCG is equal to a second priority of the second LCG, the first LCG has delay information available for transmission, and the second LCG has no delay information available for transmission; and the UE is configured to transmit the at least one BSR by: based on determining that an uplink grant is not sufficient to accommodate the first status report format, and reporting the at least one BSR for the first LCG and the second LCG in an order of the first LCG and the second LCG.

It is to be understood that the summary section is not intended to identify key or essential features of embodiments of the present disclosure, nor is it intended to be used to limit the scope of the present disclosure. Other features of the present disclosure will become easily comprehensible through the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 illustrates an example of a wireless communications system that supports buffer status report in accordance with aspects of the present disclosure;

Fig. 2 illustrates a flowchart of a method that supports buffer status report in accordance with some aspects of the present disclosure;

Fig. 3 illustrates an example of delay information generation and reporting in accordance with some implementations of the present disclosure;

Fig. 4 illustrates a flowchart of a method that supports determination of first delay information in accordance with aspects of the present disclosure;

Fig. 5 illustrates an example of delay information generation and reporting in accordance with some implementations of the present disclosure;

Fig. 6 illustrates a flowchart of a method that supports determination of second delay information in accordance with aspects of the present disclosure;

Fig. 7 illustrates a flowchart of a method that supports report of second delay information in accordance with aspects of the present disclosure;

Fig. 8 illustrates a flowchart of a method that supports report of first delay information in accordance with aspects of the present disclosure;

Fig. 9 illustrates an example of delay information generation and reporting in accordance with some implementations of the present disclosure;

Fig. 10 illustrates a flowchart of a method that supports determination of third delay information in accordance with aspects of the present disclosure;

Fig. 11 illustrates a flowchart of a method that supports report of third delay information in accordance with aspects of the present disclosure;

Fig. 12 illustrates a flowchart of a method that supports determination of status report format in accordance with aspects of the present disclosure;

Fig. 13 illustrates an example of a device that supports buffer status report in accordance with some aspects of the present disclosure;

Fig. 14 illustrates an example of a device that supports report of first delay information in accordance with other aspects of the present disclosure;

Fig. 15 illustrates an example of a device that supports determination of status report format in accordance with other aspects of the present disclosure;

Fig. 16 illustrates an example of a processor that supports buffer status report in accordance with aspects of the present disclosure;

Fig. 17 illustrates an example of a processor that supports determination of first delay information in accordance with aspects of the present disclosure; and

Fig. 18 illustrates an example of a processor that supports determination of status report format in accordance with aspects of the present disclosure.

DETAILED DESCRIPTION

Principles of the present disclosure will now be described with reference to some embodiments. It is to be understood that these embodiments are described only for the purpose of illustration and help those skilled in the art to understand and implement the present disclosure, without suggesting any limitation as to the scope of the disclosure. The disclosure described herein may be implemented in various manners other than the ones described below.

In the following description and claims, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skills in the art to which this disclosure belongs.

References in the present disclosure to “one embodiment, ” “an example embodiment, ” “an embodiment, ” “some embodiments, ” and the like indicate that the embodiment (s) described may include a particular feature, structure, or characteristic, but it is not necessary that every embodiment includes the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment (s) . Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

It shall be understood that although the terms “first” and “second” or the like may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could also be termed as a second element, and similarly, a second element could also be termed as a first element, without departing from the scope of embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the listed terms.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a” , “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” , “comprising” , “has” , “having” , “includes” and/or “including” , when used herein, specify the presence of stated features, elements, and/or components etc., but do not preclude the presence or addition of one or more other features, elements, components and/or combinations thereof.

As described above, to reuse a padding BSR with a buffer size of zero as implicit EoDB indicator for an RAN does not work in some cases.

In a first case, if more than one LCG has data available for transmission and an uplink (UL) grant is not sufficient to accommodate a long padding BSR, but is sufficient to accommodate a short truncated BSR which is truncated for the LCG with the highest priority logical channel with data available for transmission, a base station cannot determine whether the buffer size of an LCG is equal to zero or not.

For example, a UE has an LCG#1, an LCG#2 and an LCG#3. Buffer sizes for LCG#1 and LCG#3 are greater than zero, and a buffer size of LCG#2 is equal to zero. A priority of LCG#1 is higher than a priority of LCG#2, and a priority of LCG#2 is equal to a priority of LCG#3. If a short truncated BSR is used, the short truncated BSR only includes a buffer size of LCG#1 which is greater than zero. In this case, upon receiving the short truncated BSR, a base station cannot determine whether the buffer sizes for LCG#2 and LCG#3 are equal to zero or not.

In a second case, if the UL grant is not sufficient to additionally accommodate any padding BSR medium access control (MAC) control element (CE) and a subheader of the MAC CE, no padding BSR is triggered.

In a third case, if the UL grant is not sufficient to accommodate the triggered BSR, all triggered BSR may be cancelled if all triggered BSRs may be cancelled when at least one UL grant can accommodate all pending data available for transmission but is not sufficient to additionally accommodate the BSR MAC CE and a subheader of the MAC CE.

In view of the above, the present disclosure provides a solution that supports buffer status report. In this solution, a UE determines whether uplink data of at least one logical channel which belongs to at least one LCG becomes unavailable to a MAC entity of the UE. If the UE determines whether the uplink data becomes unavailable, the UE triggers at least one first BSR for the at least one logical channel or for the at least one LCG. Each of the at least one first BSR indicates a first buffer size of one of the at least one LCG is equal to zero. In this way, a base station can determine a buffer size of at least one logical channel or of at least one LCG becomes zero.

Aspects of the present disclosure are described in the context of a wireless communications system.

Fig. 1 illustrates an example of a wireless communications system 100 that supports buffer status report in accordance with aspects of the present disclosure. The wireless communications system 100 may include one at least one of network entities 102 (also referred to as network equipment (NE) ) , one or more terminal devices or UEs 104, a core network 106, and a packet data network 108. The wireless communications system 100 may support various radio access technologies. In some implementations, the wireless communications system 100 may be a 4G network, such as an LTE network or an LTE-advanced (LTE-A) network. In some other implementations, the wireless communications system 100 may be a 5G network, such as an NR network. In other implementations, the wireless communications system 100 may be a combination of a 4G network and a 5G network, or other suitable radio access technology including institute of electrical and electronics engineers (IEEE) 802.11 (Wi-Fi) , IEEE 802.16 (WiMAX) , IEEE 802.20. The wireless communications system 100 may support radio access technologies beyond 5G. Additionally, the wireless communications system 100 may support technologies, such as time division multiple access (TDMA) , frequency division multiple access (FDMA) , or code division multiple access (CDMA) , etc.

The network entities 102 may be collectively referred to as network entities 102 or individually referred to as a network entity 102.

The network entities 102 may be dispersed throughout a geographic region to form the wireless communications system 100. One or more of the network entities 102 described herein may be or include or may be referred to as a network node, a base station (BS) , a network element, a radio access network (RAN) node, a base transceiver station, an access point, a NodeB, an eNodeB (eNB) , a next-generation NodeB (gNB) , or other suitable terminology. A network entity 102 and a UE 104 may communicate via a communication link 110, which may be a wireless or wired connection. For example, a network entity 102 and a UE 104 may perform wireless communication (e.g., receive signaling, transmit signaling) over a Uu interface.

A network entity 102 may provide a geographic coverage area 112 for which the network entity 102 may support services (e.g., voice, video, packet data, messaging, broadcast, etc. ) for one or more UEs 104 within the geographic coverage area 112. For example, a network entity 102 and a UE 104 may support wireless communication of signals related to services (e.g., voice, video, packet data, messaging, broadcast, etc. ) according to one or multiple radio access technologies. In some implementations, a network entity 102 may be moveable, for example, a satellite associated with a non-terrestrial network. In some implementations, different geographic coverage areas 112 associated with the same or different radio access technologies may overlap, but the different geographic coverage areas 112 may be associated with different network entities 102. Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The one or more UEs 104 may be dispersed throughout a geographic region of the wireless communications system 100. A UE 104 may include or may be referred to as a mobile device, a wireless device, a remote device, a remote unit, a handheld device, or a subscriber device, or some other suitable terminology. In some implementations, the UE 104 may be referred to as a unit, a station, a terminal, or a client, among other examples. Additionally, or alternatively, the UE 104 may be referred to as an internet-of-things (IoT) device, an internet-of-everything (IoE) device, or machine-type communication (MTC) device, among other examples. In some implementations, a UE 104 may be stationary in the wireless communications system 100. In some other implementations, a UE 104 may be mobile in the wireless communications system 100.

The one or more UEs 104 may be devices in different forms or having different capabilities. Some examples of UEs 104 are illustrated in Fig. 1. A UE 104 may be capable of communicating with various types of devices, such as the network entities 102, other UEs 104, or network equipment (e.g., the core network 106, the packet data network 108, a relay device, an integrated access and backhaul (IAB) node, or another network equipment) , as shown in Fig. 1. Additionally, or alternatively, a UE 104 may support communication with other network entities 102 or UEs 104, which may act as relays in the wireless communications system 100.

A UE 104 may also be able to support wireless communication directly with other UEs 104 over a communication link 114. For example, a UE 104 may support wireless communication directly with another UE 104 over a device-to-device (D2D) communication link. In some implementations, such as vehicle-to-vehicle (V2V) deployments, vehicle-to-everything (V2X) deployments, or cellular-V2X deployments, the communication link 114 may be referred to as a sidelink. For example, a UE 104 may support wireless communication directly with another UE 104 over a PC5 interface.

A network entity 102 may support communications with the core network 106, or with another network entity 102, or both. For example, a network entity 102 may interface with the core network 106 through one or more backhaul links 116 (e.g., via an S1, N2, N2, or another network interface) . The network entities 102 may communicate with each other over the backhaul links 116 (e.g., via an X2, Xn, or another network interface) . In some implementations, the network entities 102 may communicate with each other directly (e.g., between the network entities 102) . In some other implementations, the network entities 102 may communicate with each other or indirectly (e.g., via the core network 106) . In some implementations, one or more network entities 102 may include subcomponents, such as an access network entity, which may be an example of an access node controller (ANC) . An ANC may communicate with the one or more UEs 104 through one or more other access network transmission entities, which may be referred to as a radio heads, smart radio heads, or transmission-reception points (TRPs) .

In some implementations, a network entity 102 may be configured in a disaggregated architecture, which may be configured to utilize a protocol stack physically or logically distributed among two or more network entities 102, such as an integrated access backhaul (IAB) network, an open radio access network (O-RAN) (e.g., a network configuration sponsored by the O-RAN Alliance) , or a virtualized RAN (vRAN) (e.g., a cloud RAN (C-RAN) ) . For example, a network entity 102 may include one or more of a central unit (CU) , a distributed unit (DU) , a radio unit (RU) , a RAN intelligent controller (RIC) (e.g., a near-real time RIC (Near-RT RIC) , a non-real time RIC (Non-RT RIC) ) , a service management and orchestration (SMO) system, or any combination thereof.

An RU may also be referred to as a radio head, a smart radio head, a remote radio head (RRH) , a remote radio unit (RRU) , or a transmission reception point (TRP) . One or more components of the network entities 102 in a disaggregated RAN architecture may be co-located, or one or more components of the network entities 102 may be located in distributed locations (e.g., separate physical locations) . In some implementations, one or more network entities 102 of a disaggregated RAN architecture may be implemented as virtual units (e.g., a virtual CU (VCU) , a virtual DU (VDU) , a virtual RU (VRU) ) .

Split of functionality between a CU, a DU, and an RU may be flexible and may support different functionalities depending upon which functions (e.g., network layer functions, protocol layer functions, baseband functions, radio frequency functions, and any combinations thereof) are performed at a CU, a DU, or an RU. For example, a functional split of a protocol stack may be employed between a CU and a DU such that the CU may support one or more layers of the protocol stack and the DU may support one or more different layers of the protocol stack. In some implementations, the CU may host upper protocol layer (e.g., a layer 3 (L3) , a layer 2 (L2) ) functionality and signaling (e.g., radio resource control (RRC) , service data adaption protocol (SDAP) , packet data convergence protocol (PDCP) ) . The CU may be connected to one or more DUs or RUs, and the one or more DUs or RUs may host lower protocol layers, such as a layer 1 (L1) (e.g., physical (PHY) layer) or an L2 (e.g., radio link control (RLC) layer, medium access control (MAC) layer) functionality and signaling, and may each be at least partially controlled by the CU 160.

Additionally, or alternatively, a functional split of the protocol stack may be employed between a DU and an RU such that the DU may support one or more layers of the protocol stack and the RU may support one or more different layers of the protocol stack. The DU may support one or multiple different cells (e.g., via one or more RUs) . In some implementations, a functional split between a CU and a DU, or between a DU and an RU may be within a protocol layer (e.g., some functions for a protocol layer may be performed by one of a CU, a DU, or an RU, while other functions of the protocol layer are performed by a different one of the CU, the DU, or the RU) .

A CU may be functionally split further into CU control plane (CU-CP) and CU user plane (CU-UP) functions. A CU may be connected to one or more DUs via a midhaul communication link (e.g., F1, F1-c, F1-u) , and a DU may be connected to one or more RUs via a fronthaul communication link (e.g., open fronthaul (FH) interface) . In some implementations, a midhaul communication link or a fronthaul communication link may be implemented in accordance with an interface (e.g., a channel) between layers of a protocol stack supported by respective network entities 102 that are in communication via such communication links.

The core network 106 may support user authentication, access authorization, tracking, connectivity, and other access, routing, or mobility functions. The core network 106 may be an evolved packet core (EPC) , or a 5G core (5GC) , which may include a control plane entity that manages access and mobility (e.g., a mobility management entity (MME) , an access and mobility management functions (AMF) ) and a user plane entity that routes packets or interconnects to external networks (e.g., a serving gateway (S-GW) , a packet data network (PDN) gateway (P-GW) , or a user plane function (UPF) ) . In some implementations, the control plane entity may manage non-access stratum (NAS) functions, such as mobility, authentication, and bearer management (e.g., data bearers, signal bearers, etc. ) for the one or more UEs 104 served by the one or more network entities 102 associated with the core network 106.

The core network 106 may communicate with the packet data network 108 over one or more backhaul links 116 (e.g., via an S1, N2, N2, or another network interface) . The packet data network 108 may include an application server 118. In some implementations, one or more UEs 104 may communicate with the application server 118. A UE 104 may establish a session (e.g., a protocol data unit (PDU) session, or the like) with the core network 106 via a network entity 102. The core network 106 may route traffic (e.g., control information, data, and the like) between the UE 104 and the application server 118 using the established session (e.g., the established PDU session) . The PDU session may be an example of a logical connection between the UE 104 and the core network 106 (e.g., one or more network functions of the core network 106) .

In the wireless communications system 100, the network entities 102 and the UEs 104 may use resources of the wireless communications system 100 (e.g., time resources (e.g., symbols, slots, subframes, frames, or the like) or frequency resources (e.g., subcarriers, carriers) ) to perform various operations (e.g., wireless communications) . In some implementations, the network entities 102 and the UEs 104 may support different resource structures. For example, the network entities 102 and the UEs 104 may support different frame structures. In some implementations, such as in 4G, the network entities 102 and the UEs 104 may support a single frame structure. In some other implementations, such as in 5G and among other suitable radio access technologies, the network entities 102 and the UEs 104 may support various frame structures (i.e., multiple frame structures) . The network entities 102 and the UEs 104 may support various frame structures based on one or more numerologies.

One or more numerologies may be supported in the wireless communications system 100, and a numerology may include a subcarrier spacing and a cyclic prefix. A first numerology (e.g., μ=0) may be associated with a first subcarrier spacing (e.g., 15 kHz) and a normal cyclic prefix. In some implementations, the first numerology (e.g., μ=0) associated with the first subcarrier spacing (e.g., 15 kHz) may utilize one slot per subframe. A second numerology (e.g., μ=1) may be associated with a second subcarrier spacing (e.g., 30 kHz) and a normal cyclic prefix. A third numerology (e.g., μ=2) may be associated with a third subcarrier spacing (e.g., 60 kHz) and a normal cyclic prefix or an extended cyclic prefix. A fourth numerology (e.g., μ=3) may be associated with a fourth subcarrier spacing (e.g., 120 kHz) and a normal cyclic prefix. A fifth numerology (e.g., μ=4) may be associated with a fifth subcarrier spacing (e.g., 240 kHz) and a normal cyclic prefix.

A time interval of a resource (e.g., a communication resource) may be organized according to frames (also referred to as radio frames) . Each frame may have a duration, for example, a 10 millisecond (ms) duration. In some implementations, each frame may include multiple subframes. For example, each frame may include 10 subframes, and each subframe may have a duration, for example, a 1 ms duration. In some implementations, each frame may have the same duration. In some implementations, each subframe of a frame may have the same duration.

Additionally or alternatively, a time interval of a resource (e.g., a communication resource) may be organized according to slots. For example, a subframe may include a number (e.g., quantity) of slots. The number of slots in each subframe may also depend on the one or more numerologies supported in the wireless communications system 100. For instance, the first, second, third, fourth, and fifth numerologies (i.e., μ=0, μ=1, μ=2, μ=3, μ=4) associated with respective subcarrier spacings of 15 kHz, 30 kHz, 60 kHz, 120 kHz, and 240 kHz may utilize a single slot per subframe, two slots per subframe, four slots per subframe, eight slots per subframe, and 16 slots per subframe, respectively. Each slot may include a number (e.g., quantity) of symbols (e.g., OFDM symbols) . In some implementations, the number (e.g., quantity) of slots for a subframe may depend on a numerology. For a normal cyclic prefix, a slot may include 14 symbols. For an extended cyclic prefix (e.g., applicable for 60 kHz subcarrier spacing) , a slot may include 12 symbols. The relationship between the number of symbols per slot, the number of slots per subframe, and the number of slots per frame for a normal cyclic prefix and an extended cyclic prefix may depend on a numerology. It should be understood that reference to a first numerology (e.g., μ=0) associated with a first subcarrier spacing (e.g., 15 kHz) may be used interchangeably between subframes and slots.

In the wireless communications system 100, an electromagnetic (EM) spectrum may be split, based on frequency or wavelength, into various classes, frequency bands, frequency channels, etc. By way of example, the wireless communications system 100 may support one or multiple operating frequency bands, such as frequency range designations FR1 (410 MHz –7.125 GHz) , FR2 (24.25 GHz –52.6 GHz) , FR3 (7.125 GHz –24.25 GHz) , FR4 (52.6 GHz –114.25 GHz) , FR4a or FR4-1 (52.6 GHz –71 GHz) , and FR5 (114.25 GHz –300 GHz) . In some implementations, the network entities 102 and the UEs 104 may perform wireless communications over one or more of the operating frequency bands. In some implementations, FR1 may be used by the network entities 102 and the UEs 104, among other equipment or devices for cellular communications traffic (e.g., control information, data) . In some implementations, FR2 may be used by the network entities 102 and the UEs 104, among other equipment or devices for short-range, high data rate capabilities.

FR1 may be associated with one or multiple numerologies (e.g., at least three numerologies) . For example, FR1 may be associated with a first numerology (e.g., μ=0) , which includes 15 kHz subcarrier spacing; a second numerology (e.g., μ=1) , which includes 30 kHz subcarrier spacing; and a third numerology (e.g., μ=2) , which includes 60 kHz subcarrier spacing. FR2 may be associated with one or multiple numerologies (e.g., at least 2 numerologies) . For example, FR2 may be associated with a third numerology (e.g., μ=2) , which includes 60 kHz subcarrier spacing; and a fourth numerology (e.g., μ=3) , which includes 120 kHz subcarrier spacing.

Fig. 2 illustrates a flowchart of a method 200 that supports buffer status report in accordance with aspects of the present disclosure. The operations of the method 200 may be implemented by a device or its components as described herein. For example, the operations of the method 200 may be performed by a UE 104 as described herein. In some implementations, the device may execute a set of instructions to control the function elements of the device to perform the described functions. Additionally, or alternatively, the device may perform aspects of the described functions using special-purpose hardware.

At 210, the UE 104 determines whether uplink (UL) data of at least one logical channel (e.g., which belongs to at least one LCG) becomes unavailable (e.g., becomes zero) to a MAC entity of the UE 104. For example, the UE 104 determines whether UL data of all the at least one logical channel which belongs to all the at least one LCG becomes unavailable to a MAC entity of the UE 104. For example, the UE 104 determines whether uplink (UL) data of all at least one logical channel which belongs to the at least one LCG becomes unavailable to a MAC entity of the UE 104.

If the UE 104 determines that the UL data becomes unavailable (e.g., becomes zero) , the UE 104 triggers, at 220, at least one first BSR for the at least one logical channel or for the at least one LCG. Each of the at least one first BSR indicates a first buffer size of one of the at least one LCG is equal to zero.

If the UE 104 determines that the UL data becomes unavailable (e.g., becomes zero) , the UE 104 triggers, at 220, at least one first BSR for the at least one logical channel or for the at least one LCG and detects at least one end of at least one data burst of the at least one logical channel. Each of the at least one first BSR indicates a first buffer size of one of the at least one LCG is equal to zero.

In some implementations, the UE 104 may determine that the UL data of at least one logical channel (e.g., which belongs to at least one LCG) becomes unavailable (e.g., becomes zero) to the MAC entity of the UE 104 by detecting at least one end of at least one data burst of the at least one logical channel. If the UE 104 detects at least one end of at least one data burst of the at least one logical channel, it means that the data available for transmission for the at least one LCG either has been transmitted or accommodated in a UL grant. For example, the UE 104 determines whether UL data of all the at least one logical channel which belongs to all the at least one LCG becomes unavailable to a MAC entity of the UE 104 by detecting at least one end of at least one data burst of all the at least one logical channel. For example, the UE 104 determines whether UL data of all at least one logical channel which belongs to the at least one LCG becomes unavailable to a MAC entity of the UE 104 by detecting at least one end of at least one data burst of all the at least one logical channel.

If the UE 104 determines that the UL data of at least one logical channel which belongs to at least one LCG becomes unavailable (e.g., becomes zero) to the MAC entity of the UE 104 and/or detecting at least one end of at least one data burst of the at least one logical channel, the UE 104 may transmit the at least one first BSR to the base station 102. Each of the at least one first BSR indicates the first buffer size of one of the at least one LCG is equal to zero. For example, upon determining the UL data of all the at least one logical channel which belongs to at least one LCG or all the at least one LCG becomes unavailable to the MAC entity of the UE 104 or detecting at least one end of at least one data burst of the at least one logical channel or all the at least one logical channel, the UE 104 may transmit the at least one first BSR to the base station 102.

If the UE 104 triggers a BSR for at least one logical channel which belongs to at least one LCG, the UL data of which becomes unavailable (e.g., becomes zero) to the MAC entity of the UE 104 and/or detects at least one end of at least one data burst of the at least one logical channel, the UE 104 may transmit the at least one first BSR to the base station 102. Each of the at least one first BSR indicates the first buffer size of one of the at least one LCG is equal to zero.

If the base station 102 receives the at least one first BSR, the base station 102 may determine an end transmission of data burst for at least one logical channel to instruct the UE 104 to enter a discontinuous reception (DRX) inactive mode for power saving of the UE 104.

In some implementations, the UE 104 may receive, from the base station 102, a configuration for the least one logical channel. The UE 104 may determine, based on the configuration for the least one logical channel, whether the UL data of the at least one logical channel which belongs to at least one LCG becomes unavailable (e.g., becomes zero) to the MAC entity of the UE 104.

For example, a LCG #1 comprises a logical channel #1 and a logical channel #2. The UE 104 receives, from the base station 102, a first configuration for the logical channel #1. The first configuration may indicate that if UL data of the logical channel #1 becomes unavailable (e.g., becomes zero) to the MAC entity of the UE 104, the UE 104 may trigger a BSR for the logical channel #1 or for the LCG #1. The BSR indicates a buffer size of the LCG #1 is equal to zero.

If the UE 104 determines that that the UL data of the logical channel #1 becomes unavailable to the MAC entity of the UE 104 and that the logical channel #2 has no data available for transmission, the UE 104 may determine that the buffer size of the LCG #1 becomes zero. Thus, the UE 104 may trigger, based on the first configuration, a BSR for the logical channel #1 or for the LCG #1. The BSR indicates the buffer size of the LCG #1 is equal to zero.

In some implementations, the UE 104 may receive, from the base station 102, a second configuration for the least one LCG. The UE 104 may determine, based on the second configuration, whether the UL data of the at least one logical channel which belongs to at least one LCG becomes unavailable to the MAC entity of the UE 104 or the BSR of the at least one logical channel which belongs to at least one LCG becomes or equals to zero.

For example, a LCG #1 comprises a logical channel #1 and a logical channel #2. The UE 104 receives, from the base station 102, a second configuration for the LCG #1. The configuration for the logical channel #1 may indicate that if a buffer size of the LCG #1 becomes zero, the UE 104 may trigger a BSR for the LCG #1. The BSR indicates the buffer size of the LCG #1 is equal to zero.

If the UE 104 determines that that the UL data of the logical channel #1 becomes unavailable to the MAC entity of the UE 104 and that the logical channel #2 has no data available for transmission, the UE 104 may determine that the buffer size of the LCG #1 becomes zero. Thus, the UE 104 may trigger, based on the second configuration, a BSR for the LCG #1. The BSR indicates the buffer size of the LCG #1 is equal to zero.

In some implementations, each of the at least one first BSR may comprise a dedicated BSR. For example, each of the at least one first BSR may be a new BSR which is separate from a legacy BSR. The legacy BSR may comprise a regular BSR or periodicity BSR or a padding BSR.

In some implementations, the new BSR may be identified by a MAC subheader with LCID as specified in Table 6.2.1-2 in TS 38.321. A specific LCID from the reserved index is assigned for the new BSR. Table 1 provides an example of a value of a LCID for the new BSR.

Table 1

Alternatively, in some implementations, each of the at least one first BSR may comprise a legacy BSR. The legacy BSR may comprise a regular BSR or a padding BSR.

For example, if the UE 104 triggers a regular BSR, a BSR shall be triggered if any of the following events occur:

‐ UL data, for a logical channel or all logical channels which belongs to an or all LCG (s) and optionally which is configured to trigger BSR if the volume of data with available for transmission becomes zero, becomes unavailable to the MAC entity;

in which case the BSR is referred below to as “Regular BSR” ;

‐ retxBSR-Timer expires, for a logical channel or all logical channels which belongs to an or all LCG (s) and optionally which is configured to trigger BSR if the volume of data with available for transmission becomes zero, becomes unavailable to the MAC entity, in which case the BSR is referred below to as “Regular BSR” .

‐ UE detects end of data burst, for a logical channel or all logical channels which belongs to an or all LCG (s) ;

in which case the BSR is referred below to as “Regular BSR” ;

‐ retxBSR-Timer expires, and UE detects end of data burst, for a logical channel or all logical channels which belongs to an or all LCG (s) and optionally which is configured to trigger BSR if the volume of data with available for transmission becomes zero, in which case the BSR is referred below to as “Regular BSR” .

In some implementations, if the UE 104 determines that only one first LCG has data available for transmission, the UE 104 may transmit a second BSR in a Short BSR format for the first LCG to the base station 102. The second BSR comprises a second buffer size which is equal to non-zero. For example, the first LCG may be comprised in the at least one LCG as described above. Alternatively, the first LCG may be separate from the at least one LCG as described above.

In some implementations, if the UE 104 determines that none of the at least one LCG has data available for transmission, the UE 104 may transmit a second BSR in a Short BSR format for one of the at least one LCG to the base station 102. The second BSR comprises a second buffer size which is equal to zero.

In some implementations, the second BSR may comprise one of the following: a regular BSR, a periodic BSR, or a padding BSR.

For example, if the UE 104 104 triggers a regular or periodic BSR, if the UE 104 triggers a padding BSR, if no LCGs has data available for transmission, the UE 104 still reports the regular BSR to the base station 104, to indicate buffer size equal to 0 for the UE 104. The LCG ID in the BSR could be any of LCG IDs or a special value different form LCGs allocated to the UE 104. For example, the regular BSR content determination and report may be as following underlined text.

For regular and periodic BSR, the MAC entity shall:

1> if more than one LCG has data available for transmission when the MAC PDU containing the BSR is to be built:

2> report Long BSR for all LCGs which have data available for transmission.

1> else if only one LCG has data available for transmission when the BSR is to be built:

2> report Short BSR of the LCG with data available for transmission.

1> else (if no LCG has data available for transmission when the BSR is to be built) :

2> report Short BSR.

For example, if the UE 104 triggers padding BSR, if no LCGs has data available for transmission, the UE 104 still reports the padding BSR, to indicate buffer size equal to 0 for the UE 104. The LCG ID in a Short Truncated BSR format or Short BSR format could be any of LCG IDs or an LCGID of the at least one LCG or a special value different form LCGs allocated to the UE 104. For example, the padding BSR content determination and report may be as following underlined text.

For a padding BSR, the MAC entity shall:

1> if the number of padding bits is equal to or larger than the size of the Short BSR plus its subheader but smaller than the size of the Long BSR plus its subheader:

2> if more than one LCG has data available for transmission when the BSR is to be built:

3> if the number of padding bits is equal to the size of the Short BSR plus its subheader:

4> report Short Truncated BSR of the LCG with the highest priority logical channel with data available for transmission.

3> else:

4> report Long Truncated BSR of the LCG (s) with the logical channels having data available for transmission following a decreasing order of the highest priority logical channel (with or without data available for transmission) in each of these LCG (s) , and in case of equal priority, in increasing order of LCGID.

2> else if only one LCG has data available for transmission when the BSR is to be built:

3> report Short BSR of the LCG with data available for transmission.

2> else (if no LCG has data available for transmission when the BSR is to be built)

3> report short BSR.

1> else if the number of padding bits is equal to or larger than the size of the Long BSR plus its subheader:

2> report Long BSR for all LCGs which have data available for transmission.

In some implementations, a format of the at least one first BSR may be a dedicated BSR format (for example, a new BSR format) or a legacy BSR format. The legacy BSR may comprise a Long BSR format, a Long Truncated BSR format, a Short BSR format.

In some implementations, the dedicated BSR format may not comprise MAC CE content, which means only a MAC subheader with a specific LCID is included.

In some implementations, BSR trigger enhancement may be performed. In the BSR trigger enhancement, if the UE 104 determines that the UL data of at least one logical channel or at least one LCG becomes unavailable (e.g., becomes zero) to the MAC entity of the UE 104 and determines that no triggered third BSR indicates the first buffer size is equal to zero, the UE 104 may trigger the at least one first BSR for the at least one logical channel or for the at least one LCG. The at least one logical channel may be in the at least one LCG. Each of the at least one first BSR indicates the first buffer size of one of the at least one LCG is equal to zero.

In some implementations, the UL data of at least one logical channel becomes unavailable to the MAC entity of the UE means the volume of the data available for transmission of the at least one logical channel after a MAC PDU is built becomes 0 or equals to 0. The UL data of at least one LCG becomes unavailable to the MAC entity of the UE means the volume of the data available for transmion of the LCG becomes 0 or equals to 0.

In some implementations, the triggered third BSR may comprise a padding BSR or a regular BSR or periodic BSR.

For example, a UE has an LCG#1, an LCG#2 and an LCG#3. Buffer sizes for LCG#1 and LCG#3 are greater than zero, and a buffer size of LCG#2 is equal to zero. A priority of LCG#1 is higher than a priority of LCG#2, and a priority of LCG#2 is equal to a priority of LCG#3. The UE 104 triggers a padding BSR and the padding BSR is in a short truncated BSR format. The triggered padding BSR in a short truncated format only includes a buffer size of LCG#1 which is greater than zero. In this case, upon receiving the padding BSR, the base station 120 cannot determine whether the buffer sizes for LCG#2 and LCG#3 are equal to zero or not. Thus, no triggered BSR indicates the buffer size of LCG#2 is equal to zero. If the UE 104 determines that the UL data of at least one logical channel belonging to LCG#2 becomes unavailable to the MAC entity of the UE 104, the UE 104 may trigger a BSR for the at least one logical channel or for LCG#2. The BSR indicates the buffer size of LCG#2 is equal to zero.

In some implementations, the UE 104 may receive a configuration of the BSR trigger enhancement from the base station 102. In turn, the UE 104 may trigger, based on the configuration, at least one first BSR for the at least one logical channel or for the at least one LCG.

In some implementations, BSR cancel enhancement may be performed. In the BSR cancel enhancement, the UE 104 has determined that the UL data of at least one logical channel or at least one LCG becomes unavailable and has triggered at least one first BSR for the at least one logical channel or for the at least one LCG. The UE 104 does not cancel the triggered at least one first BSR if a UL grant can accommodate all pending data available for transmission but is not sufficient to additionally accommodate a MAC CE and a subheader of the MAC CE. The MAC CE comprises the triggered at least one first BSR.

In some implementations, BSR cancel enhancement may be performed. In the BSR cancel enhancement, the UE 104 has determined that the UL data of all the at least one logical channel or all the at least one LCG becomes unavailable and has triggered at least one first BSR for all the at least one logical channel or for all the at least one LCGs. All the at least one logical channel may be included in the at least one LCG. The UE 104 does not cancel the triggered at least one first BSR if a UL grant can accommodate all pending data available for transmission but is not sufficient to additionally accommodate a MAC CE and a subheader of the MAC CE. The MAC CE comprises the triggered at least one first BSR.

For example, all triggered BSRs may be cancelled when the UL grant (s) can accommodate all pending data available for transmission but is not sufficient to additionally accommodate the BSR MAC CE plus its subheader if none of all the at least one LCG or none of the at least one logical channel are needed to report the buffer size which is equal to 0 or becomes 0.

In some implementations, the UE 104 may receive a configuration of the BSR cancel enhancement from the base station 102. In turn, the UE 104 may not cancel, based on the configuration, the triggered at least one first BSR for the at least one logical channel or for the at least one LCG.

In some implementations, if the at least one first BSR comprises at least one dedicated BSR (for example, new BSR) , The priority between the dedicated BSR and legacy BSR should be specified.

In some implementations, a first priority of the at least one dedicated BSR is above a second priority of a regular BSR or a periodic BSR. In other words, the first priority of the at least one dedicated BSR is above the second priority of a BSR with exception of BSR included for padding.

For example, logical channels shall be prioritized in accordance with the following order (highest priority listed first) :

- C-RNTI MAC CE or data from UL-CCCH;

- Configured Grant Confirmation MAC CE or MAC CEs for BFR or Multiple Entry Configured Grant Confirmation MAC CE;

- Sidelink Configured Grant Confirmation MAC CE;

- LBT failure MAC CE;

- MAC CE for Timing Advance Report;

- MAC CE for SL-BSR prioritized according to clause 5.22.1.6;

- MAC CE for dedicated BSR (for example, new BSR) ;

- MAC CE for BSR, with exception of BSR included for padding;

- Single Entry PHR MAC CE or Multiple Entry PHR MAC CE;

- MAC CE for the number of Desired Guard Symbols;

- MAC CE for Pre-emptive BSR;

- MAC CE for SL-BSR, with exception of SL-BSR prioritized according to clause 5.22.1.6 and SL-BSR included for padding;

- data from any Logical Channel, except data from UL-CCCH;

- MAC CE for Recommended bit rate query;

- MAC CE for BSR included for padding;

- MAC CE for SL-BSR included for padding.

In some implementations, a first priority of the at least one dedicated BSR is equal to a second priority of a regular BSR or a periodic BSR. In other words, the first priority of the at least one dedicated BSR is equal to the second priority of a BSR with exception of BSR included for padding. It is up to UE implementation to select which to report from the two BSRs, i.e., that prioritization among the two MAC CEs is up to UE implementation.

- C-RNTI MAC CE or data from UL-CCCH;

- Sidelink Configured Grant Confirmation MAC CE;

- LBT failure MAC CE;

- MAC CE for Timing Advance Report;

- MAC CE for SL-BSR prioritized according to clause 5.22.1.6;

- MAC CE for BSR, with exception of BSR included for padding, or MAC CE for dedicated BSR (for example, new BSR) ;

- Single Entry PHR MAC CE or Multiple Entry PHR MAC CE;

- MAC CE for the number of Desired Guard Symbols;

- MAC CE for Pre-emptive BSR;

- data from any Logical Channel, except data from UL-CCCH;

- MAC CE for Recommended bit rate query;

- MAC CE for BSR included for padding;

- MAC CE for SL-BSR included for padding.

In some implementations, a first priority of the at least one dedicated BSR is below a second priority of a regular BSR or a periodic BSR. In other words, the first priority of the at least one dedicated BSR is below the second priority of a BSR with exception of BSR included for padding.

In some implementations, a first priority of the at least one dedicated BSR is above a priority of data from any logical channel, except data from UL-CCCH;

- C-RNTI MAC CE or data from UL-CCCH;

- Sidelink Configured Grant Confirmation MAC CE;

- LBT failure MAC CE;

- MAC CE for Timing Advance Report;

- MAC CE for SL-BSR prioritized according to clause 5.22.1.6;

- MAC CE for BSR, with exception of BSR included for padding;

- MAC CE for dedicated BSR (for example, new BSR) ;

- Single Entry PHR MAC CE or Multiple Entry PHR MAC CE;

- MAC CE for the number of Desired Guard Symbols;

- MAC CE for Pre-emptive BSR;

- data from any Logical Channel, except data from UL-CCCH;

- MAC CE for Recommended bit rate query;

- MAC CE for BSR included for padding;

- MAC CE for SL-BSR included for padding.

In some implementations, a first priority of the at least one dedicated BSR is below a priority of data from any Logical Channel, except data from UL-CCCH;

In some implementations, the first priority of the at least one dedicated BSR is above a second priority of a padding BSR.

- C-RNTI MAC CE or data from UL-CCCH;

- Sidelink Configured Grant Confirmation MAC CE;

- LBT failure MAC CE;

- MAC CE for Timing Advance Report;

- MAC CE for SL-BSR prioritized according to clause 5.22.1.6;

- MAC CE for BSR, with exception of BSR included for padding;

- Single Entry PHR MAC CE or Multiple Entry PHR MAC CE;

- MAC CE for the number of Desired Guard Symbols;

- MAC CE for Pre-emptive BSR;

- data from any Logical Channel, except data from UL-CCCH;

- MAC CE for Recommended bit rate query;

- MAC CE for dedicated BSR (for example, new BSR) ;

- MAC CE for BSR included for padding;

- MAC CE for SL-BSR included for padding.

In some implementations, the first priority of the at least one dedicated BSR is equal to a second priority of a padding BSR. It is up to UE implementation to select which to report from the two BSRs, i.e., that prioritization among the two MAC CEs is up to UE implementation.

- C-RNTI MAC CE or data from UL-CCCH;

- Sidelink Configured Grant Confirmation MAC CE;

- LBT failure MAC CE;

- MAC CE for Timing Advance Report;

- MAC CE for SL-BSR prioritized according to clause 5.22.1.6;

- MAC CE for BSR, with exception of BSR included for padding;

- Single Entry PHR MAC CE or Multiple Entry PHR MAC CE;

- MAC CE for the number of Desired Guard Symbols;

- MAC CE for Pre-emptive BSR;

- data from any Logical Channel, except data from UL-CCCH;

- MAC CE for Recommended bit rate query;

- MAC CE for BSR included for padding or MAC CE for dedicated BSR (for example, new BSR) ;

- MAC CE for SL-BSR included for padding.

In some implementations, the first priority of the at least one dedicated BSR is below a second priority of a padding BSR.

- C-RNTI MAC CE or data from UL-CCCH;

- Sidelink Configured Grant Confirmation MAC CE;

- LBT failure MAC CE;

- MAC CE for Timing Advance Report;

- MAC CE for SL-BSR prioritized according to clause 5.22.1.6;

- MAC CE for BSR, with exception of BSR included for padding;

- Single Entry PHR MAC CE or Multiple Entry PHR MAC CE;

- MAC CE for the number of Desired Guard Symbols;

- MAC CE for Pre-emptive BSR;

- data from any Logical Channel, except data from UL-CCCH;

- MAC CE for Recommended bit rate query;

- MAC CE for BSR included for padding;

- MAC CE for dedicated BSR (for example, new BSR) ;

- MAC CE for SL-BSR included for padding.

It shall be noted that prioritization among Configured Grant Confirmation MAC CE, Multiple Entry Configured Grant Confirmation MAC CE, and MAC CEs for BFR is up to UE implementation.

In some implementations, the BSR may be reported per logical channel. If the UE 104 determines that the UL data of at least one logical channel or all the at least one logical channel becomes unavailable to the MAC entity of the UE 104, the UE 104 triggers, at 220, at least one first BSR for the at least one logical channel. Each of the at least one first BSR indicates a first buffer size of one of the at least one logical channel is equal to zero.

In some implementations, the UE 104 may determine that the UL data of at least one logical channel or all the at least one logical channel (e.g., which belongs to at least one LCG or all the at least one LCG) becomes unavailable to the MAC entity of the UE 104 by detecting at least one end of at least one data burst of the at least one logical channel or all the at least one logical channel. If the UE 104 detects at least one end of at least one data burst of the at least one logical channel or all the at least one logical channel, it means that the data available for transmission for the at least one logical channel either has been transmitted or accommodated in a UL grant.

Upon determining the UL data of at least one logical channel becomes unavailable to the MAC entity of the UE 104 or detecting at least one end of at least one data burst of the at least one logical channel or all the at least one logical channel, the UE 104 may transmit the at least one first BSR to the base station 102. Each of the at least one first BSR indicates the first buffer size of one of the at least one logical channel is equal to zero. In some implementations, a delay report including delay information may be deprioritized due to the intra-UE prioritization. In such implementations, it needs to consider how to handle the delay report to assure a base station can determine the right reference time of the delay information by using autonomous transmission grant. This will be described with reference to Fig. 3.

Fig. 3 illustrates an example of delay information generation and reporting in accordance with some implementations of the present disclosure. As shown in Fig. 3, a UE may trigger a report of delay information at T1 and generate a MAC CE including the delay information at T2. The delay information indicates remaining time of a packet data convergence protocol (PDCP) discard timer. The UE may determine a reference time of the delay information is T3. When a base station receives this MAC PDU, the base station determines the reference time of delay information is T3. However, if a physical layer of the UE drops configured grant (CG) at T3 due to the higher priority PHY-index UL transmission, the UE may perform at least one autonomous transmission of the MAC PDU using subsequent CG resource with the same HARQ process, which PDU is retrieved from the same HARQ process of previous de-prioritized grant. The autonomous transmission grant can be deprioritized multiple times. When the base station receives this MAC PDU, the base station cannot determine the reference time of delay information is T3. Thus, the base station cannot accurately determine the remaining time of the PDCP discard timer.

In view of the above, the present disclosure provides a solution that supports delay information report. In this solution, a UE determines a first CG for an autonomous transmission of delay information. The delay information indicating remaining time of a PDCP discard timer. The UE determines a first time point of the autonomous transmission as a first reference time. In turn, the UE determines the delay information based on a value of the PDCP discard timer and the first reference time.

Fig. 4 illustrates a flowchart of a method 400 that supports determination of first delay information in accordance with aspects of the present disclosure. The operations of the method 400 may be implemented by a device or its components as described herein. For example, the operations of the method 400 may be performed by a UE 104 as described herein. In some implementations, the device may execute a set of instructions to control the function elements of the device to perform the described functions. Additionally, or alternatively, the device may perform aspects of the described functions using special-purpose hardware.

At 410, the UE 104 determines a first CG for an autonomous transmission of first delay information. The first delay information indicates first remaining time of a PDCP discard timer.

In some implementations, the delay information may correspond to a data volume information. For example, the delay information may indicate the remaining time of a PDCP discard timer for at least one PDCP service data unit (SDU) , at least one PDU set, or at least one data burst of a LCG or a logical channel with data available for transmission. The remaining time of a packet data convergence protocol (PDCP) discard timer may be the shortest value of available data for transmission of a LCG or a logical channel. In this case, at most one delay information is corresponding to a logical channel or an LCG. In another case, a logical channel or an LCG may have more than one delay information, which indicates the remaining time of a PDCP discard timer for different PDCP service data unit (SDU) (s) , different PDU set (s) , or different data burst (s) of a LCG or a logical channel with data available for transmission.

At 420, the UE 104 determines a first time point of the autonomous transmission as a first reference time.

At 430, the UE 104 determines the first delay information based on a value of the PDCP discard timer and the first reference time.

With the method 400, upon receiving the first delay information, the base station 102 can accurately determine the remaining time of the PDCP discard timer.

In some implementations, the autonomous transmission of first delay information may be immediately subsequent to an initial transmission of second delay information. This will be described with reference to Figs. 5, 6 and 7.

Fig. 5 illustrates an example of delay information generation and reporting in accordance with some implementations of the present disclosure. As shown in Fig. 5, at T1, the UE 104 trigger a report of the second delay information. In turn, the UE 104 may determine the second delay information by performing a method 600 which will be described below.

Fig. 6 illustrates a flowchart of a method 600 that supports determination of second delay information in accordance with aspects of the present disclosure. The operations of the method 600 may be implemented by a device or its components as described herein. For example, the operations of the method 600 may be performed by a UE 104 as described herein. In some implementations, the device may execute a set of instructions to control the function elements of the device to perform the described functions. Additionally, or alternatively, the device may perform aspects of the described functions using special-purpose hardware.

At 610, the UE 104 determines a second CG (such as CG#2 in Fig. 5) for an initial transmission of second delay information. The second delay information indicates second remaining time of the PDCP discard timer.

At 620, the UE 104 determines a second time point of the initial transmission as a second reference time. For example, in the example of in Fig. 5, the second time point of the initial transmission is T3. Thus, the UE 104 determines T3 as the second reference time.

At 630, the UE 104 determines the second delay information based on the value of the PDCP discard timer and the second reference time. For example, the UE 104 may generate the second delay information based on the value of the PDCP discard timer and the second reference time.

In some implementations, in order to report the second delay information to the base station 102, the UE 104 may perform a method 700 which will be described below.

Fig. 7 illustrates a flowchart of a method 700 that supports report of second delay information in accordance with aspects of the present disclosure. The operations of the method 700 may be implemented by a device or its components as described herein. For example, the operations of the method 700 may be performed by a UE 104 as described herein. In some implementations, the device may execute a set of instructions to control the function elements of the device to perform the described functions. Additionally, or alternatively, the device may perform aspects of the described functions using special-purpose hardware.

At 710, the UE 104 generates a MAC PDU including the second delay information. For example, the UE 104 may generate the MAC PDU including the second delay information at T2 as shown in Fig. 5.

At 720, the UE 104 delivers the MAC PDU and the second CG (such as CG#2 in Fig. 5) to an identified hybrid automatic repeat request (HARQ) process.

At 730, the UE 104 instructs the HARQ process to initiate a first new transmission of the MAC PDU.

In some implementations, the second CG (such as CG#2 in Fig. 5) may be deprioritized. In other words, the second CG may be not prioritized.

For example, for the MAC entity configured with lch-basedPrioritization, if the corresponding PUSCH transmission of a CG is cancelled by Cancellation Indication Radio Network Temporary Identity (CI-RNTI) or cancelled by a high PHY-priority PUCCH or PUSCH transmission, this CG is considered as a deprioritized CG.

In such implementations, if the second CG (such as CG#2 in Fig. 5) is deprioritized, the UE 104 cancels the first new transmission of the MAC PDU including the second delay information at 740 in Fig. 7. For example, the first new transmission at T3 in Fig. 5 is cancelled. Then, the physical layer of the UE 104 may notify the cancelation transmission of the deprioritized CG to the MAC layer of the UE 104.

In some implementations, if a triggered report for the second delay information has not been cancelled, the UE 104 may determine the first delay information by performing the method 400 as described above.

For example, in the example of Fig. 5, the UE 104 determines the first CG (such as CG#1 in Fig. 5) for the autonomous transmission of the first delay information. The first delay information indicates the first remaining time of the PDCP discard timer.

In addition, the UE 104 determines the first time point of the autonomous transmission as the first reference time. For example, in the example of in Fig. 5, the first time point of the initial transmission is T4. Thus, the UE 104 determines T4 as the first reference time.

In turn, the UE 104 determines the first delay information based on the value of the PDCP discard timer and the first reference time (such as T4) .

In some implementations, the UE 104 may trigger a second report for the first delay information for autonomous transmission over the first CG (such as CG#1 in Fig. 5) if a triggered report for the second delay information has been cancelled.

In some implementations, in order to report the first delay information to the base station 102, the UE 104 may perform a method 800 which will be described below.

Fig. 8 illustrates a flowchart of a method 800 that supports report of first delay information in accordance with aspects of the present disclosure. The operations of the method 800 may be implemented by a device or its components as described herein. For example, the operations of the method 800 may be performed by a UE 104 as described herein. In some implementations, the device may execute a set of instructions to control the function elements of the device to perform the described functions. Additionally, or alternatively, the device may perform aspects of the described functions using special-purpose hardware.

At 810, if the UE 104 determines that none of at least one physical uplink shared channel (PUSCH) transmission of the MAC PDU has been completely performed, the UE 104 obtains the MAC PDU from the identified HARQ process of the first CG (such as CG#1 in Fig. 5) . Alternatively, if the UE 104 determines that the second CG (such as CG#2 in Fig. 5) previous to the first CG (such as CG#1 in Fig. 5) was deprioritized, the UE 104 obtains the MAC PDU from the identified HARQ process of the first CG (such as CG#1 in Fig. 5) .

At 820, the UE 104 updates the MAC PDU with the first delay information.

For example, if a configured grant corresponding to an HARQ process is configured with autonomous transmission (Tx) , and the previous configured grant, in the BWP, for this HARQ process was deprioritized; and if the delay information is already included in a MAC PDU for transmission on configured grant by this HARQ process, but not yet transmitted by lower layers, it is up to UE implementation how to handle the delay information content (e.g., updating the delay information based on the reference time from the point of the autonomous transmission CG) .

For another example, if a HARQ process is configured with cg-RetransmissionTimer and if the delay information is already included in a MAC PDU for transmission on configured grant by this HARQ process, but not yet transmitted by lower layers, it is up to UE implementation how to handle (e.g., update) the delay information content.

At 830, the UE 104 transmits the MAC PDU to the base station 102.

In some implementations, in order to transmit the MAC PDU to the base station 102, the UE 104 may deliver the MAC PDU and the first CG to the identified HARQ process. In addition, the UE 104 may instruct the HARQ process to initiate a third new transmission of the MAC PDU to the base station 102.

Alternatively, in some implementations, the autonomous transmission of first delay information may be immediately subsequent to a previous autonomous transmission of third delay information. This will be described with reference to Figs. 9, 10 and 11.

Fig. 9 illustrates an example of delay information generation and reporting in accordance with some implementations of the present disclosure. As shown in Fig. 9, at T1, the UE 104 trigger a report of the second delay information. In turn, the UE 104 may determine the second delay information by performing the method 600 as described above.

In some implementations, in order to report the second delay information to the base station 102, the UE 104 may perform the method 700 as described above.

In some implementations, the second CG (such as CG#2 in Fig. 9) may be deprioritized. In other words, the second CG may be not prioritized. In such implementations, the UE 104 cancels the first new transmission of the MAC PDU including the second delay information at 740 in Fig. 7. For example, the first new transmission at T3 in Fig. 9 is cancelled.

In some implementations, if a triggered report for the second delay information has not been cancelled, the UE 104 may determine the third delay information by performing the method 1000 which will be described below.

Fig. 10 illustrates a flowchart of a method 1000 that supports determination of third delay information in accordance with aspects of the present disclosure. The operations of the method 1000 may be implemented by a device or its components as described herein. For example, the operations of the method 1000 may be performed by a UE 104 as described herein. In some implementations, the device may execute a set of instructions to control the function elements of the device to perform the described functions. Additionally, or alternatively, the device may perform aspects of the described functions using special-purpose hardware.

At 1010, the UE 104 determines a third CG for a previous autonomous transmission of third delay information. The third delay information indicates third remaining time of the PDCP discard timer.

At 1020, the UE 104 determines a third time point of the previous autonomous transmission as a third reference time. For example, in the example of in Fig. 9, the third time point of the previous autonomous transmission is T5. Thus, the UE 104 determines T5 as the third reference time.

At 1030, the UE 104 determines the third delay information based on the value of the PDCP discard timer and the third reference time.

In some implementations, in order to report the third delay information to the base station 102, the UE 104 may perform a method 1100 which will be described below.

Fig. 11 illustrates a flowchart of a method 1100 that supports report of third delay information in accordance with aspects of the present disclosure. The operations of the method 1100 may be implemented by a device or its components as described herein. For example, the operations of the method 1100 may be performed by a UE 104 as described herein. In some implementations, the device may execute a set of instructions to control the function elements of the device to perform the described functions. Additionally, or alternatively, the device may perform aspects of the described functions using special-purpose hardware.

At 1110, the UE 104 obtains the MAC PDU from the identified HARQ process of the third CG (such as CG#3 in Fig. 9) if the UE 104 determines that none of at least one PUSCH transmission of the MAC PDU has been completely performed.

At 1120, the UE 104 updates the MAC PDU with the third delay information. For example, the UE 104 updates the MAC PDU generated at T2 in Fig. 9 with the third delay information.

At 1130, the UE 104 delivers the MAC PDU and the third CG to the identified HARQ process.

At 1140, the UE 104 instructs the HARQ process to initiate a second new transmission of the MAC PDU.

In some implementations, the third CG (such as CG#3 in Fig. 9) may be deprioritized. In other words, the third CG may be not prioritized. In such implementations, the UE 104 cancels the second new transmission at 1150 in Fig. 11. For example, the second new transmission at T5 in Fig. 9 is cancelled.

In some implementations, the second CG may be deprioritized by another prioritized UL grant, the UE 104 uses the first new transmission of a MAC PDU including a delay information on another prioritized UL grant, the delay information is determined based on time of the transmission of the prioritized UL grant. In other words, delay information corresponding to the second delay information may be transmitted on the prioritized grant. In such implementations, the UE 104 uses a first new transmission of a MAC PDU including a delay information on another prioritized UL grant even if the MAC PDU including the second delay information has been delivered to the lower layer (e.g., physical layer) for a new transmission and canceled for transmission.

In some implementations, the second CG may be deprioritized by another prioritized UL grant, the UE 104 uses the first new transmission of a MAC PDU including a delay information on another prioritized UL grant, and the delay information is determined based on time of the transmission of the prioritized UL grant. In other words, delay information corresponding to the second delay information may be transmitted on the prioritized grant, and further update the MAC PDU including the second delay information delivered to the lower layer, for example, remove the second delay information from the MAC PDU.

In some implementations, the third CG may be deprioritized by another prioritized UL grant, the UE 104 uses the first new transmission of a MAC PDU including the delay information on another prioritized UL grant. In other words, delay information corresponding to the third delay information may be transmitted on the prioritized grant. In such implementations, the UE 104 uses a first new transmission of a MAC PDU including a delay information on another prioritized UL grant even if the MAC PDU including the third delay information has been delivered to the lower layer (e.g., physical layer) for a new transmission and canceled for transmission.

In some implementations, the second CG may be deprioritized by another prioritized UL grant, the UE 104 uses the first new transmission of a MAC PDU including the delay information on another prioritized UL grant, and the delay information is determined based on time of the transmission of the prioritized UL grant, and further update the MAC PDU including the third delay information delivered to the lower layer, for example, remove the third delay information from the MAC PDU.

In some implementations, if a triggered report for the third delay information has not been cancelled, the UE 104 may determine the first delay information by performing the method 400 as described above.

For example, in the example of Fig. 9, the UE 104 determines the first CG (such as CG#1 in Fig. 9) for the autonomous transmission of the first delay information. The first delay information indicates the first remaining time of the PDCP discard timer.

In addition, the UE 104 determines the first time point of the autonomous transmission as the first reference time. For example, in the example of in Fig. 9, the first time point of the initial transmission is T4. Thus, the UE 104 determines T4 as the first reference time.

In some implementations, the UE 104 may trigger a report for the first delay information for autonomous transmission over the first CG (such as CG#1 in Fig. 9) if a triggered report for the third delay information has been cancelled.

In some implementations, in order to report the first delay information to the base station 102, the UE 104 may perform the method 800 as described above.

In some implementations, the first CG, the second CG and the third CG are associated with a single HARQ process identity (ID) .

It shall be understood that the method 200 may be performed in combination with at least one of the methods 400, 600, 700, 800, 1000 and 1100. The scope of the present disclosure is not limited in this regard.

Fig. 12 illustrates a flowchart of a method 1200 that supports determination of status report format in accordance with aspects of the present disclosure. The operations of the method 1200 may be implemented by a device or its components as described herein. For example, the operations of the method 1200 may be performed by a UE 104 as described herein. In some implementations, the device may execute a set of instructions to control the function elements of the device to perform the described functions. Additionally, or alternatively, the device may perform aspects of the described functions using special-purpose hardware.

At 1210, the UE 104 determines a status report format for at least one BSR for at least one LCG.

At 1220, the UE 104 transmits, to the base station 102, the at least one BSR in the status report format.

In some implementations, the UE 104 may determine a first status report format as the status report format. The first status report format may comprise a first field and a second field. The first field is related to a first buffer size of the at least one LCG, and the second field is related to delay information for the at least one LCG. The delay information indicates remaining time of a PDCP discard timer. Hereinafter, the first status report format may be referred to as an enhanced BSR (EBSR) format. In some implementations, the first status report format may further comprise a third field, and the third field indicates whether the second field is present or not or whether there is available delay information available for transmission. The first status report format may further comprise a first field. The first status report format may further comprise a fourth field.

In some implementations, the first status report format may further comprise a fourth field, and the fourth field indicates whether the first field is present or not or whether there’s available delay information available for transmission.

In some implementations, the UE 104 may determine a second status report format as the status report format. The second status report format may comprise the first field and comprise none of the second field and the third field. The first field is related to a buffer size of the at least one LCG. The second field is related to delay information for the at least one LCG. The third field indicates whether the second field is present or not. The second status report format may comprise the fourth field.

In some implementations, the at least one LCG of the first status report may be replaced by the at least one logical channel.

In some implementations, the second status report format may comprise one of the following: a regular BSR format, a periodic BSR format, or a padding BSR format.

In some implementations, the UE 104 may receive a configuration of the status report format from the base station 102. The configuration may indicate one of the first status report format and the second status report format is to be used. The UE 104 may determine the status report format based on the configuration. For example, the configuration may indicate one of the first status report format and the second status report format is to be used for the at least one LCG. For example, the configuration may indicate one of the first status report format and the second status report format is to be used for the at least one logical channel. If an LCG including the at least one logical channel, the LCG is considered to use the first status report.

In some implementations, the UE 104 may receive a configuration of the at least one LCG from the base station 102. The configuration may indicate that the at least one LCG is configured to report the delay information. In other words, the UE 104 may be configured to report the delay information for at least one logical channel belonging to the at least one LCG. The UE 104 determines the at least one LCG which is configured to report the delay information according to the at least one logical channel included in the at least one LCG. Alternatively, the UE 104 may be configured to report the delay information for the at least one LCG.

In some implementations, if the UE 104 is configured to report the delay information, the UE 104 may determine the first status report format as the status report format.

In such implementations, if the report of the delay information has been cancelled. (i.e., delay information is not available for transmission) or not cancelled (i.e., delay information is available for transmission) but the at least one LCG has data available for transmission (i.e., buffer size to report) and the at least one LCG is configured to report the delay information, the UE 104 may determine the first status report format as the status report format.

In such implementations, even if only the LCGs different from all the at least one LCG only has data available for transmission (i.e., buffer size to report) and the LCGs are not configured to report the delay information, the UE 104 may determine the first status report format as the status report format.

In some implementations, if the at least one LCG has the delay information available for transmission, the UE 104 may determine the first status report format as the status report format.

In some implementations, if the at least one LCG has data available for transmission and the at least one LCG is configured to report the delay information, the UE 104 may determine the first status report format as the status report format.

In some implementations, enhanced BSR has the first status report format, BSR has the second status report format.

For example, for the regular BSR, the periodic BSR, or the padding BSR, the MAC entity shall:

1> if at least one LCG has data available for transmission with delay information report configured for transmission when the MAC PDU containing the BSR is to be built:

2> report enhanced BSR for all LCGs which have data available for transmission.

1> else:

2> report BSR for all LCGs which have data available for transmission.

1> if at least one LCG has data available for transmission with enhanced status report configured for transmission when the MAC PDU containing the BSR is to be built:

2> report enhanced BSR for all LCGs which have data available for transmission.

1> else:

2> report BSR for all LCGs which have data available for transmission.

For example, for a regular BSR, a periodic BSR or a padding BSR, the MAC entity of the UE 104 shall:

1> if at least one LCG has data available for transmission and delay information available for transmission when the MAC PDU containing the BSR is to be built:

2> report enhanced BSR for all LCGs which have data available for transmission.

1> else:

2> report BSR for all LCGs which have data available for transmission without delay information.

In some implementations, if the at least one LCG has data available for transmission and all of the at least one LCG has no delay information for the at least one LCG available for transmission, the UE 104 may determine the second status report format as the status report format.

In some implementations, if only the LCGs different from all the at least one LCG has data available for transmission and all of the LCGs is not configured to report delay information, the UE 104 may determine the second status report format as the status report format.

In some implementations, if only the LCGs different from all at least one LCG has data available for transmission and all the LCGs is not configured to use first status report, the UE 104 may determine the second status report format as the status report format.

In some implementations, the BSR in the second status report format may comprise one of the following: a regular BSR, a periodic BSR, or a padding BSR.

1> if at least one LCG has data available for transmission with delay information available for transmission when the MAC PDU containing the BSR is to be built:

2> report enhanced BSR for all LCGs which have data available for transmission

1> else:

2> report BSR for all LCGs which have data available for transmission.

In some implementations, if an uplink grant is not sufficient to accommodate a first status report format but sufficient to accommodate the second status report format, the UE 104 may determine the second status report format as the status report format.

For an example, for padding BSR, the MAC entity shall:

1> if the UL grant is not sufficient to include the Long EBSR but sufficient to include the Long BSR,

2> UE reports the Long BSR;

1> if the UL grant is not sufficient to include the short EBSR but sufficient to include the short BSR,

2> UE reports the Short BSR;

1> if the UL grant is not sufficient to include the Long truncated EBSR but sufficient to include the Long truncated BSR,

2> UE reports the Long truncated BSR

For an example, all triggered BSRs may be cancelled when the UL grant (s) can accommodate all pending data available for transmission but is not sufficient to additionally accommodate the BSR MAC CE and its subheader.

In some implementations, the at least one LCG may comprise a first LCG and a second LCG or the at least one LCG may comprise a first LCG, the second LCG is not configured to report delay information. A first priority of the first LCG is equal to a second priority of the second LCG. The first LCG has delay information available for transmission, and the second LCG has no delay information available for transmission. In such implementations, if an uplink grant is not sufficient to accommodate the first status report format, the UE 104 may report the at least one BSR for the first LCG and the second LCG in an order of the first LCG and the second LCG.

In such implementation, if the UE 104 reports the EBSR, and if the UL grant is not sufficient to include the Long EBSR but sufficient to include the Long truncated EBSR, the UE 104 reports EBSR for the LCG (s) following a decreasing order of the highest logical channel priority in each of the LCGs, and in case of equal priority, in order of LCG (s) with delay information available for transmission and without delay information available for transmission.

In such implementation, if the UE 104 reports the EBSR, and if the UL grant is not sufficient to include the Long EBSR but sufficient to include the Long truncated EBSR, the UE 104 reports EBSR for the LCG (s) following a decreasing order of the highest logical channel priority in each of the LCGs, in order of LCG (s) with delay information available for transmission and without delay information available for transmission, and in case of equal priority and with delay information available for transmission, in order of LCG (s) with delay information.

In such implementation, if the UE 104 reports the EBSR, and if the UL grant is not sufficient to include the Long EBSR but sufficient to include the Long truncated EBSR, the UE 104 reports EBSR for the LCG (s) following a decreasing order of the highest logical channel priority in each of the LCGs, in order of LCG (s) with delay information available for transmission and without delay information available for transmission, and in case of equal priority and with delay information available for transmission, in order of LCG (s) with delay information, and in case of equal priority and with equal delay information available for transmission, in increasing order of the LCG ID.

For example, for a padding BSR, the MAC entity shall:

3> else:

4> report Long Truncated BSR of the LCG (s) with the logical channels having data available for transmission following a decreasing order of the highest priority logical channel (with or without data available for transmission) in each of these LCG (s) , in case of equal priority and in case with and without delay information in each of these LCG ID, optionally in an order of with delay information and without delay information, and in case of equal priority and with delay information, optionally in increasing order of the delay information, and in case of equal priority and with equal delay information, optionally in increasing order of LCGID, in case of equal priority and without delay information, in increasing order of LCGID.

2> else:

3> report Short BSR.

2> report Long BSR for all LCGs which have data available for transmission.

In some implementations, report of the delay information may be cancelled. In some implementations, all of at least one report of the delay information triggered prior to MAC PDU assembly shall be cancelled when a MAC PDU is transmitted and this MAC PDU includes a Long or Short EBSR MAC CE which contains the delay information up to (and including) the last event that triggered a report prior to the MAC PDU assembly.

In some implementations, all of at least one triggered EBS report of the delay information may be cancelled when at least one UL grant can accommodate all pending data available for transmission with delay information but is not sufficient to additionally accommodate the EBSR MAC CE and its subheader.

It shall be understood that the method 1200 may be performed in combination with at least one of the methods 200, 400, 600, 700, 800, 1000 and 1100. The scope of the present disclosure is not limited in this regard.

Fig. 13 illustrates an example of a device 1300 that supports buffer status report in accordance with aspects of the present disclosure. The device 1300 may be an example of UE 104 as described herein. The device 1300 may support wireless communication with one or more network entities 102, UEs 104, or any combination thereof. The device 1300 may include components for bi-directional communications including components for transmitting and receiving communications, such as a processor 1302, a memory 1304, a transceiver 1306, and, optionally, an I/O controller 1308. These components may be in electronic communication or otherwise coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces (e.g., buses) .

The processor 1302, the memory 1304, the transceiver 1306, or various combinations thereof or various components thereof may be examples of means for performing various aspects of the present disclosure as described herein. For example, the processor 1302, the memory 1304, the transceiver 1306, or various combinations or components thereof may support a method for performing one or more of the operations described herein.

In some implementations, the processor 1302, the memory 1304, the transceiver 1306, or various combinations or components thereof may be implemented in hardware (e.g., in communications management circuitry) . The hardware may include a processor, a digital signal processor (DSP) , an application-specific integrated circuit (ASIC) , a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic, discrete hardware components, or any combination thereof configured as or otherwise supporting a means for performing the functions described in the present disclosure. In some implementations, the processor 1302 and the memory 1304 coupled with the processor 1302 may be configured to perform one or more of the functions described herein (e.g., executing, by the processor 1302, instructions stored in the memory 1304) .

For example, the processor 1302 may support wireless communication at the device 1300 in accordance with examples as disclosed herein. The processor 1302 may be configured to operable to support a means for performing the following: determining whether uplink data of at least one logical channel which belongs to at least one LCG becomes unavailable to a medium access control (MAC) entity of the UE; and based on determining that the uplink data becomes unavailable, triggering at least one first BSR for the at least one logical channel or for the at least one LCG, each of the at least one first BSR indicating a first buffer size of one of the at least one LCG is equal to zero.

The processor 1302 may include an intelligent hardware device (e.g., a general-purpose processor, a DSP, a CPU, a microcontroller, an ASIC, an FPGA, a programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof) . In some implementations, the processor 1302 may be configured to operate a memory array using a memory controller. In some other implementations, a memory controller may be integrated into the processor 1302. The processor 1302 may be configured to execute computer-readable instructions stored in a memory (e.g., the memory 1304) to cause the device 1300 to perform various functions of the present disclosure.

The memory 1304 may include random access memory (RAM) and read-only memory (ROM) . The memory 1304 may store computer-readable, computer-executable code including instructions that, when executed by the processor 1302 cause the device 1300 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such as system memory or another type of memory. In some implementations, the code may not be directly executable by the processor 1302 but may cause a computer (e.g., when compiled and executed) to perform functions described herein. In some implementations, the memory 1304 may include, among other things, a basic I/O system (BIOS) which may control basic hardware or software operation such as the interaction with peripheral components or devices.

The I/O controller 1308 may manage input and output signals for the device 1300. The I/O controller 1308 may also manage peripherals not integrated into the device M02. In some implementations, the I/O controller 1308 may represent a physical connection or port to an external peripheral. In some implementations, the I/O controller 1308 may utilize an operating system such as or another known operating system. In some implementations, the I/O controller 1308 may be implemented as part of a processor, such as the processor 1306. In some implementations, a user may interact with the device 1300 via the I/O controller 1308 or via hardware components controlled by the I/O controller 1308.

In some implementations, the device 1300 may include a single antenna 1310. However, in some other implementations, the device 1300 may have more than one antenna 1310 (i.e., multiple antennas) , including multiple antenna panels or antenna arrays, which may be capable of concurrently transmitting or receiving multiple wireless transmissions. The transceiver 1306 may communicate bi-directionally, via the one or more antennas 1310, wired, or wireless links as described herein. For example, the transceiver 1306 may represent a wireless transceiver and may communicate bi-directionally with another wireless transceiver. The transceiver 1306 may also include a modem to modulate the packets, to provide the modulated packets to one or more antennas 1310 for transmission, and to demodulate packets received from the one or more antennas 1310. The transceiver 1306 may include one or more transmit chains, one or more receive chains, or a combination thereof.

A transmit chain may be configured to generate and transmit signals (e.g., control information, data, packets) . The transmit chain may include at least one modulator for modulating data onto a carrier signal, preparing the signal for transmission over a wireless medium. The at least one modulator may be configured to support one or more techniques such as amplitude modulation (AM) , frequency modulation (FM) , or digital modulation schemes like phase-shift keying (PSK) or quadrature amplitude modulation (QAM) . The transmit chain may also include at least one power amplifier configured to amplify the modulated signal to an appropriate power level suitable for transmission over the wireless medium. The transmit chain may also include one or more antennas 1310 for transmitting the amplified signal into the air or wireless medium.

A receive chain may be configured to receive signals (e.g., control information, data, packets) over a wireless medium. For example, the receive chain may include one or more antennas 1310 for receive the signal over the air or wireless medium. The receive chain may include at least one amplifier (e.g., a low-noise amplifier (LNA) ) configured to amplify the received signal. The receive chain may include at least one demodulator configured to demodulate the receive signal and obtain the transmitted data by reversing the modulation technique applied during transmission of the signal. The receive chain may include at least one decoder for decoding the processing the demodulated signal to receive the transmitted data.

Fig. 14 illustrates an example of a device 1400 that supports determination of first delay information in accordance with aspects of the present disclosure. The device 1400 may be an example of a UE 104 as described herein. The device 1400 may support wireless communication with one or more network entities 102, UEs 104, or any combination thereof. The device 1400 may include components for bi-directional communications including components for transmitting and receiving communications, such as a processor 1402, a memory 1404, a transceiver 1406, and, optionally, an I/O controller 1408. These components may be in electronic communication or otherwise coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces (e.g., buses) .

The processor 1402, the memory 1404, the transceiver 1406, or various combinations thereof or various components thereof may be examples of means for performing various aspects of the present disclosure as described herein. For example, the processor 1402, the memory 1404, the transceiver 1406, or various combinations or components thereof may support a method for performing one or more of the operations described herein.

In some implementations, the processor 1402, the memory 1404, the transceiver 1406, or various combinations or components thereof may be implemented in hardware (e.g., in communications management circuitry) . The hardware may include a processor, a digital signal processor (DSP) , an application-specific integrated circuit (ASIC) , a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic, discrete hardware components, or any combination thereof configured as or otherwise supporting a means for performing the functions described in the present disclosure. In some implementations, the processor 1402 and the memory 1404 coupled with the processor 1402 may be configured to perform one or more of the functions described herein (e.g., executing, by the processor 1402, instructions stored in the memory 1404) .

For example, the processor 1402 may support wireless communication at the device 1400 in accordance with examples as disclosed herein. The processor 1402 may be configured to operable to support a means for performing the following: determining a first CG for an autonomous transmission of first delay information, the first delay information indicating first remaining time of a PDCP discard timer; determining a first time point of the autonomous transmission as a first reference time; and determining the first delay information based on a value of the PDCP discard timer and the first reference time.

The processor 1402 may include an intelligent hardware device (e.g., a general-purpose processor, a DSP, a CPU, a microcontroller, an ASIC, an FPGA, a programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof) . In some implementations, the processor 1402 may be configured to operate a memory array using a memory controller. In some other implementations, a memory controller may be integrated into the processor 1402. The processor 1402 may be configured to execute computer-readable instructions stored in a memory (e.g., the memory 1404) to cause the device 1400 to perform various functions of the present disclosure.

The memory 1404 may include random access memory (RAM) and read-only memory (ROM) . The memory 1404 may store computer-readable, computer-executable code including instructions that, when executed by the processor 1402 cause the device 1400 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such as system memory or another type of memory. In some implementations, the code may not be directly executable by the processor 1402 but may cause a computer (e.g., when compiled and executed) to perform functions described herein. In some implementations, the memory 1404 may include, among other things, a basic I/O system (BIOS) which may control basic hardware or software operation such as the interaction with peripheral components or devices.

The I/O controller 1408 may manage input and output signals for the device 1400. The I/O controller 1408 may also manage peripherals not integrated into the device M02. In some implementations, the I/O controller 1408 may represent a physical connection or port to an external peripheral. In some implementations, the I/O controller 1408 may utilize an operating system such as or another known operating system. In some implementations, the I/O controller 1408 may be implemented as part of a processor, such as the processor 1406. In some implementations, a user may interact with the device 1400 via the I/O controller 1408 or via hardware components controlled by the I/O controller 1408.

In some implementations, the device 1400 may include a single antenna 1410. However, in some other implementations, the device 1400 may have more than one antenna 1410 (i.e., multiple antennas) , including multiple antenna panels or antenna arrays, which may be capable of concurrently transmitting or receiving multiple wireless transmissions. The transceiver 1406 may communicate bi-directionally, via the one or more antennas 1410, wired, or wireless links as described herein. For example, the transceiver 1406 may represent a wireless transceiver and may communicate bi-directionally with another wireless transceiver. The transceiver 1406 may also include a modem to modulate the packets, to provide the modulated packets to one or more antennas 1410 for transmission, and to demodulate packets received from the one or more antennas 1410. The transceiver 1406 may include one or more transmit chains, one or more receive chains, or a combination thereof.

A transmit chain may be configured to generate and transmit signals (e.g., control information, data, packets) . The transmit chain may include at least one modulator for modulating data onto a carrier signal, preparing the signal for transmission over a wireless medium. The at least one modulator may be configured to support one or more techniques such as amplitude modulation (AM) , frequency modulation (FM) , or digital modulation schemes like phase-shift keying (PSK) or quadrature amplitude modulation (QAM) . The transmit chain may also include at least one power amplifier configured to amplify the modulated signal to an appropriate power level suitable for transmission over the wireless medium. The transmit chain may also include one or more antennas 1410 for transmitting the amplified signal into the air or wireless medium.

A receive chain may be configured to receive signals (e.g., control information, data, packets) over a wireless medium. For example, the receive chain may include one or more antennas 1410 for receive the signal over the air or wireless medium. The receive chain may include at least one amplifier (e.g., a low-noise amplifier (LNA) ) configured to amplify the received signal. The receive chain may include at least one demodulator configured to demodulate the receive signal and obtain the transmitted data by reversing the modulation technique applied during transmission of the signal. The receive chain may include at least one decoder for decoding the processing the demodulated signal to receive the transmitted data.

Fig. 15 illustrates an example of a device 1500 that supports determination of status report format in accordance with aspects of the present disclosure. The device 1500 may be an example of UE 104 as described herein. The device 1500 may support wireless communication with one or more network entities 102, UEs 104, or any combination thereof. The device 1500 may include components for bi-directional communications including components for transmitting and receiving communications, such as a processor 1502, a memory 1504, a transceiver 1506, and, optionally, an I/O controller 1508. These components may be in electronic communication or otherwise coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces (e.g., buses) .

The processor 1502, the memory 1504, the transceiver 1506, or various combinations thereof or various components thereof may be examples of means for performing various aspects of the present disclosure as described herein. For example, the processor 1502, the memory 1504, the transceiver 1506, or various combinations or components thereof may support a method for performing one or more of the operations described herein.

In some implementations, the processor 1502, the memory 1504, the transceiver 1506, or various combinations or components thereof may be implemented in hardware (e.g., in communications management circuitry) . The hardware may include a processor, a digital signal processor (DSP) , an application-specific integrated circuit (ASIC) , a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic, discrete hardware components, or any combination thereof configured as or otherwise supporting a means for performing the functions described in the present disclosure. In some implementations, the processor 1502 and the memory 1504 coupled with the processor 1502 may be configured to perform one or more of the functions described herein (e.g., executing, by the processor 1502, instructions stored in the memory 1504) .

For example, the processor 1502 may support wireless communication at the device 1500 in accordance with examples as disclosed herein. The processor 1502 may be configured to operable to support a means for performing the following: determining a status report format for at least one BSR for at least one LCG; and transmitting, to a base station, the at least one BSR in the status report format.

The processor 1502 may include an intelligent hardware device (e.g., a general-purpose processor, a DSP, a CPU, a microcontroller, an ASIC, an FPGA, a programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof) . In some implementations, the processor 1502 may be configured to operate a memory array using a memory controller. In some other implementations, a memory controller may be integrated into the processor 1502. The processor 1502 may be configured to execute computer-readable instructions stored in a memory (e.g., the memory 1504) to cause the device 1500 to perform various functions of the present disclosure.

The memory 1504 may include random access memory (RAM) and read-only memory (ROM) . The memory 1504 may store computer-readable, computer-executable code including instructions that, when executed by the processor 1502 cause the device 1500 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such as system memory or another type of memory. In some implementations, the code may not be directly executable by the processor 1502 but may cause a computer (e.g., when compiled and executed) to perform functions described herein. In some implementations, the memory 1504 may include, among other things, a basic I/O system (BIOS) which may control basic hardware or software operation such as the interaction with peripheral components or devices.

The I/O controller 1508 may manage input and output signals for the device 1500. The I/O controller 1508 may also manage peripherals not integrated into the device M02. In some implementations, the I/O controller 1508 may represent a physical connection or port to an external peripheral. In some implementations, the I/O controller 1508 may utilize an operating system such as or another known operating system. In some implementations, the I/O controller 1508 may be implemented as part of a processor, such as the processor 1506. In some implementations, a user may interact with the device 1500 via the I/O controller 1508 or via hardware components controlled by the I/O controller 1508.

In some implementations, the device 1500 may include a single antenna 1510. However, in some other implementations, the device 1500 may have more than one antenna 1510 (i.e., multiple antennas) , including multiple antenna panels or antenna arrays, which may be capable of concurrently transmitting or receiving multiple wireless transmissions. The transceiver 1506 may communicate bi-directionally, via the one or more antennas 1510, wired, or wireless links as described herein. For example, the transceiver 1506 may represent a wireless transceiver and may communicate bi-directionally with another wireless transceiver. The transceiver 1506 may also include a modem to modulate the packets, to provide the modulated packets to one or more antennas 1510 for transmission, and to demodulate packets received from the one or more antennas 1510. The transceiver 1506 may include one or more transmit chains, one or more receive chains, or a combination thereof.

A transmit chain may be configured to generate and transmit signals (e.g., control information, data, packets) . The transmit chain may include at least one modulator for modulating data onto a carrier signal, preparing the signal for transmission over a wireless medium. The at least one modulator may be configured to support one or more techniques such as amplitude modulation (AM) , frequency modulation (FM) , or digital modulation schemes like phase-shift keying (PSK) or quadrature amplitude modulation (QAM) . The transmit chain may also include at least one power amplifier configured to amplify the modulated signal to an appropriate power level suitable for transmission over the wireless medium. The transmit chain may also include one or more antennas 1510 for transmitting the amplified signal into the air or wireless medium.

A receive chain may be configured to receive signals (e.g., control information, data, packets) over a wireless medium. For example, the receive chain may include one or more antennas 1510 for receive the signal over the air or wireless medium. The receive chain may include at least one amplifier (e.g., a low-noise amplifier (LNA) ) configured to amplify the received signal. The receive chain may include at least one demodulator configured to demodulate the receive signal and obtain the transmitted data by reversing the modulation technique applied during transmission of the signal. The receive chain may include at least one decoder for decoding the processing the demodulated signal to receive the transmitted data.

Fig. 16 illustrates an example of a processor 1600 that supports buffer status report in accordance with aspects of the present disclosure. The processor 1600 may be an example of a processor configured to perform various operations in accordance with examples as described herein. The processor 1600 may include a controller 1602 configured to perform various operations in accordance with examples as described herein. The processor 1600 may optionally include at least one memory 1604, such as L1/L2/L3 cache. Additionally, or alternatively, the processor 1600 may optionally include one or more arithmetic-logic units (ALUs) 1600. One or more of these components may be in electronic communication or otherwise coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces (e.g., buses) .

The processor 1600 may be a processor chipset and include a protocol stack (e.g., a software stack) executed by the processor chipset to perform various operations (e.g., receiving, obtaining, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) in accordance with examples as described herein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the processor chipset (e.g., the processor 1600) or other memory (e.g., random access memory (RAM) , read-only memory (ROM) , dynamic RAM (DRAM) , synchronous dynamic RAM (SDRAM) , static RAM (SRAM) , ferroelectric RAM (FeRAM) , magnetic RAM (MRAM) , resistive RAM (RRAM) , flash memory, phase change memory (PCM) , and others) .

The controller 1602 may be configured to manage and coordinate various operations (e.g., signaling, receiving, obtaining, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) of the processor 1600 to cause the processor 1600 to support various operations in accordance with examples as described herein. For example, the controller 1602 may operate as a control unit of the processor 1600, generating control signals that manage the operation of various components of the processor 1600. These control signals include enabling or disabling functional units, selecting data paths, initiating memory access, and coordinating timing of operations.

The controller 1602 may be configured to fetch (e.g., obtain, retrieve, receive) instructions from the memory 1604 and determine subsequent instruction (s) to be executed to cause the processor 1600 to support various operations in accordance with examples as described herein. The controller 1602 may be configured to track memory address of instructions associated with the memory 1604. The controller 1602 may be configured to decode instructions to determine the operation to be performed and the operands involved. For example, the controller 1602 may be configured to interpret the instruction and determine control signals to be output to other components of the processor 1600 to cause the processor 1600 to support various operations in accordance with examples as described herein. Additionally, or alternatively, the controller 1602 may be configured to manage flow of data within the processor 1600. The controller 1602 may be configured to control transfer of data between registers, arithmetic logic units (ALUs) , and other functional units of the processor 1600.

The memory 1604 may include one or more caches (e.g., memory local to or included in the processor 1600 or other memory, such RAM, ROM, DRAM, SDRAM, SRAM, MRAM, flash memory, etc. In some implementation, the memory 1604 may reside within or on a processor chipset (e.g., local to the processor 1600) . In some other implementations, the memory 1604 may reside external to the processor chipset (e.g., remote to the processor 1600) .

The memory 1604 may store computer-readable, computer-executable code including instructions that, when executed by the processor 1600, cause the processor 1600 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such as system memory or another type of memory. The controller 1602 and/or the processor 1600 may be configured to execute computer-readable instructions stored in the memory 1604 to cause the processor 1600 to perform various functions. For example, the processor 1600 and/or the controller 1602 may be coupled with or to the memory 1604, the processor 1600, the controller 1602, and the memory 1604 may be configured to perform various functions described herein. In some examples, the processor 1600 may include multiple processors and the memory 1604 may include multiple memories. One or more of the multiple processors may be coupled with one or more of the multiple memories, which may, individually or collectively, be configured to perform various functions herein.

The one or more ALUs 1600 may be configured to support various operations in accordance with examples as described herein. In some implementation, the one or more ALUs 1600 may reside within or on a processor chipset (e.g., the processor 1600) . In some other implementations, the one or more ALUs 1600 may reside external to the processor chipset (e.g., the processor 1600) . One or more ALUs 1600 may perform one or more computations such as addition, subtraction, multiplication, and division on data. For example, one or more ALUs 1600 may receive input operands and an operation code, which determines an operation to be executed. One or more ALUs 1600 be configured with a variety of logical and arithmetic circuits, including adders, subtractors, shifters, and logic gates, to process and manipulate the data according to the operation. Additionally, or alternatively, the one or more ALUs 1600 may support logical operations such as AND, OR, exclusive-OR (XOR) , not-OR (NOR) , and not-AND (NAND) , enabling the one or more ALUs 1600 to handle conditional operations, comparisons, and bitwise operations.

The processor 1600 may support wireless communication in accordance with examples as disclosed herein. The processor 1600 may be configured to or operable to support a means for performing the following: determining whether uplink data of at least one logical channel which belongs to at least one LCG becomes unavailable to a medium access control (MAC) entity of the UE; and based on determining that the uplink data becomes unavailable, triggering at least one first BSR for the at least one logical channel or for the at least one LCG, each of the at least one first BSR indicating a first buffer size of one of the at least one LCG is equal to zero.

Fig. 17 illustrates an example of a processor 1700 that supports determination of first delay information in accordance with aspects of the present disclosure. The processor 1700 may be an example of a processor configured to perform various operations in accordance with examples as described herein. The processor 1700 may include a controller 1702 configured to perform various operations in accordance with examples as described herein. The processor 1700 may optionally include at least one memory 1704, such as L1/L2/L3 cache. Additionally, or alternatively, the processor 1700 may optionally include one or more arithmetic-logic units (ALUs) 1700. One or more of these components may be in electronic communication or otherwise coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces (e.g., buses) .

The processor 1700 may be a processor chipset and include a protocol stack (e.g., a software stack) executed by the processor chipset to perform various operations (e.g., receiving, obtaining, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) in accordance with examples as described herein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the processor chipset (e.g., the processor 1700) or other memory (e.g., random access memory (RAM) , read-only memory (ROM) , dynamic RAM (DRAM) , synchronous dynamic RAM (SDRAM) , static RAM (SRAM) , ferroelectric RAM (FeRAM) , magnetic RAM (MRAM) , resistive RAM (RRAM) , flash memory, phase change memory (PCM) , and others) .

The controller 1702 may be configured to manage and coordinate various operations (e.g., signaling, receiving, obtaining, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) of the processor 1700 to cause the processor 1700 to support various operations in accordance with examples as described herein. For example, the controller 1702 may operate as a control unit of the processor 1700, generating control signals that manage the operation of various components of the processor 1700. These control signals include enabling or disabling functional units, selecting data paths, initiating memory access, and coordinating timing of operations.

The controller 1702 may be configured to fetch (e.g., obtain, retrieve, receive) instructions from the memory 1704 and determine subsequent instruction (s) to be executed to cause the processor 1700 to support various operations in accordance with examples as described herein. The controller 1702 may be configured to track memory address of instructions associated with the memory 1704. The controller 1702 may be configured to decode instructions to determine the operation to be performed and the operands involved. For example, the controller 1702 may be configured to interpret the instruction and determine control signals to be output to other components of the processor 1700 to cause the processor 1700 to support various operations in accordance with examples as described herein. Additionally, or alternatively, the controller 1702 may be configured to manage flow of data within the processor 1700. The controller 1702 may be configured to control transfer of data between registers, arithmetic logic units (ALUs) , and other functional units of the processor 1700.

The memory 1704 may include one or more caches (e.g., memory local to or included in the processor 1700 or other memory, such RAM, ROM, DRAM, SDRAM, SRAM, MRAM, flash memory, etc. In some implementation, the memory 1704 may reside within or on a processor chipset (e.g., local to the processor 1700) . In some other implementations, the memory 1704 may reside external to the processor chipset (e.g., remote to the processor 1700) .

The memory 1704 may store computer-readable, computer-executable code including instructions that, when executed by the processor 1700, cause the processor 1700 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such as system memory or another type of memory. The controller 1702 and/or the processor 1700 may be configured to execute computer-readable instructions stored in the memory 1704 to cause the processor 1700 to perform various functions. For example, the processor 1700 and/or the controller 1702 may be coupled with or to the memory 1704, the processor 1700, the controller 1702, and the memory 1704 may be configured to perform various functions described herein. In some examples, the processor 1700 may include multiple processors and the memory 1704 may include multiple memories. One or more of the multiple processors may be coupled with one or more of the multiple memories, which may, individually or collectively, be configured to perform various functions herein.

The one or more ALUs 1700 may be configured to support various operations in accordance with examples as described herein. In some implementation, the one or more ALUs 1700 may reside within or on a processor chipset (e.g., the processor 1700) . In some other implementations, the one or more ALUs 1700 may reside external to the processor chipset (e.g., the processor 1700) . One or more ALUs 1700 may perform one or more computations such as addition, subtraction, multiplication, and division on data. For example, one or more ALUs 1700 may receive input operands and an operation code, which determines an operation to be executed. One or more ALUs 1700 be configured with a variety of logical and arithmetic circuits, including adders, subtractors, shifters, and logic gates, to process and manipulate the data according to the operation. Additionally, or alternatively, the one or more ALUs 1700 may support logical operations such as AND, OR, exclusive-OR (XOR) , not-OR (NOR) , and not-AND (NAND) , enabling the one or more ALUs 1700 to handle conditional operations, comparisons, and bitwise operations.

The processor 1700 may support wireless communication in accordance with examples as disclosed herein. The processor 1700 may be configured to or operable to support a means for performing the following: determining a first CG for a autonomous transmission of first delay information, the first delay information indicating first remaining time of a PDCP discard timer; determining a first time point of the autonomous transmission as a first reference time; and determining the first delay information based on a value of the PDCP discard timer and the first reference time.

Fig. 18 illustrates an example of a processor 1800 that supports determination of status report format in accordance with aspects of the present disclosure. The processor 1800 may be an example of a processor configured to perform various operations in accordance with examples as described herein. The processor 1800 may include a controller 1802 configured to perform various operations in accordance with examples as described herein. The processor 1800 may optionally include at least one memory 1804, such as L1/L2/L3 cache. Additionally, or alternatively, the processor 1800 may optionally include one or more arithmetic-logic units (ALUs) 1800. One or more of these components may be in electronic communication or otherwise coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces (e.g., buses) .

The processor 1800 may be a processor chipset and include a protocol stack (e.g., a software stack) executed by the processor chipset to perform various operations (e.g., receiving, obtaining, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) in accordance with examples as described herein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the processor chipset (e.g., the processor 1800) or other memory (e.g., random access memory (RAM) , read-only memory (ROM) , dynamic RAM (DRAM) , synchronous dynamic RAM (SDRAM) , static RAM (SRAM) , ferroelectric RAM (FeRAM) , magnetic RAM (MRAM) , resistive RAM (RRAM) , flash memory, phase change memory (PCM) , and others) .

The controller 1802 may be configured to manage and coordinate various operations (e.g., signaling, receiving, obtaining, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) of the processor 1800 to cause the processor 1800 to support various operations in accordance with examples as described herein. For example, the controller 1802 may operate as a control unit of the processor 1800, generating control signals that manage the operation of various components of the processor 1800. These control signals include enabling or disabling functional units, selecting data paths, initiating memory access, and coordinating timing of operations.

The controller 1802 may be configured to fetch (e.g., obtain, retrieve, receive) instructions from the memory 1804 and determine subsequent instruction (s) to be executed to cause the processor 1800 to support various operations in accordance with examples as described herein. The controller 1802 may be configured to track memory address of instructions associated with the memory 1804. The controller 1802 may be configured to decode instructions to determine the operation to be performed and the operands involved. For example, the controller 1802 may be configured to interpret the instruction and determine control signals to be output to other components of the processor 1800 to cause the processor 1800 to support various operations in accordance with examples as described herein. Additionally, or alternatively, the controller 1802 may be configured to manage flow of data within the processor 1800. The controller 1802 may be configured to control transfer of data between registers, arithmetic logic units (ALUs) , and other functional units of the processor 1800.

The memory 1804 may include one or more caches (e.g., memory local to or included in the processor 1800 or other memory, such RAM, ROM, DRAM, SDRAM, SRAM, MRAM, flash memory, etc. In some implementation, the memory 1804 may reside within or on a processor chipset (e.g., local to the processor 1800) . In some other implementations, the memory 1804 may reside external to the processor chipset (e.g., remote to the processor 1800) .

The memory 1804 may store computer-readable, computer-executable code including instructions that, when executed by the processor 1800, cause the processor 1800 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such as system memory or another type of memory. The controller 1802 and/or the processor 1800 may be configured to execute computer-readable instructions stored in the memory 1804 to cause the processor 1800 to perform various functions. For example, the processor 1800 and/or the controller 1802 may be coupled with or to the memory 1804, the processor 1800, the controller 1802, and the memory 1804 may be configured to perform various functions described herein. In some examples, the processor 1800 may include multiple processors and the memory 1804 may include multiple memories. One or more of the multiple processors may be coupled with one or more of the multiple memories, which may, individually or collectively, be configured to perform various functions herein.

The one or more ALUs 1800 may be configured to support various operations in accordance with examples as described herein. In some implementation, the one or more ALUs 1800 may reside within or on a processor chipset (e.g., the processor 1800) . In some other implementations, the one or more ALUs 1800 may reside external to the processor chipset (e.g., the processor 1800) . One or more ALUs 1800 may perform one or more computations such as addition, subtraction, multiplication, and division on data. For example, one or more ALUs 1800 may receive input operands and an operation code, which determines an operation to be executed. One or more ALUs 1800 be configured with a variety of logical and arithmetic circuits, including adders, subtractors, shifters, and logic gates, to process and manipulate the data according to the operation. Additionally, or alternatively, the one or more ALUs 1800 may support logical operations such as AND, OR, exclusive-OR (XOR) , not-OR (NOR) , and not-AND (NAND) , enabling the one or more ALUs 1800 to handle conditional operations, comparisons, and bitwise operations.

The processor 1800 may support wireless communication in accordance with examples as disclosed herein. The processor 1800 may be configured to or operable to support a means for performing the following: determining a status report format for at least one BSR for at least one LCG; and transmitting, to a base station, the at least one BSR in the status report format.

It should be noted that the methods described herein describes possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Further, aspects from two or more of the methods may be combined.

The various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed with a general-purpose processor, a DSP, an ASIC, a CPU, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions may also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium that may be accessed by a general-purpose or special-purpose computer. By way of example, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable ROM (EEPROM) , flash memory, compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that may be used to carry or store desired program code means in the form of instructions or data structures and that may be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor.

As used herein, including in the claims, an article “a” before an element is unrestricted and understood to refer to “at least one” of those elements or “one or more” of those elements. The terms “a, ” “at least one, ” “one or more, ” and “at least one of one or more” may be interchangeable. As used herein, including in the claims, “or” as used in a list of items (e.g., a list of items prefaced by a phrase such as “at least one of” or “one or more of” or “one or both of” ) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C) . Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an example step that is described as “based on condition A” may be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on”shall be construed in the same manner as the phrase “based at least in part on. Further, as used herein, including in the claims, a “set” may include one or more elements.

The description herein is provided to enable a person having ordinary skill in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to a person having ordinary skill in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

A user equipment (UE) , comprising:

a processor; and

a transceiver coupled to the processor,

wherein the processor is configured to:

determine whether uplink data of at least one logical channel which belongs to at least one logical channel group (LCG) becomes unavailable to a medium access control (MAC) entity of the UE; and

based on determining that the uplink data becomes unavailable, trigger at least one first Buffer Status Report (BSR) for the at least one logical channel or for the at least one LCG, each of the at least one first BSR indicating a first buffer size of one of the at least one LCG is equal to zero.
The UE of claim 1, wherein the processor is configured to determine that the uplink data becomes unavailable by:

detecting at least one end of at least one data burst of the at least one logical channel.
The UE of claim 1, wherein the at least one first BSR comprises at least one dedicated BSR.
The UE of claim 3, wherein a first priority of the at least one dedicated BSR is above, equal to or below a second priority of a regular BSR or a periodic BSR.
The UE of claim 1, wherein the processor is configured to trigger the at least one first BSR by:

triggering the at least one first BSR based on determining the following:

the uplink data becomes unavailable; and

no triggered third BSR indicates the first buffer size is equal to zero.
The UE of claim 1, wherein the processor is further configured:

not to cancel the triggered at least one first BSR based on determining that an uplink grant can accommodate all pending data available for transmission but is not sufficient to additionally accommodate a MAC control element (CE) and a subheader of the MAC CE, the MAC CE comprising the triggered at least one first BSR.
The UE of claim 1, wherein the processor is configured to determine whether the uplink data of the at least one logical channel which belongs to the at least one LCG becomes unavailable by:

receiving, via the transceiver from a base station, a configuration for the least one logical channel or the at least one LCG; and

determining whether the uplink data becomes unavailable based on the configuration.
A user equipment (UE) , comprising:

a processor; and

a transceiver coupled to the processor,

wherein the processor is configured to:

determine a first configured grant (CG) for an autonomous transmission of first delay information, the first delay information indicating first remaining time of a packet data convergence protocol (PDCP) discard timer;

determine a first time point of the autonomous transmission as a first reference time; and

determine the first delay information based on a value of the PDCP discard timer and the first reference time.
The UE of claim 8, wherein the processor is further configured to:

obtain the medium access control (MAC) protocol data unit (PDU) from the identified hybrid automatic repeat request (HARQ) process of the first CG based on determining that none of at least one physical uplink shared channel (PUSCH) transmission of the MAC PDU has been completely performed;

update the MAC PDU with the first delay information; and

transmit the MAC PDU via the transceiver to a base station.
The UE of claim 8, wherein the processor is further configured to:

obtain a medium access control (MAC) protocol data unit (PDU) from an identified hybrid automatic repeat request (HARQ) process based on determining that a CG previous to the first CG was deprioritized.
A user equipment (UE) , comprising:

a processor; and

a transceiver coupled to the processor,

wherein the processor is configured to:

determine a status report format for at least one Buffer Status Report (BSR) for at least one logical channel group (LCG) ; and

transmit, via the transceiver to a base station, the at least one BSR in the status report format.
The UE of claim 11, wherein the processor is configured to determine the status report format by:

determining a first status report format as the status report format, the first status report format comprising a first field and a second field, the first field being related to a first buffer size of the at least one LCG, and the second field being related to delay information for the at least one LCG, the delay information indicating remaining time of a packet data convergence protocol (PDCP) discard timer.
The UE of claim 12, wherein the processor is configured to determine the first status report format as the status report format by:

based on determining that the UE is configured to report the delay information or to use the first status report, determining the first status report format as the status report format.
The UE of claim 12, wherein the processor is configured to determine the first status report format as the status report format by:

based on determining that the at least one LCG has the delay information available for transmission, determining the first status report format as the status report format.
The UE of claim 12, wherein the processor is configured to determine the first status report format as the status report format by:

based on determining that the at least one LCG has data available for transmission and the at least one LCG is configured to report the delay information or use the first status report, determining the first status report format as the status report format.
The UE of claim 11, wherein the processor is configured to determine the status report format by:

determining a second status report format as the status report format, the second status report format comprising a first field and comprising none of a second field and a third field, the first field being related to a buffer size of the at least one LCG.
The UE of claim 16, wherein the processor is configured to determine the second status report format as the status report format by:

based on determining that the at least one LCG has data available for transmission and all of the at least one LCG has no delay information for the at least one LCG available for transmission, determining the second status report format as the status report format, the delay information indicating remaining time of a packet data convergence protocol (PDCP) discard timer.
The UE of claim 16 or 17, wherein the processor is configured to determine the second status report format as the status report format by:

based on determining that the at least one LCG has data available for transmission and all of the at least one LCG is not configured to report delay information or use the first status report for the at least one LCG available for transmission, determining the second status report format as the status report format, the delay information indicating remaining time of a packet data convergence protocol (PDCP) discard timer.
The UE of claim 16, wherein the processor is configured to determine the second status report format as the status report format by:

based on determining that an uplink grant is not sufficient to accommodate a first status report format but sufficient to accommodate the second status report format, the first status report format comprising the first field and a second field, the second field being related to delay information for the at least one LCG, the delay information indicating remaining time of a packet data convergence protocol (PDCP) discard timer.
The UE of claim 12, wherein the at least one LCG comprises a first LCG and a second LCG, a first priority of the first LCG is equal to a second priority of the second LCG, the first LCG has delay information available for transmission, and the second LCG has no delay information available for transmission; and

the processor is configured to transmit the at least one BSR by:

based on determining that an uplink grant is not sufficient to accommodate the first status report format, reporting the at least one BSR for the first LCG and the second LCG in an order of the first LCG and the second LCG.