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WO2024089809A1 - Method for manufacturing memory device using semiconductor element - Google Patents

Method for manufacturing memory device using semiconductor element Download PDF

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Publication number
WO2024089809A1
WO2024089809A1 PCT/JP2022/039959 JP2022039959W WO2024089809A1 WO 2024089809 A1 WO2024089809 A1 WO 2024089809A1 JP 2022039959 W JP2022039959 W JP 2022039959W WO 2024089809 A1 WO2024089809 A1 WO 2024089809A1
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layer
material layer
memory cell
gate conductor
layers
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French (fr)
Japanese (ja)
Inventor
望 原田
康司 作井
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Unisantis Electronics Singapore Pte Ltd
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Unisantis Electronics Singapore Pte Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present invention relates to a method for manufacturing a memory device using semiconductor elements.
  • DRAM Dynamic Random Access Memory
  • SGT Square Gate Transistor
  • Patent Document 1 and Non-Patent Document 1 a selection transistor and connects a capacitor
  • PCM Phase Change Memory
  • RRAM Resistive Random Access Memory
  • Non-Patent Document 4 a resistive variable element
  • MRAM Magnetic-resistive Random Access Memory
  • DRAM memory cells (see Patent Document 2, Non-Patent Documents 6 to 10) that are composed of one MOS transistor without a capacitor.
  • a source-drain current of an N-channel MOS transistor generates a group of holes and electrons in the channel by impact ionization, and some or all of the group of holes are retained in the channel to write logical memory data "1". Then, the group of holes is removed from the channel to write logical memory data "0".
  • this memory cell there are random memory cells with "1” written and memory cells with "0" written for a common selected word line.
  • the floating body channel voltage of the selected memory cell connected to this selected word line fluctuates greatly due to the capacitive coupling between the gate electrode and the channel.
  • the issues are to improve the decrease in operating margin due to the fluctuation in the floating body channel voltage, and to improve the decrease in data retention characteristics due to the removal of some of the group of holes, which are the signal charges stored in the channel.
  • Twin-Transistor MOS transistor memory element in which one memory cell is formed using two MOS transistors in an SOI (Silicon On Insulator) layer (see, for example, Patent Documents 3 and 4, and Non-Patent Document 11).
  • an N + layer which serves as a source or drain and separates the floating body channels of the two MOS transistors, is formed in contact with an insulating layer on the substrate side.
  • This N + layer electrically separates the floating body channels of the two MOS transistors.
  • a group of holes which is a signal charge, is accumulated only in the floating body channel of one MOS transistor.
  • the other MOS transistor serves as a switch for reading out the group of holes of the signal accumulated in the other MOS transistor.
  • the group of holes which is a signal charge, is accumulated in the channel of one MOS transistor, so that, as in the memory cell consisting of one MOS transistor described above, the problem is to improve the decrease in the operating margin or to improve the decrease in data retention characteristics caused by removing part of the group of holes, which is the signal charge accumulated in the channel.
  • FIG. 6 there is a dynamic flash memory cell 111 composed of a MOS transistor without a capacitor (see Patent Document 5 and Non-Patent Document 12).
  • a floating body semiconductor body 102 on a SiO 2 layer 101 of an SOI substrate.
  • an N + layer 103 connected to a source line SL and an N + layer 104 connected to a bit line BL.
  • first gate insulating layer 109a connected to the N + layer 103 and covering the floating body semiconductor body 102, the N + layer 104, and a second gate insulating layer 109b connected to the first gate insulating layer 109a via a slit insulating film 110 and covering the floating body semiconductor body 102.
  • first gate conductor layer 105a that covers the first gate insulating layer 109a and is connected to the plate line PL
  • second gate conductor layer 105b that covers the second gate insulating layer 109b and is connected to the word line WL.
  • a slit insulating layer 110 between the first gate conductor layer 105a and the second gate conductor layer 105b.
  • DFM Dynamic Flash Memory
  • a zero voltage is applied to the N + layer 103, and a positive voltage is applied to the N + layer 104, so that the first N-channel MOS transistor region made of the floating body semiconductor body 102 covered with the first gate conductor layer 105a is operated in the saturation region, and the second N-channel MOS transistor region made of the floating body semiconductor body 102 covered with the second gate conductor layer 105b is operated in the linear region.
  • the second N-channel MOS transistor region no pinch-off point exists, and an inversion layer 107b is formed over the entire surface.
  • the inversion layer 107b formed under the second gate conductor layer 105b connected to the word line WL acts as a substantial drain of the first N-channel MOS transistor region.
  • the memory write operation is performed by removing the electrons from the electron-hole group generated by the impact ionization phenomenon from the floating body semiconductor body 102 and retaining some or all of the hole group 106 in the floating body semiconductor body 102. This state becomes logical storage data "1".
  • a positive voltage is applied to the plate line PL
  • a zero voltage is applied to the word line WL and the bit line BL
  • a negative voltage is applied to the source line SL to remove the hole group 106 from the floating body semiconductor body 102 to perform an erase operation.
  • This state becomes logical memory data "0".
  • the voltage applied to the first gate conductor layer 105a connected to the plate line PL is set to be higher than the threshold voltage when logical memory data is "1" and lower than the threshold voltage when logical memory data is "0", thereby obtaining a characteristic in which no current flows even if the voltage of the word line WL is increased when reading logical memory data "0", as shown in FIG. 6(d).
  • the channels of the first and second N-channel MOS transistor regions which have the first gate conductor layer 105a connected to the plate line PL and the second gate conductor layer 105b connected to the word line WL as their gates, are connected by the floating body semiconductor body 102, so that the voltage fluctuation of the floating body semiconductor body 102 when a selection pulse voltage is applied to the word line WL is greatly suppressed.
  • Critoloveanu “A Compact Capacitor-Less High-Speed DRAM Using Field Effect-Controlled Charge Regeneration,” Electron Device Letters, Vol. 35, No. 2, pp. 179-181 (2012) T. Ohsawa, K. Fujita, T. Higashi, Y. Iwata, T. Kajiyama, Y. Asao, and K. Sunouchi: “Memory design using a one-transistor gain cell on SOI,” IEEE JSSC, vol.37, No.11, pp1510-1522 (2002). T. Shino, N. Kusunoki, T. Higashi, T. Ohsawa, K. Fujita, K. Hatsuda, N. Ikumi, F.
  • a method for manufacturing a memory device using a semiconductor element includes the steps of: A method for manufacturing a memory device performing a data write operation, a data read operation, and a data erase operation by applying voltages to a first impurity layer, a first gate conductor layer, a second gate conductor layer, a second impurity layer, a third impurity layer, a third gate conductor layer, a fourth gate conductor layer, and a fourth impurity layer, the method comprising: forming, from below, on a first substrate, the first impurity layer, a first semiconductor layer, a first gate insulating layer surrounding the first semiconductor layer, a first gate conductor layer surrounding a lower portion of the first gate insulating layer, a second gate conductor layer surrounding an upper portion of the first gate insulating layer, and the second impurity layer; forming a first conductor layer connected to the second impurity layer and extending in a horizontal direction, a first
  • the second invention is the first invention described above, characterized in that the first material layer and the third material layer are made of conductive material layers, and the second material layer and the third material layer are made of oxide insulating layers.
  • the third invention is the second invention described above, characterized in that the first material layer has a structure in which the first conductor layer extends upward.
  • the fourth invention is characterized in that in the first invention, the first material layer is made up of the first conductor layer extending upward and an oxide insulating layer on the first conductor layer, and the second material is formed from a portion where the first conductor layer is connected to the second impurity layer and the oxide insulating layer in the horizontal direction from the first material layer portion.
  • the fifth invention is the first invention, characterized in that the first material layer is an oxide insulating layer, and the second material layer is formed from the second impurity layer extending in the vertical direction.
  • the sixth invention is the first invention, characterized in that the first and third gate conductor layers and the second and fourth gate conductor layers are formed by dividing them into multiple parts in a vertical cross section or a horizontal cross section.
  • the seventh invention is characterized in that, in the first invention, one of the first and third gate conductor layers and the second and fourth gate conductor layers is connected to a plate line, and the other is connected to a word line.
  • the eighth invention is the first invention, characterized in that one of the first impurity layer and the second impurity layer is connected to a bit line, and the other is connected to a source line.
  • 1A to 1C are structural diagrams illustrating a method for manufacturing a two-stage dynamic flash memory cell according to a first embodiment
  • 1A to 1C are structural diagrams illustrating a method for manufacturing a two-stage dynamic flash memory cell according to a first embodiment
  • 1A to 1C are structural diagrams illustrating a method for manufacturing a two-stage dynamic flash memory cell according to a first embodiment
  • 1A to 1C are structural diagrams illustrating a method for manufacturing a two-stage dynamic flash memory cell according to a first embodiment
  • 11A and 11B are structural diagrams for explaining a method for manufacturing a two-stage dynamic flash memory cell according to a second embodiment.
  • FIG. 1 is a diagram for explaining a conventional dynamic flash memory.
  • FIG. 1A shows a plan view of the memory cell
  • FIG. 2A shows a cross-sectional view taken along line XX' in (a)
  • FIG. 2A shows a cross-sectional view of a one-stage dynamic flash memory cell
  • FIG. 2A shows a cross-sectional view of a one-stage dynamic flash memory cell different from the one-stage dynamic flash memory cell in (a).
  • a first N + layer 2a (an example of a "first impurity layer” in the claims), a first P layer 3 (an example of a “first semiconductor layer” in the claims), and a second N + layer 2b (an example of a "second impurity layer” in the claims) are formed on a P layer substrate 1 (an example of a "first substrate” in the claims).
  • a first conductor layer 4 is formed on a part of the upper surface of the first N + layer 2a and extending in the Y-Y' line direction in a plan view.
  • a first insulating layer 15 is formed covering the first P layer substrate 1, the first N + layer 2a, and the first metal layer 4.
  • a first gate insulating layer 5 (an example of a "first gate insulating layer” in the claims) is formed surrounding the first P layer 3.
  • a first gate conductor layer 6 (an example of the "first gate conductor layer” in the claims), a second insulating layer 7, and a second gate conductor layer 8 (an example of the "second gate conductor layer” in the claims) are formed from below, surrounding the first gate insulating layer 5.
  • a third insulating layer 9 is formed on the second gate conductor layer 8, surrounding the outer periphery of the second N + layer 2b.
  • the first P layer 3 may be formed by, for example, an epitaxial crystal growth method, a Metal-Assisted Solid-Phase Crystallization (MSC) method, or a Metal-Induced Lateral Crystallization (MILC) method after forming at least the first gate conductor layer 6, the second insulating layer 7, the second gate conductor layer 8, and the third insulating layer 9.
  • the first gate conductor layer 6 and the second gate conductor layer 8 may be formed by removing the dummy gate layer after forming the first P layer 3, and filling the resulting space with material layers for the first gate conductor layer 6 and the second gate conductor layer 8.
  • the first P layer 3 may be formed by forming a single crystal P-type semiconductor layer using lithography and etching.
  • a second conductor layer 11 (an example of the "first conductor layer” in the claims) is formed on the third insulating layer 9 and surrounding the N + layer 2b, a first material layer 12 (an example of the "first material layer” in the claims), and a second material layer 13 (an example of the "second material layer” in the claims) is formed on the N + layer 2b.
  • One or both of the first material layer 12 and the second material layer 13 are formed of an oxide insulating layer such as silicon oxide (SiO2).
  • the first conductor layer 4 is connected to the first bit line (BL1), the first gate conductor layer 6 is connected to the first plate line PL1, the second gate conductor layer 8 is connected to the first word line WL1, and the second conductor layer 11 is connected to the first source line SL1.
  • a one-stage dynamic flash memory cell (an example of the "first memory cell” in the claims) is formed on the P-layer substrate 1.
  • 1A and 1B show only a single memory cell, but in reality, a plurality of memory cells are formed two-dimensionally at the same time (this is the same in other embodiments).
  • the first gate conductor layer 6, the second gate conductor layer 8, and the second conductor layer 11 in the memory block are formed to be commonly connected within the memory block region.
  • Figures 2A(a) and (b) show cross sections of two single-stage dynamic flash memory cells.
  • Figure 2A(a) is a cross section of a single-stage dynamic flash memory cell formed by the process shown in Figures 1A and 1B.
  • Figure 2A(b) is a cross section of another single-stage dynamic flash memory cell formed by the same process as Figure 2A(a) and having the same structure as Figure 2A(a).
  • the P-layer substrate 1a (an example of the "second substrate” in the claims) in Figure 2A(b) corresponds to the P-layer substrate 1 in Figure 2A(a).
  • the third N + layer 2aa corresponds to the first N + layer 2a.
  • the second P layer 3a corresponds to the first P layer 3, and the fourth N + layer 2ba corresponds to the second N + layer 4a.
  • the third conductor layer 4a corresponds to the first conductor layer 4
  • the fourth insulating layer 15a corresponds to the first insulating layer 15
  • the second gate insulating layer 5a corresponds to the first gate insulating layer 5
  • the third gate conductor layer 6a corresponds to the first gate conductor layer 6
  • the fifth insulating layer 7a corresponds to the second insulating layer 7
  • the fourth gate conductor layer 8a corresponds to the second gate conductor layer 8
  • the sixth insulating layer 9a corresponds to the third insulating layer 9
  • the fourth conductor layer 11a corresponds to the second conductor layer 11
  • the third material layer 12a (an example of the "third material layer” in the claims) corresponds to the first material layer 12
  • the fourth material layer 13a (an example of the "fourth material layer” in the claims) corresponds to the second material layer 13.
  • the third conductor layer 4a is connected to the second bit line (BL2), the third gate conductor layer 6a is connected to the second plate line PL2, the fourth gate conductor layer 8a is connected to the second word line WL2, and the fourth conductor layer 11a is connected to the second source line SL1.
  • the one-stage dynamic flash memory cell of FIG. 2A(b) (an example of the "second memory cell” in the claims) is turned upside down and bonded to the one-stage dynamic flash memory cell of FIG. 2A(a) such that the first material layer 12 and the third material layer 12a overlap, and similarly the second material layer 13 and the fourth material layer 13a overlap.
  • the bonding strength of the two one-stage dynamic flash memory cells can be increased. Then, the second P-layer substrate 1a is thinned to a predetermined thickness by etching from the upper surface.
  • FIG. 2B shows the state where the single-stage dynamic flash memory cell of FIG. 2A(b) is turned upside down and bonded to the single-stage dynamic flash memory cell of FIG. 2A(a) such that the first material layer 12 and the third material layer 12a overlap, and similarly the second material layer 13 and the fourth material layer 13a overlap.
  • the second P-layer substrate 1a is then etched from the top surface to a predetermined thickness to form a two-stage dynamic flash memory cell (an example of the "two-stage memory cell" in the claims). In practice, this two-stage dynamic flash memory cell is formed two-dimensionally on the P-layer substrate 1.
  • the first gate conductor layer 6, the second gate conductor layer 8, the second conductor layer 11, the fourth conductor layer 11a, the fourth gate conductor layer 8a, and the third gate conductor layer 6a in the block region are formed to be commonly connected between the two-stage dynamic flash memory cells in the block region.
  • the first gate conductor layer 6, the second gate conductor layer 8, the second conductor layer 11, the fourth conductor layer 11a, the fourth gate conductor layer 8a, and the third gate conductor layer 6a in the memory block region are connected to external wiring from the periphery of the memory block region.
  • the first conductor layer 4 and the third conductor layer 4a are each independently connected to external wiring from the periphery of the block region.
  • a predetermined voltage is applied to the first conductor layer 4, the first gate conductor layer 6, the second gate conductor layer 8, the second conductor layer 11, the third conductor layer 4a, the third gate conductor layer 6a, the fourth gate conductor layer 8a, and the fourth conductor layer 11a to generate electron-hole pairs in one or both of the first P layer 3 and the second P layer 3a by impact ionization or by using gate induced drain leakage current (GIDL: Gate Induced Drain Leakage, see non-patent document 10), thereby performing a data write operation in which a group of holes, which is a signal charge, remains in one or both of the first P layer 3 and the second P layer 3a.
  • GIDL Gate Induced Drain Leakage
  • a predetermined voltage is applied to the first conductor layer 4, the first gate conductor layer 6, the second gate conductor layer 8, the second conductor layer 11, the third conductor layer 4a, the third gate conductor layer 6a, the fourth gate conductor layer 8a, and the fourth conductor layer 11a to perform a data erasing operation that removes the group of holes, which are signal charges, from one or both of the first P layer 3 and the second P layer 3a.
  • the second and fourth conductor layers 11, 11a connected to the first and second source lines SL1, SL2 can be driven either synchronously or asynchronously if the first to fourth material layers 12, 12a, 13, 13a are all oxide insulating layers. Otherwise, the second and fourth conductor layers 11, 11a are electrically connected, so the second and fourth conductor layers 11, 11a are driven synchronously. In this case, only one of the second and fourth conductor layers 11, 11a may be connected to a drive circuit around the block region.
  • the first and third gate conductor layers 6, 6a are connected to the first and second plate lines PL1, PL2, and the second and fourth gate conductor layers 8, 8a are connected to the first and second word lines WL1, WL2.
  • the first and third gate conductor layers 6, 6a may be connected to the first and second word lines WL1, WL2, and the second and fourth gate conductor layers 8, 8a may be connected to the plate lines PL1, PL2. This also ensures normal dynamic flash memory operation.
  • first and third N + layers 2a, 2aa may be connected to a source line, and the second and fourth N + layers 2b, 2ba may be connected to a bit line.
  • first and third N + layers 2a, 2aa may be formed on the first and second P-layer substrates 1, 1a so as to be connected between adjacent dynamic flash memories.
  • one or both of the first material layer 12 and the second material layer 13 are formed of an oxide insulating layer.
  • one or both of the third material layer 12a and the fourth material layer 13a in FIG. 2A(b) may be formed of an oxide insulating layer.
  • both the first material layer 12 and the second material layer 13 may be formed of the same material layer. In this case, both the first material layer 12 and the second material layer 13 may be formed simultaneously. This is the same for the third material layer 12a and the fourth material layer 13a in FIG. 2A(b).
  • the second and fourth material layers 13 and 13a when the second and fourth material layers 13 and 13a are low-resistance semiconductor layers containing a large amount of impurities, the second and fourth material layers 13 and 13a may be second and fourth N + layers 2b and 2ba extending in the vertical direction. Furthermore, when the second and fourth material layers 13, 13a are oxide insulating layers, the first and third material layers 12, 12a may be integrated with the second and fourth conductor layers 11, 11a by extending in the vertical direction.
  • each of the first and third gate conductor layers 6, 6a may be divided into multiple parts in the vertical direction.
  • Each of the second and fourth gate conductor layers 8, 8a may be divided into multiple parts in the vertical direction.
  • Each of the first and third gate conductor layers 6, 6a may be divided into multiple parts in a planar cross section.
  • Each of the second and fourth gate conductor layers 8, 8a may be divided into multiple parts in a planar cross section.
  • the divided gate conductor layers may be driven synchronously or asynchronously.
  • one of the first and third gate conductor layers and the second and fourth gate conductor layers may be connected to a plate line, and the other may be connected to a word line.
  • one of the first impurity layer and the second impurity layer may be connected to a bit line, and the other may be connected to a source line.
  • one or more two-stage dynamic flash memory cells having the same structure may be stacked on the two-stage dynamic flash memory cell shown in Fig. 2B.
  • the first and third N + layers 2a and 2aa may be formed long in the vertical direction, and the two N + layers (corresponding to the N + layer 2aa in Fig. 2B) may be in contact with each other at the bonding surface.
  • the arrangement of the two-stage dynamic flash memory cells having the first and second P layers 3, 3a in a plan view may be a square lattice, an oblique lattice, a honeycomb, a zigzag, a sawtooth pattern, etc. Alternatively, they may be arranged two-dimensionally in any arrangement to form a memory block region.
  • the first dynamic flash memory cells may be arranged two-dimensionally on a wafer, and a memory block chip having the second dynamic flash memory cells may be bonded to the wafer.
  • two wafers on which the first and second dynamic flash memory cells are formed may be bonded to each other.
  • the P-layer substrates 1, 1a may also use semiconductors, SOI (Silicon On Insulator), well structures, etc.
  • SOI Silicon On Insulator
  • the manufacturing method of this embodiment is characterized in that, on a P-layer substrate 1, from the bottom, there are a first N + layer 2a connected to a first conductor layer 4 which becomes a first bit line BL1, a first P layer 3, a gate insulating layer 5, a first gate conductor layer 6, a second insulating layer 9, a second gate conductor layer 8, a third insulating layer 9, a second N + layer 2b on the top of the P layer 3, a second conductor layer 11 connected to the second N + layer 2b, a first material layer 12 on the second conductor layer, and a second material layer 13 on the second N + layer 2b, a first dynamic flash memory cell, and a second one-stage dynamic flash memory cell having the same structure as the first one-stage dynamic flash memory cell are bonded together so that the first and third material layers 12, 12a and the second and fourth material layers 13, 13a overlap with each other.
  • the first and third material layers 12, 12a and the second and fourth material layers 13, 13a are each formed of an oxide insulating layer such as silicon oxide (SiO2), which can increase the adhesive strength between the single-stage dynamic flash memory cells, thereby obtaining a two-stage dynamic flash memory cell with high mechanical strength.
  • oxide insulating layer such as silicon oxide (SiO2)
  • FIG. 3 shows a case where the second material layer 13 in FIG. 2A is formed of an oxide insulating layer 13A, and the first material layer 12 is formed of a conductor layer 11A in which the second conductor layer 11 in FIG. 2A extends to the upper surface.
  • Two of these one-stage dynamic flash memory cells are bonded together in the same manner as in FIG. 2A and 2B to form a two-stage dynamic flash memory cell.
  • the adhesive strength between the first one-stage dynamic flash memory cell and the second one-stage dynamic flash memory cell which has the same structure as the first one-stage dynamic flash memory cell, is maintained by the adhesive between the oxide insulating layer 13A and the oxide insulating layer corresponding to the oxide insulating layer 13A of the second one-stage dynamic flash memory cell.
  • the first source line SL1 and the second source line SL2 are directly connected, and the connected first source line SL1 and second source line SL2 can be used as a low-resistance common source line for the first one-stage dynamic flash memory cell and the second one-stage dynamic flash memory cell. This makes it possible to improve the performance of the dynamic flash memory.
  • FIG. 4 shows the case where the first material layer 12 and second material layer 13 in FIG. 2A are formed from the second conductor layer 11B and oxide insulating layer 16 from below.
  • Two of these single-stage dynamic flash memory cells are bonded together in the same manner as in FIGS. 2A and 2B to form a two-stage dynamic flash memory cell.
  • An oxide insulating layer 16 is formed on the entire top surface of the single-stage dynamic flash memory cell.
  • Two single-stage dynamic flash memory cells are bonded together with their oxide insulating layers on the entire surface. This results in a bond with high adhesive strength.
  • FIG. 5 shows a case where the first material layer 12 is an oxide insulating layer, and the second material layer 13 is formed by vertically extending the second N + layer 2b to the upper surface position of the first material layer 12.
  • the first material layer 12, which is an oxide insulating layer, contributes to the bonding strength of the two single-stage dynamic flash memory cells.
  • the P layers 3, 3a and the N + layers 2a, 2aa, 2b, 2ba may be made of silicon (Si) or other semiconductor materials.
  • the first gate insulating layer 5 may also be formed of different material layers in the area surrounded by the first gate conductor layer 6 and the area surrounded by the second gate conductor layer 8.
  • the dynamic flash memory operation is also performed in a structure in which the polarity of the conductivity type of each of the first to fourth N + layers 2a, 2b, 2aa, 2ba and the first and second P layers 3, 3a is reversed.
  • the first and second P layers 3, 3a become N layers, so the majority carriers become electrons. Therefore, the electron group generated by impact ionization becomes the signal charge in the memory operation.
  • first and third conductor layers 4, 4a formed on the first and third N + layers 2a, 2aa may be formed on the bottoms of the first and third N + layers 2a, 2aa.
  • the method of manufacturing a memory device using semiconductor elements according to the present invention makes it possible to obtain a dynamic flash memory, which is a high-density, high-performance memory device.
  • First P-layer substrate 1a Second P-layer substrate 2a: First N + layer 2b: Second N + layer 2aa: Third N + layer 2ba: Fourth N + layer 3: first P layer 3a: second P layer 4: first conductor layer 11: second conductor layer 4a: third conductor layer 5: first gate insulating layer 5a: second gate insulating layer 6: first gate conductor layer 8: second gate conductor layer 6a: third gate conductor layer 8a: fourth gate conductor layer 13A, 15: oxide insulating layer 7: second insulating layer 9: third insulating layer 12: first material layer 13: second material layer 12a: third material layer 13a: fourth material layer 15: first insulating layer 16: oxide insulating layers 11A, 11B: conductor layer BL1: first bit line BL2: second bit line PL1: first plate line PL2: second plate line SL1: first source line SL2: second source line

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Abstract

The present invention comprises: a step of forming a first memory cell by forming, from bottom to top, a first N+layer 2a, a first P-layer 3, a first gate insulating layer 5, a first gate conductor layer 6, a second gate conductor layer 8, and a second N+layer 2b on a first P-layer substrate 1, and forming a second conductor layer 11 connected to a second N+layer 2b and extending horizontally, a first material layer 12 on the first conductor layer 11, and a second material layer 13 on the second N+layer 2b; a step of forming a second memory cell having the same structure as the first memory cell on a second P-layer substrate 1a; and forming a two-stage memory cell by aligning the positions of the first material layer 12 and the third material layer 12a, aligning the positions of the second material layer 13 and the fourth material layer 13a, and attaching the first memory cell and the second memory cell to each other. One or both of the first and third material layers 12 and 12a and the second and fourth material layers 13 and 13a can be oxide material layers.

Description

半導体素子を用いたメモリ装置の製造方法Manufacturing method of memory device using semiconductor element

　本発明は、半導体素子を用いたメモリ装置の製造方法に関する。 The present invention relates to a method for manufacturing a memory device using semiconductor elements.

　近年、ＬＳＩ（Large Scale Integration）技術開発において、メモリ素子の高集積化と高性能化が求められている。 In recent years, the development of LSI (Large Scale Integration) technology has created a demand for higher integration and performance of memory elements.

　メモリ素子の高密度化と高性能化が進められている。ＳＧＴ（Surrounding Gate Transistor、特許文献１、非特許文献１を参照）を選択トランジスタとして用いて、キャパシタを接続したＤＲＡＭ（Dynamic Random Access Memory、例えば、非特許文献２を参照）、抵抗変化素子を接続したＰＣＭ（Phase Change Memory、例えば、非特許文献３を参照）、ＲＲＡＭ（Resistive Random Access Memory、例えば、非特許文献４を参照)、電流により磁気スピンの向きを変化させて抵抗を変化させるＭＲＡＭ（Magneto-resistive Random Access Memory、例えば、非特許文献５を参照）などがある。 Memory elements are being made denser and more powerful. Examples include DRAM (Dynamic Random Access Memory; see, for example, Non-Patent Document 2), which uses an SGT (Surrounding Gate Transistor; see Patent Document 1 and Non-Patent Document 1) as a selection transistor and connects a capacitor; PCM (Phase Change Memory; see, for example, Non-Patent Document 3), which connects a resistive variable element; RRAM (Resistive Random Access Memory; see, for example, Non-Patent Document 4); and MRAM (Magneto-resistive Random Access Memory; see, for example, Non-Patent Document 5), which changes the resistance by changing the direction of magnetic spins using electric current.

　また、キャパシタを有しない、１個のＭＯＳトランジスタで構成された、ＤＲＡＭメモリセル（特許文献２、非特許文献６～非特許文献１０を参照）などがある。例えばＮチャネルＭＯＳトランジスタのソース、ドレイン間電流によりチャネル内にインパクトイオン化現象により発生させた正孔群、電子群の内、正孔群の一部、または全てをチャネル内に保持させて論理記憶データ“１”書込みを行う。そして、チャネル内から正孔群を除去して論理記憶データ“０”書込みを行う。このメモリセルでは、共通の選択ワード線に対して、ランダムに“１”書込みのメモリセルと“０”書込みのメモリセルが存在する。選択ワード線にオン電圧が印加されると、この選択ワード線に繋がる選択メモリセルのフローティングボディチャネル電圧はゲート電極とチャネルとの容量結合により大きく変動する。このメモリセルでは、フローティングボディチャネル電圧変動による動作マージンの低下の改善、そして、チャネルに溜められた信号電荷である正孔群の一部が除去されることによるデータ保持特性の低下の改善が課題である。 Also, there are DRAM memory cells (see Patent Document 2, Non-Patent Documents 6 to 10) that are composed of one MOS transistor without a capacitor. For example, a source-drain current of an N-channel MOS transistor generates a group of holes and electrons in the channel by impact ionization, and some or all of the group of holes are retained in the channel to write logical memory data "1". Then, the group of holes is removed from the channel to write logical memory data "0". In this memory cell, there are random memory cells with "1" written and memory cells with "0" written for a common selected word line. When an on-voltage is applied to the selected word line, the floating body channel voltage of the selected memory cell connected to this selected word line fluctuates greatly due to the capacitive coupling between the gate electrode and the channel. In this memory cell, the issues are to improve the decrease in operating margin due to the fluctuation in the floating body channel voltage, and to improve the decrease in data retention characteristics due to the removal of some of the group of holes, which are the signal charges stored in the channel.

　また、ＳＯＩ（Silicon On Insulator）層に、２つのＭＯＳトランジスタを用いて１つのメモリセルを形成したTwin-Transistor MOSトランジスタメモリ素子がある（例えば、特許文献３、４、非特許文献１１を参照）。これらの素子では、２つのＭＯＳトランジスタのフローティングボディチャネルを分ける、ソース、またはドレインとなるＮ+層が基板側にある絶縁層に接して形成されている。このＮ+層により、２つのＭＯＳトランジスタのフローティングボディ チャネルは、電気的に分離される。信号電荷である正孔群は、一方のＭＯＳトランジスタのフローティングボディ チャネルだけに蓄積される。他方のＭＯＳトランジスタは、片方のＭＯＳトランジスタに溜められた信号の正孔群を読みだすためのスイッチとなる。このメモリセルにおいても、信号電荷である正孔群は一つのＭＯＳトランジスタのチャネルに溜められるので、前述の１個のＭＯＳトランジスタよりなるメモリセルと同じく、動作マージンの低下の改善、又はチャネルに溜められた信号電荷である正孔群の一部が除去されることによるデータ保持特性の低下の改善が課題である。 There is also a Twin-Transistor MOS transistor memory element in which one memory cell is formed using two MOS transistors in an SOI (Silicon On Insulator) layer (see, for example, Patent Documents 3 and 4, and Non-Patent Document 11). In these elements, an N + layer, which serves as a source or drain and separates the floating body channels of the two MOS transistors, is formed in contact with an insulating layer on the substrate side. This N + layer electrically separates the floating body channels of the two MOS transistors. A group of holes, which is a signal charge, is accumulated only in the floating body channel of one MOS transistor. The other MOS transistor serves as a switch for reading out the group of holes of the signal accumulated in the other MOS transistor. In this memory cell, the group of holes, which is a signal charge, is accumulated in the channel of one MOS transistor, so that, as in the memory cell consisting of one MOS transistor described above, the problem is to improve the decrease in the operating margin or to improve the decrease in data retention characteristics caused by removing part of the group of holes, which is the signal charge accumulated in the channel.

　また、図６に示す、キャパシタを有しない、ＭＯＳトランジスタで構成された、ダイナミック フラッシュ メモリセル１１１がある（特許文献５、非特許文献１２を参照）。図６（ａ）に示すように、ＳＯＩ基板のＳｉＯ2層１０１上にフローティングボディ半導体母体１０２がある。フローティングボディ半導体母体１０２の両端にソース線ＳＬに接続するＮ+層１０３とビット線ＢＬに接続するＮ+層１０４がある。そして、Ｎ+層１０３に繋がり、且つフローティングボディ半導体母体１０２を覆った第１のゲート絶縁層１０９ａと、Ｎ+層１０４と、スリット絶縁膜１１０を介して第１のゲート絶縁層１０９ａと繋がり、且つフローティングボディ半導体母体１０２を覆った第２のゲート絶縁層１０９ｂとがある。そして、第１のゲート絶縁層１０９ａを覆ってプレート線ＰＬに繋がった第１のゲート導体層１０５ａがあり、第２のゲート絶縁層１０９ｂを覆ってワード線ＷＬに繋がった第２のゲート導体層１０５ｂがある。そして、第１のゲート導体層１０５ａと第２のゲート導体層１０５ｂとの間には、スリット絶縁層１１０がある。これにより、ＤＦＭ（Dynamic Flash Memory）のメモリセル１１１が形成される。なお、ソース線ＳＬがＮ+層１０４に接続し、ビット線ＢＬがＮ+層１０３に接続するように構成してもよい。 Also, as shown in FIG. 6, there is a dynamic flash memory cell 111 composed of a MOS transistor without a capacitor (see Patent Document 5 and Non-Patent Document 12). As shown in FIG. 6(a), there is a floating body semiconductor body 102 on a SiO 2 layer 101 of an SOI substrate. At both ends of the floating body semiconductor body 102, there is an N + layer 103 connected to a source line SL and an N + layer 104 connected to a bit line BL. Then, there is a first gate insulating layer 109a connected to the N + layer 103 and covering the floating body semiconductor body 102, the N + layer 104, and a second gate insulating layer 109b connected to the first gate insulating layer 109a via a slit insulating film 110 and covering the floating body semiconductor body 102. Then, there is a first gate conductor layer 105a that covers the first gate insulating layer 109a and is connected to the plate line PL, and there is a second gate conductor layer 105b that covers the second gate insulating layer 109b and is connected to the word line WL. Then, there is a slit insulating layer 110 between the first gate conductor layer 105a and the second gate conductor layer 105b. This forms a memory cell 111 of a DFM (Dynamic Flash Memory). It is also possible to configure the source line SL to be connected to the N + layer 104, and the bit line BL to be connected to the N + layer 103.

　そして、図６（ａ）に示すように、例えば、Ｎ+層１０３にゼロ電圧、Ｎ+層１０４にプラス電圧を印加し、第１のゲート導体層１０５ａで覆われたフローティングボディ半導体母体１０２よりなる第１のＮチャネルＭＯＳトランジスタ領域を飽和領域で動作させ、第２のゲート導体層１０５ｂで覆われたフローティングボディ半導体母体１０２よりなる第２のＮチャネルＭＯＳトランジスタ領域を線形領域で動作させる。この結果、第２のＮチャネルＭＯＳトランジスタ領域には、ピンチオフ点は存在せずに全面に反転層１０７ｂが形成される。このワード線ＷＬの接続された第２のゲート導体層１０５ｂの下側に形成された反転層１０７ｂは、第１のＮチャネルＭＯＳトランジスタ領域の実質的なドレインとして働く。この結果、第１のＮチャネルＭＯＳトランジスタ領域と、第２のＮチャネルＭＯＳトランジスタ領域との間のチャネル領域の境界領域で電界は最大となり、この領域でインパクトイオン化現象が生じる。そして、図６（ｂ）に示すように、インパクトイオン化現象により生じた電子・正孔群の内の電子群をフローティングボディ半導体母体１０２から除き、そして正孔群１０６の一部、または全てをフローティングボディ半導体母体１０２に保持することによりメモリ書き込み動作が行われる。この状態が論理記憶データ“１”となる。 6(a), for example, a zero voltage is applied to the N + layer 103, and a positive voltage is applied to the N + layer 104, so that the first N-channel MOS transistor region made of the floating body semiconductor body 102 covered with the first gate conductor layer 105a is operated in the saturation region, and the second N-channel MOS transistor region made of the floating body semiconductor body 102 covered with the second gate conductor layer 105b is operated in the linear region. As a result, in the second N-channel MOS transistor region, no pinch-off point exists, and an inversion layer 107b is formed over the entire surface. The inversion layer 107b formed under the second gate conductor layer 105b connected to the word line WL acts as a substantial drain of the first N-channel MOS transistor region. As a result, the electric field becomes maximum in the boundary region of the channel region between the first N-channel MOS transistor region and the second N-channel MOS transistor region, and impact ionization occurs in this region. 6B, the memory write operation is performed by removing the electrons from the electron-hole group generated by the impact ionization phenomenon from the floating body semiconductor body 102 and retaining some or all of the hole group 106 in the floating body semiconductor body 102. This state becomes logical storage data "1".

　そして、図６（ｃ）に示すように、例えばプレート線ＰＬにプラス電圧、ワード線WLと、ビット線ＢＬにゼロ電圧、ソース線ＳＬにマイナス電圧を印加して、正孔群１０６をフローティングボディ半導体母体１０２から除去して消去動作を行う。この状態が論理記憶データ“０”となる。そして、データ読み出しにおいて、プレート線ＰＬに繋がる第１のゲート導体層１０５ａに印加する電圧を、論理記憶データ“１”時のしきい値電圧より高く、且つ論理記憶データ“０”時のしきい値電圧より低く設定することにより、図６（ｄ）に示すように論理記憶データ“０”読み出しでワード線ＷＬの電圧を高くしても電流が流れない特性が得られる。この特性により、メモリセルと比べ、大幅に動作マージンの拡大が図られる。このメモリセルでは、プレート線ＰＬに繋がる第１のゲート導体層１０５ａと、ワード線ＷＬに繋がる第２のゲート導体層１０５ｂをゲートとした第１、第２のＮチャネルＭＯＳトランジスタ領域のチャネルがフローティングボディ半導体母体１０２で繋がっていることにより、ワード線ＷＬに選択パルス電圧が印加された時のフローティングボディ半導体母体１０２の電圧変動が大きく抑圧される。これにより、前述のメモリセルにおいて問題の動作マージンの低下、又はチャネルに溜められた信号電荷である正孔群の一部が除去されることによるデータ保持特性の低下の問題が大きく改善される。今後、本メモリ素子に対して更なる特性改善と高集積化が求められる。 As shown in FIG. 6(c), for example, a positive voltage is applied to the plate line PL, a zero voltage is applied to the word line WL and the bit line BL, and a negative voltage is applied to the source line SL to remove the hole group 106 from the floating body semiconductor body 102 to perform an erase operation. This state becomes logical memory data "0". Then, in data reading, the voltage applied to the first gate conductor layer 105a connected to the plate line PL is set to be higher than the threshold voltage when logical memory data is "1" and lower than the threshold voltage when logical memory data is "0", thereby obtaining a characteristic in which no current flows even if the voltage of the word line WL is increased when reading logical memory data "0", as shown in FIG. 6(d). This characteristic allows a significant expansion of the operating margin compared to memory cells. In this memory cell, the channels of the first and second N-channel MOS transistor regions, which have the first gate conductor layer 105a connected to the plate line PL and the second gate conductor layer 105b connected to the word line WL as their gates, are connected by the floating body semiconductor body 102, so that the voltage fluctuation of the floating body semiconductor body 102 when a selection pulse voltage is applied to the word line WL is greatly suppressed. This greatly improves the problem of the reduction in operating margins in the memory cell described above, or the deterioration of data retention characteristics due to the removal of part of the hole group, which is the signal charge accumulated in the channel. In the future, further characteristic improvements and high integration will be required for this memory element.

特開平２－１８８９６６号公報Japanese Patent Application Laid-Open No. 2-188966 特開平３－１７１７６８号公報Japanese Patent Application Laid-Open No. 3-171768 ＵＳ２００８／０１３７３９４　Ａ１US2008/0137394 A1 ＵＳ２００３／０１１１６８１　Ａ１US2003/0111681 A1 特許第７０５７０３２号公報Japanese Patent No. 7057032

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　ダイナミック フラッシュ メモリセルにおいて、更なる高集積化が求められる。 There is a demand for even higher integration in dynamic flash memory cells.

　上記の課題を解決するために、第１発明に係る半導体素子を用いたメモリ装置の製造方法は、
　第１の不純物層と、第１のゲート導体層と、第２のゲート導体層と、第２の不純物層と、第３の不純物層と、第３のゲート導体層と、第４のゲート導体層と、第４の不純物層とに印加する電圧により、データ書き込み動作と、データ読み出し動作と、データ消去動作を行うメモリ装置の製造方法であって、
　第１の基板上に、下から前記第１の不純物層と、第１の半導体層と、前記第１の半導体層を囲んだ第１のゲート絶縁層と、前記第１のゲート絶縁層の下部を囲んだ第１のゲート導体層と、前記第１のゲート絶縁層の上部を囲んだ第２のゲート導体層と、前記第２の不純物層とを形成する工程と、
　前記第２の不純物層に繋がり、水平方向に伸する第１の導体層と、前記第１の導体層上の第１の材料層と、前記第２の不純物層上の第２の材料層とを形成して、第１のメモリセルを形成する工程と、
　前記第１のメモリセルと同じ構造の第２の基板上の第２のメモリセルを形成する工程と、
　前記第２のメモリセルにおいて、前記第１のメモリセルの前記第１の材料層に対応する第３の材料層と、前記第１のメモリセルの前記第２の材料層に対応する第４の材料層を、前記第１の材料層と前記第３の材料層の位置を合わせ、前記第２の材料層と前記第４の材料層の位置を合わせて、前記第１のメモリセルと前記第２のメモリセルとを貼り合わせた構造よりなる２段メモリセルを形成する工程と、
　を備え、
　前記第１及び第３の材料層と、前記第２及び第４の材料層の一方、又は両方が酸化材料層であることを特徴とする。 In order to solve the above problems, a method for manufacturing a memory device using a semiconductor element according to a first aspect of the present invention includes the steps of:
A method for manufacturing a memory device performing a data write operation, a data read operation, and a data erase operation by applying voltages to a first impurity layer, a first gate conductor layer, a second gate conductor layer, a second impurity layer, a third impurity layer, a third gate conductor layer, a fourth gate conductor layer, and a fourth impurity layer, the method comprising:
forming, from below, on a first substrate, the first impurity layer, a first semiconductor layer, a first gate insulating layer surrounding the first semiconductor layer, a first gate conductor layer surrounding a lower portion of the first gate insulating layer, a second gate conductor layer surrounding an upper portion of the first gate insulating layer, and the second impurity layer;
forming a first conductor layer connected to the second impurity layer and extending in a horizontal direction, a first material layer on the first conductor layer, and a second material layer on the second impurity layer to form a first memory cell;
forming a second memory cell on a second substrate having the same structure as the first memory cell;
forming a second memory cell having a structure in which the first memory cell and the second memory cell are bonded together by forming a third material layer corresponding to the first material layer of the first memory cell and a fourth material layer corresponding to the second material layer of the first memory cell, aligning the positions of the first material layer and the third material layer and aligning the positions of the second material layer and the fourth material layer;
Equipped with
One or both of the first and third material layers and the second and fourth material layers are oxide material layers.

　第２発明は、上記の第１発明において、前記第１の材料層、前記第３の材料層が導体材料層よりなり、前記第２の材料層と前記第３の材料層が酸化絶縁層よりなることを特徴とする。 The second invention is the first invention described above, characterized in that the first material layer and the third material layer are made of conductive material layers, and the second material layer and the third material layer are made of oxide insulating layers.

　第３発明は、上記の第２発明において、前記第１の材料層が前記第１の導体層が上方に伸延した構造であることを特徴とする。 The third invention is the second invention described above, characterized in that the first material layer has a structure in which the first conductor layer extends upward.

　第４発明は、上記の第１発明において、前記第１の材料層が、上方に伸延した前記第１の導体層と、前記第１の導体層上の酸化絶縁層とよりなり、前記第２の材料が、前記第１の導体層が前記第２の不純物層上まで繋がった部分と、前記第１の材料層部分から水平方向に前記酸化絶縁層より形成されることを特徴とする。 The fourth invention is characterized in that in the first invention, the first material layer is made up of the first conductor layer extending upward and an oxide insulating layer on the first conductor layer, and the second material is formed from a portion where the first conductor layer is connected to the second impurity layer and the oxide insulating layer in the horizontal direction from the first material layer portion.

　第５発明は、上記の第１発明において、前記第１の材料層が酸化絶縁層であり、前記第２の材料層が垂直方向に伸延した前記第２の不純物層より形成されることを特徴とする。 The fifth invention is the first invention, characterized in that the first material layer is an oxide insulating layer, and the second material layer is formed from the second impurity layer extending in the vertical direction.

　第６発明は、上記の第１発明において、前記第１及び第３のゲート導体層と、前記第２及び第４のゲート導体層が、垂直断面、又は水平断面で複数に分割して形成されることを特徴とする。 The sixth invention is the first invention, characterized in that the first and third gate conductor layers and the second and fourth gate conductor layers are formed by dividing them into multiple parts in a vertical cross section or a horizontal cross section.

　第７発明は、上記の第１発明において、前記第１及び第３のゲート導体層と、前記第２及び第４のゲート導体層の一方がプレート線に接続し、他方がワード線に接続するように形成することを特徴とする。 The seventh invention is characterized in that, in the first invention, one of the first and third gate conductor layers and the second and fourth gate conductor layers is connected to a plate line, and the other is connected to a word line.

　第８発明は、上記の第１発明において、前記第１の不純物層と第２の不純物層の一方をビット線に接続し、他方をソース線に接続するように形成することを特徴とする。 The eighth invention is the first invention, characterized in that one of the first impurity layer and the second impurity layer is connected to a bit line, and the other is connected to a source line.

第１実施形態に係る２段ダイナミックフラッシュメモリセルの製造方法を説明するための構造図である。1A to 1C are structural diagrams illustrating a method for manufacturing a two-stage dynamic flash memory cell according to a first embodiment; 第１実施形態に係る２段ダイナミックフラッシュメモリセルの製造方法を説明するための構造図である。1A to 1C are structural diagrams illustrating a method for manufacturing a two-stage dynamic flash memory cell according to a first embodiment; 第１実施形態に係る２段ダイナミックフラッシュメモリセルの製造方法を説明するための構造図である。1A to 1C are structural diagrams illustrating a method for manufacturing a two-stage dynamic flash memory cell according to a first embodiment; 第１実施形態に係る２段ダイナミックフラッシュメモリセルの製造方法を説明するための構造図である。1A to 1C are structural diagrams illustrating a method for manufacturing a two-stage dynamic flash memory cell according to a first embodiment; 第２実施形態に係る２段ダイナミックフラッシュメモリセルの製造方法を説明するための構造図である。。11A and 11B are structural diagrams for explaining a method for manufacturing a two-stage dynamic flash memory cell according to a second embodiment. 第３実施形態に係る２段ダイナミックフラッシュメモリセルの製造方法を説明するための構造図である。13A to 13C are structural diagrams for explaining a method for manufacturing a two-stage dynamic flash memory cell according to a third embodiment; 第４実施形態に係る２段ダイナミックフラッシュメモリセルの製造方法を説明するための構造図である。13A to 13C are structural diagrams for explaining a method for manufacturing a two-stage dynamic flash memory cell according to a fourth embodiment; 従来例のダイナミックフラッシュメモリを説明するための図である。FIG. 1 is a diagram for explaining a conventional dynamic flash memory.

　以下、本発明の実施形態に係る、半導体素子を用いたメモリ装置（以後、ダイナミック フラッシュ メモリと呼ぶ）の製造方法について、図面を参照しながら説明する。 Below, a method for manufacturing a memory device using semiconductor elements (hereinafter referred to as dynamic flash memory) according to an embodiment of the present invention will be described with reference to the drawings.

（第１実施形態）
　図１Ａ、図１Ｂ、図２Ａ、図２Ｂを用いて、本発明の第１実施形態に係る２段ダイナミック フラッシュ メモリセルの製造方法を説明する。図１Ａ、図１Ｂにおける、（ａ）図はメモリセルの平面図、（ｂ）図は（ａ）図におけるＸ－Ｘ’線に沿った断面図、（ｃ）図は（ａ）図におけるＹ－Ｙ’線に沿った断面図を示す。図２Ａの（ａ）図は、１段のダイナミック フラッシュ メモリセルの断面図を示す。そして、図２Ａの（ｂ）図は（ａ）図の１段のダイナミック フラッシュ メモリセルとは別の１段のダイナミック フラッシュ メモリセルの断面図を示す。 First Embodiment
A method for manufacturing a two-stage dynamic flash memory cell according to a first embodiment of the present invention will be described with reference to Figures 1A, 1B, 2A, and 2B. In Figures 1A and 1B, (a) shows a plan view of the memory cell, (b) shows a cross-sectional view taken along line XX' in (a), and (c) shows a cross-sectional view taken along line YY' in (a). (a) of Figure 2A shows a cross-sectional view of a one-stage dynamic flash memory cell. And (b) of Figure 2A shows a cross-sectional view of a one-stage dynamic flash memory cell different from the one-stage dynamic flash memory cell in (a).

　図１Ａに示すように、Ｐ層基板１（特許請求の範囲の「第１の基板」の一例である）上に第１のＮ+層２ａ（特許請求の範囲の「第１の不純物層」の一例である）、第１のＰ層３（特許請求の範囲の「第１の半導体層」の一例である）、第２のＮ+層２ｂ（特許請求の範囲の「第２の不純物層」の一例である）を形成する。第１のＮ+層２ａの一部の上面にあって、平面視において、Ｙ－Ｙ’線方向に伸延する第１の導体層４を形成する。第１のＰ層基板１、第１のＮ+層２ａ、第１の金属層４を覆って第１の絶縁層１５を形成する。第１のＰ層３を囲んで第１のゲート絶縁層５（特許請求の範囲の「第１のゲート絶縁層」の一例である）を形成する。第１のゲート絶縁層５を囲んで、下から第１のゲート導体層６（特許請求の範囲の「第１のゲート導体層」の一例である）、第２の絶縁層７、第２のゲート導体層８（特許請求の範囲の「第２のゲート導体層」の一例である）を形成する。第２のゲート導体層８上にあって、第２のＮ+層２ｂの外周を囲んで、第３の絶縁層９を形成する。なお、第１のＰ層３は、少なくとも、第１のゲート導体層６、第２の絶縁層７、第２のゲート導体層８，第３の絶縁層９を形成した後に、例えばエピタキシャル結晶成長法、ＭＳＣ（Metal-Assisted Solid-Phase Crystallization）法、ＭＩＬＣ（Metal Induced Lateral Crystallization）法などにより形成してもよい。また、第１のゲート導体層６、第２のゲート導体層８は、第１のＰ層３を形成した後にダミーゲート層を除去して、そこに生じた空間に第１のゲート導体層６、第２のゲート導体層８の材料層を埋め込んで形成してもよい。また、第１のＰ層３は、単結晶Ｐ型半導体層をリソグラフィ法とエッチング法を用いて形成してもよい。 As shown in FIG. 1A, a first N + layer 2a (an example of a "first impurity layer" in the claims), a first P layer 3 (an example of a "first semiconductor layer" in the claims), and a second N + layer 2b (an example of a "second impurity layer" in the claims) are formed on a P layer substrate 1 (an example of a "first substrate" in the claims). A first conductor layer 4 is formed on a part of the upper surface of the first N + layer 2a and extending in the Y-Y' line direction in a plan view. A first insulating layer 15 is formed covering the first P layer substrate 1, the first N + layer 2a, and the first metal layer 4. A first gate insulating layer 5 (an example of a "first gate insulating layer" in the claims) is formed surrounding the first P layer 3. A first gate conductor layer 6 (an example of the "first gate conductor layer" in the claims), a second insulating layer 7, and a second gate conductor layer 8 (an example of the "second gate conductor layer" in the claims) are formed from below, surrounding the first gate insulating layer 5. A third insulating layer 9 is formed on the second gate conductor layer 8, surrounding the outer periphery of the second N + layer 2b. The first P layer 3 may be formed by, for example, an epitaxial crystal growth method, a Metal-Assisted Solid-Phase Crystallization (MSC) method, or a Metal-Induced Lateral Crystallization (MILC) method after forming at least the first gate conductor layer 6, the second insulating layer 7, the second gate conductor layer 8, and the third insulating layer 9. The first gate conductor layer 6 and the second gate conductor layer 8 may be formed by removing the dummy gate layer after forming the first P layer 3, and filling the resulting space with material layers for the first gate conductor layer 6 and the second gate conductor layer 8. The first P layer 3 may be formed by forming a single crystal P-type semiconductor layer using lithography and etching.

　次に、図１Ｂに示すように、第３の絶縁層９上にあって、Ｎ+層２ｂを囲んで第２の導体層１１（特許請求の範囲の「第１の導体層」の一例である）、第１の材料層１２（特許請求の範囲の「第１の材料層」の一例である）と、Ｎ+層２ｂ上に第２の材料層１３（特許請求の範囲の「第２の材料層」の一例である）を形成する。第１の材料層１２と、第２の材料層１３との一方、または両方は、例えば酸化シリコン（ＳｉＯ２）などの酸化絶縁層で形成される。第１の導体層４は第１のビット線（ＢＬ１）に接続され、第１のゲート導体層６は第１のプレート線ＰＬ１に接続され、第２のゲート導体層８は第１のワード線ＷＬ１に接続され、第２の導体層１１は第１のソース線ＳＬ１に接続される。これにより、１段ダイナミック フラッシュ メモリセル（特許請求の範囲の「第１のメモリセル」の一例である）がＰ層基板１上に形成される。図１Ａ、図１Ｂでは単一のメモリセルのみを示しているが、実際には複数のメモリセルが２次元状に同時に形成される（他の実施形態でも同様である）。１段ダイナミック フラッシュ メモリセルが２次元状に配置されたメモリブロック領域では、そのメモリブロック内の第１のゲート導体層６、第２のゲート導体層８、第２の導体層１１は、メモリブロック領域内で共通に繋がって形成される。 Next, as shown in FIG. 1B, a second conductor layer 11 (an example of the "first conductor layer" in the claims) is formed on the third insulating layer 9 and surrounding the N + layer 2b, a first material layer 12 (an example of the "first material layer" in the claims), and a second material layer 13 (an example of the "second material layer" in the claims) is formed on the N + layer 2b. One or both of the first material layer 12 and the second material layer 13 are formed of an oxide insulating layer such as silicon oxide (SiO2). The first conductor layer 4 is connected to the first bit line (BL1), the first gate conductor layer 6 is connected to the first plate line PL1, the second gate conductor layer 8 is connected to the first word line WL1, and the second conductor layer 11 is connected to the first source line SL1. As a result, a one-stage dynamic flash memory cell (an example of the "first memory cell" in the claims) is formed on the P-layer substrate 1. 1A and 1B show only a single memory cell, but in reality, a plurality of memory cells are formed two-dimensionally at the same time (this is the same in other embodiments). In a memory block region where one-stage dynamic flash memory cells are arranged two-dimensionally, the first gate conductor layer 6, the second gate conductor layer 8, and the second conductor layer 11 in the memory block are formed to be commonly connected within the memory block region.

　図２Ａ（ａ）、（ｂ）に２つの１段ダイナミック フラッシュ メモリセルの断面を示す。図２Ａ（ａ）は図１Ａ、１Ｂで示した工程により形成した１段ダイナミック フラッシュ メモリセルの断面である。図２Ａ（ｂ）は図２Ａ（ａ）と同じ工程により形成し、図２Ａ（ａ）と同じ構造の別の１段ダイナミック フラッシュ メモリセルの断面である。図２Ａ（ｂ）のＰ層基板１ａ（特許請求の範囲の「第２の基板」の一例である）は図２Ａ（ａ）のＰ層基板１に対応する。同じく、第３のＮ+層２ａａは、第１のＮ+層２ａに対応している。そして、第２のＰ層３ａは第１のＰ層３に対応し、第４のＮ+層２ｂａは第２のＮ+層２ｂに対応し、第３の導体層４ａは第１の導体層４に対応し、第４の絶縁層1５ａは第１の絶縁層１５に対応し、第２のゲート絶縁層５ａは第１のゲート絶縁層５に対応し、第３のゲート導体層６ａは第１のゲート導体層６に対応し、第５の絶縁層７ａは第２の絶縁層７、第４のゲート導体層８ａは第２のゲート導体層８に対応し、第６の絶縁層９ａは第３の絶縁層９に対応し、第４の導体層１１ａは第２の導体層１１に対応し、第３の材料層１２ａ（特許請求の範囲の「第３の材料層」の一例である）は第１の材料層１２に対応し、第４の材料層１３ａ（特許請求の範囲の「第４の材料層」の一例である）は第２の材料層１３に対応している。そして、第３の導体層４ａは第２のビット線（ＢＬ２）に接続され、第３のゲート導体層６ａは第２のプレート線ＰＬ２に接続され、第４のゲート導体層８ａは第２のワード線ＷＬ２に接続され、第４の導体層１１ａは第２のソース線ＳＬ１に接続される。そして、図２Ａ（ｂ）の１段ダイナミック フラッシュ メモリセル（特許請求の範囲の「第２のメモリセル」の一例である）を上下逆にして、図２Ａ（ａ）の１段ダイナミック フラッシュ メモリセルと、第１の材料層１２と第３の材料層１２ａとが重なり、同じく第２の材料層１３と第４の材料層１３ａとが重なるようにして、貼り合わせる。第１の材料層１２と、第２の材料層１３との一方、または両方に、例えば酸化シリコン（ＳｉＯ２）などの酸化絶縁層を用いることにより、２つの１段ダイナミック フラッシュ メモリセルの貼り合わせ強度を大きくできる。そして、第２のＰ層基板１ａを上面より所定の厚さにエッチングして薄くする。 Figures 2A(a) and (b) show cross sections of two single-stage dynamic flash memory cells. Figure 2A(a) is a cross section of a single-stage dynamic flash memory cell formed by the process shown in Figures 1A and 1B. Figure 2A(b) is a cross section of another single-stage dynamic flash memory cell formed by the same process as Figure 2A(a) and having the same structure as Figure 2A(a). The P-layer substrate 1a (an example of the "second substrate" in the claims) in Figure 2A(b) corresponds to the P-layer substrate 1 in Figure 2A(a). Similarly, the third N + layer 2aa corresponds to the first N + layer 2a. The second P layer 3a corresponds to the first P layer 3, and the fourth N + layer 2ba corresponds to the second N + layer 4a. + layer 2b, the third conductor layer 4a corresponds to the first conductor layer 4, the fourth insulating layer 15a corresponds to the first insulating layer 15, the second gate insulating layer 5a corresponds to the first gate insulating layer 5, the third gate conductor layer 6a corresponds to the first gate conductor layer 6, the fifth insulating layer 7a corresponds to the second insulating layer 7, the fourth gate conductor layer 8a corresponds to the second gate conductor layer 8, the sixth insulating layer 9a corresponds to the third insulating layer 9, the fourth conductor layer 11a corresponds to the second conductor layer 11, the third material layer 12a (an example of the "third material layer" in the claims) corresponds to the first material layer 12, and the fourth material layer 13a (an example of the "fourth material layer" in the claims) corresponds to the second material layer 13. The third conductor layer 4a is connected to the second bit line (BL2), the third gate conductor layer 6a is connected to the second plate line PL2, the fourth gate conductor layer 8a is connected to the second word line WL2, and the fourth conductor layer 11a is connected to the second source line SL1. The one-stage dynamic flash memory cell of FIG. 2A(b) (an example of the "second memory cell" in the claims) is turned upside down and bonded to the one-stage dynamic flash memory cell of FIG. 2A(a) such that the first material layer 12 and the third material layer 12a overlap, and similarly the second material layer 13 and the fourth material layer 13a overlap. By using an oxide insulating layer such as silicon oxide (SiO2) for one or both of the first material layer 12 and the second material layer 13, the bonding strength of the two one-stage dynamic flash memory cells can be increased. Then, the second P-layer substrate 1a is thinned to a predetermined thickness by etching from the upper surface.

　図２Ｂに、図２Ａ（ｂ）の１段ダイナミック フラッシュ メモリセルを上下逆にして、図２Ａ（ａ）の１段ダイナミック フラッシュ メモリセルと、第１の材料層１２と第３の材料層１２ａとが重なり、同じく第２の材料層１３と第４の材料層１３ａとが重なるようにして、貼り合わせた状態を示す。そして、第２のＰ層基板１ａを上面より所定の厚さにエッチングして薄くしている。これにより、２段ダイナミック フラッシュ メモリセル（特許請求の範囲の「２段メモリセル」の一例である）が形成される。実際には、この２段ダイナミック フラッシュ メモリセルがＰ層基板１上に２次元状に形成される。２次元状に配置されたブロック領域では、そのブロック領域内の第１のゲート導体層６、第２のゲート導体層８、第２の導体層１１、第４の導体層１１ａ、第４のゲート導体層８ａ、第３ゲートの導体層６ａは、ブロック領域の各２段ダイナミック フラッシュ メモリセル間で共通に繋がって形成される。そして、メモリブロック領域内の第１のゲート導体層６、第２のゲート導体層８、第２の導体層１１、第４の導体層１１ａ、第４のゲート導体層８ａ、第３ゲートの導体層６ａは、メモリブロック領域の周辺部より外部配線に接続する。そして、第１の導体層４、第３の導体層４ａは、それぞれ独立にブロック領域の周辺部より外部配線に接続する。 2B shows the state where the single-stage dynamic flash memory cell of FIG. 2A(b) is turned upside down and bonded to the single-stage dynamic flash memory cell of FIG. 2A(a) such that the first material layer 12 and the third material layer 12a overlap, and similarly the second material layer 13 and the fourth material layer 13a overlap. The second P-layer substrate 1a is then etched from the top surface to a predetermined thickness to form a two-stage dynamic flash memory cell (an example of the "two-stage memory cell" in the claims). In practice, this two-stage dynamic flash memory cell is formed two-dimensionally on the P-layer substrate 1. In the block region arranged two-dimensionally, the first gate conductor layer 6, the second gate conductor layer 8, the second conductor layer 11, the fourth conductor layer 11a, the fourth gate conductor layer 8a, and the third gate conductor layer 6a in the block region are formed to be commonly connected between the two-stage dynamic flash memory cells in the block region. The first gate conductor layer 6, the second gate conductor layer 8, the second conductor layer 11, the fourth conductor layer 11a, the fourth gate conductor layer 8a, and the third gate conductor layer 6a in the memory block region are connected to external wiring from the periphery of the memory block region. The first conductor layer 4 and the third conductor layer 4a are each independently connected to external wiring from the periphery of the block region.

　図２Ｂに示した２段ダイナミック フラッシュ メモリセルにおいて、第１の導体層４と、第１のゲート導体層６と、第２のゲート導体層８と、第２の導体層１１と、第３の導体層４ａ、第３のゲート導体層６ａと、第４のゲート導体層８ａと、第４の導体層１１ａに所定の電圧を印加して、第１のＰ層３と、第２のＰ層３ａの一方、または両方にインパクトイオン化現象により、またはゲート誘起ドレインリーク電流（ＧＩＤＬ:Gate Induced Drain Leakage、非特許文献１０を参照）を用いて電子・正孔対を発生させて、信号電荷である正孔群を第１のＰ層３と第２のＰ層３ａの一方、または両方に残存させるデータ書き込み動作を行う。そして、第１の導体層４と、第１のゲート導体層６と、第２のゲート導体層８と、第２の導体層１１と、第３の導体層４ａと、第３のゲート導体層６ａと、第４のゲート導体層８ａと、第４の導体層１１ａに所定の電圧を印加して、信号電荷である正孔群を第１のＰ層３と第２のＰ層３ａの一方または両方から除去するデータ消去動作を行う。 In the two-stage dynamic flash memory cell shown in FIG. 2B, a predetermined voltage is applied to the first conductor layer 4, the first gate conductor layer 6, the second gate conductor layer 8, the second conductor layer 11, the third conductor layer 4a, the third gate conductor layer 6a, the fourth gate conductor layer 8a, and the fourth conductor layer 11a to generate electron-hole pairs in one or both of the first P layer 3 and the second P layer 3a by impact ionization or by using gate induced drain leakage current (GIDL: Gate Induced Drain Leakage, see non-patent document 10), thereby performing a data write operation in which a group of holes, which is a signal charge, remains in one or both of the first P layer 3 and the second P layer 3a. Then, a predetermined voltage is applied to the first conductor layer 4, the first gate conductor layer 6, the second gate conductor layer 8, the second conductor layer 11, the third conductor layer 4a, the third gate conductor layer 6a, the fourth gate conductor layer 8a, and the fourth conductor layer 11a to perform a data erasing operation that removes the group of holes, which are signal charges, from one or both of the first P layer 3 and the second P layer 3a.

　第１及び第２のソース線ＳＬ１、ＳＬ２に繋がる第２及び第４の導体層１１、１１ａは、第１乃至第４の材料層１２、１２ａ、１３、１３ａ全てが酸化絶縁層である場合は、同期、及び非同期のどちらでも駆動できる。それ以外では、第２及び第４の導体層１１、１１ａは電気的に繋がっているので、第２及び第４の導体層１１、１１ａは同期駆動となる。この場合は、第２及び第４の導体層１１、１１ａの片方だけをブロック領域の周辺で駆動回路と接続してもよい。 The second and fourth conductor layers 11, 11a connected to the first and second source lines SL1, SL2 can be driven either synchronously or asynchronously if the first to fourth material layers 12, 12a, 13, 13a are all oxide insulating layers. Otherwise, the second and fourth conductor layers 11, 11a are electrically connected, so the second and fourth conductor layers 11, 11a are driven synchronously. In this case, only one of the second and fourth conductor layers 11, 11a may be connected to a drive circuit around the block region.

　なお、図２Ａでは、第１及びの第３のゲート導体層６、６ａは、第１及び第２のプレート線ＰＬ１、ＰＬ２に接続し、第２及び第４のゲート導体層８、８ａは第１及び第２のワード線ＷＬ１、ＷＬ２に接続していた。これに対し、第１及びの第３のゲート導体層６、６ａは、第１及び第２のワード線ＷＬ１、ＷＬ２に接続し、第２及び第４のゲート導体層８、８ａはプレート線ＰＬ１、ＰＬ２に接続してもよい。これによっても、正常なダイナミック フラッシュ メモリ動作がなされる。 In FIG. 2A, the first and third gate conductor layers 6, 6a are connected to the first and second plate lines PL1, PL2, and the second and fourth gate conductor layers 8, 8a are connected to the first and second word lines WL1, WL2. Alternatively, the first and third gate conductor layers 6, 6a may be connected to the first and second word lines WL1, WL2, and the second and fourth gate conductor layers 8, 8a may be connected to the plate lines PL1, PL2. This also ensures normal dynamic flash memory operation.

　また、第１及び第３のＮ+層２ａ、２ａａはソース線に接続し、第２及び第４のＮ+層２ｂ、２ｂａはビット線に接続してもよい。この場合、第１及び第３のＮ+層２ａ、２ａａは、第１及び第２のＰ層基板１，１ａ上で、隣接ダイナミック フラッシュ メモリ間で繋がって形成されてもよい。 Also, the first and third N + layers 2a, 2aa may be connected to a source line, and the second and fourth N + layers 2b, 2ba may be connected to a bit line. In this case, the first and third N + layers 2a, 2aa may be formed on the first and second P-layer substrates 1, 1a so as to be connected between adjacent dynamic flash memories.

　また、図１Ｂにおいて、第１の材料層１２と、第２の材料層１３との一方、または両方は酸化絶縁層で形成されると述べた。同様に、図２Ａ（ｂ）における第３の材料層１２ａと、第４の材料層１３ａの一方または両方は酸化絶縁層で形成されてもよい。第１の材料層１２と、第２の材料層１３の両方が酸化絶縁層である場合は、第１の材料層１２と、第２の材料層１３の両方が同じ材料層で形成してもよい。この場合は、第１の材料層１２と、第２の材料層１３の両方が同時に形成されてもよい。このことは、図２Ａ（ｂ）における第３の材料層１２ａと、第４の材料層１３ａについても同じである。また、第２及び第４の材料層１３、１３ａが不純物を多く含んだ低抵抗半導体層である場合は、第２及び第４の材料層１３、１３ａは、垂直方向に伸延した第２及び第４のＮ+層２ｂ、２ｂａであってもよい。また、第２及び第４の材料層１３、１３ａが酸化絶縁層である場合、第１及び第３の材料層１２、１２ａは第２及び第４の導体層１１、１１ａが垂直方向に伸びて一体化させてもよい。 Also, in FIG. 1B, it has been stated that one or both of the first material layer 12 and the second material layer 13 are formed of an oxide insulating layer. Similarly, one or both of the third material layer 12a and the fourth material layer 13a in FIG. 2A(b) may be formed of an oxide insulating layer. When both the first material layer 12 and the second material layer 13 are oxide insulating layers, both the first material layer 12 and the second material layer 13 may be formed of the same material layer. In this case, both the first material layer 12 and the second material layer 13 may be formed simultaneously. This is the same for the third material layer 12a and the fourth material layer 13a in FIG. 2A(b). Also, when the second and fourth material layers 13 and 13a are low-resistance semiconductor layers containing a large amount of impurities, the second and fourth material layers 13 and 13a may be second and fourth N + layers 2b and 2ba extending in the vertical direction. Furthermore, when the second and fourth material layers 13, 13a are oxide insulating layers, the first and third material layers 12, 12a may be integrated with the second and fourth conductor layers 11, 11a by extending in the vertical direction.

　また、図２Ａにおいて、第１及び第３のゲート導体層６、６ａの各々は垂直方向に複数に分割されていてもよい。第２及び第４のゲート導体層８、８ａの各々は垂直方向に複数に分割されていてもよい。また、第１及び第３のゲート導体層６、６ａの各々は平面断面において複数に分割されていてもよい。第２及び第４のゲート導体層８、８ａの各々は平面断面において、複数に分割されていてもよい。そして、分割されたゲート導体層は同期、または非同期で駆動されてもよい。 In addition, in FIG. 2A, each of the first and third gate conductor layers 6, 6a may be divided into multiple parts in the vertical direction. Each of the second and fourth gate conductor layers 8, 8a may be divided into multiple parts in the vertical direction. Each of the first and third gate conductor layers 6, 6a may be divided into multiple parts in a planar cross section. Each of the second and fourth gate conductor layers 8, 8a may be divided into multiple parts in a planar cross section. The divided gate conductor layers may be driven synchronously or asynchronously.

　また、前記第１及び第３のゲート導体層と、前記第２及び第４のゲート導体層の一方をプレート線に接続し、他方をワード線に接続してもよい。また、前記第１の不純物層と第２の不純物層の一方をビット線に接続し、他方をソース線に接続してもよい。 Also, one of the first and third gate conductor layers and the second and fourth gate conductor layers may be connected to a plate line, and the other may be connected to a word line. Also, one of the first impurity layer and the second impurity layer may be connected to a bit line, and the other may be connected to a source line.

　また、図２Ｂに示した２段ダイナミック フラッシュ メモリセルの上に、同じ構造の２段ダイナミック フラッシュ メモリセルを１つ又は複数個積層させてもよい。これにより、多段ダイナミック フラッシュ メモリセルが形成される。この場合、第１及び第３のＮ+層２ａ、２ａａを垂直方向に長く形成し、貼り合わせ面で、両者のＮ+層（図２ＢのＮ+層２ａａがこれに対応する）が接触する構造を有してもよい。 Also, one or more two-stage dynamic flash memory cells having the same structure may be stacked on the two-stage dynamic flash memory cell shown in Fig. 2B. This forms a multi-stage dynamic flash memory cell. In this case, the first and third N + layers 2a and 2aa may be formed long in the vertical direction, and the two N + layers (corresponding to the N + layer 2aa in Fig. 2B) may be in contact with each other at the bonding surface.

　また、第１及び第２のＰ層３、３ａを有する２段ダイナミック フラッシュ メモリセルの平面視での配置は、正方格子、斜方格子、ハニカム、ジグザグ、のこぎり状などであってよい。又は任意の配置で２次元状に配列させてメモリブロック領域を形成しても良い。 The arrangement of the two-stage dynamic flash memory cells having the first and second P layers 3, 3a in a plan view may be a square lattice, an oblique lattice, a honeycomb, a zigzag, a sawtooth pattern, etc. Alternatively, they may be arranged two-dimensionally in any arrangement to form a memory block region.

　また、第１のダイナミック フラッシュ メモリセルをウエハ上に２次元状に配列させ、そして、第２のダイナミック フラッシュ メモリセルを有したメモリブロックのチップを貼り合わせてもよい。また、第１及び第２のダイナミック フラッシュ メモリセルを形成した２つのウエハを貼り合わせてもよい。 Alternatively, the first dynamic flash memory cells may be arranged two-dimensionally on a wafer, and a memory block chip having the second dynamic flash memory cells may be bonded to the wafer. Alternatively, two wafers on which the first and second dynamic flash memory cells are formed may be bonded to each other.

　また、Ｐ層基板１、１ａは半導体、ＳＯＩ（Silicon On Insulator）、ウエル構造などを用いてもよい。 The P-layer substrates 1, 1a may also use semiconductors, SOI (Silicon On Insulator), well structures, etc.

　本実施形態によれば、下記のような特徴を有する。
　本実施形態の製造方法の特徴は、Ｐ層基板１上に下から第１のビット線ＢＬ１となる第１の導体層４に繋がる第１のＮ+層２ａ、第１のＰ層３、ゲート絶縁層５、第１のゲート導体層６、第２の絶縁層９、第２のゲート導体層８、第３の絶縁層９、、Ｐ層３の頂部の第２のＮ+層２ｂ、第２のＮ+層２ｂに繋がる第２の導体層１１、第２の導体層上の第１の材料層１２と、第２のＮ+層２ｂ上に第２の材料層１３を有する第１のダイナミック フラッシュ メモリセルと、第１の１段ダイナミック フラッシュ メモリセルと同じ構造の第２の１段ダイナミック フラッシュ メモリセルを、それぞれの第１及び第３の材料層１２，１２ａと、第２及び第４の材料層１３、１３ａとが重なるように貼り合わせた。そして、第１及び第３の材料層１２、１２ａと、第２及び第４の材料層１３、１３ａの一方または両方は、例えば酸化シリコン（ＳｉＯ２）などの酸化絶縁層で形成した。これにより、１段ダイナミック フラッシュ メモリセル間の接着強度を高めることができる。これにより、高い機械的強度の２段ダイナミック フラッシュ メモリセルが得られる。 This embodiment has the following features.
The manufacturing method of this embodiment is characterized in that, on a P-layer substrate 1, from the bottom, there are a first N + layer 2a connected to a first conductor layer 4 which becomes a first bit line BL1, a first P layer 3, a gate insulating layer 5, a first gate conductor layer 6, a second insulating layer 9, a second gate conductor layer 8, a third insulating layer 9, a second N + layer 2b on the top of the P layer 3, a second conductor layer 11 connected to the second N + layer 2b, a first material layer 12 on the second conductor layer, and a second material layer 13 on the second N + layer 2b, a first dynamic flash memory cell, and a second one-stage dynamic flash memory cell having the same structure as the first one-stage dynamic flash memory cell are bonded together so that the first and third material layers 12, 12a and the second and fourth material layers 13, 13a overlap with each other. The first and third material layers 12, 12a and the second and fourth material layers 13, 13a are each formed of an oxide insulating layer such as silicon oxide (SiO2), which can increase the adhesive strength between the single-stage dynamic flash memory cells, thereby obtaining a two-stage dynamic flash memory cell with high mechanical strength.

　図３に、図２Ａにおける第２の材料層１３が、酸化絶縁層１３Ａで形成され、第１の材料層１２が、図２Ａにおける第２の導体層１１が上面まで伸延した導体層１１Ａが形成される場合を示す。この１段ダイナミック フラッシュ メモリセルの２つを、図２A、２Bと同様に貼り合わせて２段ダイナミック フラッシュ メモリセルを形成する。この場合、第１の１段ダイナミック フラッシュ メモリセルと同じ構造の第２の１段ダイナミック フラッシュ メモリセルとの接着強度は、酸化絶縁層１３Ａと、第２の１段ダイナミック フラッシュ メモリセルの酸化絶縁層１３Ａに対応する酸化絶縁層との接着で保持される。これにより、第１のソース線ＳＬ１と第２のソース線ＳＬ２が直接つながることにより、繋がった第１のソース線ＳＬ１と第２のソース線ＳＬ２を第１の１段ダイナミック フラッシュ メモリセルと第２の１段ダイナミック フラッシュ メモリセルの低抵抗共通ソース線とすることが出来る。これにより、ダイナミック フラッシュ メモリの高性能化を図ることが出来る。 3 shows a case where the second material layer 13 in FIG. 2A is formed of an oxide insulating layer 13A, and the first material layer 12 is formed of a conductor layer 11A in which the second conductor layer 11 in FIG. 2A extends to the upper surface. Two of these one-stage dynamic flash memory cells are bonded together in the same manner as in FIG. 2A and 2B to form a two-stage dynamic flash memory cell. In this case, the adhesive strength between the first one-stage dynamic flash memory cell and the second one-stage dynamic flash memory cell, which has the same structure as the first one-stage dynamic flash memory cell, is maintained by the adhesive between the oxide insulating layer 13A and the oxide insulating layer corresponding to the oxide insulating layer 13A of the second one-stage dynamic flash memory cell. As a result, the first source line SL1 and the second source line SL2 are directly connected, and the connected first source line SL1 and second source line SL2 can be used as a low-resistance common source line for the first one-stage dynamic flash memory cell and the second one-stage dynamic flash memory cell. This makes it possible to improve the performance of the dynamic flash memory.

　図４に、図２Ａにおける第１の材料層１２と、第２の材料層１３とが、下から第２の導体層１１Ｂと酸化絶縁層１６より形成される場合を示す。この１段ダイナミック フラッシュ メモリセルの２つが、図２A、２Bと同様に貼り合わせられて２段ダイナミック フラッシュ メモリセルが形成される。１段ダイナミック フラッシュ メモリセルの上面全体に酸化絶縁層１６が形成される。全面の酸化絶縁層同志で２つの１段ダイナミック フラッシュ メモリセルが貼り合わせられる。これにより、接着強度の大きい貼り合わせがなされる。 FIG. 4 shows the case where the first material layer 12 and second material layer 13 in FIG. 2A are formed from the second conductor layer 11B and oxide insulating layer 16 from below. Two of these single-stage dynamic flash memory cells are bonded together in the same manner as in FIGS. 2A and 2B to form a two-stage dynamic flash memory cell. An oxide insulating layer 16 is formed on the entire top surface of the single-stage dynamic flash memory cell. Two single-stage dynamic flash memory cells are bonded together with their oxide insulating layers on the entire surface. This results in a bond with high adhesive strength.

　図５に第１の材料層１２が酸化絶縁層であり、第２の材料層１３が、垂直方向に第２のＮ+層２ｂが第１の材料層１２の上面位置まで伸延して形成されている場合を示す。この１段ダイナミック フラッシュ メモリセルの２つが、図２A、２Bと同様に貼り合わされて２段ダイナミック フラッシュ メモリセルが形成される。酸化絶縁層である第１の材料層１２が２つの１段ダイナミック フラッシュ メモリセルの貼り合わせ強度に寄与する。 5 shows a case where the first material layer 12 is an oxide insulating layer, and the second material layer 13 is formed by vertically extending the second N + layer 2b to the upper surface position of the first material layer 12. Two of these single-stage dynamic flash memory cells are bonded together in the same manner as in FIGS. 2A and 2B to form a two-stage dynamic flash memory cell. The first material layer 12, which is an oxide insulating layer, contributes to the bonding strength of the two single-stage dynamic flash memory cells.

（その他の実施形態）
　なお、本実施形態における、Ｐ層３、３ａ、Ｎ+層２ａ、２ａａ、２ｂ、２ｂａは、シリコン（Ｓｉ）、又は他の半導体材料であってもよい。 Other Embodiments
In this embodiment, the P layers 3, 3a and the N + layers 2a, 2aa, 2b, 2ba may be made of silicon (Si) or other semiconductor materials.

　また、第１のゲート絶縁層５は、第１のゲート導体層６で囲まれた領域と、第２のゲート導体層８で囲まれた領域で異る材料層で形成されてもよい。 The first gate insulating layer 5 may also be formed of different material layers in the area surrounded by the first gate conductor layer 6 and the area surrounded by the second gate conductor layer 8.

　また、図１において、第１乃至第４のＮ+層２ａ、２ｂ、２ａａ、２ｂａ、第１及び第２のＰ層３、３ａのそれぞれの導電型の極性を逆にした構造においても、ダイナミック フラッシュ メモリ動作がなされる。この場合、第１及び第２のＰ層３，３ａがＮ層になるので、多数キャリアは電子になる。従って、インパクトイオン化により生成された電子群がメモリ動作における信号電荷になる。 1, the dynamic flash memory operation is also performed in a structure in which the polarity of the conductivity type of each of the first to fourth N + layers 2a, 2b, 2aa, 2ba and the first and second P layers 3, 3a is reversed. In this case, the first and second P layers 3, 3a become N layers, so the majority carriers become electrons. Therefore, the electron group generated by impact ionization becomes the signal charge in the memory operation.

　また、第１及び第３のＮ+層２ａ、２ａａ上に形成された第１及び第３の導体層４、４ａは、第１及び第３のＮ+層２ａ、２ａａの底部に形成されてもよい。 Furthermore, the first and third conductor layers 4, 4a formed on the first and third N + layers 2a, 2aa may be formed on the bottoms of the first and third N + layers 2a, 2aa.

　また、本発明は、本発明の広義の精神と範囲を逸脱することなく、様々な実施形態及び変形が可能とされるものである。また、上述した各実施形態は、本発明の一実施例を説明するためのものであり、本発明の範囲を限定するものではない。上記実施例及び変形例は任意に組み合わせることができる。さらに、必要に応じて上記実施形態の構成要件の一部を除いても本発明の技術思想の範囲内となる。 Furthermore, the present invention allows for various embodiments and modifications without departing from the broad spirit and scope of the present invention. Furthermore, each of the above-described embodiments is intended to explain one example of the present invention, and does not limit the scope of the present invention. The above-described embodiments and modifications can be combined in any manner. Furthermore, even if some of the constituent elements of the above-described embodiments are omitted as necessary, they will still fall within the scope of the technical concept of the present invention.

　本発明に係る、半導体素子を用いたメモリ装置の製造方法によれば、高密度で、かつ高性能のメモリ装置であるダイナミック フラッシュ メモリが得られる。 The method of manufacturing a memory device using semiconductor elements according to the present invention makes it possible to obtain a dynamic flash memory, which is a high-density, high-performance memory device.

１：第１のＰ層基板
１ａ：第２のＰ層基板
２ａ：第１のＮ+層
２ｂ：第２のＮ+層
２ａａ：第３のＮ+層
２ｂａ：第４のＮ+層
３：第１のＰ層
３ａ：第２のＰ層
４：第１の導体層
１１：第２の導体層
４ａ：第３の導体層
５：第１のゲート絶縁層
５ａ：第２のゲート絶縁層
６：第１のゲート導体層
８：第２のゲート導体層
６ａ：第３のゲート導体層
８ａ：第４のゲート導体層
１３Ａ、１５：酸化絶縁層
７：第２の絶縁層
９：第３の絶縁層
１２：第１の材料層
１３：第２の材料層
１２ａ：第３の材料層
１３ａ：第４の材料層
１５：第１の絶縁層
１６：酸化絶縁層
１１Ａ、１１Ｂ：導体層
ＢＬ１：第１のビット線
ＢＬ２：第２のビット線
ＰＬ１：第１のプレート線
ＰＬ２：第２のプレート線
ＳＬ１：第１のソース線
ＳＬ２：第２のソース線 1: First P-layer substrate 1a: Second P-layer substrate 2a: First N + layer 2b: Second N + layer 2aa: Third N + layer 2ba: Fourth N + layer 3: first P layer 3a: second P layer 4: first conductor layer 11: second conductor layer 4a: third conductor layer 5: first gate insulating layer 5a: second gate insulating layer 6: first gate conductor layer 8: second gate conductor layer 6a: third gate conductor layer 8a: fourth gate conductor layer 13A, 15: oxide insulating layer 7: second insulating layer 9: third insulating layer 12: first material layer 13: second material layer 12a: third material layer 13a: fourth material layer 15: first insulating layer 16: oxide insulating layers 11A, 11B: conductor layer BL1: first bit line BL2: second bit line PL1: first plate line PL2: second plate line SL1: first source line SL2: second source line

Claims (8)

　第１の不純物層と、第１のゲート導体層と、第２のゲート導体層と、第２の不純物層と、第３の不純物層と、第３のゲート導体層と、第４のゲート導体層と、第４の不純物層とに印加する電圧により、データ書き込み動作と、データ読み出し動作と、データ消去動作を行うメモリ装置の製造方法であって、
　第１の基板上に、下から前記第１の不純物層と、第１の半導体層と、前記第１の半導体層を囲んだ第１のゲート絶縁層と、前記第１のゲート絶縁層の下部を囲んだ第１のゲート導体層と、前記第１のゲート絶縁層の上部を囲んだ第２のゲート導体層と、前記第２の不純物層とを形成する工程と、
　前記第２の不純物層に繋がり、水平方向に伸する第１の導体層と、前記第１の導体層上の第１の材料層と、前記第２の不純物層上の第２の材料層とを形成して、第１のメモリセルを形成する工程と、
　前記第１のメモリセルと同じ構造の第２の基板上の第２のメモリセルを形成する工程と、
　前記第２のメモリセルにおいて、前記第１のメモリセルの前記第１の材料層に対応する第３の材料層と、前記第１のメモリセルの前記第２の材料層に対応する第４の材料層を、前記第１の材料層と前記第３の材料層の位置を合わせ、前記第２の材料層と前記第４の材料層の位置を合わせて、前記第１のメモリセルと前記第２のメモリセルとを貼り合わせた構造よりなる２段メモリセルを形成する工程と、
　を備え、
　前記第１及び第３の材料層と、前記第２及び第４の材料層の一方、又は両方が酸化材料層であることを特徴とする半導体素子を用いたメモリ装置の製造方法。 A method for manufacturing a memory device performing a data write operation, a data read operation, and a data erase operation by applying voltages to a first impurity layer, a first gate conductor layer, a second gate conductor layer, a second impurity layer, a third impurity layer, a third gate conductor layer, a fourth gate conductor layer, and a fourth impurity layer, the method comprising:
forming, from below, on a first substrate, the first impurity layer, a first semiconductor layer, a first gate insulating layer surrounding the first semiconductor layer, a first gate conductor layer surrounding a lower portion of the first gate insulating layer, a second gate conductor layer surrounding an upper portion of the first gate insulating layer, and the second impurity layer;
forming a first conductor layer connected to the second impurity layer and extending in a horizontal direction, a first material layer on the first conductor layer, and a second material layer on the second impurity layer to form a first memory cell;
forming a second memory cell on a second substrate having the same structure as the first memory cell;
forming a second memory cell having a structure in which the first memory cell and the second memory cell are bonded together by forming a third material layer corresponding to the first material layer of the first memory cell and a fourth material layer corresponding to the second material layer of the first memory cell, aligning the positions of the first material layer and the third material layer and aligning the positions of the second material layer and the fourth material layer;
Equipped with
A method for manufacturing a memory device using a semiconductor element, wherein one or both of the first and third material layers and the second and fourth material layers are oxide material layers. 　前記第１の材料層、前記第３の材料層が導体材料層よりなり、前記第２の材料層と前記第３の材料層が酸化絶縁層よりなる、
　ことを特徴とする請求項１に記載の半導体素子を用いたメモリ装置の製造方法。 the first material layer and the third material layer are made of conductive material layers, and the second material layer and the third material layer are made of oxide insulating layers;
2. A method for manufacturing a memory device using the semiconductor element according to claim 1. 　前記第１の材料層が前記第１の導体層が上方に伸延した構造である、
　ことを特徴とする請求項２に記載の半導体素子を用いたメモリ装置の製造方法。 The first material layer has a structure in which the first conductor layer extends upward.
3. A method for manufacturing a memory device using the semiconductor element according to claim 2. 　前記第１の材料層が、上方に伸延した前記第１の導体層と、前記第１の導体層上の酸化絶縁層とよりなり、前記第２の材料が、前記第１の導体層が前記第２の不純物層上まで繋がった部分と、前記第１の材料層部分から水平方向に前記酸化絶縁層より形成される、
　ことを特徴とする請求項１に記載の半導体素子を用いたメモリ装置の製造方法。 The first material layer is composed of the first conductor layer extending upward and an oxide insulating layer on the first conductor layer, and the second material is formed by a portion where the first conductor layer is connected to the second impurity layer and the oxide insulating layer in a horizontal direction from the first material layer portion.
2. A method for manufacturing a memory device using the semiconductor element according to claim 1. 　前記第１の材料層が酸化絶縁層であり、前記第２の材料層が垂直方向に伸延した前記第２の不純物層より形成される、
　ことを特徴とする請求項１に記載の半導体素子を用いたメモリ装置の製造方法。 the first material layer is an oxide insulating layer, and the second material layer is formed of the second impurity layer extending in a vertical direction;
2. A method for manufacturing a memory device using the semiconductor element according to claim 1. 　前記第１及び第３のゲート導体層と、前記第２及び第４のゲート導体層が、垂直断面、又は水平断面で複数に分割して形成される、
　ことを特徴とする請求項１に記載の半導体素子を用いたメモリ装置の製造方法。 the first and third gate conductor layers and the second and fourth gate conductor layers are formed by dividing the first and third gate conductor layers into a plurality of parts in a vertical cross section or a horizontal cross section;
2. A method for manufacturing a memory device using the semiconductor element according to claim 1. 　前記第１及び第３のゲート導体層と、前記第２及び第４のゲート導体層の一方がプレート線に接続し、他方がワード線に接続するように形成する、
　ことを特徴とする請求項１に記載の半導体素子を用いたメモリ装置の製造方法。 forming the first and third gate conductor layers and the second and fourth gate conductor layers so that one of them is connected to a plate line and the other is connected to a word line;
2. A method for manufacturing a memory device using the semiconductor element according to claim 1. 　前記第１の不純物層と第２の不純物層の一方をビット線に接続し、他方をソース線に接続するように形成する、
　ことを特徴とする請求項１に記載の半導体素子を用いたメモリ装置の製造方法。 one of the first impurity layer and the second impurity layer is formed to be connected to a bit line, and the other is formed to be connected to a source line;
2. A method for manufacturing a memory device using the semiconductor element according to claim 1.
PCT/JP2022/039959 2022-10-26 2022-10-26 Method for manufacturing memory device using semiconductor element Ceased WO2024089809A1 (en)

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