WO2024067511A1 - Photosensitive pixel structure, image sensor, and electronic device - Google Patents

Abstract

The present application belongs to the technical field of image sensors. Disclosed is a photosensitive pixel structure. The photosensitive pixel structure comprises: a photosensitive unit, a photosensitive signal processing circuit, and a gain mode selection circuit, wherein the photosensitive unit is connected to the photosensitive signal processing circuit; the gain mode selection circuit outputs a gain mode selection signal, and the gain mode selection circuit is connected to the photosensitive signal processing circuit; the photosensitive signal processing circuit comprises a photosensitive signal reading unit and a gain processing unit, the photosensitive signal reading unit being connected to the photosensitive unit to receive an initial photosensitive signal, the gain processing unit being connected to the gain mode selection circuit to receive the gain mode selection signal, and the gain processing unit being connected to the photosensitive signal reading unit; and the photosensitive signal processing circuit determines a gain processing mode for the initial photosensitive signal according to the gain mode selection signal.

Description

Photosensitive pixel structure, image sensor and electronic device

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to the Chinese patent application filed with the China Patent Office on September 30, 2022, with application number 202211220462.5 and application name “Photosensitive pixel structure, image sensor and electronic device”, and the Chinese patent application filed with the China Patent Office on January 18, 2023, with application number 202310077565.9 and application name “Photosensitive pixel structure, image sensor and electronic device”, the entire contents of which are incorporated by reference in this application.

Technical Field

The present application belongs to the technical field of image sensors, and specifically relates to a photosensitive pixel structure, an image sensor and an electronic device.

Background technique

With the development of shooting technology, the Dual Conversion Gain-High Dynamic Range (DCG-HDR) technology in image sensors has also received more and more attention. After the DCG-HDR technology, in order to further increase the dynamic range, the Triple Conversion Gain-High Dynamic Range (TCG-HDR) technology came into being. At present, there are two ideas for TCG-HDR technology:

The first idea: Due to the limitation of wiring space and other factors, pixel-by-pixel modulation cannot be achieved for mobile terminals. Therefore, the relevant technology is to first expose each pixel structure in the pixel array in the high conversion gain (HCG) mode, and read the first image information under the high gain processing mode HCG; then expose each pixel structure in the middle conversion gain (MCG), and read the second image information under the middle gain processing mode MCG; then expose each pixel structure in the low conversion gain (LCG) mode, and read the third image information under the low gain processing mode LCG; finally, the first image information, the second image information and the third image information are selected/cropped/optimized/synthesized by the back-end image signal processor (ISP), and the final high dynamic range (HDR) image is output.

The second idea is to use a complex system composed of a complex image sensor chip and an off-chip optical encoding device for step-by-step exposure. The off-chip optical encoding device includes multiple components, such as an eyepiece, a conductive head group, a polarizing beam splitter, an encoder, etc., which are installed through a complex connection structure.

The inventor discovered during the research process that:

For the first approach, since both the first image information under the high-gain processing mode HCG and the second image information under the low-gain processing mode LCG are required (i.e., two frames of images), it is time-consuming and requires the powerful image signal processing capability of the ISP, so it is also energy-consuming. Furthermore, since the ISP has a processing defect of selecting and rejecting image signals, the HDR image synthesized by the first image information and the second image information may have brightness or/color stratification and signal-to-noise ratio (SNR) drop, that is, in some scenes with complex changes in brightness and darkness, the synthesized HDR image may have the problem of partial overexposure of some pixels or partial underexposure of some pixels, and it is impossible to At the same time, some pixels that are overexposed or underexposed are compensated.

As for the second idea, although the current pixel-by-pixel exposure time control technology can achieve pixel-level dynamic range modulation to avoid overexposure or underexposure problems, the implementation of the pixel-by-pixel exposure time control technology is too complicated and requires precise calibration between different devices. That is, the pixel-by-pixel exposure time control technology has problems such as size, power consumption, and difficulty in adjustment, which limits its application scope.

Summary of the invention

The purpose of the embodiments of the present application is to provide a photosensitive pixel structure, an image sensor and an electronic device that can achieve dynamic range modulation at the pixel level to avoid overexposure or underexposure, and can also solve the problems of high energy consumption, complex structure and narrow application range.

In a first aspect, an embodiment of the present application provides a photosensitive pixel structure, including a photosensitive unit, a photosensitive signal processing circuit, and a gain mode selection circuit;

The photosensitive unit includes a photosensitive element for generating an initial photosensitive signal, and the photosensitive unit is connected to the photosensitive signal processing circuit;

The gain mode selection circuit outputs a gain mode selection signal, and the gain mode selection circuit is connected to the photosensitive signal processing circuit;

The photosensitive signal processing circuit includes a photosensitive signal reading unit and a gain processing unit, wherein the photosensitive signal reading unit is connected to the photosensitive unit to receive the initial photosensitive signal, the gain processing unit is connected to the gain mode selection circuit to receive the gain mode selection signal, and the gain processing unit is connected to the photosensitive signal reading unit;

The gain mode selection circuit comprises a first selection subcircuit and a second selection subcircuit, the gain mode selection signal output by the first selection subcircuit is a first mode selection signal, and the gain mode selection signal output by the second selection subcircuit is a second mode selection signal;

The photosensitive signal processing circuit determines a gain processing mode for the initial photosensitive signal according to the gain mode selection signal.

In a second aspect, an embodiment of the present application provides an image sensor, which includes the photosensitive pixel structure of the first aspect.

In a third aspect, an embodiment of the present application provides an electronic device comprising the image sensor of the second aspect.

In the embodiment of the present application, since a gain mode selection circuit is provided in the embodiment of the present application, the gain mode selection circuit can output a gain mode selection signal to the gain processing unit of the photosensitive signal processing circuit, so that the photosensitive signal processing circuit can determine the gain processing mode of the initial photosensitive signal according to the gain mode selection signal. Then, for each photosensitive pixel structure, its gain processing mode can be controlled by the gain mode selection circuit, so that the photosensitive pixel structure and the usage scenario can select the working mode corresponding to the usage scenario, realize pixel-level dynamic range modulation, and reduce overexposure or underexposure. In addition, since the gain mode selection circuit includes a first selection subcircuit and The second selection subcircuit can realize the selection of more working modes through the first mode selection signal output by the first selection subcircuit and the second mode selection signal output by the second selection subcircuit.

In addition, due to the simple circuit structure, the gain processing mode of the initial light-sensitive signal can be adaptively adjusted, and there is no need to obtain two images for processing, which reduces energy consumption. It can also effectively reduce the problem of partial overexposure or partial underexposure of some pixels in some scenes with complex changes in brightness and darkness, and can also compensate for partial overexposure or partial underexposure at the same time.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic structural diagram of a photosensitive pixel structure provided in an embodiment of the present application;

FIG2 is a schematic structural diagram of another photosensitive pixel structure provided in an embodiment of the present application;

FIG3 is a schematic structural diagram of another photosensitive pixel structure provided in an embodiment of the present application;

FIG4 is a schematic structural diagram of another photosensitive pixel structure provided in an embodiment of the present application;

FIG5 is a schematic diagram of the structure of a gain mode selection circuit provided in an embodiment of the present application;

FIG6 is a schematic diagram of the structure of another gain mode selection circuit provided in an embodiment of the present application;

FIG7 is a circuit diagram of a photosensitive pixel structure provided in an embodiment of the present application;

FIG8 is a circuit diagram of another photosensitive pixel structure provided in an embodiment of the present application;

FIG9 is a circuit diagram of another photosensitive pixel structure provided in an embodiment of the present application;

FIG10 is a circuit diagram of another photosensitive pixel structure provided in an embodiment of the present application;

FIG11 is a circuit diagram of another photosensitive pixel structure provided in an embodiment of the present application;

FIG12 is a circuit diagram of another photosensitive pixel structure provided in an embodiment of the present application;

FIG13 is a circuit diagram of another photosensitive pixel structure provided in an embodiment of the present application;

FIG14 is a circuit diagram of another photosensitive pixel structure provided in an embodiment of the present application;

FIG15 is a circuit diagram of another photosensitive pixel structure provided in an embodiment of the present application;

FIG16 is a schematic diagram of another photosensitive pixel processing circuit in the photosensitive pixel structure provided in an embodiment of the present application;

FIG. 17 is a schematic diagram of another photosensitive pixel processing circuit in the photosensitive pixel structure provided in an embodiment of the present application.

Specific embodiments

The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

The “ground terminal”, “first ground terminal”, “second ground terminal” and “third ground terminal” in the present application may refer to the same ground terminal connected to the ground level in an actual circuit.

The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that the terms used in this way are appropriate. The terms "and/or" and "the" in the specification and claims generally refer to at least one of the connected objects, and the character "/" generally refers to an "or" relationship between the connected objects.

The pixel structure provided in the embodiment of the present application is described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

The embodiment of the present application provides a photosensitive pixel structure, as shown in FIG1 , the photosensitive pixel structure includes: a photosensitive unit 10 , a photosensitive signal processing circuit 11 and a gain mode selection circuit 12 ;

The photosensitive unit 11 includes a photosensitive element 101 for generating an initial photosensitive signal, and the photosensitive unit 10 is connected to the photosensitive signal processing circuit 11;

The gain mode selection circuit 12 outputs a gain mode selection signal, and the gain mode selection circuit 12 is connected to the photosensitive signal processing circuit 11;

The photosensitive signal processing circuit 11 includes a photosensitive signal reading unit 112 and a gain processing unit 111, wherein the photosensitive signal reading unit 112 is connected to the photosensitive unit 10 to receive the initial photosensitive signal, and the gain processing unit 111 is connected to the gain mode selection circuit 11 to receive the gain mode selection signal, and the gain processing unit 111 is connected to the photosensitive signal reading unit 112;

The gain mode selection circuit 12 includes a first selection subcircuit 120 and a second selection subcircuit 121 . The gain mode selection signal output by the first selection subcircuit 120 is a first mode selection signal, and the gain mode selection signal output by the second selection subcircuit 121 is a second mode selection signal.

The photosensitive signal processing circuit 11 determines a gain processing mode for the initial photosensitive signal according to the gain mode selection signal.

The output end of the light-sensing signal processing circuit 11 is the output end of the light-sensing pixel structure.

The first selection sub-circuit 120 receives a first initial selection signal at its input terminal and then outputs a first mode selection signal to the gain processing unit 111 .

The second selection sub-circuit 121 receives a second initial selection signal at its input terminal and then outputs a second mode selection signal to the gain processing unit 111 .

Then, the gain processing unit 111 selects the corresponding gain processing mode according to the first initial selection signal outputting the corresponding first gain mode selection signal and the second initial selection signal and the second gain mode selection signal.

In the embodiment of the present application, the specific circuit structure of the photosensitive unit 10, the photosensitive signal processing circuit 11 and the gain mode selection circuit 12 of the photosensitive unit 10 is not limited. As long as the response function is met, it is within the scope of protection of the photosensitive pixel structure provided in the embodiment of the present application.

In a possible implementation, the gain processing mode may include three operating modes: a high gain processing mode HCG, a medium gain processing mode MCG, and a low gain processing mode LCG. Different combinations of the first mode selection signal and the second mode selection signal correspond to different operating modes. For example, the first mode selection signal is When the signal is a high level signal and the second mode selection signal is a high level signal, it corresponds to the high gain processing mode HCG; for example, when the first mode selection signal is a low level signal and the second mode selection signal is a high level signal, it corresponds to the medium gain processing mode MCG; for example, when the first mode selection signal is a low level signal and the second mode selection signal is a low level signal, it corresponds to the high gain processing mode HCG.

In different gain modes, the photoelectron accumulation rate represented by the output signal of the photosensitive pixel structure is different. For example, in the high-gain processing mode HCG, the photoelectron accumulation rate represented by the output signal of the photosensitive pixel structure is the highest (rapidly increasing), indicating that the light sensitivity of the photosensitive pixel in the high-gain processing mode HCG is the highest; in the low-gain processing mode LCG, the photoelectron accumulation rate represented by the output signal of the photosensitive pixel structure is the lowest, indicating that the light sensitivity of the photosensitive pixel in the low-gain processing mode LCG is the lowest; in the medium-gain processing mode MCG, the photoelectron accumulation rate represented by the output signal of the photosensitive pixel structure is between the corresponding rates of the high-gain processing mode HCG and the low-gain processing mode LCG, indicating that the light sensitivity of the photosensitive pixel in the medium-gain processing mode MCG is between the corresponding light sensitivity of the high-gain processing mode HCG and the low-gain processing mode LCG.

In some possible embodiments, the first initial selection signal LCG_SEL connected to the first mode selection signal input terminal of the first selection subcircuit 120 or the second initial selection signal MCG_SEL connected to the second mode selection signal input terminal of the second selection subcircuit 121 can be different level signals in the configuration phase and the reading phase within one frame time, or can be the same level signal, which determines the working mode of each photosensitive pixel structure according to the current usage scenario.

In some possible implementations, the first mode selection signal and the second mode selection signal can both be a first level or a second level, for example, both can be a high level signal or a high level signal. The first mode selection signal input to the first mode selection signal input terminal can be different level signals in the configuration phase and the reading phase within a frame time, or can be the same level signal. The working mode of each pixel structure needs to be determined according to the application scenario. Low gain processing mode LCG Low gain processing mode LCG Medium gain processing mode LCG Medium gain processing mode LCG Low gain processing mode LCG Medium gain processing mode LCG

Among them, the usage scenario can be determined by the electronic device identifying the preview image of the camera, such as identifying the content of the preview image to determine whether it is highly overexposed, moderately overexposed, or underexposed. If it is highly overexposed, it is necessary to enter the low gain processing mode LCG, if it is moderately overexposed, it is necessary to enter the medium gain processing mode LCG, if it is underexposed, it is necessary to enter the high gain processing mode HCG, or identify according to the scene mode selected by the user to determine whether the low gain processing mode LCG, the medium gain processing mode LCG, or the high gain processing mode HCG is required.

In the embodiment of the present application, since a gain mode selection circuit 12 is provided, the gain mode selection circuit 12 can output a gain mode selection signal to the gain processing unit 111 of the photosensitive signal processing circuit 11, so that the photosensitive signal processing circuit 11 can determine the gain processing mode for the initial photosensitive signal according to the gain mode selection signal. Then, for each photosensitive pixel structure, its gain processing mode can be controlled by the gain mode selection circuit 12, so that the photosensitive pixel structure and the usage scenario can select the working mode corresponding to the usage scenario, realize pixel-level dynamic range modulation, and reduce overexposure or underexposure. In addition, since the gain mode selection circuit 12 includes a first selection subcircuit 120 and a second selection subcircuit 121, the gain mode selection signal is output through the first selection subcircuit 120. The first mode selection signal output by the second selection sub-circuit 121 and the second mode selection signal output by the second selection sub-circuit 121 can realize the selection of more working modes.

In addition, due to the simple circuit structure, the gain processing mode of the initial light-sensitive signal can be adaptively adjusted, and there is no need to obtain two images for processing, which reduces energy consumption. It can also effectively reduce the problem of partial overexposure or partial underexposure of some pixels in some scenes with complex changes in brightness and darkness, and can also compensate for partial overexposure or partial underexposure at the same time.

In some embodiments of the present application, referring to FIG. 2 , the photosensitive signal processing circuit 11 further includes a reset unit 113 , which is connected to the gain processing unit 111 , and is used to reset the photosensitive signal processing circuit 11 .

7 , the reset unit 113 includes a reset transistor T3 , a reset signal input terminal, a power signal input terminal and a reset signal output terminal.

When the fourth transistor is a P-type transistor, the gate of the reset transistor T3 is used as a reset signal input terminal, and the reset signal RST is connected; the source of the reset transistor 3 is used as a power signal input terminal, and the power signal VDD is connected; the drain of the reset transistor T3 is used as a reset signal output terminal, and the transistor T1 is connected. The reset signal input terminal inputs the reset signal RST. For example, when the reset signal RST is at a low level, the reset transistor T3 is turned on, and the photosensitive pixel structure is reset. When the reset signal RST is at a high level, the reset transistor T3 is turned off.

When the fourth transistor is an N-type transistor, the gate of the reset transistor T3 is connected to the reset signal terminal RST, and the drain of the reset transistor T3 is used as the power signal input terminal and connected to the power signal VDD; the source of the reset transistor T3 is used as the reset signal output terminal and is connected to the transistor T1. The reset signal input terminal inputs the reset signal RST, such as a high level, and the reset transistor T3 is turned on to reset the photosensitive pixel structure. When the reset signal RST is at a low level, the reset transistor T3 is turned off.

In the subsequent stage of selecting the working mode of the light-sensing signal processing circuit 11 to read and output the initial light-sensing signal of the light-sensing unit 10 , the reset signal RST controls the reset transistor T3 to be turned off.

It should be noted that the transistors at various positions in the embodiments of the present application can be N-type or P-type, and then electrically connected according to the N-type or P-type principles and provide corresponding on or off signals.

In some embodiments of the present application, the first selection subcircuit 120 has a first selection signal input terminal, a first selection signal output terminal and a first selection control signal input terminal, and the first selection signal output terminal is electrically connected to the gain processing unit 111; the first selection signal input terminal is used to access the first initial selection signal LCG_SEL, the first selection control signal input terminal is used to access the first selection control signal SEL_CLK, and the first selection signal output terminal is used to output the first mode selection signal according to the first initial selection signal under the control of the first selection control signal;

The second selection subcircuit 121 has a second selection signal input terminal, a second selection signal output terminal and a second selection control signal input terminal, and the second selection signal output terminal is electrically connected to the gain processing unit 111; the second selection signal input terminal is used to access the second initial selection signal MCG_SEL, the second selection control signal input terminal is used to access the second selection control signal SEL_CLK, and the second selection signal output terminal is used to access the second initial selection signal MCG_SEL. The second mode selection signal is output according to the second initial selection signal under the control of the second selection control signal.

It can be understood that, for the first selection subcircuit 120, the first initial selection signal LCG_SEL connected to the first selection control signal input terminal can be a constant first level signal or a square wave signal within one frame time. In the case where the first initial selection signal LCG_SEL is a constant first level signal, the second mode selection signal output from the first selection signal output terminal is directly output to the input terminal of the gain processing unit 111 of the photosensitive signal processing circuit 11; in the case where the first initial selection signal LCG_SEL is a square wave signal, and the square wave signal includes a first level signal and a second level signal, and the voltage of the first level signal is greater than the voltage of the second level signal, the first initial selection signal LCG_SEL input to the first selection signal input terminal or the first mode selection signal obtained based on the first initial selection signal LCG_SEL can be first cached in the first mode selection circuit 11, and then the first mode selection signal is output to the photosensitive signal processing circuit 11 when needed.

It can be understood that, for the second selection subcircuit 121, the second initial selection signal MCG_SEL connected to the second selection control signal input terminal can be a constant second level signal or a square wave signal within one frame time. In the case where the second initial selection signal MCG_SEL is a constant second level signal, the second mode selection signal output from the second selection signal output terminal is directly output to the input terminal of the gain processing unit 111 of the photosensitive signal processing circuit 11; in the case where the second initial selection signal MCG_SEL is a square wave signal, and the square wave signal includes a first level signal and a second level signal, and the voltage of the first level signal is greater than the voltage of the second level signal, the initial selection signal MCG_SEL input to the second selection signal input terminal or the second mode selection signal obtained based on the first initial selection signal MCG_SEL can be first cached in the second mode selection circuit 11, and then the gain mode selection signal is output to the photosensitive signal processing circuit 11 when needed.

It should be noted that, for the second selection sub-circuit 121 , its principle is similar to that of the first selection sub-circuit 120 .

As shown in FIG7 , the first selection signal input terminal of the first selection subcircuit 120 may be a gate, the first selection control signal input terminal may be a source, the first selection signal output terminal may be a drain, and the first selection signal output terminal is connected to the gate of the transistor T1. The first selection control signal input terminal is used to receive the first selection control signal SEL_CLK; the first selection signal input terminal is connected to the first initial selection signal LCG_SEL, and then the first selection control signal input terminal may be a first mode selection signal outputted by the first control selection signal output terminal as a high level or a low level, thereby turning on or off the transistor T1.

The second selection signal input terminal of the second selection subcircuit 121 may be a gate, the second selection control signal input terminal may be a source, the second selection signal output terminal may be a drain, and the second selection signal output terminal is connected to the gate of the transistor T2. The second selection control signal input terminal is used to receive the second selection control signal SEL_CLK; the second selection signal input terminal is connected to the second initial selection signal MCG_SEL, and then the second selection control signal input terminal can control the second mode selection signal outputted from the second control selection signal output terminal to be high level or low level, thereby turning on or off the transistor T2.

Then, when the transistor T1 and the transistor T2 are turned on, the light-sensing signal processing circuit 11 is in the low gain processing mode LCG; when the transistor T1 is turned off and the transistor T2 is turned on, the light-sensing signal processing circuit 11 is in the medium gain processing mode LCG. gain processing mode MCG; when the transistor T1 is disconnected and the transistor T2 is disconnected, the photosensitive signal processing circuit 11 is in the high gain processing mode HCG.

It should be noted that, referring to FIG. 3 and FIG. 7 , the first selection subcircuit 120 includes the aforementioned first cache element 125 with a cache function, and the first cache element 125 may be a cache capacitor C4. The output end of the first cache element 125 is a first selection signal output end. Referring to FIG. 8 , relative to FIG. 7 , a first selection switch element 127 is added on the basis of FIG. 7 , and the first selection switch element 127 may be the transistor M1 in FIG. 8 , and then the output end of the transistor M1 is the first selection signal output end.

It should be noted that, referring to FIG. 3 and FIG. 7 , the second selection subcircuit 121 includes the aforementioned second cache element 126 with a cache function, and the second cache element 126 may be a cache capacitor C3. The output end of the second cache element 126 is a second selection signal output end. Referring to FIG. 8 , relative to FIG. 7 , a second selection switch element 128 is added on the basis of FIG. 7 , and the second selection switch element 128 may be the transistor M2 in FIG. 8 , and then the output end of the transistor M2 is the second selection signal output end.

In some embodiments of the present application, referring to FIG. 3 , the first selection subcircuit 120 further includes a first cache element 125 and a first selection switch element 127 .

The first cache element 125 is electrically connected to the first selection signal input terminal, the first cache element is electrically connected to the first selection signal output terminal, and the first cache element 126 is used to store the first initial selection signal LCG_SEL or the first mode selection signal;

The first end of the first selection switch element 127 is connected to the first selection signal output end to receive the first mode selection signal, the second end of the first selection switch element 127 is connected to the gain processing unit 111, and the control end of the first selection switch element 127 is connected to the first enable control signal to output the first mode selection signal to the gain processing unit 111 when it is necessary to switch the gain processing mode of the initial photosensitive signal.

It can be understood that, as shown in FIG8 , the first selection switch element 127 is a transistor M1. A transistor M1 controlled by an enable control signal EN is provided between the output end of the cache capacitor C4 and the gain processing unit 111. When the photosensitive pixel structure is updating the gain mode selection signal in the reading phase, the enable control signal EN can be kept at a low level or "0" to disconnect the transistor M1. After the photosensitive pixel structure updates the first initial selection signal LCG_SEL or the first mode selection signal cached in the corresponding cache capacitor C4, the required photosensitive pixel structure is determined according to the shooting requirements, and the corresponding enable control signal EN can be pulled high to output the gain mode selection signal cached in the cache capacitor C4 of the photosensitive pixel structure to the gain processing unit 111.

As shown in Figure 8, the second selection switch element 128 is a transistor M2. A transistor M2 controlled by an enable control signal EN is set between the output end of the cache capacitor C3 and the gain processing unit 111. When the photosensitive pixel structure is updating the gain mode selection signal in the reading phase, the enable control signal EN can be kept at a low level or "0" to disconnect the transistor M2. After the photosensitive pixel structure updates the second initial selection signal MCG_SEL or the second mode selection signal cached in the corresponding cache capacitor C3, the required photosensitive pixel structure is determined according to the shooting requirements, and the corresponding enable control signal EN can be pulled high to allow the cache capacitor cached in the photosensitive pixel structure to be fully active. The second mode selection signal in C3 is output to the gain processing unit 111 .

The above process is beneficial for the photosensitive signal processing circuit 11 in each photosensitive pixel structure to obtain the above two mode selection signals, and then enter the corresponding gain processing mode according to the above two mode selection signals, and then in the corresponding gain processing mode, amplify the electrical signal of the photosensitive unit 10 to read the image information.

Of course, when each photosensitive pixel structure in the pixel array is updating the gain mode selection signal in the reading phase, the enable control signal EN can be kept at a low level or "0" so that the transistor M1 and the transistor M2 are disconnected. When the pixel structures in the pixel array have updated the first mode selection signal cached in the corresponding cache capacitor C4 and the second mode selection signal cached in the cache capacitor C3, the enable control signals EN corresponding to all the photosensitive pixel structures in the pixel array can be pulled high at the same time, so that the first mode selection signal cached in the cache capacitor C4 of the photosensitive pixel structure and the second mode selection signal cached in the cache capacitor C3 are output to the gain processing unit at the same time, so as to control the photosensitive signal reading unit 112 to operate in one of the high gain processing mode HCG, the medium gain processing mode MCG or the low gain processing mode LCG, which is beneficial for the photosensitive signal processing circuit 11 in each pixel structure to obtain the second mode selection signal and the first mode selection signal at the same time, amplify the electrical signal of the photosensitive unit, and read the image information at the same time, so as to realize the global shutter of the complementary metal oxide semiconductor (CMOS) image sensor (CIS).

It should be noted that, through the above method, the corresponding gain mode selection signal can be temporarily stored by the above two buffer elements, and then the gain mode selection signal temporarily stored by the buffer element can be outputted through the above two selection switch elements when the gain mode needs to be changed. Alternatively, through the above method, the initial selection signal can be temporarily stored by the above two buffer elements, and then the initial selection signal temporarily stored by the buffer element can be adjusted to the required gain mode selection signal for output when the gain mode needs to be changed through the above two selection switch elements.

In some embodiments of the present application, the first selection subcircuit 120 includes a first switch element M4 and a first cache capacitor C4;

The control end of the first switch element M4 is the first selection control signal input end, the first end of the first switch element M4 is the first selection signal input end, the second end of the first switch element M4 is electrically connected to the first end of the first cache capacitor C4, the first end of the first cache capacitor C4 is electrically connected to the first selection signal output end, and the second end of the first cache capacitor C4 is grounded.

It should be noted that, in this embodiment, the first cache element 125 is a first cache capacitor C4.

As shown in FIG7 , the first switch element M4 is a transistor M4, and the first cache capacitor is C4. The control end of the transistor M4 is the selection control signal input end SEL_CTR; the first end of the transistor M4 is the selection signal input end, receiving the first initial selection signal LCG_SEL; the second end of the transistor M4 is connected to the first end of the first cache capacitor C4, and the second end of the first cache capacitor C4 is grounded GND. By means of the cache capacitor, the first mode selection signal can be stored more simply.

It should be noted that the second selection sub-circuit 121 includes a second switch element M3 and a second cache circuit. Capacity C3;

The control end of the second switch element M3 is the second selection control signal input end, the second end of the second switch element M3 is the second selection signal input end, the second end of the second switch element M3 is electrically connected to the second end of the second cache capacitor, the second end of the second cache capacitor is electrically connected to the second selection signal output end, and the second end of the second cache capacitor C3 is grounded.

It should be noted that the second cache element 128 is a second cache capacitor C3 .

As shown in Figure 7, the second switch element M3 is a transistor M3, and the second cache capacitor is C3. The control end of the transistor M3 is the selection control signal input end SEL_CTR; the second end of the transistor M3 is the selection signal input end, which receives the second initial selection signal MCG_SEL; the second end of the transistor M3 is connected to the first end of the second cache capacitor C3, and the second end of the second cache capacitor C3 is grounded GND. By means of a cache capacitor, the second mode selection signal can be stored more simply. In Figure 7, if the MCG_SEL signal cached in the cache capacitor C3 is to be changed or updated, the control signal SEL_CLK of the transistor M3 needs to be pulled high, so that M3 is closed, and the updated MCG_SEL signal enters the cache capacitor C3; if the LCG_SEL signal cached in the cache capacitor C4 is to be changed or updated, the control signal SEL_CLK of the transistor M4 needs to be pulled high, so that M4 is closed, and the updated LCG_SEL signal enters the cache capacitor C4. If the control signal SEL_CLK of transistor M3 and the control signal SEL_CLK of transistor M4 are pulled low, transistor M3 and transistor M4 are disconnected, and no matter how the external MCG_SEL signal and LCG_SEL signal change, the MCG_SEL signal in cache capacitor C3 and the LCG_SEL signal in cache capacitor C4 remain unchanged.

In some embodiments of the present application, the first selection subcircuit 120 includes a first trigger 123, and the first trigger 123 has the first selection signal input terminal D, the first selection signal output terminal Q and the first selection control signal input terminal.

The first selection signal input terminal D is used to access the initial selection signal LCG_SEL, the first selection control signal input terminal is used to access the first selection control signal SEL_CTR, and the first selection signal output terminal Q is used to output the first mode selection signal according to the first initial selection signal LCG_SEL under the control of the first selection control signal SEL_CTR. Optionally, referring to FIG. 5, a first selection switch element 127 may be added after the first trigger 123, the first selection signal output terminal of the first trigger 123 is connected to the first terminal of the first selection switch element 127, and the second terminal of the first selection switch element 127 is connected to the gain processing unit 111. Referring to FIG. 13, the first trigger 123 includes the selection signal input terminal D for receiving the initial selection signal LCG_SEL, the first trigger 123 has the first selection signal output terminal Q, and the first trigger 123 has the selection control signal input terminal for receiving the selection control signal SEL_CTR. The first selection signal output terminal Q is connected to the input terminal of the transistor M1, and the output terminal of the transistor M1 is connected to the gain processing unit 111.

In the embodiment of the present application, the first mode selection signal can be temporarily stored by the first trigger 123, and then the first mode selection signal temporarily stored by the first trigger 123 is output when the gain mode needs to be changed through the first selection switch element 127. Alternatively, the first initial selection signal can be temporarily stored by the first trigger 123, and then the first mode selection signal temporarily stored by the first trigger 123 is output when the gain mode needs to be changed through the first selection switch element 127. A first initial selection signal temporarily stored in a flip-flop 123 is adjusted to a required first mode selection signal for output operation.

In one embodiment of the present application, the first trigger 123 can be retained, and the first selection switch element 127 can be removed. The first selection signal output terminal of the first trigger 123 is connected to the gain processing unit 111. Referring to FIG. 11, the first trigger G1 has the selection signal input terminal D for receiving the initial selection signal DCG_SEL. The first trigger G1 has the first selection signal output terminal Q. The first trigger G1 has the first selection control signal input terminal for receiving the selection control signal SEL_CTR. The first selection signal output terminal Q is connected to the gain processing unit 111.

In some embodiments, the second selection subcircuit 121 includes a second flip-flop 124 , and the second flip-flop 124 has the second selection signal input terminal D, the second selection signal output terminal Q, and the second selection control signal input terminal.

The second selection signal input terminal D is used to access the initial selection signal LCG_SEL, the second selection control signal input terminal is used to access the second selection control signal SEL_CTR, and the second selection signal output terminal Q is used to output the second mode selection signal according to the second initial selection signal LCG_SEL under the control of the second selection control signal SEL_CTR.

Optionally, referring to FIG5 , a second selection switch element 128 may be added after the second trigger 124, and the second selection signal output terminal of the second trigger 124 is connected to the second terminal of the second selection switch element 127, and the second terminal of the second selection switch element 128 is connected to the gain processing unit 111. Referring to FIG13 , the second trigger 124 includes the selection signal input terminal D for receiving the initial selection signal MCG_SEL. The second selection signal output terminal Q and the selection control signal input terminal are used to receive the selection control signal SEL_CTR. The second selection signal output terminal Q is connected to the input terminal of the transistor M2, and the output terminal of the transistor M2 is connected to the gain processing unit 111.

In the embodiment of the present application, the second mode selection signal can be temporarily stored by the second trigger 124, and then the second mode selection signal temporarily stored by the second trigger 124 is outputted only when the gain mode needs to be changed by the second selection switch element 128. Alternatively, in the above manner, the second initial selection signal can be temporarily stored by the second trigger 124, and then the second initial selection signal temporarily stored by the second trigger 124 is adjusted to the required second mode selection signal for output only when the gain mode needs to be changed by the second selection switch element.

In one embodiment of the present application, the second trigger 124 can be retained, and the second selection switch element 128 can be removed. The second selection signal output terminal of the second trigger 124 is connected to the gain processing unit 111. Referring to FIG. 11, the second trigger G1 has the selection signal input terminal D for receiving the initial selection signal DCG_SEL. The second trigger G1 has the second selection signal output terminal Q. The second trigger G1 has the second selection control signal input terminal for receiving the selection control signal SEL_CTR. The second selection signal output terminal Q is connected to the gain processing unit 111.

In the embodiment of the present application, the first trigger 123 and the second trigger 124 are used to output the gain mode selection signal, thereby realizing the selection of the gain mode.

In the embodiment of the present application, the first trigger 123 may be an implementation of the first cache element 125 The second trigger 124 may be an implementation of the second cache element 126 .

In some embodiments of the present application, referring to Figure 11, the first trigger 123 is a digital signal trigger G1, and the first trigger 123 also has a setting signal terminal S and a reset signal terminal R; when the setting signal terminal is loaded with a first level, the first mode selection signal output by the first selection signal output terminal Q makes the photosensitive signal processing circuit work in a first gain processing mode; when the reset signal terminal is loaded with a second level, the first mode selection signal output by the first selection signal output terminal Q and the second mode selection signal output by the second selection subcircuit make the photosensitive signal processing circuit 11 work in a second gain processing mode.

The first gain processing mode may be set to a low gain processing mode LCG, or may be set to a medium gain processing mode MCG or a high gain processing mode HCG.

By loading the same control signal to the setting signal terminal S of the trigger in all photosensitive pixel units and loading the same control signal to the reset signal terminal R of the trigger in all photosensitive pixel units, the image sensor containing all photosensitive pixel units can be operated in the traditional low-gain processing mode LCG, medium-gain processing mode MCG or high-gain processing mode HCG, thereby canceling the pixel-level adaptive gain mode selection function in the image sensor and fixing all photosensitive pixel structures in the image sensor in a certain gain mode, so as to cope with special shooting scenes.

In some embodiments of the present application, the digital signal trigger G1 may be a digital signal trigger (Data Flip-Flop, DFlip-Flop), i.e., a D signal trigger G1; the first selection signal input terminal D of the D signal trigger G1 receives the first initial selection signal LCG_SEL; the first selection control signal input terminal of the D signal trigger G1 receives the first receiving control signal SEL_CTR; the first selection signal output terminal Q of the D signal trigger G1 outputs the first mode selection signal. Among them, the first selection control signal input terminal may be an input terminal of a clock signal.

Based on the working principle of the D-signal flip-flop G1, it can be known that if the LCG_SEL signal needs to be cached, the control signal SEL_CTR needs a rising edge signal (the rising edge of the clock signal, that is, the process of the signal changing from "0" to "1"). At this time, the external initial selection signal LCG_SEL will be cached in this D-signal flip-flop G1. When the first control signal SEL_CTR signal provides a falling edge signal (the falling edge of the clock signal, that is, the process of the signal changing from "1" to "0"), the selection signal output terminal Q of the D-signal flip-flop G1 outputs the cached first mode selection signal LCG_SEL. The initial selection signal LCG_SEL outside the D-signal flip-flop G1 needs to cooperate with the control signal SEL_CTR to complete the caching of the initial selection signal LCG_SEL signal and the output of the first mode selection signal. When the control signal SEL_CTR signal remains at "0", no matter how the initial selection signal LCG_SEL signal outside the D-signal flip-flop G1 changes, the LCG_SEL signal cached in the D-signal flip-flop G1 remains unchanged.

It should be noted that the principle of the digital signal trigger G2 is similar to that of the digital signal trigger G1, except that its initial selection signal is the aforementioned MCG_SEL. LCG_SEL and MCG_SEL are both high or low levels, but the two triggers may receive the same level or different levels at the same time. In addition, the device using the D signal trigger as the cache mode selection signal does not need to be fixed frequency. Therefore, this cache can provide a stable and power-saving mode selection signal cache function. Furthermore, for applications without adaptive TCG-HDR requirements, the TCG selection signal cache step can be flexibly skipped by setting the signal end and resetting the signal end, which can be applied to rolling shutter or global shutter.

In some embodiments of the present application, referring to Figure 5, the first selection sub-circuit includes a first digital signal buffer 129, the first digital signal buffer 129 has the first selection signal input terminal, the first selection signal output terminal and the first selection control signal input terminal, and a digital signal cache unit 1291 for storing the first initial selection signal or the first mode selection signal.

The first selection signal input terminal is used for receiving an initial selection signal LCG_SEL.

The first selection signal output terminal is used to output the gain mode selection signal LCG_SEL’.

The first selection control signal input terminal is used to receive the selection control signal SEL_CLK, and the digital signal buffer unit 1291 is used to store the first mode selection signal.

In the above manner, the initial selection signal LCG_SEL can be converted into a gain mode selection signal LCG_SEL’ through the digital signal buffer 129 for output to select the working mode.

It should be noted that the second selection sub-circuit includes a second digital signal buffer, and its principle is similar to that of the first digital signal buffer 129, except that the received first initial selection signal is MCG_SEL, and the output second mode selection signal is MCG_SEL’, which will not be described in detail here.

In some embodiments of the present application, referring to FIG. 5 , the first selection subcircuit 120 includes a first switch element M4 and a first cache element 125 , and the first cache element 125 is a digital signal cache unit 1291 ;

The digital signal buffer unit 1291 includes a first switch tube M1, a second switch tube M12, a third switch tube M13, and a fourth switch tube M14;

The control end of the first switch element M4 is the selection control signal input end SEL_CLK, the first end of the first switch element M4 is the selection signal input end LCG_SEL, the second end of the first switch element M4 is electrically connected to the first end of the first switch tube M11, and the second end of the first switch element M4 is also electrically connected to the second end of the second switch tube M12;

The first switch tube M11 is of N type, a control end of the first switch tube M11 is electrically connected to a control end of the second switch tube M12, and a second end of the first switch tube M11 is grounded;

The second switch tube M12 is of P type, the control end of the second switch tube M12 is electrically connected to the first end of the third switch tube M13, the first end of the second switch tube M12 is connected to the power signal, and the second end of the second switch tube M12 is electrically connected to the control end of the third switch tube M13;

The third switch tube M13 is of N type, a first end of the third switch tube M13 is electrically connected to a second end of the fourth switch tube M14, and a second end of the third switch tube M13 is grounded;

The fourth switch tube M14 is of P type, a control end of the fourth switch tube M14 is electrically connected to a control end of the third switch tube M14, a first end of the fourth switch tube M14 is connected to the power signal, and a second end of the fourth switch tube M14 is electrically connected to the selection control signal output end.

The embodiment of the present application uses four transistors to realize the aforementioned cache function with a simple circuit structure. And gain mode selection signal output function.

In some embodiments of the present application, the first switching element M4 is a transistor M4. Referring to FIG5 , the digital signal buffer 129 includes: a transistor M4 and a digital signal buffer unit 1291; the control end (source) of the second transistor M4 is electrically connected to the first control signal input end; the first electrode of the transistor M2 is electrically connected to the first selection signal input end; the second electrode of the transistor M4 is electrically connected to the input end of the digital signal buffer unit 1291; and the output end of the digital signal buffer unit 1291 is connected to the first switching element M1 or to the gain processing unit 111.

It can be understood that the initial selection signal LCG_SEL is turned on by the transistor M4 controlled by the control signal SEL_CLK, and then LCG_SEL enters the digital signal buffer unit 1291. The cached initial selection signal LCG_SEL is inverted to LCG_SEL' by the digital signal buffer unit 1291 and then output. Among them, if the signal of the initial selection signal LCG_SEL is "1", the signal of LCG_SEL' is "0", and vice versa.

Referring to FIG. 6 , on the basis of FIG. 5 , a first selection switch element M8 is added, the first end of the first selection switch element M8 is the first selection signal input end LCG_SEL, and the second end is connected to the first end of the first switch element M4. The control end of the first selection switch element M8 is the enable signal input end EN. In the embodiment of the present application, a first selection switch element M8 may be further provided before the first switch element M4, and the selection switch element M8 is used to receive an enable signal to start or stop the digital signal buffer 129 from working.

It should be noted that the second selection subcircuit 121 includes a second switch element M3 and a first cache element 126, and the first cache element is a digital signal cache unit. The second switch element M3 is similar to the first switch element M1, and the digital signal cache unit in the second selection subcircuit 121 is similar to the digital signal cache unit in the first selection subcircuit 120, which will not be described in detail.

In some embodiments of the present application, the first selection subcircuit 120 also includes a first selection switch element 127, a first end of the first selection switch element 127 is connected to the first selection signal output end to receive the first mode selection signal, a second end of the first selection switch element 127 is connected to the gain processing unit 112, and a control end of the first selection switch element 127 is used to access a first enable control signal to output the first mode selection signal to the gain processing unit 111 when it is necessary to switch the gain processing mode of the initial photosensitive signal.

The second selection subcircuit 121 also includes a second selection switch element 128, a first end of the second selection switch element 128 is connected to the second selection signal output end to receive the second mode selection signal, a second end of the second selection switch element 128 is connected to the gain processing unit 112, and a control end of the second selection switch element 128 is used to access a second enable control signal to output the second mode selection signal to the gain processing unit 111 when it is necessary to switch the gain processing mode of the initial photosensitive signal.

In the embodiment of the present application, the first selection subcircuit 120 may only have the first cache element 125, which may be, for example, the aforementioned first cache capacitor C4, or the trigger 123, or the digital signal buffer G1, or the digital signal buffer unit 1281. The output end of the first cache element 125 may be directly connected to the gain processing unit 111. On this basis, as shown in FIG3 and FIG4, a first selection switch element 127 may be added to the above components, and the output end of the first cache element 125 may be connected to the first end of the first selection switch element 127. A second end of the first selection switch element 127 is connected to the gain processing unit 111 .

The second selection subcircuit 121 may also have only the second cache element 126, which may be, for example, the aforementioned first cache capacitor C3, or the trigger 124, or the digital signal buffer G2, or the digital signal buffer unit 1291. The output end of the second cache element 126 may be directly connected to the gain processing unit 111. On this basis, as shown in FIG3 and FIG4, a second selection switch element 128 may be added to the above components, the output end of the cache element 121 may be connected to the first end of the second selection switch element 128, and the second end of the second selection switch element 128 may be connected to the gain processing unit 111.

In some embodiments of the present application, referring to FIG. 7 , the light-sensing signal reading unit 11 includes a first storage capacitor FD, a signal amplifying element SF, and a reading switch element T5;

The first end of the first storage capacitor FD is electrically connected to the photosensitive unit 10 to receive the initial photosensitive signal, the first end of the first storage capacitor FD is also connected to the gain processing unit 111, and the second end of the first storage capacitor FD is grounded;

The input end of the signal amplifying element SF is connected to the first end of the first storage capacitor FD, and the output end of the signal amplifying element SF is connected to the first end of the reading switch element T5 to output the amplified light-sensing signal;

The control end of the read switch element T5 is used to access the output control signal SEL, and the second end of the read switch element T5 is the photosensitive signal output end PIX_OUT of the photosensitive pixel structure.

In the embodiment of the present application, the signal amplification element SF can be a transistor or an amplifier composed of multiple transistors, such as a capacitive feedback transimpedance amplifier (CTIA) amplifier, or other amplifiers, which are not limited here.

In some embodiments of the present application, referring to Figure 7, the signal amplifying element SF is an amplifying switch element, the control end of the amplifying switch element is connected to the first end of the first storage capacitor FD, the first end of the amplifying switch element is connected to the power supply signal VDD, and the second end of the amplifying switch element is electrically connected to the first end of the read switch element T5.

In the embodiment of the present application, the gate of the amplifying switch element SF is connected to the first end of the first storage capacitor FD. The drain of the amplifying switch element SF is connected to the power supply signal VDD, and the source of the amplifying switch element SF is electrically connected to the source of the second reading switch element M6. The reading switch element T5 can be a transistor T5.

In some embodiments of the present application, referring to FIG. 7 , the photosensitive unit 10 further includes a second switch element T4 connected to the photosensitive element PD.

The control end of the second switch element T4 is used to access the reading control signal TX, the first end of the second switch element T4 is electrically connected to the photosensitive element PD to receive the initial photosensitivity signal, and the second end of the second switch element T4 is connected to the photosensitivity signal reading unit 112.

In FIG. 7 , the second switch element T4 may be a sixth transistor T4 , and the second end of the sixth transistor T4 is further connected to the control end (gate) of the signal amplifying element SF.

In some embodiments of the present application, referring to FIG. 7 , the photosensitive pixel structure includes a plurality of photosensitive pixel units, each of the photosensitive pixel units includes at least one photosensitive unit, and the plurality of photosensitive pixel units are connected to the same photosensitive signal reading unit.

In the embodiment of the present application, the photosensitive pixel structure may include N photosensitive pixel units, where N is an integer greater than 0. Each of the photosensitive pixel units may include 1, 4, 9, 16 photosensitive units 10, etc. The present application does not impose any limitation thereto.

In the embodiment of the present application, referring to FIG. 15 , for a synthetic pixel, it includes a plurality of photosensitive pixel units 21, and the photosensitive pixel unit 21 includes a plurality of photosensitive units 10, so that a single color filter (Color Filter, CF) is changed from a single PD to a multi-PD combination. In this regard, there are the following two application scenarios: Scenario 1, performing pixel-by-pixel TCG-HDR on a pixel structure of a color in a pixel array; Scenario 2, performing TCG-HDR on a Bayer array (Red Green Green Blue, RGGB).

For scene 1, each color is composed of four sub-pixels of the same color. Referring to FIGS. 9 and 10 , the photosensitive pixel unit 21 includes four photosensitive units 10 , and the four photosensitive units 10 use the same set of gain mode selection circuits 12 .

For scenario 2, as shown in FIG15, the entire 4×4 pixel group is a unit, that is, there are 4 photosensitive pixel units 21, each photosensitive pixel unit 21 includes 4 photosensitive units 10, and each photosensitive pixel unit 21 is connected to a photosensitive signal processing circuit. Therefore, the pixels in this 4-in-1 Bayer array all use the MCG_SEL signal and LCG_SEL signal provided by the same set of gain mode selection circuits 12. Therefore, in this 4×4 pixel group, only one gain mode selection circuit 11 is required.

In some embodiments of the present application, referring to FIGS. 4 and 7 , the gain processing unit 111 includes a first gain processing subunit 1111 and a second gain processing subunit 1112 ; the first gain processing subunit 1111 includes a second storage capacitor C2 , and the second gain processing subunit 1112 includes a third storage capacitor C1 ;

The first gain processing subunit 1111 is connected to the first selection subcircuit 120 to receive the first mode selection signal, and the second gain processing subunit 1112 is connected to the second selection subcircuit 121 to receive the second mode selection signal. The photosensitive signal processing circuit 11 selects the second storage capacitor C2 and the third storage capacitor C1 to be connected in parallel with the first storage capacitor FD in the photosensitive signal reading unit or selects the third storage capacitor C1 to be connected in parallel with the first storage capacitor FD in the photosensitive signal reading unit according to the first mode selection signal and the second mode selection signal, thereby adjusting the gain processing mode of the photosensitive signal processing circuit for the initial photosensitive signal.

The gate of the transistor T1 included in the first gain processing subunit 1111 is connected to the drain of the transistor M1. The gate of the transistor T2 included in the second gain processing subunit 1112 is connected to the drain of the transistor M2.

It can be understood that the photosensitive signal processing circuit selects the second storage capacitor and the third storage capacitor to be connected in parallel with the first storage capacitor in the photosensitive signal reading unit, or selects the third storage capacitor to be connected in parallel with the first storage capacitor in the photosensitive signal reading unit.

7, the second storage capacitor C2 and the third storage capacitor C1 are connected in parallel with the first storage capacitor FD. When the second storage capacitor C2 and the third storage capacitor C1 are connected in parallel with the first storage capacitor FD, it is a low gain processing mode LCG. When the third storage capacitor C1 is connected in parallel with the first storage capacitor FD, it is a medium gain processing mode MCG. When the second storage capacitor C2 and the third storage capacitor C1 are not connected in parallel with the first storage capacitor FD, that is, when the second storage capacitor C2, the third storage capacitor C1 and the first storage capacitor FD are all disconnected, it is a high gain processing mode HCG.

When the first mode selection signal is at the first level and the second mode selection signal is at the first level, the light-sensing signal processing circuit operates in the low-gain processing mode;

For example, in Figure 7, the first mode selection signal output by the first selection subcircuit is a high level 1, and the second mode selection signal output by the second selection subcircuit is a high level 1, T1 and T2 are turned on, C1 and C2 are connected in parallel with FD, the photosensitive signal is dispersed to C1 and C2, and the photosensitive signal processing circuit operates in the low gain processing mode LCG.

When the first mode selection signal is at the second level and the second mode selection signal is at the first level, the light-sensing signal processing circuit operates in the medium gain processing mode.

For example, in Figure 7, the first mode selection signal output by the first selection sub-circuit is a low level 0, and the second mode selection signal output by the second selection sub-circuit is a high level 1, T1 is disconnected, T2 is turned on, C1 is connected in parallel with FD, C2 is disconnected, the photosensitive signal is dispersed to C1, and the photosensitive signal processing circuit operates in the medium gain processing mode MCG.

When the second mode selection signal is at the second level, the light-sensing signal processing circuit operates in the high-gain processing mode.

For example, the second mode selection signal output by the second selection subcircuit in FIG. 7 is low level 0, T2 is disconnected, C1 and C2 are disconnected from the first storage capacitor FD, all photosensitive signals are amplified and output, and the photosensitive signal processing circuit operates in the high gain processing mode HCG.

It should be noted that, in the embodiment of the present application, when the second mode selection signal output by the second selection subcircuit is low level 0, the first mode selection signal output by the first selection subcircuit can be low level 0 or high level 0, which does not affect the disconnection of C1 and C2 from the first storage capacitor FD. Of course, the first mode selection signal output by the first selection subcircuit can be set to low level 0, so that energy consumption can be reduced.

In some embodiments of the present application, referring to FIG. 7 , the first gain processing subunit 1111 further includes a first mode switching switch element T1; a control end of the first mode switching switch element T1 is connected to the first selection subcircuit 120 for accessing the first mode selection signal, a first end of the first mode switching switch element T1 is connected to a first end of the second storage capacitor C2; a second end of the first mode switching switch element is connected to the second gain processing subunit 1112;

The second gain processing subunit 1112 also includes a second mode switching switch element T2; the control end of the second mode switching switch element T2 is connected to the second selection subcircuit 121 for accessing the second mode selection signal, the first end of the second mode switching switch element T2 is connected to the first end of the third storage capacitor C1, and the first end of the second mode switching switch element T2 is also connected to the second end of the first mode switching switch element T1; the second end of the second mode switching switch element T2 is connected to the first storage capacitor FD A first end is connected;

A second end of the second storage capacitor C2 is grounded, a second end of the first storage capacitor FD is grounded, and a second end of the third storage capacitor C1 is grounded.

As shown in FIG7 , the control end of the first mode switching switch element T1 is also connected to the first end of the cache capacitor C4. As shown in FIG8 , the control end of the first mode switching switch element T1 can be connected to the output end of the transistor M1. The control end of the second mode switching switch element T2 is also connected to the first end of the cache capacitor C3. The control end of the second mode switching switch element T2 can be connected to the output end of the transistor M2.

In some embodiments of the present application, referring to FIG. 7 , the light-sensing signal processing circuit 11 further includes a reset unit 113 , the reset unit 113 is connected to the gain processing unit 111 , and the reset unit 113 is used to reset the light-sensing signal processing circuit 11 ;

The reset unit includes a reset switch element T3, a control end of the reset switch element T3 is used to access a reset control signal RST, a first end of the reset switch element T3 is connected to a power signal, and a second end of the reset switch element T3 is connected to a first end of the first mode switching switch element T1.

In one embodiment, when the control end of the reset switch element T3 is loaded with a first level (high level), the light-sensing signal processing circuit 11 is reset. When the control end of the reset switch element T3 is loaded with a second level (low level), the two mode selection signals output by the two selection signal output ends enable the light-sensing signal processing circuit 11 to select a certain working mode.

As shown in FIG. 7 , the reset switch element T3 is a transistor T3.

In the embodiment of the present application, as shown in FIG8 , compared with FIG7 , the only difference is that a first transistor M1 is provided between the first node and the first selection signal output terminal. The first node is a connection point between the second end of M4 and the first end of C4, and a first transistor M2 is provided between the second node and the second selection signal output terminal. The second node is a connection point between the second end of M3 and the first end of C3.

In the embodiment of the present application, FIG. 9 corresponds to the pixel structure of each pixel unit in the 4-in-1 pixel array. Referring to FIG. 9 , compared with FIG. 7 , the gain mode selection circuit 12 is the same, except that the photosensitive pixel unit 21 includes four photosensitive units 10 with the same structure; wherein the first photosensitive unit includes a first photodiode PD1 and a transistor M4a; the second photosensitive unit includes a second photodiode PD2 and a transistor M4b; the third photosensitive unit includes a third photodiode PD3 and a transistor M4c; the fourth photosensitive unit includes a fourth photodiode PD4 and a transistor M4d; the positive electrode of PD1 is connected to G ND; the negative electrode of PD1 is connected to the first electrode of M4a; the control electrode of PD1 is connected to the control signal TX1; the positive electrode of PD2 is connected to GND; the negative electrode of PD2 is connected to the first electrode of M4b; the control electrode of PD2 is connected to the control signal TX2; the positive electrode of PD3 is connected to GND; the negative electrode of PD3 is connected to the first electrode of M4c; the control electrode of PD3 is connected to the control signal TX3; the positive electrode of PD4 is connected to GND; the negative electrode of PD4 is connected to the first electrode of M4d; the control electrode of PD4 is connected to the control signal TX4; the output ends (drains) of M4a, M4b, M4c, and M4d are all connected to the photosensitive signal processing circuit 11.

In the embodiment of the present application, referring to FIG. 10, compared with FIG. 9, the only difference is that a first transistor M1 is provided between the first node and the first selection signal output terminal. The first node is the second terminal of M4 and the first terminal of C4. The second node is a connection point between the second end of M3 and the first end of C3, and a first transistor M2 is provided between the second node and the second selection signal output terminal. The second node is a connection point between the second end of M3 and the first end of C3.

In the embodiment of the present application, referring to FIG. 11 , compared with FIG. 7 , the only difference is that the first selection subcircuit 120 in FIG. 7 is replaced with a cache element 123 including a D signal trigger G1, and the second selection subcircuit 121 is replaced with a cache element 124 including a D signal trigger G2.

In an embodiment of the present application, referring to FIG. 12 , compared with FIG. 9 , the only difference is that the first switch element M4 and the first cache capacitor C4 in the first selection subcircuit 120 in FIG. 9 are replaced with a D signal trigger G1, and the first switch element M4 and the first cache capacitor C4 in the second selection subcircuit 121 are replaced with a D signal trigger G2.

In the embodiment of the present application, referring to FIG13 , compared with FIG11 , the only difference is that a transistor M1 is provided between the Q output terminal of the trigger G1 and the first mode selection signal output terminal, and a transistor M2 is provided between the Q output terminal of the trigger G2 and the second mode selection signal output terminal.

In the embodiment of the present application, referring to FIG14 , compared with FIG12 , the only difference is that a transistor M1 is provided between the Q output terminal of the trigger G1 and the first mode selection signal output terminal, and a transistor M2 is provided between the Q output terminal of the trigger G2 and the second mode selection signal output terminal.

It should be noted that the light-sensing signal processing circuit 112 can adopt the structures shown in FIGS. 7 to 14 as well as the structures shown in FIGS. 16 and 17 . As shown in FIG. 16 ,

The positive electrode of PD is connected to the ground terminal; the negative electrode of PD is connected to the first electrode of T4; the control electrode of T4 is connected to the charge output control signal input terminal TX; the second electrode of T4 is connected to the control electrode of SF to form a first connection point; C2 and T1 are connected in series to form a first series branch; C1 and T2 are connected in series to form a second series branch; the first series branch, the second series branch and FD are connected in parallel to form a first parallel branch; the first parallel branch is connected between the first connection point and the ground terminal. The control electrode of T1 is connected to the second mode selection signal, and the control electrode of T2 is connected to the first mode selection signal, so that the photosensitive signal processing circuit switches the processing mode; the first electrode of SF is connected to the power signal input terminal VDD; the second electrode of SF is connected to the first electrode of T5; the second electrode of T5 is connected to the pixel signal output terminal PIX_OUT; the control electrode of T5 is connected to the pixel readout control signal input terminal SEL; the control terminal of T3 is connected to the reset signal input terminal RST; the first electrode of T3 is connected to VDD; the second electrode of T3 is connected to the first connection point.

As shown in Figure 17, compared with Figure 1a, the only difference is that the structure in the photosensitive processing circuit 11 and the connection method of the second pole of T3 have changed, wherein the connection method of T2, C2, FD and the control pole of T1 remains unchanged, T1 is connected in series between the second pole of T3 and the first connection point; T3 and T1 are connected to form a second connection point, and C1 is bridged between the second connection point and the ground terminal.

In some embodiments, the photosensitive signal processing circuit switches between a high gain processing mode, a medium gain processing mode, and a low gain processing mode according to the first mode selection signal and the second mode selection signal output by the gain mode selection circuit.

In some embodiments, when the first mode selection signal is at the first level and the second mode selection signal is at the first level, the photosensitive signal processing circuit operates in the low gain processing mode;

When the first mode selection signal is at the second level and the second mode selection signal is at the first level, the light-sensing signal processing circuit operates in the medium gain processing mode;

When the first mode selection signal is at the second level, the light-sensing signal processing circuit operates in the high-gain processing mode.

Wherein, when the first mode selection signal is at the second level, no matter the first mode selection signal is at a high level or a low level, T1 and T2 are disconnected, and the light-sensing signal will not be dispersed into C1 and C2.

In order to facilitate understanding of the technical solution of the embodiment of the present application, the working principles of the photosensitive unit 10 and the photosensitive processing circuit 11 are introduced:

The photodiode PD in the photosensitive circuit 10 senses light and performs photoelectric conversion in each frame time to generate a charge e-, which is buffered in the first storage capacitor FD (here, FD can be a floating diffusion capacitor) after passing through T4 (usually an N-type metal-oxide-semiconductor (NMOS) transistor. In the reading stage, the charge e- in the first storage capacitor FD will be converted into a corresponding voltage by the amplifying switch element SF (here, SF can be a source follower, that is, a common drain amplifier), and after passing through the T5 switch, it is output to the outside of the pixel structure through PIX_OUT.

T3 is used to reset the first storage capacitor FD to VDD under the action of the reset control signal input by RST. The amplifying switch element SF is used to change the size of the first storage capacitor FD to meet the needs of different modes. Because in the high gain processing mode HCG, the voltage of the first storage capacitor FD needs to be as small as possible; and in the low gain processing mode LCG, the voltage of the first storage capacitor FD needs to be as large as possible. Therefore, by adding T1, T2 and C1, C2 in the pixel structure, by controlling the opening and closing of T1 and T2, the pixel structure is switched between the three modes of HCG, MCG and LCG.

Among them, C1 is used for the first expansion of FD; C2 is used for further expansion of FD. When the pixel structure needs to work in the high-gain processing mode HCG, T1 and T2 are both in the disconnected state, and FD is responsible for taking over the charge e- transferred from PD. When the pixel structure needs to work in the medium-gain processing mode LCG, T2 is closed, and FD is connected in parallel with C1 to achieve expansion. Among them, T3 must remain disconnected to prevent resetting. Therefore, the charge e- transferred from PD is FD+C1. When the pixel structure needs to work in the low-gain processing mode LCG, T1 and T2 are disconnected at the same time, and FD is connected in parallel with C1 and C2 to achieve further expansion. Among them, T3 must remain disconnected to prevent resetting. Therefore, the charge e- transferred from PD is FD+C1+C2. In short, the essential method to realize the TCG function is to change the size of the FD capacitor as needed.

Then, in the case where the above-mentioned transistor is an N-type MOS tube, the first level is a high level 1, and the second level is a low level 0. In the process of selecting the gain mode in the present application, RST is a low level 0, and T3 is disconnected. Then, when the first mode selection signal is 1 and the second mode selection signal is 1, T1 and T2 are turned on, C1 and C2 are connected in parallel with FD, and both disperse the charge generated by the photosensitive unit, and enter the low gain processing mode LCG. When the first mode selection signal is 0 and the second mode selection signal is 1, T1 is disconnected, T2 is turned on, C1 is connected in parallel with FD to disperse the charge generated by the photosensitive unit, C2 is not connected in parallel with FD, and C2 does not disperse the charge generated by the photosensitive unit, and enters the medium gain processing mode MCG. When the second mode selection signal is 0, T2 is disconnected, C1 and C2 are not connected in parallel with FD, and C1 and C2 do not disperse the charge generated by the photosensitive unit. All photosensitive signals are amplified and enter the high gain processing mode HCG. In this case, T1 is disconnected to save energy.

Wherein, when the second mode selection signal is 0, the first mode selection signal may be 0 or 1. In this case, when the first mode selection signal is 0, power consumption may be saved.

It can be understood that the photosensitive pixel structure provided in the embodiment of the present application is not only applicable to a 4-in-1 pixel array, but can also be extended to a 9-in-1 and 16-in-1 pixel array, which have similar structures.

Similarly, the photosensitive pixel structure provided in the embodiment of the present application can be applied to a CIS with four primary colors (Red, Green, Blue, White, RGBW), rather than just a CIS with a three primary color array (Red, Green, Blue, RGBW). In this case, the implementation methods of the photosensitive processing circuit 11 and the gain mode selection circuit 12 remain unchanged for different pixel array requirements, and only the component structure in the photosensitive circuit 10 is different.

It should be noted that in the embodiments of the present application, M1~M14 and T1-T4 can all be Metal Oxide Semiconductor (MOS) transistors, which can be N-type or P-type. When a certain type of transistor is used, the connection relationship between the gate, source and drain can be adjusted according to the principle of the transistor and the requirements of the circuit of the present application.

In order to understand the technical solution of the embodiment of the present application, based on the above-mentioned photosensitive pixel circuit, the pixel structure driving method of FIG. 7 is now introduced in stages within one frame time:

In the reset phase, DCG_SEL, CLK_CTL, and RST are all high level "1" (ensuring that M3, M4, T3, T1, and T2 are all turned on), and the first refresh is performed to empty the storage capacitors FD, C1, and C2; the end of the reset phase is marked by RST becoming "0", that is, T3 is disconnected.

During the exposure phase, the PD in the photosensitive unit 10 works, senses the light signal to generate charges, and stores the charges in the inherent capacitance of the PD. M6 can be in an off state or in an on state.

In the reading stage, CLK_CTL is at a high level to refresh the actual LCG_SEL into C4, refresh the actual MCG_SEL into C3 (second refresh), and input LCG_SEL into M4 to control the on or off of M4, and input MCG_SEL into M3 to control the on or off of M3, so that the pixel structure works in the mode corresponding to the signals output by C3 and C4; when the signals output by C3 and C4 correspond to HCG, T1 and T2 are turned off, and C1 and C2 are disconnected from FD respectively; TX and SEL are both at high levels, T4 and T5 are turned on, and the charge generated by the photosensitive unit 10 is stored in the FD, and is amplified by SF and output through the output end of the photosensitive signal processing circuit 11. When the signal output by C3 and C4 corresponds to MCG, T1 is turned off, T2 is turned on, C1 is connected in parallel with FD, and C2 is disconnected from FD; TX and SEL are both high level, T4 and T5 are turned on, and the charge generated for the photosensitive unit 10 is stored in FD, amplified by SF and output through the output end of the photosensitive signal processing circuit 11. When the signal output by C3 and C4 corresponds to LCG, T1 and T2 are turned on, C1 and C2 are connected in parallel with FD respectively; TX and SEL are both high level, T4 and T5 are turned on, and the charge generated for the photosensitive unit 10 is stored in FD, amplified by SF and output through the output end of the photosensitive signal processing circuit 11.

It is understandable that, due to the leakage characteristics of M3 and M4 in the embodiment of the present application, the cache of the cache capacitors C3 and C4 has a time limit. Therefore, it must be refreshed after a certain time. The refresh frequency The time required for updating all pixels in the pixel array is not less than the time required for updating once. Here, if the time in the reset phase or the exposure phase exceeds the preset time, it is necessary to refresh as needed (re-flush the mode control signal into the control electrodes of T1 and T2); at the same time, in the reading phase, if T4 and T5 are turned on with a delay, they also need to be refreshed as needed.

On the basis of the above-mentioned embodiment, an embodiment of the present application provides an image sensor, which includes the above-mentioned pixel structure.

Based on the above embodiment, an embodiment of the present application provides an electronic device, which includes the above image sensor.

It should be noted that in the embodiments of the present application, the electronic devices include but are not limited to mobile phones, tablet computers, laptop computers, PDAs, vehicle-mounted terminals, wearable devices, and pedometers, etc.

Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this disclosure.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

Through the description of the above implementation methods, those skilled in the art can clearly understand that the above embodiment method can be implemented by means of software plus a necessary general hardware platform, or by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the relevant technology, can be embodied in the form of a software product, which is stored in a storage medium (ROM, RAM, disk, CD), including a number of instructions for enabling a terminal The terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) executes the methods described in each embodiment of the present application.

It is understood that the embodiments described in the embodiments of the present disclosure can be implemented by hardware, software, firmware, middleware, microcode or a combination thereof. For hardware implementation, modules, units, and sub-units can be implemented in one or more application specific integrated circuits (ASIC), digital signal processors (DSP), digital signal processing devices (DSPD), programmable logic devices (PLD), field programmable gate arrays (FPGA), general-purpose processors, controllers, microcontrollers, microprocessors, other electronic units for performing the functions described in the present disclosure or a combination thereof.

For software implementation, the technology described in the embodiments of the present disclosure can be implemented by a module (such as a process, function, etc.) that performs the functions described in the embodiments of the present disclosure. The software code can be stored in a memory and executed by a processor. The memory can be implemented in the processor or outside the processor.

It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

Although the optional embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including optional embodiments and all changes and modifications that fall within the scope of the present application.

Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity from another entity, and do not necessarily require or imply any such actual relationship or order between these entities. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or terminal device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the article or terminal device including the elements.

The technical solution provided by the present application is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. At the same time, for those skilled in the art, according to the principles and implementation methods of the present application, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present application.

Claims (20)

A photosensitive pixel structure, comprising a photosensitive unit, a photosensitive signal processing circuit and a gain mode selection circuit; The photosensitive unit includes a photosensitive element for generating an initial photosensitive signal, and the photosensitive unit is connected to the photosensitive signal processing circuit; The gain mode selection circuit outputs a gain mode selection signal, and the gain mode selection circuit is connected to the photosensitive signal processing circuit; The photosensitive signal processing circuit includes a photosensitive signal reading unit and a gain processing unit, wherein the photosensitive signal reading unit is connected to the photosensitive unit to receive the initial photosensitive signal, the gain processing unit is connected to the gain mode selection circuit to receive the gain mode selection signal, and the gain processing unit is connected to the photosensitive signal reading unit; The gain mode selection circuit comprises a first selection subcircuit and a second selection subcircuit, the gain mode selection signal output by the first selection subcircuit is a first mode selection signal, and the gain mode selection signal output by the second selection subcircuit is a second mode selection signal; The photosensitive signal processing circuit determines a gain processing mode for the initial photosensitive signal according to the gain mode selection signal. According to the photosensitive pixel structure according to claim 1, wherein the photosensitive signal processing circuit further includes a reset unit, the reset unit is connected to the gain processing unit, and the reset unit is used to reset the photosensitive signal processing circuit. The photosensitive pixel structure according to claim 1, wherein: The first selection subcircuit has a first selection signal input terminal, a first selection signal output terminal and a first selection control signal input terminal, and the first selection signal output terminal is electrically connected to the gain processing unit; the first selection signal input terminal is used to access a first initial selection signal, the first selection control signal input terminal is used to access a first selection control signal, and the first selection signal output terminal is used to output the first mode selection signal according to the first initial selection signal under the control of the first selection control signal; The second selection subcircuit has a second selection signal input terminal, a second selection signal output terminal and a second selection control signal input terminal, and the second selection signal output terminal is electrically connected to the gain processing unit; the second selection signal input terminal is used to access the second initial selection signal, the second selection control signal input terminal is used to access the second selection control signal, and the second selection signal output terminal is used to output the second mode selection signal according to the second initial selection signal under the control of the second selection control signal. The photosensitive pixel structure according to claim 3, wherein the first selection subcircuit further comprises a first cache element and a first selection switch element, The first cache element is electrically connected to the first selection signal input terminal, the first cache element is electrically connected to the first selection signal output terminal, and the first cache element is used to store the first initial selection signal or the first mode selection signal; The first end of the first selection switch element is connected to the first selection signal output end to receive the first mode selection signal, the second end of the first selection switch element is connected to the gain processing unit, and the control end of the first selection switch element is connected to the first enable control signal to output the first mode selection signal to the gain processing unit when it is necessary to switch the gain processing mode of the initial photosensitive signal. The photosensitive pixel structure according to claim 3, wherein the first selection subcircuit comprises a first switch element and a first cache capacitor; The control end of the first switch element is the first selection control signal input end, the first end of the first switch element is the first selection signal input end, the second end of the first switch element is electrically connected to the first end of the first cache capacitor, the first end of the first cache capacitor is electrically connected to the first selection signal output end, and the second end of the first cache capacitor is grounded. The photosensitive pixel structure according to claim 3, wherein the first selection subcircuit includes a first trigger, and the first trigger has the first selection signal input terminal, the first selection signal output terminal and the first selection control signal input terminal. The photosensitive pixel structure according to claim 6, wherein the first trigger is a digital signal trigger, and the first trigger also has a setting signal terminal and a reset signal terminal; when the setting signal terminal is loaded with a first level, the first mode selection signal output by the first selection signal output terminal causes the photosensitive signal processing circuit to operate in a first gain processing mode; when the reset signal terminal is loaded with a second level, the first mode selection signal output by the first selection signal output terminal and the second mode selection signal output by the second selection subcircuit cause the photosensitive signal processing circuit to operate in a second gain processing mode. The photosensitive pixel structure according to claim 3, wherein the first selection subcircuit includes a first digital signal buffer, the first digital signal buffer having the first selection signal input terminal, the first selection signal output terminal, the first selection control signal input terminal, and a digital signal cache unit for storing the first initial selection signal or the first mode selection signal. The photosensitive pixel structure according to claim 3, wherein the first selection subcircuit comprises a first cache element, and the first cache element comprises: a first switch element and a digital signal cache unit; The digital signal buffer unit includes a first switch tube, a second switch tube, a third switch tube, and a fourth switch tube; The control end of the first switch element is the first selection control signal input end, the first end of the first switch element is the first selection signal input end, the second end of the first switch element is electrically connected to the first end of the first switch tube, and the second end of the first switch element is also electrically connected to the second end of the second switch tube; The first switch tube is of N type, the control end of the first switch tube is electrically connected to the control end of the second switch tube, and the second end of the first switch tube is grounded; The second switch tube is of P type, the control end of the second switch tube is electrically connected to the first end of the third switch tube, the first end of the second switch tube is connected to the power signal, and the second end of the second switch tube is electrically connected to the The control end of the third switch tube is electrically connected; The third switch tube is of N type, a first end of the third switch tube is electrically connected to a second end of the fourth switch tube, and a second end of the third switch tube is grounded; The fourth switch tube is of P type, the control end of the fourth switch tube is electrically connected to the control end of the third switch tube, the first end of the fourth switch tube is connected to the power signal, and the second end of the fourth switch tube is electrically connected to the first selection control signal output end. The photosensitive pixel structure according to any one of claims 5 to 9, wherein the first selection subcircuit also includes a first selection switch element, a first end of the first selection switch element is connected to the first selection signal output end to receive the first mode selection signal, a second end of the first selection switch element is connected to the gain processing unit, and a control end of the first selection switch element is used to access a first enable control signal to output the first mode selection signal to the gain processing unit when it is necessary to switch the gain processing mode of the initial photosensitive signal. The photosensitive pixel structure according to claim 1, wherein the photosensitive signal reading unit comprises a first storage capacitor, a signal amplifying element and a reading switch element; The first end of the first storage capacitor is electrically connected to the photosensitive unit to receive the initial photosensitive signal, the first end of the first storage capacitor is also connected to the gain processing unit, and the second end of the first storage capacitor is grounded; The input end of the signal amplifying element is connected to the first end of the first storage capacitor, and the output end of the signal amplifying unit is connected to the first end of the reading switch element for outputting the amplified light-sensing signal; The control end of the reading switch element is used to access the output control signal, and the second end of the reading switch element is the photosensitive signal output end of the photosensitive pixel structure. According to the photosensitive pixel structure of claim 11, the signal amplifying element is an amplifying switch element, the control end of the amplifying switch element is connected to the first end of the first storage capacitor, the first end of the amplifying switch element is connected to the power supply signal, and the second end of the amplifying switch element is electrically connected to the first end of the second reading switch element. A photosensitive pixel structure according to claim 1 or any one of claims 11 to 12, wherein the photosensitive pixel structure comprises a plurality of photosensitive pixel units, each of the photosensitive pixel units comprises at least one photosensitive unit, and the plurality of photosensitive pixel units are connected to the same photosensitive signal reading unit. The photosensitive pixel structure according to claim 1, wherein the gain processing unit comprises a first gain processing subunit and a second gain processing subunit; the first gain processing subunit comprises a second storage capacitor, and the second gain processing subunit comprises a third storage capacitor; The first gain processing subunit is connected to the first selection subcircuit to receive the first mode selection signal, the second gain processing subunit is connected to the second selection subcircuit to receive the second mode selection signal, and the photosensitive signal processing circuit selects the second storage capacitor and the third storage capacitor to be connected to the first storage capacitor in the photosensitive signal reading unit according to the first mode selection signal and the second mode selection signal. The storage capacitor is connected in parallel or the third storage capacitor is selected to be connected in parallel with the first storage capacitor in the photosensitive signal reading unit, so as to adjust the gain processing mode of the photosensitive signal processing circuit for the initial photosensitive signal. The photosensitive pixel structure according to claim 14, wherein: The first gain processing subunit further includes a first mode switching switch element; a control end of the first mode switching switch element is connected to the first selection subcircuit for accessing the first mode selection signal, a first end of the first mode switching switch element is connected to a first end of the second storage capacitor; a second end of the first mode switching switch element is connected to the second gain processing subunit; The second gain processing subunit further includes a second mode switching switch element; a control end of the second mode switching switch element is connected to the second selection subcircuit for accessing the second mode selection signal, a first end of the second mode switching switch element is connected to the first end of the third storage capacitor, and the first end of the second mode switching switch element is also connected to the second end of the first mode switching switch element; and a second end of the second mode switching switch element is connected to the first end of the first storage capacitor; A second end of the second storage capacitor is grounded, and a second end of the first storage capacitor is grounded. The photosensitive pixel structure according to claim 15, wherein the photosensitive signal processing circuit further comprises a reset unit, the reset unit is connected to the gain processing unit, and the reset unit is used to reset the photosensitive signal processing circuit; The reset unit includes a reset switch element, a control end of the reset switch element is used to access a reset control signal, a first end of the reset switch element is connected to a power signal, and a second end of the reset switch element is connected to a first end of the first mode switching switch element. The photosensitive pixel structure according to claim 1, wherein the photosensitive signal processing circuit switches between a high gain processing mode, a medium gain processing mode and a low gain processing mode according to the first mode selection signal and the second mode selection signal output by the gain mode selection circuit. The photosensitive pixel structure according to claim 17, wherein: When the first mode selection signal is at the first level and the second mode selection signal is at the first level, the light-sensing signal processing circuit operates in the low-gain processing mode; When the first mode selection signal is at the second level and the second mode selection signal is at the first level, the light-sensing signal processing circuit operates in the medium gain processing mode; When the second mode selection signal is at the second level, the light-sensing signal processing circuit operates in the high-gain processing mode. An image sensor, comprising a photosensitive pixel structure as claimed in any one of claims 1 to 17. An electronic device, comprising the image sensor as claimed in claim 18.