WO2023236443A1 - Processor, electronic device and multi-thread shared instruction prefetching method - Google Patents

Abstract

A processor, an electronic device and a multi-thread shared instruction prefetching method, relating to the technical field of computers. The processor comprises: an instruction cache and a thread group unit. The thread group unit is configured to send a first instruction prefetching request to the instruction cache, the first instruction prefetching request being used for obtaining an instruction corresponding to a thread group to be created within a period of time in the future; the instruction cache is configured to perform instruction prefetching in response to the first instruction prefetching request. Before a thread group is created, a first instruction prefetching request used for obtaining an instruction corresponding to a thread group to be created within a period of time in the future is sent to an instruction cache in advance, so that the instruction cache has enough time to perform instruction prefetching in advance, and thus the probability of subsequent instruction access failure can be reduced, and the effect is particularly obvious for a new thread.

Description

An instruction prefetching method shared by processors, electronic devices and multi-threads

Cross-references to related applications

This application requests the priority of the Chinese patent application with application number 202210649455.0 and titled "A processor, electronic device and multi-thread shared instruction prefetching method" submitted to the State Intellectual Property Office of China on June 10, 2022. The entire contents of which are incorporated herein by reference.

Technical field

The present application belongs to the field of computer technology, and specifically relates to a processor, an electronic device, and a multi-thread shared instruction prefetching method.

Background technique

Processor instruction fetch performance is very important. The instruction cache is usually designed to alleviate the delay problem of instruction fetch access. If the instruction fetch request hits the instruction cache, the instruction can be obtained immediately. If the instruction fetch request does not hit the instruction cache, the instruction fetch request needs to be sent to the next level cache or main memory to obtain the instruction. Usually this type of processing requires a long response time, thereby reducing performance.

In order to improve the hit rate of instruction fetch requests in the instruction cache, reduce the instruction fetch delay, and prevent the system from stalling due to insufficient instruction supply, instruction prefetching technology is proposed. The key points of instruction prefetch quality are controlling the timing of instruction prefetching (too early or too late will affect the effect of instruction prefetching) and avoiding repeated prefetching by multi-thread groups (wasting prefetching bandwidth).

The instruction fetching method of current instruction prefetching technology is mainly to prefetch in sequence or jump prefetching according to a fixed step size, that is, to prefetch the next fixed number of instructions based on the position of the existing instruction fetch request. This instruction prefetching method The time margin is insufficient and the prefetching is not timely enough. As a result, if there is an instruction fetch request to access the prefetch instruction, there is a high probability that the prefetch action of the prefetch instruction has just occurred or is in progress (that is, the corresponding prefetch instruction has not yet been has not been obtained), especially for a newly started new thread, due to the relatively long cold start time of the new thread, the initial fetch requests of the new process are all access failures (misses), and it takes a long time to obtain them. to the corresponding instruction, thus failing to achieve the purpose of prefetching.

Contents of the invention

In view of this, the purpose of this application is to provide an instruction prefetching method shared by processors, electronic devices, and multi-threads to improve the existing instruction prefetching technology that causes insufficient prefetching in a timely manner, resulting in a high probability of instruction access failure. The problem of waiting for a long time to get the corresponding instructions.

Some embodiments of the present application provide a processor, including: an instruction cache and a thread group unit; the thread group unit is configured to send a first instruction prefetch request to the instruction cache, and the first instruction prefetch request is sent to the instruction cache. The fetch request is used to obtain instructions corresponding to the thread group to be created in the future; the instruction cache is configured to perform instruction prefetching in response to the first instruction prefetch request.

In some embodiments of the present application, before creating a thread group, the first instruction prefetch request for obtaining instructions corresponding to the thread group to be created in the future is sent to the instruction cache in advance, so that the instruction cache has enough Prefetch instructions in advance of the time, which can reduce the probability of subsequent instruction access failures, especially for new threads, the effect is particularly obvious.

In conjunction with a possible implementation of some embodiments of the present application, the first instruction prefetch request may include: fetch address information and the number of prefetched instructions, and the instruction cache responds to the first instruction prefetch request. Instruction prefetching may include: the instruction cache responds to the first instruction prefetch request, obtains the number of prefetched instructions from a later-level cache according to the fetch address information, and stores them in the instruction cache. .

In conjunction with a possible implementation of some embodiments of the present application, the processor may further include: an instruction fetching unit; the thread group unit may also be configured to distribute the created thread group to the instruction fetching unit ; The instruction fetch unit may be configured to issue a corresponding instruction fetch request based on the received thread group; the instruction cache may also be configured to respond to the instruction fetch request and return the instruction hit by the instruction fetch request. .

In some embodiments of the present application, the created thread group is distributed to the instruction fetch unit, so that the instruction fetch unit issues the corresponding instruction fetch request based on the received thread group, and obtains the corresponding instruction from the instruction cache for subsequent processing. Operation, in addition, since the instruction fetch request is sent after the first instruction prefetch request, this can reduce the probability of subsequent instruction access failure, especially for new threads, the effect is particularly obvious.

In conjunction with a possible implementation of some embodiments of the present application, the number of instruction fetching units may be multiple.

In conjunction with a possible implementation manner of the embodiment of the present application, the instruction fetching unit may also be configured to monitor the storage amount of instructions corresponding to each thread group that have been prefetched into the instruction cache. When the amount is less than the preset threshold, a second instruction prefetch request is sent to the instruction cache; the instruction cache may also be configured to perform instruction prefetching in response to the second instruction prefetch request.

In some embodiments of the present application, by monitoring the storage amount of instructions that have been prefetched into the instruction cache corresponding to each thread group, when the cached instruction storage amount is less than a preset threshold, a second instruction prefetch is sent to the instruction cache. The request is to facilitate instruction prefetching in advance to increase the probability of subsequent instruction fetch requests hitting instructions and shorten the waiting time for instruction fetching.

In conjunction with a possible implementation manner of some embodiments of the present application, the instruction cache may be further configured to: before performing instruction prefetching in response to the second instruction prefetch request, after receiving the second instruction prefetch request, When a fetch request is made, it is determined that the second instruction prefetch request does not exist in the prefetch status table, wherein the prefetch status table is used to record the second instruction prefetch request in progress, or the second instruction prefetch request that has been completed within a period of time. Second instruction prefetch request.

In some embodiments of the present application, before performing instruction prefetching in response to the second instruction prefetching request, the instruction cache first determines that there is no second instruction prefetching request in the prefetch status table, and then responds to the second instruction prefetching request. Instruction prefetching can avoid repeated prefetching and waste of prefetching bandwidth.

In conjunction with a possible implementation manner of some embodiments of the present application, the instruction cache may be further configured to, when receiving a second instruction prefetch request, record the received second instruction prefetch request in the cache. Get the status table.

In some embodiments of the present application, the received second instruction prefetch request is recorded in the prefetch status table to facilitate the management of the second instruction prefetch request and learn the instruction prefetch of the second instruction prefetch request. Condition.

In conjunction with a possible implementation manner of some embodiments of the present application, the instruction cache may be configured specifically: in the prefetch status table, there is no data from the received second instruction prefetch request. If there are other instruction prefetch requests of the corresponding thread group, the received second instruction prefetch request will be directly recorded in the prefetch status table; or, if there is an instruction prefetch request from the corresponding thread group in the prefetch status table Other instruction prefetch requests of the thread group corresponding to the received second instruction prefetch request are updated, and the prefetch range of the other instruction prefetch requests is updated. The updated prefetch range of the other instruction prefetch requests includes The prefetch range of the received second instruction prefetch request.

In some embodiments of the present application, when recording the received second instruction prefetch request in the prefetch status table, if there are no other instruction prefetch requests from the same thread group in the prefetch status table, then the received second instruction prefetch request will be recorded directly in the prefetch status table. The received second instruction prefetch request is recorded in the prefetch status table. If there are other instruction prefetch requests from the same thread group, the prefetch ranges of other instruction prefetch requests are updated to the updated prefetch range. The fetch range includes the prefetch range of the received second instruction prefetch request, so that repeated prefetching and waste of prefetch bandwidth can be avoided in the future.

In conjunction with a possible implementation of some embodiments of the present application, the priority of the instruction cache in responding to the first instruction prefetch request may be lower than the priority of responding to the second instruction prefetch request.

In some embodiments of the present application, by making the priority of the instruction cache to respond to the first instruction prefetch request be lower than the priority of responding to the second instruction prefetch request, instructions can be processed for the thread group by utilizing the idle bandwidth of the instruction cache. Prefetching, so that it does not affect the normal memory access performance of the instruction cache.

In conjunction with a possible implementation of some embodiments of the present application, the instruction cache may be configured to delete the expired prefetch range and the expired second instruction prefetch request in the prefetch status table.

In conjunction with a possible implementation of some embodiments of the present application, the second instruction prefetch request may include instruction fetch address information and the number of prefetched instructions.

Other embodiments of the present application also provide an electronic device, including a body and a processor as provided in any of the above-mentioned embodiments of the present application and/or in combination with any possible implementation of some embodiments of the present application.

Some embodiments of the present application also provide a multi-thread shared instruction prefetching method, including: the instruction cache obtains a first instruction prefetch request sent by a thread group unit, wherein the first instruction prefetch request is The thread group unit sends it before creating the thread group. The first instruction prefetch request is used to obtain instructions corresponding to the thread group to be created in the future; the instruction cache responds to the first instruction prefetch request. Perform instruction prefetching.

In conjunction with a possible implementation of some embodiments of the present application, the first instruction prefetch request may include: fetch address information and the number of prefetched instructions, and the instruction cache responds to the first instruction prefetch request. Performing instruction prefetching may include: the instruction cache responds to the first instruction prefetch request, obtains the number of prefetched instructions from a later-level cache according to the instruction fetch address information, and stores them in the instruction In cache.

In conjunction with a possible implementation of some embodiments of the present application, the method may further include: the instruction cache receiving a second instruction prefetch request issued from the instruction fetch unit, wherein the second instruction prefetch request The fetch request is sent when the storage amount of instructions prefetched into the instruction cache corresponding to the thread group is less than a preset threshold; the instruction cache performs instruction prefetching in response to the second instruction prefetch request.

In conjunction with a possible implementation manner of some embodiments of the present application, before the instruction cache performs instruction prefetching in response to the second instruction prefetch request, the method may further include: the instruction cache receives When the second instruction prefetch request is made, it is determined that the second instruction prefetch request does not exist in the prefetch status table, wherein the prefetch status table is used to record the ongoing second instruction prefetch request, or Second instruction prefetch requests that have completed within a certain period of time.

In conjunction with a possible implementation manner of some embodiments of the present application, the method may further include: when receiving the second instruction prefetch request, there is no instruction in the prefetch status table from the received instruction prefetch request. For other instruction prefetch requests of the thread group corresponding to the second instruction prefetch request, the received second instruction prefetch request is directly recorded in the prefetch status table; or, in the prefetch status There are other instruction prefetch requests from the thread group corresponding to the received second instruction prefetch request in the table. The prefetch range of the other instruction prefetch requests is updated. The updated other instruction prefetch requests are The prefetch range of the fetch request includes the prefetch range of the received second instruction prefetch request.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments of the application. The objectives and other advantages of the present application may be realized and attained by the structure particularly pointed out in the written description and accompanying drawings.

Description of the drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings needed to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some implementations of the present application. For example, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts. The above and other objects, features and advantages of the present application will become clearer as shown in the accompanying drawings. The same reference numbers refer to the same parts throughout the drawings. The drawings are not intentionally scaled to actual size and are focused on illustrating the gist of the present application.

Figure 1 shows a schematic structural diagram of a processor provided by an embodiment of the present application.

FIG. 2 shows a schematic structural diagram of yet another processor provided by an embodiment of the present application.

FIG. 3 shows a schematic structural diagram of an electronic device provided by an embodiment of the present application.

FIG. 4 shows a schematic flowchart of a multi-thread shared instruction prefetching method provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

It should be noted that similar reference numerals and letters represent similar items in the following figures, therefore, once an item is defined in one figure, it does not need further definition and explanation in subsequent figures. At the same time, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that these entities or any such actual relationship or sequence between operations. Furthermore, the terms "comprises," "comprises," or any other variations thereof are intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also those not expressly listed other elements, or elements inherent to the process, method, article or equipment. Without further limitation, an element defined by the statement "comprises a..." does not exclude the presence of additional identical elements in a process, method, article, or apparatus that includes the stated element.

In the description of this application, it should also be noted that, unless otherwise clearly stated and limited, the terms "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection, or Integrated connection; it can also be electrical connection; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be internal connection between two components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood on a case-by-case basis.

Furthermore, the term "and/or" in this application is only an association relationship describing related objects, indicating that there can be three relationships. For example, A and/or B can mean: A alone exists, and A and A exist simultaneously. B, there are three situations of B alone. The term "plurality" refers to two or more than two unless otherwise stated.

In view of the shortcomings of the existing instruction prefetch technology, for example, because the prefetch is not timely enough, if an instruction fetch request accesses the prefetch instruction, there is a high probability that the prefetch action of the prefetch instruction has just occurred or is in progress. (that is, the corresponding prefetch instruction has not yet been obtained), especially for a new thread that has just been started. Since the cold start time of the new thread is relatively long, all the initial fetch requests of the new process are access failures (misses). , it takes a long time to get the corresponding instructions.

Based on this, embodiments of the present application provide a new multi-thread shared instruction prefetching method, which can effectively reduce the probability of instruction access failure and reduce the waiting time for instruction fetching requests, especially for new threads. Especially obvious.

For a better understanding, the following is explained in conjunction with the processor shown in Figure 1. The processor may include: an instruction cache and a thread group unit, and the instruction cache and the thread group unit may be connected.

The thread group unit is responsible for creating the thread group. Since the cold start time of the new thread is relatively long, in order to reduce the probability of instruction access failure and reduce the waiting time of the instruction fetch request. The thread group unit can be configured to send the first instruction prefetch request to the instruction cache in advance before creating the thread group. The first instruction prefetch request can be used to obtain a period of time in the future (the length of time can be configured according to application requirements). ), so that there is enough time to prefetch instructions in advance, which can reduce the probability of instruction access failure, especially for new threads, the effect is particularly obvious.

Among them, the first instruction prefetch request carries control information for instruction prefetching, for example, fetch address information (to obtain the global access address of the instruction) and the number of prefetched instructions (used to indicate the number of instructions that need to be prefetched, Its value can be flexibly configured as needed). If the access addresses of the instructions to be prefetched are continuous, the fetch address information may only include the first address information of the fetched instruction, and it is enough to continuously fetch instructions as many as the prefetched instructions starting from the first address information. If the access addresses of the instructions to be prefetched are not consecutive, the fetch address information needs to include the access addresses corresponding to the number of prefetched instructions. For example, if the number of prefetched instructions is 32, the fetch address information needs to include the access addresses corresponding to the fetched 32 instructions.

A thread group can include multiple (such as 16, 32, 64, etc.) threads that obtain the same instruction. Multiple threads that obtain the same instruction are divided into the same thread group so that they can be fetched simultaneously by sending an instruction request. Obtain the instructions required by multiple threads and improve the efficiency of instruction acquisition.

The instruction cache may be configured to perform instruction prefetching in response to the first instruction prefetch request. The first instruction prefetch request may include: fetch address information and the number of prefetched instructions. The instruction cache is specifically configured to respond to the first instruction prefetch request, obtain instructions with the number of prefetched instructions from the subsequent level cache (next level cache or main memory) according to the fetch address information, and store them in the instruction cache. For example, assuming that the number of prefetched instructions is 64, 64 instructions are fetched from the lower-level cache based on the fetch address information.

It should be noted that the number of prefetch instructions can be flexibly configured as needed and is not limited to 64 or 32 in the above example. Therefore, the 32 and 64 in the example cannot be understood as a limitation on the present application.

Optionally, the priority of the first instruction prefetch request is relatively low, so that it will not affect the normal memory access work of the instruction cache, and the idle bandwidth of the instruction cache is used to prefetch instructions for the new thread group to reduce the number of thread groups. The cold start time and the number of prefetched instructions can be flexibly configured to obtain the best performance according to different application scenarios. When the instruction cache has a heavy workload, such as when receiving a first instruction prefetch request, the instruction cache may be performing instruction fetch of an earlier created thread group, and the first instruction prefetch request will Due to the backlog of no response, if the thread group corresponding to the first instruction prefetch request has finished executing, the first instruction prefetch request will be invalid and will be automatically deleted.

In the embodiment of this application, before creating a thread group, the first instruction prefetch request for obtaining instructions corresponding to the thread group to be created in the future is sent to the instruction cache in advance, so that the instruction cache has enough time. Perform instruction prefetching in advance, which can reduce the probability of subsequent instruction access failures, especially for new threads, the effect is particularly obvious.

In one embodiment, the processor further includes an instruction fetching unit, the schematic diagram of which is shown in Figure 2 . The instruction fetch unit is connected to the thread group unit and the instruction cache respectively.

The thread group unit can also be configured to distribute created thread groups to the fetch unit. A period of time after the thread group unit sends the first instruction prefetch request (which can be configured as needed), the thread group unit will formally create the thread group corresponding to the first instruction prefetch request, and then distribute the created thread group to Fetch unit.

Optionally, in order to support parallel multi-threaded instruction fetching, the number of instruction fetching units can be multiple (two or two). The specific value of the instruction fetching unit can be determined according to the requirements of parallel instruction fetching. For example, if it needs to support If 8 thread groups concurrently fetch instructions, the number of instruction fetch units is 8. If 16 thread groups need to support concurrent instruction fetching, the number of instruction fetch units is 16.

Each instruction fetch unit has the same function, for example, it is used to issue an instruction fetch request to the instruction cache based on the thread group. Each instruction fetch request carries a global access address, and the instruction can be fetched based on the access address. The instruction cache may also be configured to respond to an instruction fetch request and return to the instruction fetch unit the instruction hit by the instruction fetch request. If the instruction fetch request hits the instruction cache, the instruction can be obtained immediately. If the instruction fetch request does not hit the instruction cache, the instruction cache needs to send the instruction fetch request to the subsequent level cache (next level cache or main memory) to obtain the instruction.

Optionally, the instruction fetching unit can also be configured to monitor the storage amount of instructions that have been prefetched into the instruction cache corresponding to each thread group, and when it is detected that the storage amount is less than a preset threshold (flexibly configurable), The instruction cache sends a second instruction prefetch request. The instruction cache may also be configured to perform instruction prefetching in response to a second instruction prefetch request. The instruction fetch unit can monitor the consumption status of the prefetch instructions of each thread group. When it detects that the prefetch instruction storage amount is insufficient (less than the preset threshold), it starts the second instruction prefetch request of the thread group and sends the instruction to the instruction fetcher. The cache sends a second instruction prefetch request.

For ease of understanding, an example is given below. Assuming that the preset threshold is 32, it means that when the storage amount of instructions that have been prefetched into the instruction cache corresponding to the thread group is less than 32, instruction prefetching is required. For example, assuming that a thread group (assuming that the thread group requires a total of 192 instructions) is not created, the instruction cache prefetches the 128 instructions required by the thread group in advance, and then when the instruction fetch unit starts executing the thread group, An instruction fetch request will be issued to the instruction cache to obtain the corresponding instruction. When the 97th instruction is obtained, because the cached instruction storage amount is lower than the preset threshold (32 at this time), an instruction fetch request will be issued to the instruction cache. Issue a second instruction prefetch request to obtain instructions after the thread group, such as the 129th to 160th instructions. After that, when the 129th instruction is fetched, since the cached instruction storage amount (31) is lower than the preset threshold (32 at this time), a second instruction prefetch request will be sent to the instruction cache to fetch it. The instructions after the thread group, for example, get the 161st to 192nd instructions. It should be noted that the examples shown here are only for the convenience of understanding. The above instruction fetch unit monitors the storage amount of instructions that have been prefetched into the instruction cache corresponding to each thread group, and issues the instruction when the storage amount is insufficient. The second instruction prefetch request explains the principle of prefetching instructions. Various special values in the above examples should not be understood as limitations on this application.

The second instruction prefetch request is similar to the first instruction prefetch request, and also carries control information for instruction prefetching, for example, fetch address information (to obtain the global access address of the instruction) and the number of prefetched instructions (used in Yu represents the number of instructions that need to be prefetched, and its value can be flexibly configured as needed).

The instruction fetch unit can calculate the storage amount of instructions that have been prefetched into the instruction cache corresponding to each thread group based on the number of instructions that have been prefetched and the number of instructions consumed (the number of instructions that the instruction fetch unit normally fetches). For example, for a certain thread group, assuming that the number of instructions prefetched by the instruction fetch unit is 64 and the number of instructions consumed is 32, then the storage amount of instructions that have been prefetched into the instruction cache corresponding to the thread group is 64-32=32.

In an optional implementation, the instruction cache may also be configured to notify the The instruction prefetching situation of the instruction fetch unit. In addition, even if there is no response to the first instruction prefetch request or the second instruction prefetch request, the instruction fetch unit will be notified of the instruction prefetching situation regularly or irregularly, so as to facilitate the instruction fetching unit. Learn in real time the storage amount of instructions that have been prefetched into the instruction cache corresponding to each thread group.

It should be noted that for the same thread, the instruction fetch range of the first instruction prefetch request and the instruction fetch range of the second instruction prefetch request may or may not overlap, and may be the instruction fetch range of the second instruction prefetch request. Next to the instruction fetch range of the first instruction prefetch request, for example, the instruction fetch range of the first instruction prefetch request is address 0 to address 31, and the instruction fetch range of the second instruction prefetch request may be address 32 to address 63. ; Or the instruction fetch ranges of the two may overlap or even be the same, that is, the instruction fetch range of the first instruction prefetch request and the instruction fetch range of the second instruction prefetch request can be flexibly set according to needs.

Optionally, the priority of the first instruction prefetch request is relatively low. This may mean that the priority of the instruction cache responding to the first instruction prefetch request is lower than the priority of the second instruction prefetch request. If the workload of the instruction cache is heavy, When, the instruction cache may not respond to the first instruction prefetch request of the thread group, then the corresponding instructions of the thread group that have been prefetched into the instruction cache are zero. At this time, the instruction fetch unit is sending the second instruction prefetch request. When fetching a request, the fetch range can start from the first address or start from an address after the first address. If the instruction cache has responded to the first instruction prefetch request, when the instruction fetch unit sends the second instruction prefetch request, its instruction fetch range can fetch instructions immediately adjacent to the instruction fetch range of the first instruction prefetch request.

In order to avoid repeated prefetching and wasting prefetch bandwidth, optionally, the instruction cache can also be configured to: before performing instruction prefetching in response to the second instruction prefetch request, when receiving the second instruction prefetch request, determine There is no second instruction prefetch request in the fetch status table, where the prefetch status table is used to record an ongoing second instruction prefetch request, or a second instruction prefetch request that has been completed within a period of time. In this implementation, when receiving the second instruction prefetch request, the instruction cache does not directly respond to the second instruction prefetch request to perform instruction prefetching, but determines that the second instruction prefetch does not exist in the prefetch status table. Instruction prefetching is performed only in response to the second instruction prefetch request when the second instruction prefetch request is received. If there is a second instruction prefetch request in the prefetch status table, it indicates that the second instruction prefetch request is in the process of instruction prefetching, or that the instruction prefetching has been completed, and it can be discarded directly.

The instruction cache may be further configured to record the received second instruction prefetch request in the prefetch status table when the second instruction prefetch request is received. In order to avoid repeated prefetching and wasting prefetch bandwidth, optionally, the instruction cache is configured such that there are no other instructions from the thread group corresponding to the received second instruction prefetch request in the prefetch status table. Prefetch request (for other second instruction prefetch requests from the same thread group as the current second instruction prefetch request), directly record the received second instruction prefetch request in the prefetch status table; or, There are other instruction prefetch requests from the thread group corresponding to the received second instruction prefetch request in the prefetch status table, the prefetch range of the other instruction prefetch requests is updated, and the updated other instruction prefetch requests The prefetch range includes the prefetch range of the received second instruction prefetch request.

To facilitate understanding, examples are provided. Assume that the instruction fetch unit issues a second instruction prefetch request for a certain thread group for the first time. At this time, since there are no other instruction prefetch requests from the thread group in the prefetch status table, the instruction prefetch request is directly The second instruction prefetch request is recorded in the prefetch status table. For another example, after that, the instruction fetch unit issues a second instruction prefetch request for the thread group for the second time. At this time, because there are other instruction prefetch requests from the thread group (i.e., the first instruction prefetch request) in the prefetch status table, The second instruction prefetch request issued for the first time), therefore, only the prefetch range of other instruction prefetch requests in the prefetch status table (in this case, the second instruction prefetch request issued for the first time) needs to be carried out. Update it to include the prefetch range of the second instruction prefetch request issued for the second time. That is, the control information used for instruction prefetching (for example, including instruction fetch address information and the number of prefetched instructions) in the second instruction prefetch request issued for the first time is updated.

In addition, the instruction cache can also be configured to delete the expired prefetch range in the prefetch status table, as well as the expired second instruction prefetch request, that is, delete the second instruction prefetch request in the prefetch status table whose completion time exceeds the preset time. Instruction prefetch request, retain the second instruction prefetch request whose completion time is within the preset time.

The processor shown in this application can be improved on the architecture of existing mainstream processors, so that while supporting high concurrent access to the instruction cache, it can effectively reduce the probability of instruction access failure and reduce the acquisition of instruction fetch requests. How long to wait for the command. Among them, the existing mainstream processors can be general-purpose processors, including central processing units (Central Processing Unit, CPU), network processors (Network Processor, NP), graphics processors (Graphics Processing Unit, GPU), etc.; they can also It is a Digital Signal Processor (DSP), Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA), or it can be a microprocessor or anything else Conventional processors, etc.

Based on the same inventive concept, embodiments of the present application also provide an electronic device, which may include a body and the above-mentioned processor. Among them, the ontology may include a transceiver, communication bus, memory, etc. In one embodiment, the structure of the electronic device is shown in Figure 3 .

The components of the transceiver, memory, and processor are directly or indirectly electrically connected to each other to realize data transmission or interaction. For example, these components may be electrically connected to each other through one or more communication buses or signal lines. Among them, the transceiver can be used to send and receive data. Memory can be used to store data.

Among them, the memory can be, but is not limited to, random access memory (Random Access Memory, RAM), read-only memory (Read Only Memory, ROM), programmable read-only memory (Programmable Read-Only Memory, PROM), erasable memory In addition to read-only memory (Erasable Programmable Read-Only Memory, EPROM), electrically erasable read-only memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc.

Among them, the above-mentioned electronic devices include but are not limited to smartphones, tablets, computers, servers, etc.

The implementation principle and technical effects of the processor provided by the electronic device embodiment are the same as those of the aforementioned processor embodiment. For the purpose of brief description, for matters not mentioned in the electronic device embodiment, please refer to the corresponding content in the processor embodiment. .

Based on the same inventive concept, embodiments of the present application also provide a multi-thread shared instruction prefetching method, as shown in Figure 4 . The multi-thread shared instruction prefetching method provided by the embodiment of the present application can be applied to the above-mentioned processor. The multi-thread shared instruction prefetching method provided by the embodiment of the present application will be described below with reference to FIG. 4 .

S1: The instruction cache obtains the first instruction prefetch request sent by the thread group unit, where the first instruction prefetch request is sent by the thread group unit before the thread group is created.

Among them, the first instruction prefetch request is used to obtain instructions corresponding to the thread group to be created in the future. By sending the first instruction prefetch request to the instruction cache in advance before creating the thread group, so that there is enough time to perform instruction prefetching in advance, this can reduce the probability of instruction access failure, especially for new threads.

S2: The instruction cache responds to the first instruction prefetch request and performs instruction prefetching.

The first instruction prefetch request includes: fetch address information and the number of prefetched instructions. The process of instruction prefetching by the instruction cache in response to the first instruction prefetch request may be: responding to the first instruction prefetch request, obtaining the number of prefetched instructions from the subsequent level cache (next level cache or main memory) according to the fetch address information. instructions and stored in the instruction cache.

The instruction cache is specifically configured to respond to the first instruction prefetch request, obtain instructions with the number of prefetched instructions from the subsequent level cache (next level cache or main memory) according to the fetch address information, and store them in the instruction cache. For example, assuming that the number of prefetched instructions is 64, 64 instructions are fetched from the lower-level cache based on the fetch address information. It should be noted that the number of prefetch instructions can be flexibly configured as needed and is not limited to 64 as shown in the example here. Therefore, 64 cannot be understood as a limitation on this application.

Optionally, the multi-thread shared instruction prefetching method may also include: the instruction cache receives a second instruction prefetch request issued from the instruction fetch unit, wherein the second instruction prefetch request is a prefetched instruction corresponding to the thread group. It is sent when the storage amount of instructions in the instruction cache is less than the preset threshold; the instruction cache responds to the second instruction prefetch request to perform instruction prefetching.

Optionally, before the instruction cache performs instruction prefetching in response to the second instruction prefetch request, the multi-thread shared instruction prefetching method may also include the instruction cache determining, when receiving the second instruction prefetch request, the prefetch status table There is no second instruction prefetch request, wherein the prefetch status table is used to record an ongoing second instruction prefetch request, or a second instruction prefetch request that has been completed within a period of time.

Optionally, the multi-thread shared instruction prefetching method may also include: when receiving the second instruction prefetch request, there is no instruction in the prefetch status table corresponding to the received second instruction prefetch request. Other instruction prefetch requests from the thread group will directly record the received second instruction prefetch request in the prefetch status table; or, there is a received second instruction prefetch request from the prefetch status table. For other instruction prefetch requests of the corresponding thread group, the prefetch range of other instruction prefetch requests is updated, and the updated prefetch range of other instruction prefetch requests includes the prefetch range of the received second instruction prefetch request.

The implementation principle and technical effects of the multi-thread shared instruction prefetching method provided by the embodiments of the present application are the same as those of the aforementioned processor embodiments. For the sake of brief description, for matters not mentioned in the method embodiments, please refer to the aforementioned processing. The corresponding content in the device embodiment.

It should be noted that each embodiment in this specification is described in a progressive manner. Each embodiment focuses on its differences from other embodiments. The same and similar parts between the various embodiments are referred to each other. Can.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present application, and all of them should be covered. within the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Industrial applicability

This application provides an instruction prefetching method shared by processors, electronic devices, and multi-threads, and belongs to the field of computer technology. The processor includes: an instruction cache and a thread group unit; the thread group unit is configured to send a first instruction prefetch request to the instruction cache; the first instruction is pre-configured to send the first instruction prefetch request to the instruction cache; An instruction prefetch request is used to obtain instructions corresponding to a thread group to be created in the future; the instruction cache is configured to perform instruction prefetching in response to the first instruction prefetch request. In the embodiment of this application, before creating a thread group, the first instruction prefetch request for obtaining instructions corresponding to the thread group to be created in the future is sent to the instruction cache in advance, so that the instruction cache has enough time. Perform instruction prefetching in advance, which can reduce the probability of subsequent instruction access failures, especially for new threads, the effect is particularly obvious.

In addition, it can be understood that the processor, electronic device and multi-thread shared instruction prefetching method of the present application are reproducible and can be used in a variety of industrial applications. For example, the processor, electronic device, and multi-thread shared instruction prefetching method of the present application can be used in any computer that requires a processor.

Claims (17)

A processor, characterized in that it includes: instruction cache; A thread group unit configured to send a first instruction prefetch request to the instruction cache, where the first instruction prefetch request is used to obtain instructions corresponding to a thread group to be created in the future; The instruction cache is configured to perform instruction prefetching in response to the first instruction prefetch request. The processor of claim 1, wherein the first instruction prefetch request includes: fetch address information and a prefetch instruction number, and the instruction cache performs instruction prefetching in response to the first instruction prefetch request. Fetching includes: the instruction cache responds to the first instruction prefetch request, obtains instructions of the number of prefetched instructions from a subsequent level cache according to the instruction fetch address information, and stores them in the instruction cache. The processor according to claim 1 or 2, characterized in that the processor further includes: Fetch unit; The thread group unit is further configured to distribute the created thread group to the instruction fetch unit; The instruction fetch unit is configured to issue a corresponding instruction fetch request based on the received thread group; The instruction cache is further configured to respond to the instruction fetch request and return the instruction hit by the instruction fetch request. The processor according to claim 3, wherein the number of the instruction fetching units is multiple. The processor according to claim 3 or 4, wherein the instruction fetching unit is further configured to monitor the storage amount of instructions corresponding to each thread group that have been prefetched into the instruction cache. When the storage amount is less than the preset threshold, send a second instruction prefetch request to the instruction cache; The instruction cache is further configured to perform instruction prefetching in response to the second instruction prefetch request. The processor of claim 5, wherein the instruction cache is further configured to: before performing instruction prefetching in response to the second instruction prefetch request, after receiving the second instruction prefetch request When, it is determined that the second instruction prefetch request does not exist in the prefetch status table, wherein the prefetch status table is used to record the second instruction prefetch request in progress, or the second instruction prefetch request that has been completed within a period of time. Instruction prefetch request. The processor of claim 6, wherein the instruction cache is further configured to, when receiving a second instruction prefetch request, record the received second instruction prefetch request in the prefetch state. table. The processor according to claim 7, wherein the instruction cache is specifically configured to: If there is no other instruction prefetch request from the thread group corresponding to the received second instruction prefetch request in the prefetch status table, the received second instruction prefetch request will be directly processed. Recorded in the prefetch status table; or, There are other instruction prefetch requests from the thread group corresponding to the received second instruction prefetch request in the prefetch status table, and the prefetch range of the other instruction prefetch requests is updated. After the update The prefetch range of the other instruction prefetch request includes the prefetch range of the received second instruction prefetch request. The processor according to claim 7 or 8, wherein the priority of the instruction cache responding to the first instruction prefetch request is lower than the priority of responding to the second instruction prefetch request. The processor according to any one of claims 7 to 9, wherein the instruction cache is configured to delete an expired prefetch range in the prefetch status table and an expired second instruction cache. Get the request. The processor according to any one of claims 5 to 10, wherein the second instruction prefetch request includes fetch address information and the number of prefetched instructions. An electronic device, characterized by comprising a body and a processor according to any one of claims 1-11. A multi-thread shared instruction prefetching method, which is characterized by including: The instruction cache obtains the first instruction prefetch request sent by the thread group unit, wherein the first instruction prefetch request is sent by the thread group unit before creating the thread group, and the first instruction prefetch request is used to obtain Instructions corresponding to the thread groups that will be created in the future; The instruction cache performs instruction prefetching in response to the first instruction prefetch request. The method of claim 13, wherein the first instruction prefetch request includes: fetch address information and a prefetch instruction number, and the instruction cache performs instruction prefetching in response to the first instruction prefetch request. The method includes: the instruction cache responds to the first instruction prefetch request, obtains instructions with the number of prefetched instructions from a subsequent level cache according to the instruction fetch address information, and stores them in the instruction cache. The method according to claim 13 or 14, characterized in that the method further includes: The instruction cache receives a second instruction prefetch request issued from the instruction fetch unit, wherein the second instruction prefetch request is that the storage amount of instructions that have been prefetched into the instruction cache corresponding to the thread group is less than Sent when the threshold is preset; The instruction cache performs instruction prefetching in response to the second instruction prefetch request. The method of claim 15, wherein before the instruction cache performs instruction prefetching in response to the second instruction prefetch request, the method further includes: When receiving the second instruction prefetch request, the instruction cache determines that the second instruction prefetch request does not exist in the prefetch status table, wherein the prefetch status table is used to record the ongoing third instruction prefetch request. A second instruction prefetch request, or a second instruction prefetch request that has completed within a period of time. The method of claim 16, further comprising: When receiving the second instruction prefetch request, if there are no other instruction prefetch requests from the thread group corresponding to the received second instruction prefetch request in the prefetch status table, the instruction prefetch request will be directly processed. The received second instruction prefetch request is recorded in the prefetch status table; or, There are other instruction prefetch requests from the thread group corresponding to the received second instruction prefetch request in the prefetch status table, and the prefetch range of the other instruction prefetch requests is updated. After the update The prefetch range of the other instruction prefetch request includes the prefetch range of the received second instruction prefetch request.

Images