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WO2023178865A1 - 半导体超结功率器件 - Google Patents

半导体超结功率器件 Download PDF

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Publication number
WO2023178865A1
WO2023178865A1 PCT/CN2022/101560 CN2022101560W WO2023178865A1 WO 2023178865 A1 WO2023178865 A1 WO 2023178865A1 CN 2022101560 W CN2022101560 W CN 2022101560W WO 2023178865 A1 WO2023178865 A1 WO 2023178865A1
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gate
type body
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power device
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French (fr)
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王鹏飞
刘磊
袁愿林
王睿
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Suzhou Oriental Semiconductor Co Ltd
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Suzhou Oriental Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates

Definitions

  • the present application relates to the technical field of semiconductor power devices, for example, to a semiconductor superjunction power device.
  • Semiconductor superjunction power devices are based on charge balance technology, which can reduce on-resistance and parasitic capacitance, making semiconductor superjunction power devices have extremely fast switching characteristics, which can reduce switching losses and achieve higher power conversion efficiency.
  • Miller capacitance (Crss) and its corresponding gate-to-drain capacitance (Cgd) play an important role in the switching process of semiconductor superjunction power devices.
  • the gate-to-drain capacitance (Cgd) will mutate, which causes the electrical performance of the semiconductor superjunction power device to also mutate.
  • the present application provides a semiconductor superjunction power device that can adjust the change curve of the gate-drain capacitance, so as to solve the problem of gate-drain capacitance mutation of semiconductor superjunction power devices in related technologies.
  • This application provides a semiconductor superjunction power device, including:
  • An n-type drift region located above the n-type drain region
  • a plurality of p-type pillars forming a charge balance structure between the p-type pillars and the n-type drift region;
  • a first p-type body region is provided on the top of the p-type pillar, and a first n-type source region is provided in the first p-type body region;
  • a first gate trench is provided between adjacent first p-type body regions in part of the first p-type body region, and a first gate dielectric layer and a first gate electrode are provided in the first gate trench;
  • At least two second gate trenches are provided between adjacent first p-type body regions except for the part of the first p-type body region, and a second gate dielectric layer and a second gate dielectric layer are disposed in the second gate trenches.
  • Second gate is provided between adjacent first p-type body regions except for the part of the first p-type body region, and a second gate dielectric layer and a second gate dielectric layer are disposed in the second gate trenches.
  • Another semiconductor superjunction power device includes:
  • An n-type drift region located above the n-type drain region
  • a plurality of p-type pillars forming a charge balance structure between the p-type pillars and the n-type drift region;
  • a first p-type body region is provided on the top of the p-type pillar, and a first n-type source region is provided in the first p-type body region;
  • a first gate trench is provided between adjacent first p-type body regions in part of the first p-type body region, and a first gate dielectric layer and a first gate electrode are provided in the first gate trench;
  • a third gate trench is provided between adjacent first p-type body regions except for the part of the first p-type body region, and a third gate dielectric layer and two The third gate.
  • Figure 1 is a schematic cross-sectional structural diagram of a semiconductor superjunction power device provided by an embodiment of the present application
  • Figure 2 is a schematic cross-sectional structural diagram of another semiconductor superjunction power device provided by an embodiment of the present application.
  • FIG. 3 is a schematic cross-sectional structural diagram of another semiconductor superjunction power device provided by an embodiment of the present application.
  • Figure 1 is a schematic cross-sectional structural diagram of a semiconductor superjunction power device provided by an embodiment of the present application.
  • a semiconductor superjunction power device provided by an embodiment of the present application includes an n-type drain region 20, an n-type The drain region 20 can be externally connected to the drain voltage through the metal layer.
  • the n-type drift region 21 is located above the n-type drain region 20 .
  • a plurality of p-type pillars 22 form a charge balance structure between the p-type pillars 22 and the n-type drift region 21 .
  • FIG. 1 For convenience of display and explanation, only three p-type pillar 22 structures are shown in FIG. 1 as an example.
  • a first p-type body region 23 is disposed on the top of each p-type pillar 22 , and a first n-type source region 24 is disposed in the first p-type body region 23 .
  • a first gate trench 30 is located between two adjacent first p-type body regions 23 in part of the first p-type body region 23. At least two second gate trenches 31 are disposed between the p-type body regions 23.
  • FIG. 1 only shows the structure of the two second gate trenches 31 as an example.
  • the first gate trench The first gate dielectric layer 25 and the first gate electrode 26 are disposed in the second gate trench 30 , and the second gate dielectric layer 35 and the second gate electrode 36 are disposed in the second gate trench 31 .
  • the width of the second gate trench 31 is made smaller than the width of the first gate trench 30.
  • the semiconductor superjunction power device of the present application has a first gate trench between adjacent first p-type body regions in part of the first p-type body region. At least two second gate trenches are provided between adjacent first p-type body regions, so that the semiconductor super power device has at least two different gate-drain capacitance values, so that during the switching process, the mutation point of the gate-drain capacitance are divided into different source-drain voltage points, which reduces the mutation speed of the gate-drain capacitance, adjusts the change curve of the gate-drain capacitance, and reduces the gate voltage oscillation caused by the mutation of the gate-drain capacitance.
  • FIG. 2 is a schematic cross-sectional structural diagram of another semiconductor superjunction power device provided by an embodiment of the present application.
  • the semiconductor superjunction power device shown in Figure 2 is based on the semiconductor superjunction power device shown in Figure 1 and also includes The second p-type body region 33 between the adjacent first p-type body regions 23 and between the adjacent second gate trenches 31 may optionally be located in the second p-type body region.
  • a second n-type source region is disposed in the second p-type body region 33 (not shown in FIG. 2 ).
  • the second n-type source region 24 is disposed in the second p-type body region 33 in the same manner as the first n-type source region 24 is disposed in the first p-type body region.
  • the settings in zone 23 are the same).
  • FIG 3 is a schematic cross-sectional structural diagram of another semiconductor superjunction power device provided by an embodiment of the present application.
  • the semiconductor superjunction power device of the present application includes an n-type drain region 20 located between the n-type drain region 20 n-type drift region 21 on.
  • a plurality of p-type pillars 22 form a charge balance structure between the p-type pillars 22 and the n-type drift region 21 .
  • a first p-type body region 23 is disposed on the top of each p-type pillar 22
  • a first n-type source region 24 is disposed in the first p-type body region 23 .
  • a first gate trench 30 is located between two adjacent first p-type body regions 23 in part of the first p-type body region 23.
  • a third gate trench 32 is disposed between the p-type body regions 23 .
  • the first gate trench 30 is disposed with a first gate dielectric layer 25 and a first gate electrode 26 .
  • a third gate trench 32 is disposed with a third gate trench 32 .
  • two third gates 46 are respectively located on both sides of the third gate trench 32 , and the two third gates 46 are insulated and isolated by an insulating layer 47 .
  • the width of the third gate trench 32 is made larger than the width of the first gate trench 30 .

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  • Junction Field-Effect Transistors (AREA)

Abstract

本文公开一种半导体超结功率器件，包括：n型漏区；位于n型漏区之上的n型漂移区；多个p型柱，p型柱与n型漂移区之间形成电荷平衡结构；p型柱顶部设有第一p型体区，第一p型体区内设有第一n型源区；部分第一p型体区中相邻的第一p型体区之间设有一个第一栅沟槽，所述第一栅沟槽内设有第一栅介质层和第一栅极；除所述部分第一p型体区外的相邻的第一p型体区之间设有至少两个第二栅沟槽，所述第二栅沟槽内设有第二栅介质层和第二栅极。

Description

半导体超结功率器件
本申请要求在2022年03月21日提交中国专利局、申请号为202210281110.4的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体功率器件技术领域，例如涉及一种半导体超结功率器件。
背景技术
半导体超结功率器件基于电荷平衡技术，可以降低导通电阻和寄生电容，使得半导体超结功率器件具有极快的开关特性，可以降低开关损耗，实现更高的功率转换效率。半导体超结功率器件在开启和关断过程中，米勒电容(Crss)及其所对应的栅漏电容(Cgd)对半导体超结功率器件的开关过程起到重要的作用。半导体超结功率器件在开启和关断时，栅漏电容(Cgd)会发生突变，这使得半导体超结功率器件的电学性能也发生突变。
发明内容
本申请提供一种可以调节栅漏电容的变化曲线的半导体超结功率器件，以解决相关技术中的半导体超结功率器件的栅漏电容突变问题。
本申请提供的一种半导体超结功率器件，包括：
n型漏区；
位于所述n型漏区之上的n型漂移区；
多个p型柱，所述p型柱与所述n型漂移区之间形成电荷平衡结构；
所述p型柱顶部设有第一p型体区，所述第一p型体区内设有第一n型源区；
部分第一p型体区中相邻的第一p型体区之间设有一个第一栅沟槽，所述第一栅沟槽内设有第一栅介质层和第一栅极；
除所述部分第一p型体区外的相邻的第一p型体区之间设有至少两个第二栅沟槽，所述第二栅沟槽内设有第二栅介质层和第二栅极。
本申请提供的另一种半导体超结功率器件，包括：
n型漏区；
位于所述n型漏区之上的n型漂移区；
多个p型柱，所述p型柱与所述n型漂移区之间形成电荷平衡结构；
所述p型柱顶部设有第一p型体区，所述第一p型体区内设有第一n型源区；
部分第一p型体区中相邻的第一p型体区之间设有一个第一栅沟槽，所述第一栅沟槽内设有第一栅介质层和第一栅极；
除所述部分第一p型体区外的相邻的第一p型体区之间设有一个第三栅沟槽，所述第三栅沟槽内设有第三栅介质层和两个第三栅极。
附图说明
图1是本申请实施例提供的一种半导体超结功率器件的剖面结构示意图；
图2是本申请实施例提供的另一种半导体超结功率器件的剖面结构示意图；
图3是本申请实施例提供的另一种半导体超结功率器件的剖面结构示意图。
具体实施方式
以下将结合本申请实施例中的附图，通过具体方式，描述本申请的技术方案。所描述的实施例是本申请的一部分实施例。为说明本申请的具体实施方式，附图中所列图形大小并不代表实际尺寸，附图是示意性的，不应限定本申请的范围。
图1是本申请实施例提供的一种半导体超结功率器件的剖面结构示意图，如图1所示，本申请实施例提供的一种半导体超结功率器件，包括n型漏区20，n型漏区20可以通过金属层外接漏极电压。位于n型漏区20之上的n型漂移区21。
多个p型柱22，p型柱22与n型漂移区21之间形成电荷平衡结构。为了方便展示和说明，图1中仅示例性的示出了三个p型柱22结构。
在每个p型柱22的顶部设有第一p型体区23，第一p型体区23内设有第一n型源区24。
介于部分第一p型体区23中相邻的两个第一p型体区23之间的一个第一栅沟槽30，除部分第一p型体区23外的相邻的第一p型体区23之间设有至少两个第二栅沟槽31，为了方便展示和说明，图1中仅示例性的示出了两个第二栅沟槽31结构，第一栅沟槽30内设有第一栅介质层25和第一栅极26，第二栅沟槽31内设有第二栅介质层35和第二栅极36。为了方便设置p型柱22与n型 漂移区21之间形成的电荷平衡结构，一实施例中，使得第二栅沟槽31的宽度小于第一栅沟槽30的宽度。
本申请的半导体超结功率器件，在部分第一p型体区中相邻的第一p型体区之间设有一个第一栅沟槽，在除部分第一p型体区外的相邻的第一p型体区之间设有至少两个第二栅沟槽，使得半导体超级功率器件内具有至少两种不同的栅漏电容值，从而在开关过程中，栅漏电容的突变点被分到不同的源漏电压点上，这使得栅漏电容突变速度降低，调节了栅漏电容的变化曲线，也就降低了由栅漏电容突变引起的栅极电压震荡。
图2是本申请实施例提供的另一种半导体超结功率器件的剖面结构示意图，图2所示的半导体超结功率器件是在图1所示的半导体超结功率器件的基础上，还包括介于相邻的第一p型体区23之间且介于相邻的第二栅沟槽31之间的第二p型体区33，可选的，还可以在第二p型体区33内设置第二n型源区(图2中未示出，第二n型源区在第二p型体区33内的设置方式可以与第一n型源区24在第一p型体区23内的设置方式相同)。通过设置第二p型体区，可以调节栅漏电容的突变速度。
图3是本申请实施例提供的另一种半导体超结功率器件的剖面结构示意图，如图3所示，本申请的半导体超结功率器件包括n型漏区20，位于n型漏区20之上的n型漂移区21。多个p型柱22，p型柱22与n型漂移区21之间形成电荷平衡结构。在每个p型柱22的顶部均设有第一p型体区23，第一p型体区23内设有第一n型源区24。
介于部分第一p型体区23中相邻的两个第一p型体区23之间的一个第一栅沟槽30，除部分第一p型体区23外的相邻的第一p型体区23之间设有一个第三栅沟槽32，第一栅沟槽30内设有第一栅介质层25和第一栅极26，第三栅沟槽32内设有第三栅介质层45和两个第三栅极46。一实施例中，两个第三栅极46分别位于第三栅沟槽32的两侧，两个第三栅极46之间通过绝缘层47绝缘隔离。
为了方便设置p型柱22与n型漂移区21之间形成的电荷平衡结构，一实施例中，使得第三栅沟槽32的宽度大于第一栅沟槽30的宽度。

Claims (7)

  1. 一种半导体超结功率器件，包括：
    n型漏区；
    位于所述n型漏区之上的n型漂移区；
    多个p型柱，所述p型柱与所述n型漂移区之间形成电荷平衡结构；
    所述p型柱顶部设有第一p型体区，所述第一p型体区内设有第一n型源区；
    部分第一p型体区中相邻的第一p型体区之间设有一个第一栅沟槽，所述第一栅沟槽内设有第一栅介质层和第一栅极；
    除所述部分第一p型体区外的相邻的第一p型体区之间设有至少两个第二栅沟槽，所述第二栅沟槽内设有第二栅介质层和第二栅极。
  2. 如权利要求1所述的半导体超结功率器件，还包括介于相邻的第一p型体区之间且介于相邻的第二栅沟槽之间的第二p型体区。
  3. 如权利要求2所述的半导体超结功率器件，其中，所述第二p型体区内设有第二n型源区。
  4. 如权利要求1所述的半导体超结功率器件，其中，所述第二栅沟槽的宽度小于所述第一栅沟槽的宽度。
  5. 一种半导体超结功率器件，包括：
    n型漏区；
    位于所述n型漏区之上的n型漂移区；
    多个p型柱，所述p型柱与所述n型漂移区之间形成电荷平衡结构；
    所述p型柱顶部设有第一p型体区，所述第一p型体区内设有第一n型源区；
    部分第一p型体区中相邻的第一p型体区之间设有一个第一栅沟槽，所述第一栅沟槽内设有第一栅介质层和第一栅极；
    除所述部分第一p型体区外的相邻的第一p型体区之间设有一个第三栅沟槽，所述第三栅沟槽内设有第三栅介质层和两个第三栅极。
  6. 如权利要求5所述的半导体超结功率器件，其中，所述第三栅沟槽的宽度大于所述第一栅沟槽的宽度。
  7. 如权利要求5所述的半导体超结功率器件，其中，所述两个第三栅极分别位于所述第三栅沟槽的两侧，所述两个第三栅极之间绝缘隔离。
PCT/CN2022/101560 2022-03-21 2022-06-27 半导体超结功率器件 Ceased WO2023178865A1 (zh)

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CN202210281110.4 2022-03-21
CN202210281110.4A CN116825829A (zh) 2022-03-21 2022-03-21 半导体超结功率器件

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Citations (4)

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