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WO2022250741A1 - Procédé et appareil de gestion de valeurs aberrantes - Google Patents

Procédé et appareil de gestion de valeurs aberrantes Download PDF

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Publication number
WO2022250741A1
WO2022250741A1 PCT/US2022/011036 US2022011036W WO2022250741A1 WO 2022250741 A1 WO2022250741 A1 WO 2022250741A1 US 2022011036 W US2022011036 W US 2022011036W WO 2022250741 A1 WO2022250741 A1 WO 2022250741A1
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WO
WIPO (PCT)
Prior art keywords
outlier
block
training
dnn
tvso
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PCT/US2022/011036
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English (en)
Inventor
Lorenzo Zuolo
Rino Micheloni
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Microchip Technology Inc
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Microchip Technology Inc
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Filing date
Publication date
Priority claimed from US17/506,735 external-priority patent/US11514994B1/en
Application filed by Microchip Technology Inc filed Critical Microchip Technology Inc
Priority to DE112022001015.0T priority Critical patent/DE112022001015T5/de
Priority to CN202280027141.5A priority patent/CN117121108A/zh
Publication of WO2022250741A1 publication Critical patent/WO2022250741A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0499—Feedforward networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G06N3/09—Supervised learning
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3431—Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50004—Marginal testing, e.g. race, voltage or current testing of threshold voltage

Definitions

  • the reliability of a device is an indication of the probability that the device will perform its intended function during a specified period of time under stated conditions. Because age of flash memory devices is typically measured as a function of the number of program and erase (PE) cycles of the flash memory device (or the number of PE cycles of individual blocks of the flash memory device), the reliability of flash memory devices are typically determined based on the number of PE cycles of the flash memory device (or the number of PE cycles of each block of the flash memory device). Reliability states that correspond to a particular number (or range) of PE cycles of a flash memory device or a block of a flash memory device are referred to hereinafter as PE-based reliability states.
  • PE-based reliability states that correspond to a particular number (or range) of PE cycles of a flash memory device or a block of a flash memory device.
  • PE-based reliability states are usually created by identifying the number of PE cycles in the expected lifetime of the flash memory device or the expected lifetime of individual blocks of the flash memory device and dividing the expected lifetime of the flash memory device (or blocks of the flash memory device) into a number of periods based on the number of PE cycles, such that the periods span the entire lifetime of the flash memory device (or blocks of the flash memory device).
  • each flash memory device or block of the flash memory device has an anticipated end of life of 5,000 PE cycles and the lifetime of the flash memory device/block is divided into five periods based on the number of PE cycles such that a first period (that defines a first PE-based reliability state) corresponds to the first thousand PE cycles (0-1000 PE cycles) of the flash memory device/block, a second period (that defines a second PE-based reliability state) corresponds to the next thousand PE cycles (1001-2000 PE cycles) of the flash memory device/block, a third period (that defines a third PE- based reliability state) corresponds to the next thousand PE cycles (2001- 3000 PE cycles) of the flash memory device/block, a fourth period (that defines a fourth PE- based reliability state) corresponds to the next thousand PE cycles (3001-4000 PE cycles) of the flash memory device/block and a fifth period (that defines a fifth PE-based reliability state) corresponds to the last thousand PE cycles(4001-5000 PE
  • Some Solid State Drives use threshold-voltage-shift reads for reading flash memory devices to obtain low levels of Uncorrectable Bit Error Rate (UBER) required for client and enterprise SSD’s.
  • Threshold-voltage-shift reads are performed by sending a threshold- voltage-shift read instruction from a flash controller to a flash memory device that is to be read.
  • One or more threshold- Voltage-Shift Offset (TVSO) value is sent with the threshold-voltage- shift read instruction.
  • the TVSO value indicates the amount by which the threshold voltage that is used to perform the read is to be offset from a corresponding default threshold voltage that is specified by the manufacturer of the flash memory device.
  • Flash memory manufacturers typically publish a product specification that includes a set of TVSO values for each PE-based reliability state (e.g. a plurality of sets of TVSO values, and for each set of TVSO values the range of PE cycles where that set of TVSO values is recommended).
  • the flash controller then needs only to identify the current number of PE cycles of the flash memory device or the block of the flash memory device to be read and look up the corresponding set of TVSO values (e.g., using a lookup table) and then send the identified set of TVSO values along with the address to be read to the flash memory device.
  • the flash memory device performs a read of the address at the specified TVSO values and returns the results of the read to the flash controller.
  • Some users and flash controller manufacturers perform flash memory characterization testing of exemplary flash memory devices to identify TVSO values that are more precise than those specified by the manufacturer of the flash memory device.
  • some of these users and flash controller manufacturers expand the number of characteristics in the PE-based reliability state by using other characteristics to define the PE-based reliability state such as the retention time and/or the number of read disturbs of the block to be read.
  • These conventional PE-based reliability states and devices work well for almost all of the blocks of the SSD.
  • Outlier blocks are typically identified by the fact that they have a higher raw bit error rate (RBER) than the other blocks in their PE-based reliability state.
  • Some SSD’s perform background error testing of each of the memory blocks in the SSD to identify RBER in each read. When the RBER exceeds a predetermined error threshold the block is identified to be a bad block. Once a block is identified as a bad block, it is no longer used by the SSD in order to prevent an uncorrectable bit error during operation (e.g., when there are too many errors in a particular page for soft-error correction). When uncorrectable bit errors occur during operation a Redundant Array of Independent Disks (RAID) operation is required to recover the stored data, resulting in increased system latency and negatively impacting quality of service (QoS) of the SSD.
  • RAID Redundant Array of Independent Disks
  • a method for outlier block management at a flash controller that uses TVSO values for performing reads of a flash memory device includes testing the flash memory device to identify one or more outlier blocks of the flash memory device, the one or more outlier blocks having a number of errors greater than an outlier-error threshold; and loading hyperparameters for a deep neural network (DNN) into a training circuit of the flash controller.
  • DNN deep neural network
  • a plurality of test reads of the one or more outlier blocks are performed and a number of errors in the test reads are identified.
  • the DNN is trained at the training circuit using a mini-batch training process and using the identified number of errors in the test reads.
  • the trained DNN is tested to determine whether the trained DNN meets a training error threshold (TET) and the performing the plurality of test reads, the identifying the number of errors in the test reads, the training and the testing are repeated until the trained DNN meets the TET to identify parameters of an outlier-block DNN.
  • TET training error threshold
  • a neural network operation is performed at a neural network engine of the flash controller using the identified parameters of the outlier-block DNN to predict TVSO values corresponding to the one or more outlier blocks; and a read is performed using the predicted TVSO values.
  • a flash controller includes a read circuit coupled to a TVSO-read table indicating TVSO values to be used for reading a flash memory device and a decode circuit coupled to the read circuit, the decode circuit configured to decode reads of the flash memory device.
  • the flash controller includes a training circuit and a control circuit coupled to the training circuit.
  • the control circuit is to identify one or more outlier blocks of the flash memory device, the outlier blocks having a number of errors greater than an outlier-error threshold, and to load hyperparameters for a deep neural network (DNN) into the training circuit.
  • the read circuit is to perform a plurality of test reads of the identified one or more outlier blocks.
  • the decode circuit is to identify the number of errors in the test reads of the identified one or more outlier blocks.
  • the training circuit is to train the DNN using a mini-batch training process and using the identified number of errors in the test reads and to test the trained DNN to determine whether the trained DNN meets a training error threshold.
  • the training circuit, the decode circuit and the control circuit is to repeat performing the plurality of test reads, identifying the number of errors in the test reads, training and testing until the trained DNN meets the TET to identify parameters of an outlier-block DNN.
  • a neural network engine is coupled to the training circuit and the control circuit, the neural network engine to perform a neural network operation using the parameters of the outlier- block DNN to predict TVSO values corresponding to the one or more outlier blocks.
  • the control circuit is to store the predicted TVSO values, and the read circuit is to perform a read using the predicted TVSO values.
  • a method for outlier management at a flash controller that uses threshold voltage shift offset (TVSO) values for performing reads of a flash memory device includes: performing a plurality of test reads of an outlier block, the outlier block having a number of errors greater than a training error threshold; and identifying a number of errors in the test reads.
  • Hyperparameters for a deep neural network (DNN) are loaded into a training circuit of the flash controller. The DNN is trained at the training circuit using a mini-batch training process and using the identified number of errors in the test reads; and the trained DNN is tested to determine whether the trained DNN meets a TET.
  • the performing the plurality of test reads, the identifying the number of errors in the test reads, the training and the testing are repeated until the trained DNN meets the TET to identify parameters of an outlier-block DNN.
  • a neural network operation is performed at a neural network engine of the flash controller using the identified parameters of the outlier- block DNN to predict TVSO values corresponding to the one or more outlier block.
  • the predicted TVSO values are stored and a read is performed using the predicted TVSO values.
  • the method and apparatus of the present invention does not require that outlier blocks be marked as bad blocks and retired as soon as they are identified as outlier blocks, increasing the number of blocks available for use by the SSD. Accordingly, the present method and apparatus extends the useful life of outlier blocks while maintaining UBER of the SSD within acceptable levels during the lifetime of the SSD.
  • FIG. 1 is a diagram illustrating a SSD that includes a flash controller, flash memory devices and a memory device.
  • FIG. 2 is a diagram illustrating a method for outlier block management at a flash controller that uses TVSO values for performing reads of a flash memory device.
  • FIG. 3 is a block diagram illustrating a data record.
  • FIG. 4 is a block diagram illustrating an outlier-block DNN and the training of the outlier-block DNN.
  • FIG. 5 is a diagram illustrating iterations on the x-axis and training error on the y-axis for training an outlier-block DNN for predicting a set of outlier-block TVSO values for a single outlier-block, where the training is stopped as soon as the training error reaches a TET.
  • FIG. 6 is a diagram illustrating iterations on the x-axis and training error on the y-axis for training an outlier-block DNN for predicting a set of outlier-block TVSO values for a single outlier-block, where the training continues after the TET is reached.
  • FIG. 7 is a diagram illustrating iterations on the x-axis and training error on the y-axis for training an outlier-block DNN for predicting a set of outlier-block TVSO values for a plurality of outlier-blocks.
  • FIG. 8 is a block diagram illustrating an outlier-block DNN and inputs and outputs for a neural network operation of the outlier-block DNN.
  • FIG. 9 is a diagram illustrating a method for managing outlier blocks in which outlier- blocks are retired by identifying the outlier block to be retired as a bad-block.
  • FIG. 1 shows an SSD 1 that includes a flash controller 3, a plurality of flash memory devices 2 and a memory device 14.
  • Flash controller 3 is coupled to flash memory devices 2 for storing data and for reading data from flash memory devices 2.
  • the flash memory devices 2 are NAND devices connected to form a plurality of channels (e.g. channels 17-19) and flash controller 3, flash memory devices 2 and memory device 14 are devices mounted to a circuit board (not shown).
  • SSD 1 includes a plurality of flash packages, each flash package containing 8 flash memory die such that there are 8 die for each channel 17-19.
  • Memory device 14 is a volatile memory device such as a Dynamic Random Access Memory (DRAM) that is electrically coupled to flash controller 3.
  • DRAM Dynamic Random Access Memory
  • Flash controller 3 is an integrated circuit device that includes data storage circuit 4, status circuit 5, read circuit 6, decode circuit 7, program circuit 8, control circuit 9, neural network engine 10, training circuit 13, input and output (I/O) circuit 11 and erase circuit 12.
  • Data storage circuit 4 includes a configuration file for a PE-based-reliability-state neural network 16a that predicts TVSO values using PE-based reliability states, a TVSO-read table 16b, optionally hyperparameters for a DNN 16c and one or more configuration files for an outlier-block DNN 16d.
  • a DNN is a neural network having more than a single hidden layer of neurons.
  • Control circuit 9 is coupled to data storage circuit 4, status circuit 5, read circuit 6, decode circuit 7, program circuit 8, neural network engine 10, I/O circuit 11, erase circuit 12 and training circuit 13.
  • Decode circuit 7 is further coupled to read circuit 6.
  • Status circuit 5 is further coupled to data storage circuit 4, read circuit 6, program circuit 8, neural network engine 10 and erase circuit 12.
  • Read circuit 6 is further coupled to data storage circuit 4, neural network engine 10, I/O circuit 11 and training circuit 13.
  • Neural network engine 10 is further coupled to data storage 4.
  • I/O circuit 11 is further coupled to data storage 4, program circuit 8, erase circuit 12 and training circuit 13.
  • Training circuit 13 is further coupled to data storage circuit 4.
  • circuit 5 Some or all of circuit 5, read circuit 6, decode circuit 7, program circuit 8, control circuit 9, neural network engine 10, input and output (I/O) circuit 11, erase circuit 12 and training circuit 13 are dedicated circuits for performing operations, and some or all of circuit 5, read circuit 6, decode circuit 7, program circuit 8, control circuit 9, neural network engine 10, input and output (I/O) circuit 11, erase circuit 12 and training circuit 13 can be firmware that includes instructions that are performed on one or more processor for performing operations of flash controller 3, with the instructions stored in registers of one or more of circuit 5, read circuit 6, decode circuit 7, program circuit 8, control circuit 9, neural network engine 10, input and output (I/O) circuit 11, erase circuit 12 and training circuit 13 and/or stored in data storage 4 or memory device 14.
  • circuit 5 Some of all of circuit 5, read circuit 6, decode circuit 7, program circuit 8, control circuit 9, neural network engine 10, training circuit 13, input and output (I/O) circuit 11 and erase circuit 12 include processors for performing instructions and instructions are loaded into flash controller 3 prior to operation of flash controller 3 by a user.
  • status circuit 5 each time that a block is closed, status circuit 5 is operable to count the number of reads of the block while the block is closed and the number of reads of the block while the block is closed is stored as a read disturb value (RD) for the block. When a block is erased the RD of the erased block is reset to zero.
  • status circuit 5 is operable to start a timer to determine the amount of time that has elapsed since the block was closed. The elapsed time as determined by the timer at any point in time is defined as the retention time (RT) for the block (e.g. a closed-block retention time value).
  • Status circuit 5 is also operable for counting the number of program and erase cycles (PE) of each block of the flash memory device 2 during the entire lifetime of the flash memory device 2 and storing the count in data storage 4 or memory device 14.
  • PE program and erase cycles
  • Flash controller 3 receives read and write instructions from a host computer at I/O circuit 11, and performs program operations, erase operations and read operations on memory cells of flash memory devices 2 to complete the instructions from the host computer.
  • I/O circuit 11 includes circuitry to receive input and output and coupling the input to internal circuits of flash controller 3 and to couple the output to devices external to flash controller 3.
  • TVSO-read table 16b indicates TVSO values to be used for reading a flash memory device 2.
  • Read circuit 6 performs reads of flash memory devices 2.
  • Decode circuit 7 decodes reads of the flash memory devices 2.
  • Program circuit 8 performs program operations to store data in flash memory devices 2.
  • Erase circuit 12 erases memory locations in one or more of flash memory devices 2.
  • Status circuit 5 tracks the status and the operations of flash controller 3 and flash memory devices 2.
  • the status includes the current PE cycles the current RT and the current RD of each of the good blocks of each flash memory device 2.
  • Data storage circuit 4 is a structure in flash controller 3 that is capable of storing data, and may include cache memory and/or static random- access memory (SRAM).
  • Neural network engine 11 includes a specialized hardware circuit (e.g., a specialized configurable accelerator) to perform a neural network operation.
  • I/O circuit 11 includes one or more circuit for receiving a write instruction from a host computer and for coupling the write instruction to program circuit 8.
  • Program circuit 8 in response to receiving the write instruction, programs codewords into on one or more of flash memory devices 2.
  • I/O circuit 11 includes one or more circuit for receiving a read instruction from a host computer and for coupling the read instruction to read circuit 6.
  • Read circuit 6 in response to receiving the read instruction, performs a lookup in TVSO-read table 16b using the current status of the memory location of the flash memory device 2 that is to be read, as indicated by status circuit 5, identifies the TVSO values to use in performing the read; sends a read command that includes the identified TVSO values to a flash memory device 2 that is to be read; receives a response from the flash memory device 2 and decode circuit 7 is operable to decode the results from the read command.
  • the sets of TVSO values initially stored in TVSO-read table 16b that may be referred to hereinafter individually as a “set of PE-based-reliability-state TVSO values” are generated using conventional PE-based reliability states as is known in the art, and may be the PE-based- reliability-state TVSO values in the documentation published by the manufacturer of flash memory devices 2.
  • the TVSO-read table can include different sets of PE-based-reliability-state TVSO values for different blocks and can include a block number index associated with each set of PE-based-reliability-state TVSO values.
  • a PE cycle index is associated with each set of PE-based-reliability-state TVSO values stored in TVSO-read table 16b and a lookup is performed to identify the set of PE- based-reliability-state TVSO values associated with the PE cycle index that matches the current number of PE cycles and that matches the block number index of the block that is to be read.
  • a PE cycle index, RT index and RD index are associated with each set of PE-based-reliability-state TVSO values stored in TVSO-read table 16b and a lookup is performed to identify the set of set of PE-based-reliability-state TVSO values associated with the PE cycle index that matches the current number of PE cycles, the RT index that matches the current RT, the RD index that matches the current RT and the block number of the block that is to be read.
  • PE-based-reliability-state TVSO values stored in TVSO-read table 16b can be obtained from the manufacturer of flash memory devices 2, alternatively, they are determined by performing a neural network operation and storing the results of the neural network operation in TVSO-read table 16b.
  • a configuration file for a PE-based-reliability-state neural network 16a is stored and a neural network operation is performed to identify the PE-based- reliability-state TVSO values.
  • TVSO-read table 16b are generated as shown in US Patent Application Serial Number 17/089,891 filed on 11/5/2020 and titled “Regression Neural Network for Identifying Threshold Voltages to be Used in Reads of Flash Memory Devices;” that is incorporated herein by reference in its entirety.
  • bad blocks are indicated in one or more bad block table 16e.
  • bad block table 16e is illustrated as being a single table stored in data storage circuit 4, it is appreciated that bad blocks could be indicated using multiple bad block tables (e.g., a table for each flash memory device 2), and that the bad block table(s) could be stored in data storage 14 or in flash memory devices 2.
  • Bad block table 16e includes data identifying each of the blocks that have been indicated to be defective by the manufacturer of a flash memory device 2.
  • bad block table 16e is updated to include an identifier of the defective block so as to prevent usage of the defective block for storing data.
  • Training circuit 13 optionally receives hyperparameters for a DNN 16c and performs neural network training to identify parameters for an outlier-block DNN.
  • training circuit 13 includes a specialized hardware circuit (e.g., a specialized configurable accelerator) to perform the neural network training operation.
  • training circuit 13 includes a processor and software operable on the processor performs training using a mini-batch training process to generate an outlier-block DNN and to generate and store configuration files for the outlier-block DNN.
  • mini-batch training algorithm is a training algorithm in which the number of training items that is used to perform a single iteration of training is less than the total number of training items that are used to perform training, and where the number of training items that are used to perform a single iteration of training is greater than one.
  • FIG. 2 illustrates a method (100) for outlier management at a flash controller that uses TVSO values for performing reads of a flash memory device.
  • Hyperparameters for a DNN are optionally received (101).
  • I/O circuit 11 optionally receives the initial hyperparameters from an external source such as a host computing device and stores the hyperparameters 16c in data storage circuit 4.
  • hyperparameters 16c are stored in memory device (DRAM) 14.
  • the hyperparameters can include one or more of: the number of layers, the number of neurons in each layer, the training algorithm to use, type of test to be used in the testing the trained DNN and a training error threshold (TET) for the testing, the batch size, the number of iterations of each mini-batch, initial weights and initial bias values.
  • TET training error threshold
  • Hyperparameters for a deep neural network are loaded (102) into a training circuit of the flash controller.
  • the first time that step 102 is performed the initial set of hyperparameters optionally received in step 101 is loaded into training circuit 13.
  • control circuit 9 loads hyperparameters 16c into training circuit 13.
  • one or more of the following hyperparameters are coupled to training circuit 13 in step 103: the number of layers, the number of neurons in each layer, the training algorithm to, type of test to be used in the testing the trained DNN and TET for the testing, the batch size, the number of iterations for each mini-batch, initial weights and initial bias values.
  • a flash memory device is tested to identify or more outlier blocks of the flash memory device (103), the one or more outlier blocks having a number of errors greater than a first outlier- error threshold (OET1).
  • control circuit 9 identifies one or more outlier blocks of the flash memory devices 2, the outlier blocks having a number of errors greater than OET1.
  • the term “outlier block,” as used in the present application is a block of a flash memory device 2 having a number of errors greater than an error threshold and specifically includes a block of a flash memory device 2 having a number of errors greater than OET1.
  • outlier blocks are identified by determining the number of errors from a read and comparing it to an OET1 (e.g., that may be set by a user) and those blocks having an error exceeding OET1 are identified to be outlier blocks.
  • the OET1 is a value that is set to be above the average error for the blocks being tested by a predetermined amount (e.g., twenty percent above the average).
  • background reads are performed and a running average error for the background reads is calculated and compared to the number of errors in the memory location being tested, and when the error of a memory location being tested exceeds the average error by the predetermined amount (e.g., twenty percent) the block containing the memory location being tested is determined to be an outlier block.
  • a plurality of test reads of the one or more outlier blocks are performed (104) and a number of errors in the test reads is identified (105).
  • read circuit 6 performs a plurality of test reads of the identified one or more outlier blocks and decode circuit 7 identifies the number of errors in the test reads of the identified one or more outlier blocks.
  • each iteration of step 104 includes a set of “N” test reads of the one or more outlier block, where N is equal to the batch size received in step 101. In one example N is fifty. However, N could also be five or ten. In one example the batch size and “N” is configurable by the user, with the user providing the input batch size in step 101.
  • control circuit 9 communicates a read command to read circuit 6.
  • Read circuit 6, in response to the read command sends the read command to the flash memory device 2 over one of channels 17-19 to read a particular memory location in the outlier block of one of flash memory devices 2.
  • the response to the read command is received at read circuit 6 and is coupled to decode module 7 for decoding.
  • Decode module 7 decodes the response to the read command and identifies the number of errors in the read. The number of errors in the read is coupled to training circuit 13 along with the feature values corresponding to the read that was performed.
  • training circuit 13 includes input registers and/or a cache memory configured to store the received data records.
  • a data record 30 is formed after each read that indicates the feature values corresponding to the read and the identified number of errors in the read.
  • Data record 30 includes wordline index 31 that indicates the wordline of the memory location that was read, a block index 32 indicating the bock of the memory location that was read, a page index 33 indicating the page of the memory location that was read, the number of program and erase (PE) cycles for the block containing the memory location that was read 34, the RT of the block containing the memory location that was read 35, the RD of the block containing the memory location that was read 36, the TVSO values 37-43 used to perform the read (TVSOl, TVS02, TVS03, TVS04, TVS05, TVS06 and TVS07) and the number of errors in the read (E) 44.
  • PE program and erase
  • the DNN is trained (106) at the training circuit using a mini-batch training process and using the identified number of errors in the test reads.
  • training circuit 13 trains the DNN using a mini-batch training process and using the identified number of errors in the test reads.
  • feature values 31-33 and 35-36 PE is not required for the training
  • TVSO values 37-43 and E 44 of each data record 30 are entered into training circuit 13 that performs mini-batch training to generate outlier-block DNN 45 that predicts TVSO values that minimize E 44.
  • outlier-block DNN is a DNN that generates output indicating a set of TVSO values to be used for reading memory locations in the one or more outlier block (e.g., TVSO values that produce a minimum amount of error or an amount of error proximate a minimum amount of error when reading the particular memory location), and specifically includes a DNN that generates a set of TVSO values to be used for reading memory locations in a single outlier block, and further specifically includes a DNN that generates output indicating a set of TVSO values that produce a minimum amount of error (or an amount of error proximate a minimum amount of error) when reading a particular memory location in the single outlier block.
  • step 105 uses the indicated batch size and the indicated training algorithm.
  • step 106 includes generating a neural network framework having the number of layers, the number of neurons in each layer and initial weights and initial bias values indicated by the hyperparameters optionally entered in step 101.
  • the training process uses the training algorithm, the batch size, and the number of iterations in each mini-batch optionally entered in step 101 to perform the training.
  • the trained DNN is tested (107) to determine whether the trained DNN meets the TET.
  • training circuit 13 tests the trained DNN to determine whether the trained DNN meets the TET.
  • the hyperparameters optionally received in step 101 indicating the type of test to be used in testing the trained DNN a TET for the testing
  • the testing of step 107 uses the indicated type of test and the indicated TET.
  • the input indicating the type of test indicates a min-squared error test and the TET is a min-squared error rate.
  • Steps 104-110 are repeated until the trained DNN meets the TET in step 108.
  • the training produces an outlier-block DNN and the parameters of the outlier-block DNN are optionally stored as shown by step 112.
  • the parameters consist of weights and bias values
  • training circuit 13 stores a configuration file 16d for the outlier-block DNN in data storage 4 that includes the parameters.
  • the configuration file 16d for each outlier-block DNN includes, in addition to the parameters for the particular outlier-block DNN, values indicating the architecture of the outlier-block DNN such as the number of layers, the number of neurons in each layer, the connections between neurons and the type of activation function to use.
  • the outlier-block is defective.
  • the total number of iterations (I) in the training of a particular outlier block is determined by incrementing a counter (109) each time that the trained DNN fails to meet the TET and I is compared to a first outlier-block failure threshold (FIT) (110).
  • FIT can be set by the user or the manufacturer of SSD 1, and can be a number sufficiently large such that the training process is unlikely to converge on results that meet the TET.
  • I exceeds FIT the outlier-block is marked as a bad block (111) (e.g., by storing a value identifying the bad block (e.g. the block number) in bad block table 16e) such that the outlier-block is no longer used (it is “retired”).
  • FIG. 5 shows an example in which arrow 55 indicates the identification of a first outlier- block, arrow 56 indicates when the outlier-block DNN (the first-outlier-block DNN) is generated that predicts a set of TVSO values for the first outlier-block; and in which curved line 51 illustrates the error rate of the mini-batch training process.
  • Each iteration of step 106 is a “mini batch” of the training process and is indicated by one of lines B1 through B5, where a first set of M iterations are performed in a first mini-batch Bl, a second set of M iterations are performed in a second mini-batch B2, a third set of M iterations are performed in a third mini-batch B3, a fourth set of M iterations are performed in a second mini-batch B4 and a fifth set of M iterations are performed in a fifth mini-batch B5.
  • the y-axis of FIG. 5 indicates error, and the x-axis indicates the number of iterations.
  • steps 104-105 is indicated by one of lines 52- 1 through 52-6, including a first set of test reads and number of errors identification 52-1, a second set of test reads and number of errors identification 52-2, a third set of test reads and number of errors identification 52-3, a fourth set of test reads and number of errors identification 52-4, a fifth set of test reads and number of errors identification 52-5 and a sixth set of test reads and number of errors identification 52-6.
  • the TET is a min error rate of 10 that is shown as dashed line 59.
  • the number of test reads in each iteration of steps 104-105 is N (e.g., N memory locations in the outlier block are read and error is determined for all N reads), and all N samples are used in each iteration of the training process, with each iteration of step 106 (each mini-batch processing step) including M iterations of training in which the data records from all N reads (N data records) are used (where “M” is the number of iterations in each mini-batch).
  • the records 30 from the first set of reads and number of errors determination 52-1 is used to perform training of mini-batch Bl; the records 30 from the second set of reads and number of errors determination 52-2 is used to perform training of mini-batch B2; the records 30 from the third set of reads and number of errors determination 52- 3 is used to perform training of mini-batch B3; the records 30 from the fourth set of reads and number of errors determination 52-4 is used to perform training of mini-batch B4; and the records 30 from the fifth set of reads and number of errors determination 52-5 is used to perform training of mini-batch B5.
  • mini-batch B 1 through B5 each include M iterations, and in each iteration all N data records are input into the training circuit 13 and are used to train the DNN.
  • the mean gradient of the mini-batch is calculated and is used to update the weights and bias values.
  • Mini-batch Bl starts with the initial weights and bias values optionally received in step 101 and reads/error determination 52-1 are input into training circuit 13 and M iterations of training using the N training records are performed, the mean gradient of the mini-batch is calculated and used to update the weights and bias values.
  • the testing of step 107 is performed after the training of each mini-batch. More particularly, testing is performed after mini-batch Bl to determine that the trained DNN does not meet the TET (since the trained DNN after mini-batch B 1 has a min error rate exceeding 10 ); testing is performed after mini-batch B2 to determine that the trained DNN does not meet the TET (since the trained DNN after mini-batch B2 has a min error rate exceeding 10 ); testing is performed after mini-batch B3 to determine that the trained DNN does not meet the TET (since the trained DNN after mini-batch B3 has a min error rate exceeding 10 ); testing is performed after mini-batch B4 to determine that the trained DNN does not meet the TET (since the trained DNN after mini-batch B4 has a min error rate exceeding 10 ); and testing is performed after mini-batch B5 to determine that the trained DNN does meet the TET (since the trained DNN after mini-batch B5 has a min error rate that does not exceed
  • the iterative process of steps 104-107 ends and the trained DNN resulting from the training of mini-batch B5 is determined to be the first outlier-block DNN 56.
  • the parameters are stored (e.g., by training circuit 13) in configuration file for outlier-block DNN 16d (that may also be referred to hereinafter as an “outlier-block DNN configuration file”) along with values indicating the architecture of the outlier-block DNN, including the number of layers, the number of neurons in each layer, the connections between neurons and the type of activation function to be performed.
  • FIG. 6 shows an example in which a second outlier-block is identified 65 and in which the process of steps 104-107 is continued after the TET is reached to obtain an outlier-block DNN 66 having a lower error rate than that of first outlier-block DNN 56 shown in FIG. 5.
  • the x-axis of FIG. 6 indicates iterations, the y-axis indicates error and curved line 61 illustrates the error rate of the mini-batch training process.
  • FIG 6 shows set of test reads and error identification 62-1, set of test reads and error identification 62-2, set of test reads and error identification 62-3, set of test reads and error identification 62-4, set of test reads and error identification 62-5, set of test reads and error identification 62-6, set of test reads and error identification 62-7, set of test reads and error identification 62-8, set of test reads and error identification 62-9 and set of test reads and error identification 62-10 (that is not used).
  • the process may be extended as illustrated in FIG. 6 after TET is reached when there are no other outlier blocks that have been identified.
  • outlier-block DNN 56 was generated using reads of a single outlier-block (first outlier-block 55) to identify a first set of parameters that are used for identifying TVSO values to be used for reading the first outlier block.
  • outlier-block DNN 66 was generated using reads of a single outlier-block (second outlier-block 65) to identify a second set of parameters that are used for identifying TVSO values to be used for reading the second outlier block.
  • the configuration files for generating outlier-block DNN 56 and 66 are configuration files for an outlier-block DNN for predicting a set of TVSO values for a single outlier-block.
  • an outlier block DNN can be generated that is operable to generate TVSO values for more than one outlier block.
  • each outlier- block DNN 76 predicts TVSO values for a plurality of outlier-blocks.
  • a plurality of outlier-blocks are identified as shown by arrow 75 (step 103 of FIG. 2) and the sets of reads and number of errors determination 72-1 through 72-6 each read N memory locations from the plurality of outlier-blocks (steps 104-105 of FIG. 2).
  • mini-batches B1-B5 train the DNN to predict TVSO values for the plurality of outlier blocks and the testing of step 107 tests the error rate in predicting TVSO values for the plurality of outlier blocks (e.g., both of the outlier blocks).
  • the error rate 71 of the mini-batch training process does not exceed the TET 59 an outlier-block DNN 76 is generated that can predict TVSO values for a plurality of outlier- blocks.
  • a neural network operation is performed (113) at a neural network engine of the flash controller using the identified parameters of the outlier- block DNN to predict a set of TVSO values corresponding to the one or more outlier blocks, that may be referred to hereinafter as a “set of outlier-block TVSO values.”
  • control circuit 9 loads the configuration file for the outlier-block DNN 16d into neural network engine 10.
  • Neural network engine 10 performs a neural network operation using the parameters of the outlier-block DNN to predict the set of outlier-block TVSO values corresponding to the one or more outlier blocks.
  • neural network engine 10 includes configurable logic that is configured using the configuration file for an outlier-block DNN 16d or using other configuration files/data to generate a configured neural network engine that is operable to perform the neural network operation.
  • neural network engine 10 has some or all of the features shown in US Patent Application Serial Number 17/347,388 filed on June 14, 2021, titled “Method and Apparatus for Performing a Neural Network Operation” which is incorporated by reference herein in its entirety.
  • the configuration file indicates a number of input neurons, a number of output neurons, a number of layers of hidden neurons, a number of hidden neurons in each layer of hidden neurons, and a type of activation function module (AFM) (e.g. ReLU AFM, Leaky ReLU AFM, SatLin AFM, symmetric SatLin AFM or linear interpolation AFM).
  • AFM activation function module
  • FIG. 8 shows a diagram of an exemplary outlier-block DNN 90 that includes an input layer 91 including a plurality of input neurons, an output layer 95 including a plurality of output neurons and layers 92-94 of hidden neurons.
  • outlier-block DNN 90 is a neural network configured to predict TVSO values that minimize (or that are proximate the minimum) the number of errors in a read of the flash memory device 2 and the training algorithm is a gradient descend algorithm with five iterations in each mini-batch.
  • Input into the neural network operation includes a WORDLINE INDEX indicating a wordline of the outlier block that is input to a first input neuron, a BLOCK INDEX indicating a block of the outlier block that is input into a second input neuron, a PAGE INDEX indicating a page of the outlier block that is input into a third input neuron, a retention time value (RT VALUE) that indicates the retention time of the outlier block that is into a fourth input neuron, and a read disturb value (RD VALUE) that indicates the number of read disturbs for the outlier block that is entered into a fifth input neuron.
  • WORDLINE INDEX indicating a wordline of the outlier block that is input to a first input neuron
  • BLOCK INDEX indicating a block of the outlier block that is input into a second input neuron
  • PAGE INDEX indicating a page of the outlier block that is input into a third input neuron
  • RT VALUE retention
  • output neurons 95 include a first output neuron that generates output indicating a TVSO value for a first threshold voltage offset region (TVSOl), a second output neuron that generates output indicating a TVSO value for a second threshold voltage offset region (TVS02) a third output neuron that generates output indicating a TVSO value for a third threshold voltage offset region (TVS03); a fourth output neuron that generates output indicating a TVSO value for a fourth threshold voltage offset region (TVS04); a fifth output neuron that generates output indicating a TVSO value for a fifth threshold voltage offset region (TVS05); a sixth output neuron that generates output indicating a TVSO value for a sixth threshold voltage offset region (TVS06); and a seventh output neuron that generates output indicating a TVSO value for a seventh threshold voltage offset region (TVS07).
  • TVSOl threshold voltage offset region
  • TVS02 second threshold voltage offset region
  • TVS03 third threshold voltage offset region
  • TVS04 a fourth output neuro
  • the output TVSO values TVS01-TVS07 from the neural network operation indicate TVSO values that minimize (or that are proximate the minimum) the number of errors when performing a read of the particular outlier-block.
  • the seven threshold values represent the number of threshold values needed for a TLC memory device, however the embodiments are not meant to be so limited.
  • the predicted set of outlier-block TVSO values are optionally stored (114) in a TVSO- read table by replacing TVSO values previously stored in the TVSO-read table with the predicted set of outlier-block TVSO values.
  • control circuit 9 and/or neural network 10 stores the predicted set of outlier-block TVSO values from the neural network operation in TVSO-read table 16b.
  • the predicted set of outlier-block TVSO values for the outlier block stored in the TVSO-read table replace the TVSO values (e.g., PE- based-reliability-state TVSO values) previously stored in TVSO-read table 16b.
  • read circuit 6 performs a read using the predicted set of outlier-block TVSO values.
  • flash controller 3 receives a read instructions from a host computer at I/O circuit 11 and read circuit 6, upon receiving the read instruction, performs a lookup in TVSO-read table 16b using the current status (e.g., current number of read disturbs and retention time) of the memory location of the flash memory device 2 that is to be read to identify the set of outlier-block TVSO values to use in performing the read; sends a read command that includes the identified set of outlier-block TVSO values to a flash memory device 2 that is to be read; receives a response from the flash memory device 2 and decode circuit 7 decodes the results from the read command.
  • current status e.g., current number of read disturbs and retention time
  • training circuit 13, decode circuit 7 and control circuit 9 repeat the testing flash memory device to identify one or more additional outlier-block, the performing the plurality of test reads, the identifying the number of errors in the test reads, the training and the testing until the trained DNN meets the training error threshold to identify parameters of an additional outlier-block DNN (for the one or more additional outlier-block) and a neural network operation of the additional outlier-block DNN is performed to predict an additional set of outlier-block TVSO values to be used for reading the one or more additional outlier-block.
  • step 104-108 a single outlier-block DNN is trained to identify a set of outlier-block TVSO values for the single outlier block. Accordingly, step 103 will identify a single outlier-block, step 104 will perform test reads of the single outlier-block, step 105 will identify the number of errors in the test reads of the single outlier-block and the neural network operation of step 113 will generate a predicted set of outlier-block TVSO values for the single outlier block. In this example, the testing and identifying additional sets of outlier-block TVSO values is repeated (line 121) in the same manner.
  • step 103 will identify an additional (single) outlier-block
  • step 104 will perform test reads of the additional (single) outlier-block
  • step 105 will identify the number of errors in the test reads of the additional (single) outlier-block
  • the neural network operation of step 113 will generate a predicted set of outlier-block TVSO values for the additional (single) outlier block.
  • all configuration files for an outlier-block DNN stored in step 112 and all outlier-block DNN’s used to perform neural network operations in step 113 predict a set of outlier-block TVSO values for a single outlier block.
  • the outlier-block DNN is a neural network for identifying TVSO values for a single outlier block or for a small number of outlier- blocks, the accuracy of the TVSO value prediction is improved as compared to TVSO values identified using PE-based-reliability-states that predict TVSO values for a large number of blocks because the outlier-block DNN does not have to encompass a wide range of samples (data for numerous blocks, all of which have different characteristics) and a wide span of PE cycles.
  • Method 100 is performed to generate and optionally store predicted TVSO values for outlier blocks. It is appreciated that the PE-based-reliability-state TVSO values for non-outlier blocks will vary with the number of PE cycles and the sets of outlier-block TVSO values will not vary with increasing PE cycles. Accordingly, in the example in which TVSO-read table 16b includes only a PE cycle index and block number index associated with each set of PE-based- reliability-state TVSO values, each of the sets of outlier-block TVSO values will be stored by replacing all corresponding PE-based-reliability-state TVSO values for the particular block number without regard to the number of PE cycles, such that the predicted set of outlier- block TVSO values will be used for all subsequent values of PE cycles. In FIG. 1 both the PE-based- reliability-state TVSO values for non-outlier blocks and sets of outlier-block TVSO values are stored in TVSO-read table 16b.
  • step 201 includes testing a single outlier-block by performing one or more reads of the single outlier- block after some or all of the steps of method 100 have been performed, determining the number of errors in the one or more reads of the single outlier-block and comparing the number of errors in the one or more reads of the single outlier- block to a second outlier-error threshold (OET2).
  • OET2 second outlier-error threshold
  • the outlier-block being tested fails the outlier- block testing and the method moves to step 203.
  • an outlier-block is defective and that it will repeatedly fail outlier- block testing of step 201.
  • an outlier block failure count is incremented (203) and when the outlier-block failure count exceeds (204) a second outlier-block failure threshold (FT2) the outlier-block is retired by marking it as a bad block (206).
  • FT2 second outlier-block failure threshold
  • the outlier-block is retired by storing an index identifying the block (e.g., the block number) in bad block table 16e.
  • FT2 is initially set to a default value and can be set by the user or the manufacturer of SSD. In one example FT2 is set low enough so as to prevent an outlier-block from unnecessarily consuming power and other resources of flash controller 3, but high enough to allow most outlier-blocks to continue to be used for the remainder of the life of the outlier-block.
  • an updated set of predicted outlier-block TVSO values are generated (and optionally stored) for the outlier-block that failed the outlier-block testing (205) by repeating steps 104-108 and 113 (and optionally steps 109-112 and 114) of method 100.
  • the sets of outlier- block TVSO values are kept current, maintaining UBER of the SSD within acceptable levels during the lifetime of the SSD.
  • the method and apparatus of FIGS 1-9 manages outlier blocks by performing neural network operations that accurately predict the TVSO values to be used for reading outlier blocks, allowing the outlier blocks to continue to be used even after they are identified as outlier-blocks.
  • the method and apparatus of the present invention does not require that outlier blocks be marked as bad blocks and retired as soon as they are identified as outlier blocks in order to prevent uncorrectable bit errors.
  • the life of outlier-blocks is extended and the amount of blocks available to store information is increased as compared to systems that mark outlier blocks as bad blocs as soon as they are identified as outlier blocks. Accordingly, the present method and apparatus extends the useful life of outlier blocks while maintaining UBER of the SSD within acceptable levels during the lifetime of the SSD.

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Abstract

Procédé de gestion de valeurs aberrantes au niveau d'un contrôleur flash consistant à tester un dispositif de mémoire flash afin d'identifier un ou plusieurs blocs de valeurs aberrantes du dispositif de mémoire flash. Des hyperparamètres pour un DNN sont chargés dans un circuit d'apprentissage. Des lectures de test du ou des blocs de valeurs aberrantes sont mises en œuvre et un nombre d'erreurs dans les lectures de test est identifié. Le DNN est entraîné au moyen d'un procédé d'apprentissage par mini-lots et au moyen du nombre identifié d'erreurs dans les lectures de test et est testé afin de déterminer si le DNN entraîné satisfait un seuil d'erreur d'apprentissage. La mise en œuvre, l'identification, l'apprentissage et le test sont répétés jusqu'à ce que le DNN entraîné satisfasse au seuil d'erreurs d'apprentissage afin d'identifier des paramètres d'un DNN à bloc de valeurs aberrantes. Une opération de réseau neuronal est mise en œuvre au moyen des paramètres identifiés afin de prédire un ensemble de valeurs TVSO. Une lecture est mise en œuvre au moyen de l'ensemble de valeurs TVSO prédites.
PCT/US2022/011036 2021-05-28 2022-01-03 Procédé et appareil de gestion de valeurs aberrantes Ceased WO2022250741A1 (fr)

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US20170133107A1 (en) * 2014-08-04 2017-05-11 Conor Maurice Ryan Preventive Measures for Adaptive Flash Tuning
US20180033490A1 (en) * 2016-07-28 2018-02-01 Ip Gem Group, Llc Nonvolatile memory system with background reference positioning and local reference positioning
US10490288B1 (en) * 2018-09-27 2019-11-26 Seagate Technology Llc Page-level reference voltage parameterization for solid statesolid state storage devices
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