WO2022104991A1 - Control apparatus and brain-inspired computing system - Google Patents

Abstract

A control apparatus and a brain-inspired computing system. The apparatus comprises: a first trigger module (10); a second trigger module (20); a multiplexer (30) electrically connected to the first trigger module (10) and the second trigger module (20); and a control module (40) electrically connected to the multiplexer module (30) and used for controlling the multiplexer (30) to transmit any one first trigger signal of one or more first trigger signals and any one second trigger signal of one or more second trigger signals to one or more functional cores in a processor (1), such that the one or more functional cores execute a sub-task of a task according to the received first trigger signal and the second trigger signal. According to the apparatus, segmentation of an independent task can be achieved, thereby increasing the execution speed, reducing running time, improving chip performance, and reducing power consumption.

Description

Control device and brain-like computing system technical field

The present disclosure relates to the technical field of artificial intelligence, and in particular, to a control device and a brain-like computing system.

Background technique

The booming development of big data information networks and intelligent mobile devices has produced massive amounts of unstructured information, accompanied by a sharp increase in the demand for energy-efficient processing of such information. The traditional Von Neumann architecture chip adopts bus communication, synchronization, serial and centralized working methods, and follows Moore's Law to increase the density. It is expected that in the next 10 to 15 years, the miniaturization will reach the physical limit, and the development will be fundamentally limited.

From this, a many-core neuromorphic chip architecture is derived. This structure is different from the traditional computer processing method. Through the distributed storage of information and parallel collaborative processing, it has great advantages in dealing with some informal problems. However, the triggering mechanism of the traditional many-core neuromorphic chip architecture has great limitations and cannot perform independent task division.

SUMMARY OF THE INVENTION

In view of this, the present disclosure proposes a control device, which includes:

a first trigger module for generating one or more first trigger signals, wherein each first trigger signal corresponds to each task;

a second trigger module, electrically connected to the first trigger module, and configured to generate one or more second trigger signals according to the first trigger signal, wherein the second trigger signals correspond to subtasks of the task;

a multiplexer, electrically connected to the first trigger module and the second trigger module;

A control module, electrically connected to the multiplexing module, for controlling the multiplexer to select any one of the one or more first trigger signals and the one or more first trigger signals Any one of the two trigger signals and the second trigger signal are transmitted to one or more functional cores in the processor, so that the one or more functional cores execute the subtasks of the task according to the received first trigger signal and the second trigger signal .

In a possible implementation manner, the apparatus further includes a first timing module electrically connected to the first trigger module, the first timing module includes a first timing clock, and the first timing module is used for When receiving the first trigger signal, start the first timing clock to time the execution period of the current task;

The first triggering module is further configured to determine that the trigger is satisfied when the first timing clock reaches a first threshold, and all subtasks of the current task all finish executing and the current task is not the last task conditions of the execution cycle of the next task, and generate a first trigger signal corresponding to the execution cycle of the next task.

In a possible implementation manner, the first triggering module is further configured to, when the first timing clock reaches a third threshold, generate a forcible end signal, where the forcible end signal is used to forcibly end the The execution of the current subtasks in the current task, thereby forcibly ending the execution of the current task;

The control module is further configured to transmit the forced termination signal to each functional core of the current task by using the multiplexer.

In a possible implementation manner, the apparatus further includes a second timing module electrically connected to the second trigger module, the second timing module includes one or more second timing clocks, the second timing The module is used to start the one or more second timing clocks when receiving the second trigger signal to time the execution cycle of each subtask of the current task,

The second triggering module is further configured to determine that when the second timing clock reaches a second threshold, and the functional cores corresponding to the second trigger signals all complete the execution of the current subtasks The conditions for triggering the execution cycle of the next subtask of each current subtask in the current task are triggered, and the second trigger signal corresponding to each next subtask is generated.

In a possible implementation manner, the control module is further configured to receive an operation end signal output by each function core corresponding to the second trigger signal, and generate a subtask end when each function core outputs an operation end signal signal to determine that all functional cores corresponding to the second trigger signal end the execution of the current subtask;

The device also includes:

The first storage module, electrically connected to the control module, is used for storing the subtask end signal.

In a possible implementation manner, the control module is further configured to generate a task end signal when the subtask end signals of all subtasks of the current task are stored in the first storage module to determine the All subtasks of the current task corresponding to the first trigger signal all finish execution;

The device also includes:

A second storage module, electrically connected to the control module, is used for storing the task end signal.

In a possible implementation manner, the control module is further configured to assign functional cores to each task and subtasks of each task, number the functional cores in the processor, and assign the first functional core to each task. The sets are numbered, and the second function core sets corresponding to each subtask of each task are numbered.

In a possible implementation manner, the apparatus includes a plurality of phase group registers, a first selection register, a function core register, and a second selection register, wherein,

The phase group register is configured as a two-dimensional register with a size of s*n bits, the first dimension represents the current task number, and the second dimension includes the subtask number of the current task, where s and n are positive integers;

The first selection register is configured as a two-dimensional register with a size of m*y bits, the first dimension represents the current functional core number, and the second dimension represents the task number to which the current functional core belongs, wherein m and y are positive. integer, and y=log ₂ s;

The functional core register is configured as a two-dimensional register with a size of n*m bits, the first dimension represents the subtask number, and the second dimension represents the functional core included in the subtask;

The second selection register is configured as a two-dimensional register with a size of m*x bits, the first dimension represents the number of the functional core, and the second dimension represents the subtask number described by the current functional core, where x=log ₂ n .

In a possible implementation manner, the control module is further configured to:

Release the function core in the processor corresponding to the first trigger signal under the condition that a preset condition is satisfied, and the preset condition includes:

The current task is the last task and the execution of the current task ends; or

When forcibly ending the execution of the current task.

According to another aspect of the present disclosure, a brain-like computing system is provided, the system including the control device.

Through the above device, the embodiment of the present disclosure can generate one or more first trigger signals according to the number of tasks to be executed, and generate one or more second trigger signals, according to the first trigger signal, one or more second trigger signals The signal controls the corresponding function core to execute each subtask of the current task, which can support parallel or mixed operations of multiple asynchronous tasks. At the same time, by dividing the current task into subtasks, the function cores with similar tasks can be executed at the same time, so that Through the two-level trigger mechanism, the independent tasks can be divided, the execution speed can be accelerated, the running time can be reduced, and the performance of the chip can be improved. thereby reducing power consumption. The task may be a network or application task, such as a task of performing neural network operations (for example, a VGG network or a ResNet50 network), or a task of running application software, and the like.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure, and together with the description, serve to explain the principles of the disclosure.

FIG. 1 shows a schematic diagram of a control device according to an embodiment of the present disclosure.

FIG. 2 shows a schematic diagram of grouping of processor functional cores according to an embodiment of the present disclosure.

FIG. 3 shows a schematic diagram of a triggering sequence of a control apparatus according to an embodiment of the present disclosure.

FIG. 4 shows a schematic diagram of a triggering sequence of a control apparatus according to an embodiment of the present disclosure.

FIG. 5 shows a schematic diagram of a control device according to an embodiment of the present disclosure.

6a and 6b show schematic diagrams of a control device according to an embodiment of the present disclosure.

Detailed ways

Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numbers in the figures denote elements that have the same or similar functions. While various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

As used in this disclosure, "first," "second," and similar terms do not denote any order, quantity, or importance, but are merely used to distinguish the various components. Likewise, words such as "a," "an," or "the" do not denote a limitation of quantity, but rather denote the presence of at least one. "Comprises" or "comprising" and similar words mean that the elements or things appearing before the word encompass the elements or things recited after the word and their equivalents, but do not exclude other elements or things. Words like "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following detailed description. It will be understood by those skilled in the art that the present disclosure may be practiced without certain specific details. In some instances, methods, means, components and circuits well known to those skilled in the art have not been described in detail so as not to obscure the subject matter of the present disclosure.

With the continuous development of neural network technology, massive amounts of unstructured information have been generated, accompanied by a sharp increase in the demand for energy-efficient processing of such information. Among them, the many-core neuromorphic chip architecture is different from the traditional computer processing method. Through the distributed storage of information and parallel collaborative processing, it has great advantages in dealing with some informal problems. However, the trigger mechanism in the traditional chip cannot perform independent network task division when executing multiple networks, and has great limitations.

In order to further improve performance, an embodiment of the present disclosure provides a control device, through two-level triggering control function cores, the first-level triggering can divide different networks or applications, and the second-level triggering can divide networks or similar calculations within applications The task is assigned to perform operations in the functional core, which effectively improves the performance of the chip and has high application value.

Please refer to FIG. 1 , which shows a schematic diagram of a control device according to an embodiment of the present disclosure.

As shown in Figure 1, the device includes:

a first trigger module 10, configured to generate one or more first trigger signals, wherein each first trigger signal corresponds to each task;

The second triggering module 20 is electrically connected to the first triggering module 10, and is configured to generate one or more second triggering signals according to the first triggering signal, wherein the second triggering signal corresponds to the subtask of the task;

The multiplexer 30 is electrically connected to the first trigger module 10 and the second trigger module 20;

The control module 40, electrically connected to the multiplexing module 30, is used to control the multiplexer 30 to select any one of the one or more first trigger signals and the one or more first trigger signals. Any one of the multiple second trigger signals is transmitted to one or more functional cores in the processor 1, so that the one or more functional cores execute according to the received first trigger signal and the second trigger signal Subtasks of tasks.

Through the above device, the embodiment of the present disclosure can generate one or more first trigger signals according to the number of tasks to be executed, and generate one or more second trigger signals, according to the first trigger signal, one or more second trigger signals The signal controls the corresponding function core to execute each subtask of the current task, which can support parallel or mixed operations of multiple asynchronous tasks. At the same time, by dividing the current task into subtasks, the function cores with similar tasks can be executed at the same time, so that Through the two-level trigger mechanism, the independent tasks can be divided, the execution speed can be accelerated, the running time can be reduced, and the performance of the chip can be improved. thereby reducing power consumption. The task may be a network or application task, such as a task of performing neural network operations (for example, a VGG network or a ResNet50 network), or a task of running application software, and the like.

The control apparatus in the embodiment of the present disclosure may be used in a terminal or a server. The terminal is also called user equipment (UE), mobile station (MS), mobile terminal (MT), etc., and is a A device that provides voice and/or data connectivity to a user, eg, a handheld device with wireless connectivity, an in-vehicle device, etc. At present, some examples of terminals are: mobile phone (mobile phone), tablet computer, notebook computer, PDA, mobile internet device (MID), wearable device, virtual reality (virtual reality, VR) device, augmented reality ( augmentedreality (AR) equipment, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grid , wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, wireless terminal in car networking, etc.

Each module of the embodiments of the present disclosure may be implemented by a dedicated hardware circuit or a general-purpose hardware circuit. Exemplarily, the control module may include a controller with a function of executing instructions, and the control module may be implemented in any appropriate manner. The implementation, for example, can be implemented by a microprocessor, a central processing unit (CPU), a control logic part in a memory controller, etc., including but not limited to the following types of chips: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicon Labs C8051F320. Inside the processor 101, the executable instructions may be executed by hardware circuits such as logic gates, switches, application specific integrated circuits (ASICs), programmable logic controllers and embedded microcontrollers.

Please refer to FIG. 2 , which shows a schematic diagram of grouping of processor functional cores according to an embodiment of the present disclosure.

In a possible implementation, the processor to which the apparatus of the embodiment of the present disclosure can be applied may be a many-core neuromorphic chip. As shown in FIG. 2 , the processor may include multiple functional cores, which may The functional cores of the processor are grouped.

In an example, as shown in FIG. 2 , step_grp (beat timing group) and Phase_grp (phase timing group) may respectively represent corresponding functional core sets, and step_grp0 , step_grp1 , and step_grp2 represent functional core sets corresponding to each first trigger signal , Phase_grp0, Phase_grp1, Phase_grp2, Phase_grp3, Phase_grp4, Phase_grp5 represent functional core sets corresponding to each second trigger signal, and C00 to C44 represent different functional cores. For example, Phase_grp0 corresponds to the functional core set including functional cores C00, C01, C10, and C11, Phase_grp1, Phase_grp2, Phase_grp3, Phase_grp4, Phase_grp5 are related to the functional cores in the same way, and step_grp0 corresponds to Phase_grp0, Phase_grp1, and Phase_grp2. The relationship between the three functional core sets, step_grp1, step_grp2 and Phase_grp3, Phase_grp4, Phase_grp5 is the same, as shown in Figure 2, a Phase_grp can be included in one or more step_grp, a functional core can be included in one or more In multiple Phase_grp (such as C13 is included in Phase_grp1, and is included in Phase_grp3 at the same time), in an example, if it is two completely independent networks, their functional core sets do not have overlapping functional cores (such as step_grp2 and step_grp3) ), if the two networks have data interaction, then their functional core sets can have overlapping functional cores, which can be used for data interaction or have other functions (for example, C13 is included in Phase_grp1, and is also included in Phase_grp3. ).

In one example, the same step_grp can be used to perform the same network task, each Phase_grp under the same step_grp can be used to perform the same or similar tasks under the same network task, the functional cores under the same Phase_grp can be used to perform primitive operations, In a possible implementation manner, after finishing a certain network task or application task, the functional core set may be re-divided.

In a possible implementation manner, the control device can be applied to a system-on-chip including a plurality of functional cores (or called processor cores), and each first trigger signal corresponds to a part of the functional cores in the system-on-chip, that is, a function A set of cores, the first trigger signal can trigger these functional cores to work by generating a second trigger signal, and each subtask can be executed, and each second trigger signal can correspond to one or more of the part of the functional cores. The correspondence between the first trigger signal, the second trigger signal and the functional core can be set manually or automatically as required. The above-mentioned corresponding relationship can be released after a complete task (for example, a neural network operation is completed), so as to be reset later.

In a possible implementation manner, the corresponding relationship between the first trigger signal, the second trigger signal and the functional core may be reset before starting a complete task. Specifically, if there are a sufficient number of required If there are idle function cores, you can complete the settings and start executing a complete task. If there are no idle function cores, you can wait for other tasks to finish executing and release the function cores. After the number of idle function cores meets the needs, complete the settings and start. perform a complete task. Since the same function core can correspond to different second trigger signals or first trigger signals, the multiplexing signal can be set for the multiplexable function core after the setting is completed, so that when the function core is set to the function core in other tasks, It can be used as an idle functional core to participate in the operation, so that the functional core can be fully utilized, and the performance and utilization rate of the system can be improved.

In a possible implementation manner, the execution cycle of the current task may include execution cycles of one or more subtasks, that is, between two first trigger signals, multiple cycles of second trigger signals may appear. Taking the neural network operation task as an example, for a neural network with a small amount of operation, the first trigger signal can complete one operation (current task) of the entire neural network in one execution cycle, wherein the second trigger signal is in each cycle. It can complete a link of neural network operation, such as the operation of a network layer, and the function core corresponding to each second trigger signal can perform similar operations (subtasks) in each link, such as addition or multiplication. to perform the corresponding primitive operation. For example, still taking Figure 2 as an example, the four functional cores C00, C01, C10, and C11 corresponding to Phase_grp0 can perform addition respectively, and the six functional cores C02, C03, C12, C13, C22, and C23 corresponding to Phase_grp1 can perform multiplication respectively. , etc., which are not limited in the present disclosure. For a neural network with a large amount of computation, the first trigger signal can complete a link in one operation of the entire neural network in one execution cycle, such as the operation of a network layer (current task), that is, the current task can also It is a subtask of a higher-level task (the entire neural network operation task). In this case, the settings of the functional core between the subtasks can be used, and the functional core does not need to be released between the subtask and the execution cycle of the subtask. redistrict. The second trigger signal can complete a part of a link in each cycle, such as a convolution operation in a network layer operation, and the function core corresponding to each second trigger signal can perform similar operations in each link ( subtask), in a possible implementation manner, after completing a link of the neural network operation task, the corresponding relationship between the first trigger signal and the second trigger signal and the functional core can be used, and after completing the entire neural network task, Release the functional core.

In a possible implementation manner, the first trigger module may generate the first trigger signal according to an external input signal, or may generate the first trigger signal by itself. For example, the apparatus may further include an external trigger module 90 (as shown in FIG. 5 ). For the initial first trigger signal, when a new task needs to be performed, the external trigger module 90 may generate and input a start signal, so that the first trigger signal needs to be executed. A trigger module generates the first trigger signal, or the external trigger module 90 can directly generate the first trigger signal; during the execution of the task, the first trigger module can generate a new first trigger signal when judging that the task period is not over. It will be introduced in detail below.

Please refer to FIG. 3 , which shows a schematic diagram of a trigger sequence of a control apparatus according to an embodiment of the present disclosure.

Among them, clk represents the reference clock, and if clk is set to 1, it represents the number of reference clocks; step group0 and step group1 represent the functional core set (or called beat timing group) corresponding to each first trigger signal, and different first trigger signals can be used with In triggering the respective corresponding functional core sets to perform different tasks, for example, a first trigger signal is used to perform a computing task of a neural network, and another first trigger signal is used to perform a computing task of another neural network, or an application software operation tasks, etc. The function core set corresponding to the first trigger signal can be called a beat timing group; step_ck0 represents the first trigger signal corresponding to step group0, which can be called the beat trigger signal corresponding to step group0; step_ck0 is set to 1 to indicate that a beat trigger signal is received; step_ck1 represents the beat trigger signal corresponding to step group1, step_ck1 is set to 1 to indicate that a beat trigger signal is received; p_grp0_ck and p_grp1_ck respectively represent the two second trigger signals corresponding to step group0, the second trigger signal can be called a phase trigger signal, the second trigger signal The set of function cores corresponding to the trigger signal can be called a phase timing group. When the phase trigger signal is set to 1, it means that a phase trigger signal is received; p_grp2_ck, p_grp3_ck and p_grp4_ck respectively represent the three phase trigger signals corresponding to step group1, and the phase trigger signal set to 1 means that A phase trigger signal is received; s_grp0_finish indicates the signal that all the corresponding functional core sets of step group0 have finished executing, that is, the signal that all subtasks of the current task (that is, the task corresponding to step group0) have all finished executing, which can be called step The beat end signal of group0, the beat end signal is set to 1 when all the phase timing groups in step group0 finish executing all corresponding subtasks, otherwise it is set to 0; s_grp1_finish represents the signal that all the corresponding function core sets of step group1 have finished executing, which can be It is called the beat end signal of step group1; it is set to 1 when all the phase timing groups in step group1 finish executing all corresponding subtasks, otherwise it is set to 0.

As shown in Figure 3, in a possible implementation, for step group0, when step_ck0 is received, p_grp0_ck and p_grp1_ck are triggered, and all phase timing groups in step group0 group are triggered at the same time, starting a new phase timing group working cycle ( It can be called execution cycle), wherein the working cycles of the phase timing groups of different phase timing groups can be the same or different. After receiving the beat trigger signal, the beat timing clock (which can be called the first timing clock) can be started. When the number of clocks of the clock is equal to the number of clocks at the end of the beat, you can check whether all the phase timing groups in the beat timing group have finished working, and you can also check whether the signal with s_grp0_finish set to 1 is received. If so (s_grp0_finish is set to 1 at this time), trigger the A beat sequence group work cycle (step_ck0 is automatically set to 1 at this time) or end the work and release all functional cores in the beat sequence group, otherwise wait for all the work to end and start the next beat sequence group work cycle or end the work, if it reaches the mandatory If the work is not all finished when the clock is finished, a forced end signal will be generated to force the execution of all phase timing groups under the beat timing group to end, and the related first timing clock and each second timing clock will be reset to zero. The same is true for step_ck1.

It should be noted that the number of working cycle clocks of the phase timing groups under the same beat timing group can be the same or different; the phase timing groups belonging to the same beat timing group receive the phase trigger signal and trigger their corresponding first sub The tasks are synchronous. After the execution of the first subtask, the automatic triggering of subsequent subtasks of these phase sequence groups can be asynchronous, and the phase sequence groups belonging to different beat sequence groups can be triggered asynchronously. Different beat timing groups can also be asynchronous.

Please refer to FIG. 4 , which shows a schematic diagram of a triggering sequence of a control apparatus according to an embodiment of the present disclosure.

In an example, as shown in Figure 4, clk represents the reference clock, and if clk is set to 1, it represents the number of 1 reference clock; s_ck represents the first trigger signal, which can be called a beat trigger signal, and phase group0 and phase group1 represent different second trigger signals. The function core set corresponding to the trigger signal (or called the phase timing group), and the function core set corresponding to the second trigger signal can be called the phase timing group; s_ck is set to 1 to indicate that a beat trigger signal is received; p_grp0_ck indicates that phase group0 corresponds to the first Two trigger signals, the second trigger signal can be called a phase trigger signal; p_grp0_ck is set to 1 to indicate that a corresponding phase trigger signal is received; p_grp1_ck indicates that the phase trigger signal corresponding to phase group1; p_grp1_ck is set to 1 to indicate that a corresponding phase trigger signal has been received ;core0, core1 and core2 respectively represent the three functional cores under phase group0, core3 and core4 respectively represent the two functional cores under phase group1; p_grp0_finish represents the signal that all the functional cores of phase group0 have finished executing, which can be called phase group0 phase End signal; set to 1 when all functional cores in phase group0 have finished executing operations, otherwise set to 0, p_grp1_finish indicates the signal that all functional cores of phase group1 have finished executing, which can be called the phase end signal of phase group1, and all functional cores in phase group1 have ended Set to 1 if the operation is performed, otherwise set to 0. The beat end signal can be obtained from the phase end signal of the phase sequence group corresponding to each phase sequence group under the beat sequence group, that is to say, s_grp0_finish in FIG. p0, p1, p2 and p3 respectively indicate that the corresponding functional core is in the corresponding execution operation state.

In a possible implementation, as shown in Figure 4, for phase group0, when s_ck is received, p_grp0_ck is triggered synchronously, and all functional cores in the phase group0 group are triggered at the same time to control core0, core1 and core2 to start executing operations, where , the time for different function cores to perform operations can be the same or different. After the function core starts to work, the phase timing clock (which can be called the second timing clock) can be started. When the number of clocks of the phase timing clock is equal to the number of phase end clocks, it can be Check whether the function cores in the phase sequence group all end the current subtask, if so, trigger the next phase sequence group work cycle (can be called the execution cycle), otherwise wait for all the operations to complete the current subtask to start the next phase Timing group duty cycle. If the function check in the phase sequence group completes the execution of all subtasks of the current task, p_grp0_finish is set to 1. When the function core in the phase sequence group does not all finish executing all subtasks of the current task, it will continue to execute until all subtasks are executed. After completion, start the next task, or receive the forced end signal of the beat sequence group, force end all current subtasks. The same is true for phase group1.

It should be noted that the number of clocks performed by each functional core in the same phase timing group can be the same or different; the functional cores belonging to the same phase timing group are triggered synchronously, and the functional cores belonging to different phase timing groups are Can be triggered asynchronously.

The trigger sequence of the control device is exemplarily introduced above, and an exemplary description is given below in conjunction with the possible implementation of the control device.

Please refer to FIG. 5 , which shows a schematic diagram of a control apparatus according to an embodiment of the present disclosure.

In a possible implementation manner, as shown in FIG. 5 , the apparatus may further include a first timing module 50 electrically connected to the first trigger module 10 , and the first timing module 50 may include a first timing module a clock, the first timing module 50 is configured to start the first timing clock when receiving the first trigger signal to time the execution cycle of the current task;

In a possible implementation manner, the first triggering module 10 may also be configured to be used when the first timing clock reaches a first threshold, and all subtasks of the current task all finish executing and the current task If it is not the last task, it is determined that the condition for triggering the execution period of the next task is satisfied, and a first trigger signal corresponding to the execution period of the next task is generated.

In the embodiment of the present disclosure, the execution of all subtasks of the current task is completed, which means that the execution of the current task is completed. The idleness of functional cores can be reduced as much as possible, each functional core can be utilized to the greatest extent, and the execution efficiency can be improved.

In an example, the first threshold may be set in advance, and different first trigger signals may correspond to different first thresholds. For example, the first threshold (number of clocks) can be directly input from the outside, or parameters related to the first threshold can be input, and the control module can perform a correlation operation to determine the first threshold according to the obtained parameters.

In a possible implementation, as shown in FIG. 5 , the apparatus may include a register module 70 .

In one example, the register module 70 may include a first threshold register to receive an externally inputted first threshold.

In one example, the first threshold may be a change value that changes according to different tasks, and is received each time the execution cycle of the current task is triggered, or it may be a preset fixed value that only needs to be received once, and can be repeated later use.

In one example, when the conditions for triggering the execution cycle of the next task are met, the execution cycle of the next task can be triggered, that is, the execution of the next task can be started, and the execution mode of the next task can be the same as that of the current task.

In one example, the first timing clock may be clocked every time a reference clock cycle passes, and it is determined whether the first threshold value is reached.

By setting the first threshold, the embodiments of the present disclosure can realize the pre-control and deployment of the execution cycles of different network applications, thereby realizing the asynchronous and independent running of different tasks, and speeding up the running speed.

In one example, the first timing clock may be restarted from 0 each time a new first trigger signal is generated.

By comparing the timing duration of the first timing clock with the first threshold, it is judged whether the conditions for triggering the execution cycle of the next task are met, so that the execution cycle of the current task can be controlled, so that different tasks can be better scheduled and the running time can be reduced. time and improve execution efficiency.

In a possible implementation manner, the first trigger module 10 may also be configured to generate a forced end signal when the first timing clock reaches a third threshold, where the forced end signal is used for forcibly ending The execution of each current subtask in the current task, thereby forcibly ending the execution of the current task;

In a possible implementation manner, the control module 40 may also be configured to transmit the forced termination signal to each functional core of the current task by using the multiplexer 30, so that each functional core terminates the operation.

In one example, the third threshold may be greater than the first threshold, may be a change value that changes according to different tasks, and is received each time the execution cycle of the current task is triggered, or may be a preset fixed value, which only needs to be You can receive it once, and you can reuse it later.

In one example, the register module 70 may include a third threshold register to store the third threshold, and the third threshold register may be read or written to obtain or set the third threshold.

In one example, when the current task reaches the third threshold and has not yet completed execution, a program error may occur in the current task and cause it to be stuck. For example, for a certain link in a neural network task, the estimated execution The number of clocks required by this link task is 500 clocks. In this way, when the first timing clock reaches 1000 clocks, and the link task has not finished executing, it is likely that a program error has occurred and an infinite loop has entered. Unable to end (this is a morbid state), it needs to be forced to end, so in this case, the third threshold can be set as 1000 clocks, and when the third threshold is reached, the task is not finished, and the task is forced to end. If the current task is a subtask of the upper-level task, the entire upper-level task can be forcibly terminated. After the execution of the entire task is forcibly terminated, the function core set corresponding to the first trigger signal can be released to avoid occupying unnecessary functions. nuclear resources.

By implementing the mechanism of forcibly ending the current task and controlling the maximum number of clocks for the execution of the current task, it is possible to avoid the infinite loop that the task cannot end due to program errors and other reasons, and avoid the possibility of wasting a large number of unnecessary functional core resources. Reduced power consumption and improved operational efficiency.

In a possible implementation manner, as shown in FIG. 5 , the apparatus may further include a second timing module 60 electrically connected to the second trigger module 20 , and the second timing module 60 may include one or more a second timing clock, the second timing module is configured to start the one or more second timing clocks when receiving the second trigger signal, so as to time the execution period of each subtask of the current task,

In a possible implementation manner, the second trigger module 20 may also be configured to end the current state when the second timing clock reaches a second threshold and all the functional cores corresponding to the second trigger signals When each subtask is executed, it is determined that the conditions for triggering the execution cycle of the next subtask of each current subtask in the current task are satisfied, and the second trigger signal corresponding to each next subtask is generated.

In the embodiment of the present disclosure, when the function core set corresponding to the current subtask has not all finished executing, the execution cycle of the next subtask can be triggered after waiting for all the function core set to finish execution, so as to prevent the current subtask from starting the next subtask. A subtask may cause the current task to be stuck in a subtask and cannot continue, thereby preventing the situation of error reporting, enabling the deployment and scheduling of each task to be executed smoothly, and improving the corresponding performance.

In an example, the second threshold may be preset, and functional core sets corresponding to different second trigger signals may correspond to corresponding second end clock numbers.

In one example, the register module 70 may include a second threshold register to receive an externally input second threshold.

In one example, the second end clock number may be a change value that changes according to different subtasks, and is received each time the execution cycle of the subtask under the current task is triggered, or it may be a preset fixed value, which only needs to be received once. Yes, it can be reused later.

By determining the second threshold according to the preset number of second end clocks, pre-control and deployment of the execution cycles of different subtasks can be realized, thereby realizing asynchronous independent operation of different subtasks, and speeding up the operation speed.

In one example, when the conditions for triggering the execution cycle of the next subtask of each current subtask are met, the execution cycle of the next task of each current subtask is triggered, that is, the execution of each next subtask is started, and the next subtask is executed. The execution method of a subtask can be the same as that of the current subtask, and so on, until all subtasks of the current task are executed or a forced end signal is received to end the execution of the subtask.

In one example, the second timing module 60 controls the second timing clock to start timing when the second trigger signal is received, and the second timing clock can determine whether the second threshold is reached every time the number of clocks passes; The trigger signal may correspond to a second timing clock, and different second timing clocks may correspond to different second thresholds. For example, after the function core set corresponding to a second trigger signal receives the second trigger signal, it can start the function corresponding to the second trigger signal. The second timing clock corresponding to the core set is compared with the corresponding second threshold; the execution cycles of each functional core set may be the same or different. The received second trigger signal here includes a second trigger signal generated according to the first trigger signal, and also includes a second trigger signal that is automatically generated when the conditions described below are met. Whenever a new second trigger signal is generated , the corresponding second timing clock can re-time from 0.

By comparing the second timing clock with the second threshold, it is judged whether the conditions for triggering the execution cycle of the next subtask of each current subtask are met, so that the execution cycle of each subtask can be controlled, so that each subtask can be better scheduled. At the same time, since different subtasks can have different execution cycles, asynchronous execution of subtasks can be realized, which further speeds up the execution speed of each subtask and reduces the running time of the current task.

In a possible implementation manner, the control module 40 may also be configured to receive the operation end signal output by each function core corresponding to the second trigger signal, and generate a sub-function when each function core outputs the operation end signal. a task end signal to determine that all functional cores corresponding to the second trigger signal end the execution of the current subtask;

In a possible implementation manner, the apparatus further includes: a first storage module (not shown), electrically connected to the control module, for storing the subtask end signal.

In one example, each functional core of the processor generates an operation end signal after completing its own operation (for example, a primitive operation such as multiplication and addition), and outputs the signal to the control module.

Please refer to FIG. 6a together. FIGS. 6a and 6b are schematic diagrams of a control device according to an embodiment of the present disclosure.

As shown in FIG. 6a and FIG. 6b, the processor may include m functional cores (cores), for example, in an example, the control module is further configured to number each functional core of the processor to uniquely identify each functional core, for example, The functional core of the processor can be set as core[0], core[0]...core[m-2], core[m-1].

In one example, when each function core performs primitive operation, the operation end signal (for example, core_finish[0], corresponding to the function core core[0]) may be low level (0), when the function core core[0] When the execution of the primitive operation is completed, the operation end signal core_finish[0] can be high (1). In this case, the control module can determine the state of the function core (idle state or operation state by detecting the operation end signal). ), when the operation end signal of all function cores in the function core set corresponding to the second trigger signal is high level, the control module generates the subtask end signal to determine that the function cores corresponding to the second trigger signal all end the current execution of subtasks.

In one example, the control module may perform an AND operation on the operation end signals in each functional core to determine the subtask end signal corresponding to the second trigger signal.

In one example, the control module can also be used to allocate functional cores to each task, and the control module can allocate idle functional cores to the tasks according to the computing requirements required by the tasks, for example, the current task corresponding to the first trigger signal can be allocated A plurality of functional cores to obtain a beat sequence group, one or more second trigger signals generated according to the first trigger signal correspond to one or more sub-tasks of the current task, and the control module further assigns them to the current task according to the operation requirements of the sub-tasks The multiple functional cores are further allocated to each subtask to obtain one or more phase timing groups. When there are multiple tasks (network or application), the control module can assign and obtain multiple beat timing groups and multiple phase timing groups. Further, the control module can number each beat timing group and each phase timing group, as shown in Figure 6a, assuming that a beat timing group includes n phase timing groups (phase groups), which are sequentially numbered as phase_grp[ 0]～phase_grp[n-1], correspondingly, when the control module determines that the operation end signals of all functional cores in the phase sequence group corresponding to the subtask are high, the control module generates the subtask end signal phase_grp_finish[0]( Corresponding to the phase sequence group phase_grp[0]) to phase_grp_finish[n-1] (corresponding to the phase sequence group phase_grp[n-1]).

In one example, as shown in FIG. 6a , the register module 70 may further include a function core register (core_en, eg core_en[0,0]), the function core register is configured as a binary register with a size of m*n bits Dimension register, the first dimension indicates the function core number (for example, the first dimension in core_en[0,0] indicates that the function core is the function core core[0], which belongs to the phase timing group phase_grp[0]), the second dimension indicates Subtask numbers included in subtasks, where n and m are both positive integers, and n≤m.

In one example, the first storage module may include a subtask end signal register (phase_grp_finish) to store the subtask end signal, and the subtask end signal register may be configured as n bits corresponding to each phase timing group (one task may include a or multiple subtasks, corresponding to one or more phase sequence groups), when all functional cores in the phase sequence group complete the operation, the subtask end signal corresponding to the phase sequence group can be 1, otherwise it can be 0.

In a possible implementation manner, the control module 40 may also be configured to generate a task end signal when the subtask end signals of all subtasks of the current task are stored in the first storage module, so as to It is determined that all subtasks of the current task corresponding to the first trigger signal all finish execution.

In a possible implementation manner, the apparatus may further include: a second storage module (not shown in FIG. 5 ), electrically connected to the control module, and configured to store the task end signal.

In an example, as shown in FIG. 6b, the control module may number each beat sequence group (step_grp). For example, if there are s tasks, the control module may establish s beat sequence groups (numbered step_grp[0]～step_grp). [s-1]).

In one example, the register module 70 may include a phase group register (eg phase_group_en[0,0]), the phase group register is configured as a two-dimensional register of size s*n bits, the first dimension represents the subtask number ( Or referred to as the phase sequence group number), the current task number (or referred to as the beat sequence group number) included in the second-dimensional current task, where s and n are both positive integers. For example, the first dimension of the phase group register phase_group_en[0,0] represents the phase timing group phase_group[0], and the second dimension represents the beat timing group step_grp[0], that is, the phase timing group phase_group[0] belongs to the beat timing group step_grp[ 0].

In one example, the second storage module may include a task end signal register (step_grp_finish) for storing task end signals of each tick timing group, and the task end signal register may be configured to include s bits, respectively corresponding to s The tick sequence group, for example, the task end signal register step_grp_finish[1] is used to store the task end signal of the tick sequence group step_grp[1].

In one example, the control module can read the subtask end signal in the subtask end signal register phase_grp_finish, and perform a phase AND operation on the subtask end signals of each subtask (phase sequence group) to obtain the current task (beat sequence For example, when all phase timing groups in a beat timing group are finished, that is, the subtask end signals corresponding to all phase timing groups in a beat timing group are all 1, the phase AND operation is performed. If the result is 1, the task end signal of this task can be set to 1, otherwise the task end signal of this task is 0.

Please refer to FIG. 6a and FIG. 6b together. As shown in FIG. 6a and FIG. 6b, each function core can send the operation end signal to the control module (or the control module obtains the operation end signal from each function core). The operation end signal of each functional core is 1. After performing the phase AND operation, the control module obtains the subtask end signal as 1, and the operation task of the phase sequence group is completed. If each subtask of the current task (beat sequence group) ( Phase sequence group) have completed the operation, then the subtask end signal of each subtask is 1, and stored in the subtask end signal register, the control module can obtain the stored value in the subtask end signal, and perform the phase AND operation , it can be obtained that the result of the AND operation is 1, then it can be determined that the current task is completed, and the task end register corresponding to the current task is set to 1, indicating that the current task has completed the operation.

In one example, the register module 70 may further include a first selection register (as shown in FIG. 6b, S_sel[0:m-1][0:y-1]), the first selection register is configured to have a size of A two-dimensional register of m*y bits, the first dimension represents the current function core number, the second dimension represents the task number to which the current function core belongs, where m and y are both positive integers, and y=log ₂ s, the control module The first selection register may be configured such that the corresponding first trigger signal s_ck(0:s-1) is output to the corresponding functional core through the multiplexer.

In an example, as shown in Figure 6b, if the current task completes the operation (the value corresponding to the task end signal register step_grp_finish is 1), and the current task is not the last task, the next tick cycle is triggered to generate all The first trigger signal corresponding to the execution cycle of the next task, each functional core freely selects any one of the first trigger signals as its own first trigger signal according to the configuration of the first selection register S_sel, or the control module selects according to the first trigger signal. The configuration of the register S_sel sends any one of the first trigger signals s_ck(0:s-1) to any one of the functional cores.

In one example, the register module 70 may further include a second selection register (as shown in FIG. 6a, P_sel[0:m-1][0:x-1]), the second selection register is configured to have a size of A two-dimensional register of m*x bits, the first dimension represents the number of the functional core, and the second dimension represents the subtask number described by the current functional core, where x=log ₂ n, the control module can configure the second selection register , so that the corresponding second trigger signal p_ck(0:n-1) is output to the corresponding functional core through the multiplexer.

In an example, as shown in FIG. 6a, if the current subtask completes the operation (the value corresponding to the subtask end signal register phase_grp_finish is 1), and the functional cores corresponding to the second trigger signals all end the current subtasks In the case of the execution of the task, the next phase cycle is triggered, and the second trigger signal corresponding to each next subtask is generated, and each functional core freely selects any second trigger signal as its own according to the configuration of the second selection register P_sel. or, the control module sends any second trigger signal p_ck(0:n-1) to any functional core according to the configuration of the first selection register P_sel.

By setting each functional core to arbitrarily select the first trigger signal and the second trigger signal in the embodiment of the present disclosure, the subsequent processor function can be expanded, and the adaptability and flexibility can be increased.

In a possible implementation manner, the control module can also be used to:

Release the functional core in the processor corresponding to the first trigger signal when a preset condition is met, where the preset condition includes:

The current task is the last task and the execution of the current task ends; or

When forcibly ending the execution of the current task.

For example, if the current task is the last link of a neural network computing task, after the current task finishes executing, the entire neural network computing task is completed, and the first trigger signal corresponding to the set of functional cores in the processor can be released, that is to say These functional core sets can become idle for use by other tasks, and after the execution of the current task is forced to end, since the end execution of the current task is a forced end after a timeout, it can lead to the end execution of the entire neural network computing task. It is also possible to release the first trigger signal corresponding to the set of functional cores in the processor. After the execution of the current task is finished, the corresponding first timing clock and each second timing clock may also be reset and cleared.

By releasing the first trigger signal corresponding to the set of functional cores in the processor after completing the execution of the task, when only a few tasks are executed, the unselected functional cores can be put into a dormant state to reduce power consumption, and at the same time, the functional cores can be released in time It can make the function core in the idle state can be selected by other tasks, improve the operation efficiency, reduce the waiting time of other tasks, and speed up the execution speed.

The control device of the embodiment of the present disclosure can support parallel or mixed operations of multiple asynchronous network applications on-chip: different step triggers can be deployed correspondingly to different network applications, and they operate independently, which can reduce power consumption. When there are only a few network applications During execution, unselected cores are in a dormant state, power consumption is reduced, and running time can be reduced: for a network application, cores with similar computing tasks are divided into a phase timing group to speed up execution.

Various embodiments of the present disclosure have been described above, and the foregoing descriptions are exemplary, not exhaustive, and not limiting of the disclosed embodiments. Numerous modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or improvement over the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (10)

A control device, characterized in that the device comprises: a first trigger module for generating one or more first trigger signals, wherein each first trigger signal corresponds to each task; a second trigger module, electrically connected to the first trigger module, and configured to generate one or more second trigger signals according to the first trigger signal, wherein the second trigger signals correspond to subtasks of the task; a multiplexer, electrically connected to the first trigger module and the second trigger module; A control module, electrically connected to the multiplexing module, for controlling the multiplexer to select any one of the one or more first trigger signals and the one or more first trigger signals Any one of the two trigger signals and the second trigger signal are transmitted to one or more functional cores in the processor, so that the one or more functional cores execute the subtasks of the task according to the received first trigger signal and the second trigger signal . The device of claim 1, wherein: The device further includes a first timing module, which is electrically connected to the first trigger module, the first timing module includes a first timing clock, and the first timing module is used for receiving the first trigger signal. starting the first timing clock to time the execution cycle of the current task; The first triggering module is further configured to determine that the trigger is satisfied when the first timing clock reaches a first threshold, and all subtasks of the current task all finish executing and the current task is not the last task conditions of the execution cycle of the next task, and generate a first trigger signal corresponding to the execution cycle of the next task. The device of claim 2, wherein: The first triggering module is further configured to, when the first timing clock reaches a third threshold, generate a forced end signal, where the forced end signal is used to forcibly end the execution of each current subtask in the current task , so as to force the execution of the current task to end; The control module is further configured to transmit the forced termination signal to each functional core of the current task by using the multiplexer. The device of claim 1, wherein: The device further includes a second timing module, electrically connected to the second trigger module, the second timing module includes one or more second timing clocks, and the second timing module is used for receiving the first timing clock. When the two trigger signals are activated, the one or more second timing clocks are started to time the execution cycle of each subtask of the current task, The second triggering module is further configured to determine that when the second timing clock reaches a second threshold and the functional cores corresponding to the second trigger signals all complete the execution of the current subtasks The conditions for triggering the execution cycle of the next subtask of each current subtask in the current task are triggered, and the second trigger signal corresponding to each next subtask is generated. The device of claim 1, wherein: The control module is also used to receive the operation end signal output by each functional core corresponding to the second trigger signal, and when each function core outputs the operation end signal, generate a subtask end signal to determine whether it is related to the second trigger signal. All the corresponding function cores end the execution of the current subtask; The device also includes: The first storage module, electrically connected to the control module, is used for storing the subtask end signal. The device of claim 5, wherein: The control module is further configured to, in the case that the subtask end signals of all subtasks of the current task are stored in the first storage module, generate a task end signal to determine the current task corresponding to the first trigger signal. All subtasks are executed; The device also includes: A second storage module, electrically connected to the control module, is used for storing the task end signal. The device according to claim 1, wherein the control module is further configured to allocate functional cores to each task and subtasks of each task, number the functional cores in the processor, and The first functional core set is numbered, and the second functional core set corresponding to each subtask of each task is numbered. The device according to claim 1, wherein the device comprises a plurality of phase group registers, a first selection register, a function core register, and a second selection register, wherein, The phase group register is configured as a two-dimensional register with a size of s*n bits, the first dimension represents the current task number, and the second dimension includes the subtask number of the current task, where s and n are both positive integers; The first selection register is configured as a two-dimensional register with a size of m*y bits, the first dimension represents the current functional core number, and the second dimension represents the task number to which the current functional core belongs, wherein m and y are positive. integer, and y=log ₂ s; The function core register is configured as a two-dimensional register with a size of n*m bits, the first dimension represents the subtask number, and the second dimension represents the function core included in the subtask; The second selection register is configured as a two-dimensional register with a size of m*x bits, the first dimension represents the number of the functional core, and the second dimension represents the subtask number described by the current functional core, where x=log ₂ n . The device according to claim 1 or 3, wherein the control module is further configured to: Release the functional core in the processor corresponding to the first trigger signal when a preset condition is met, where the preset condition includes: The current task is the last task and the execution of the current task ends; or When forcibly ending the execution of the current task. A brain-like computing system, characterized in that, the system includes the control device according to any one of claims 1-9.

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