WO2022101901A1

WO2022101901A1 - Current mirror circuit for enhancement mode wide bandgap semiconductor

Info

Publication number: WO2022101901A1
Application number: PCT/IL2021/051325
Authority: WO
Inventors: Joseph B. Bernstein
Original assignee: Ariel Scientific Innovations Ltd
Current assignee: Ariel Scientific Innovations Ltd
Priority date: 2020-11-11
Filing date: 2021-11-09
Publication date: 2022-05-19
Anticipated expiration: 2023-05-11

Abstract

A current mirror comprises a first enhancement mode transistor being a level shifting transistor; a second enhancement mode transistor being a current supply transistor; a gate of the second, current supply, transistor being connected to a first node, the first node being between a first current source resistor and a first side of a second resistor; a gate of the level shifting transistor connected to a second side of the second resistor; the second, current supply, transistor being connected at one terminal to ground via a third resistor and the second and third resistors being of equal magnitude. Alternatively, either of the second or third resistors is reversible.

Description

CURRENT MIRROR CIRCUIT FOR ENHANCEMENT MODE WIDE

BANDGAP SEMICONDUCTOR

RELATED APPLICATION

This application claims the benefit of priority of U.S. Provisional Patent Application No. 63/112,203 filed on 11 November 2020, the contents of which are incorporated herein by reference in their entirety.

FIELD AND BACKGROUND OF THE INVENTION

The present invention, in some embodiments thereof, relates to a current mirror circuit for enhancement mode wide bandgap semiconductors and, more particularly, but not exclusively, to such a circuit implemented with enhancement mode Gallium Nitride (e-GaN) technology.

One important difficulty with implementing analog e-GaN (Enhancement Mode GaN) transistors is the variability of the threshold voltage between transistors, even those manufactured together in a single integrated circuit. Furthermore, even once the devices are made, the threshold voltages can vary by a few tenths of a volt throughout the life of the device. Also, the entire transition from Off to On in an e-GaN transistor is also in the order of tenths of a volt. This makes implementation of a true current mirror, analogous to the well-known MOS current mirror impossible.

However, given that the current mirror circuit is the very basis for most silicon MOS analog circuits, it is very important to implement such a device in GaN transistors in order to make similar Analog circuits in e-GaN, especially in GaN integrated circuits.

US Provisional Patent Application No. 63/039,002, to the present inventors, filed June 15, 2020 and unpublished as of the date of filing of the present application, describes how basic analog comparators may depend on careful voltage control of the gate with a source resistor in order to maintain control of the current through the device. This current can be split to feed into a comparator circuit. Thus there is a workaround for the lack of a current mirror circuit, but no actual current mirror circuit for enhancement mode technology.

SUMMARY OF THE INVENTION

The present embodiments provide a current mirror for an enhancement mode semiconductor technology such as Gallium Nitride (e-GaN).

According to an aspect of some embodiments of the present invention there is provided a current mirror comprising: a first enhancement mode transistor being a level shifting transistor; a second enhancement mode transistor being a current supply transistor; a gate of the second, current supply, transistor being connected to a first node, the first node being between a first current source resistor and a first side of a second resistor; a gate of the level shifting transistor connected to a second side of the second resistor; the second, current supply, transistor being connected at one terminal to ground via a third resistor; the second and third resistors being of equal magnitude or one of the second and third resistors being variable.

In an embodiment, an output of the current mirror is provided by the second, current supply transistor.

The current mirror may be part of a circuit wherein the output is connected to a comparator or a difference amplifier.

In an embodiment, the comparator or the difference amplifier is connected to a ring oscillator.

In an embodiment, the comparator and ring oscillator are connected for use as a pulse width modulator or as a frequency-controlled oscillator.

In an embodiment, the enhancement mode transistors are enhancement mode gallium nitride [e-gan] transistors.

The current mirror, alone or with an associated circuit, may be built into a gallium nitride integrated circuit.

According to a second aspect of the present invention there is provided an integrated circuit built with enhancement mode Gallium Nitride (GaN) components, the integrated circuit comprising a current mirror, the current mirror comprising: a first enhancement mode transistor being a level shifting transistor; a second enhancement mode transistor being a current supply transistor; a gate of the second, current supply, transistor being connected to a first node, the first node being between a first current source resistor and a first side of a second resistor; a gate of the level shifting transistor connected to a second side of the second resistor; the second, current supply, transistor being connected at one terminal to ground via a third resistor; the second and third resistors being of equal magnitude, or one of the second and third resistors being variable. In an embodiment, an output of the current mirror is provided by the second, current supply transistor.

In an embodiment, the output is connected to a comparator or a difference amplifier.

According to a third aspect of the present invention there is provided a current mirror comprising: a first enhancement mode transistor being a level shifting transistor; a second enhancement mode transistor being a current supply transistor; a gate of the second, current supply, transistor being connected to a first node, the first node being between a first current source resistor and a gate and a drain of the first, level shifting, enhancement mode transistor; a source of the level shifting transistor connected to a second resistor; the second, current supply, transistor being connected at one terminal to ground via a third resistor; the second and third resistors being of equal magnitude or one of the second and third resistors being variable.

The enhancement mode transistors discussed herein may be enhancement mode gallium nitride [e-gan] transistors.

Unless otherwise defined, all technical and/or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention pertains. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of embodiments of the invention, exemplary methods and/or materials are described below. In case of conflict, the patent specification, including definitions, will control. In addition, the materials, methods, and examples are illustrative only and are not intended to be necessarily limiting. BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

Some embodiments of the invention are herein described, by way of example only, with reference to the accompanying drawings. With specific reference now to the drawings in detail, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of embodiments of the invention. In this regard, the description taken with the drawings makes apparent to those skilled in the art how embodiments of the invention may be practiced.

In the drawings:

Fig. 1 is a comparator according to a previously filed application of the present inventor;

Fig. 2 is a simplified schematic diagram showing a comparator using a current mirror according to the present embodiments;

Fig. 3 is a graph showing the comparator output using a current mirror according to the present embodiments;

Fig. 4 is a graph showing characteristics of the comparator using a current mirror according to the present embodiments when used as an amplifier;

Fig. 5 is a simplified diagram showing a circuit combining a current mirror according to the present embodiments with a difference amplifier and a ring oscillator to produce either a voltage controlled oscillator or a pulse width modulator; and

Fig. 6 is a simplified diagram showing a part of the circuit of Fig. 5 with a modification of the current mirror according to the present embodiments.

DESCRIPTION OF SPECIFIC EMBODIMENTS OF THE INVENTION

Due to variation in Vt between resistors, a conventional current mirror cannot be made in e-GaN (enhancement mode) HEMT transistors. The present embodiments may provide a compensation circuit.

A current mirror according to the present embodiments comprises an enhancement mode transistor used as a level shifting transistor and a second enhancement mode transistor used as a current supply transistor. The gate of the current supply transistor is connected to a common node or first node, which is in turn connected between a first current source resistor and a first side of a second resistor. The gate of the level shifting transistor is connected to the other side of the second resistor. The second, current supply, transistor is connected at one terminal to ground via a third resistor and the second and third resistors are selected to be of the same or similar magnitude. More particularly, the second and third resistors may be of similar magnitude, or the same magnitude, or one or other of them may be variable, for example to compensate for different gate thresholds at the current supply and level shifting transistors.

The current mirror may be constructed using a Current Source Resistor, R3 feeding into the enhancement mode transistor, TA through a voltage adjusting resistor RA - the second resistor in the above. The current through the current source resistor is:

I(R3) = (Vdd-VtA)/(RA + R3)

The voltage at the common node C (VC) is the voltage division of the source Voltage between the two resistors RA and R3 minus the threshold voltage of the level shifting transistor TA:

VC = VtA + (Vdd - VtA)*(RA/(RA+R3))

Since the current through RB is determined by the Voltage at the common node C (VC) minus the threshold voltage of transistor B (VtB) divided by the source resistor RB, the current through the current supply transistor, TB (IB):

IB = (VC-VtB)/RB

This current may be approximately equal to the current through TA, assuming that Vt is nearly the same. Any difference in Vt will be small compared to the voltage at common node C, allowing flexibility in variation in threshold voltages between TA and TB.

If both resistors, RA and RB are equal and the threshold voltages are approximately equal then the current through both transistors will be equal, making a true compensated current mirror.

The current through the current mirror is fixed and proportional to the supply voltage, Vdd.

This current is chosen such that the swing of both sides of the comparator are between Vdd and the common node voltage, VC.

When the input voltage is small, the output is directly proportional to the input as with a differential amplifier.

When the input voltage is more than about 1/2V above the reference voltage, the inverting voltage goes to about VC while the non-inverting voltage goes to approximately Vdd as seen below. Furthermore, by choosing appropriate ratios of the current mirror resistors, the circuit will be stable through a full range of Vdd from about VC (4V in our example) to as high as the transistors can go, in our example, 100V.

In one aspect the current mirror may drive a voltage controlled oscillator and in another aspect may drive a pulse width modulator. The current mirror may of course be used in any other application where mirroring of a current is required.

For purposes of better understanding some embodiments of the present invention, reference is first made to the construction and operation of the circuit of applicant’s prior application, unpublished on filing of the present application, as illustrated in Figure 1.

Figure 1 illustrates a comparator circuit 10 having a voltage controlled current source 12. The voltage controlled current source consists of a reference voltage (V3) connected to the gate of a small, low current, transistor 14. The example in this figure is the EPC 2038 transistor. Of course, a smaller device may be substituted when the present circuit is integrated into a single chip along with a PWM and even, perhaps, the main power switches, as will be discussed in greater detail below.

The V3 reference voltage 12 is connected to the gate of the current source transistor 14 where the current is controlled by the source resistor (Rcurr) 16. The current through the transistor 14 is fixed by the reference voltage (V3) minus the threshold voltage of the transistor (between 1 and 2.5V) divided by the resistance, Rcurr. This current is then shared between the two upper transistors 18 and 20. When the input voltage (V2) is below the second reference voltage (V4) then the right-hand transistor, 20, is ON and the left-hand transistor, 18, is OFF. Thus, the voltage drop across resistor 22 is the full current from the current source times the resistance, which in the illustrated circuit is 500kOhms). When the voltage at the ON transistor is low, it can go down to below the reference voltage, depending on the control current and drain resistor values.

The same is true when the input voltage goes above the threshold, the current moves to the other transistor 18 and the inverting output goes low while the non-inverting output goes high. Thus, the circuit of Fig. 1 works as a comparator of the input voltage as compared to the second reference voltage (V2) such that the inverting output goes high, to near the Drain voltage (VI) when the transistor is OFF. The opposite happens at the opposite transistor, which goes high when the input voltage is above the V2 reference voltage.

The circuit may be built of discrete components or as an integrated circuit. In either case the circuit may be built with enhancement mode Gallium Nitride (GaN) components, since the use of the present comparator circuit allows for a current source, even though a current mirror (as is common in silicon MOS devices) cannot be built with the current art using GaN components. The comparator circuit compares the input voltage with a reference voltage to provide a controllable constant current source. The comparator compares the input and reference voltages and changes state in accordance with the comparison result with only a small difference related to the threshold voltage difference. In either state the drive transistor, which always has a positive threshold voltage, is either full on or full off and thus acts as a controllable current source. The comparator thus has a first drive transistor having a positive threshold voltage, the drive transistor being switched on and off based on a comparison result of said comparator, and typically is provided with a second drive transistor connected in the opposite configuration, so that when the first drive is off the second drive is on and vice versa. The two drive transistors may provide complementary pull up and pull down drivers.

Before explaining at least one embodiment of the invention in detail, it is to be understood that the invention is not necessarily limited in its application to the details of construction and the arrangement of the components and/or methods set forth in the following description and/or illustrated in the drawings and/or the Examples. The invention is capable of other embodiments or of being practiced or carried out in various ways.

Reference is now made to Fig. 2 which shows a circuit according to embodiments of the present invention. In the present embodiments a comparator circuit 20 makes use of a current mirror 21. The current mirror circuit 21 comprises Current Source Resistor, R3 - 22 - feeding into an enhancement mode transistor, TA 24 through a voltage adjusting resistor RA 26. The current through this resistor, as discussed above, is:

I(R3) = (Vdd-VtA)/(RA + R3)

The voltage at common node C 28 is VC, which is the voltage division of the source Voltage between the two resistors RA 26 and R3 22 minus the threshold voltage of the transistor TA 24:

VC = VtA + (Vdd - VtA)*(RA/(RA+R3)).

Current supply transistor TB 32 of the current mirror circuit has a gate connected to note C 28, and is connected between node D 34 and ground via resistor RB 30. The current through resistor RB 30 is determined by the Voltage at common node C 28 (VC) minus the threshold voltage of transistor B 32, which voltage is denoted VtB, divided by the source resistor RB 30, the current through the current supply transistor, TB (IB):

IB = (VC-VtB)/RB The current IB may be approximately equal to the current through TA, assuming that Vt is nearly the same. Any difference in Vt will be small compared to the voltage at node C, allowing flexibility in variation in threshold voltages between TA and TB.

If both resistors, RA and RB are equal and the threshold voltages are approximately equal then, as explained above, the current through both transistors will be equal, making a true compensated current mirror.

The resistor RA may be varied in comparison to RB to balance out the voltages so that the voltage mirror is perfectly balanced. This can be accomplished by using a potentiometer or other controlled resistive device for one of the resistors so that the threshold voltage variation can be better controlled.

The current through the current mirror is thus fixed and proportional to the supply voltage, Vdd.

The current IB is chosen such that the swings at both sides of the comparator are between Vdd and the common node voltage, VC.

When the input voltage is more than about 1/2V above the reference voltage, the inverting voltage goes to about VC while the non-inverting voltage goes to approximately Vdd as seen below.

Furthermore, by choosing appropriate ratios of the current mirror resistors, the current mirror circuit 21 may be stable through a full range of Vdd from about VC (4V in an example) to as high as the transistors can go, for example, 100V.

Reference is now made to Fig. 3, which shows the characteristic output of the comparator circuit in terms of current v. voltage using the current mirror of the present embodiments. The main supply voltage is shown at 40. The inverting output is shown at 42. The non-inverting output is shown at 44 and the input voltage multiplied by 10 is shown at 46.

Reference is now made to Fig. 4, which is a simplified diagram showing the circuit characteristics when the comparator using the current mirror of the present embodiments is used as an amplifier. The main supply voltage is shown at 50, the difference between the positive and negative outputs is shown at 52 and the input voltage multiplied by 25 is shown at 54.

Reference is now made to Fig. 5, which is a simplified diagram showing a ring oscillator that uses a current mirror according to the present embodiments to provide a pulse width modulator (PWM) or a frequency controlled oscillator, depending on how it is operated, as will be explained below. Arrow 60 points to a current mirror as described above. Arrow 62 indicates a difference amplifier. Arrow 64 indicates a ring oscillator and arrow 66 indicates output logic.

Current mirror 60 comprises current supply transistor 70 and level shifting transistor 72. Variable resistor 74 may be adjusted for the differences in gate thresholds.

Difference amplifier 62 has an input transistor 76 and a reference voltage transistor 78. The reference voltage transistor is on the current path from current supply transistor 70, which means it receives the mirrored current. Difference amplifier 62 gives an output that is negative if the voltage at the input 76 is higher than the voltage at the reference 78 and v.v. Specifically, when the first voltage, 76, is high then the output voltage from the comparator is low. Since these voltages drive the first two stages of the ring oscillator 64 then the charging time is short with the high voltage node but the second gate node is then low, so the second pulse is longer. When one voltage is high and the second is low, then the output will be a varying pulse width from mostly ON to mostly OFF, and the device serves as a pulse width modulator. Similarly, when the comparator voltage output is low and the other side is High, the PWM is reversed. The frequency is fixed primarily by the timing of the three legs of the RO circuit, thus the frequency is mostly constant.

However the device may also be used a frequency-controlled oscillator by changing the input voltage at the difference amplifier. The charging time of each input capacitance is determined by the voltages at the upper gates and the resistance in series with the following gate input. Hence, as the voltage is raised the frequency will increase proportionally to the applied voltage. This gives an independent voltage controlled oscillator (VCO) while the duty cycle is determined by the input voltage compared to the reference voltage.

In either case, the output of the ring oscillator 64 is provided at 80 to the output logic 66 to meet inverters 82 and 84. The two invertors give a positive output and a negative output, and are latched at latch 86 for output driver inverter 88.

Reference is now made to Fig. 6, which is a detail of the circuit of Fig. 5 with a modification 90 of the current mirror circuit. In the modified current mirror circuit 90, the positions of the variable resistor 92 and the level shift transistor are reversed as compared with the positions of variable resistor 74 and level shifting transistor 72 in Fig. 5. The difference amplifier 96 is the same as in the previous figure and is connected at its output as before to ring oscillator 98, partly shown.

It is expected that during the life of a patent maturing from this application many relevant enhancement mode technologies will be developed and the scope of the term “enhancement mode” is intended to include all such new technologies a priori. The terms "comprises", "comprising", "includes", "including", “having” and their conjugates mean "including but not limited to".

The term “consisting of’ means “including and limited to”.

As used herein, the singular form "a", "an" and "the" include plural references unless the context clearly dictates otherwise.

It is appreciated that certain features of the invention, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment and the present description is to be construed as if such embodiments are explicitly set forth herein. Conversely, various features of the invention, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable subcombination or may be suitable as a modification for any other described embodiment of the invention and the present description is to be construed as if such separate embodiments, subcombinations and modified embodiments are explicitly set forth herein. Certain features described in the context of various embodiments are not to be considered essential features of those embodiments, unless the embodiment is inoperative without those elements.

Although the invention has been described in conjunction with specific embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and broad scope of the appended claims.

It is the intent of the applicant(s) that all publications, patents and patent applications referred to in this specification are to be incorporated in their entirety by reference into the specification, as if each individual publication, patent or patent application was specifically and individually noted when referenced that it is to be incorporated herein by reference. In addition, citation or identification of any reference in this application shall not be construed as an admission that such reference is available as prior art to the present invention. To the extent that section headings are used, they should not be construed as necessarily limiting. In addition, any priority document(s) of this application is/are hereby incorporated herein by reference in its/their entirety.

Claims

WHAT IS CLAIMED IS:

1. A current mirror comprising: a first enhancement mode transistor being a level shifting transistor; a second enhancement mode transistor being a current supply transistor; a gate of said second, current supply, transistor being connected to a first node, the first node being between a first current source resistor and a first side of a second resistor; a gate of said level shifting transistor connected to a second side of said second resistor; said second, current supply, transistor being connected at one terminal to ground via a third resistor; said second and third resistors being of equal magnitude or one of said second and third resistors being variable.

2. The current mirror of claim 1, wherein an output of said current mirror is provided by said second, current supply transistor.

3. The current mirror of claim 1 or claim 2, being part of a circuit wherein said output is connected to a comparator or a difference amplifier.

4. The current mirror of claim 3, wherein said comparator or said difference amplifier is connected to a ring oscillator.

5. The current mirror of claim 4, wherein said comparator and ring oscillator are connected for use as a pulse width modulator or as a frequency-controlled oscillator.

6. The current mirror of any one of the preceding claims, wherein said enhancement mode transistors are enhancement mode gallium nitride [e-gan] transistors.

7. The current mirror of claim 6, built into a gallium nitride integrated circuit.

8. An integrated circuit built with enhancement mode Gallium Nitride (GaN) components, the integrated circuit comprising a current mirror, the current mirror comprising: a first enhancement mode transistor being a level shifting transistor; a second enhancement mode transistor being a current supply transistor; a gate of said second, current supply, transistor being connected to a first node, the first node being between a first current source resistor and a first side of a second resistor; a gate of said level shifting transistor connected to a second side of said second resistor; said second, current supply, transistor being connected at one terminal to ground via a third resistor; said second and third resistors being of equal magnitude, or one of said second and third resistors being variable.

9. The integrated circuit of claim 8, wherein an output of said current mirror is provided by said second, current supply transistor.

10. The integrated circuit of claim 8 or claim 9, wherein said output is connected to a comparator or a difference amplifier.

11. The integrated circuit of claim 10, wherein said comparator or said difference amplifier is connected to a ring oscillator.

12. The integrated circuit of claim 11, wherein said comparator and ring oscillator are connected for use as a pulse width modulator or as a frequency-controlled oscillator.

13. The integrated circuit of any one of claims 8 - 12, wherein said enhancement mode transistors are enhancement mode gallium nitride [e-gan] transistors.

14. A current mirror comprising: a first enhancement mode transistor being a level shifting transistor; a second enhancement mode transistor being a current supply transistor; a gate of said second, current supply, transistor being connected to a first node, the first node being between a first current source resistor and a gate and a drain of said first, level shifting, enhancement mode transistor; a source of said level shifting transistor connected to a second resistor; said second, current supply, transistor being connected at one terminal to ground via a third resistor; said second and third resistors being of equal magnitude or one of said second and third resistors being variable.

15. The current mirror of claim 14, wherein an output of said current mirror is provided by said second, current supply transistor.

16. The current mirror of claim 14 or claim 15, being part of a circuit wherein said output is connected to a comparator or a difference amplifier.

17. The current mirror of claim 16, wherein said comparator or said difference amplifier is connected to a ring oscillator.

18. The current mirror of claim 17, wherein said comparator and ring oscillator are connected for use as a pulse width modulator or as a frequency-controlled oscillator.

19. The current mirror of any one of claims 14 - 18, wherein said enhancement mode transistors are enhancement mode gallium nitride [e-gan] transistors.

20. The current mirror of any one of claims 14 - 19, built into a gallium nitride integrated circuit.