WO2022188445A1 - Chip package structure and manufacturing method therefor - Google Patents

Abstract

The present invention provides a chip package structure and a manufacturing method therefor. By arranging an insulating layer and a solder mask which are retracted inwards along a side edge of a chip substrate, a cutting path is exposed out of the insulating layer and the solder mask in an uncut wafer. The solder mask extends to the outer side of the insulating layer, covers the insulating layer and is combined with the substrate, so that the insulating layer can be completely sealed and protected, and thus the erosion of water vapor and the like on the insulating layer is reduced; moreover, part of the stress of the solder mask is directly borne by the substrate, and when no layering occurs between the solder mask and the substrate, the insulating layer is only subjected to a small amount of stress.

Description

Chip package structure and manufacturing method thereof

This application claims the priority of the Chinese patent application whose filing date is March 12, 2021, the application number is 202110270310.5, and the invention name is "chip packaging structure and its manufacturing method", the entire contents of which are incorporated into this application by reference.

technical field

The present invention relates to the technical field of packaging, in particular to a chip packaging structure and a manufacturing method thereof.

Background technique

Based on the material properties of the materials of each layer of the chip packaging structure, such as film formation defects, compactness, thermal expansion coefficient, etc., different stresses will be generated inside and between each layer of the material, and the stress of the material used in the solder mask layer affects the is the largest, especially during the thermal shock of the chip reliability test, the stress changes are even more severe. The silicon material of the chip base and the insulating layer are relatively brittle materials, and delamination is most likely to occur during the stress change process.

In the prior art, an insulating layer and a solder resist layer that completely cover the wafer are usually formed on the surface of the wafer, and then a single chip is obtained by cutting. The chip obtained by this method, on the one hand, due to cutting, there will be unavoidable micro-cracks at the edge, on the other hand, the film layer is disconnected at the edge of the chip, and the stress is not compensated on the other side, so that The edge of the chip substrate is more stressed, so when delamination occurs, the chip substrate or insulating layer tends to start at the edge of the chip and then extend inward.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a chip packaging structure and a manufacturing method thereof.

The present invention provides a chip package structure. The chip includes a base, which has a first surface, a second surface opposite to the first surface, and a plurality of side surfaces connecting the first surface and the second surface. An insulating layer, a metal wiring layer and a solder resist layer are arranged on the surface in sequence, and the solder resist layer is provided with a solder bump that is electrically connected to the metal wiring layer, and is characterized in that:

The edge of the insulating layer and the edge of the solder resist layer are respectively indented along the side surface of the base by a first distance a and a second distance b, wherein 0nm≤b<a;

The insulating layer is located inside the solder resist layer, and the portion of the solder resist layer located outside the insulating layer covers the substrate and covers the sides of the insulating layer.

As a further improvement of the present invention, the side surface of the substrate is provided with grooves recessed inward along the first surface of the substrate, and the grooves are distributed along the length direction of the side surface of the substrate.

As a further improvement of the present invention, the groove forms a stepped structure on the side surface of the base, and has a side wall surface of the groove and a bottom surface of the groove, and the top of the side wall surface of the groove and the side surface of the base on the same side are separated by a third space. Three distances c, where c≤b.

As a further improvement of the present invention, a buffer layer is provided between the insulating layer and the metal wiring layer.

As a further improvement of the present invention, the second surface of the substrate is provided with a soldering pad, the first surface of the substrate is provided with a through hole extending toward the second surface, the soldering pad is exposed at the bottom of the through hole, and the metal The wiring layer extends to the bonding pad along the sidewall of the through hole, and is electrically connected to the bonding pad.

The present invention also provides a method for manufacturing a chip package structure, comprising the steps of:

A wafer is provided, the wafer has a first surface and a second surface opposite to each other, a plurality of chip substrates are arranged in an array on the wafer, and dicing lines are distributed between the adjacent substrates;

An insulating layer is formed on the first surface of the substrate, the insulating layers are formed on each of the substrates at intervals and independently distributed, and the edge of the insulating layer on each of the substrates is indented inward along the cutting track. a distance a;

A metal wiring layer and a solder resist layer are sequentially formed on the insulating layer, and the solder resist layers that are independently distributed at intervals are formed on each of the substrates, and the edge of the solder resist layer on each of the substrates is along the The cutting track is indented inward by a second distance b, wherein 0nm≤b<a, and the part of the solder resist layer located outside the insulating layer covers the substrate and covers the side edges of the insulating layer;

A through hole exposing the metal wiring layer is opened on the solder resist layer, and a solder bump electrically connected to the metal wiring layer is formed in the through hole;

The wafer is cut along the scribe line to obtain multiple independent chip packaging structures.

As a further improvement of the present invention, before "forming an insulating layer on the first surface of the substrate", it also includes the steps:

A full trench is formed on the first surface of the wafer above the scribe line, and the width of the full trench is greater than the width of the scribe line.

As a further improvement of the present invention, the full groove has a groove side wall surface and a groove bottom surface, and the top of the groove side wall surface and the edge of the scribe line on the same side are separated by a third distance c, where c ≤b, the bottom surface of the groove at least completely exposes the scribe line.

As a further improvement of the present invention, before "sequentially forming a metal wiring layer and a solder resist layer on the insulating layer", the steps further include:

A buffer layer is formed on the insulating layer.

As a further improvement of the present invention, before "forming an insulating layer on the first surface of the substrate", it also includes the steps:

A through hole extending toward the second surface of the wafer is formed on the first surface of the wafer, and the bottom of the through hole exposes the bonding pad provided on the second surface of the wafer.

The beneficial effects of the present invention are: by arranging the insulating layer and the solder resist layer indented inward along the side of the chip substrate, in the uncut wafer, the insulating layer and the solder resist layer are exposed to the dicing line. When cutting and separating each chip, the silicon base part of the wafer can be cut directly, avoiding the cutting of the insulating layer and the solder mask layer, so as to avoid the formation of micro-cracks at the edges of the two layers due to cutting; on the other hand, the insulating layer and The solder resist layer forms a complete continuous film layer structure on the surface of the substrate, and there is no situation that stress is generated on one side in the cut film layer and cannot be compensated.

Moreover, the solder mask layer extends to the outside of the insulating layer, which covers the insulating layer and is combined with the substrate. On the one hand, the solder mask layer can completely seal and protect the insulating layer, thereby slowing down the erosion of the insulating layer by water vapor; Part of the stress of the layer can be directly borne by the substrate. When there is no delamination between the solder resist layer and the substrate, the insulating layer is only subjected to a small amount of stress, which further improves the reliability of the chip packaging structure.

Description of drawings

FIG. 1 is a schematic diagram of a chip packaging structure in Embodiment 1 of the present invention.

FIG. 2 is a schematic diagram of the chip package structure before cutting and separation in the first embodiment of the present invention.

FIG. 3 is an enlarged schematic view of A in FIG. 1 .

FIG. 4 is a schematic diagram of a chip packaging structure in Embodiment 2 of the present invention.

FIG. 5 is a schematic diagram of the chip package structure before cutting and separation in the second embodiment of the present invention.

FIG. 6 is an enlarged schematic view of B in FIG. 4 .

FIG. 7 is a schematic diagram of a chip packaging structure in Embodiment 3 of the present invention.

FIG. 8 is a schematic diagram of the chip package structure before cutting and separation in the third embodiment of the present invention.

FIG. 9 is an enlarged schematic view of C in FIG. 7 .

FIG. 10 is an enlarged schematic view of D in FIG. 8 .

FIG. 11 is a schematic diagram of a manufacturing process of a chip package structure in an embodiment of the present invention.

12 to 16 are schematic diagrams of each step of a manufacturing process of a chip package structure in an embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be clearly and completely described below in conjunction with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary, only used to explain the present invention, and should not be construed as a limitation of the present invention.

For the convenience of description, the term used to describe the relative position in space, such as "upper", "lower", "rear", "front", etc., is used to describe one unit or feature shown in the drawings relative to another A unit or feature relationship. The term spatially relative position may include different orientations of the device in use or operation other than the orientation shown in the figures. For example, if the device in the figures is turned over, elements described as "below" or "above" other elements or features would then be oriented "below" or "above" the other elements or features. Thus, the exemplary term "below" can encompass both spatial orientations of below and above.

As shown in FIG. 1 to FIG. 10 , the present invention provides a chip package structure. The chip includes a substrate 1 , which has a first surface 11 , a second surface 12 opposite to the first surface 11 , and a connection between the first surface 11 and the second surface 11 . On the side surface 13 of the surface 12, an insulating layer 2, a metal wiring layer 3 and a solder resist layer 4 are sequentially provided on the first surface 11 of the base 1, and the solder resist layer 4 is provided with a solder bump 6 electrically connected to the metal wiring layer 3. .

The insulating layer 2 is SiO2, Si3N4, etc., which are formed on the surface of the chip substrate 1 by vapor deposition, and at least a metal wiring layer 3 for electrically connecting the chip is formed on the insulating layer 2, and the metal wiring layer 3 is projected on the insulating layer. Within 2, the formation method of the metal wiring layer 3 includes a series of processes of metal deposition, photolithography, copper plating, film removal, and copper/titanium etching. The solder resist layer 4 covers the surface of the chip for insulation and sealing protection.

The chip may be a MEMS chip or an image sensor chip, etc. According to different chip types, the chip may also be provided with structures such as a protective cover plate 5 , and the protective cover plate 5 is attached to the second surface 12 of the substrate 1 .

According to different chip types, in some embodiments, the second surface 12 of the chip substrate 1 is provided with solder pads, the first surface 11 of the substrate 1 is provided with through holes extending toward the second surface 12, and the solder pads are exposed at the bottom of the through holes, and the metal The wiring layer 3 extends to the pad along the sidewall of the through hole, and is electrically connected to the pad.

Further, in some embodiments, a buffer layer 7 may also be provided between the insulating layer 2 and the metal wiring layer to relieve the stress between the insulating layer 2 and the metal wiring layer 3 .

As shown in FIG. 2 , the chip is obtained by cutting and separating the wafer 1 ′. The wafer 1 ′ has opposite first and second surfaces, that is, corresponding to the first surface 11 and the second surface 12 of the chip substrate 1 , the wafer 1 'A plurality of chip substrates 1 are arranged in the upper array, and dicing lanes 8 are distributed between adjacent chip substrates 1. After the encapsulation process and testing are subsequently completed, a single chip is obtained by cutting and separating along the dicing lanes 8. It should be noted that the dicing lane 8 between two adjacent chip substrates 1 is only a blank area reserved between the two chip substrates 1 for cutting, and the dicing lane 8 is between the chip substrates 1 on both sides. Does not have an actual boundary line.

Since a certain loss is inevitable when cutting the wafer 1 ′ by laser or mechanical means, the dicing lane 8 has a certain width d, that is, the width of the kerf when cutting the wafer 1 ′ along the dicing lane 8 .

The edge of the insulating layer 2 and the edge of the solder resist layer 4 are respectively retracted inward along the side surface 13 of the substrate 1 by a first distance a and a second distance b, where 0 nm≦b<a. That is, there is a first distance a between the side of the chip insulating layer 2 and the side 13 of the substrate 1 on the same side, and a second distance b between the side of the solder resist layer 4 and the side 13 of the substrate 1 on the same side.

It should be noted that when the chip is not cut and separated from the wafer 1 ′, the first distance a and the second distance b described here are the distance between the edge of the insulating layer 2 , the edge of the solder mask layer 4 and the edge of the adjacent dicing line 8 . distance between.

In the manufacturing process, the insulating layer 2 and the solder resist layer 4 are formed at intervals on the wafer 1 ′ through a mask plate corresponding to the shape of the insulating layer 2 and the solder resist layer 4 . The insulating layer 2 is located inside the solder resist layer 4 , and the portion of the solder resist layer 4 located outside the insulating layer 2 covers the substrate 1 and covers the sides of the insulating layer 2 .

As shown in FIGS. 1 to 3 , in the first embodiment, the second length b is 0 nm, that is, the side surface of the solder resist layer 4 is flush with the side surface 13 of the substrate 1 . ', the solder resist layers 4 on the adjacent chip substrates 1 are arranged at intervals, and the width of the interval is consistent with the width of the dicing road 8, so that the solder resist layer 4 exposes the dicing road 8. On the one hand, when cutting and separating each chip, it is possible to Directly cut the silicon base part of the wafer 1' to avoid cutting the insulating layer 2 and the solder mask layer 4, so as to avoid the formation of micro-cracks at the edges of the two layers due to cutting; on the other hand, the insulating layer 2 and the solder mask The layer 4 forms a complete continuous film layer structure on the surface of the substrate 1, and there is no situation that stress is generated on one side of the cut film layer and cannot be compensated.

Moreover, since the solder resist layer 4 extends to the outside of the insulating layer 2, it covers the insulating layer 2 and is combined with the substrate 1. On the one hand, the solder resist layer 4 can completely seal and protect the insulating layer 2, thereby slowing down the effect of water vapor on the insulating layer 2. On the other hand, part of the stress of the solder resist layer 4 can be directly borne by the substrate 1. When there is no delamination between the solder resist layer 4 and the substrate 1, the insulating layer 2 will only be subjected to a small amount of stress, which further improves the chip packaging. structural reliability.

In addition, since the second length b is smaller than the first length a, that is, there is a certain distance between the edge of the insulating layer 2 and the solder resist layer 4, so even when delamination occurs between the substrate 1 and the solder resist layer 4, there is a The delamination transition distance makes it difficult for delamination to extend to the interior of the insulating layer 2 .

In other implementations of the first embodiment, when the stress of the solder resist layer 4 is sufficiently low, the insulating layer 2 may be indented only to form spaced insulating layers 2, which are formed on the surface of the wafer 1'. The complete solder resist layer 4, the solder resist layer 4 is cut together with the wafer 1' during the cutting process.

As shown in FIG. 4 to FIG. 6 , in the second embodiment, the difference from the first embodiment is that the second length b is greater than 0 nm, that is, in the uncut and separated wafer 1 ′, the edge of the solder resist layer 4 and the base 1 There is a space between the sides, and by setting the edge of the solder mask 4 away from the edge of the cutting track 8, the stress of the solder mask 4 will not directly act on the side of the substrate 1 and the substrate 1 will be pulled from the side. .

The first length a and the second length b can be specifically adjusted according to the chip size and functional requirements, and are not particularly limited, as long as the second length b is smaller than the first length a.

Further, in some embodiments of the present invention, the side surface 13 of the substrate 1 is provided with grooves 9 recessed inward along the first surface 11 of the substrate 1 , and the grooves 9 are distributed along the length direction of the side surface 13 of the substrate 1 .

As shown in FIGS. 7 to 10 , in the third embodiment, the difference from the second embodiment is that the chip further includes a trench 9 , the trench 9 forms a stepped structure on the side surface 13 of the substrate 1 , and has sidewall surfaces 91 of the trench 9 . There is a third distance c between the bottom surface 92 of the trench 9, the top end of the side wall surface 91 of the trench 9 and the side surface 13 of the substrate 1 on the same side, where c≤b, that is, the side surface of the solder resist layer 4 and the side wall surface 91 of the trench 9 Flush, or the edge of the solder resist layer 4 is indented by a certain distance along the sidewall surface 91 of the trench 9 .

In the uncut and separated wafer 1 ′, a full trench 9 ′ covering the dicing lane 8 is formed above it, and the full trench 9 ′ opens upward. After a single chip is obtained by dicing, the full trench 9 ′ follows the chip. After being cut, a groove 9 is formed on the side surface 13 of the substrate 1 , which is open upwards and sideways at the same time. There is a third distance c between the top of the sidewall surface 91 of the single-sided groove 9 and the edge of the dicing road 8, then the width of the opening of the full groove 9' is d+2c, and the bottom surface 92 of the full groove 9' at least completely exposes the dicing road 8 .

The groove 9 is formed by etching before cutting. By setting the groove 9 with a width larger than the cutting road 8 and having a certain depth above the cutting road 8, the initial position of the cutting is low, and there is a partial margin on both sides, thereby The strength of the single chip substrate 1 at the corners after dicing can be enhanced, so that it can withstand greater stress and further enhance the reliability of the chip.

Before cutting, the longitudinal cross-sectional shape of the groove 9 can be a rectangle or an inverted trapezoid, as long as the cutting line 8 can be exposed.

As shown in FIG. 11 , the present invention also provides a method for manufacturing a chip packaging structure, comprising the steps of:

S1 : As shown in FIG. 12 , a wafer 1 ′ is provided. The wafer 1 ′ has opposite first surfaces 11 and second surfaces 12 , and a plurality of chip substrates 1 are arranged in an array on the wafer 1 ′, adjacent to the chip substrates 1 . There are cutting lanes 8 distributed therebetween, and the width of the cutting lanes 8 is d.

Further, in some embodiments of the present invention, the step of forming trenches 9 is also included.

S11 : A full trench 9 ′ is formed on the first surface 11 of the wafer 1 ′ above the dicing lane 8 , and the width of the full trench 9 ′ is greater than the width of the dicing lane 8 .

Specifically, the full trench 9' is formed by etching. The full trench 9' has the sidewall surface 91 of the trench 9 and the bottom surface 92 of the trench 9, the top of the sidewall surface 91 of the full trench 9' and the edge of the scribe line 8 on the same side. There is a third distance c therebetween, that is, after subsequent cutting, the full trench 9 ′ is cut into trenches 9 located on the side surface 13 of the substrate 1 .

There is a third distance c between the top of the side wall surface 91 of the groove 9 and the side surface 13 of the substrate 1 on the same side of the groove 9, the width of the upper end surface of the groove 9 is d+2c, and the bottom surface 92 of the groove 9 exposes at least the cutting track 8, and the groove 9 The longitudinal cross-sectional shape may be a rectangle, an inverted trapezoid, or the like.

Further, according to different types of chips, after forming the full trench 9', it also includes forming a through hole on the first surface 11 of the wafer 1' extending toward the second surface 12 of the wafer 1', and the bottom of the through hole exposes the first surface of the wafer 1'. 12 solder pads on both sides.

Alternatively, it may also include attaching the protective cover plate 5 on the second surface 12 of the substrate 1 .

S2: As shown in FIG. 13 , an insulating layer 2 is formed on the first surface 11 of the chip substrate 1 , an insulating layer 2 is formed on each substrate 1 with independent intervals, and the edge of the insulating layer 2 on each substrate 1 is along the dicing line 8 The first distance a is indented inward.

Specifically, the insulating layer 2 is formed by vapor deposition technology, and the insulating layer 2 is formed on the substrate 1 through a mask plate corresponding to the planar shape of the insulating layer 2 .

The metal wiring layer 3 is formed by a series of processes of metal deposition, photolithography, copper plating, film removal, and copper/titanium etching. The vertical projection of the metal wiring layer 3 is located in the insulating layer 2 .

Further, in some embodiments of the present invention, after the insulating layer 2 is formed, it also includes forming a buffer layer 7 on the insulating layer 2 .

S3: As shown in FIG. 14, a metal wiring layer 3 and a solder resist layer 4 are formed on the insulating layer 2 in sequence, and a solder resist layer 4 with independent intervals is formed on each substrate 1, and the solder resist layer on each substrate 1 is formed. The edge is indented inward along the scribe line 8 by a second distance b, wherein 0 nm≤c≤b<a, the part of the solder resist layer 4 located outside the insulating layer 2 covers the substrate 1 and covers the side of the insulating layer 2 .

Specifically, the method for forming the solder resist layer 4 includes a sequence of processes such as deposition, photolithography, chemical plating, etc. The solder resist layer 4 is formed on the substrate 1 through a mask corresponding to the planar shape of the solder resist layer 4 .

S4 : As shown in FIG. 15 , a through hole exposing the metal wiring layer 3 is formed on the solder resist layer 4 , and a solder bump 6 electrically connected to the metal wiring layer 3 is formed in the through hole.

S5: As shown in FIG. 16, the wafer 1' is cut along the dicing lane 8 to obtain a plurality of independent chip packaging structures.

It should be understood that although this specification is described in terms of embodiments, not every embodiment only includes an independent technical solution, and this description in the specification is only for the sake of clarity, and those skilled in the art should take the specification as a whole, and each The technical solutions in the embodiments can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

The series of detailed descriptions listed above are only specific descriptions for the feasible embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any equivalent embodiments or changes made without departing from the technical spirit of the present invention All should be included within the protection scope of the present invention.

Claims (10)

A chip packaging structure, the chip includes a substrate, which has a first surface, a second surface opposite to the first surface, and a plurality of side surfaces connecting the first surface and the second surface, which are arranged in sequence on the first surface of the substrate An insulating layer, a metal wiring layer and a solder resist layer are provided, and the solder resist layer is provided with a solder bump that is electrically connected to the metal wiring layer, and is characterized in that: The edge of the insulating layer and the edge of the solder resist layer are respectively indented along the side surface of the base by a first distance a and a second distance b, wherein 0nm≤b<a; The insulating layer is located inside the solder resist layer, and the portion of the solder resist layer located outside the insulating layer covers the substrate and covers the sides of the insulating layer. The chip package structure according to claim 1, wherein the side surface of the base is provided with grooves recessed inward along the first surface of the base, and the grooves are distributed along the length direction of the side surface of the base. The chip package structure according to claim 2, wherein the trench forms a stepped structure on the side surface of the base, and has a sidewall surface of the trench and a bottom surface of the trench, and the top of the sidewall surface of the trench and the same side thereof A third distance c is spaced between the side surfaces of the substrates, wherein c≤b. The chip package structure according to claim 1, wherein a buffer layer is provided between the insulating layer and the metal wiring layer. The chip package structure according to claim 1, wherein the second surface of the base is provided with a bonding pad, the first surface of the base is provided with a through hole extending toward the second surface, and the bottom of the through hole is exposed The bonding pad, the metal wiring layer extends to the bonding pad along the sidewall of the through hole, and is electrically connected to the bonding pad. A method for manufacturing a chip packaging structure, comprising the steps of: A wafer is provided, the wafer has a first surface and a second surface opposite to each other, a plurality of chip substrates are arranged in an array on the wafer, and dicing lines are distributed between the adjacent substrates; An insulating layer is formed on the first surface of the substrate, the insulating layers are formed on each of the substrates at intervals and independently distributed, and the edge of the insulating layer on each of the substrates is indented inward along the cutting track. a distance a; A metal wiring layer and a solder resist layer are sequentially formed on the insulating layer, and the solder resist layers that are independently distributed at intervals are formed on each of the substrates, and the edge of the solder resist layer on each of the substrates is along the The cutting track is indented inward by a second distance b, wherein 0nm≤b<a, and the part of the solder resist layer located outside the insulating layer covers the substrate and covers the side edges of the insulating layer; A through hole exposing the metal wiring layer is opened on the solder resist layer, and a solder bump electrically connected to the metal wiring layer is formed in the through hole; The wafer is cut along the scribe line to obtain multiple independent chip packaging structures. The method for manufacturing a chip package structure according to claim 6, further comprising the steps of: A full trench is formed on the first surface of the wafer above the scribe line, and the width of the full trench is greater than the width of the scribe line. The method for manufacturing a chip package structure according to claim 7, wherein: The full trench has a trench sidewall surface and a trench bottom surface, and a third distance c is spaced between the top of the trench sidewall surface and the edge of the scribe line on the same side of the trench, where c≤b, the trench The bottom surface at least fully exposes the scribe line. The method for manufacturing a chip package structure according to claim 6, characterized in that before "sequentially forming a metal wiring layer and a solder resist layer on the insulating layer", it further comprises the steps of: A buffer layer is formed on the insulating layer. The method for manufacturing a chip package structure according to claim 6, further comprising the steps of: A through hole extending toward the second surface of the wafer is formed on the first surface of the wafer, and the bottom of the through hole exposes the bonding pad provided on the second surface of the wafer.

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