WO2022079890A1 - 秘密シフトシステム、秘密シフト装置、秘密シフト方法、プログラム - Google Patents
秘密シフトシステム、秘密シフト装置、秘密シフト方法、プログラム Download PDFInfo
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- WO2022079890A1 WO2022079890A1 PCT/JP2020/039077 JP2020039077W WO2022079890A1 WO 2022079890 A1 WO2022079890 A1 WO 2022079890A1 JP 2020039077 W JP2020039077 W JP 2020039077W WO 2022079890 A1 WO2022079890 A1 WO 2022079890A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/30—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy
- H04L9/3006—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy underlying computational problems or public-key parameters
- H04L9/3033—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy underlying computational problems or public-key parameters details relating to pseudo-prime or prime number generation, e.g. primality test
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0816—Key establishment, i.e. cryptographic processes or cryptographic protocols whereby a shared secret becomes available to two or more parties, for subsequent use
- H04L9/085—Secret sharing or secret splitting, e.g. threshold schemes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
Definitions
- the present invention relates to a secret calculation technique, and particularly to a technique for performing a bit shift operation in a secret calculation.
- Secret calculation is a method of obtaining the result of a specified operation without restoring the encrypted numerical value (see, for example, Reference Non-Patent Document 1).
- Reference In the method of Non-Patent Document 1 encryption is performed by distributing a plurality of information whose numerical values can be restored to three secret computing devices, and addition / subtraction, constant sum, multiplication, and constant multiplication are performed without restoring the numerical values.
- Logical operation negative, logical product, logical sum, exclusive logical sum
- data format conversion integer, binary number
- W is a predetermined constant of 3 or more
- a protocol that realizes secret calculation by cooperative calculation by W secret computing devices is called a multi-party protocol.
- Non-Patent Document 1 Koji Chida, Hiroki Hamada, Dai Igarashi, Katsumi Takahashi, “Reconsideration of Lightweight Verifiable 3-Party Concealed Function Calculation,” In CSS, 2010.
- Non-Patent Document 2 As documents relating to a protocol and implementation of secret calculation for performing floating-point arithmetic.
- the bit shift operation required to perform a floating-point operation is an operation that shifts the binary bit pattern to the left or right, and is one of the basic operations in computer processing.
- an object of the present invention is to provide a secret calculation technique for performing a bit shift operation at high speed by using a protocol for performing a left shift by inputting a numerical value to be shifted and a shift amount.
- P is a prime number
- p is the number of bits of the prime number P
- Q is the number of the remainder ring
- M is the upper limit of the MSB position of the input numerical value
- M' is the MSB allowed by the share.
- the upper limit of the position, [R, R'] is the range of the right shift amount covered by the divided right shift, and it is composed of three or more secret shift devices
- u be an integer that satisfies u ⁇ M'-M + 1
- One aspect of the present invention is composed of three or more secret shift devices, where P is a prime number, p is the number of bits of the prime number P, and M is the upper limit of the shift amount, and the share of the numerical value a is [[a]] P. From the share of the shift amount ⁇ ⁇ ⁇ >> p (however, 0 ⁇ ⁇ ⁇ M, the value 2 M a obtained by shifting the value a to the left by M bits does not overflow), the value a is ⁇ bits to the right.
- P is a prime number
- p is the number of bits of the prime number P
- Q is the number of the remainder ring
- M is the upper limit of the MSB position of the input numerical value
- three or more secret shift devices It is composed of the share [[a]] P of the numerical value a and the share ⁇ ⁇ >> Q of the shift amount ⁇ (however, if ⁇ ⁇ 0, it represents a left shift, and if ⁇ ⁇ 0, it represents a right shift.
- ⁇ (Caret) represents a superscript.
- x y ⁇ z means that y z is a superscript for x
- x y ⁇ z means that y z is a subscript for x
- _ (underscore) represents a subscript.
- x y_z means that y z is a superscript for x
- x y_z means that y z is a subscript for x.
- [[x]] y represents the mod y element x (k, n)-secretly shared share.
- secret sharing for example, Shamir secret sharing or duplicate secret sharing can be used.
- the mod y element x is represented by (k, n)-replica secret-shared share with ⁇ x >> y . Since (k, n) -replication secret sharing is (k, n) -secret sharing, the protocol applicable to (k, n) -secret sharing is (k, n) -replication secret sharing. Can also be applied.
- the share is expressed as ⁇ x >> y , it means that the property of duplicate secret sharing is used.
- (k, k) -replica secret sharing is called (k, k) -additive secret sharing.
- the mod y element x is represented by (k, k) -additive secret-shared share by ⁇ x> y .
- [[x]] 2 ⁇ m represents a share in which m shares of the format [[x]] 2 are arranged. Note that [[x]] 2 ⁇ m may be regarded as a bit representation of a numerical value.
- X ⁇ y means that x and y are equal as real numbers on the computer. That is, it means that the difference between x and y is within a certain error range.
- a / d represents the value of integer division with the decimal point truncated. Therefore, integer division by a power of 2 is equivalent to a right shift. Also, for two numbers a and d, (a / d) Re represents the value of real division.
- Ceiling (a) represents the smallest integer greater than or equal to a for the number a.
- Floating-point 2 b a (where a and b represent the mantissa and exponent, respectively) is referred to as the floating-point (a, b). Also, m floating point numbers 2 b_0 a 0 , 2 b_1 a 1 ,..., 2 b_m-1 a m-1 (however, a i and bi (0 ⁇ i ⁇ m) have a mantissa and an exponent, respectively.
- ⁇ a (a 0 , a 1 ,..., a m-1 )
- ⁇ b (b 0 , b 1 ,..., b m-1 )
- the length m of the vector ⁇ a (a 0 , a 1 ,..., a m-1 ) may be expressed as
- step2 Party 0 and party 1 share a random number r 01 . Also, party 1 and party 2 share a random number r 12 .
- ⁇ ⁇ >> p 01 represents the share held by party 0 and party 1 with respect to the share ⁇ ⁇ >> p .
- ⁇ a> P 0 represents the share held by party 0 with respect to share ⁇ a> P.
- ⁇ ⁇ >> p 12 represents the share held by parties 1 and 2 with respect to the share ⁇ ⁇ >> p .
- ⁇ a> P 1 represents the share held by party 1 with respect to share ⁇ a> P.
- ⁇ ⁇ >> p 20 represents the share held by party 2 and party 0 with respect to the share ⁇ ⁇ >> p .
- step1 Calculate the share ⁇ ⁇ >> p using the modulus transformation.
- the modulus transformation for example, the modulus transformation using the above-mentioned quotient transfer can be used.
- step3 Calculate ⁇ f L >> p using mod 2 ⁇ mod p conversion.
- step7 Calculate [[f L ]] P using mod 2 ⁇ mod P conversion.
- u is the right shift amount that can be covered by one shift amount concealed right shift (specifically, the amount in the range of 1 to M'-M bits), and d is the right in the range of 1 to M-1 bits.
- the amount of shift required to shift is the number of times the hidden right shift is executed.
- step2 Calculate the share ⁇ ⁇ >> p using the modulus transformation.
- the modulus transformation for example, the modulus transformation using the above-mentioned quotient transfer can be used.
- f d-1 for f L f d- 2 for f d-1 , and so on.
- F 0 , f 1 ,..., f d-1 , f L with such properties are called transitive flags.
- step4 Calculate ⁇ f 1 >> p , ⁇ f 2 >> p ,..., ⁇ f d-1 >> p , ⁇ f L >> p using mod 2 ⁇ mod p conversion ..
- step8 mod 2 ⁇ mod P Use the conversion to calculate [[f 0 ]] P , [[f 1 ]] P ,..., [[f d-1 ]] P , [[f L ]] P ..
- step1 Let u be an integer that satisfies u ⁇ M'-M + 1. Also, let [R, R'] be the range of the right shift amount covered by the divided right shift, and let d be an integer satisfying d ⁇ ceiling (((R'-R + 1) / u) Re ).
- ⁇ L indicates that the calculation of the part enclosed in parentheses can be omitted when it is not necessary to consider the shift amount larger than -R (for example, when it is known that the shift is to the right). Also, ⁇ 0 is not an extremely large value when it is not necessary to consider a shift amount smaller than -R'(for example, the right shift amount is larger than the value to which the shift amount concealed shift (No. 1) can be applied). If you know that), it means that you can omit the calculation of the part enclosed in parentheses.
- step2 Calculate the share ⁇ ⁇ >> p using the modulus transformation.
- the modulus transformation for example, the modulus transformation using the above-mentioned quotient transfer can be used.
- f d-1 for f L f d- 2 for f d-1 , and so on.
- F 0 , f 1 ,..., f d-1 , f L with such properties are called transitive flags.
- step4 Using mod 2 ⁇ mod p conversion, ⁇ f 1 >> p , ⁇ f 2 >> p ,..., ⁇ f d-1 >> p ⁇ , ⁇ f L >> p ⁇ L To calculate.
- step8 Using mod 2 ⁇ mod P conversion, ⁇ [[f 0 ]] P , ⁇ 0 [[f 1 ]] P ,..., [[f d-1 ]] P ⁇ , [[f L ]] Calculate P ⁇ L.
- FIG. 1 is a block diagram showing a configuration of the secret shift system 10.
- the secret shift system 10 includes W secret shift devices 100 1 , ..., 100 W (W is a predetermined integer of 3 or more).
- the secret shift devices 100 1 , ..., 100 W are connected to the network 800 and can communicate with each other.
- the network 800 may be, for example, a communication network such as the Internet or a broadcast communication path.
- FIG. 2 is a block diagram showing the configuration of the secret shift device 100 i (1 ⁇ i ⁇ W).
- FIG. 3 is a flowchart showing the operation of the secret shift system 10.
- the secret shift device 100 i includes a shift amount calculation unit 140 i , a left shift unit 150 i , a right shift unit 160 i , and a recording unit 190 i .
- Each component of the secret shift device 100 i except the recording unit 190 i is required for the operation required for the secret calculation, that is, in order to realize the function of each component among the protocols described in ⁇ Technical Background>. It is configured to perform the required operations.
- a specific functional configuration for realizing individual operations in the present invention for example, a configuration capable of executing the algorithms disclosed in each of Reference Non-Patent Documents 1 to 5 is sufficient, and these are conventional configurations. Since there is, a detailed explanation will be omitted.
- the recording unit 190 i is a component unit that records information necessary for processing of the secret shift device 100 i . For example, the upper limit value M of the shift amount described later is recorded.
- the secret shift system 10 realizes the secret calculation of the shift amount concealed right shift, which is a multi-party protocol. Therefore, the shift amount calculation means 140 (not shown) of the secret shift system 10 is composed of the shift amount calculation unit 140 1 , ..., 140 W , and the left shift means 150 (not shown) is the left shift unit 150 1 . , ..., 150 W , and the right shift means 160 (not shown) is composed of right shift unit 160 1 , ..., 160 W.
- the operation of the secret shift system 10 will be described with reference to FIG.
- the shift amount calculation means 140 calculates the share ⁇ M- ⁇ >> p from the share ⁇ ⁇ >> p and the upper limit value M.
- the left shift means 150 may be configured to execute, for example, a shift amount concealed left shift.
- the right shift means 160 may be configured so as to be able to execute, for example, a shift amount public right shift.
- FIG. 4 is a block diagram showing the configuration of the secret shift system 20.
- the secret shift system 20 includes W secret shift devices 2001, ..., 200 W (W is a predetermined integer of 3 or more).
- the secret shift devices 2001 , ..., 200 W are connected to the network 800 and can communicate with each other.
- the network 800 may be, for example, a communication network such as the Internet or a broadcast communication path.
- FIG. 5 is a block diagram showing the configuration of the secret shift device 200 i (1 ⁇ i ⁇ W).
- FIG. 6 is a flowchart showing the operation of the secret shift system 20.
- the secret shift device 200 i includes a modulus conversion unit 210 i , a first flag calculation unit 220 i , a second flag calculation unit 230 i , a shift amount calculation unit 240 i , and a left shift unit 250. It includes i , a right shift unit 260 i , a third flag calculation unit 270 i , a shift value calculation unit 280 i , and a recording unit 290 i .
- Each component of the secret shift device 200 i except the recording unit 290 i is required for the operation required for the secret calculation, that is, in order to realize the function of each component among the protocols described in ⁇ Technical Background>. It is configured to perform the required operations.
- the recording unit 290 i is a component unit that records information necessary for processing of the secret shift device 200 i . For example, record the upper limit value M of the MSB position of the numerical value to be input later.
- the secret shift system 20 realizes the secret calculation of the shift amount secret shift (No. 1), which is a multi-party protocol, by the cooperative calculation by the W secret shift devices 200 i . Therefore, the modulus conversion means 210 (not shown) of the secret shift system 20 is composed of the modulus conversion units 210 1 , ..., 210 W , and the first flag calculation means 220 (not shown) is the first flag calculation unit. 220 1 , ..., 220 W , the second flag calculation means 230 (not shown) is composed of the second flag calculation unit 230 1 , ..., 230 W , and the shift amount calculation means 240 (not shown).
- Consists of shift amount calculation units 240 1 , ..., 240 W , and the left shift means 250 (not shown) is composed of left shift units 250 1 , ..., 250 W , and the right shift means 260 (shown in the figure). (Not shown) is composed of right shift units 260 1 , ..., 260 W , and the third flag calculation means 270 (not shown) is composed of third flag calculation units 270 1 , ..., 270 W , and is a shift value calculation means.
- 280 (not shown) is composed of a shift value calculation unit 280 1 , ..., 280 W.
- the operation of the secret shift system 20 will be described with reference to FIG.
- the modulus conversion means 210 calculates the share ⁇ ⁇ >> p from the share ⁇ ⁇ >> Q.
- the modulus conversion means 210 may be configured so as to be able to perform the modulus conversion, for example.
- the first flag calculation means 220 calculates, for example, the share ⁇ ( ⁇ ⁇ 0) >> Q from the share ⁇ ⁇ >> Q , and uses the modulus transformation to calculate the share ⁇ ( ⁇ ⁇ 0) >> Q.
- the second flag calculation means 230 calculates the share ⁇ f L >> p from the share [[f L ]] 2 calculated in S220.
- the second flag calculation means 230 may be configured so as to be able to execute, for example, a mod 2 ⁇ mod p conversion.
- the left shift means 250 may be configured to execute, for example, a shift amount concealed left shift.
- the right shift means 260 may be configured so as to be able to execute, for example, a shift amount open right shift.
- the third flag calculation means 270 calculates the share [[f L ]] P from the share [[f L ]] 2 calculated in S220.
- the third flag calculation means 270 may be configured to execute, for example, mod 2 ⁇ mod P conversion.
- the shift value calculation means 280 is shared from the share [[b]] P calculated in S250 and the share [[c]] P calculated in S260 and the share [[f L ]] P calculated in S270.
- [s]] P [[c]] P + ([[b]] P -[[c]] P ) [[f L ]] P is calculated.
- the embodiment of the present invention it is possible to perform a shift operation at high speed while concealing the numerical value to be shifted and the shift amount.
- the amount that can be shifted to the right is limited, it is possible to perform the shift operation at high speed.
- FIG. 7 is a block diagram showing the configuration of the secret shift system 30.
- the secret shift system 30 includes W secret shift devices 300 1 , ..., 300 W (W is a predetermined integer of 3 or more).
- the secret shift devices 300 1 , ..., 300 W are connected to the network 800 and can communicate with each other.
- the network 800 may be, for example, a communication network such as the Internet or a broadcast communication path.
- FIG. 8 is a block diagram showing the configuration of the secret shift device 300 i (1 ⁇ i ⁇ W).
- FIG. 9 is a flowchart showing the operation of the secret shift system 30.
- the secret shift device 300 i includes a modulus conversion unit 310 i , a first flag calculation unit 320 i , a second flag calculation unit 330 i , a shift amount calculation unit 340 i , and a left shift unit 350. It includes i , a right shift unit 360 i , a third flag calculation unit 370 i , a shift value calculation unit 380 i , and a recording unit 390 i .
- Each component of the secret shift device 300 i except the recording unit 390 i is required for the operation required for the secret calculation, that is, in order to realize the function of each component among the protocols described in ⁇ Technical Background>. It is configured to perform the required operations.
- the recording unit 390 i is a component unit that records information necessary for processing of the secret shift device 300 i .
- the upper limit value M hereinafter referred to as the first upper limit value
- the upper limit value M' hereinafter referred to as the second upper limit value
- the secret shift system 30 realizes the secret calculation of the shift amount secret shift (No. 2), which is a multi-party protocol, by the cooperative calculation by the W secret shift devices 300 i . Therefore, the modulus conversion means 310 (not shown) of the secret shift system 30 is composed of the modulus conversion units 310 1 , ..., 310 W , and the first flag calculation means 320 (not shown) is the first flag calculation unit. 320 1 , ..., 320 W , the second flag calculation means 330 (not shown) is composed of the second flag calculation unit 330 1 , ..., 330 W , and the shift amount calculation means 340 (not shown).
- Consists of shift amount calculation units 340 1 , ..., 340 W , and the left shift means 350 (not shown) is composed of left shift units 350 1 , ..., 350 W , and the right shift means 360 (shown in the figure). (Not shown) is composed of right shift units 360 1 , ..., 360 W , and the third flag calculation means 370 (not shown) is composed of third flag calculation units 370 1 , ..., 370 W , and is a shift value calculation means.
- 380 (not shown) is composed of a shift value calculation unit 380 1 , ..., 380 W.
- the operation of the secret shift system 30 will be described with reference to FIG.
- the modulus conversion means 310 calculates the share ⁇ ⁇ >> p from the share ⁇ ⁇ >> Q.
- the modulus conversion means 310 may be configured so as to be able to perform the modulus conversion, for example.
- the first flag calculation means 320 is, for example, from share ⁇ ⁇ >> Q to share ⁇ ( ⁇ ⁇ -M + 1) >> Q , ⁇ ( ⁇ ⁇ -M + 1 + u) >> Q , ... , ⁇ ( ⁇ ⁇ -M + 1 + (d-1) u) >> Q , ⁇ ( ⁇ ⁇ 0) >> Q is calculated and shared using modulus transformation ⁇ ( ⁇ ⁇ -M +) 1) >> Q , ⁇ ( ⁇ ⁇ -M + 1 + u) >> Q ,..., ⁇ ( ⁇ ⁇ -M + 1 + (d-1) u) >> Q , ⁇ ( ⁇ ⁇ ) 0) >> Share from Q ⁇ ( ⁇ ⁇ -M + 1) >> 2 , ⁇ ( ⁇ ⁇ -M + 1 + u) >> 2 ,..., ⁇ ( ⁇ ⁇ -M + 1 +) d-1) u) >> 2 , ⁇ ( ⁇ ⁇ 0) >> 2 is calculated and share ⁇ (
- the share ⁇ ⁇ >> p may be used instead of the share ⁇ ⁇ >> Q.
- the numerical value u and the numerical value d may be calculated by the first flag calculation means 320 from the first upper limit value M and the second upper limit value M', and the numerical value u and the numerical value d may be calculated in advance by the recording unit. It may be recorded in 390 i .
- the second flag calculation means 330 has the share [[f 1 ]] 2 , [[f 2 ]] 2 , ..., [[f d-1 ]] 2 , [[f L ]] calculated in S320. From 2 , calculate the share ⁇ f 1 >> p , ⁇ f 2 >> p ,..., ⁇ f d-1 >> p , ⁇ f L >> p .
- the second flag calculation means 330 may be configured so as to be able to execute, for example, a mod 2 ⁇ mod p conversion.
- the left shift means 350 may be configured so as to be able to execute, for example, a shift amount concealed left shift.
- the right shift means 360 may be configured so as to be able to execute, for example, a batch shift amount public right shift.
- the third flag calculation means 370 has the share [[f 0 ]] 2 , [[f 1 ]] 2 , ..., [[f d-1 ]] 2 , [[f L ]] calculated in S320. From 2 , calculate the share [[f 0 ]] P , [[f 1 ]] P ,..., [[f d-1 ]] P , [[f L ]] P.
- the third flag calculation means 370 may be configured to execute, for example, mod 2 ⁇ mod P conversion.
- the shift value calculation means 380 has a share [[b]] P calculated in S350 and a share [[c 0 ]] P , [[c 1 ]] P ,..., [[c d- ] calculated in S360.
- the embodiment of the present invention it is possible to perform a shift operation at high speed while concealing the numerical value to be shifted and the shift amount. In particular, it is possible to perform a shift operation at high speed without limiting the amount that can be shifted to the right.
- FIG. 7 is a block diagram showing the configuration of the secret shift system 40.
- the secret shift system 40 includes W secret shift devices 400 1 , ..., 400 W (W is a predetermined integer of 3 or more).
- the secret shift devices 400 1 , ..., 400 W are connected to the network 800 and can communicate with each other.
- the network 800 may be, for example, a communication network such as the Internet or a broadcast communication path.
- FIG. 8 is a block diagram showing the configuration of the secret shift device 400 i (1 ⁇ i ⁇ W).
- FIG. 9 is a flowchart showing the operation of the secret shift system 40.
- the secret shift device 400 i includes a modulus conversion unit 410 i , a first flag calculation unit 420 i , a second flag calculation unit 430 i , a shift amount calculation unit 440 i , and a left shift unit 450. It includes i , a right shift unit 460 i , a third flag calculation unit 470 i , a shift value calculation unit 480 i , and a recording unit 490 i .
- Each component of the secret shift device 400 i except the recording unit 490 i is required for the operation required for the secret calculation, that is, in order to realize the function of each component among the protocols described in ⁇ Technical Background>. It is configured to perform the required operations.
- the recording unit 490 i is a component unit that records information necessary for processing of the secret shift device 400 i .
- the upper limit value M hereinafter referred to as the first upper limit value
- M' hereinafter referred to as the second upper limit value
- the secret shift system 40 realizes the secret calculation of the shift amount secret shift (No. 3) which is a multi-party protocol. Therefore, the modulus conversion means 410 (not shown) of the secret shift system 40 is composed of the modulus conversion units 410 1 , ..., 410 W , and the first flag calculation means 420 (not shown) is the first flag calculation unit. 420 1 , ..., 420 W , the second flag calculation means 430 (not shown) is composed of the second flag calculation unit 430 1 , ..., 430 W , and the shift amount calculation means 440 (not shown).
- Consists of shift amount calculation units 440 1 , ..., 440 W , and the left shift means 450 (not shown) is composed of left shift units 450 1 , ..., 450 W , and the right shift means 460 (shown in the figure). (Not shown) is composed of right shift units 460 1 , ..., 460 W , and the third flag calculation means 470 (not shown) is composed of third flag calculation units 470 1 , ..., 470 W , and is a shift value calculation means.
- 480 (not shown) is composed of a shift value calculation unit 480 1 , ..., 480 W.
- the secret shift system 40 will be described with reference to FIG.
- the modulus conversion means 410 calculates the share ⁇ ⁇ >> p from the share ⁇ ⁇ >> Q.
- the modulus conversion means 410 may be configured so as to be able to perform the modulus conversion, for example.
- the first flag calculation means 420 is, for example, from share ⁇ ⁇ >> Q to share ⁇ ( ⁇ ⁇ -R') >> Q , ⁇ ( ⁇ ⁇ -R'+ u) >> Q ,..., ⁇ ( ⁇ ⁇ -R'+ (d-1) u) >> Q , ⁇ ( ⁇ ⁇ -R + 1) >> Calculate Q and share using modulus transformation ⁇ ( ⁇ ⁇ -R' ) >> Q , ⁇ ( ⁇ ⁇ -R'+ u) >> Q ,..., ⁇ ( ⁇ ⁇ -R'+ (d-1) u) >> Q , ⁇ ( ⁇ ⁇ -R +) 1) >> Share from Q ⁇ ( ⁇ ⁇ -R') >> 2 , ⁇ ( ⁇ ⁇ -R'+ u) >> 2 ,..., ⁇ ( ⁇ ⁇ -R'+ (d-1) ) u) >> 2 , ⁇ ( ⁇ ⁇ -R + 1) >> 2 and share ⁇ ( ⁇ ⁇
- the second flag calculation means 430 has the share [[f 1 ]] 2 , [[f 2 ]] 2 , ..., [[f d-1 ]] 2 , [[f L ]] calculated in S420. From 2 , calculate the share ⁇ f 1 >> p , ⁇ f 2 >> p ,..., ⁇ f d-1 >> p , ⁇ f L >> p .
- the second flag calculation means 430 may be configured so as to be able to execute, for example, mod 2 ⁇ mod p conversion.
- the left shift means 450 may be configured to execute, for example, a shift amount concealed left shift.
- the right shift means 460 may be configured so as to be able to execute, for example, a batch shift amount public right shift.
- the third flag calculation means 470 has the share [[f 0 ]] 2 , [[f 1 ]] 2 , ..., [[f d-1 ]] 2 , [[f L ]] calculated in S420. From 2 , calculate the share [[f 0 ]] P , [[f 1 ]] P ,..., [[f d-1 ]] P , [[f L ]] P.
- the third flag calculation means 470 may be configured to execute, for example, mod 2 ⁇ mod P conversion.
- the shift value calculation means 480 has a share [[b]] P calculated in S450 and a share [[c 0 ]] P , [[c 1 ]] P ,..., [[c d- ] calculated in S460.
- Shift amount Concealed shift (No. 3) is when it is not necessary to consider the shift amount larger than -R or when it is not necessary to consider the shift amount smaller than -R', as explained in ⁇ Technical background>. Can omit some calculations. Therefore, if any of these two applies, the secret shift system 40 can be configured to omit some calculations.
- the embodiment of the present invention it is possible to perform a shift operation at high speed while concealing the numerical value to be shifted and the shift amount. In particular, it is possible to perform a shift operation at high speed without limiting the amount that can be shifted to the right.
- FIG. 10 is a diagram showing an example of a functional configuration of a computer that realizes each of the above-mentioned devices.
- the processing in each of the above-mentioned devices can be carried out by having the recording unit 2020 read a program for making the computer function as each of the above-mentioned devices and operating the control unit 2010, the input unit 2030, the output unit 2040, and the like.
- the device of the present invention is, for example, as a single hardware entity, an input unit to which a keyboard or the like can be connected, an output unit to which a liquid crystal display or the like can be connected, and a communication device (for example, a communication cable) capable of communicating outside the hardware entity.
- Communication unit CPU (Central Processing Unit, cache memory, registers, etc.) to which can be connected, RAM and ROM as memory, external storage device as hard hardware, and input, output, and communication units of these.
- CPU, RAM, ROM has a bus connecting so that data can be exchanged between external storage devices.
- a device (drive) or the like capable of reading and writing a recording medium such as a CD-ROM may be provided in the hardware entity.
- a physical entity equipped with such hardware resources there is a general-purpose computer or the like.
- the external storage device of the hardware entity stores a program required to realize the above-mentioned functions and data required for processing of this program (not limited to the external storage device, for example, reading a program). It may be stored in a ROM, which is a dedicated storage device). Further, the data obtained by the processing of these programs is appropriately stored in a RAM, an external storage device, or the like.
- each program stored in the external storage device (or ROM, etc.) and the data required for processing of each program are read into the memory as needed, and are appropriately interpreted and executed and processed by the CPU. ..
- the CPU realizes a predetermined function (each component represented by the above, ... section, ... means, etc.).
- the present invention is not limited to the above-described embodiment, and can be appropriately modified without departing from the spirit of the present invention. Further, the processes described in the above-described embodiment are not only executed in chronological order according to the order described, but may also be executed in parallel or individually depending on the processing capacity of the device that executes the processes or if necessary. ..
- the processing function in the hardware entity (device of the present invention) described in the above embodiment is realized by the computer, the processing content of the function that the hardware entity should have is described by the program. Then, by executing this program on the computer, the processing function in the above hardware entity is realized on the computer.
- the program that describes this processing content can be recorded on a computer-readable recording medium.
- the recording medium that can be read by a computer may be, for example, a magnetic recording device, an optical disk, a photomagnetic recording medium, a semiconductor memory, or the like.
- a hard disk device, a flexible disk, a magnetic tape or the like as a magnetic recording device, and an optical disk such as a DVD (DigitalVersatileDisc), a DVD-RAM (RandomAccessMemory), or a CD-ROM (CompactDiscReadOnly). Memory), CD-R (Recordable) / RW (ReWritable), etc., MO (Magneto-Optical disc), etc. as a magneto-optical recording medium, EEP-ROM (Electronically Erasable and Programmable-Read Only Memory), etc. as a semiconductor memory. Can be used.
- the distribution of this program is carried out, for example, by selling, transferring, renting, etc. a portable recording medium such as a DVD or CD-ROM in which the program is recorded. Further, the program may be stored in the storage device of the server computer, and the program may be distributed by transferring the program from the server computer to another computer via the network.
- a computer that executes such a program first, for example, first stores a program recorded on a portable recording medium or a program transferred from a server computer in its own storage device. Then, when the process is executed, the computer reads the program stored in its own storage device and executes the process according to the read program. Further, as another execution form of this program, a computer may read the program directly from a portable recording medium and execute processing according to the program, and further, the program is transferred from the server computer to this computer. You may execute the process according to the received program one by one each time. In addition, the above processing is executed by a so-called ASP (Application Service Provider) type service that realizes the processing function only by the execution instruction and result acquisition without transferring the program from the server computer to this computer. May be.
- the program in this embodiment includes information used for processing by a computer and equivalent to the program (data that is not a direct command to the computer but has a property that regulates the processing of the computer, etc.).
- the hardware entity is configured by executing a predetermined program on the computer, but at least a part of these processing contents may be realized in terms of hardware.
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Abstract
Description
従来、浮動小数点演算を行う秘密計算のプロトコルや実装に関する文献として、非特許文献1や非特許文献2がある。浮動小数点演算を行うために必要となるビットシフト演算は、2進数のビットパターンを左右にずらす演算であり、コンピュータ処理では基本的な演算の一つである。
本発明の各実施形態における秘密計算は、既存の秘密計算上のプロトコルを用いて構築される。ここでは、まず記法について説明する。
Pを素数とする。例えば、メルセンヌ素数P=261-1とするとよい。pを素数Pのビット数とする。なお、p=|P|と表すこともある。Pがメルセンヌ素数であるとき、pは素数となる。例えば、P=261-1とすると、p=61となる。また、Qを剰余環の位数とする。位数Qは素数Pやそのビット数pとして用いる。また、位数Qは浮動小数点の指数部に用いることができる。位数Qを浮動小数点の指数部に用いる場合、例えば、Q=213-1とすることができる。
まず、本発明で用いる既存の秘密計算プロトコルについて説明する。加減算、定数和、乗算、定数倍、論理演算(否定、論理積、論理和、排他的論理和)、データ形式変換(整数、二進数)、指数関数の計算については、既存のプロトコルを用いる。その他本発明で用いる既存のプロトコルとして以下のものを用いる。
入力:数値xのシェア[[x]]y(数値xのシェア<<x>>y)
出力:数値xのシェア<x>y
具体的には、参考非特許文献2に記載の方法がある。
[(k, k)-加法的秘密分散から(k, n)-秘密分散(複製秘密分散)への変換]
入力:数値xのシェア<x>y
出力:数値xのシェア[[x]]y(数値xのシェア<<x>>y)
具体的には、参考非特許文献2に記載の方法がある。
入力:数値xのシェア[[x]]2(数値xのシェア<<x>>2)
出力:数値xのシェア[[x]]q(数値xのシェア<<x>>q)
具体的には、参考非特許文献2に記載の方法がある。
入力:数値xのシェア[[x]]q、シフト量ρ
出力:数値xをρビット右シフトして得られる数値のシェア[[x/2ρ]]q
具体的には、参考非特許文献3に記載の方法がある。
[一括シフト量公開右シフト]
入力:数値xのシェア[[x]]q、シフト量ρ0, …, ρm-1
出力:数値xをρ0ビット, …, ρm-1ビット右シフトして得られる数値のシェア[[x/2ρ_0]]q, …, [[x/2ρ_m-1]]q
具体的には、参考非特許文献4に記載の方法がある。
なお、自明な方法として、シフト量公開右シフトの繰り返しで、一括シフト量公開右シフトを構成することもできる。
入力:数値xのシェア<<x>>q
出力:数値xのシェア<<x>>r
具体的には、参考非特許文献2に記載の方法がある。
入力:数値xのシェア[[x]]q
パラメータ:入力される数値の最大ビット数M
出力:数値xのシェア[[x]]2^M
具体的には、参考非特許文献2に記載の方法がある。
続いて、本発明の秘密計算プロトコルについて説明する。
入力:数値aのシェア[[a]]P, ローテーション量(シフト量)ρ(≧0)のシェア<<ρ>>p
出力:数値aをρビット左シフトして得られる数値のシェア[[2ρa]]P
出力となるシェアは乗算や指数関数計算のプロトコル等を用いることで計算することもできるが、ランダム置換(参考非特許文献5参照)の考えを用いた方法で計算することもできる。具体例として、n=3の場合について説明する。
(ラウンド1)
step1:シェア[[a]]Pを、パーティ0、パーティ1がシェアを持つ(k, k)-加法的秘密分散<a>Pに変換する。
step5:パーティ0は<c>P 0=2(<<ρ>>^p)_20b1を計算する。
step7:シェア<c>Pを(k, n)-秘密分散のシェア[[c]]Pに変換する。
入力:数値aのシェア[[a]]P, シフト量ρのシェア<<ρ>>p
パラメータ:シフト量の上限値M
ただし、0≦ρ≦M, 数値aをMビット左シフトして得られる数値2Maはオーバーフローしないものとする。
step1:<<M-ρ>>pを計算する.
step2:乗法的ローテーションを用いて、数値aをM-ρビット左シフトして得られる数値のシェア[[2M-ρa]]Pを計算する。
入力:数値aのシェア[[a]]P、シフト量ρのシェア<<ρ>>Q(ただし、ρ≧0の場合は左シフト、ρ<0の場合は右シフトを表すものとする)
パラメータ:入力される数値のMSB(Most Significant Bit)位置のとりうる上限値M
出力:数値aをρビットシフトして得られる数値sのシェア[[s]]P
ここで、s=2ρaが成り立つ。
入力:数値aのシェア[[a]]P、シフト量ρのシェア<<ρ>>Q(ただし、ρ≧0の場合は左シフト、ρ<0の場合は右シフトを表すものとする)
パラメータ:入力される数値のMSB位置のとりうる上限値M、シェアが許容するMSB位置の上限値M’
出力:数値aをρビットシフトして得られる数値sのシェア[[s]]P
ここで、s=2ρaが成り立つ。
入力:数値aのシェア[[a]]P、シフト量ρのシェア<<ρ>>Q(ただし、ρ≧0の場合は左シフト、ρ<0の場合は右シフトを表すものとする)
パラメータ:入力される数値のMSB位置のとりうる上限値M、シェアが許容するMSB位置の上限値M’
出力:数値aをρビットシフトして得られる数値sのシェア[[s]]P
ここで、s=2ρaが成り立つ。
以下、図1~図3を参照して秘密シフトシステム10について説明する。図1は、秘密シフトシステム10の構成を示すブロック図である。秘密シフトシステム10は、W個(Wは3以上の所定の整数)の秘密シフト装置1001、…、100Wを含む。秘密シフト装置1001、…、100Wは、ネットワーク800に接続しており、相互に通信可能である。ネットワーク800は、例えば、インターネットなどの通信網あるいは同報通信路などでよい。図2は、秘密シフト装置100i(1≦i≦W)の構成を示すブロック図である。図3は、秘密シフトシステム10の動作を示すフローチャートである。
以下、図4~図6を参照して秘密シフトシステム20について説明する。図4は、秘密シフトシステム20の構成を示すブロック図である。秘密シフトシステム20は、W個(Wは3以上の所定の整数)の秘密シフト装置2001、…、200Wを含む。秘密シフト装置2001、…、200Wは、ネットワーク800に接続しており、相互に通信可能である。ネットワーク800は、例えば、インターネットなどの通信網あるいは同報通信路などでよい。図5は、秘密シフト装置200i(1≦i≦W)の構成を示すブロック図である。図6は、秘密シフトシステム20の動作を示すフローチャートである。
以下、図7~図9を参照して秘密シフトシステム30について説明する。図7は、秘密シフトシステム30の構成を示すブロック図である。秘密シフトシステム30は、W個(Wは3以上の所定の整数)の秘密シフト装置3001、…、300Wを含む。秘密シフト装置3001、…、300Wは、ネットワーク800に接続しており、相互に通信可能である。ネットワーク800は、例えば、インターネットなどの通信網あるいは同報通信路などでよい。図8は、秘密シフト装置300i(1≦i≦W)の構成を示すブロック図である。図9は、秘密シフトシステム30の動作を示すフローチャートである。
以下、図7~図9を参照して秘密シフトシステム40について説明する。図7は、秘密シフトシステム40の構成を示すブロック図である。秘密シフトシステム40は、W個(Wは3以上の所定の整数)の秘密シフト装置4001、…、400Wを含む。秘密シフト装置4001、…、400Wは、ネットワーク800に接続しており、相互に通信可能である。ネットワーク800は、例えば、インターネットなどの通信網あるいは同報通信路などでよい。図8は、秘密シフト装置400i(1≦i≦W)の構成を示すブロック図である。図9は、秘密シフトシステム40の動作を示すフローチャートである。
シフト量秘匿シフト(その3)は、<技術的背景>で説明した通り、-Rより大きいシフト量を考慮しなくてよい場合や、-R’より小さいシフト量を考慮しなくてよい場合には、一部の計算を省略することができる。そこで、これら2つのいずれかに該当する場合は、秘密シフトシステム40を一部の計算を省略するように構成することができる。
図10は、上述の各装置を実現するコンピュータの機能構成の一例を示す図である。上述の各装置における処理は、記録部2020に、コンピュータを上述の各装置として機能させるためのプログラムを読み込ませ、制御部2010、入力部2030、出力部2040などに動作させることで実施できる。
Claims (6)
- Pを素数、pを素数Pのビット数、Qを剰余環の位数、Mを入力される数値のMSB位置のとりうる上限値、M’をシェアが許容するMSB位置の上限値、[R, R’]を分割した右シフトでカバーする右シフト量の範囲とし、
3個以上の秘密シフト装置で構成され、数値aのシェア[[a]]Pとシフト量ρのシェア<<ρ>>Q(ただし、ρ≧0の場合は左シフト、ρ<0の場合は右シフトを表すものとする)から、数値aをρビットシフトして得られる数値sのシェア[[s]]P(ただし、s=2ρa)を計算する秘密シフトシステムであって、
シェア<<ρ>>Qから、シェア<<ρ>>pを計算するモジュラス変換手段と、
uをu≦M’-M+1を満たす整数、dをd≧ceiling(((R’-R+1)/u)Re)を満たす整数とし、
シェア<<ρ>>Qまたはシェア<<ρ>>pと範囲[R, R’]と数値uと数値dから、シェア[[f0]]2=[[(ρ≧-R’)]]2, [[f1]]2=[[(ρ≧-R’+u)]]2, …, [[fd-1]]2=[[(ρ≧-R’+(d-1)u)]]2, [[fL]]2=[[(ρ≧-R+1)]]2を計算する第1フラグ計算手段と、
シェア[[f1]]2, [[f2]]2, …, [[fd-1]]2, [[fL]]2から、シェア<<f1>>p, <<f2>>p, …, <<fd-1>>p, <<fL>>pを計算する第2フラグ計算手段と、
シェア<<ρ>>pとシェア<<f1>>p, <<f2>>p, …,<<fd-1>>p, <<fL>>pと範囲の上限値R’と数値uと数値dから、シェア<<ρ’>>p=<<ρ>>p+R’-u(Σ1≦i<d<<fi>>p)+((d-1)u-R’)<<fL>>pを計算するシフト量計算手段と、
シェア[[a]]Pとシェア<<ρ’>>pから、シェア[[b]]P=[[2ρ’a]]Pを計算する左シフト手段と、
シェア[[b]]Pと範囲の上限値R’と数値uと数値dから、シェア[[c0]]P=[[2ρ’a/2R’]]P, [[c1]]P=[[2ρ’a/(2R’-u)]]P, …,[[cd-1]]P=[[2ρ’a/(2R’-(d-1)u)]]Pを計算する右シフト手段と、
シェア[[f0]]2, [[f1]]2, …, [[fd-1]]2, [[fL]]2から、シェア[[f0]]P, [[f1]]P, …, [[fd-1]]P, [[fL]]Pを計算する第3フラグ計算手段と、
シェア[[b]]Pとシェア[[c0]]P, [[c1]]P, …, [[cd-1]]Pとシェア[[f0]]P, [[f1]]P, …, [[fd-1]]P, [[fL]]Pから、シェア[[s]]P=[[c0]]P[[f0]]P+([[c1]]P-[[c0]]P)[[f1]]P+…+([[cd-1]]P-[[cd-2]]P)[[fd-1]]P+([[b]]P-[[cd-1]]P)[[fL]]Pを計算するシフト値計算手段と、
を含む秘密シフトシステム。 - Pを素数、pを素数Pのビット数、Qを剰余環の位数、Mを入力される数値のMSB位置のとりうる上限値、M’をシェアが許容するMSB位置の上限値、[R, R’]を分割した右シフトでカバーする右シフト量の範囲とし、
数値aのシェア[[a]]Pとシフト量ρのシェア<<ρ>>Q(ただし、ρ≧0の場合は左シフト、ρ<0の場合は右シフトを表すものとする)から、数値aをρビットシフトして得られる数値sのシェア[[s]]P(ただし、s=2ρa)を計算する、3個以上の秘密シフト装置で構成される秘密シフトシステムの中の秘密シフト装置であって、
シェア<<ρ>>Qから、シェア<<ρ>>pを計算するモジュラス変換部と、
uをu≦M’-M+1を満たす整数、dをd≧ceiling(((R’-R+1)/u)Re)を満たす整数とし、
シェア<<ρ>>Qまたはシェア<<ρ>>pと範囲[R, R’]と数値uと数値dから、シェア[[f0]]2=[[(ρ≧-R’)]]2, [[f1]]2=[[(ρ≧-R’+u)]]2, …, [[fd-1]]2=[[(ρ≧-R’+(d-1)u)]]2, [[fL]]2=[[(ρ≧-R+1)]]2を計算する第1フラグ計算部と、
シェア[[f1]]2, [[f2]]2, …, [[fd-1]]2, [[fL]]2から、シェア<<f1>>p, <<f2>>p, …, <<fd-1>>p, <<fL>>pを計算する第2フラグ計算部と、
シェア<<ρ>>pとシェア<<f1>>p, <<f2>>p, …,<<fd-1>>p, <<fL>>pと範囲の上限値R’と数値uと数値dから、シェア<<ρ’>>p=<<ρ>>p+R’-u(Σ1≦i<d<<fi>>p)+((d-1)u-R’)<<fL>>pを計算するシフト量計算部と、
シェア[[a]]Pとシェア<<ρ’>>pから、シェア[[b]]P=[[2ρ’a]]Pを計算する左シフト部と、
シェア[[b]]Pと範囲の上限値R’と数値uと数値dから、シェア[[c0]]P=[[2ρ’a/2R’]]P, [[c1]]P=[[2ρ’a/(2R’-u)]]P, …,[[cd-1]]P=[[2ρ’a/(2R’-(d-1)u)]]Pを計算する右シフト部と、
シェア[[f0]]2, [[f1]]2, …, [[fd-1]]2, [[fL]]2から、シェア[[f0]]P, [[f1]]P, …, [[fd-1]]P, [[fL]]Pを計算する第3フラグ計算部と、
シェア[[b]]Pとシェア[[c0]]P, [[c1]]P, …, [[cd-1]]Pとシェア[[f0]]P, [[f1]]P, …, [[fd-1]]P, [[fL]]Pから、シェア[[s]]P=[[c0]]P[[f0]]P+([[c1]]P-[[c0]]P)[[f1]]P+…+([[cd-1]]P-[[cd-2]]P)[[fd-1]]P+([[b]]P-[[cd-1]]P)[[fL]]Pを計算するシフト値計算部と、
を含む秘密シフト装置。 - Pを素数、pを素数Pのビット数、Qを剰余環の位数、Mを入力される数値のMSB位置のとりうる上限値、M’をシェアが許容するMSB位置の上限値、[R, R’]を分割した右シフトでカバーする右シフト量の範囲とし、
3個以上の秘密シフト装置で構成される秘密シフトシステムが、数値aのシェア[[a]]Pとシフト量ρのシェア<<ρ>>Q(ただし、ρ≧0の場合は左シフト、ρ<0の場合は右シフトを表すものとする)から、数値aをρビットシフトして得られる数値sのシェア[[s]]P(ただし、s=2ρa)を計算する秘密シフト方法であって、
前記秘密シフトシステムが、シェア<<ρ>>Qから、シェア<<ρ>>pを計算するモジュラス変換ステップと、
uをu≦M’-M+1を満たす整数、dをd≧ceiling(((R’-R+1)/u)Re)を満たす整数とし、
前記秘密シフトシステムが、シェア<<ρ>>Qまたはシェア<<ρ>>pと範囲[R, R’]と数値uと数値dから、シェア[[f0]]2=[[(ρ≧-R’)]]2, [[f1]]2=[[(ρ≧-R’+u)]]2, …, [[fd-1]]2=[[(ρ≧-R’+(d-1)u)]]2, [[fL]]2=[[(ρ≧-R+1)]]2を計算する第1フラグ計算ステップと、
前記秘密シフトシステムが、シェア[[f1]]2, [[f2]]2, …, [[fd-1]]2, [[fL]]2から、シェア<<f1>>p, <<f2>>p, …, <<fd-1>>p, <<fL>>pを計算する第2フラグ計算ステップと、
前記秘密シフトシステムが、シェア<<ρ>>pとシェア<<f1>>p, <<f2>>p, …,<<fd-1>>p, <<fL>>pと範囲の上限値R’と数値uと数値dから、シェア<<ρ’>>p=<<ρ>>p+R’-u(Σ1≦i<d<<fi>>p)+((d-1)u-R’)<<fL>>pを計算するシフト量計算ステップと、
前記秘密シフトシステムが、シェア[[a]]Pとシェア<<ρ’>>pから、シェア[[b]]P=[[2ρ’a]]Pを計算する左シフトステップと、
前記秘密シフトシステムが、シェア[[b]]Pと範囲の上限値R’と数値uと数値dから、シェア[[c0]]P=[[2ρ’a/2R’]]P, [[c1]]P=[[2ρ’a/(2R’-u)]]P, …,[[cd-1]]P=[[2ρ’a/(2R’-(d-1)u)]]Pを計算する右シフトステップと、
前記秘密シフトシステムが、シェア[[f0]]2, [[f1]]2, …, [[fd-1]]2, [[fL]]2から、シェア[[f0]]P, [[f1]]P, …, [[fd-1]]P, [[fL]]Pを計算する第3フラグ計算ステップと、
前記秘密シフトシステムが、シェア[[b]]Pとシェア[[c0]]P, [[c1]]P, …, [[cd-1]]Pとシェア[[f0]]P, [[f1]]P, …, [[fd-1]]P, [[fL]]Pから、シェア[[s]]P=[[c0]]P[[f0]]P+([[c1]]P-[[c0]]P)[[f1]]P+…+([[cd-1]]P-[[cd-2]]P)[[fd-1]]P+([[b]]P-[[cd-1]]P)[[fL]]Pを計算するシフト値計算ステップと、
を含む秘密シフト方法。 - Pを素数、pを素数Pのビット数、Mをシフト量の上限値とし、
3個以上の秘密シフト装置で構成され、数値aのシェア[[a]]Pとシフト量ρのシェア<<ρ>>p(ただし、0≦ρ≦M, 数値aをMビット左シフトして得られる数値2Maはオーバーフローしないものとする)から、数値aをρビット右シフトして得られる数値sのシェア[[s]]P(ただし、s=a/2ρ)を計算する秘密シフトシステムであって、
シェア<<ρ>>pと上限値Mから、シェア<<M-ρ>>pを計算するシフト量計算手段と、
シェア[[a]]Pとシェア<<M-ρ>>pから、シェア[[b]]P=[[2M-ρa]]Pを計算する左シフト手段と、
シェア[[b]]Pと上限値Mから、シェア[[s]]P=[[2M-ρa/2M]]Pを計算する右シフト手段と、
を含む秘密シフトシステム。 - Pを素数、pを素数Pのビット数、Qを剰余環の位数、Mを入力される数値のMSB位置のとりうる上限値とし、
3個以上の秘密シフト装置で構成され、数値aのシェア[[a]]Pとシフト量ρのシェア<<ρ>>Q(ただし、ρ≧0の場合は左シフト、ρ<0の場合は右シフトを表すものとする)から、数値aをρビットシフトして得られる数値sのシェア[[s]]P(ただし、s=2ρa)を計算する秘密シフトシステムであって、
シェア<<ρ>>Qから、シェア<<ρ>>pを計算するモジュラス変換手段と、
シェア<<ρ>>Qまたはシェア<<ρ>>pから、シェア[[fL]]2=[[(ρ≧0)]]2を計算する第1フラグ計算手段と、
シェア[[fL]]2から、シェア<<fL>>pを計算する第2フラグ計算手段と、
シェア<<ρ>>pとシェア<<fL>>pと上限値Mから、シェア<<ρ’>>p=<<ρ>>p+M-M<<fL>>pを計算するシフト量計算手段と、
シェア[[a]]Pとシェア<<ρ’>>pから、シェア[[b]]P=[[2ρ’a]]Pを計算する左シフト手段と、
シェア[[b]]Pと上限値Mから、シェア[[c]]P=[[2ρ’a/2M]]Pを計算する右シフト手段と、
シェア[[fL]]2から、シェア[[fL]]Pを計算する第3フラグ計算手段と、
シェア[[b]]Pとシェア[[c]]Pとシェア[[fL]]Pから、シェア[[s]]P=[[c]]P+([[b]]P-[[c]]P)[[fL]]Pを計算するシフト値計算手段と、
を含む秘密シフトシステム。 - 請求項2に記載の秘密シフト装置としてコンピュータを機能させるためのプログラム。
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| PCT/JP2020/039077 WO2022079890A1 (ja) | 2020-10-16 | 2020-10-16 | 秘密シフトシステム、秘密シフト装置、秘密シフト方法、プログラム |
| JP2022556802A JP7485067B2 (ja) | 2020-10-16 | 2020-10-16 | 秘密シフトシステム、秘密シフト装置、秘密シフト方法、プログラム |
| EP20957719.6A EP4210028B1 (en) | 2020-10-16 | 2020-10-16 | Secure shift system, secure shift apparatus, secure shift method, and program |
| CN202080106084.0A CN116324934B (zh) | 2020-10-16 | 2020-10-16 | 秘密移位系统、秘密移位装置、秘密移位方法、记录介质 |
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