WO2022067455A1

WO2022067455A1 - Solid state imaging device

Info

Publication number: WO2022067455A1
Application number: PCT/CN2020/118617
Authority: WO
Inventors: Takahashi Seiji
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-09-29
Filing date: 2020-09-29
Publication date: 2022-04-07
Anticipated expiration: 2023-03-29
Also published as: CN116158088B; CN116158088A

Abstract

A solid state imaging device in which a plurality of unit pixels are arranged in the form of a matrix along row and column directions is provided. Each unit pixel comprises: a plurality of light sensing areas for a plurality of colors; and a signal readout circuit area. Each light sensing area includes: an on-chip lens; a color filter; one or more photodiodes; one or more transfer transistors; and a part of floating diffusion. The signal readout circuit area includes a plurality of in-pixel transistors. In each unit pixel, the floating diffusion and the in-pixel transistors are shared by a plurality of photodiodes and transfer transistors. Elements in each unit pixel are symmetrically arranged with respect to a center line of each unit pixel.

Description

SOLID STATE IMAGING DEVICE

TECHNICAL FIELD

The present application relates to a solid state imaging device.

BACKGROUND

A CMOS (Complementary Metal Oxide Semiconductor) image sensor may be used as a solid state imaging device which converts light information into an electric signal. In a pixel of the CMOS image sensor, a plurality of photodiodes share a single signal readout circuit in order to shrink size of the pixel. At the same time, it is a requirement not to degrade performance of the pixel.

As an arrangement of color filters for the pixel, a Bayer arrangement is often used. In the Bayer arrangement, one unit pixel comprises two green sensors, one blue sensor, and one red sensor. It is required for sensitivity of the two green sensors to be the same. However, if incident light is reflected at an area of the signal readout circuit, this reflected light may enter the sensors. If the amount of the entering light is different between the two green sensors, the level of signals outputted from the two green sensors becomes different. This difference induces a maze-like fixed pattern noise in an outputted image.

SUMMARY

According to a first aspect of the present application, a solid state imaging device in which a plurality of unit pixels are arranged in the form of a matrix along row and column directions is provided. Each unit pixel comprises: a plurality of light sensing areas for a plurality of colors; and a signal readout circuit area. Each light sensing area includes: an on-chip lens; a color filter; one or more photodiodes; one or more transfer transistors; and a part of floating diffusion. The signal readout circuit area includes a plurality of in-pixel transistors. In each unit pixel, the floating diffusion and the in-pixel transistors are shared by a plurality of photodiodes and transfer transistors. Elements in each unit pixel are symmetrically arranged with respect to a center line of each unit pixel.

According to a second aspect of the present application, the plurality of in-pixel transistors comprise a reset transistor, a source follower transistor, and a row-select transistor. The reset transistor and the row-select transistor are the same size, and are symmetrically arranged with respect to the center line. The source follower transistor is arranged on the center line, and has a symmetrical shape with respect to the center line.

According to a third aspect of the present application, the plurality of in-pixel transistors comprise a reset transistor, dual conversion gain transistors, source follower transistors, and a row-select transistor. The reset transistor and the row-select transistor are the same size, and are symmetrically arranged with respect to the center line. The dual conversion gain transistors and the source follower transistors are the same size, and are symmetrically arranged with respect to the center line.

According to the present application, elements in one unit pixel are symmetrically arranged with respect to a center line of the unit pixel. Therefore, an imbalance of the amount of light reflected at an area of a signal readout circuit is not created, and thereby an imbalance of level of signals outputted from photodiodes is not created. Thus, a maze-like fixed pattern noise in an outputted image is suppressed.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 shows a Bayer arrangement of color filters.

FIG. 2 shows a layout of elements in one unit pixel of a solid state imaging device according to a first embodiment of the present application.

FIG. 3 shows a layout of elements in one unit pixel of a solid state imaging device according to a second embodiment of the present application.

FIG. 4 shows a circuit in one unit pixel of a solid state imaging device according to the second embodiment of the present application.

FIG. 5 shows a layout of elements in one unit pixel of a solid state imaging device according to a third embodiment of the present application.

FIG. 6 shows a layout of elements in one unit pixel of a solid state imaging device according to a fourth embodiment of the present application.

FIG. 7 shows a layout of elements in one unit pixel of a solid state imaging device according to a fifth embodiment of the present application.

FIG. 8 shows a layout of elements in one unit pixel of a solid state imaging device according to a sixth embodiment of the present application.

FIG. 9 shows a layout of elements in one unit pixel of a solid state imaging device according to a seventh embodiment of the present application.

FIG. 10 shows a layout of elements in one unit pixel of a solid state imaging device according to an eighth embodiment of the present application.

FIG. 11 shows a layout of elements in one unit pixel of a solid state imaging device according to a ninth embodiment of the present application.

FIG. 12 shows an exemplary imaging equipment in which a solid state imaging device according to the present application is used.

FIG. 13 shows application fields in which a solid state imaging device according to the present application is used.

DESCRIPTION OF EMBODIMENTS

FIG. 1 shows a Bayer arrangement of color filters. In the Bayer arrangement, three color filters including green, blue, and red filters are arranged in the form of a matrix along row and column directions. One unit pixel comprises a set of four filters including two green filters (Gb and Gr filters) , one blue filter (B filter) , and one red filter (R filter) . A Gb filter is a green filter next to a B filter, and a Gr filter is a green filter next to an R filter, in a row direction.

FIG. 2 shows a layout of elements in one unit pixel of a solid state imaging device according to a first embodiment of the present application. One unit pixel comprises four light sensing areas including Gb, B, R, and Gr sensing areas, and one signal readout circuit area. Each light sensing area includes an on-chip lens OCL, a color filter (Gb, B, R, or Gr filter) , two photodiodes, two transfer transistors, and a part of floating diffusion. The signal readout circuit area includes three in-pixel transistors TR1, TR2, and TR3, and two pixel well contacts PW. However, the number of elements included in the signal readout circuit area is not limited to the aforementioned number.

Photodiodes PD1 and PD2 are covered with a Gb filter and an on-chip lens OCL. Photodiodes PD3 and PD4 are covered with an R filter and an on-chip lens OCL. Photodiodes PD5 and PD6 are covered with a B filter and an on-chip lens OCL. Photodiodes PD7 and PD8 are covered with a Gr filter and an on-chip lens OCL.

Eight photodiodes PD1 to PD8 are connected to eight transfer transistors TX1 to TX8, respectively. The eight transfer transistors TX1 to TX8 are connected to floating diffusion FD.

The signal readout circuit area is arranged on a boundary of the unit pixel under the R sensing area and the Gr sensing area. The pixel well contacts PW are arranged at the lower left and right corners of the boundary.

The floating diffusion FD and signal readout circuit are shared by eight photodiodes PD1 to PD8 and transfer transistors TX1 to TX8.

Elements in the unit pixel are symmetrically arranged with respect to a center line YY’ of the unit pixel. The in-pixel transistors TR1 and TR3 are the same size, and are symmetrically arranged with respect to the center line YY’. The in-pixel transistor TR2 is arranged on the center line YY’, and has a symmetrical shape with respect to the center line YY’.

Due to these arrangements, an imbalance of the amount of light reflected at an area of the signal readout circuit is not created, and thereby an imbalance of level of signals outputted from Gb and Gr sensing areas is not created. Thus, a maze-like fixed pattern noise in an outputted image is suppressed.

FIG. 3 shows a layout of elements in one unit pixel of a solid state imaging device according to a second embodiment of the present application. In the second embodiment, the signal readout circuit area includes a reset transistor RST, a source follower transistor SF, and a row-select transistor SEL as the three in-pixel transistors.

The floating diffusion FD, the reset transistor RST, the source follower transistor SF, and the row-select transistor SEL are shared by eight photodiodes PD1 to PD8 and transfer transistors TX1 to TX8.

Elements in the unit pixel are symmetrically arranged with respect to a center line YY’ of the unit pixel. The reset transistor RST and the row-select transistor SEL are the same size, and are symmetrically arranged with respect to the center line YY’. The source follower transistor SF is arranged on the center line YY’, has a symmetrical shape with respect to the center line YY’, and is larger than the reset transistor RST and the row-select transistor SEL. The remainder of the constitution is the same as the first embodiment.

FIG. 4 shows a circuit in one unit pixel of a solid state imaging device according to the second embodiment of the present application. The reset transistor RST is turned on in response to a reset signal, and resets charge accumulated in the floating diffusion FD. The photodiodes PD1 to PD8 generate charge corresponding to the amount of incident light by photoelectric conversion, and accumulate the generated charge. One of the transfer transistors TX1 to TX8 is turned on in response to a transfer signal, and transfers charge accumulated in one of the photodiodes PD1 to PD8 to the floating diffusion FD. Voltage of the floating diffusion FD is determined by the transferred charge. This voltage is applied to a gate of the source follower transistor SF. The source follower transistor SF sends a pixel signal corresponding to the voltage of the floating diffusion FD to the row-select transistor SEL. The row-select transistor SEL is connected to a vertical signal line VSL, and sends the pixel signal to the vertical signal line VSL in response to a row-select signal.

FIG. 5 shows a layout of elements in one unit pixel of a solid state imaging device according to a third embodiment of the present application. In the third embodiment, a channel direction of the reset transistor RST and the row-select transistor SEL forms an angle of 90 degrees with respect to a channel direction of the source follower transistor SF. A source of the source follower transistor SF and a drain of the row-select transistor SEL are independent active areas, respectively, and are connected by metal wiring. Thereby, resistance of this node is lowered, and signal linearity and RC delay are improved. The remainder of the constitution is the same as the second embodiment.

FIG. 6 shows a layout of elements in one unit pixel of a solid state imaging device according to a fourth embodiment of the present application. In the fourth embodiment, the source follower transistor SF is divided into four sub transistors. These four sub transistors are connected to each other in parallel. Multiple source follower transistors improve pixel noise and pixel reset noise. Two sub transistors and the remaining two sub transistors are symmetrically arranged with respect to the center line YY’. The remainder of the constitution is the same as the third embodiment.

FIG. 7 shows a layout of elements in one unit pixel of a solid state imaging device according to a fifth embodiment of the present application. In the fifth embodiment, gates of the two sub transistors at the same side with respect to the center line YY’ are combined. The remainder of the constitution is the same as the fourth embodiment.

FIG. 8 shows a layout of elements in one unit pixel of a solid state imaging device according to a sixth embodiment of the present application. In the sixth embodiment, two dual conversion gain transistors DCG and the two sub transistors (source follower transistors) are the same size, and are symmetrically arranged with respect to the center line YY’. A symmetrical layout with the dual conversion gain transistors DCG enhances a dynamic range. The remainder of the constitution is the same as the fifth embodiment.

FIG. 9 shows a layout of elements in one unit pixel of a solid state imaging device according to a seventh embodiment of the present application. In the seventh embodiment, a part of a channel of the reset transistor RST is overlapped with a part of the photodiode PD3, a part of a channel of the dual conversion gain transistor DCG is overlapped with a part of the photodiode PD4, a part of a channel of the sub transistor (source follower transistor) is overlapped with a part of the photodiode PD7, and a part of a channel of the row-select transistor SEL is overlapped with a part of the photodiode PD8. These arrangements increase volume of the photodiodes and thereby increase saturation capacitance. Therefore, a dynamic range is enhanced and S/N in bright light is improved. The remainder of the constitution is the same as the sixth embodiment.

FIG. 10 shows a layout of elements in one unit pixel of a solid state imaging device according to an eighth embodiment of the present application. In the eighth embodiment, one photodiode is covered with one color filter and one on-chip lens. Therefore, one unit pixel comprises four photodiodes PD1 to PD4, which are connected to four transfer transistors TX1 to TX4, respectively. The remainder of the constitution is the same as the seventh embodiment.

FIG. 11 shows a layout of elements in one unit pixel of a solid state imaging device according to a ninth embodiment of the present application. In the ninth embodiment, the row-select transistor SEL is arranged on a boundary of the unit pixel on the left side of the Gb sensing area, and on a row-directional center line of the Gb sensing area. The reset transistor RST is arranged on a boundary of the unit pixel on the left side of the R sensing area, and on a row-directional center line of the R sensing area. The dual conversion gain transistors DCG are arranged on a column-directional center line of the R sensing area. The sub transistors (source follower transistors) are arranged on a column-directional center line of the Gr sensing area. The remainder of the constitution is the same as the eighth embodiment.

In other embodiments, one unit pixel may comprise a number of photodiodes which differs from the number in the aforementioned embodiments. For example, comprising two photodiodes along a row direction multiplied by four photodiodes along a column direction is possible. Similarly, 4x4, 8x2, and 2x8 are possible.

The present application can be applied to array devices. For the devices, various substrates such as a bulk silicon substrate, a silicon-on-insulator substrate, a silicon-germanium substrate, and other photosensitive substrates can be used.

FIG. 12 shows an exemplary imaging equipment in which a solid state imaging device according to the present application is used. The imaging equipment comprises a lens 1, a shutter 2, a solid state imaging device 3, a signal processing circuit 4, and a monitor 5. The lens 1 forms an image of an object on the solid state imaging device 3. The shutter 2 controls incident light to the solid state imaging device 3. The solid state imaging device 3 outputs a pixel signal corresponding to the incident light. The signal processing circuit 4 performs various signal processing to the pixel signal. The monitor 5 displays the image of the object corresponding to the processed pixel signal.

In the imaging equipment using the solid state imaging device 3 according to the present application, the monitor 5 can display the image in which a maze-like fixed pattern noise is suppressed.

FIG. 13 shows application fields in which a solid state imaging device according to the present application is used. The solid state imaging device according to the present application can be used in various application fields such as a mobile phone camera, a digital camera, a network camera, a security and surveillance camera, a video camera, an automotive and transport camera, a medical camera, and machine vision.

Claims

A solid state imaging device in which a plurality of unit pixels are arranged in the form of a matrix along row and column directions,

each unit pixel comprises: a plurality of light sensing areas for a plurality of colors; and a signal readout circuit area,

each light sensing area includes: an on-chip lens; a color filter; one or more photodiodes; one or more transfer transistors; and a part of floating diffusion,

the signal readout circuit area includes a plurality of in-pixel transistors,

in each unit pixel, the floating diffusion and the in-pixel transistors are shared by a plurality of photodiodes and transfer transistors, and

elements in each unit pixel are symmetrically arranged with respect to a center line of each unit pixel.
The solid state imaging device according to claim 1, the plurality of light sensing areas in each unit pixel comprise two green sensing areas, one blue sensing area, and one red sensing area in a Bayer arrangement.
The solid state imaging device according to claim 2, the plurality of in-pixel transistors comprise a reset transistor, a source follower transistor, and a row-select transistor,

the reset transistor and the row-select transistor are the same size, and are symmetrically arranged with respect to the center line, and

the source follower transistor is arranged on the center line, and has a symmetrical shape with respect to the center line.
The solid state imaging device according to claim 3, a channel direction of the reset transistor and the row-select transistor forms an angle of 90 degrees with respect to a channel direction of the source follower transistor.
The solid state imaging device according to claim 4, the source follower transistor is divided into a plurality of sub transistors.
The solid state imaging device according to claim 5, gates of the sub transistors at the same side with respect to the center line are combined.
The solid state imaging device according to claim 2, the plurality of in-pixel transistors comprise a reset transistor, dual conversion gain transistors, source follower transistors, and a row-select transistor,

the reset transistor and the row-select transistor are the same size, and are symmetrically arranged with respect to the center line, and

the dual conversion gain transistors and the source follower transistors are the same size, and are symmetrically arranged with respect to the center line.
The solid state imaging device according to claim 7, the reset transistor and the row-select transistor are arranged along the column direction, and the dual conversion gain transistors and the source follower transistors are arranged along the row direction.
The solid state imaging device according to claim 1, a part of the in-pixel transistors is overlapped with a part of the photodiodes.