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WO2021227725A1 - 驱动电路、驱动方法、显示面板及显示装置 - Google Patents

驱动电路、驱动方法、显示面板及显示装置 Download PDF

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Publication number
WO2021227725A1
WO2021227725A1 PCT/CN2021/086093 CN2021086093W WO2021227725A1 WO 2021227725 A1 WO2021227725 A1 WO 2021227725A1 CN 2021086093 W CN2021086093 W CN 2021086093W WO 2021227725 A1 WO2021227725 A1 WO 2021227725A1
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Prior art keywords
transistor
electrically connected
terminal
driving
electrode
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PCT/CN2021/086093
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English (en)
French (fr)
Inventor
董甜
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to US17/626,460 priority Critical patent/US11830433B2/en
Publication of WO2021227725A1 publication Critical patent/WO2021227725A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a driving circuit, a driving method, a display panel, and a display device.
  • OLED displays are one of the hot spots in the field of flat panel display research. Compared with liquid crystal displays (LCD), OLED displays have low energy consumption, low production costs, self-luminous, wide Advantages such as viewing angle and fast response speed.
  • the driving circuit used to control the light emission of the light-emitting device is the core technical content of the OLED display and has important research significance.
  • the voltage of the gate of the driving transistor is unstable, which in turn leads to unstable light emission and causes the problem of uneven brightness.
  • a driving transistor a first electrode of the driving transistor is electrically connected to a first power terminal, and a second electrode of the driving transistor is electrically connected to a device to be driven;
  • a first control circuit a first terminal of the first control circuit is electrically connected to a data detection terminal, a control terminal of the first control circuit is electrically connected to a control signal terminal; and the first control circuit is configured to respond to The signal of the first control signal terminal connects the data detection terminal with the second terminal of the first control circuit;
  • a stabilizing capacitor, the first pole of the stabilizing capacitor is electrically connected to the second terminal of the first control circuit, and the second pole of the stabilizing capacitor is electrically connected to the first power terminal;
  • the second control circuit the first end of the second control circuit is electrically connected to the first electrode of the stabilizing capacitor, and the second end of the second control circuit is electrically connected to the gate of the driving transistor, so The control terminal of the second control circuit is electrically connected to the control signal terminal; and the second control circuit is configured to connect the first pole of the stabilizing capacitor to the control signal terminal in response to the signal of the second control signal terminal.
  • the gate of the driving transistor is turned on.
  • control signal terminal includes: a scan signal terminal
  • the first control circuit includes a first transistor; wherein, the first electrode of the first transistor is electrically connected to the data detection terminal, the gate of the first transistor is electrically connected to the scan signal terminal, and the The second pole of the first transistor is electrically connected to the first pole of the stabilizing capacitor;
  • the second control circuit includes a second transistor; wherein, the first pole of the second transistor is electrically connected to the first pole of the stabilizing capacitor, and the gate of the second transistor is electrically connected to the scan signal terminal. Connected, the second electrode of the second transistor is electrically connected to the gate of the driving transistor.
  • control signal terminal further includes: a detection signal terminal;
  • the first control circuit further includes a third transistor; wherein, the first electrode of the third transistor is electrically connected to the data detection terminal, the gate of the third transistor is electrically connected to the detection signal terminal, so The second pole of the third transistor is electrically connected to the first pole of the stabilizing capacitor;
  • the second control circuit further includes a fourth transistor; wherein, the first pole of the fourth transistor is electrically connected to the first pole of the stabilizing capacitor, and the gate of the fourth transistor is connected to the detection signal terminal.
  • the second electrode of the fourth transistor is electrically connected to the gate of the driving transistor.
  • control signal terminal includes: a detection signal terminal
  • the driving circuit further includes:
  • a fifth transistor the gate of the fifth transistor is electrically connected to the detection signal terminal, and the first electrode of the fifth transistor is electrically connected to the gate of the driving transistor;
  • a sixth transistor The gate of the sixth transistor is electrically connected to the detection signal terminal, the first electrode of the sixth transistor is electrically connected to the second electrode of the fifth transistor, and the first electrode of the sixth transistor is electrically connected to the second electrode of the fifth transistor.
  • the two poles are electrically connected with the second pole of the driving transistor.
  • the driving circuit further includes:
  • a storage capacitor the first electrode of the storage capacitor is electrically connected to the gate of the driving transistor, and the second electrode of the storage capacitor is electrically connected to the first power terminal.
  • a plurality of sub-pixels are located on the base substrate, and at least one of the plurality of sub-pixels includes a light-emitting device and the above-mentioned driving circuit; wherein, the second electrode of the driving transistor in the driving circuit and the light-emitting The first electrode of the device is electrically connected;
  • a plurality of control signal lines are located on the base substrate, and the control signal terminal of the driving circuit in a row of sub-pixels is electrically connected to at least one of the control signal lines;
  • a plurality of data detection lines are located on the base substrate, and the data detection end of the driving circuit in a column of sub-pixels is electrically connected to at least one of the data detection lines.
  • the multiple control signal lines include: scanning signal lines; and the scanning signal terminals of the driving circuits in a row of sub-pixels are electrically connected to one of the scanning signal lines.
  • the multiple control signal lines further include: a detection signal line; the detection signal terminal of the driving circuit in a row of sub-pixels is electrically connected to one of the detection signal lines.
  • the display panel further includes:
  • a plurality of seventh transistors one of the data detection lines corresponds to one of the seventh transistors; wherein, the gates of the plurality of seventh transistors are electrically connected to the reset signal line, and the plurality of seventh transistors
  • the first poles are all electrically connected to the initialization signal line, and the second poles of each of the seventh transistors are electrically connected to the corresponding data detection lines.
  • the display panel further includes:
  • a first power line, the first power line is electrically connected to the first power terminal of the drive circuit
  • a second power line, the second power line is electrically connected to the second electrode of the light-emitting device
  • the power management circuit includes: a first power generation circuit, a second power generation circuit, an eighth transistor, and a ninth transistor; wherein the first power generation circuit is configured to generate a first power source that is loaded to the first power source. Voltage, the second power generation circuit is configured to generate a second voltage applied to the second power terminal;
  • the output terminal of the first power generation circuit is electrically connected to the first power line
  • the gate of the eighth transistor is electrically connected to the first selection signal terminal, the first electrode of the eighth transistor is electrically connected to the output terminal of the first power generation circuit, and the second electrode of the eighth transistor is electrically connected to The second power cord is electrically connected;
  • the gate of the ninth transistor is electrically connected to the second selection signal terminal, the first electrode of the ninth transistor is electrically connected to the output terminal of the second power generation circuit, and the second electrode of the ninth transistor is electrically connected to The second power cord is electrically connected.
  • the display device provided by the embodiment of the present disclosure includes the above-mentioned display panel.
  • the driving method includes: a display phase and a detection phase;
  • the display stage includes a data writing stage and a light emitting stage
  • the first control circuit responds to the signal of the first control signal terminal to conduct the data detection terminal with the second terminal of the first control circuit;
  • a second control circuit responds to the signal of the second control signal terminal to conduct the first pole of the stabilizing capacitor and the gate of the driving transistor;
  • the driving transistor In the light-emitting phase, the driving transistor generates a driving current, and provides the driving current to the device to be driven to drive the device to be driven to emit light;
  • the detection phase includes a reset phase, a charging phase, and a sampling phase;
  • an initialization signal is loaded to the data detection terminal to reset the data detection terminal;
  • the first control circuit responds to the signal of the first control signal terminal to reset the data detection terminal Conducted with the second terminal of the first control circuit, the second control circuit responds to the signal of the second control signal terminal to conduct the first terminal of the stabilizing capacitor and the gate of the driving transistor To reset the driving transistor;
  • the data detection terminal is floating, and the first control circuit conducts the data detection terminal with the second terminal of the first control circuit in response to the signal of the first control signal terminal
  • the second control circuit responds to the signal at the second control signal terminal to turn on the first pole of the stabilizing capacitor and the gate of the driving transistor; the fifth transistor and the sixth transistor are turned on to Charging the data detection terminal;
  • the charged voltage of the data detection terminal is collected.
  • FIG. 1 is a schematic diagram of the structure of some driving circuits in the embodiments of the disclosure.
  • Figure 2a is a timing diagram of some signals in an embodiment of the disclosure.
  • FIG. 2b is a timing diagram of still other signals in the embodiments of the disclosure.
  • FIG. 3 is a schematic diagram of the structure of still other driving circuits in the embodiments of the disclosure.
  • FIG. 4 is a timing diagram of other signals in the embodiments of the disclosure.
  • FIG. 5 is a flowchart of some driving methods of the driving circuit in the embodiments of the disclosure.
  • FIG. 6 is a flowchart of still other driving methods of the driving circuit in the embodiments of the disclosure.
  • FIG. 7 is a schematic diagram of the structure of some display panels in the embodiments of the disclosure.
  • FIG. 8 is a schematic diagram of specific structures of some display panels in the embodiments of the disclosure.
  • FIG. 9a is a timing diagram of some signals of the display panel in an embodiment of the disclosure.
  • FIG. 9b is a timing diagram of some signals of the display panel in an embodiment of the disclosure.
  • Some driving circuits provided by the embodiments of the present disclosure, as shown in FIG. 1, may include:
  • the driving transistor M0, the first electrode of the driving transistor M0 is electrically connected to the first power supply terminal ELVDD, and the second electrode of the driving transistor M0 is electrically connected to the device L to be driven;
  • the first terminal of the first control circuit 1 is electrically connected to the data detection terminal SD, and the control terminal of the first control circuit 1 is electrically connected to the control signal terminal CS; and the first control circuit 1 is configured to respond to The signal of the first control signal terminal CS connects the data detection terminal SD with the second terminal of the first control circuit 1;
  • the voltage stabilizing capacitor CLC, the first pole of the voltage stabilizing capacitor CLC is electrically connected to the second end of the first control circuit 1;
  • the second control circuit 2 The first end of the second control circuit 2 is electrically connected to the second electrode of the voltage stabilizing capacitor CLC, the second end of the second control circuit 2 is electrically connected to the gate of the driving transistor M0, and the second control circuit The control terminal of 2 is electrically connected to the control signal terminal CS; and the second control circuit 2 is configured to conduct the second electrode of the stabilizing capacitor CLC and the gate of the driving transistor M0 in response to the signal of the second control signal terminal CS .
  • the first control circuit is configured to conduct the data detection terminal with the second terminal of the first control circuit in response to the signal of the first control signal terminal; the second control circuit is configured to respond The signal at the second control signal terminal connects the first pole of the stabilizing capacitor to the gate of the driving transistor.
  • the charge storage effect of the voltage stabilizing capacitor can be used, so that the leakage current of the transistor is stored in the stabilizing capacitor, thereby reducing the gap between the first pole of the stabilizing capacitor and the data detection terminal. Voltage difference, thereby reducing leakage current.
  • the voltage of the first electrode of the voltage stabilizing capacitor and the voltage of the gate of the driving transistor can be approximately the same during the light-emitting phase, so that the voltage difference between the first electrode of the voltage stabilizing capacitor and the gate of the driving transistor can be approximately If the value is zero, the influence of the leakage current on the voltage of the gate of the driving transistor can be further reduced, and the voltage stability of the gate of the driving transistor can be further improved.
  • the control signal terminal CS includes: a scan signal terminal GA; wherein, the first control circuit 1 includes a first transistor M1; wherein, the first transistor M1 One electrode is electrically connected to the data detection terminal SD, the gate of the first transistor M1 is electrically connected to the scanning signal terminal GA, and the second electrode of the first transistor M1 is electrically connected to the first electrode of the voltage stabilizing capacitor CLC.
  • the second control circuit 2 includes a second transistor M2; wherein, the first pole of the second transistor M2 is electrically connected to the first pole of the voltage stabilizing capacitor CLC, and the gate of the second transistor M2 is electrically connected to the scan signal terminal GA, The second electrode of the second transistor M2 is electrically connected to the gate of the driving transistor M0.
  • the control signal terminal CS may further include: a detection signal terminal SA.
  • the driving circuit further includes: a fifth transistor M5 and a sixth transistor M6.
  • the gate of the fifth transistor M5 is electrically connected to the detection signal terminal SA
  • the first electrode of the fifth transistor M5 is electrically connected to the gate of the driving transistor M0.
  • the gate of the sixth transistor M6 is electrically connected to the detection signal terminal SA
  • the first electrode of the sixth transistor M6 is electrically connected to the second electrode of the fifth transistor M5
  • the second electrode of the sixth transistor M6 is electrically connected to the second electrode of the driving transistor M0.
  • the driving circuit may further include a storage capacitor CST.
  • the first electrode of the storage capacitor CST is electrically connected to the gate of the driving transistor M0, and the second electrode of the storage capacitor CST is electrically connected to the first power terminal ELVDD.
  • the driving transistor M0M0 can be a P-type transistor; wherein, the first electrode of the driving transistor M0M0 has its source, the second electrode of the driving transistor M0M0 has its drain, and the driving transistor M0M0 is in In the saturation state, a driving signal transmitted from the source of the driving transistor M0M0 to its drain can be generated.
  • the driving transistor M0 can also be an N-type transistor; wherein the first electrode of the driving transistor M0 has its drain, the second electrode of the driving transistor M0 has its source, and when the driving transistor M0 is in a saturated state, it can be driven by The drain of the transistor M0 transmits a driving signal to its source.
  • the device to be driven may be a light-emitting device, and the driving signal may be used as a driving current for driving the light-emitting device to emit light.
  • the device to be driven can also be set to other devices, which is not limited here.
  • the device to be driven is a light-emitting device as an example.
  • the first electrode of the light emitting device is electrically connected to the second electrode of the driving transistor M0M0, and the second electrode of the light emitting device is electrically connected to the second power terminal ELVSSELVSS.
  • the first electrode of the light-emitting device is its positive electrode
  • the second electrode is its negative electrode.
  • the light-emitting device is generally an electroluminescent diode.
  • the light-emitting device may include: Micro Light Emitting Diode (Micro LED), Organic Light Emitting Diode (OLED), and Quantum Dot Light Emitting Diode ( At least one of Quantum Dot Light Emitting Diodes, QLED).
  • a general light-emitting device has a light-emitting threshold voltage, and emits light when the voltage across the light-emitting device is greater than or equal to the light-emitting threshold voltage.
  • the specific structure of the light emitting device can be designed and determined according to the actual application environment, which is not limited here.
  • all transistors may be P-type transistors.
  • all transistors can also be N-type transistors, which can also be designed and determined according to the actual application environment, which is not limited here.
  • the P-type transistor is turned off under the action of a high-level signal, and turned on under the action of a low-level signal.
  • the N-type transistor is turned on under the action of a high-level signal, and cut off under the action of a low-level signal.
  • the transistor mentioned in the above embodiments of the present disclosure may be a thin film transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS), which is not limited here.
  • TFT thin film transistor
  • MOS metal oxide semiconductor field effect transistor
  • the first electrode of the transistor can be used as its source and the second electrode as its drain; or, conversely, the first electrode of the transistor can be used as its drain.
  • the second pole is used as its source, which can be designed and determined according to the actual application environment, and no specific distinction is made here.
  • the voltage Vdd of the first power terminal ELVDD is generally positive, and the voltage Vss of the second power terminal ELVSS is generally grounded or negative.
  • the specific values of the voltage Vdd of the first power terminal ELVDD and the voltage Vss of the second power terminal ELVSS can be designed and determined according to the actual application environment, and are not limited here.
  • the working process of the above-mentioned driving circuit may include: a display phase T10 and a detection phase T20.
  • the display phase T10 may include a data writing phase T11 and a light emitting phase T12.
  • the detection signal terminal SA is always a high-level signal.
  • the detection signal terminal SA is a high-level signal
  • the fifth transistor M5 and the sixth transistor M6 are both turned off.
  • the scan signal terminal GA is a low-level signal
  • both the first transistor M1 and the second transistor M2 can be controlled to be turned on.
  • the data signal of the data detection terminal SD can be input to the gate of the driving transistor M0, so that the gate voltage of the driving transistor M0 is the voltage Vdata of the data signal, which is stored by the storage capacitor CST.
  • the voltage of the first pole of the voltage stabilizing capacitor CLC is also the voltage Vdata of the data signal.
  • the voltage difference between the first electrode of the voltage stabilizing capacitor CLC and the gate of the driving transistor M0 can be substantially zero, so there is no voltage drop, so that the influence of the leakage current on the voltage of the gate of the driving transistor M0 can be reduced. Furthermore, the stability of the voltage of the gate of the driving transistor M0 can be improved.
  • both the fifth transistor M5 and the sixth transistor M6 are turned off. Since the scan signal terminal GA is a high-level signal, both the first transistor M1 and the second transistor M2 can be controlled to be turned off.
  • the driving transistor M0 handles the saturation state, thereby generating a driving current Id that drives the light emitting device L to emit light, and, Wherein, Vdd is the voltage of the first power supply terminal ELVDD, and Vth is the threshold voltage of the driving transistor M0. Thus, the light emitting device L is driven to emit light.
  • the detection phase T20 may include a reset phase T21, a charging phase T22, and a sampling phase T23.
  • the detection signal terminal SA is a high-level signal
  • the fifth transistor M5 and the sixth transistor M6 are both turned off.
  • the scan signal terminal GA is a low-level signal
  • both the first transistor M1 and the second transistor M2 can be controlled to be turned on.
  • the reset signal of the data detection terminal SD can be input to the gate of the driving transistor M0, so that the gate voltage of the driving transistor M0 is the voltage Vinit of the reset signal, thereby resetting the gate of the driving transistor M0.
  • the data detection terminal SD is floating. Since the detection signal terminal SA is a low-level signal, the fifth transistor M5 and the sixth transistor M6 are both turned on. Since the scan signal terminal GA is a low-level signal, both the first transistor M1 and the second transistor M2 can be controlled to be turned on. In this way, the voltage of the first power supply terminal ELVDD can charge the data detection terminal SD through the first transistor M1, the second transistor M2, the fifth transistor M5, and the sixth transistor M6. And the charging ends when the data detection terminal SD is charged to Vdd+Vth. It should be noted that the charging time needs several hundred microseconds to several milliseconds. Of course, the charging time can be set according to the requirements of the actual application, and it is not limited here.
  • the detection signal terminal SA is a low-level signal
  • the fifth transistor M5 and the sixth transistor M6 are both turned on.
  • the scan signal terminal GA is a low-level signal
  • both the first transistor M1 and the second transistor M2 can be controlled to be turned on.
  • the voltage of the data detection terminal SD is collected and processed according to the collected voltage of the data detection terminal SD to realize the threshold voltage compensation of the driving transistor M0.
  • the embodiments of the present disclosure further provide some array substrates, the schematic structural diagrams of which are shown in FIG. 3, which are modified for the implementation in the above-mentioned embodiments.
  • FIG. 3 which are modified for the implementation in the above-mentioned embodiments.
  • the control signal terminal CS may further include: a detection signal terminal SA.
  • the first control circuit 1 further includes a third transistor M3; wherein the first pole of the third transistor M3 is electrically connected to the data detection terminal SD, the gate of the third transistor M3 is electrically connected to the detection signal terminal SA, and the third transistor M3 is electrically connected to the detection signal terminal SA.
  • the second pole of M3 is electrically connected to the first pole of the voltage stabilizing capacitor CLC.
  • the second control circuit 2 also includes a fourth transistor M4; wherein the first pole of the fourth transistor M4 is electrically connected to the first pole of the voltage stabilizing capacitor CLC, the gate of the fourth transistor M4 is electrically connected to the detection signal terminal SA, The second electrode of the four-transistor M4 is electrically connected to the gate of the driving transistor M0.
  • the display phase T10 may include a data writing phase T11 and a light emitting phase T12.
  • the detection signal terminal SA is always a high-level signal
  • the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are all turned off.
  • the working process of the driving circuit shown in FIG. 3 in the display phase T10 may be basically the same as the working process of the driving circuit shown in FIG. 1 in the display phase T10, and details are not described here.
  • the detection phase T20 may include a reset phase T21, a charging phase T22, and a sampling phase T23.
  • the scanning signal terminal GA is always a high-level signal, and the first transistor M1 and the second transistor M2 are both turned off.
  • the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are all turned on.
  • the reset signal of the data detection terminal SD can be input to the gate of the driving transistor M0, so that the gate voltage of the driving transistor M0 is the voltage Vinit of the reset signal, thereby resetting the gate of the driving transistor M0.
  • the data detection terminal SD is floating. Since the detection signal terminal SA is a low-level signal, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are all turned on. In this way, the voltage of the first power supply terminal ELVDD can charge the data detection terminal SD through the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6. And the charging ends when the data detection terminal SD is charged to Vdd+Vth. It should be noted that the charging time needs several hundred microseconds to several milliseconds. Of course, the charging time can be set according to the requirements of the actual application, and it is not limited here.
  • the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are all turned on.
  • the voltage of the data detection terminal SD is collected and processed according to the collected voltage of the data detection terminal SD to realize the threshold voltage compensation of the driving transistor M0.
  • the driving method may include: a display phase T10 and a detection phase T20; wherein, the display phase T10 includes a data writing phase and a light emitting phase.
  • the detection phase T20 includes a reset phase, a charging phase, and a sampling phase.
  • the driving method of the driving circuit provided by the embodiment of the present disclosure may include the following steps:
  • the first control circuit responds to the signal of the first control signal terminal to conduct the data detection terminal and the second terminal of the first control circuit; the second control circuit responds to the signal of the second control signal terminal, Connect the first pole of the voltage stabilizing capacitor to the gate of the driving transistor.
  • the driving transistor In the light-emitting stage, the driving transistor generates a driving current, and provides the driving current to the device to be driven to drive the device to be driven to emit light.
  • the driving method of the driving circuit provided by the embodiment of the present disclosure may include the following steps:
  • S610 In the reset phase, load an initialization signal to the data detection terminal to reset the data detection terminal; the first control circuit responds to the signal of the first control signal terminal to conduct the data detection terminal with the second terminal of the first control circuit, In response to the signal of the second control signal terminal, the second control circuit turns on the first electrode of the voltage stabilizing capacitor and the gate of the driving transistor to reset the driving transistor;
  • the data detection terminal is floating, and the first control circuit responds to the signal of the first control signal terminal to conduct the data detection terminal with the second terminal of the first control circuit; the second control circuit responds to the second control
  • the signal at the signal terminal turns on the first pole of the voltage stabilizing capacitor and the gate of the driving transistor; the fifth transistor and the sixth transistor are turned on to charge the data detection terminal;
  • embodiments of the present disclosure also provide some display panels, as shown in FIG. 7, which may include a base substrate 100.
  • at least one of the plurality of sub-pixels may include a light emitting device and a driving circuit; wherein the second electrode of the driving transistor M0 in the driving circuit is electrically connected to the first electrode of the light emitting device.
  • the structure and working principle of the driving circuit can be referred to the above-mentioned embodiments, which will not be repeated here.
  • the structure of the driving circuit shown in FIG. 3 is taken as an example for description.
  • each sub-pixel may include: a light-emitting device and a driving circuit.
  • the display panel may further include: a plurality of control signal lines CSL and a plurality of data detection lines SDL on the base substrate 100.
  • the control signal terminal CS of the driving circuit in a row of sub-pixels is electrically connected to at least one control signal line CSL
  • the data detection terminal SD of the driving circuit in a column of sub-pixels is electrically connected to at least one data detection line SDL.
  • the data detection terminal SD of the driving circuit in a column of sub-pixels is electrically connected to a data detection line SDL correspondingly.
  • control signal terminal CS may include the scan signal terminal GA, and the specific implementation can refer to the embodiments shown in FIG. 1 and FIG. 3.
  • the multiple control signal lines CSL may include: scan signal lines GAL.
  • the scan signal terminal GA of the driving circuit in a row of sub-pixels is electrically connected to a scan signal line GAL correspondingly. That is, the gates of the first transistor M1 and the second transistor M2 of the driving circuit in a row of sub-pixels are electrically connected to a corresponding one of the scanning signal lines GAL.
  • control signal terminal CS may further include a detection signal terminal SA, and the specific implementation can refer to the embodiments shown in FIG. 1 and FIG. 3.
  • the multiple control signal lines CSL may further include: a detection signal line SAL; the detection signal terminal SA of the driving circuit in a row of sub-pixels and one detection signal line SAL corresponds to electrical connection. That is, the gates of the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 of the driving circuit in a row of sub-pixels may all be electrically connected to a corresponding detection signal line SAL.
  • the display panel may further include: a reset signal line RE, an initialization signal line INIT, and a plurality of seventh transistors M7.
  • one data detection line SDL corresponds to a seventh transistor M7.
  • the gates of the seventh transistors M7 are electrically connected to the reset signal line RE
  • the first electrodes of the seventh transistors M7 are electrically connected to the initialization signal line INIT
  • the second electrodes of the seventh transistors M7 are electrically connected to the reset signal line RE.
  • the corresponding data detection line SDL is electrically connected.
  • the reset signal line RE, the initialization signal line INIT, and the plurality of seventh transistors M7 may be provided in the non-display area BB. Of course, in actual applications, it can be designed according to actual application requirements, which is not limited here.
  • the display panel may further include: a first power line VDDL, a second power line VSSL, and a power management circuit 200.
  • the first power line VDDL is electrically connected to the first power terminal ELVDD of the driving circuit
  • the second power line VSSL is electrically connected to the second electrode of the light emitting device L.
  • the power management circuit 200 may include: a first power generation circuit 210, a second power generation circuit 220, an eighth transistor M8, and a ninth transistor M8; wherein, the first power generation circuit 210 is configured to generate power to the first power terminal The second power generation circuit 220 is configured to generate the second voltage applied to the second power supply terminal ELVSS;
  • the output terminal of the first power generation circuit 210 is electrically connected to the first power line VDDL;
  • the gate of the eighth transistor M8 is electrically connected to the first selection signal terminal SW1, the first electrode of the eighth transistor M8 is electrically connected to the output terminal of the first power generation circuit 210, and the second electrode of the eighth transistor M8 is electrically connected to the second power source.
  • the gate of the ninth transistor M8 is electrically connected to the second selection signal terminal SW2, the first electrode of the ninth transistor M8 is electrically connected to the output terminal of the second power generation circuit 220, and the second electrode of the ninth transistor M8 is electrically connected to the second power source.
  • Line VSSL for electrical connection.
  • the power management circuit 200 may be provided in a driver integrated circuit (Integrated Circuit, IC).
  • IC Integrated Circuit
  • the working process of the above-mentioned display panel may include: a display phase T10 and a detection phase T20.
  • the display phase T10 may include a data writing phase T11 and a light emitting phase T12.
  • the signal HSY for controlling the voltage on the collected data detection line SDL is always at a high level, so in the display phase T10, the working process of collecting the voltage on the data detection line SDL is not performed.
  • the detection signal line SAL is always loaded with a high level signal
  • the first selection signal terminal SW1 is always loaded with a high level signal
  • the second selection signal terminal SW2 is always loaded with a low level signal
  • the reset signal line RE is always loaded with a high level signal. Level signal. Therefore, in the display phase T10, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are all turned off.
  • the detection signal line SAL is a high-level signal
  • the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are all turned off. Since the scan signal line GAL is a low-level signal, both the first transistor M1 and the second transistor M2 can be controlled to be turned on. In this way, the data signal on the data detection line SDL can be input to the gate of the driving transistor M0, so that the gate voltage of the driving transistor M0 is the voltage Vdata of the data signal.
  • the voltage of the first pole of the voltage stabilizing capacitor CLC is also the voltage Vdata of the data signal.
  • the voltage difference between the first electrode of the voltage stabilizing capacitor CLC and the gate of the driving transistor M0 can be substantially zero, so there is no voltage drop, so that the influence of the leakage current on the voltage of the gate of the driving transistor M0 can be reduced. Furthermore, the stability of the voltage of the gate of the driving transistor M0 can be improved.
  • the fifth transistor M5 and the sixth transistor M6 are both turned off. Since the scan signal terminal GA is a high-level signal, both the first transistor M1 and the second transistor M2 can be controlled to be turned off.
  • the driving transistor M0 handles the saturation state, thereby generating a driving current Id for driving the light emitting device L to emit light, thereby causing the light emitting device to emit light.
  • Vdd is the voltage of the first power supply terminal ELVDD
  • Vth is the threshold voltage of the driving transistor M0.
  • the detection phase T20 may include a reset phase T21, a charging phase T22, and a sampling phase T23.
  • a high-level signal is always applied to the scan signal line GAL
  • a high-level signal is always applied to the second selection signal terminal SW2
  • a low-level signal is always applied to the first selection signal terminal SW1. Therefore, in the detection phase T20, the first transistor M1, the second transistor M2, and the ninth transistor M8 are all turned off.
  • the seventh transistor M7 is turned on to input the reset signal transmitted on the initialization signal line INIT into the data detection line SDL. Since the detection signal line SAL is a low-level signal, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are all turned on. Both the first transistor M1 and the second transistor M2 can be controlled to be turned on. In this way, the reset signal of the data detection line SDL can be input to the gate of the driving transistor M0, so that the gate voltage of the driving transistor M0 is the voltage Vinit of the reset signal, thereby resetting the gate of the driving transistor M0.
  • the seventh transistor M7 is turned off, and the data detection line SDL is floating. Since the detection signal line SAL is a low-level signal, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are all turned on. In this way, the voltage of the first power supply terminal ELVDD can charge the data detection line SDL through the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6. And the charging ends when the data detection line SDL is charged to Vdd+Vth. It should be noted that the charging time needs several hundred microseconds to several milliseconds. Of course, the charging time can be set according to the requirements of the actual application, and it is not limited here.
  • the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are all turned on.
  • the signal HSY that controls the voltage on the collected data detection line SDL is low. Therefore, in the sampling phase T23, the voltage on the collected data detection line SDL can be controlled and processed according to the voltage on the collected data detection line SDL.
  • the threshold voltage compensation of the driving transistor M0 is realized.
  • the embodiment of the present disclosure also provides a display device, including the above-mentioned display panel provided by the embodiment of the present disclosure.
  • the principle of the display device to solve the problem is similar to that of the aforementioned display panel. Therefore, the implementation of the display device can refer to the implementation of the aforementioned display panel, and the repetitive points will not be repeated here.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • Other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as a limitation to the present disclosure.
  • the first control circuit is configured to conduct the data detection terminal and the second terminal of the first control circuit in response to the signal of the first control signal terminal;
  • the two control circuits are configured to conduct the first pole of the stabilizing capacitor and the gate of the driving transistor in response to the signal of the second control signal terminal.
  • the charge storage effect of the voltage stabilizing capacitor can be used, so that the leakage current of the transistor is stored in the stabilizing capacitor, thereby reducing the gap between the first pole of the stabilizing capacitor and the data detection terminal. Voltage difference, thereby reducing leakage current.
  • the voltage of the first electrode of the voltage stabilizing capacitor and the voltage of the gate of the driving transistor can be approximately the same during the light-emitting phase, so that the voltage difference between the first electrode of the voltage stabilizing capacitor and the gate of the driving transistor can be approximately If the value is zero, the influence of the leakage current on the voltage of the gate of the driving transistor can be further reduced, and the voltage stability of the gate of the driving transistor can be further improved.

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Abstract

一种驱动电路、驱动方法、显示面板及显示装置，其中，驱动电路包括：驱动晶体管（M0），驱动晶体管（M0）的第一极与第一电源端（ELVDD）电连接，驱动晶体管（M0）的第二极与待驱动器件(L)电连接；第一控制电路（1），第一控制电路（1）的第一端与数据检测端电连接，第一控制电路（1）的控制端与控制信号端（CS）电连接；稳压电容 (CLC)，稳压电容(CLC)的第一极与第一控制电路（1）的第二端电连接，稳压电容(CLC)的第二极与第一电源端（ELVDD）电连接；第二控制电路（2），第二控制电路（2）的第一端与稳压电容(CLC)的第一极电连接，第二控制电路（2）的第二端与驱动晶体管（M0）的栅极电连接，第二控制电路（2）的控制端与控制信号端（CS）电连接。

Description

驱动电路、驱动方法、显示面板及显示装置
相关申请的交叉引用
本申请要求在2020年05月13日提交中国专利局、申请号为202010400264.1、申请名称为“驱动电路、驱动方法、显示面板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，特别涉及驱动电路、驱动方法、显示面板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示器是当今平板显示器研究领域的热点之一，与液晶显示器(Liquid Crystal Display，LCD)相比，OLED显示器具有低能耗、生产成本低、自发光、宽视角及响应速度快等优点。其中，用于控制发光器件发光的驱动电路是OLED显示器的核心技术内容，具有重要的研究意义。然而，由于驱动电路中晶体管的漏电流特性，导致驱动晶体管的栅极的电压不稳定，进而导致发光不稳定，造成亮度不均的问题。
发明内容
本公开实施例提供的驱动电路，包括：
驱动晶体管，所述驱动晶体管的第一极与第一电源端电连接，所述驱动晶体管的第二极与待驱动器件电连接；
第一控制电路，所述第一控制电路的第一端与数据检测端电连接，所述第一控制电路的控制端与控制信号端电连接；且所述第一控制电路被配置为响应于所述第一控制信号端的信号，将所述数据检测端与所述第一控制电路 的第二端导通；
稳压电容，所述稳压电容的第一极与所述第一控制电路的第二端电连接，所述稳压电容的第二极与所述第一电源端电连接；
第二控制电路，所述第二控制电路的第一端与所述稳压电容的第一极电连接，所述第二控制电路的第二端与所述驱动晶体管的栅极电连接，所述第二控制电路的控制端与所述控制信号端电连接；且所述第二控制电路被配置为响应于所述第二控制信号端的信号，将所述稳压电容的第一极与所述驱动晶体管的栅极导通。
在一些示例中，在本公开实施例中，所述控制信号端包括：扫描信号端；
所述第一控制电路包括第一晶体管；其中，所述第一晶体管的第一极与所述数据检测端电连接，所述第一晶体管的栅极与所述扫描信号端电连接，所述第一晶体管的第二极与所述稳压电容的第一极电连接；
所述第二控制电路包括第二晶体管；其中，所述第二晶体管的第一极与所述稳压电容的第一极电连接，所述第二晶体管的栅极与所述扫描信号端电连接，所述第二晶体管的第二极与所述驱动晶体管的栅极电连接。
在一些示例中，在本公开实施例中，所述控制信号端还包括：检测信号端；
所述第一控制电路还包括第三晶体管；其中，所述第三晶体管的第一极与所述数据检测端电连接，所述第三晶体管的栅极与所述检测信号端电连接，所述第三晶体管的第二极与所述稳压电容的第一极电连接；
所述第二控制电路还包括第四晶体管；其中，所述第四晶体管的第一极与所述稳压电容的第一极电连接，所述第四晶体管的栅极与所述检测信号端电连接，所述第四晶体管的第二极与所述驱动晶体管的栅极电连接。
在一些示例中，在本公开实施例中，所述控制信号端包括：检测信号端；
所述驱动电路还包括：
第五晶体管，所述第五晶体管的栅极与所述检测信号端电连接，所述第五晶体管的第一极与所述驱动晶体管的栅极电连接；
第六晶体管，所述第六晶体管的栅极与所述检测信号端电连接，所述第六晶体管的第一极与所述第五晶体管的第二极电连接，所述第六晶体管的第二极与所述驱动晶体管的第二极电连接。
在一些示例中，在本公开实施例中，所述驱动电路还包括：
存储电容，所述存储电容的第一极与所述驱动晶体管的栅极电连接，所述存储电容的第二极与所述第一电源端电连接。
本公开实施例提供的显示面板，包括：
衬底基板；
多个子像素，位于所述衬底基板上，且所述多个子像素中的至少一个包括发光器件以及上述驱动电路；其中，所述驱动电路中的所述驱动晶体管的第二极与所述发光器件的第一电极电连接；
多条控制信号线，位于所述衬底基板上，且一行子像素中驱动电路的控制信号端与至少一条所述控制信号线对应电连接；
多条数据检测线，位于所述衬底基板上，且一列子像素中驱动电路的数据检测端与至少一条所述数据检测线对应电连接。
在一些示例中，在本公开实施例中，所述多条控制信号线包括：扫描信号线；一行子像素中驱动电路的扫描信号端与一条所述扫描信号线对应电连接。
在一些示例中，在本公开实施例中，所述多条控制信号线还包括：检测信号线；一行子像素中驱动电路的检测信号端与一条所述检测信号线对应电连接。
在一些示例中，在本公开实施例中，所述显示面板还包括：
复位信号线；
初始化信号线；
多个第七晶体管，一条所述数据检测线对应一个所述第七晶体管；其中，所述多个第七晶体管的栅极均与所述复位信号线电连接，所述多个第七晶体管的第一极均与所述初始化信号线电连接，各所述第七晶体管的第二极分别 与对应的所述数据检测线电连接。
在一些示例中，在本公开实施例中，所述显示面板还包括：
第一电源线，所述第一电源线与所述驱动电路的第一电源端电连接；
第二电源线，所述第二电源线与所述发光器件的第二电极电连接；
电源管理电路，包括：第一电源生成电路、第二电源生成电路、第八晶体管和第九晶体管；其中，所述第一电源生成电路被配置为生成向所述第一电源端加载的第一电压，所述第二电源生成电路被配置为生成向所述第二电源端加载的第二电压；
其中，所述第一电源生成电路的输出端与所述第一电源线电连接；
所述第八晶体管的栅极与第一选择信号端电连接，所述第八晶体管的第一极与所述第一电源生成电路的输出端电连接，所述第八晶体管的第二极与所述第二电源线电连接；
所述第九晶体管的栅极与第二选择信号端电连接，所述第九晶体管的第一极与所述第二电源生成电路的输出端电连接，所述第九晶体管的第二极与所述第二电源线电连接。
本公开实施例提供的显示装置，包括上述显示面板。
本公开实施例提供的上述驱动电路的驱动方法，所述驱动方法包括：显示阶段和检测阶段；
所述显示阶段包括数据写入阶段和发光阶段；
其中，在所述数据写入阶段，所述第一控制电路响应于所述第一控制信号端的信号，将所述数据检测端与所述第一控制电路的第二端导通；所述第二控制电路响应于所述第二控制信号端的信号，将所述稳压电容的第一极与所述驱动晶体管的栅极导通；
在所述发光阶段，所述驱动晶体管产生驱动电流，并将所述驱动电流提供给所述待驱动器件，驱动所述待驱动器件发光；
所述检测阶段包括复位阶段、充电阶段以及取样阶段；
其中，在所述复位阶段，向所述数据检测端加载初始化信号，对所述数 据检测端进行复位；所述第一控制电路响应于所述第一控制信号端的信号，将所述数据检测端与所述第一控制电路的第二端导通，所述第二控制电路响应于所述第二控制信号端的信号，将所述稳压电容的第一极与所述驱动晶体管的栅极导通，对所述驱动晶体管进行复位；
在所述充电阶段，所述数据检测端浮接，所述第一控制电路响应于所述第一控制信号端的信号，将所述数据检测端与所述第一控制电路的第二端导通；所述第二控制电路响应于所述第二控制信号端的信号，将所述稳压电容的第一极与所述驱动晶体管的栅极导通；第五晶体管和第六晶体管导通，以对所述数据检测端进行充电；
在所述取样阶段，采集所述数据检测端充电后的电压。
附图说明
图1为本公开实施例中的一些驱动电路的结构示意图；
图2a为本公开实施例中的一些信号时序图；
图2b为本公开实施例中的又一些信号时序图；
图3为本公开实施例中的又一些驱动电路的结构示意图；
图4为本公开实施例中的又一些信号时序图；
图5为本公开实施例中的驱动电路的一些驱动方法的流程图；
图6为本公开实施例中的驱动电路的又一些驱动方法的流程图；
图7为本公开实施例中的一些显示面板的结构示意图；
图8为本公开实施例中的一些显示面板的具体结构示意图；
图9a为本公开实施例中的显示面板的一些信号时序图；
图9b为本公开实施例中的显示面板的一些信号时序图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然， 所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
本公开实施例提供的一些驱动电路，如图1所示，可以包括：
驱动晶体管M0，驱动晶体管M0的第一极与第一电源端ELVDD电连接，驱动晶体管M0的第二极与待驱动器件L电连接；
第一控制电路1，第一控制电路1的第一端与数据检测端SD电连接，第一控制电路1的控制端与控制信号端CS电连接；且第一控制电路1被配置为响应于第一控制信号端CS的信号，将数据检测端SD与第一控制电路1的第二端导通；
稳压电容CLC，稳压电容CLC的第一极与第一控制电路1的第二端电连接；
第二控制电路2，第二控制电路2的第一端与稳压电容CLC的第二极电连接，第二控制电路2的第二端与驱动晶体管M0的栅极电连接，第二控制电路2的控制端与控制信号端CS电连接；且第二控制电路2被配置为响应于第二控制信号端CS的信号，将稳压电容CLC的第二极与驱动晶体管M0的栅 极导通。
本公开实施例提供的上述驱动电路，第一控制电路被配置为响应于第一控制信号端的信号，将数据检测端与第一控制电路的第二端导通；第二控制电路被配置为响应于第二控制信号端的信号，将稳压电容的第一极与驱动晶体管的栅极导通。并且，通过设置稳压电容，可以利用稳压电容存储电荷的作用，以使晶体管的漏电流被存储到稳压电容中，从而可以减小稳压电容的第一极与数据检测端之间的电压差，进而减小漏电流。并且，还可以在发光阶段使稳压电容的第一极的电压与驱动晶体管的栅极的电压大致相同，从而可以使稳压电容的第一极与驱动晶体管的栅极之间的电压差大致为零，进一步可以降低漏电流对驱动晶体管的栅极的电压的影响，进一步提高驱动晶体管的栅极的电压稳定性。
在具体实施时，在本公开实施例中，如图1所示，控制信号端CS包括：扫描信号端GA；其中，第一控制电路1包括第一晶体管M1；其中，第一晶体管M1的第一极与数据检测端SD电连接，第一晶体管M1的栅极与扫描信号端GA电连接，第一晶体管M1的第二极与稳压电容CLC的第一极电连接。并且，第二控制电路2包括第二晶体管M2；其中，第二晶体管M2的第一极与稳压电容CLC的第一极电连接，第二晶体管M2的栅极与扫描信号端GA电连接，第二晶体管M2的第二极与驱动晶体管M0的栅极电连接。
在具体实施时，在本公开实施例中，如图1所示，控制信号端CS还可以包括：检测信号端SA。并且，驱动电路还包括：第五晶体管M5和第六晶体管M6。其中，第五晶体管M5的栅极与检测信号端SA电连接，第五晶体管M5的第一极与驱动晶体管M0的栅极电连接。第六晶体管M6的栅极与检测信号端SA电连接，第六晶体管M6的第一极与第五晶体管M5的第二极电连接，第六晶体管M6的第二极与驱动晶体管M0的第二极电连接。
在具体实施时，在本公开实施例中，如图1所示，驱动电路还可以包括：存储电容CST。其中，存储电容CST的第一极与驱动晶体管M0的栅极电连接，存储电容CST的第二极与第一电源端ELVDD电连接。
在具体实施时，如图1所示，驱动晶体管M0M0可以为P型晶体管；其中，驱动晶体管M0M0的第一极为其源极，驱动晶体管M0M0的第二极为其漏极，并且该驱动晶体管M0M0处于饱和状态时，可以产生由驱动晶体管M0M0的源极传输向其漏极的驱动信号。当然，驱动晶体管M0也可以为N型晶体管；其中，驱动晶体管M0的第一极为其漏极，驱动晶体管M0的第二极为其源极，并且该驱动晶体管M0处于饱和状态时，可以产生由驱动晶体管M0的漏极传输向其源极的驱动信号。
在具体实施时，待驱动器件可以为发光器件，则驱动信号可以作为驱动发光器件发光的驱动电流。当然，在实际应用中，待驱动器件还可以设置为其他器件，在此不作限定。下面均以待驱动器件为发光器件为例进行说明。
在具体实施时，在本公开实施例中，发光器件的第一电极与驱动晶体管M0M0的第二极电连接，发光器件的第二电极与第二电源端ELVSSELVSS电连接。其中，发光器件的第一电极为其正极，第二电极为其负极。并且，发光器件一般为电致发光二极管，例如，发光器件可以包括：微型发光二极管(Micro Light Emitting Diode，Micro LED)、有机电致发光二极管(Organic Light Emitting Diode，OLED)以及量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)中的至少一种。另外，一般发光器件具有发光阈值电压，在发光器件两端的电压大于或等于发光阈值电压时进行发光。在实际应用中，可以根据实际应用环境来设计确定发光器件的具体结构，在此不作限定。
以上仅是举例说明本公开实施例提供的驱动电路中的各电路的具体结构，在具体实施时，上述电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，这些均在本公开的保护范围之内，具体在此不作限定。
在一些示例中，为了降低制备工艺，在具体实施时，在本公开实施例中，如图1所示，可以使所有晶体管均为P型晶体管。当然，也可以使所有晶体管均为N型晶体管，这也可以根据实际应用环境来设计确定，在此不作限定。
进一步的，在具体实施时，在本公开实施例中，P型晶体管在高电平信号作用下截止，在低电平信号作用下导通。N型晶体管在高电平信号作用下导通，在低电平信号作用下截止。
需要说明的是，本公开上述实施例中提到的晶体管可以是薄膜晶体管(Thin Film Transistor，TFT)，也可以是金属氧化物半导体场效应管(Metal Oxide Scmiconductor，MOS)，在此不作限定。
在具体实施中，可以根据晶体管的类型以及其栅极的信号，将晶体管的第一极作为其源极，第二极作为其漏极；或者，反之，将晶体管的第一极作为其漏极，第二极作为其源极，这可以根据实际应用环境来设计确定，具体在此不做具体区分。
在具体实施时，在本公开实施例中，第一电源端ELVDD的电压Vdd一般为正值，第二电源端ELVSS的电压Vss一般接地或为负值。在实际应用中，第一电源端ELVDD的电压Vdd和第二电源端ELVSS的电压Vss的具体数值可以根据实际应用环境来设计确定，在此不作限定。
下面以图1所示的驱动电路为例，结合图2a与图2b所示的信号时序图，对本公开实施例提供的上述驱动电路的工作过程作以描述。
具体地，本公开实施例提供的上述驱动电路的工作过程可以包括：显示阶段T10和检测阶段T20。
其中，如图2a所示，显示阶段T10可以包括数据写入阶段T11和发光阶段T12。并且，在显示阶段T10中，检测信号端SA一直为高电平信号。
在数据写入阶段T11，由于检测信号端SA为高电平信号，因此第五晶体管M5和第六晶体管M6均截止。由于扫描信号端GA为低电平信号，可以控制第一晶体管M1和第二晶体管M2均导通。这样可以使数据检测端SD的数据信号输入驱动晶体管M0的栅极，以使驱动晶体管M0的栅极电压为数据信号的电压Vdata，并通过存储电容CST进行存储。并且，还会使稳压电容CLC的第一极的电压也为数据信号的电压Vdata。这样可以使稳压电容CLC的第一极与驱动晶体管M0的栅极之间的电压差大致为零，因此不存在压降，从而可以降低漏 电流对驱动晶体管M0的栅极的电压的影响，进而可以提高驱动晶体管M0的栅极的电压的稳定性。
在发光阶段T12，由于检测信号端SA为高电平信号，因此第五晶体管M5和第六晶体管M6均截止。由于扫描信号端GA为高电平信号，可以控制第一晶体管M1和第二晶体管M2均截止。驱动晶体管M0处理饱和状态，从而产生驱动发光器件L发光的驱动电流Id，并且，
Figure PCTCN2021086093-appb-000001
其中，Vdd为第一电源端ELVDD的电压，Vth为驱动晶体管M0的阈值电压。从而驱动发光器件L发光。
其中，如图2b所示，检测阶段T20可以包括复位阶段T21、充电阶段T22以及取样阶段T23。
在复位阶段T21，由于检测信号端SA为高电平信号，因此第五晶体管M5和第六晶体管M6均截止。由于扫描信号端GA为低电平信号，可以控制第一晶体管M1和第二晶体管M2均导通。这样可以使数据检测端SD的复位信号输入驱动晶体管M0的栅极，以使驱动晶体管M0的栅极电压为复位信号的电压Vinit，从而对驱动晶体管M0的栅极进行复位。
在充电阶段T22，数据检测端SD浮接，由于检测信号端SA为低电平信号，因此第五晶体管M5和第六晶体管M6均导通。由于扫描信号端GA为低电平信号，可以控制第一晶体管M1和第二晶体管M2均导通。这样可以使第一电源端ELVDD的电压通过第一晶体管M1、第二晶体管M2、第五晶体管M5和第六晶体管M6对数据检测端SD充电。并在将数据检测端SD充电到Vdd+Vth时结束充电。需要说明的是，充电时间需要几百微秒到几毫秒，当然充电时间可以根据实际应用的需求进行设定，在此不作限定。
在取样阶段T23，由于检测信号端SA为低电平信号，因此第五晶体管M5和第六晶体管M6均导通。由于扫描信号端GA为低电平信号，可以控制第一晶体管M1和第二晶体管M2均导通。采集数据检测端SD的电压，并根据采集到的数据检测端SD的电压进行处理以实现对驱动晶体管M0的阈值电压补偿。
本公开实施例又提供了一些阵列基板，其结构示意图如图3所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，如图3所示，控制信号端CS还可以包括：检测信号端SA。并且，第一控制电路1还包括第三晶体管M3；其中，第三晶体管M3的第一极与数据检测端SD电连接，第三晶体管M3的栅极与检测信号端SA电连接，第三晶体管M3的第二极与稳压电容CLC的第一极电连接。第二控制电路2还包括第四晶体管M4；其中，第四晶体管M4的第一极与稳压电容CLC的第一极电连接，第四晶体管M4的栅极与检测信号端SA电连接，第四晶体管M4的第二极与驱动晶体管M0的栅极电连接。
下面以图3所示的驱动电路为例，结合图2a与图3所示的信号时序图，对本公开实施例提供的上述驱动电路的工作过程作以描述。
其中，如图2a所示，显示阶段T10可以包括数据写入阶段T11和发光阶段T12。并且，在显示阶段T10中，检测信号端SA一直为高电平信号，则第三晶体管M3、第四晶体管M4、第五晶体管M5和第六晶体管M6均截止。图3所示的驱动电路在显示阶段T10的工作过程可以与图1所示的驱动电路在显示阶段T10的工作过程基本相同，具体在此不作赘述。
其中，如图4所示，检测阶段T20可以包括复位阶段T21、充电阶段T22以及取样阶段T23。在检测阶段T20，扫描信号端GA一直为高电平信号，则第一晶体管M1和第二晶体管M2均截止。
在复位阶段T21，由于检测信号端SA为低电平信号，因此第三晶体管M3、第四晶体管M4、第五晶体管M5和第六晶体管M6均导通。这样可以使数据检测端SD的复位信号输入驱动晶体管M0的栅极，以使驱动晶体管M0的栅极电压为复位信号的电压Vinit，从而对驱动晶体管M0的栅极进行复位。
在充电阶段T22，数据检测端SD浮接，由于检测信号端SA为低电平信号，因此第三晶体管M3、第四晶体管M4、第五晶体管M5和第六晶体管M6均导通。这样可以使第一电源端ELVDD的电压通过第三晶体管M3、第四晶体管M4、 第五晶体管M5和第六晶体管M6对数据检测端SD充电。并在将数据检测端SD充电到Vdd+Vth时结束充电。需要说明的是，充电时间需要几百微秒到几毫秒，当然充电时间可以根据实际应用的需求进行设定，在此不作限定。
在取样阶段T23，由于检测信号端SA为低电平信号，因此第三晶体管M3、第四晶体管M4、第五晶体管M5和第六晶体管M6均导通。采集数据检测端SD的电压，并根据采集到的数据检测端SD的电压进行处理以实现对驱动晶体管M0的阈值电压补偿。
基于同一发明构思，本公开实施例还提供了一些上述驱动电路的驱动方法。驱动方法可以包括：显示阶段T10和检测阶段T20；其中，显示阶段T10包括数据写入阶段和发光阶段。检测阶段T20包括复位阶段、充电阶段以及取样阶段。
如图5所示，本公开实施例提供的驱动电路的驱动方法，可以包括如下步骤：
S510、在数据写入阶段，第一控制电路响应于第一控制信号端的信号，将数据检测端与第一控制电路的第二端导通；第二控制电路响应于第二控制信号端的信号，将稳压电容的第一极与驱动晶体管的栅极导通。
S520、在发光阶段，驱动晶体管产生驱动电流，并将驱动电流提供给待驱动器件，驱动待驱动器件发光。
需要说明的是，上述步骤S510-S520的工作过程和工作原理可以参照上述实施例中驱动电路的工作过程，在此不作赘述。
如图6所示，本公开实施例提供的驱动电路的驱动方法，可以包括如下步骤：
S610、在复位阶段，向数据检测端加载初始化信号，对数据检测端进行复位；第一控制电路响应于第一控制信号端的信号，将数据检测端与第一控制电路的第二端导通，第二控制电路响应于第二控制信号端的信号，将稳压电容的第一极与驱动晶体管的栅极导通，对驱动晶体管进行复位；
S620、在充电阶段，数据检测端浮接，第一控制电路响应于第一控制信 号端的信号，将数据检测端与第一控制电路的第二端导通；第二控制电路响应于第二控制信号端的信号，将稳压电容的第一极与驱动晶体管的栅极导通；第五晶体管和第六晶体管导通，以对数据检测端进行充电；
S630、在取样阶段，采集数据检测端充电后的电压。
需要说明的是，上述步骤S610-S630的工作过程和工作原理可以参照上述实施例中驱动电路的工作过程，在此不作赘述。
基于同一发明构思，本公开实施例还提供了一些显示面板，如图7所示，可以包括：衬底基板100。位于衬底基板100的显示区AA中的多个像素单元PX，像素单元PX可以包括多个子像素spx。示例性地，多个子像素中的至少一个可以包括发光器件和驱动电路；其中，驱动电路中的驱动晶体管M0的第二极与发光器件的第一电极电连接。需要说明的是，该驱动电路的结构和工作原理可以参照上述实施例，在此不作赘述。下面均以图3所示的驱动电路的结构为例进行说明。
在具体实施时，在本公开实施例中，可以使每一个子像素包括：一个发光器件和一个驱动电路。
在具体实施时，在本公开实施例中，如图7所示，显示面板还可以包括：位于衬底基板100上的多条控制信号线CSL和多条数据检测线SDL。其中，一行子像素中驱动电路的控制信号端CS与至少一条控制信号线CSL对应电连接，一列子像素中驱动电路的数据检测端SD与至少一条数据检测线SDL对应电连接。示例性地，一列子像素中驱动电路的数据检测端SD与一条数据检测线SDL对应电连接。
在具体实施时，控制信号端CS可以包括扫描信号端GA，并且其具体实施方式可以参照图1和图3所示的实施例。在本公开实施例中，结合图3、图7以及图8所示，多条控制信号线CSL可以包括：扫描信号线GAL。其中，一行子像素中驱动电路的扫描信号端GA与一条扫描信号线GAL对应电连接。也就是说，一行子像素中驱动电路的第一晶体管M1和第二晶体管M2的栅极均与对应的一条扫描信号线GAL电连接。
在具体实施时，控制信号端CS还可以包括：检测信号端SA，并且其具体实施方式可以参照图1和图3所示的实施例。在本公开实施例中，结合图3、图7以及图8所示，多条控制信号线CSL还可以包括：检测信号线SAL；一行子像素中驱动电路的检测信号端SA与一条检测信号线SAL对应电连接。也就是说，一行子像素中驱动电路的第三晶体管M3、第四晶体管M4、第五晶体管M5以及第六晶体管M6的栅极可以均与对应的一条检测信号线SAL电连接。
在具体实施时，在本公开实施例中，结合图3、图7以及图8所示，显示面板还可以包括：复位信号线RE、初始化信号线INIT以及多个第七晶体管M7。其中，一条数据检测线SDL对应一个第七晶体管M7。并且，多个第七晶体管M7的栅极均与复位信号线RE电连接，多个第七晶体管M7的第一极均与初始化信号线INIT电连接，各第七晶体管M7的第二极分别与对应的数据检测线SDL电连接。示例性地，复位信号线RE、初始化信号线INIT以及多个第七晶体管M7可以设置于非显示区BB中。当然，在实际应用中，可以根据实际应用的需求进行设计，在此不作限定。
在具体实施时，在本公开实施例中，结合图3、图7以及图8所示，显示面板还可以包括：第一电源线VDDL，第二电源线VSSL，电源管理电路200。其中，第一电源线VDDL与驱动电路的第一电源端ELVDD电连接，第二电源线VSSL与发光器件L的第二电极电连接。并且，电源管理电路200可以包括：第一电源生成电路210、第二电源生成电路220、第八晶体管M8和第九晶体管M8；其中，第一电源生成电路210被配置为生成向第一电源端ELVDD加载的第一电压，第二电源生成电路220被配置为生成向第二电源端ELVSS加载的第二电压；
其中，第一电源生成电路210的输出端与第一电源线VDDL电连接；
第八晶体管M8的栅极与第一选择信号端SW1电连接，第八晶体管M8的第一极与第一电源生成电路210的输出端电连接，第八晶体管M8的第二极与第二电源线VSSL电连接；
第九晶体管M8的栅极与第二选择信号端SW2电连接，第九晶体管M8的第一极与第二电源生成电路220的输出端电连接，第九晶体管M8的第二极与第二电源线VSSL电连接。
示例性地，电源管理电路200可以设置于驱动集成电路(Integrated Circuit，IC)中。当然，在实际应用中，可以根据实际应用的需求进行设计，在此不作限定。
下面结合图7和图8所示的显示面板，结合图9a与图9b所示的信号时序图，对本公开实施例提供的上述显示面板的工作过程作以描述。其中，以一个子像素中的驱动电路的工作过程为了。
具体地，本公开实施例提供的上述显示面板的工作过程可以包括：显示阶段T10和检测阶段T20。
其中，如图9a所示，显示阶段T10可以包括数据写入阶段T11和发光阶段T12。并且，在显示阶段T10中，控制采集数据检测线SDL上的电压的信号HSY一直为高电平，因此在显示阶段T10中，不进行采集数据检测线SDL上的电压的工作过程。并且，对检测信号线SAL一直加载高电平信号，对第一选择信号端SW1一直加载高电平信号，对第二选择信号端SW2一直加载低电平信号，对复位信号线RE一直加载高电平信号。因此，在显示阶段T10中，第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7、以及第八晶体管M8均截止。
在数据写入阶段T11，由于检测信号线SAL为高电平信号，因此第三晶体管M3、第四晶体管M4、第五晶体管M5和第六晶体管M6均截止。由于扫描信号线GAL为低电平信号，可以控制第一晶体管M1和第二晶体管M2均导通。这样可以使数据检测线SDL上的数据信号输入驱动晶体管M0的栅极，以使驱动晶体管M0的栅极电压为数据信号的电压Vdata。并且，还会使稳压电容CLC的第一极的电压也为数据信号的电压Vdata。这样可以使稳压电容CLC的第一极与驱动晶体管M0的栅极之间的电压差大致为零，因此不存在压降，从而可以降低漏电流对驱动晶体管M0的栅极的电压的影响，进而可以提高驱动晶体管 M0的栅极的电压的稳定性。
在发光阶段T12，由于检测信号线SAL为高电平信号，因此第五晶体管M5和第六晶体管M6均截止。由于扫描信号端GA为高电平信号，可以控制第一晶体管M1和第二晶体管M2均截止。驱动晶体管M0处理饱和状态，从而产生驱动发光器件L发光的驱动电流Id，从而使发光器件发光。并且，
Figure PCTCN2021086093-appb-000002
其中，Vdd为第一电源端ELVDD的电压，Vth为驱动晶体管M0的阈值电压。
其中，如图9b所示，检测阶段T20可以包括复位阶段T21、充电阶段T22以及取样阶段T23。并且，在检测阶段T20，对扫描信号线GAL一直加载高电平信号，对第二选择信号端SW2一直加载高电平信号，对第一选择信号端SW1一直加载低电平信号。因此，在检测阶段T20中，第一晶体管M1、第二晶体管M2以及第九晶体管M8均截止。
在复位阶段T21，由于复位信号线RE上传输的信号为低电平信号，因此第七晶体管M7导通，以将初始化信号线INIT上传输的复位信号输入数据检测线SDL。由于检测信号线SAL为低电平信号，因此第三晶体管M3、第四晶体管M4、第五晶体管M5和第六晶体管M6均导通。可以控制第一晶体管M1和第二晶体管M2均导通。这样可以使数据检测线SDL的复位信号输入驱动晶体管M0的栅极，以使驱动晶体管M0的栅极电压为复位信号的电压Vinit，从而对驱动晶体管M0的栅极进行复位。
在充电阶段T22，由于复位信号线RE上传输的信号为高电平信号，因此第七晶体管M7截止，数据检测线SDL浮接。由于检测信号线SAL为低电平信号，因此第三晶体管M3、第四晶体管M4、第五晶体管M5和第六晶体管M6均导通。这样可以使第一电源端ELVDD的电压通过第三晶体管M3、第四晶体管M4、第五晶体管M5和第六晶体管M6对数据检测线SDL充电。并在将数据检测线SDL充电到Vdd+Vth时结束充电。需要说明的是，充电时间需要几百微秒到几毫秒，当然充电时间可以根据实际应用的需求进行设定，在此不作限定。
在取样阶段T23，由于检测信号线SAL为低电平信号，因此第三晶体管M3、第四晶体管M4、第五晶体管M5和第六晶体管M6均导通。控制采集数据检测线SDL上的电压的信号HSY为低电平，因此在取样阶段T23中，可以控制采集数据检测线SDL上的电压，并根据采集到的数据检测线SDL上的电压进行处理以实现对驱动晶体管M0的阈值电压补偿。
基于同一发明构思，本公开实施例还提供了显示装置，包括本公开实施例提供的上述显示面板。该显示装置解决问题的原理与前述显示面板相似，因此该显示装置的实施可以参见前述显示面板的实施，重复之处在此不再赘述。
在具体实施时，在本公开实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
本公开实施例提供的驱动电路、驱动方法显示面板及显示装置，第一控制电路被配置为响应于第一控制信号端的信号，将数据检测端与第一控制电路的第二端导通；第二控制电路被配置为响应于第二控制信号端的信号，将稳压电容的第一极与驱动晶体管的栅极导通。并且，通过设置稳压电容，可以利用稳压电容存储电荷的作用，以使晶体管的漏电流被存储到稳压电容中，从而可以减小稳压电容的第一极与数据检测端之间的电压差，进而减小漏电流。并且，还可以在发光阶段使稳压电容的第一极的电压与驱动晶体管的栅极的电压大致相同，从而可以使稳压电容的第一极与驱动晶体管的栅极之间的电压差大致为零，进一步可以降低漏电流对驱动晶体管的栅极的电压的影响，进一步提高驱动晶体管的栅极的电压稳定性。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不 脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (12)

  1. 一种驱动电路，其中，包括：
    驱动晶体管，所述驱动晶体管的第一极与第一电源端电连接，所述驱动晶体管的第二极与待驱动器件电连接；
    第一控制电路，所述第一控制电路的第一端与数据检测端电连接，所述第一控制电路的控制端与控制信号端电连接；且所述第一控制电路被配置为响应于所述第一控制信号端的信号，将所述数据检测端与所述第一控制电路的第二端导通；
    稳压电容，所述稳压电容的第一极与所述第一控制电路的第二端电连接，所述稳压电容的第二极与所述第一电源端电连接；
    第二控制电路，所述第二控制电路的第一端与所述稳压电容的第一极电连接，所述第二控制电路的第二端与所述驱动晶体管的栅极电连接，所述第二控制电路的控制端与所述控制信号端电连接；且所述第二控制电路被配置为响应于所述第二控制信号端的信号，将所述稳压电容的第一极与所述驱动晶体管的栅极导通。
  2. 如权利要求1所述的驱动电路，其中，所述控制信号端包括：扫描信号端；
    所述第一控制电路包括第一晶体管；其中，所述第一晶体管的第一极与所述数据检测端电连接，所述第一晶体管的栅极与所述扫描信号端电连接，所述第一晶体管的第二极与所述稳压电容的第一极电连接；
    所述第二控制电路包括第二晶体管；其中，所述第二晶体管的第一极与所述稳压电容的第一极电连接，所述第二晶体管的栅极与所述扫描信号端电连接，所述第二晶体管的第二极与所述驱动晶体管的栅极电连接。
  3. 如权利要求2所述的驱动电路，其中，所述控制信号端还包括：检测信号端；
    所述第一控制电路还包括第三晶体管；其中，所述第三晶体管的第一极 与所述数据检测端电连接，所述第三晶体管的栅极与所述检测信号端电连接，所述第三晶体管的第二极与所述稳压电容的第一极电连接；
    所述第二控制电路还包括第四晶体管；其中，所述第四晶体管的第一极与所述稳压电容的第一极电连接，所述第四晶体管的栅极与所述检测信号端电连接，所述第四晶体管的第二极与所述驱动晶体管的栅极电连接。
  4. 如权利要求1-3任一项所述的驱动电路，其中，所述控制信号端包括：检测信号端；
    所述驱动电路还包括：
    第五晶体管，所述第五晶体管的栅极与所述检测信号端电连接，所述第五晶体管的第一极与所述驱动晶体管的栅极电连接；
    第六晶体管，所述第六晶体管的栅极与所述检测信号端电连接，所述第六晶体管的第一极与所述第五晶体管的第二极电连接，所述第六晶体管的第二极与所述驱动晶体管的第二极电连接。
  5. 如权利要求1-4任一项所述的驱动电路，其中，所述驱动电路还包括：
    存储电容，所述存储电容的第一极与所述驱动晶体管的栅极电连接，所述存储电容的第二极与所述第一电源端电连接。
  6. 一种显示面板，其中，包括：
    衬底基板；
    多个子像素，位于所述衬底基板上，且所述多个子像素中的至少一个包括发光器件以及如权利要求1-5任一项所述的驱动电路；其中，所述驱动电路中的所述驱动晶体管的第二极与所述发光器件的第一电极电连接；
    多条控制信号线，位于所述衬底基板上，且一行子像素中驱动电路的控制信号端与至少一条所述控制信号线对应电连接；
    多条数据检测线，位于所述衬底基板上，且一列子像素中驱动电路的数据检测端与至少一条所述数据检测线对应电连接。
  7. 如权利要求6所述的显示面板，其中，所述多条控制信号线包括：扫描信号线；一行子像素中驱动电路的扫描信号端与一条所述扫描信号线对应 电连接。
  8. 如权利要求7所述的显示面板，其中，所述多条控制信号线还包括：检测信号线；一行子像素中驱动电路的检测信号端与一条所述检测信号线对应电连接。
  9. 如权利要求6-8任一项所述的显示面板，其中，所述显示面板还包括：
    复位信号线；
    初始化信号线；
    多个第七晶体管，一条所述数据检测线对应一个所述第七晶体管；其中，所述多个第七晶体管的栅极均与所述复位信号线电连接，所述多个第七晶体管的第一极均与所述初始化信号线电连接，各所述第七晶体管的第二极分别与对应的所述数据检测线电连接。
  10. 如权利要求6-9任一项所述的显示面板，其中，所述显示面板还包括：
    第一电源线，所述第一电源线与所述驱动电路的第一电源端电连接；
    第二电源线，所述第二电源线与所述发光器件的第二电极电连接；
    电源管理电路，包括：第一电源生成电路、第二电源生成电路、第八晶体管和第九晶体管；其中，所述第一电源生成电路被配置为生成向所述第一电源端加载的第一电压，所述第二电源生成电路被配置为生成向所述第二电源端加载的第二电压；
    其中，所述第一电源生成电路的输出端与所述第一电源线电连接；
    所述第八晶体管的栅极与第一选择信号端电连接，所述第八晶体管的第一极与所述第一电源生成电路的输出端电连接，所述第八晶体管的第二极与所述第二电源线电连接；
    所述第九晶体管的栅极与第二选择信号端电连接，所述第九晶体管的第一极与所述第二电源生成电路的输出端电连接，所述第九晶体管的第二极与所述第二电源线电连接。
  11. 一种显示装置，其中，包括如权利要求6-10任一项所述的显示面板。
  12. 一种如权利要求1-5任一项所述的驱动电路的驱动方法，其中，所述 驱动方法包括：显示阶段和检测阶段；
    所述显示阶段包括数据写入阶段和发光阶段；
    其中，在所述数据写入阶段，所述第一控制电路响应于所述第一控制信号端的信号，将所述数据检测端与所述第一控制电路的第二端导通；所述第二控制电路响应于所述第二控制信号端的信号，将所述稳压电容的第一极与所述驱动晶体管的栅极导通；
    在所述发光阶段，所述驱动晶体管产生驱动电流，并将所述驱动电流提供给所述待驱动器件，驱动所述待驱动器件发光；
    所述检测阶段包括复位阶段、充电阶段以及取样阶段；
    其中，在所述复位阶段，向所述数据检测端加载初始化信号，对所述数据检测端进行复位；所述第一控制电路响应于所述第一控制信号端的信号，将所述数据检测端与所述第一控制电路的第二端导通，所述第二控制电路响应于所述第二控制信号端的信号，将所述稳压电容的第一极与所述驱动晶体管的栅极导通，对所述驱动晶体管进行复位；
    在所述充电阶段，所述数据检测端浮接，所述第一控制电路响应于所述第一控制信号端的信号，将所述数据检测端与所述第一控制电路的第二端导通；所述第二控制电路响应于所述第二控制信号端的信号，将所述稳压电容的第一极与所述驱动晶体管的栅极导通；第五晶体管和第六晶体管导通，以对所述数据检测端进行充电；
    在所述取样阶段，采集所述数据检测端充电后的电压。
PCT/CN2021/086093 2020-05-13 2021-04-09 驱动电路、驱动方法、显示面板及显示装置 Ceased WO2021227725A1 (zh)

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