WO2021112170A1 - Infrared led element - Google Patents

Abstract

The present invention achieves an infrared LED element that can spread a current in a plane direction while improving light extraction efficiency.　The infrared LED element comprises: a conductive support substrate; a p-type or n-type first semiconductor layer disposed on the support substrate; an active layer disposed on the first semiconductor layer; a second semiconductor layer which is disposed on the active layer, is made of InP that is a different conductive type from the first semiconductor layer, and has uneven portions formed on the (-100) surface that is a surface opposite to the support substrate; a first electrode that is formed on a surface of the support substrate opposite to the active layer; and a second electrode disposed on the second semiconductor layer and having a shape extending in a direction substantially parallel to [011] and a direction substantially parallel to [0-11], wherein in the second electrode, the width A1 of a region extending in the direction substantially parallel to [0-11] is greater than the width B1 of a region extending in the direction substantially parallel to [011].

Description

Infrared LED element

The present invention relates to an infrared LED element.

Conventionally, as a light emitting element whose emission wavelength is in the infrared region of 1000 nm or more, development as a laser element for communication / measurement has been widely promoted. On the other hand, LED devices in such a wavelength range have not been used so far and have not been developed as much as laser devices.

For example, in Patent Document 1 below, a GaAs-based light emitting device can generate light having a wavelength of 0.7 to 0.8 μm (700 to 800 nm), but has a longer wavelength of about 1.3 μm (1300 nm). It is disclosed that an InP-based light emitting device is required to generate light. In particular, according to Patent Document 1, a p-type InP substrate can be used as a growth substrate, and an electrode can be formed after sequentially epitaxially growing a p-type clad layer, an active layer, and an n-type clad layer lattice-matched with an InP crystal. It is disclosed.

It should be noted that the infrared light element having an emission wavelength of about 850 nm is different in that a GaAs system is used for the active layer, but the electrodes on the p side and the n side are sandwiched between the active layer in the stacking direction. The LED element arranged as described above is disclosed in Patent Document 2 below.

According to Patent Document 2, a p-side electrode is arranged on the back surface side of the conductive support substrate, and a p-type semiconductor layer, an active layer, and an n-type semiconductor layer are laminated on the main surface (front surface) on the opposite side. The body is arranged via the reflective metal layer, and the n-side electrode is arranged on the upper surface of the n-type semiconductor layer. Then, in order to improve the light extraction efficiency, the surface of the n-type semiconductor layer is subjected to uneven processing.

Japanese Unexamined Patent Publication No. 4-282875 Japanese Unexamined Patent Publication No. 2012-129357 Japanese Unexamined Patent Publication No. 2012-74489

As mentioned above, the development of LED elements with emission wavelengths exceeding 1000 nm has not progressed because there have been few industrial applications so far. On the other hand, in recent years, there has been an increasing demand from the market for LED elements that emit light in such a wavelength band, and LED elements having higher light intensity have been demanded.

From this point of view, the present inventors also provide electrodes on the front and back surfaces of the wafer and the semiconductor layer on the light extraction surface side, as in the structure disclosed in Patent Document 2, in the InP-based infrared LED element. It was examined to improve the light extraction efficiency by applying unevenness processing to the surface of the wafer. Further, in order to allow an electric current to flow over a wide range in the active layer, it is necessary to form electrodes having a shape extending in a plurality of linear shapes such as a lattice shape and a comb shape on the surface of the semiconductor layer on the light extraction surface side. investigated.

By the way, when the surface of the semiconductor layer on the light extraction surface side is subjected to uneven processing, it is performed by etching after forming the electrode material on the surface. On the other hand, when the electrode is formed after the surface of the semiconductor layer is subjected to the unevenness processing, the electrode is formed on the surface of the semiconductor layer having the unevenness, and as a result, the surface of the electrode also becomes uneven. When the surface of the electrode is uneven in this way, the contact area between the bonding wire and the surface of the electrode becomes small when wire bonding is performed on the surface of the electrode in the subsequent mounting process of the LED element. There arises a problem that the bonding strength of the bonding wire is lowered. From this point of view, etching is performed after forming the electrode material on the surface of the semiconductor layer.

However, according to the diligent research by the present inventors, even if the surface of the semiconductor layer is subjected to uneven processing after forming the linear electrode, the effect of spreading the current in the surface direction may not be sufficiently exhibited. Was confirmed.

In view of the above problems, an object of the present invention is to realize an infrared LED element capable of expanding the current in the plane direction while improving the light extraction efficiency.

The infrared LED element according to the present invention is
Conductive support substrate and
A p-type or n-type first semiconductor layer arranged on the upper layer of the support substrate, and
It is composed of an active layer arranged on the upper layer of the first semiconductor layer and an InP arranged on the upper layer of the active layer and having a different conductive type from the first semiconductor layer, and is a surface opposite to the support substrate. A second semiconductor layer having an uneven portion formed on the (-100) surface, and
A first electrode formed on the surface of the support substrate opposite to the active layer,
It has a second electrode arranged on the upper layer of the second semiconductor layer and having a shape extending in a direction substantially parallel to the [011] direction and a direction substantially parallel to the [0-11] direction. ,
The second electrode is characterized in that the width A1 of the region extending in a direction substantially parallel to the [0-11] direction is larger than the width B1 of the region extending in the [011] direction.

In the present specification, "substantially parallel" in the direction D1 and the direction D2 means that the absolute value of the angle formed by the direction D1 and the direction D2 is less than 5 °.

When the light extraction surface is the (-100) plane and the infrared LED element is cut in a plane orthogonal to the (-100) plane, the direction in which the cross-sectional shape of the uneven portion becomes a forward mesa shape is [0-11]. ] Direction, and the direction orthogonal to this is the [011] direction.

As the most common method for forming an uneven portion on the light extraction surface of an LED element, a method of dipping in an acid-based etching solution without using a patterned mask is known (see Patent Document 3 above). .. However, the present inventors have repeatedly studied an etching solution capable of efficiently forming uneven portions on the light extraction surface side of the second semiconductor layer made of InP by such a method. It has been difficult to develop and obtain an etching solution capable of forming uneven portions in a stable and reproducible manner.

A dry etching method is known as another method for forming uneven portions on the surface of the layer. Using this method, the present inventors have studied the formation of uneven portions by patterning the light extraction surface of the second semiconductor layer made of InP with a resist mask by photolithography technology and dry etching. ..

However, if dry etching of the InP film is not performed while the wafer is heated, the etching rate will be slow and processing will be difficult. On the other hand, if dry etching is performed by heating, the shape of the resist that will be the patterning mask will collapse due to heat. Problems arise. Therefore, the present inventors considered that it is difficult to use this method in consideration of industrial mass productivity.

Therefore, the present inventors examined a method of etching with an etching solution containing hydrochloric acid in a state where the light extraction surface of the second semiconductor layer made of InP is patterned with a resist mask by a photolithography technique. Then, we succeeded in forming uneven portions on the light extraction surface of the second semiconductor layer in a stable and reproducible manner.

However, even when the uneven portion is formed by such a method, it has been confirmed that the effect of spreading the current in the surface direction is not sufficiently exhibited when the uneven portion is processed after the linear electrode is formed as described above.

Here, according to the diligent research by the present inventors, when etching is performed with an etching solution in a state where a patterned resist mask is provided on the light extraction surface, a specific direction is obtained with respect to the surface direction (horizontal direction). It was found that the etching progress rate is high in one direction and the etching progress rate is slow in the other direction. More specifically, it has been found that the etching progress rate in the [011] direction is faster than the etching progress rate in the [0-11] direction when the light extraction surface is the (-100) surface. ..

In the present specification and drawings, the negative sign "-" attached immediately before the number in parentheses indicating the Miller index indicates the inversion of the index. Further, in the present specification, the description "[011] direction" is a concept including the [011] direction and the [0-1-1] direction which is the direction in which the direction is reversed with respect to the [011] direction. is there. Similarly, the description "[0-11] direction" is a concept including the [0-11] direction and the [01-1] direction, which is the direction in which the direction is reversed with respect to the [0-11] direction. is there.

If the etching processing time is lengthened, the etching in the [011] direction proceeds rapidly, and as a result, the second semiconductor layer located directly below the electrode may be etched. In this case, the contact area between the linear electrode and the second semiconductor layer decreases, the resistance between the linear electrode and the semiconductor interface increases, and the amount of current injected from the linear electrode decreases. As a result, the effect of spreading the current in the plane direction is not sufficiently exhibited.

On the other hand, in order to suppress the etching of the semiconductor layer directly under the electrode, a method of stopping the etching process before the etching in the [011] direction proceeds more than necessary can be considered. In this case, [0] As a result of the etching not progressing so much in the -11] direction, it is not possible to form uneven portions at high density with respect to the light extraction surface.

On the other hand, according to the infrared LED element described above, with respect to the width of the second electrode constituting the linear electrode, the width A1 of the region extending in the direction substantially parallel to the [0-11] direction, that is, [ The width A1 in the [011] direction is formed to be larger than the width B1 of the region extending in the direction substantially parallel to the [011] direction, that is, the width B1 in the [0-11] direction. As a result, the etching progresses more in the [011] direction than in the [0-11] direction, and even if the second semiconductor layer directly under the second electrode is etched, the width of the second electrode in the same direction is wide. Since a large amount is secured, a sufficient contact area between the second electrode and the second semiconductor layer is secured. As a result, it is possible to suppress the situation in which the effect of expanding the current in the plane direction is not realized due to the increase in contact resistance.

When the infrared LED element is viewed from a direction orthogonal to the (-100) plane, the second semiconductor layer is substantially parallel to a side substantially parallel to the [0-11] direction and substantially parallel to the [011] direction. It may have a rectangular shape having parallel sides.

The LED element has a square or rectangular chip shape due to the process of cutting the LED element into an element shape from the wafer. According to the above configuration, since the side forming the chip and the stretching direction of the second electrode forming the linear electrode are parallel to each other, it becomes easy to spread the current in the plane direction and make the current density uniform.

Further, the uneven portion has a plurality of recesses formed on the (-100) surface of the second semiconductor layer, which are deeper in the depth direction orthogonal to the (-100) surface than the surroundings.
The recess has a length A2 in the [011] direction larger than a length B2 in the [0-11] direction.
The values of A1 / A2 and B1 / B2 may both be 1 or more and 6 or less.

When the values of A1 / A2 and B1 / B2 are small values less than 1, the second semiconductor layer directly under the second electrode is etched by etching, the second electrode is peeled off, and the contact resistance becomes extremely high. there is a possibility. On the other hand, the widths (A2, B2) of the concave portions forming the uneven portion are several μm or more due to the limit of the patterning ability by the photolithography method. Therefore, when the values of A1 / A2 and B1 / B2 exceed 6, the area of the second electrode becomes too large, and as a result, the area of the second electrode covering the light extraction surface becomes too wide. As a result, the light extraction efficiency is reduced.

The active layer contains In and P.
The main emission wavelength may be 1000 nm or more and less than 2000 nm.

The infrared LED element may have a reflective layer made of a conductive material that exhibits reflectivity to light emitted from the active layer between the support substrate and the first semiconductor layer.

According to such a configuration, the light emitted from the active layer to the support substrate side can be returned to the light extraction surface side, and the light extraction efficiency is improved.

According to the present invention, an infrared LED element capable of expanding the current in the plane direction while increasing the light extraction efficiency while increasing the light extraction efficiency is realized.

It is sectional drawing which shows typically the structure of one Embodiment of the infrared LED element of this invention. It is a top view which shows typically the structure of one Embodiment of the infrared LED element of this invention. It is an enlarged view of the region C1 in FIG. 2A. It is a photograph of the (-100) plane of the second semiconductor layer taken by a scanning electron microscope. It is a photograph of the cross section of the second semiconductor layer cut by the X1-X1 line in FIG. 3A taken by a scanning electron microscope. It is sectional drawing in one step for demonstrating the manufacturing method of the infrared LED element shown in FIG. It is sectional drawing in one step for demonstrating the manufacturing method of the infrared LED element shown in FIG. It is sectional drawing in one step for demonstrating the manufacturing method of the infrared LED element shown in FIG. It is sectional drawing in one step for demonstrating the manufacturing method of the infrared LED element shown in FIG. It is sectional drawing in one step for demonstrating the manufacturing method of the infrared LED element shown in FIG. It is sectional drawing in one step for demonstrating the manufacturing method of the infrared LED element shown in FIG. It is sectional drawing in one step for demonstrating the manufacturing method of the infrared LED element shown in FIG.

An embodiment of the infrared LED element according to the present invention will be described with reference to the drawings. The following drawings are schematically shown, and the dimensional ratios on the drawings do not always match the actual dimensional ratios. In addition, the dimensional ratios may not match between the drawings.

In the present specification, the description "GaInAsP" means that it is a mixed crystal of Ga, In, As and P, and the description of the composition ratio is simply omitted.

In the present specification, the expression "the layer B is formed on the upper layer of the layer A" means that the thin film is formed on the surface of the layer A as well as the case where the layer B is directly formed on the surface of the layer A. It is intended to include the case where the layer B is formed through the layer B. The term "thin film" as used herein may refer to a layer having a film thickness of 10 nm or less, preferably a layer having a film thickness of 5 nm or less.

[Construction]
FIG. 1 is a cross-sectional view schematically showing the structure of an embodiment of the infrared LED device of the present invention. The infrared LED element 1 includes a conductive support substrate 30, a reflection layer 5 arranged on the upper layer of the support substrate 30, a first semiconductor layer 7 arranged on the upper layer of the reflection layer 5, and a first semiconductor layer 7. The active layer 8 arranged on the upper layer and the second semiconductor layer 9 arranged on the upper layer of the active layer 8 are provided.

Further, the infrared LED element 1 shown in FIG. 1 has a first electrode 13 arranged on a surface of the support substrate 30 opposite to the active layer 8 and a second electrode formed on the upper surface of the second semiconductor layer 9. 11 and.

Further, the infrared LED element 1 shown in FIG. 1 includes a bonding layer 25, an insulating layer 21, and a contact electrode 23.

The infrared LED element 1 uses the second semiconductor layer 9 as a light extraction surface. More specifically, the (-100) surface of the second semiconductor layer 9 constitutes the light extraction surface. The details of each element will be described below.

(Support board 30)
The support substrate 30 is made of a conductive material, for example, Si, InP, Ge, GaAs, SiC, or CuW. Si is preferable from the viewpoint of heat exhaustability and manufacturing cost. The thickness of the support substrate 30, that is, the length related to the [-100] direction orthogonal to the (-100) plane is 50 μm or more and 500 μm or less, preferably 100 μm or more and 300 μm or less. .. As an example, the thickness of the support substrate 30 is 250 μm.

(Joint layer 25)
The bonding layer 25 is composed of, for example, Au, Au-Zn, Au-Sn, Au-In, Au-Cu-Sn, Cu-Sn, Pd-Sn, Sn and the like. As will be described later, the bonding layer 25 is used for bonding the wafer including the epitaxial layer formed on the growth substrate 20 described later and the support substrate 30.

(Reflective layer 5)
The reflective layer 5 is made of a material having high reflection characteristics with respect to infrared light emitted from the active layer 8 and having conductivity. As an example, the reflective layer 5 is made of a metal or alloy such as Al, Au, Ag, or Cu.

The reflective layer 5 is provided for the purpose of directing the light emitted from the active layer 8 and traveling toward the support substrate 30 toward the second semiconductor layer 9 side, which is the light extraction surface. That is, when the infrared LED element 1 includes the reflection layer 5, high light extraction efficiency is realized. However, in the present invention, it is arbitrary whether or not the infrared LED element 1 includes the reflective layer 5.

(Insulation layer 21, contact electrode 23)
In the infrared LED element 1 shown in FIG. 1, an insulating layer 21 is formed between the first semiconductor layer 7 and the reflective layer 5. The insulating layer 21 is made of a material having high transparency to infrared light, and is made of, for example, SiO ₂ , SiN, Al ₂ O _3, or the like.

The contact electrode 23 is formed so as to penetrate the insulating layer 21 and electrically connect the first semiconductor layer 7 and the reflective layer 5. The contact electrode 23 is composed of, for example, AuZn, AuBe, or a laminated structure containing at least Au and Zn (for example, Au / Zn / Au, etc.). The contact electrode 23 is preferably arranged at a position not facing the second electrode 11, which will be described later, in the [-100] direction. As a result, the current flowing through the active layer 8 is expanded in the plane direction, and the effect of increasing the luminous efficiency can be obtained.

However, it is optional whether the infrared LED element 1 includes the insulating layer 21 and the contact electrode 23.

(First semiconductor layer 7)
In the present embodiment, the first semiconductor layer 7 included in the infrared LED element 1 is a p-type semiconductor layer. The infrared LED element 1 shown in FIG. 1 includes a contact layer 7b and a clad layer 7a.

The contact layer 7b is made of, for example, a Zn-doped GaInAsP having a film thickness of 0.2 μm. The film thickness of the contact layer 7b is preferably 0.05 μm or more and 0.5 μm or less. The p-type dopant concentration of the contact layer 7b is preferably 5 × 10 ¹⁷ / cm ³ or more and 5 × 10 ¹⁸ / cm ³ or less, and more preferably 1 × 10 ¹⁸ / cm ³ or more and 3 × 10 ¹⁸ /. It is less than cm ^3.

The clad layer 7a is made of, for example, a Zn-doped InP having a film thickness of 3.55 μm. The film thickness of the clad layer 7a is preferably 0.5 μm or more and 7 μm or less, and more preferably 1 μm or more and 5 μm or less. The p-type dopant concentration of the clad layer 7a is preferably 1 × 10 ¹⁷ / cm ³ or more and 3 × 10 ¹⁸ / cm ³ or less, and more preferably 5 × 10 ¹⁷ / cm 3 or less at a position away from the active layer 8. It is cm ³ or more and 3 × 10 ¹⁸ / cm ³ or less.

As the p-type impurity material doped in the first semiconductor layer 7 (7a, 7b), Zn, Mg, Be and the like can be used, and Zn or Mg is preferable, and Zn is particularly preferable. The materials of the p-type dopant of the clad layer 7a and the p-type dopant of the contact layer 7b may be the same or different.

(Active layer 8)
The active layer 8 is composed of a material that produces infrared light having a main emission wavelength of 1000 nm or more and less than 2000 nm. More preferably, the active layer 8 is composed of a material that produces infrared light having a maximum peak wavelength of 1000 nm or more and less than 2000 nm.

The active layer 8 is appropriately selected from materials capable of generating light of a target wavelength and capable of epitaxial growth in lattice matching with a growth substrate 20 (more specifically, an InP substrate) described later. For example, the active layer 12 may have a single layer structure of GaInAsP, AlGaInAs, or InGaAs, or a well layer composed of GaInAsP, AlGaInAs, or InGaAs, and GaInAsP, AlGaInAs, InGaAs, or GaInAsP, which has a larger bandgap energy than the well layer. An MQW (Multiple Quantum Well) structure including a barrier layer made of InP may be used.

The active layer 8 may be doped in n-type or p-type, or may be undoped. When doped into an n-type, for example, Si can be used as the dopant.

When the active layer 8 has a single-layer structure, the film thickness of the active layer 8 is 100 nm or more and 2000 nm or less, preferably 500 nm or more and 1500 nm or less. When the active layer 8 has an MQW structure, a well layer having a film thickness of 5 nm or more and 20 nm or less and a barrier layer are laminated in a range of 2 cycles or more and 50 cycles or less.

As an example, the active layer 8 is composed of n-type GaInAsP having a film thickness of 900 nm.

(Second semiconductor layer 9)
In the present embodiment, the second semiconductor layer 9 included in the infrared LED element 1 is an n-type InP layer and constitutes an n-type clad layer. The n-type dopant concentration of the second semiconductor layer 9 is preferably 1 × 10 ¹⁷ / cm ³ or more and 5 × 10 ¹⁸ / cm ³ or less, and more preferably 5 × 10 ¹⁷ / cm ³ or more and 4 × 10 ^{It is 18} / cm ³ or less. As the n-type impurity material doped in the second semiconductor layer 9, Sn, Si, S, Ge, Se and the like can be used, and Si is particularly preferable.

The film thickness of the second semiconductor layer 9 is 1 μm or more and 30 μm or less, preferably 5 μm or more and 10 μm or less.

As will be described later, when n-type InP is used as the growth substrate 20, a part of the growth substrate 20 can also be used as the second semiconductor layer 9. In this case, the remaining growth substrate 20 can be regarded as a part of the second semiconductor layer 9. That is, the film thickness of the second semiconductor layer 9 described above includes the thickness of the remaining growth substrate 20.

(First electrode 13)
In this embodiment, the first electrode 13 corresponds to the p-side electrode. The first electrode 13 is formed on the side opposite to the active layer 8 of the support substrate 30, that is, on the back surface side.

Ohmic contact is realized with the first electrode 13 with respect to the support substrate 30. As an example, the first electrode 13 may be made of a material such as Ti / Au, and may include a plurality of these materials. In the present specification, the notation "X1 / X2" used when describing a material means that a layer made of X1 and a layer made of X2 are laminated.

(Second electrode 11)
In this embodiment, the second electrode 11 corresponds to the n-side electrode. The second electrode 11 is formed on the upper surface of the second semiconductor layer 9, and ohmic contact is realized with respect to the surface of the second semiconductor layer 9. As an example, the second electrode 11 is made of a material such as AuGe / Ni / Au, Pt / Ti, or Ge / Pt, and a plurality of these materials may be provided.

FIG. 2A is a schematic plan view of the infrared LED element 1 when viewed from the light extraction direction. Further, FIG. 2B is an enlarged view of the region C1 in FIG. 2A.

As shown in FIGS. 2A and 2B, the second electrode 11 has a shape extending linearly along a direction parallel to the rectangular side constituting the infrared LED element 1. More specifically, the second electrode 11 has a region 11a extending in a direction substantially parallel to the [0-11] direction and a region 11b extending in a direction substantially parallel to the [011] direction. ..

In the following, for the purpose of avoiding complexity, the description of "substantially parallel directions" is simply abbreviated as "parallel directions".

The width of the second electrode 11 related to the region 11a extending in the direction parallel to the [0-11] direction (that is, the width related to the [011] direction) A1 is the region 11b extending in the direction parallel to the [011] direction. (That is, the width related to the [0-11] direction) is larger than B1 (see FIG. 2B). With such a configuration, as will be described later, the contact area between the second electrode 11 and the second semiconductor layer 9 is secured even after the etching step for forming the uneven portion 9a, and the increase in contact resistance is suppressed.

Note that, as shown in FIG. 2A, a pad electrode 11p having a plane area larger than the surrounding area may be formed at a part of the second electrode 11. The pad electrode forms a region for connecting the bonding wire, and is composed of, for example, Ti / Au, Ti / Pt / Au, or the like.

In FIG. 2A, the second electrode 11 has one region 11a extending in a direction parallel to the [0-11] direction and four regions 11b extending in a direction parallel to the [011] direction. Is shown, but the number of each region is arbitrary.

(Concave and convex portion 9a)
As shown in FIG. 1, a concavo-convex portion 9a is formed on the light extraction surface side of the second semiconductor layer 9, that is, the (-100) surface. The shape of the uneven portion 9a will be described with reference to FIGS. 3A and 3B.

FIG. 3A is a photograph of the (-100) surface of the second semiconductor layer 9 taken with a scanning electron microscope. Further, FIG. 3B is a cross-sectional photograph of the second semiconductor layer 9, which corresponds to the photograph of the X1-X1 line cross section in FIG. 3A.

In the present embodiment, the uneven portions 9a are periodically arranged on the (-100) plane of the second semiconductor layer 9. More specifically, the uneven portion 9a has a concave portion 41 provided on the (-100) surface of the second semiconductor layer 9 and a region (convex portion 42) in which the concave portion 41 is not provided. These concave portions 41 and convex portions 42 are formed so as to be aligned in the [011] direction and the [-100] direction. However, in the present invention, it is arbitrary whether or not the uneven portion 9a is periodically arranged.

As shown in FIG. 3A, the recess 41 has a length A2 in the [011] direction larger than a length B2 in the [0-11] direction. As will be described later in the section of the manufacturing method, the uneven portion 9a is formed by wet etching using an etching solution with a resist mask patterned on the second semiconductor layer 9 made of InP. .. At this time, regarding the etching in the direction parallel to the (-100) plane, the etching proceeds fastest in the [011] direction, and the etching progresses slowly in the [0-11] direction orthogonal to the [011] direction. Therefore, when the uneven portion 9a is formed by wet etching described later, the recess 41 in which the length A2 in the [011] direction is larger than the length B2 in the [0-11] direction is formed in the second semiconductor layer 9. It is formed on the (-100) plane.

The ratio A1 / A2 of the width A1 of the second electrode 11 shown in FIG. 2B in the [011] direction and the length A2 of the recess 41 shown in FIG. 3A in the [011] direction is 1 or more and 6 or less. Is preferable. Similarly, the ratio B1 / B2 of the width B1 of the second electrode 11 shown in FIG. 2B in the [0-11] direction and the length B2 of the recess 41 shown in FIG. 3A in the [0-11] direction is also It is preferably 1 or more and 6 or less.

In the photograph shown in FIG. 3B, the cross-sectional shape of the uneven portion 9a has a forward mesa shape. In this way, the direction indicating the forward mesa shape is set to the [0-11] direction, and the direction orthogonal to this is set to the [011] direction.

[Production method]
An example of a method for manufacturing the infrared LED element 1 will be described with reference to the drawings of FIGS. 4A to 4G.

(Step S1)
As shown in FIG. 4A, the growth substrate 20 is prepared. As the growth substrate 20, for example, an InP substrate doped with n-type impurities at a dopant concentration of ^{1 × 10 17} / cm ³ or more and 3 × 10 ¹⁸ / cm ^{3 or less can be used.}

(Step S2)
As shown in FIG. 4A, the growth substrate 20 is conveyed into the MOCVD (Metal Organic Chemical Vapor Deposition) apparatus, and the second semiconductor layer 9, the active layer 8, and the first semiconductor layer are placed on the (100) plane of the growth substrate 20. 7 is sequentially epitaxially grown. In this step S2, the type and flow rate of the raw material gas, the treatment time, the environmental temperature, and the like are appropriately adjusted according to the material and film thickness of the layer to be grown. For example, trimethylindium (TMIn) is used as the In source, trimethylgallium (TMGa) is used as the Ga source, arsine (AsH ₃ ) is used as the As source, and phosphine (PH ₃ ) is used as the P source. Each layer is grown by supplying it together with the carrier gas.

Material examples of each semiconductor layer (9, 8, 7) are as described above. As an example, by this epitaxial growth step, a second semiconductor layer 9 made of Si-doped InP, an active layer 8 made of Si-doped GaInAsP, a clad layer 7a made of Zn-doped InP, and Zn are used. The first semiconductor layer 7 including the contact layer 7b made of GaInAsP doped with is obtained an epitaxial wafer formed on the growth substrate 20.

(Step S3)
The epitaxial wafer is taken out from the MOCVD apparatus, and an insulating layer 21 including an opening is formed on the surface of the second semiconductor layer 14 by using a resist mask patterned by a photolithography method. After that, a material for forming the contact electrode 23 is formed in the opening, and then an alloy treatment (annealing treatment) is performed by heat treatment at 450 ° C. for 10 minutes, so that the contact electrode 23 and the contact layer 7b are formed. Ohmic contact with is formed.

After that, the reflective layer 5 is formed on the upper layer of the insulating layer 21. The reflective layer 5 is formed by forming the above-mentioned metal or alloy material into a film by a general method such as a vapor deposition method.

(Step S4)
Next, as shown in FIG. 4C, after forming the bonding layer 25 on the upper layer of the reflective layer 5, the conductive support substrate 30 is bonded to the wafer via the bonding layer 25. For example, the bonding process is performed at a temperature of 280 ° C. and a pressure of 1 MPa.

Before forming the bonding layer 25, for example, a barrier metal layer made of Ti / Pt may be formed on the upper layer of the reflective layer 5. The barrier metal layer is provided for the purpose of suppressing deterioration of the reflection characteristics of the reflection layer 5 by diffusing the constituent materials of the bonding layer 25 toward the reflection layer 5.

Further, the bonding layer 25 may be formed in advance on the surface of the support substrate 30 to be bonded. In this case, a metal layer for contact (for example, Ti) may be formed on the surface of the support substrate 30, and a bonding layer 25 may be formed on the upper layer. At the time of bonding, the bonding layer 25 on the support substrate 30 and the bonding layer 25 on the growth substrate 20 are melted and integrated.

(Step S5)
As shown in FIG. 4D, a process of reducing the thickness of the growth substrate 20 is performed. This step is performed, for example, by performing a wet etching process with an etching solution containing hydrochloric acid.

In the above embodiment, since the growth substrate 20 is made of an n-type InP like the second semiconductor layer 9, the (-100) surface of the growth substrate 20 exposed after the completion of this step S5 is the light extraction surface. Configure. On the other hand, the growth substrate 20 may be completely peeled off, in which case the (-100) surface of the second semiconductor layer 9 exposed after the completion of step S5 constitutes the light extraction surface.

When the growth substrate 20 is made of an n-type InP as in the second semiconductor layer 9, it is technically meaningless to describe the second semiconductor layer 9 and the growth substrate 20 separately after this step. , The growth substrate 20 will also be described as a part of the second semiconductor layer 9.

(Step S6)
As shown in FIG. 4E, the second electrode 11 is formed in a predetermined region on the (-100) plane of the second semiconductor layer 9. For the second electrode 11, a material for forming the second electrode 11 (for example, AuGe / Ni / Au) is formed by using a vacuum deposition apparatus, and the second electrode 11 is formed.

In this step S6, as described above, the second electrode 11 is formed so as to extend in the direction parallel to the [0-11] direction and the direction parallel to the [011] direction. Further, at this time, the width A1 relating to the region 11a extending in the direction parallel to the [0-11] direction (that is, the width relating to the [011] direction) relates to the region 11b extending in the direction parallel to the [011] direction. The second electrode 11 is formed so as to be larger than the width (that is, the width related to the [0-11] direction) B1.

(Step S7)
As shown in FIG. 4F, a patterned resist mask 40 is formed on the upper surface of the second semiconductor layer 9. Then, as shown in FIG. 4G, the wafer in the state where the resist mask 40 is formed is subjected to a wet etching process using an etching solution containing hydrochloric acid. As a result, the etching solution permeates through the region where the resist mask 40 is not formed, that is, the second semiconductor layer 9 exposed from the opening, and the etching proceeds. As a result, the recess 41 is formed on the (-100) surface side of the second semiconductor layer 9.

As described above, in the second electrode 11 formed in step S6, the width A1 in the [011] direction is larger than the width B1 in the [0-11] direction. As a result, by the wet etching step in this step S7, the etching of the second semiconductor layer 9 proceeds in the [011] direction rather than the [0-11] direction, and the second semiconductor directly below the second electrode 11 Even if the layer 9 is etched, since the width of the second electrode 11 is formed thick in the same direction, a sufficient contact area between the second electrode 11 and the second semiconductor layer 9 can still be secured.

(Step S8)
After the resist mask 40 is peeled off, the first electrode 13 is formed on the back surface side of the support substrate 30. Specifically, a material for forming the first electrode 13 (for example, Ti / Au) is formed by using a vacuum vapor deposition apparatus, and the first electrode 13 is formed.

After that, a mesa etching process is performed to separate each element, and the infrared LED element 1 shown in FIG. 1 is formed.

[Another Embodiment]
Hereinafter, another embodiment will be described.

<1> In the above embodiment, the case where the concave-convex portion 9a formed on the (-100) surface of the second semiconductor layer 9 is periodic has been described, but the arrangement mode of the concave portion 41 and the convex portion 42 is not necessarily periodic. It does not have to have sex.

<2> In the above embodiment, the case where the growth substrate 20 is made of the same material as the second semiconductor layer 9 has been described, but a substrate made of a material different from that of the second semiconductor layer 9 may be used, and impurities are not doped. It may be a substrate. In these cases, the growth substrate is completely peeled off in step S5.

In this case, in step S2, the etching stopper layer may be formed on the upper surface of the growth substrate 20 before the growth of the second semiconductor layer 9. In this case, the etching can be stopped when the etching stopper layer is exposed in step S5. The etching stopper layer may have etching selectivity with respect to the growth substrate 20.

<3> In step S8, from a material having transparency to infrared light with respect to the (-100) surface of the second semiconductor layer 9 on which the uneven portion 9a is formed after the resist mask 40 is peeled off. It may form a dielectric layer. As the dielectric layer, for example, SiO ₂ , SiN, Al ₂ O _{3 and the} like can be used. Since the refractive index value of each of these materials is the value between InP and air, the effect of reducing the amount of light totally reflected on the active layer 8 side on the (-100) plane of the second semiconductor layer 9 is reduced. Is obtained.

<4> In the above embodiment, the stretching direction of the second electrode 11 and the side forming the wafer of the infrared LED element 1 have been described as being substantially parallel, but the present invention is not limited to this.

<5> In the above embodiment, the conductive type of the first semiconductor layer 7 and the second semiconductor layer 9 may be inverted. That is, in the infrared LED element 1 shown in FIG. 1, the first semiconductor layer 7 may be an n-type semiconductor layer and the second semiconductor layer 9 may be a p-type semiconductor layer.

1: Infrared LED element 5: Reflective layer 7: First semiconductor layer 7a: Clad layer 7b: Contact layer 8: Active layer 9: Second semiconductor layer 9a: Concavo-convex portion 11: Second electrode 11a: Region 11b: Region 11p : Pad electrode 12: Active layer 13: First electrode 14: Second semiconductor layer 20: Growth substrate 21: Insulation layer 23: Contact electrode 25: Bonding layer 30: Support substrate 40: Resist mask 41: Recessed portion 42: Convex portion

Claims (5)

Conductive support substrate and
A p-type or n-type first semiconductor layer arranged on the upper layer of the support substrate, and
It is composed of an active layer arranged on the upper layer of the first semiconductor layer and an InP arranged on the upper layer of the active layer and having a different conductive type from the first semiconductor layer, and is a surface opposite to the support substrate. A second semiconductor layer having an uneven portion formed on the (-100) surface, and
A first electrode formed on the surface of the support substrate opposite to the active layer,
It has a second electrode that is arranged on the upper layer of the second semiconductor layer and has a shape that extends in a direction substantially parallel to the [011] direction and substantially parallel to the [0-11] direction.
In the second electrode, the width A1 of the region extending in the direction substantially parallel to the [0-11] direction is larger than the width B1 of the region extending in the direction substantially parallel to the [011] direction. An infrared LED element characterized by. When viewed from a direction orthogonal to the (-100) plane, the second semiconductor layer has a side substantially parallel to the [0-11] direction and a side substantially parallel to the [011] direction. The infrared LED element according to claim 1, wherein the infrared LED element has a rectangular shape. The uneven portion is formed with a plurality of recesses formed on the (-100) plane of the second semiconductor layer, which are deeper in the depth direction orthogonal to the (-100) plane than the periphery.
The recess has a length A2 in the [011] direction larger than a length B2 in the [0-11] direction.
The infrared LED element according to claim 1, wherein the values of A1 / A2 and B1 / B2 are both 1 or more and 6 or less. The active layer contains In and P.
The infrared LED element according to claim 1, wherein the main emission wavelength is 1000 nm or more and less than 2000 nm. The infrared ray according to claim 1, wherein a reflective layer made of a conductive material exhibiting reflectivity to light emitted from the active layer is provided between the support substrate and the first semiconductor layer. LED element.

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