WO2021093002A1 - Array substrate, display panel and preparation method - Google Patents

Abstract

Provided are an array substrate (10), a display panel and a preparation method, wherein an inorganic insulating protective layer (13) of the array substrate (10) is located on a driving circuit layer (12), an organic insulating protective layer (14) is located on the inorganic insulating protective layer (13), the thickness of the organic insulating protective layer (14) in a cutting region (A1) and a test terminal setting region (A2) is less than the thickness of the organic insulating protective layer (14) in a display region (A3); and on the basis of the structure, when laser cutting is performed on the cutting region (A1) and a test terminal (122), the organic insulating protective layer (14) remains little or no residue.

Description

Array substrate, display panel and preparation method Technical field

This application relates to the field of display technology, and in particular to an array substrate, a display panel and a manufacturing method.

Background technique

In liquid crystal displays, in order to reduce the size of the bonding area on the array substrate and achieve the effect of achieving a larger display area, the flip-chip film bonding technology is generally used to combine the flexible circuit board with chip IC and the LCD panel array substrate (Array substrate) bonding terminal (bonding Lead) area binding to realize signal transmission. In order to improve the yield rate of the LCD screen and prevent defective products from flowing into the module or into the client, a lighting inspection is currently set in the module stage, and various mode signals are input to check the display function defects.

In order to improve the detection rate, shorting bar (shorting bar, hereinafter referred to as test terminal) is generally used for human eye inspection. The shorting bar area is connected to the bonding lead area and is set in the peripheral area of the panel. After the inspection is completed, the shorting Bar and related circuits are laser cut to prevent the signal transmission of the actual product from being affected.

The current liquid crystal display technology is a flat Array substrate topography, which improves post-process photoresist coating characteristics, while providing improved contrast, lower parasitic capacitance, etc., using organic insulating films (PFA, Polymer Film on Array) to replace traditional SiNx films or SiOx films, etc. The inorganic insulating film serves as an insulating protective layer.

Since the organic insulating film has high light transmittance and low light and heat absorption, there are problems such as laser cutting residue.

technical problem

The present application provides an array substrate, a display panel, and a manufacturing method, so as to alleviate the technical problem of laser cutting residual of organic insulating film in the prior art.

Technical solutions

To solve the above problems, the technical solutions provided by this application are as follows:

An embodiment of the present application provides an array substrate, which includes:

Substrate

The driving circuit layer is located on the substrate and forms a thin film transistor, a binding terminal and a test terminal;

An inorganic insulating protective layer located on the driving circuit layer;

The organic insulating protective layer is located on the inorganic insulating protective layer;

Wherein, the thickness of the organic insulating protection layer in the cutting area and the test terminal setting area is smaller than the thickness of the organic insulating protection layer in the display area.

In the array substrate provided by the embodiment of the present application, the material of the organic insulating protective layer includes an organic insulating film.

In the array substrate provided by the embodiment of the present application, the array substrate forms a groove in the cutting area, and the groove penetrates the organic insulating protective layer.

In the array substrate provided by the embodiment of the present application, the groove penetrates the inorganic insulating protective layer.

In the array substrate provided by the embodiment of the present application, the array substrate includes a gate insulating layer, and the groove penetrates the gate insulating layer.

In the array substrate provided by the embodiment of the present application, the organic insulating protective layer is hollowed out in the test terminal arrangement area.

In the array substrate provided by the embodiment of the present application, the organic insulating protective layer and the inorganic insulating protective layer are hollowed out in the test terminal arrangement area.

At the same time, an embodiment of the present application provides a display panel, which includes: a first substrate;

The second substrate is arranged opposite to the first substrate;

Wherein, the first substrate includes: a substrate; a driving circuit layer, located on the substrate, forming thin film transistors, binding terminals, and test terminals; an inorganic insulating protection layer, located on the driving circuit layer; organic insulation protection The thickness of the organic insulating protective layer in the cutting area and the test terminal setting area is smaller than the thickness of the organic insulating protective layer in the display area.

In the display panel provided by the embodiment of the present application, the first substrate further includes a color resist layer, and the color resist layer is located between the inorganic insulating protective layer and the organic insulating protective layer.

In the display panel provided by the embodiment of the present application, the first substrate further includes: a pixel electrode layer located on the organic insulating protective layer.

In the display panel provided by the embodiment of the present application, the material of the pixel electrode layer is indium tin oxide.

In the display panel provided by the embodiment of the present application, the first substrate further includes: an alignment film layer located on the pixel electrode layer.

In the display panel provided by the embodiment of the present application, the driving circuit layer includes an active layer, an insulating layer, a gate layer, a gate insulating layer, a source and drain layer, and the gate layer is patterned to form the test terminal .

In the display panel provided by the embodiment of the present application, the material of the organic insulating protective layer includes an organic insulating film.

In the display panel provided by the embodiment of the present application, the array substrate forms a groove in the cutting area, and the groove is at least partially formed in the organic insulating protective layer.

In the display panel provided by the embodiment of the present application, the array substrate forms a groove in the cutting area, and the groove penetrates the organic insulating protective layer.

In the display panel provided by the embodiment of the present application, the groove penetrates the organic insulating protective layer and is at least partially formed in the inorganic insulating protective layer.

In the display panel provided by the embodiment of the present application, the groove penetrates the inorganic insulating protective layer.

Further, an embodiment of the present application provides a method for manufacturing a display panel, which includes:

Provide substrate;

Preparing a driving circuit layer on the substrate; the driving circuit layer forms a thin film transistor, a binding terminal, and a test terminal;

Preparing an inorganic insulating protective layer on the driving circuit layer;

Preparing an organic insulating protective layer on the inorganic insulating protective layer;

The organic insulating protective layer is processed so that the thickness of the organic insulating protective layer in the cutting area and the test terminal setting area is smaller than the thickness of the organic insulating protective layer in the display area.

In the method for manufacturing the display panel provided by the embodiment of the present application, the step of processing the organic insulating protective layer includes:

Using one of a slit mask, a semi-shielding and semi-transmitting mask, or a full-transmitting mask to thin the organic insulating protective layer;

The organic insulating protective layer after the thinning treatment is etched.

Beneficial effect

The present application provides an array substrate, a display panel, and a manufacturing method. The array substrate includes a substrate, a driving circuit layer is located on the substrate, a thin film transistor, a binding terminal, and a test terminal are formed, and an inorganic insulating protective layer is located on the driving circuit. On the circuit layer, the organic insulating protective layer is located on the inorganic insulating protective layer, and the thickness of the organic insulating protective layer in the cutting area and the test terminal setting area is smaller than the thickness of the organic insulating protective layer in the display area; based on this structure After completing the module lighting test, when laser cutting the cutting area and the test terminal, there is little or no residue of the organic insulating protective layer, which alleviates the technical problem of the laser cutting residual of the organic insulating film in the prior art, and ensures Static resistance of subsequent modules.

Description of the drawings

In order to explain the embodiments or the technical solutions in the prior art more clearly, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are merely inventions. For some embodiments, those of ordinary skill in the art can obtain other drawings based on these drawings without creative work.

FIG. 1 is a top view of an array substrate provided by an embodiment of the application.

FIG. 2 is a first cross-sectional schematic diagram of an array substrate provided by an embodiment of the application.

FIG. 3 is a schematic cross-sectional view of a second type of the array substrate provided by an embodiment of the application.

FIG. 4 is a third schematic cross-sectional view of the array substrate provided by the embodiment of the application.

FIG. 5 is a schematic diagram of a fourth cross-sectional view of an array substrate provided by an embodiment of the application.

FIG. 6 is a flowchart of a method for manufacturing a display panel provided by an embodiment of the application.

7 to 9 are schematic diagrams of the manufacturing process of the display panel provided by the embodiments of the application.

Embodiments of the present invention

The description of the following embodiments refers to the attached drawings to illustrate specific embodiments that can be implemented in the present application. The directional terms mentioned in this application, such as [Top], [Bottom], [Front], [Back], [Left], [Right], [Inner], [Outer], [Side], etc., are for reference only The direction of the additional schema. Therefore, the directional terms used are used to illustrate and understand the application, rather than to limit the application. In the figure, units with similar structures are indicated by the same reference numerals.

In view of the existing technical problems of the laser cutting residual of the organic insulating film in the prior art, the embodiments of the present application can alleviate.

In an embodiment, as shown in FIGS. 1 to 5, the array substrate 10 provided by the embodiment of the present application includes:

Substrate 11;

The driving circuit layer 12 is located on the substrate 11 and forms a thin film transistor, a bonding terminal 121 and a test terminal 122; the bonding terminal 121 is formed in the bonding area A4, and the test terminal 122 is formed in the test terminal setting area A2; A pole layer M1 and a gate insulating layer M2, and the gate layer M1 is patterned to form a binding terminal 121 and a test terminal 122;

The inorganic insulating protective layer 13 is located on the driving circuit layer 12;

The organic insulating protective layer 14 is located on the inorganic insulating protective layer 13;

Wherein, the thickness of the organic insulating protection layer 14 in the cutting area A1 and the test terminal setting area A2 is smaller than the thickness of the organic insulating protection layer in the display area A3.

This embodiment provides an array substrate. The array substrate includes a substrate, a driving circuit layer is located on the substrate, and a thin film transistor, a bonding terminal, and a test terminal are formed. The inorganic insulating protective layer is located on the driving circuit layer, and the organic The insulating protective layer is located on the inorganic insulating protective layer. The thickness of the organic insulating protective layer in the cutting area and the test terminal setting area is smaller than the thickness of the organic insulating protective layer in the display area; based on this structure, the module is completed After the lighting test, when laser cutting the cutting area and the test terminal, there is little or no residue of the organic insulating protective layer, which alleviates the technical problem of the laser cutting residual of the organic insulating film in the prior art, and ensures the durability of the subsequent modules Electrostatic ability.

In an embodiment, the driving circuit layer 12 includes an active layer, an insulating layer, a gate layer M1, a gate insulating layer M2, a source-drain layer, and the like. The gate layer M1 is patterned to form test terminals.

In an embodiment, the material of the organic insulating protective layer 14 includes an organic insulating film.

In an embodiment, the array substrate forms a groove C in the cutting area A1, and the groove C is at least partially formed in the organic insulating protective layer 14.

In an embodiment, as shown in (1) of FIG. 2, the array substrate forms a groove C in the cutting area A1, and the groove C penetrates the organic insulating protective layer 14.

In one embodiment, the groove C penetrates the organic insulating protective layer 14 and is at least partially formed in the inorganic insulating protective layer 13.

In an embodiment, as shown in (2) of FIG. 2, the groove C penetrates the inorganic insulating protective layer 13.

In one embodiment, the groove C penetrates the organic insulating protective layer 14 and the inorganic insulating protective layer 13 and is at least partially formed in the gate insulating layer.

In an embodiment, as shown in (3) of FIG. 2, the array substrate includes a gate insulating layer M2, and the groove penetrates the gate insulating layer M2.

In an embodiment, as shown in FIG. 3, the thickness of the organic insulating protective layer 14 in the test terminal setting area is smaller than the thickness of the inorganic insulating protective layer 13 in the test terminal setting area.

In an embodiment, as shown in FIG. 4, the organic insulating protective layer 14 is hollowed out in the test terminal arrangement area.

In an embodiment, as shown in FIG. 5, the organic insulating protective layer 14 and the inorganic insulating protective layer 13 are hollowed out in the test terminal setting area.

In an embodiment, the display panel provided by the embodiment of the present application includes:

First substrate

The second substrate is arranged opposite to the first substrate;

Wherein, the first substrate includes:

Substrate

The driving circuit layer is located on the substrate and forms a thin film transistor, a binding terminal and a test terminal;

An inorganic insulating protective layer located on the driving circuit layer;

The organic insulating protective layer is located on the inorganic insulating protective layer;

Wherein, the thickness of the organic insulating protection layer in the cutting area and the test terminal setting area is smaller than the thickness of the organic insulating protection layer in the display area.

This embodiment provides a display panel. The first substrate of the display panel includes a substrate, a driving circuit layer is located on the substrate, and a thin film transistor, a bonding terminal, and a test terminal are formed. The inorganic insulating protective layer is located on the driving circuit. On the layer, the organic insulating protective layer is located on the inorganic insulating protective layer, and the thickness of the organic insulating protective layer in the cutting area and the test terminal setting area is smaller than the thickness of the organic insulating protective layer in the display area; based on this structure, After completing the module lighting test, when laser cutting the cutting area and the test terminal, there is little or no residue of the organic insulating protective layer, which alleviates the technical problem of the laser cutting residual of the organic insulating film in the prior art, and ensures the follow-up The electrostatic resistance of the module.

In an embodiment, the first substrate further includes: a color resist layer, and the color resist layer is located between the inorganic insulating protective layer and the organic insulating protective layer.

In an embodiment, the first substrate further includes: a pixel electrode layer located on the organic insulating protective layer.

In an embodiment, the material of the pixel electrode layer is a transparent material such as indium tin oxide.

In an embodiment, the first substrate further includes: an alignment film layer located on the pixel electrode layer.

In an embodiment, the driving circuit layer includes an active layer, an insulating layer, a gate layer M1, a gate insulating layer M2, a source and drain layer, etc., and the gate layer M1 is patterned to form a test terminal.

In an embodiment, the material of the organic insulating protective layer includes an organic insulating film.

In an embodiment, the array substrate forms a groove C in the cutting area A1, and the groove C is at least partially formed in the organic insulating protective layer.

In an embodiment, the array substrate forms a groove C in the cutting area A1, and the groove C penetrates the organic insulating protective layer.

In one embodiment, the groove C penetrates the organic insulating protective layer and is at least partially formed in the inorganic insulating protective layer.

In an embodiment, the groove C penetrates the inorganic insulating protective layer.

In one embodiment, the groove C penetrates the organic insulating protective layer and the inorganic insulating protective layer, and is at least partially formed in the gate insulating layer.

In an embodiment, the array substrate includes a gate insulating layer M2, and the groove penetrates the gate insulating layer M2.

In an embodiment, the thickness of the organic insulating protection layer in the test terminal setting area is smaller than the thickness of the inorganic insulating protection layer in the test terminal setting area.

In an embodiment, the organic insulating protective layer is hollowed out in the test terminal setting area.

In an embodiment, the organic insulating protective layer and the inorganic insulating protective layer are hollowed out in the test terminal arrangement area.

In an embodiment, the pixel electrode formed by patterning the pixel electrode layer includes:

The backbone of the pixel electrode divides a sub-pixel into at least two display domains;

At least two pixel electrode branches extending in different directions from the pixel electrode backbone in each display domain;

Wherein, in at least two display domains, the angle between the pixel electrode branch and the trunk of the same pixel electrode is different.

This embodiment provides a liquid crystal display panel. The pixel electrode of the liquid crystal display panel is divided into at least two display domains, and in the at least two display domains, the angles between the pixel electrode branches and the same pixel electrode backbone are different, so different The oblique electric field generated by the display domain can induce the liquid crystal molecules in different display domains to tilt in different directions to improve the color shift, and the angle between the pixel electrode branches and the same pixel electrode backbone in at least two display domains is different. Providing inclined electric fields with different included angles increases the diversity of liquid crystal rotation and lodging, further improves off-axis color shift, and alleviates the technical problem of color shift that occurs under large viewing angles in current vertical alignment liquid crystal display panels.

In an embodiment, a plurality of pixel electrode branches in one display domain are parallel to each other and spaced apart from each other, and the extension directions of the pixel electrode branches in two adjacent display domains are different.

In an embodiment, the pixel electrode backbone of the pixel electrode includes:

The backbone of the first pixel electrode;

The second pixel electrode backbone is arranged to intersect the first pixel electrode backbone;

The second pixel electrode backbone cooperates with the first pixel electrode backbone to divide the sub-pixels into a first display domain, a second display domain, a third display domain, and a fourth display domain distributed in a counterclockwise direction;

Wherein, the first included angle between the pixel electrode branch in the first display domain and the first pixel electrode backbone ranges from 35 to 45 degrees, and the pixel electrode branch in the third display domain is connected to the first pixel electrode. The range of the third included angle of the backbone is 45 to 55 degrees.

In an embodiment, the backbone of the first pixel electrode is perpendicular to the scan line and parallel to the data line.

In an embodiment, the second pixel electrode backbone is perpendicular to the data line and parallel to the scan line, that is, the second pixel electrode backbone is perpendicular to the first pixel electrode backbone.

In an embodiment, the first pixel electrode backbone passes through the midpoint of the second pixel electrode backbone.

In an embodiment, the second pixel electrode backbone passes through the midpoint of the first pixel electrode backbone.

In an embodiment, the second included angle between the pixel electrode branch in the second display domain and the trunk of the first pixel electrode is the same as the first included angle; the pixel electrode in the fourth display domain The fourth included angle between the branch and the trunk of the first pixel electrode is the same as the third included angle.

In an embodiment, the first included angle is 45 degrees, and the third included angle is 55 degrees.

In an embodiment, the second included angle between the pixel electrode branch in the second display domain and the trunk of the first pixel electrode is the same as the third included angle; the pixel electrode in the fourth display domain The fourth included angle between the branch and the trunk of the first pixel electrode is the same as the first included angle.

In an embodiment, the pixel electrode further includes:

The first closed frame connecting the ends of all the pixel electrode branches and the trunk of the pixel electrode;

At least one second closed frame sleeved on the periphery of the first closed frame and connected to the pixel electrode backbone;

The first closed frame and the second closed frame are separated from each other, and a new display domain is formed between the two; the liquid crystal molecules in the new display domain can form an orientation polar angle different from that of the liquid crystal molecules in other domains, thereby enabling further Improve the viewing angle of liquid crystal display panels in low and medium gray scales.

The pixel electrode provided in this embodiment is provided with a first closed frame connecting the ends of all pixel electrode branches and the main stem of the pixel electrode, and at least one second closed frame sleeved on the periphery of the first closed frame and connected to the main stem. The first closed frame and the second closed frame make the fringe electric field of the pixel electrode regular, so that the orientation of the liquid crystal molecules located at the edge of the sub-pixel is more uniform, can eliminate the dark lines on the periphery of the sub-pixel, and improve the optics Transmittance; in addition, a new display domain is formed between the first closed frame and the second closed frame, which can further improve the viewing angle of the liquid crystal display panel in low and medium gray levels.

In an embodiment, the shapes of the first closed frame and the second closed frame are both rectangular, and the two form a "back"-shaped structure.

In an embodiment, as shown in FIG. 6, the manufacturing method of the display panel provided in the embodiment of the present application includes the following steps:

S601: Provide substrate;

S602: preparing a driving circuit layer on the substrate; the driving circuit layer forms a thin film transistor, a binding terminal, and a test terminal;

S603: preparing an inorganic insulating protective layer on the driving circuit layer;

S604: preparing an organic insulating protective layer on the inorganic insulating protective layer;

S605: Process the organic insulating protective layer so that the thickness of the organic insulating protective layer in the cutting area and the test terminal setting area is smaller than the thickness of the organic insulating protective layer in the display area.

In an embodiment, step S605 includes:

Using one of a slit mask, a semi-shielding and semi-transmitting mask, or a full-transmitting mask to thin the organic insulating protective layer;

The organic insulating protective layer after the thinning treatment is etched.

The method provided in this application will be further described in conjunction with specific embodiments.

As shown in Figure 7, the preparation method provided by this application includes the following steps:

Step 7-1: Pre-process substrate preparation, use the Normal process to make M1→GI→AS→M2→PV1→RGB (COA process, non-COA process substrates can also be used), and the result shown in Figure 7 (1) The front substrate includes a test terminal formed by patterning the gate layer M1, a gate insulating layer M2, and an inorganic insulating protective layer M3.

Step 7-2: Prepare the organic insulating protective layer M4 on the front substrate, and use the slit mask shown in Figure 7 (2), as shown in Figure 7 (3), in the laser cutting area and the test terminal In the setting area, exposure processing is performed on the front substrate.

Step 7-3: As shown in Figure 7 (4), the organic insulating protective layer M4 is coated, exposed, developed, and Oven post-processed to obtain a thinned organic insulating protective layer M4.

In the laser cutting area and the test terminal setting area, the thickness of the organic insulating protective layer M4 is 1%-100% thinner than the display area. For example, the thickness of the organic insulating protective layer M4 in the display area is 1.5um, and a slit mask with a slit of 1/1.7 can be used to reduce the thickness to 0.5~0.8um, or a slit mask with a slit of 1/2.1 , It can be thinned to 0.4~0.6um, or adopt a slit mask design with different slits of 1/1.7 and different numbers with slits of 1/2.1. In an embodiment, the thickness of the organic insulating protective layer M4 is 0.7 um after being thinned.

Step 7-4: As shown in Figure 7 (5), the thinned organic insulating protective layer M4 is further etched, for example, the organic insulating protective layer M4 is completely etched, and the thickness of the etched film at this time is 0.7um .

After the above-mentioned manufacturing process is completed, subsequent preparation of pixel electrodes and alignment film layers is performed to obtain an array substrate, and then the assembly with the color filter substrate is completed to obtain a display panel. The assembled display panel will be subjected to a module manufacturing process to complete the preparation of the display panel.

As shown in Figure 8, the preparation method provided by this application includes the following steps:

Step 8-1: Pre-process substrate preparation, use the Normal process to make M1→GI→AS→M2→PV1→RGB (COA process, non-COA process substrates can also be used), and get as shown in Figure 8 (1) The front substrate includes a test terminal formed by patterning the gate layer M1, a gate insulating layer M2, and an inorganic insulating protective layer M3.

Step 8-2: Prepare the organic insulating protective layer M4 on the front substrate, and use the fully transparent cover as shown in Figure 8 (2), as shown in Figure 8 (3), in the laser cutting area and the test terminal In the setting area, exposure processing is performed on the front substrate.

Step 8-3: As shown in Figure 8 (4), the organic insulating protective layer M4 is coated, exposed, developed, and Oven post-processing, and the organic insulating protective layer M4 is completely removed.

Step 8-4: As shown in FIG. 8 (5), the substrate after the organic insulating protective layer M4 is removed is further etched, for example, the inorganic insulating protective layer M3 is completely etched.

After the above-mentioned manufacturing process is completed, subsequent preparation of pixel electrodes and alignment film layers is performed to obtain an array substrate, and then the assembly with the color filter substrate is completed to obtain a display panel. The assembled display panel will be subjected to a module manufacturing process to complete the preparation of the display panel.

As shown in Figure 9, the preparation method provided by this application includes the following steps:

Step 9-1: Pre-process substrate preparation, use the Normal process to make M1→GI→AS→M2→PV1→RGB (COA process, non-COA process substrates can also be used), and the result shown in Figure 9 (1) The front substrate includes a test terminal formed by patterning the gate layer M1, a gate insulating layer M2, and an inorganic insulating protective layer M3.

Step 9-2: Prepare the organic insulating protective layer M4 on the front substrate, and use the semi-shielding and semi-transmissive cover shown in Figure 9 (2), as shown in Figure 9 (3), in the laser cutting area and In the test terminal setting area, the front substrate is exposed to light.

Step 9-3: As shown in Figure 9 (4), the organic insulating protective layer M4 is coated, exposed, developed, and Oven post-processed to obtain a thinned organic insulating protective layer M4.

In an embodiment, the thickness of the organic insulating protective layer M4 is 0.7 um after being thinned.

Step 9-4: As shown in Figure 9 (5), the thinned organic insulating protective layer M4 is further etched, for example, the organic insulating protective layer M4 is completely etched, and the thickness of the etched film at this time is 0.6um .

After the above-mentioned manufacturing process is completed, subsequent preparation of pixel electrodes and alignment film layers is performed to obtain an array substrate, and then the assembly with the color filter substrate is completed to obtain a display panel. The assembled display panel will be subjected to a module manufacturing process to complete the preparation of the display panel.

According to the above embodiment, it can be seen that:

The embodiments of the present application provide an array substrate, a display panel, and a manufacturing method. The array substrate includes a substrate, a driving circuit layer is located on the substrate, a thin film transistor, a bonding terminal, and a test terminal are formed, and the inorganic insulating protective layer is located on the substrate. On the drive circuit layer, an organic insulating protective layer is located on the inorganic insulating protective layer, and the thickness of the organic insulating protective layer in the cutting area and the test terminal setting area is smaller than the thickness of the organic insulating protective layer in the display area; With this structure, after completing the module lighting test, when laser cutting the cutting area and the test terminal, the organic insulating protective layer has little or no residue, which alleviates the technical problem of the laser cutting residual of the organic insulating film in the prior art. Ensure the electrostatic resistance of subsequent modules.

In summary, although the application has been disclosed as above in preferred embodiments, the above-mentioned preferred embodiments are not intended to limit the application. Those of ordinary skill in the art can make various decisions without departing from the spirit and scope of the application. Such changes and modifications, so the protection scope of this application is subject to the scope defined by the claims.

Claims (20)

An array substrate, which includes: Substrate The driving circuit layer is located on the substrate and forms a thin film transistor, a binding terminal and a test terminal; An inorganic insulating protective layer located on the driving circuit layer; The organic insulating protective layer is located on the inorganic insulating protective layer; Wherein, the thickness of the organic insulating protection layer in the cutting area and the test terminal setting area is smaller than the thickness of the organic insulating protection layer in the display area. The array substrate according to claim 1, wherein the material of the organic insulating protective layer includes an organic insulating film. 3. The array substrate according to claim 1, wherein the array substrate forms a groove in the cutting area, and the groove penetrates the organic insulating protective layer. 4. The array substrate of claim 3, wherein the groove penetrates the inorganic insulating protective layer. 4. The array substrate according to claim 4, wherein the array substrate comprises a gate insulating layer, and the groove penetrates the gate insulating layer. 4. The array substrate according to claim 1, wherein the organic insulating protective layer is hollowed out in the test terminal arrangement area. 7. The array substrate according to claim 6, wherein the organic insulating protective layer and the inorganic insulating protective layer are hollowed out in the test terminal arrangement area. A display panel, which includes: First substrate The second substrate is arranged opposite to the first substrate; Wherein, the first substrate includes: a substrate; a driving circuit layer, located on the substrate, forming thin film transistors, binding terminals, and test terminals; an inorganic insulating protection layer, located on the driving circuit layer; organic insulation protection The thickness of the organic insulating protective layer in the cutting area and the test terminal setting area is smaller than the thickness of the organic insulating protective layer in the display area. 8. The display panel of claim 8, wherein the first substrate further comprises a color resist layer, the color resist layer being located between the inorganic insulating protective layer and the organic insulating protective layer. 8. The display panel according to claim 8, wherein the first substrate further comprises: a pixel electrode layer on the organic insulating protective layer. 8. The display panel according to claim 8, wherein the material of the pixel electrode layer is indium tin oxide. 8. The display panel according to claim 8, wherein the first substrate further comprises: an alignment film layer located on the pixel electrode layer. 8. The display panel according to claim 8, wherein the driving circuit layer comprises an active layer, an insulating layer, a gate layer, a gate insulating layer, a source and drain layer, and the gate layer is patterned to form the test Terminal. 8. The display panel according to claim 8, wherein the material of the organic insulating protective layer includes an organic insulating film. 8. The display panel of claim 8, wherein the array substrate forms a groove in the cutting area, and the groove is at least partially formed in the organic insulating protective layer. 8. The display panel according to claim 8, wherein the array substrate forms a groove in the cutting area, and the groove penetrates the organic insulating protective layer. 16. The display panel of claim 16, wherein the groove penetrates the organic insulating protective layer and is at least partially formed in the inorganic insulating protective layer. 18. The display panel of claim 17, wherein the groove penetrates the inorganic insulating protective layer. A method for preparing a display panel includes: Provide substrate; Preparing a driving circuit layer on the substrate; the driving circuit layer forms a thin film transistor, a binding terminal, and a test terminal; Preparing an inorganic insulating protective layer on the driving circuit layer; Preparing an organic insulating protective layer on the inorganic insulating protective layer; The organic insulating protective layer is processed so that the thickness of the organic insulating protective layer in the cutting area and the test terminal setting area is smaller than the thickness of the organic insulating protective layer in the display area. 18. The method for manufacturing a display panel according to claim 19, wherein the step of processing the organic insulating protective layer comprises: Using one of a slit mask, a semi-shielding and semi-transmitting mask, or a full-transmitting mask to thin the organic insulating protective layer; The organic insulating protective layer after the thinning treatment is etched.