WO2020189718A1 - Semiconductor device - Google Patents

Abstract

The present invention addresses the problem of providing a feature capable of preventing the disconnection of gate wiring of a thin-film transistor. This semiconductor device has: a base insulating film having a first step; a semiconductor layer having a second step and provided on the base insulating film; a gate insulating film which is provided on the base insulating film and the semiconductor layer, and has a third step reflecting the first step and a fourth step reflecting the second step; and a gate electrode provided on the gate insulating film so as to cover the third and fourth steps.

Description

Semiconductor device

The present invention relates to a semiconductor device, and more particularly to a semiconductor device such as a display device having a thin film transistor using an oxide semiconductor.

A technique for preventing breakage of wiring has been proposed (for example, Japanese Patent Application Laid-Open No. 2007-142382).

JP-A-2007-142382

Paragraph 0053 of JP-A-2007-142382 states that "the first wiring layer 106a of the portion on which the third wiring layer 109 is superimposed is larger than the wiring width of the second wiring layer 107a formed on the first wiring layer 106a. It is widely provided, and by providing it widely in this way, it is possible to prevent the third wiring layer 109 from being cut off. "

In a semiconductor device such as a display device having a thin film transistor (OSTFT) using an oxide semiconductor layer (OS), the gate wiring is formed by a step (taper) of the oxide semiconductor layer at a portion of the gate wiring over the oxide semiconductor layer. It may be cut off. Since the etching of the oxide semiconductor layer is wet etching, it is difficult to control the taper angle. When the gate length (L) of the thin film transistor (OSTFT) is shortened, the characteristics of the thin film transistor (OSTFT) may be poor or the gate wiring of the thin film transistor (OSTFT) may be broken.

An object of the present invention is to provide a technique capable of preventing disconnection of the gate wiring of a thin film transistor.

Other issues and new features will become apparent from the description and accompanying drawings herein.

The outline of a typical one of the present invention is as follows.

That is, according to one aspect, the semiconductor device includes a base insulating film having a first step, a semiconductor layer provided on the base insulating film and having a second step, the base insulating film and the semiconductor. A gate insulating film provided above the layer and having a third step reflecting the second step and a fourth step reflecting the first step, and the third step. And a gate electrode provided on the gate insulating film so as to cover the fourth step.

Further, according to one aspect, the semiconductor device has an underlying insulating film, a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer includes a bottom surface, a first surface, and a first side surface provided between the bottom surface and the first surface, and the first side surface has a first taper angle with respect to the bottom surface. Has. The underlying insulating film includes a second surface, a third surface, and a second side surface provided between the second surface and the third surface, and the second side surface is formed on the second surface. On the other hand, the semiconductor layer has a second taper angle, and the semiconductor layer is provided on the base insulating film so that the bottom surface of the semiconductor layer is provided on the second surface of the base insulating film. The gate insulating film is provided on the underlying insulating film and the semiconductor layer, and is provided on a fourth surface, a fifth surface provided above the fourth surface, and above the fifth surface. Includes a sixth surface, a third side surface provided between the fourth surface and the fifth surface, and a fourth side surface provided between the fifth surface and the sixth surface. .. The third side surface has the second taper angle with respect to the fourth surface, and the fourth side surface has the first taper angle with respect to the fourth surface. The gate electrode is formed on the fourth surface, the third side surface, the fifth surface, the fourth side surface, and the sixth surface of the gate insulating film.

FIG. 1 is a plan view showing the appearance of the display device according to the first embodiment. FIG. 2 is a cross-sectional view taken along the line AA of FIG. FIG. 3 is a diagram showing a basic configuration of pixels and an equivalent circuit of a display device. FIG. 4 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment. FIG. 5 is a plan view showing a configuration example of the layout of the thin film transistor OSTFT of FIG. FIG. 6 is a cross-sectional view taken along the line BB of FIG. FIG. 7 is a cross-sectional view taken along the line CC of FIG. FIG. 8 is a plan view showing a configuration example of the layout of the thin film transistor OSTFT according to the comparative example. FIG. 9 is a cross-sectional view taken along the line BB of FIG. FIG. 10 is a diagram illustrating a parameter including a pseudo taper angle. FIG. 11 is a graph showing the relationship between the pseudo-taper angle, the amount of receding of the second semiconductor layer, and the taper angle of the second semiconductor layer. FIG. 12 is a cross-sectional view showing a step of selectively forming a second semiconductor layer on the second insulating film. FIG. 13 is a cross-sectional view showing a step of forming a metal layer constituting a protective metal layer on the second insulating film and the second semiconductor layer and dry-etching the metal layer. FIG. 14 is a cross-sectional view showing a step of performing a wet etching treatment using hydrofluoric acid on the second semiconductor layer. FIG. 15 is a cross-sectional view showing a step of forming a second gate insulating film on the second insulating film and the second semiconductor layer. FIG. 16 is a cross-sectional view showing a step of selectively forming the second gate electrode on the second gate insulating film. FIG. 17 is a cross-sectional view showing a step of forming the third insulating film and the fourth insulating film on the second gate electrode and the second gate insulating film. FIG. 18 is a diagram for explaining a main part of the thin film transistor LTPSTFT of FIG. 4, and is a cross-sectional view of the thin film transistor LTPSTFT along the extending direction of the first gate electrode. FIG. 19 is a diagram for explaining a main part of the thin film transistor LTPSTFT of FIG. 4, and is a cross-sectional view of the thin film transistor LTPSTFT along a direction perpendicular to the extending direction of the first gate electrode. FIG. 20 is a cross-sectional view showing a step of performing a dry etching process on the first semiconductor layer. FIG. 21 is a cross-sectional view showing a step of performing an ashing treatment on the resist film. FIG. 22 is a cross-sectional view showing a step of performing a dry etching process on the first semiconductor layer again. FIG. 23 is a cross-sectional view showing a step of forming a first gate oxide film on the base film and the first semiconductor layer. FIG. 24 is a cross-sectional view showing a step of selectively forming the first gate electrode on the first gate oxide film. FIG. 25 is a cross-sectional view showing a step of forming the first insulating film and the second insulating film on the first gate oxide film and the first gate electrode. FIG. 26 is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment. FIG. 27 is a plan view showing a configuration example of the layout of the thin film transistor OSTFT of FIG. FIG. 28 is a cross-sectional view taken along the line DD of FIG. 27. FIG. 29 is a cross-sectional view taken along the line EE of FIG. 27. FIG. 30 is a cross-sectional view showing a step of performing a wet etching process on the semiconductor layer using an oxalic acid-based etching solution. FIG. 31 is a cross-sectional view showing a step of performing a dry etching process on the base film. FIG. 32 is a cross-sectional view showing a step of performing a wet etching process on the semiconductor layer again using an oxalic acid-based etching solution. FIG. 33 is a cross-sectional view showing a step of forming a gate insulating film on the base film and the semiconductor layer. FIG. 34 is a cross-sectional view showing a step of selectively forming a gate electrode on the gate insulating film. FIG. 35 is a cross-sectional view showing a step of forming a first insulating film and a second insulating film on the gate electrode and the gate insulating film. FIG. 36 is a cross-sectional view showing a step of selectively forming a resist film on a semiconductor layer. FIG. 37 is a cross-sectional view showing a step of performing a wet etching treatment using buffered hydrofluoric acid (BHF) on the base film and the semiconductor layer. FIG. 38 is a cross-sectional view showing a step of forming a gate insulating film on the base film and the semiconductor layer.

Hereinafter, each embodiment of the present invention will be described with reference to the drawings.

It should be noted that the disclosure is merely an example, and those skilled in the art can easily conceive of appropriate changes while maintaining the gist of the invention are naturally included in the scope of the present invention. Further, in order to clarify the explanation, the drawings may schematically represent the width, thickness, shape, etc. of each part as compared with the actual embodiment, but this is just an example, and the interpretation of the present invention is used. It is not limited.

Further, in the present specification and each figure, the same elements as those described above with respect to the existing figures may be designated by the same reference numerals, and detailed description thereof may be omitted as appropriate.

In this embodiment, a liquid crystal display device is disclosed as an example of the display device. This liquid crystal display device can be used in various devices such as smartphones, tablet terminals, mobile phone terminals, personal computers, television receivers, in-vehicle devices, and game devices.

In the present specification and claims, the expressions such as "upper" and "lower" in the description of the drawings express the relative positional relationship between the structure of interest and other structures. There is. Specifically, when viewed from the side surface, the direction from the first substrate (array substrate) to the second substrate (opposing substrate) is defined as "upper", and the opposite direction is defined as "lower".

In addition, "inside" and "outside" indicate the relative positional relationship between the two parts with respect to the display area. That is, the "inside" refers to the side relatively close to the display area with respect to one part, and the "outside" refers to the side relatively far from the display area with respect to one part. However, the definitions of "inside" and "outside" referred to here shall be in the state where the liquid crystal display device is not bent.

"Display device" refers to all display devices that display images using a display panel. The "display panel" refers to a structure that displays an image using an electro-optical layer. For example, the term display panel may refer to a display cell that includes an electro-optical layer, or refers to a structure in which another optical member (for example, a polarizing member, a backlight, a touch panel, etc.) is attached to the display cell. In some cases. Here, the "electro-optical layer" may include a liquid crystal layer, an electrochromic (EC) layer, and the like as long as technical contradiction does not occur. Therefore, although the embodiment described later will be described by exemplifying a liquid crystal panel including a liquid crystal layer as a display panel, the application to the display panel including the other electro-optical layer described above is not excluded.

(Embodiment 1)
(Example of overall configuration of display device)
FIG. 1 is a plan view showing the appearance of the display device according to the first embodiment. FIG. 2 is a cross-sectional view taken along the line AA of FIG.

In FIGS. 1 and 2, the display device DSP includes a display panel PNL, a flexible printed circuit board 1, an IC chip 2, and a circuit board 3. The display panel PNL is a liquid crystal display panel and includes a first substrate (also referred to as a TFT substrate or an array substrate) SUB1, a second substrate (also referred to as an opposing substrate) SUB2, a liquid crystal layer LC, and a sealing material SE. ing.

The display panel PNL includes a display unit (display area) DA for displaying an image and a frame-shaped non-display unit (non-display area) NDA that surrounds the outer circumference of the display unit DA. The second substrate SUB2 faces the first substrate SUB1. The first substrate SUB1 has a mounting portion MA extending in the second direction Y from the second substrate SUB2. The sealing material SE is located in the non-display portion NDA, adheres the first substrate SUB1 and the second substrate SUB2, and seals the liquid crystal layer LC.

With reference to FIG. 2, a lower polarizing plate 200 is attached below the first substrate SUB1, and an upper polarizing plate 201 is attached above the second substrate SUB2. The combination of the first substrate SUB1, the second substrate SUB2, the lower polarizing plate 200, the upper polarizing plate 201, and the liquid crystal layer LC is called a display panel PNL. Since the display panel PNL does not emit light by itself, the backlight 202 is arranged on the back surface.

A plurality of external terminals are formed on the mounting unit MA. The flexible wiring board 1 is connected to the plurality of external terminals of the mounting unit MA. A driver IC 2 for supplying a video signal or the like is mounted on the flexible wiring board 1. A circuit board 3 for supplying signals and electric power from the outside to the driver IC 2 and the display device DSP is connected to the flexible wiring board 1. The IC chip 2 may be mounted on the mounting unit MA. The IC chip 2 has a built-in display driver DD that outputs a signal necessary for displaying an image in a display mode for displaying an image.

As shown in FIG. 1, a plurality of pixel PXs are formed in a matrix in the display area DA, and each pixel PX has a thin film transistor (TFT: Thin Film Transistor) as a switching element. A drive circuit for controlling and driving scanning lines, video signal lines, and the like is formed in the non-display area NDA. The drive circuit has a thin film transistor (TFT).

The TFT used as the switching element of the pixel PX needs to have a small leakage current. A TFT made of an oxide semiconductor can reduce the leakage current. Hereinafter, the oxide semiconductor will be referred to as an OS (Oxide Semiconductor). The OS includes IGZO (Indium Gallium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), ZnON (Zinc Oxide Nitride), IGO (Indium Galium Oxide), and the like. Hereinafter, the oxide semiconductor will be described as a representative of the OS. Since the mobility of the carrier of the OS is small, it may be difficult to form the drive circuit built in the display device DSP by the TFT using the OS.

On the other hand, LTPS (Low Temperature Poly-Si) has high mobility, and is therefore suitable as a TFT that constitutes a drive circuit. In liquid crystal display devices, LTPS is often used for polycrystalline silicon (Poly-Si) in which polycrystalline silicon is continuous. Therefore, Poly-Si will also be referred to as LTPS below. Since the TFT formed by LTPS has high mobility, the drive circuit can be formed by a thin film transistor (TFT) using LTPS. Hereinafter, LTPS will also be used in the meaning of TFT using LTPS.

That is, since the thin film transistor (TFT) used for the pixel PX needs to have a small leakage current, an oxide semiconductor (OS) must be used and the thin film transistor (TFT) used for the drive circuit needs to have high mobility. Therefore, it is rational to use TFTS.

However, depending on the applicable product, it may be possible to design with amorphous silicon (a-Si) or the mobility of the OS, so the configuration of the present invention is also effective when a-Si or OS is used for the drive circuit. is there.

The display panel PNL of the present embodiment is a transmissive type having a transmissive display function for displaying an image by selectively transmitting light from the back side of the first substrate SUB1, and light from the front side of the second substrate SUB2. It may be either a reflection type having a reflection display function for displaying an image by selectively reflecting the light, or a semitransparent type having a transmission display function and a reflection display function.

Further, although the detailed configuration of the display panel PNL will be omitted here, the display panel PNL also has a display mode using a vertical electric field along the normal of the main surface of the substrate, and is oblique to the main surface of the substrate. Any configuration corresponding to a display mode using a gradient electric field inclined in the direction and a display mode using the above-mentioned lateral electric field, longitudinal electric field, and gradient electric field in an appropriate combination may be provided. The substrate main surface here is a surface parallel to the XY plane defined by the first direction X and the second direction Y.

(Example of circuit configuration of display device)
FIG. 3 is a diagram showing a basic configuration of a pixel PX and an equivalent circuit of a display device DSP. A plurality of pixels PX are arranged in a matrix in the first direction X and the second direction Y. A plurality of scanning lines G (G1, G2 ...) Are connected to the scanning line driving circuit GD. A plurality of signal lines S (S1, S2 ...) Are connected to the signal line drive circuit SD. A plurality of common electrodes CE (CE1, CE2 ...) Are connected to a voltage supply unit CD of a common voltage (Vcom) and are arranged over a plurality of pixels PX. One pixel PX is connected to one scanning line, one signal line, and one common electrode CE. The scanning line G and the signal line S do not necessarily have to extend linearly, and a part of them may be bent. For example, it is assumed that the signal line S extends in the second direction Y even if a part of the signal line S is bent. The scanning line drive circuit GD, the signal line drive circuit SD, and the voltage supply unit CD are composed of a thin film transistor (TFT).

Each pixel PX includes a switching element SW, a pixel electrode PE, a common electrode CE, a liquid crystal layer LC, and the like. The switching element SW is composed of, for example, a thin film transistor (TFT), and is electrically connected to the scanning line G and the signal line S. The scanning line G is connected to the switching element SW in each of the pixels PX arranged in the first direction X. The signal line S is connected to the switching element SW in each of the pixels PX arranged in the second direction Y. The pixel electrode PE is electrically connected to the switching element SW. Each of the pixel electrode PEs faces the common electrode CE, and the liquid crystal layer LC is driven by the electric field generated between the pixel electrode PE and the common electrode CE. The holding capacitance CS is formed, for example, between an electrode having the same potential as the common electrode CE and an electrode having the same potential as the pixel electrode PE.

(Example of thin film transistor configuration)
FIG. 4 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment. The semiconductor device 10 shown in FIG. 4 is a first substrate SUB1 provided with a plurality of thin film transistors TFT1 and TFT2. In FIG. 4, the thin film transistor TFT1 on the left side is a thin film transistor using LTPS (hereinafter, also referred to as LTPSTFT), and the thin film transistor TFT2 on the right side is a thin film transistor using an oxide semiconductor (OS) (hereinafter, also referred to as OSTFT). The semiconductor device 10 is a semiconductor device built in the display panel.

The semiconductor device 10 includes a substrate 100, an undercoat film 101, a first semiconductor layer 102, a first gate insulating film 104, a first gate electrode 105, a light-shielding layer 106, a first insulating film 107, a second insulating film 108, and a second semiconductor. It includes a layer 109, a second gate insulating film 112, a second gate electrode 116, a third insulating film 117, a fourth insulating film 118, and the like.

In FIG. 4, the base film 101 is formed on the substrate 100 made of glass or resin. The base film 101 blocks impurities from glass and the like, and is usually formed of silicon oxide SiO or silicon nitride SiN by CVD. Therefore, the base film 101 can be regarded as a base insulating film. In addition, the notation of AB (example: SiO) and the like in this specification indicates that it is a compound containing A and B as constituent elements, respectively, and means that A and B have the same composition ratio, respectively. Not.

A first semiconductor layer 102 for LTPSTFT is formed on the base film 101. The first semiconductor layer 102 is made of LTPS. The first gate insulating film 104 is formed so as to cover the first semiconductor layer 102. The first semiconductor layer 102, for example, forms amorphous silicon (a-Si), is annealed for dehydrogenation, and then is irradiated with an excima laser to convert a-Si into polycrystalline silicon (Poly-). It is possible to convert to Si) and then pattern and form Poly-Si. The first gate insulating film 104 can be formed by SiO made of TEOS (Tetraethyl orthosilicate) as a raw material.

The first gate electrode 105 and the light-shielding layer 106 are formed on the first gate insulating film 104. The first gate electrode 105 and the light-shielding layer 106 are formed of a laminated film of Ti—Al alloy—Ti or the like, or a MoW alloy or the like. The light-shielding layer 106 is for shielding the channel region 1091 of the OSTFT from being irradiated with the light from the backlight 202.

The first insulating film 107 is formed so as to cover the first gate electrode 105, the light-shielding layer 106, and the first gate insulating film 104. The first insulating film 107 is formed of SiN by CVD. A second insulating film 108 is formed on the first insulating film 107. The second insulating film 108 is formed of SiO by CVD.

A second semiconductor layer 109 for the OSTFT is formed on the second insulating film 108. The second semiconductor layer 109 is formed of an OS. The second semiconductor layer 109 includes a channel region 1091, a drain region or source region 1092, and a source region or drain region 1093 (hereinafter, the drain region or source region 1092 is used as a drain region, and the source region or drain region 1093 is used. Described as a source area). The channel region 1091 is provided between the drain region 1092 and the source region 1093. The thin film transistor TFT 2 is located above the thin film transistor TFT 1 when viewed from the substrate 100.

A protective metal layer 111 is provided at one end and the other end of the second semiconductor layer 109. That is, the metal layer 111 is connected to the end of the drain region 1092 that is not in contact with the channel region 1091 and the end of the source region 1093 that is not in contact with the channel region 1091. The metal layer 111 is made of, for example, titanium (Ti).

The second gate insulating film 112 is formed so as to cover the second insulating film 108, the second semiconductor layer 109, and the metal layer 111. The second gate insulating film 112 can be formed by CVD by CVD using SiH4 (silane) and N2O (nitrous oxide).

The second gate electrode 116 is formed on the second gate insulating film 112 corresponding to the channel region 1091. The second gate electrode 116 is formed of, for example, a laminated film of Ti—Al alloy—Ti or the like, or a Mo, MoW alloy or the like.

A third insulating film 117 is formed so as to cover the second gate insulating film 112 and the second gate electrode 116. The third insulating film 117 is made of SiN. A fourth insulating film 118 is formed on the third insulating film 117. The fourth insulating film 118 is formed of SiO.

After that, the contact hole 120 for forming the gate electrode wiring 1191 and the source / drain electrode wiring 1192 is formed in the LTPSTFT, and the contact hole 122 for forming the gate electrode wiring 1211 and the source / drain electrode wiring 1212 is formed in the OSTFT. The contact holes 120 and 122 are formed by dry etching using, for example, a CF-based (for example, CF4) or CHF-based (for example, CHF3) gas. On the LTPSTFT side, the contact hole 120 is formed in the five-layer insulating film and the six-layer insulating film, and on the OSTFT side, the contact hole 122 is formed in the two-layer insulating film and the three-layer insulating film. Then, the contact holes 120 and 122 are cleaned with an HF-based cleaning liquid, and after cleaning, the gate electrode wiring 1191, the source / drain electrode wiring 1192, the gate electrode wiring 1211 and the source / drain electrode wiring 1212 are formed. In this specification, the source / drain electrode wiring (1192, 1212) is the source / drain electrode wiring (1192, 1212) by combining the source electrode wiring and the drain electrode wiring. The gate electrode wirings 1191 and 1211 and the source and drain electrode wirings 1192 and 1212 can be formed of, for example, a laminated film of Ti, Al alloy, Ti or the like.

As shown in FIG. 4, on the LTPSTFT side, the five-layer insulating film (118, 117, 112, 108, 107) and the six-layer insulating film (118, 117, 112, 108, 107, 104) are contacted. While the holes 120 are formed, on the OSTFT side, the contact holes 122 are formed in the two-layer insulating film (118, 117) and the three-layer insulating film (118, 117, 112). Therefore, the etching conditions for forming the contact hole need to be adjusted to the LTPSTFT side. That is, the OSTFT side is exposed to the etching gas and the cleaning liquid for a longer period of time, but by providing the protective metal layer 111, the disappearance of the second semiconductor layer 109 can be prevented and the OSTFT can be stably formed.

(Structure example of thin film transistor OSTFT)
FIG. 5 is a plan view showing a configuration example of the layout of the thin film transistor OSTFT of FIG. FIG. 6 is a cross-sectional view taken along the line BB of FIG. FIG. 7 is a cross-sectional view taken along the line CC of FIG.

As shown in FIG. 5, the second gate electrode 116, which is the gate electrode of the thin film transistor OSTFT (TFT2), is arranged so as to extend along the X direction in a plan view, and is arranged on the upper side of the second semiconductor layer 109. It is passing. In the portion where the second gate electrode 116 and the second semiconductor layer 109 overlap, the length of the second gate electrode 116 along the Y direction can be regarded as the gate length L of the thin film transistor OSTFT (TFT2). The gate length L is, for example, about 3 μm. As described with reference to FIG. 4, a metal layer 111 is provided at the end of the drain region 1092 and the end of the source region 1093, respectively.

As shown in FIG. 6, the second insulating film 108 has two steps (first steps) 108a on the left and right sides of the drawing, and the second semiconductor layer 109 has a predetermined angle (first step) in cross-sectional view. It is provided on the region 108b of the second insulating film 108 raised by the step 108a having a slope having a two taper angle θ2). Both ends of the second semiconductor layer 109 have a step (second step) 109a having a slope having a predetermined angle (first taper angle θ1) in a cross-sectional view. In this case, the film thickness of the second semiconductor layer 109 does not change, but the end portion is conveniently referred to as a step. The second gate insulating film 112 has a step (third step) 112a and a step (fourth step) 112b. The taper angles θ1 and θ2 will be described later (see FIG. 10). The step may be rephrased as a step portion.

The steps 112a and 112b formed on the second gate insulating film 112 reflect the steps 108a of the second insulating film 108 and the steps 109a of the second semiconductor layer 109. Therefore, the second gate electrode 116 formed on the second gate insulating film 112 is formed on the steps 112a and 112b in the second gate insulating film 112 at the overcoming portion of the second semiconductor layer 109. Therefore, the taper angle of the second gate insulating film 112 at the overcoming portion of the second semiconductor layer 109 is relaxed, so that the second gate electrode 116 does not break. The film thickness of the second semiconductor layer 109 is, for example, about 50 nm. The film thickness of the second gate insulating film 112 is, for example, about 100 nm. The film thickness of the second gate electrode 116 is, for example, about 250 nm.

As shown in FIG. 7, the metal layer 111 is provided so as to cover the steps 109a at both ends of the second semiconductor layer 109. The metal layer 111 has a step 111a at one end of the metal layer 111 and a step 111b at the other end of the metal layer 111. The step 111a is provided between the step 108a and the step 109a. The step 111b is provided between the step 109a and the channel region 1091. The second gate insulating film 112 has steps 112a, 112b, and 112c. The steps 112a, 112b and 112c reflect the steps 108a, 111a and 111b.

(Comparison example)
A comparative example will be described with reference to FIGS. 8 and 9. FIG. 8 is a plan view showing a configuration example of the layout of the thin film transistor OSTFT according to the comparative example. FIG. 9 is a cross-sectional view taken along the line BB of FIG. In the comparative example, as shown in FIG. 9, the second insulating film 108r is not provided with the step 108a described in FIG. That is, the second semiconductor layer 109 is provided on the flat second insulating film 108r without steps, and the second gate insulating film 112r is provided on the second insulating film 108r and so as to cover the second semiconductor layer 109. Be done. Therefore, the second gate insulating film 112r is provided with a step 112b that reflects the step 109a of the second semiconductor layer 109. Then, the second gate electrode 116r is selectively formed on the second gate insulating film 112r.

Since the etching of the second semiconductor layer 109 is wet etching, it is difficult to control the taper angle of the step 109a. When the shape of the taper angle of the step 109a deteriorates, the shape of the taper angle of the step 112b deteriorates, and as a result, the second gate electrode 116r has a recess (recess) 116r1 in the cross-sectional view as shown in FIG. It may occur. Further, as shown in FIG. 8, in a plan view, a recess (neck) 116r2 may be generated in the second gate electrode 116r.

The recess (recess) 116r1 and the recess (constriction) 116r2 may lead to step breakage of the second gate electrode 116r and poor characteristics of the thin film transistor OSTFT. For example, when the gate length L shown in FIG. 8 is shortened, if a recess (constriction) 116r2 is generated in the second gate electrode 116r, the second gate electrode 116r may be disconnected. When the taper angle of the step 112b is, for example, 34 degrees or 42 degrees, a recess (recess) 116r1 or a recess (constriction) 116r2 may occur in the second gate electrode 116r.

(Example of examination of each parameter)
An example of examining the parameters will be described with reference to FIGS. 10 and 11. FIG. 10 is a diagram illustrating a parameter including a pseudo taper angle. FIG. 11 is a graph showing the relationship between the pseudo taper angle, the amount of receding of the second semiconductor layer (OS), and the taper angle of the second semiconductor layer (OS). First, each parameter will be described with reference to FIG.

The film thickness of the second semiconductor layer (OS) 109 is t1, and the amount of scraping (etching amount) of the second insulating film 108 is t2. The taper angle of the step 109a of the second semiconductor layer (OS) 109 is the first taper angle θ1, and the taper angle of the step 108a of the second insulating film 108 is the second taper angle θ2. The retreat amount x of the second semiconductor layer (OS) 109 is the length between the apex portion 108ah of the step 108a of the second insulating film 108 and the lower end portion 109ab of the step 109a of the second semiconductor layer (OS) 109. .. The retreat amount y of the second semiconductor layer (OS) 109 is the length between the lower end portion 109ab and the apex portion 109ah of the step 109a of the second semiconductor layer (OS) 109.

The taper angle of the step 112a of the second gate insulating film 112 is substantially the same as the second taper angle θ2 of the step 108a, and the taper angle of the step 112b of the second gate insulating film 112 is the first taper angle θ1 of the step 109a. It is almost the same value as. The height of the step 112b is substantially the same as the film thickness t1 of the second semiconductor layer (OS) 109, and the height of the step 112a is the amount of scraping (etching amount) t2 of the second insulating film 108. It is almost the same value.

Here, the pseudo taper angle θ0 is defined. The pseudo-taper angle θ0 is the angle (or inclination from the horizontal) between the thick wire LL connecting the apex portion 112ah of the step 112a and the apex portion 112bh of the step 112b and the lowermost surface 112s1 of the second gate insulating film 112. Angle). The taper angle θ1 and the taper angle θ2 can be defined as the inclination of the side surface or side wall forming the target step (for example, step 109a, step 108a) from the horizontal. Alternatively, the taper angle θ1 and the taper angle θ2 can be defined as the inclination of the side surface or the side wall of the target layer or film (for example, the second semiconductor layer (OS) 109, the second insulating film 108) from the horizontal. ..

Here, the thickness t1 of the second semiconductor layer (OS) and the second semiconductor layer (OS) so that the value of the pseudo-taper angle θ0 is 30 degrees or less (θ0 <30 degrees) in the following equation 1. The first taper angle θ1 and the receding amount x of the second semiconductor layer (OS) 109 are adjusted.

θ0 = tan ^-1 (t1 / ((t1 / tan θ1) + x)) (Equation 1)
FIG. 11 is a graph in which Equation 1 is plotted. When the film thickness t1 of the second semiconductor layer (OS) 109 is 50 nm, the pseudo-taper angle θ0 and the retreat amount x of the second semiconductor layer (OS) 109. The correlation with the first taper angle θ1 of the second semiconductor layer (OS) is shown. In FIG. 11, the value of the pseudo taper angle θ0 when the retreat amount x of the second semiconductor layer (OS) 109 and the first taper angle θ1 of the second semiconductor layer (OS) are changed is shown. The first taper angle θ1 is changed to 15 degrees, 30 degrees, 45 degrees, 60 degrees, 75 degrees, and 90 degrees.

An example of an experiment carried out by the present inventors will be briefly described.
Experimental Example 1: In FIG. 9, when the taper angle θ1 of the step 109a is 39 degrees and the taper angle of the step 112b is 34 degrees, the occurrence of a recess (constriction) is confirmed in the second gate electrode 116r. The film thickness of the second semiconductor layer (OS) 109 was 52.5 nm.
Experimental Example 2: In FIG. 6, when the first taper angle θ1 of the step 109a is 50 degrees and the pseudo taper angle θ0 is 24 degrees, the second gate electrode 116 has no recess (constriction). .. The film thickness of the second semiconductor layer (OS) 109 was 55.7 nm.
Experimental Example 3: In FIG. 6, when the first taper angle θ1 of the step 109a is 48 degrees and the pseudo taper angle θ0 is 22 degrees, the second gate electrode 116 has no recess (constriction). .. The film thickness of the second semiconductor layer (OS) 109 was 49 nm.
Experimental Example 4: In FIG. 6, when the first taper angle θ1 of the step 109a is 45 degrees and the pseudo taper angle θ0 is 22 degrees, the second gate electrode 116 has no recess (constriction). .. The film thickness of the second semiconductor layer (OS) 109 was 49 nm.

The following items can be considered from the above experimental examples 1-4. In Experimental Example 1 in which a concave portion (constriction) was generated, the taper angle of the step 112b was 34 degrees, whereas in Experimental Example 2-4 in which the concave portion (constriction) was improved, the pseudo taper angle θ0 was 22 degrees or more. It was 24 degrees, which was lower than the taper angle (34 degrees) of the step 112b in Experimental Example 1. From this, it was found that the pseudo-taper angle θ0 is preferably 30 degrees or less.

The examination results of the present inventors are summarized below.
1) It is desirable that the pseudo-taper angle θ0 is 30 degrees or less (θ0 <30 degrees).
2) The first taper angle θ1 of the second semiconductor layer (OS) 109 and the second taper angle θ2 of the insulating film 108 are forward taper (θ1 <90 degrees, θ2 <90 degrees) and the pseudo taper angle θ0 or more (θ0). It is desirable that <θ1, θ0 <θ2).
3) It is desirable that the scraping amount t2 of the second insulating film 108 is within ± 50% of the film thickness t1 of the second semiconductor layer (OS) 109.

By setting the above 1) to 3), it is possible to suppress the occurrence of recesses (dents) and recesses (constrictions) in the second gate electrode 116. Therefore, it is possible to prevent poor characteristics of the thin film transistor (OSTFT) and disconnection of the gate wiring of the thin film transistor (OSTFT).

The configuration shown in FIG. 10 may be paraphrased as follows.

The semiconductor layer 109 includes a bottom surface 109 s, a first surface 109 s, and a first side surface 109 ss provided between the bottom surface 109 s and the first surface 109 s, and the first side surface 109 ss is a first surface with respect to the bottom surface 109 s. It has one taper angle θ1.

The second insulating film (underlayer insulating film) 108 includes a second surface 108s1, a third surface 108s2, and a second side surface 108ss provided between the second surface 108s1 and the third surface 108s2. The second side surface 108ss has a second taper angle θ2 with respect to the second surface 108s1. The semiconductor layer 109 is provided on the third surface 108s2 of the second insulating film 108 so that the bottom surface 109bs of the semiconductor layer 109 is provided on the second surface 108s1 of the second insulating film (underlayer insulating film) 108. Has been done.

The gate insulating film 112 is provided on the second insulating film (underlayer insulating film) 108 and the semiconductor layer 109, and has a fourth surface 112s1 and a fifth surface 112s2 provided above the fourth surface 112s1. Between the sixth surface 112s3 provided above the fifth surface 112s2, the third side surface 112ss1 provided between the fourth surface 112s1 and the fifth surface 112s2, and the fifth surface 112s2 and the sixth surface 112s3. Includes a fourth side surface 112ss2 provided. The third side surface 112ss1 has a second taper angle θ2 with respect to the fourth surface 112s1, and the fourth side surface 112ss2 has a first taper angle θ1 with respect to the fifth surface 112s2.

The gate electrode 116 is formed on the fourth surface 112s1, the third side surface 112ss1, the fifth surface 112s2, the fourth side surface 112ss2, and the sixth surface 112s3 of the gate insulating film 112.

When the intersection of the third side surface 112ss1 and the fifth surface 112s2 is the first intersection 112ah and the intersection of the fourth side surface 112ss2 and the sixth surface 112s3 is the second intersection 112bh, the first intersection 112ah and the second intersection 112bh The angle between the line LL connecting between them and the fourth surface 112s1 is defined as a pseudo-taper angle θ0.

(Manufacturing method of semiconductor device 1)
Next, an example of a method of manufacturing a semiconductor device in the display device DSP will be described with reference to FIGS. 12 to 17. In the following method of manufacturing a semiconductor device, a method of manufacturing a thin film transistor (OSTFT), which is a main part, will be mainly described. Therefore, in FIG. 4, the process described in FIG. 12 is performed from the state in which the gate electrode 105 of the thin film transistor TFT1 is formed and then the semiconductor substrate on which the first insulating film 107 and the second insulating film 108 are formed is prepared. It shall be started.

FIG. 12 is a cross-sectional view showing a process of selectively forming the second semiconductor layer 109 on the second insulating film 108. The second semiconductor layer 109 is formed of an oxide semiconductor layer (OS). The film thickness of the second semiconductor layer 109 is relatively thick at this point. That is, in FIG. 14, which will be described later, since the second semiconductor layer 109 is subjected to a wet etching process using hydrofluoric acid (HF), the film thickness of the second semiconductor layer 109 is formed to be relatively thick.

FIG. 13 shows a step of forming a metal layer 111d constituting a protective metal layer 111 (see FIG. 4) on the second insulating film 108 and the second semiconductor layer 109 and dry-etching the metal layer 111d. It is sectional drawing which shows. When the metal layer 111d is dry-etched, both the second insulating film 108 and the second semiconductor layer 109 are etched. Since both ends of the second insulating film 108 not covered by the second semiconductor layer 109 are scraped by the dry etching process, steps (second taper angle θ2) having a predetermined angle (second taper angle θ2) are formed on both ends of the second insulating film 108. 1 step) 108a is formed. The amount of scraping (etching amount) of the second insulating film 108 corresponds to the scraping amount (etching amount) t2 of the second insulating film 108 in FIG.

FIG. 14 is a cross-sectional view showing a step of performing a wet etching treatment using hydrofluoric acid (HF) on the second semiconductor layer 109. By the wet etching process, the film thickness of the second semiconductor layer 109 is set to, for example, about 50 nm, and both ends of the second semiconductor layer 109 are also etched in the lateral direction. As a result, a step (second step) 109a having a predetermined angle (first taper angle θ1) is formed at both ends of the second semiconductor layer 109. The amount of etching at both ends of the second semiconductor layer 109 in the lateral direction corresponds to the amount of retreat x of the second semiconductor layer (OS) 109 in FIG.

FIG. 15 is a cross-sectional view showing a process of forming the second gate insulating film 112 on the second insulating film 108 and the second semiconductor layer 109. When the second gate insulating film 112 is formed on the second insulating film 108 and the second semiconductor layer 109, the second gate insulating film 112 has a step (third step) 112a and a step (fourth step). Two steps of 112b are formed. The two steps 112a and 112b formed on the second gate insulating film 112 reflect the step (first step) 108a and the step (second step) 109a. The second gate insulating film 112 can be formed by CVD by CVD using SiH4 (silane) and N2O (nitrous oxide). The pseudo-taper angle θ0 (see FIG. 10) composed of the two steps 112a and 112b is set to 30 degrees or less.

FIG. 16 is a cross-sectional view showing a step of selectively forming the second gate electrode 116 on the second gate insulating film 112. The second gate electrode 116 is formed of, for example, a laminated film of Ti—Al alloy—Ti or the like, or a Mo, MoW alloy or the like. The second gate electrode 116 is formed on the two steps 112a and 112b formed on the second gate insulating film 112. Since the pseudo-taper angle θ0 (see FIG. 10) composed of the two steps 112a and 112b is set to 30 degrees or less, a recess (recess) or a recess is formed in the second gate electrode 116 of the overcoming portion of the second semiconductor layer 109. It is possible to suppress the occurrence of recesses (constrictions). Therefore, it is possible to prevent poor characteristics of the thin film transistor (OSTFT) and disconnection of the gate wiring of the thin film transistor (OSTFT).

FIG. 17 is a cross-sectional view showing a process of forming the third insulating film 117 and the fourth insulating film 118 on the second gate electrode 116 and the second gate insulating film 112. A third insulating film 117 is formed so as to cover the second gate insulating film 112 and the second gate electrode 116. The third insulating film 117 is made of SiN. After the formation of the third insulating film 117, the fourth insulating film 118 is formed on the third insulating film 117. The fourth insulating film 118 is formed of SiO.

After the step shown in FIG. 17, as shown in FIG. 4, for example, a contact hole 120 for forming the source / drain electrode wiring 1192 in the LTPSTFT and a contact hole 122 for forming the source / drain electrode wiring 1212 in the OSTFT. Is formed. The contact holes 120 and 122 are formed by dry etching using, for example, a CF-based (for example, CF4) or CHF-based (for example, CHF3) gas. On the LTPSTFT side, the contact hole 120 is formed in the five-layer insulating film and the six-layer insulating film, and on the OSTFT side, the contact hole 122 is formed in the two-layer insulating film and the three-layer insulating film. After that, the contact holes 120 and 122 are cleaned with an HF-based cleaning liquid, and after cleaning, the source drain electrode wiring 1192 and the source drain electrode wiring 1212 are formed. The source / drain electrode wirings 1192 and 1212 can be formed of, for example, a laminated film of Ti, Al alloy, Ti or the like.

(Application example 1)
In the embodiment, a configuration example of a thin film transistor (OSTFT) and a method of manufacturing a semiconductor device related to the thin film transistor (OSTFT) have been described. In Application Example 1, a configuration example of the thin film transistor LTPSTFT when the technical idea of the embodiment is applied to the thin film transistor LTPSTFT, and a method of manufacturing a semiconductor device related to the thin film transistor LTPSTFT will be described with reference to the drawings.

(Structure example of thin film transistor LTPSTFT)
FIG. 18 is a diagram for explaining a main part of the thin film transistor LTPSTFT of FIG. 4, and is a cross-sectional view of the thin film transistor LTPSTFT along the extending direction of the first gate electrode. FIG. 19 is a diagram for explaining a main part of the thin film transistor LTPSTFT of FIG. 4, and is a cross-sectional view of the thin film transistor LTPSTFT along a direction perpendicular to the extending direction of the first gate electrode.

As shown in FIG. 18, the thin film transistor (LTPSTFT) is formed by covering the first semiconductor layer 102 selectively formed on the base film (base insulating film) 101 and the first semiconductor layer 102. It has a gate insulating film 104 and a first gate electrode 105 selectively formed on the first gate insulating film 104. The first semiconductor layer 102 is composed of LTPS (Low Temperature Poly-Si).

The base film 101 has two steps 101a, and the first semiconductor layer 102 is raised by two steps (first step) 101a having a predetermined angle (second taper angle θ2) in a cross-sectional view. It is provided on the region 101b of the base film 101. Both ends of the first semiconductor layer 102 have two steps (second steps) 102a having a predetermined angle (first taper angle θ1) in a cross-sectional view. The first gate insulating film 104 has two steps (third step) 104a and two steps (fourth step) 104b. The steps 104a and 104b formed on the first gate insulating film 104 reflect the steps 101a of the base film 101 and the steps 102a of the first semiconductor layer 102. Since the pseudo-taper angle θ0 (see FIG. 10) composed of the two steps 104a and 104b is set to 30 degrees or less, a recess (recess) or a recess is formed in the first gate electrode 105 of the overcoming portion of the first semiconductor layer 102. It is possible to suppress the occurrence of recesses (constrictions).

Therefore, the first gate electrode 105 formed on the first gate insulating film 104 is formed on the steps 104a and 104b in the first gate insulating film 104 at the overcoming portion of the first semiconductor layer 102. Therefore, the taper angle of the first gate insulating film 104 at the overcoming portion of the first semiconductor layer 102 is relaxed, so that the first gate electrode 105 does not break.

As shown in FIG. 19, the first semiconductor layer 102 includes a channel region 1021, a drain region or source region 1022, and a source region or drain region 1023 (in the following, the drain region or source region 1092 is referred to as a drain region. The source area or the drain area 1093 will be described as the source area). The channel region 1021 is provided between the drain region 1022 and the source region 1023. The first gate electrode 105 is formed on the first gate insulating film 104 corresponding to the upper side of the channel region 1021. As described with reference to FIG. 18, the base film 101 has two steps 101a having a predetermined angle (second taper angle θ2), and the first semiconductor layer 102 has a predetermined angle (first taper angle θ1). It has two steps (second step) 102a. The first gate insulating film 104 has two steps (third step) 104a and two steps (fourth step) 104b.

(Manufacturing method of semiconductor device 2)
Next, an example of a method of manufacturing a semiconductor device in the display device DSP will be described with reference to FIGS. 20 to 25. In the following method for manufacturing a semiconductor device, a method for manufacturing a thin film transistor (LTPSTFT), which is a main part, will be mainly described.

FIG. 20 is a cross-sectional view showing a process of performing a dry etching process on the first semiconductor layer 102. The first semiconductor layer 102 is formed on the base film (base insulating film) 101. The first semiconductor layer 102 is formed of LTPS (Low Temperature Poly-Si). A resist film RE is selectively formed on the first semiconductor layer 102. Then, the resist film RE is used as an etching mask for the dry etching process, and the first semiconductor layer 102 and the base film 101 are selectively etched. As a result, a step 101a is formed on the base film 101. The taper angle of the step 101a corresponds to the second taper angle θ2 described with reference to FIG.

FIG. 21 is a cross-sectional view showing a step of performing an ashing treatment on the resist film RE. By performing an ashing treatment on the resist film RE, the side surface of the resist film RE is scraped. As a result, both ends of the first semiconductor layer 102 are exposed from the resist film RE in a cross-sectional view.

FIG. 22 is a cross-sectional view showing a step of performing a dry etching process on the first semiconductor layer 102 again. Using the resist film RE as an etching mask for the dry etching process, the dry etching process is performed again on the first semiconductor layer 102. As a result, both ends of the first semiconductor layer 102 exposed from the resist film RE are scraped off, so that a step 102a is formed at the end of the first semiconductor layer 102 in cross-sectional view. The etching amount at both ends of the first semiconductor layer 102 corresponds to the receding amount x in FIG. Further, the taper angle of the step 102a corresponds to the first taper angle θ1 described with reference to FIG.

At this time, it is desirable to perform the dry etching process under the condition that the selection ratio between the first semiconductor layer 102 and the base film 101 becomes large. If the selection ratio between the first semiconductor layer 102 and the base film 101 is small, the exposed portion of the base film 101 is also etched, so that the amount of scraping of the base film 101 (corresponding to t2 in FIG. 10) increases. There are concerns. In addition, the tapered shape of the step 101a may deteriorate. That is, if the selection ratio between the first semiconductor layer 102 and the base film 101 is small, there is a concern that the apex portion 101ah of the step 101a is scraped off, and as a result, the pseudo-taper angle θ0 (see FIG. 10) becomes large. ..

FIG. 23 is a cross-sectional view showing a step of forming the first gate oxide film 104 on the base film 101 and the first semiconductor layer 102. After removing the resist film RE, the first gate oxide film 104 is formed on the base film 101 and the first semiconductor layer 102. Steps 104a and 104b are formed on the first gate oxide film 104. The steps 104a and 104b reflect the steps 101a of the base film 101 and the steps 102a of the first semiconductor layer 102.

FIG. 24 is a cross-sectional view showing a step of selectively forming the first gate electrode 105 on the first gate oxide film 104. The first gate electrode 105 is selectively formed on the first gate oxide film 104. Since the pseudo-taper angle θ0 (see FIG. 10) composed of the two steps 104a and 104b is set to 30 degrees or less, a recess (recess) or a recess is formed in the first gate electrode 105 of the overcoming portion of the first semiconductor layer 102. It is possible to suppress the occurrence of recesses (constrictions). Therefore, it is possible to prevent poor characteristics of the thin film transistor (LTPSTFT) and disconnection of the gate wiring of the thin film transistor (LTPSTFT).

FIG. 25 is a cross-sectional view showing a process of forming the first insulating film 107 and the second insulating film 108 on the first gate oxide film 104 and the first gate electrode 105. First, the first insulating film 107 is formed by covering the first gate oxide film 104 and the first gate electrode 105. The first insulating film 107 is formed of SiN by CVD. A second insulating film 108 is formed on the first insulating film 107. The second insulating film 108 is formed of SiO by CVD.

After that, as shown in FIG. 4, the manufacturing process of the thin film transistor OSTFT will be carried out.

(Application example 2)
The semiconductor device 10 shown in FIG. 4 is formed by combining the semiconductor device manufacturing method 1 described with reference to FIGS. 12 to 17 and the semiconductor device manufacturing method 2 described with reference to FIGS. 20 to 25. You may. As a result, it is possible to suppress the occurrence of step breakage in the first gate electrode 105 and the second gate electrode 116. Therefore, it is possible to prevent poor characteristics of the thin film transistor (LTPSTFT) and the thin film transistor (OSTFT) and disconnection of the gate wirings (105, 116) of the thin film transistor (LTPSTFT) and the thin film transistor (OSTFT).

According to the first embodiment, the following one or more effects can be obtained.

1) Since the pseudo-taper angle θ0 (see FIG. 10) composed of the two steps 112a and 112b is 30 degrees or less, a recess (recess) is formed in the second gate electrode 116 of the overcoming portion of the second semiconductor layer 109. ) And recesses (necking) can be suppressed. Therefore, it is possible to prevent poor characteristics of the thin film transistor (OSTFT) and disconnection of the gate wiring of the thin film transistor (OSTFT).

2) Since the pseudo-taper angle θ0 (see FIG. 10) composed of the two steps 104a and 104b is set to 30 degrees or less, a recess (recess) is formed in the first gate electrode 105 of the overcoming portion of the first semiconductor layer 102. ) And recesses (necking) can be suppressed. Therefore, it is possible to prevent poor characteristics of the thin film transistor (LTPSTFT) and disconnection of the gate wiring of the thin film transistor (LTPSTFT).

3) By combining the above 1) and the above 2), it is possible to suppress the occurrence of step breakage of the first gate electrode 105 and the second gate electrode 116. Therefore, it is possible to prevent poor characteristics of the thin film transistor (LTPSTFT) and the thin film transistor (OSTFT) and disconnection of the gate wirings (105, 116) of the thin film transistor (LTPSTFT) and the thin film transistor (OSTFT).

(Embodiment 2)
In the first embodiment, a semiconductor device 10 such as a display device having an LTPSTFT and an OSTFT has been described. In the second embodiment, a semiconductor device 10a such as a display device having only an OSTFT will be described. In this case, in the configuration of the OSTFT shown in FIG. 4, the protective metal layer 111 connected to the drain region 1092 and the source region 1093 can be deleted. Therefore, since the film forming and patterning steps of the metal layer 111 and the contact hole cleaning step can be eliminated, the manufacturing step of the semiconductor device 10a can be shortened.

FIG. 26 is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment. The semiconductor device 10a shown in FIG. 26 is a first substrate SUB1 provided with a thin film transistor (hereinafter, also referred to as OSTFT) using an oxide semiconductor (OS). In FIG. 26, the semiconductor device 10a is a semiconductor device provided in the display panel.

The semiconductor device 10a includes a substrate 100, a base film (base insulating film) 101, a semiconductor layer 109, a gate insulating film 301, a gate electrode 304, a first insulating film 305, a second insulating film 306, and the like.

The substrate 100 is an insulating substrate and is made of glass or resin. A base film 101 is formed on the substrate 100. The base film 101 is an insulating film and is formed of a silicon oxide SiO or a silicon nitride SiN by CVD.

A semiconductor layer 109 for OSTFT is formed on the base film 101. The semiconductor layer 109 is formed of an oxide semiconductor OS. The semiconductor layer 109 includes a channel region 1091, and the semiconductor layer 109 includes a channel region 1091, a drain region or a source region 1092, a source region or a drain region 1093 (hereinafter, the drain region or the source region 1092 is used as a drain region). , The source area or the drain area 1093 will be described as the source area). The channel region 1091 is provided between the drain region 1092 and the source region 1093. The film thickness of the semiconductor layer 109 is, for example, about 50 nm.

The gate insulating film 301 is formed so as to cover the base film 101 and the semiconductor layer 109. The gate insulating film 301 can be formed by CVD by CVD using SiH4 (silane) and N2O (nitrous oxide). The film thickness of the gate insulating film 301 is, for example, about 100 nm.

A gate electrode 304 is formed on the gate insulating film 301 corresponding to the channel region 1091. The gate electrode 304 is formed of, for example, a laminated film of Ti—Al alloy—Ti or the like, or a Mo, MoW alloy or the like. The film thickness of the gate electrode 304 is, for example, about 250 nm.

The first insulating film 305 is formed so as to cover the gate insulating film 301 and the gate electrode 304. The first insulating film 305 is made of SiN. A second insulating film 306 is formed on the first insulating film 117. The fourth insulating film 118 is formed of SiO.

A contact hole 307 for forming the source / drain electrode wiring 308 is formed in the OSTFT. The contact hole 307 is formed by dry etching using, for example, a CF-based (for example, CF4) or CHF-based (for example, CHF3) gas.

In the OSTFT, contact holes 307 are formed in the three-layer insulating film (301, 305, 306). The contact hole 307 is formed in a three-layer insulating film (306, 305, 301) so that the drain region 1092 and the source region 1093 are exposed. Then, the source / drain electrode wiring 308 is formed in the contact hole 307. As described above, the semiconductor device 10a including the thin film transistor (OSTFT) using the oxide semiconductor (OS) is configured.

FIG. 27 is a plan view showing a configuration example of the layout of the thin film transistor OSTFT of FIG. 26. FIG. 28 is a cross-sectional view taken along the line DD of FIG. 27. FIG. 29 is a cross-sectional view taken along the line EE of FIG. 27. The difference between FIG. 27 and FIG. 5 is that the reference number of the gate electrode is changed to 304 and the metal layer 111 is deleted in FIG. 27. Since the other configurations of FIG. 27 are the same as the other configurations of FIG. 5, the description thereof will be omitted.

As shown in FIGS. 28 and 29, the base film 101 has two steps (first step) 101a, and the semiconductor layer 109 has a predetermined angle (taper angle θ2 in FIG. 10) in cross-sectional view. It is provided on the region 101b of the base film 101 raised by the two steps 101a having (corresponding to). Both ends of the semiconductor layer 109 have two steps (second steps) 109a having a predetermined angle (corresponding to the taper angle θ1 in FIG. 10) in cross-sectional view. The gate insulating film 301 has two steps (third step) 301a and two steps (fourth step) 301b. The steps 301a and 301b (corresponding to the steps 112a and 112b in FIG. 10) formed on the gate insulating film 301 reflect the steps 101a of the base film 101 and the steps 109a of the semiconductor layer 109. Therefore, the gate electrode 304 formed on the gate insulating film 301 is formed on the steps 301a and 301b in the gate insulating film 301 at the overcoming portion of the semiconductor layer 109. Therefore, the taper angle of the gate insulating film 301 (corresponding to the pseudo-taper angle θ0 in FIG. 10) at the overcoming portion of the semiconductor layer 109 is relaxed, so that the gate electrode 304 does not break. That is, since the pseudo-taper angle θ0 (see FIG. 10) composed of the steps 301a and 301b is 30 degrees or less, the gate electrode 304 at the overcoming portion of the semiconductor layer 109 has a recess (recess) or a recess (constriction). It is possible to suppress the occurrence of. Therefore, it is possible to prevent poor characteristics of the thin film transistor (OSTFT) and disconnection of the gate wiring of the thin film transistor (OSTFT).

(Manufacturing method of semiconductor device 3)
Next, an example of a method of manufacturing a semiconductor device in the display device DSP will be described with reference to FIGS. 30 to 35. In the following manufacturing method of the semiconductor device, a manufacturing method of the thin film transistor (OSTFT) shown in FIG. 26 will be described.

FIG. 30 is a cross-sectional view showing a step of performing a wet etching process on the semiconductor layer 109 using an oxalic acid-based etching solution. The semiconductor layer 109 is formed on the base film (base insulating film) 101, and then the resist film RE is selectively formed on the semiconductor layer 109. After the resist film RE is formed, the semiconductor layer 109 is etched by using the resist film RE as an etching mask for wet etching treatment. As a result, the semiconductor layer 109 of the portion not covered by the resist film RE is etched.

FIG. 31 is a cross-sectional view showing a step of performing a dry etching process on the base film 101. By performing the dry etching process on the base film 101, the portion of the base film 101 exposed from the semiconductor layer 109 is etched. Since the base film 101 is scraped by etching, a step (first step) 101a having a predetermined angle (second taper angle θ2) is formed at both ends of the base film 101. The amount scraped by etching the base film 101 corresponds to the scraping amount (etching amount) t2 in FIG. In addition, the side surface of the resist film RE is scraped. As a result, both ends of the semiconductor layer 109 are exposed from the resist film RE in a cross-sectional view.

FIG. 32 is a cross-sectional view showing a step of performing a wet etching process on the semiconductor layer 109 again using an oxalic acid-based etching solution. Using the resist film RE as an etching mask for the wet etching process, the semiconductor layer 109 is subjected to the wet etching process again. As a result, both ends of the semiconductor layer 109 exposed from the resist film RE are etched in the lateral direction. As a result, a step (second step) 109a having a predetermined angle (first taper angle θ1) is formed at both ends of the semiconductor layer 109. The amount of etching at both ends of the semiconductor layer 109 in the lateral direction corresponds to the amount of retreat x of the semiconductor layer (OS) 109 in FIG.

FIG. 33 is a cross-sectional view showing a process of forming the gate insulating film 301 on the base film 101 and the semiconductor layer 109. After removing the resist film RE, the gate insulating film 301 is formed on the base film 101 and the semiconductor layer 109. When the gate insulating film 301 is formed on the base film 101 and the semiconductor layer 109, the gate insulating film 301 is formed with two steps, a step (third step) 301a and a step (fourth step) 301b. To. The two steps 301a and 301b formed in the gate insulating film 301 reflect the step (first step) 101a and the step (second step) 109a. The gate insulating film 301 can be formed by CVD by CVD using SiH4 (silane) and N2O (nitrous oxide). The pseudo-taper angle θ0 (see FIG. 10) composed of the two steps 301a and 301b is set to 30 degrees or less.

FIG. 34 is a cross-sectional view showing a process of selectively forming the gate electrode 304 on the gate insulating film 301. The gate electrode 304 is formed of, for example, a laminated film of Ti—Al alloy—Ti or the like, or a Mo, MoW alloy or the like. The gate electrode 304 is formed on the two steps 301a and 301b formed in the gate insulating film 301. Since the pseudo-taper angle θ0 (see FIG. 10) composed of the two steps 301a and 301b is set to 30 degrees or less, the gate electrode 304 at the overcoming portion of the semiconductor layer 109 has a recess (recess) or a recess (constriction). It is possible to suppress the occurrence of. Therefore, it is possible to prevent poor characteristics of the thin film transistor (OSTFT) and disconnection of the gate wiring of the thin film transistor (OSTFT).

FIG. 35 is a cross-sectional view showing a process of forming the first insulating film 305 and the second insulating film 306 on the gate electrode 304 and the gate insulating film 301. The first insulating film 305 is formed so as to cover the gate electrode 304 and the gate insulating film 301. The first insulating film 305 is made of SiN. After the formation of the first insulating film 305, the second insulating film 306 is formed on the first insulating film 305. The second insulating film 306 is formed of SiO.

After the step shown in FIG. 35, as shown in FIG. 26, contact holes 307 for forming the source / drain electrode wiring 308 in the OSTFT are formed in the gate insulating film 301, the first insulating film 305, and the second insulating film 306. Will be done. The contact hole 307 is formed by dry etching using, for example, a CF-based (for example, CF4) or CHF-based (for example, CHF3) gas. After that, the source / drain electrode wiring 308 is formed in the contact hole 307. The source / drain electrode wiring 308 can be formed of, for example, a laminated film of Ti, Al alloy, Ti, or the like.

(Manufacturing method of semiconductor device 4)
Next, a modified example of the manufacturing method of the semiconductor device in the display device DSP will be described with reference to FIGS. 36 to 38. In the following manufacturing method of the semiconductor device, a manufacturing method of the thin film transistor (OSTFT) shown in FIG. 26 will be described.

FIG. 36 is a cross-sectional view showing a process of selectively forming the resist film RE on the semiconductor layer 109. The semiconductor layer 109 is formed on the base film (base insulating film) 101, and then the resist film RE is selectively formed on the semiconductor layer 109.

FIG. 37 is a cross-sectional view showing a step of performing a wet etching process using buffered hydrofluoric acid (BHF) on the base film 101 and the semiconductor layer 109. The resist film RE is used as an etching mask for wet etching treatment using buffered hydrofluoric acid (BHF). By performing this wet etching treatment, the semiconductor layer 109 and the base film 101 of the portion not covered by the resist film RE are scraped by etching. Further, both ends of the semiconductor layer 109 exposed from the resist film RE are laterally etched by etching.

Since the base film 101 is scraped by etching, a step (first step) 101a having a predetermined angle (second taper angle θ2) is formed at both ends of the base film 101. The amount scraped by etching the base film 101 corresponds to the scraping amount (etching amount) t2 in FIG. Further, since both ends of the semiconductor layer 109 are etched in the lateral direction, a step (second step) 109a having a predetermined angle (first taper angle θ1) is formed at both ends of the semiconductor layer 109. The amount of etching at both ends of the semiconductor layer 109 in the lateral direction corresponds to the amount of retreat x of the semiconductor layer (OS) 109 in FIG.

FIG. 38 is a cross-sectional view showing a process of forming the gate insulating film 301 on the base film 101 and the semiconductor layer 109. After removing the resist film RE, the gate insulating film 301 is formed on the base film 101 and the semiconductor layer 109. When the gate insulating film 301 is formed on the base film 101 and the semiconductor layer 109, the gate insulating film 301 is formed with two steps, a step (third step) 301a and a step (fourth step) 301b. To. The two steps 301a and 301b formed in the gate insulating film 301 reflect the step (first step) 101a and the step (second step) 109a. The gate insulating film 304 can be formed by CVD by CVD using SiH4 (silane) and N2O (nitrous oxide). The pseudo-taper angle θ0 (see FIG. 10) composed of the two steps 301a and 301b is set to 30 degrees or less.

After the step shown in FIG. 38, the steps shown in FIGS. 34 and 35 are carried out. Then, as shown in FIG. 26, contact holes 307 for forming the source / drain electrode wiring 308 in the OSTFT are formed in the gate insulating film 301, the first insulating film 305, and the second insulating film 306. The contact hole 307 is formed by dry etching using, for example, a CF-based (for example, CF4) or CHF-based (for example, CHF3) gas. Next, the source / drain electrode wiring 308 is formed in the contact hole 307. The source / drain electrode wiring 308 can be formed of, for example, a laminated film of Ti, Al alloy, Ti, or the like.

According to the second embodiment, the following effects can be obtained.

1) Since the pseudo-taper angle θ0 (see FIG. 10) composed of the steps 301a and 301b is 30 degrees or less, the gate electrode 304 at the overcoming portion of the semiconductor layer 109 has a recess (recess) or a recess (constriction). It is possible to suppress the occurrence of. Therefore, it is possible to prevent poor characteristics of the thin film transistor (OSTFT) and disconnection of the gate wiring of the thin film transistor (OSTFT).

All display devices that can be appropriately designed and implemented by those skilled in the art based on the display devices described above as embodiments of the present invention also belong to the scope of the present invention as long as the gist of the present invention is included.

Within the scope of the idea of the present invention, those skilled in the art can come up with various modified examples and modified examples, and it is understood that these modified examples and modified examples also belong to the scope of the present invention. For example, those skilled in the art appropriately adding, deleting, or changing the design of each of the above-described embodiments, or adding, omitting, or changing the conditions of the process are also gist of the present invention. Is included in the scope of the present invention as long as the above is provided.

In addition, other actions and effects brought about by the aspects described in the present embodiment are clearly understood from the description of the present specification, or those which can be appropriately conceived by those skilled in the art are naturally understood to be brought about by the present invention. ..

Various inventions can be formed by an appropriate combination of a plurality of components disclosed in the above embodiment. For example, some components may be removed from all the components shown in the embodiments. In addition, components from different embodiments may be combined as appropriate.

10: Semiconductor device, 100: Substrate, 101: Underlayer, 102: First semiconductor layer, 104: First gate insulating film, 105: First gate electrode, 106: Light-shielding layer, 107: First insulating film, 108: Second insulating film, 108a: step (first step), 109: second semiconductor layer, 109a: step (second step), 112: second gate insulating film, 112a: step (third step), 112b: Step (fourth step) 116: Second gate electrode, 117: Third insulating film, 118: Fourth insulating film

Claims (14)

The underlying insulating film having the first step and
A semiconductor layer provided on the underlying insulating film and having a second step,
A gate insulating film provided on the underlying insulating film and the semiconductor layer and having a third step reflecting the first step and a fourth step reflecting the second step. When,
A semiconductor device having a gate electrode provided on the gate insulating film so as to cover the third step and the fourth step. In claim 1,
A semiconductor device having a pseudo-taper angle of 30 degrees or less, which is an inclination of a line connecting the apex of the third step and the apex of the fourth step from the horizontal. In claim 2,
The first step has a second taper angle.
The second step has a first taper angle.
The third step has the second taper angle.
The fourth step is a semiconductor device having the first taper angle. In claim 3,
A semiconductor device in which the first taper angle and the second taper angle are 90 degrees or less and equal to or more than the pseudo taper angle. In claim 4,
The semiconductor layer includes a channel region, a drain region, and a source region of the thin film transistor.
A semiconductor device in which the semiconductor layer is an oxide semiconductor. In claim 5,
The semiconductor device is a semiconductor device built in a display panel having a display area including pixels.
The thin film transistor is a semiconductor device that constitutes a switching element provided in the pixel. In claim 4,
The semiconductor layer includes a channel region, a drain region, and a source region of the thin film transistor.
A semiconductor device in which the semiconductor layer is LTPS. In claim 7,
The semiconductor device is a semiconductor device built in a display panel having a drive circuit for driving pixels.
The thin film transistor is a semiconductor device that constitutes a switching element provided in the drive circuit. Underlayer insulating film and
With the semiconductor layer
With the gate insulating film
With a gate electrode,
The semiconductor layer includes a bottom surface, a first surface, and a first side surface provided between the bottom surface and the first surface, and the first side surface has a first taper angle with respect to the bottom surface. Have,
The underlying insulating film includes a second surface, a third surface, and a second side surface provided between the second surface and the third surface, and the second side surface is formed on the second surface. On the other hand, the semiconductor layer has a second taper angle, and the semiconductor layer is provided on the base insulating film so that the bottom surface of the semiconductor layer is provided on the second surface of the base insulating film.
The gate insulating film is provided on the underlying insulating film and the semiconductor layer, and is provided on a fourth surface, a fifth surface provided above the fourth surface, and above the fifth surface. A sixth surface, a third side surface provided between the fourth surface and the fifth surface, and a fourth side surface provided between the fifth surface and the sixth surface are included. ,
The third side surface has the second taper angle with respect to the fourth surface, and the fourth side surface has the first taper angle with respect to the fifth surface.
The gate electrode is a semiconductor device formed on the fourth surface, the third side surface, the fifth surface, the fourth side surface, and the sixth surface of the gate insulating film. In claim 9.
The first intersection of the third side surface and the fifth surface,
Includes a second intersection of the fourth side surface and the sixth surface.
A semiconductor device in which the pseudo-taper angle is 30 degrees or less when the angle between the line connecting the first intersection and the second intersection and the fourth surface is a pseudo-taper angle. In claim 10,
A semiconductor device in which the first taper angle and the second taper angle are 90 degrees or less and equal to or more than the pseudo taper angle. 11.
A semiconductor device in which the distance between the second surface and the third surface of the underlying insulating film is within ± 50% of the distance between the bottom surface of the semiconductor layer and the first surface. In claim 12,
The semiconductor layer includes a channel region, a drain region, and a source region of the thin film transistor.
A semiconductor device in which the semiconductor layer is an oxide semiconductor. In claim 13,
The semiconductor device is a semiconductor device built in a display panel having a display area including pixels.
The thin film transistor is a semiconductor device that constitutes a switching element provided in the pixel.

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