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WO2020029181A1 - Dispositif de calcul à base de réseau neuronal convolutionnel tridimensionnel et produit associé - Google Patents

Dispositif de calcul à base de réseau neuronal convolutionnel tridimensionnel et produit associé Download PDF

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Publication number
WO2020029181A1
WO2020029181A1 PCT/CN2018/099658 CN2018099658W WO2020029181A1 WO 2020029181 A1 WO2020029181 A1 WO 2020029181A1 CN 2018099658 W CN2018099658 W CN 2018099658W WO 2020029181 A1 WO2020029181 A1 WO 2020029181A1
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Prior art keywords
dimensional
data
score
convolution
buffer
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Chinese (zh)
Inventor
范鸿翔
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Shenzhen Corerain Technologies Co Ltd
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Shenzhen Corerain Technologies Co Ltd
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Priority to CN201880082662.4A priority Critical patent/CN111542837B/zh
Priority to PCT/CN2018/099658 priority patent/WO2020029181A1/fr
Publication of WO2020029181A1 publication Critical patent/WO2020029181A1/fr
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0464—Convolutional networks [CNN, ConvNet]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of computers and artificial intelligence technologies, and in particular, to a three-dimensional convolutional neural network computing device and related products.
  • 3D convolutional neural network algorithms have been widely used in many applications such as behavior detection, medical image analysis, and terrain analysis.
  • 3D convolution not only extracts features in the 2D image dimension, but also adds feature extraction and analysis in the 3rd dimension, such as time or the 3D space dimension.
  • 3D convolutional neural networks are more accurate than traditional 2D convolutional neural networks in 3D data processing, such as analysis of video or 3D topographic maps. Because applications such as behavior detection and terrain geological analysis are deployed on mobile terminals, real-time processing speed is required. Therefore, how to implement 3D convolutional neural network quickly and efficiently and apply it to actual scenes is one of the current research hotspots.
  • the existing 3D convolutional neural network cannot achieve real-time processing speed, and the calculation speed is slow.
  • the embodiments of the present application provide a three-dimensional convolutional neural network computing device and related products, which realize fast processing of the three-dimensional convolutional neural network through floating-point blocks and improve calculation speed.
  • an embodiment of the present application provides a three-dimensional convolutional neural network computing device, which is characterized in that the computing device includes: a fraction processing block, an exponential kernel, a three-dimensional convolution kernel, a frame superposition block, a channel superposition block, and an output.
  • the computing device includes: a fraction processing block, an exponential kernel, a three-dimensional convolution kernel, a frame superposition block, a channel superposition block, and an output.
  • the score processing block is used to receive the score data Lm of the three-dimensional picture data block, divide the score data Lm into three two-dimensional score data, and input the three two-dimensional score data into the three-dimensional convolution kernel;
  • the exponential kernel is used to receive the shared exponential data Le of the three-dimensional image data block, and input the exponential data Le to the three-dimensional convolution kernel;
  • a three-dimensional convolution kernel which is used to perform three-dimensional convolution operations on three two-dimensional fractional data to obtain three fractional convolution operation results, divide the index data Le into three two-dimensional index data, and perform three-dimensional convolution operations to obtain three.
  • Exponential convolution operation results inputting three exponential convolution operation results and three fractional convolution operation results into the frame superposition block;
  • Frame superposition block which is used to perform frame superposition processing on three exponential convolution operation results and three fractional convolution operation results to obtain superimposed data, and input the superimposed processing data to the channel superposition block;
  • the channel superposition block is used to obtain the preliminary convolution result after performing the channel superposition processing on the data after the superposition processing, and input the preliminary processing result to the output buffer.
  • a method for performing a three-dimensional convolution operation by using the device of the first aspect includes:
  • Receive the score data Lm of the three-dimensional picture data block divide the score data Lm into three two-dimensional score data, and input the three two-dimensional score data into the three-dimensional convolution kernel;
  • the three two-dimensional fraction data is respectively subjected to a two-dimensional convolution operation to obtain three fractional convolution operation results.
  • the index data Le is divided into three two-dimensional index data and the two-dimensional convolution operation is performed to obtain three exponential convolution operation results.
  • a preliminary convolution result is obtained, and the preliminary processing result is input to the output buffer.
  • a computer-readable storage medium stores a computer program for electronic data interchange, wherein the computer program causes a computer to execute the method as provided in the second aspect.
  • a computer program product in a fourth aspect, includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute the method provided in the second aspect.
  • FIG. 1A is a schematic diagram of a two-dimensional convolution.
  • FIG. 1B is a schematic diagram of a three-dimensional convolution.
  • FIG. 2A is a schematic diagram of data representation of a floating-point block.
  • FIG. 2B is a schematic diagram of data representation of another floating point block.
  • FIG. 3 is a schematic structural diagram of a three-dimensional convolutional neural network computing device according to the present application.
  • FIG. 4 is a flowchart of a method for implementing a three-dimensional convolution operation provided by the present application.
  • an embodiment herein means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application.
  • the appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they independent or alternative embodiments that are mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.
  • the electronic device in this application may include: a server, a smart camera device, a smart phone (such as an Android phone, an iOS phone, a Windows Phone phone, etc.), a tablet computer, a handheld computer, a laptop computer, and a mobile Internet device (MID, Mobile Internet Devices) Or wearable devices, etc.
  • the above electronic devices are merely examples, not exhaustive, and include but are not limited to the above electronic devices.
  • the above electronic devices are referred to as user equipment (UE), Terminal or electronic device.
  • UE user equipment
  • Terminal the above-mentioned user equipment is not limited to the above-mentioned realization form, and may include, for example, a smart vehicle terminal, a computer device, and the like.
  • the three-dimensional convolution kernel includes: three two-dimensional fractional convolution kernels and three two-dimensional exponential convolution kernels, wherein:
  • the two-dimensional fractional convolution kernel is used for a two-dimensional convolution operation of two-dimensional fraction data
  • the two-dimensional exponential convolution kernel is used to perform a two-dimensional convolution operation of two-dimensional exponential data.
  • the apparatus further includes: a pooling processing module and an output module;
  • the pooling processing module is configured to perform pooling processing on the preliminary convolution result to obtain a final convolution result, and output the final convolution result through an output module.
  • the score processing block includes a cache, a frame first cache, a frame second cache, a first score cache, a second score cache, and a third score cache;
  • the buffer is connected to the frame first buffer and the first score buffer, the frame first buffer is connected to the frame second buffer, the frame first buffer is also connected to the second score buffer, and the frame second buffer is connected to the third score buffer.
  • the first score buffer, the second score buffer, and the third score buffer respectively output two-dimensional score data.
  • the index core includes a cache and an index cache
  • the index buffer is used for buffering three-dimensional score data and dividing the three-dimensional score data into three two-dimensional score data for output.
  • the method further includes:
  • the preliminary convolution result is pooled to obtain the final convolution result, and the final convolution result is output through the output module.
  • splitting the score data Lm into three two-dimensional score data, and inputting the three two-dimensional score data into the three-dimensional convolution kernel specifically include:
  • the score data Lm is stored in three frame buffers, and the three frame stores respectively input the two-dimensional score data to the three-dimensional convolution kernel.
  • FIG. 1A is a schematic diagram of a two-dimensional convolution.
  • a picture of each frame has two channels of data, that is, a frame 1 transparent frame represents data of channel 1 of frame 1, frame 1
  • the gray box represents the data of channel 2 of frame 1.
  • the data of the two channels of frame 1 are combined into one data frame.
  • FIG. 1B FIG. 1B is a schematic diagram of a three-dimensional convolution. Different from the two-dimensional convolution, different frames are also merged. As shown in FIG. 1B, the merged data frame has two channels of frame 1. Data and data of 2 channels of frame 2.
  • FIG. 2A is a representation of floating point data.
  • FIG. 2A is data of one frame in one channel, as shown in FIG. 2A, and one line of data represents data of one pixel, as shown in FIG. 2A.
  • FIG. 2B is a representation of floating point data of the present application. Comparing FIG. 2B with FIG. 2A, it can be seen that for data sharing Le of one channel and one channel of FIG. 2B, relative to each pixel Both have non-shared Le.
  • the floating-point block data representation of Figure 2B can greatly reduce the data storage space, which can match the FPGA cache, avoiding the problem of small caches that cannot effectively store calculation data, and operations between different blocks. In this case, the number of bits required for the fractional operation is reduced, which greatly reduces the use of on-chip computing resources.
  • FIG. 3 provides a three-dimensional convolutional neural network computing device.
  • the computing device includes a score processing block 301, an exponential kernel 302, a three-dimensional convolution kernel 303, a frame superimposing block 304, and a channel.
  • the score processing block 301 is configured to receive the score data Lm of the three-dimensional picture data block, divide the score data Lm into three two-dimensional score data, and input the three two-dimensional score data into the three-dimensional convolution kernel 303;
  • the index kernel 302 is configured to receive the shared index data Le of the three-dimensional picture data block, and input the index data Le to the three-dimensional convolution kernel 303;
  • the three-dimensional convolution kernel 303 is configured to perform three-dimensional convolution operations on three two-dimensional fraction data to obtain three score convolution operation results, divide the index data Le into three two-dimensional index data, and perform two-dimensional convolution operations to obtain three. Exponential convolution operation results, input three exponential convolution operation results and three fractional convolution operation results to the frame superposition block 304;
  • the frame superposition block 304 is configured to perform frame superposition processing on three exponential convolution operation results and three fractional convolution operation results to obtain superimposed processing data, and input the superimposed processing data to the channel superposition block 305;
  • a channel superimposing block 305 is configured to obtain a preliminary convolution result after performing channel superposition processing on the data after the superposition processing, and input the preliminary processing result to the output buffer 306.
  • the technical solution provided in this application first only deals with floating-point block data, and when processing the data of the floating-point block, the index data of the floating-point block needs to be shared index data, so that the three-dimensional convolution operation is divided into three A two-dimensional convolution operation, and then a frame superposition and a channel superposition are performed to implement a three-dimensional convolution operation.
  • the floating point block of the technical solution provided by the present application has a small amount of data, its memory space is small, so FPGA The small cache can adapt to the above structure.
  • its calculation uses three parallel two-dimensional convolution operations. Parallel operations can save calculation time, so it has the advantage of short calculation time.
  • the three-dimensional convolution kernel includes: three two-dimensional fractional convolution kernels and three two-dimensional exponential convolution kernels.
  • the two-dimensional fractional convolution kernel is used for a two-dimensional convolution operation of two-dimensional fraction data.
  • Two-dimensional exponential convolution kernel used to perform a two-dimensional convolution operation on two-dimensional exponential data.
  • the above computing device may further include a pooling processing module and an output module.
  • the pooling processing module is configured to perform pooling processing on the preliminary convolution result to obtain a final convolution result, and pass the final convolution result through the output module. Output.
  • the score processing block 301 may include: a cache 3011, a frame first cache 3012, a frame second cache 3013, a first score cache 3014, a second score cache 3015, and a third score cache 3016; among them, the cache 3011 and The first frame buffer 3012 and the first score buffer 3014 are connected, the first frame buffer 3012 is connected to the second frame buffer 3013, the first frame buffer 3012 is also connected to the second score buffer 3015, and the second frame buffer 3013 is connected to the third score The buffer 3016 is connected, and the first score buffer 3014, the second score buffer 3015, and the third score buffer 3016 respectively output two-dimensional score data.
  • the index core 302 may include: a cache 3021 and an index cache 3022, a cache 3021 for receiving three-dimensional score data, and an index cache 3022 for buffering three-dimensional score data and dividing the three-dimensional score data into three two-dimensional score data and output .
  • the technical solution provided by this application is based on block floating point operation, which reduces the bit width and computational complexity, thereby reducing the use of on-chip memory resources and hardware computing resources; based on the new 3D convolutional neural network hardware architecture, it has faster processing Speed and higher accuracy meet the requirements of real-time processing; compared with existing CPU and GPU implementations, it can make behavioral judgments with lower power consumption, and at the same time ensure correct results.
  • FIG. 4 provides a method for a three-dimensional convolution operation.
  • the method includes:
  • Step S401 Receive score data Lm of a three-dimensional picture data block, divide the score data Lm into three two-dimensional score data, and input the three two-dimensional score data into a three-dimensional convolution kernel;
  • Step S402 Receive the shared index data Le of the three-dimensional picture data block, and input the index data Le to the three-dimensional convolution kernel;
  • Step S403 Perform three-dimensional convolution operations on the three two-dimensional score data to obtain three score convolution operation results, divide the index data Le into three two-dimensional index data, and perform two-dimensional convolution operations to obtain three exponential convolution operations. As a result, three exponential convolution operation results and three fractional convolution operation results are obtained;
  • Step S404 Perform frame superposition processing on the three exponential convolution operation results and the three fractional convolution operation results to obtain data after the superposition processing;
  • Step S405 Perform the channel superposition processing on the data after the superposition processing to obtain a preliminary convolution result, and input the preliminary processing result to the output buffer.
  • An embodiment of the present application further provides a computer storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, and the computer program enables a computer to execute any one of the three-dimensional convolution operations described in the foregoing method embodiments. Part or all of the steps of a method.
  • An embodiment of the present application further provides a computer program product, the computer program product includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to perform the operations described in the foregoing method embodiments. Part or all of the steps of any method of 3D convolution operation.
  • processors and chips in the various embodiments of the present application may be integrated in one processing unit, or may exist separately physically, or two or more pieces of hardware may be integrated in one unit.
  • the computer-readable storage medium or computer-readable program may be stored in a computer-readable memory.
  • the technical solution of the present application essentially or part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product, which is stored in a memory.
  • Several instructions are included to enable a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in the embodiments of the present application.
  • the foregoing memories include: U disks, Read-Only Memory (ROM), Random Access Memory (RAM), mobile hard disks, magnetic disks, or optical disks and other media that can store program codes.
  • the program may be stored in a computer-readable memory, and the memory may include a flash disk.
  • ROM Read-only memory
  • RAM Random Access Memory
  • magnetic disks or optical disks etc.

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Abstract

L'invention concerne un dispositif de calcul à base de réseau neuronal convolutionnel tridimensionnel et un produit associé. Le dispositif de calcul comprend : un module de traitement de score, un noyau exponentiel, un noyau de convolution tridimensionnel (303), un module de superposition de trames (304), un module de superposition de canaux (305), et une mémoire cache de sortie (306). Le dispositif de calcul permet d'obtenir une vitesse de calcul élevée et une précision favorable.
PCT/CN2018/099658 2018-08-09 2018-08-09 Dispositif de calcul à base de réseau neuronal convolutionnel tridimensionnel et produit associé Ceased WO2020029181A1 (fr)

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PCT/CN2018/099658 WO2020029181A1 (fr) 2018-08-09 2018-08-09 Dispositif de calcul à base de réseau neuronal convolutionnel tridimensionnel et produit associé

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