WO2020019263A1 - Chip packaging structure, method and terminal device - Google Patents

Abstract

Provided are a chip packaging structure, a method, and a terminal device. The chip packaging structure comprises: a substrate, with an upper surface of the substrate being provided with a groove structure; a fingerprint identification chip, with the fingerprint identification chip being positioned in the groove structure, and the fingerprint identification chip being provided with a first bonding pad; and a conducting layer, with the conducting layer being positioned above the substrate, and the first bonding pad being electrically connected, via the conducting layer, to a connecting end of the chip packaging structure that is used for being electrically connected to the outside. In the embodiments of the present application, the fingerprint identification chip is embedded in the substrate via the groove structure, such that an upper surface of the packaged chip can be a flat surface, thereby effectively decreasing the deformation quantity and image distance tolerance of the fingerprint identification chip and the substrate, and achieving the purposes of optimizing the sharpness of optical fingerprint imaging, improving the identification speed and improving the user experience.

Description

Chip package structure, method and terminal equipment Technical field

The embodiments of the present application relate to the field of chip packaging, and more particularly, to a chip packaging structure, method, and terminal device.

Background technique

With the development of the mobile phone industry, traditional capacitive fingerprint recognition technology has gradually failed to meet the needs of the emerging mobile phone market due to its limited penetration capabilities, complex chip structure, thick module size, and limited placement. Fingerprint recognition technology will gradually become the mainstream of fingerprint recognition technology due to its strong penetrability and support for full-screen placement.

However, optical fingerprint recognition technology has extremely high requirements on key optical path parameters such as object distance and image distance, and the allowable tolerance range is extremely small. Existing optical fingerprint recognition products have too many design stacks and large cumulative tolerances, resulting in blurred imaging effects, which greatly affects their recognition speed and user experience, thereby limiting their wide-scale promotion and application. For example, chip on board (COB) or integrated package solutions, the stacking design is to stick the lens mount on the chip mount substrate, subject to the deformation of the bracket, the substrate, the adhesive, and the chip And tolerance values, image distance tolerances are large and unstable.

Therefore, how to reduce the image distance tolerance, and then optimize the definition of optical fingerprint imaging, improve the recognition speed and use experience is an urgent problem in the field of chip packaging.

Summary of the Invention

Provided are a chip packaging structure, a method and a terminal device, which can effectively reduce the image distance tolerance, and then optimize the definition of optical fingerprint imaging, improve recognition speed and use experience.

According to a first aspect, a chip packaging structure is provided, including: a substrate having a groove structure formed on an upper surface of the substrate; a fingerprint identification chip located in the groove structure; and the fingerprint identification chip A first pad is provided; a conductive layer is located above the substrate, and the first pad is electrically connected to a connection end of the chip package structure for electrical connection with the outside through the conductive layer. .

In the embodiment of the present application, the fingerprint recognition chip is embedded in the substrate through the groove structure, so that the upper surface of the packaged chip can be a flat surface, and the lens mount can be directly pasted on the flat surface, effectively subtracting The influence of the substrate, chip, and adhesive on the image distance tolerance has achieved the purpose of optimizing the definition of the optical fingerprint imaging, improving the recognition speed and the user experience. Further, the first pad of the fingerprint identification chip is pulled to the edge position of the substrate through the conductive layer through the conductive layer, and the purpose of packaging the fingerprint identification chip is reached.

In some possible implementation manners, the fingerprint identification chip is provided with a plurality of the first pads, the chip packaging structure is provided with a plurality of the connection ends, and the conductive layer is on a positive side of the fingerprint identification chip. An opening is formed above, so that the conductive layer is divided into a plurality of conductive units, and each one or more of the first pads are connected to one or more of the connection ends through one or more of the conductive units.

In some possible implementation manners, the chip package structure further includes: a protective layer formed on an upper surface of the conductive layer, the protective layer is formed with an opening window, and the connection end is disposed on the conductive layer. Inside the window.

In some possible implementation manners, the protective layer is formed with an opening directly above the fingerprint identification chip, so that the reflected light formed by finger reflection passes through the opening of the protective layer and is received by the fingerprint identification chip. .

In some possible implementation manners, a TSV TSV is formed between the conductive layer and the lower surface of the substrate, and the connection end is disposed at a TSV opening on the lower surface of the substrate. The conductive layer The TSV is electrically connected to the connection terminal.

In some possible implementation manners, the chip package structure further includes: an insulating layer disposed between the substrate and the conductive layer, and an opening is formed directly above the fingerprint identification chip so as to pass through The reflected light formed by the finger reflection passes through the opening of the insulating layer and is received by the fingerprint recognition chip.

In some possible implementation manners, the fingerprint recognition chip is fixed in the groove structure by liquid or solid glue, and the depth of the groove structure is the sum of the thickness of the fingerprint recognition chip and the thickness of the glue. .

In some possible implementation manners, the chip packaging structure further includes: a filter, and the filter is attached to an upper surface of the fingerprint identification chip.

In some possible implementation manners, the connection end is a second pad or a solder ball.

In some possible implementation manners, the fingerprint identification chip includes a plurality of chips arranged along a parallel direction and / or a vertical direction of an upper surface of the substrate.

In some possible implementation manners, the chip package structure further includes: a bracket and a lens; the lens is fixed above the fingerprint recognition chip through the bracket, and the lens is aligned with the fingerprint recognition chip. .

In some possible implementation manners, the lens and the bracket are provided integrally or separately.

In a second aspect, a chip packaging structure is provided, including:

A fingerprint recognition chip having a first pad provided on an upper surface thereof, a through-silicon via TSV provided between an upper surface and a lower surface of the fingerprint recognition chip, and a conductive surface provided on the lower surface of the fingerprint recognition chip Layer, the first pad is electrically connected to one end of the conductive layer through the TSV TSV, and the other end of the conductive layer is electrically connected to a connection end of the chip package structure for electrical connection with the outside .

In the embodiment of the present application, the first pad of the fingerprint identification chip is pulled to the lower surface of the fingerprint identification photo by TSV, so that the upper surface of the packaged chip can be a flat surface, and the bracket carrying the lens can be directly attached to the On the flat surface, the influence of the substrate, chip, and adhesive on the image distance tolerance is effectively subtracted, and the purposes of optimizing the definition of the optical fingerprint imaging, improving the recognition speed, and the user experience are effectively achieved. Furthermore, the TSV aperture on the lower surface of the fingerprint identification chip is pulled to the edge position of the fingerprint identification chip 201 by the conductive layer through the conductive layer, so as to achieve the purpose of packaging the fingerprint identification chip.

In some possible implementation manners, the fingerprint identification chip is provided with a plurality of the first pads, the chip packaging structure is provided with a plurality of the connection ends, and an upper surface and a lower surface of the fingerprint identification chip are provided. A plurality of TSVs are arranged between the conductive layers, and the conductive layer is formed with an opening, so that the conductive layer is divided into a plurality of conductive units, and each or more of the first pads pass one or more of the TSVs and one or more Each of the conductive units is electrically connected to one of the connection terminals.

In some possible implementation manners, the lower surface of the fingerprint identification chip is an inverted trapezoid or a multi-step inverted trapezoid, and the connection end is disposed on the lower surface of the inverted trapezoid or the multi-step inverted trapezoid.

In some possible implementation manners, the chip packaging structure further includes: a filter, and the filter is attached to an upper surface of the fingerprint identification chip.

According to a third aspect, a method for packaging a chip is provided, which includes: forming a groove structure in a substrate; fixing a fingerprint recognition chip in the groove structure; and forming a conductive layer over the substrate by using a plating process. The first pad of the fingerprint identification chip is electrically connected to the connection end of the chip packaging structure for electrical connection with the outside through the conductive layer.

In some possible implementation manners, the fingerprint identification chip is provided with a plurality of the first pads, the chip packaging structure is provided with a plurality of the connection ends, and the method further includes: removing the fingerprint identification chip. The conductive layer directly above to divide the conductive layer into a plurality of conductive units, and each or more of the first pads are connected to one or more of the conductive pads through one or more of the conductive units. Connection end.

In some possible implementation manners, the method further includes: forming a protective layer on an upper surface of the conductive layer by using a coating process; forming a window on the protective layer, and opening the window on the conductive layer. The connection ends are generated inside.

In some possible implementation manners, the method further includes: removing the protective layer directly above the fingerprint identification chip to form an opening, so that the reflected light formed by finger reflection passes through the opening of the protective layer. And received by the fingerprint identification chip.

In some possible implementation manners, the method further includes: setting a TSV between the conductive layer and a lower surface of the substrate by using a TSV TSV process; at a TSV aperture of the lower surface of the substrate, Generating said connecting end.

In some possible implementation manners, before the forming a conductive layer over the substrate by using a coating process, the method further includes: forming an insulating layer on an upper surface of the substrate by using a coating process, so that the insulating layer is formed on the insulating layer. The conductive layer is formed on the upper surface of the substrate; the insulating layer directly above the fingerprint identification chip is removed to form an opening, so that the reflected light formed by finger reflection passes through the opening of the insulating layer and is fingerprinted by the fingerprint. Recognize chip reception.

In some possible implementation manners, the fixing the fingerprint identification chip in the groove structure includes: fixing the fingerprint identification chip in the groove structure by liquid or solid glue; wherein the concave The depth of the groove structure is the sum of the thickness of the fingerprint identification chip and the thickness of the glue.

In some possible implementation manners, the method further includes: attaching a filter on an upper surface of the fingerprint identification chip.

In some possible implementation manners, the connection end is a second pad or a solder ball.

In some possible implementation manners, the fingerprint identification chip includes a plurality of chips arranged along a parallel direction and / or a vertical direction of an upper surface of the substrate.

In some possible implementation manners, the method further includes: setting a bracket and a lens above the substrate; wherein the lens is fixed above the fingerprint recognition chip through the bracket, and the lens and the The fingerprint identification chip is aligned.

In some possible implementation manners, the lens and the bracket are provided integrally or separately.

In a fourth aspect, a method for packaging a chip is provided, including:

A TSV TSV process is used to set a TSV TSV between the upper and lower surfaces of the fingerprint identification chip; a coating process is used to form a conductive layer on the lower surface of the fingerprint identification chip, and the first pad of the fingerprint identification chip It is electrically connected to one end of the conductive layer through TSV; at the other end of the conductive layer, a connection end for electrical connection with the outside is generated.

In some possible implementation manners, the fingerprint identification chip is provided with a plurality of the first pads, the chip packaging structure is provided with a plurality of the connection ends, and an upper surface and a lower surface of the fingerprint identification chip are provided. A plurality of TSVs are provided between the two, and the method further includes: dividing the conductive layer into a plurality of conductive units by forming an opening in the conductive layer, and each or more of the first pads are passed through one or more The TSVs and one or more of the conductive units are electrically connected to one or more of the connection terminals.

In some possible implementation manners, the lower surface of the fingerprint identification chip is an inverted trapezoid or a multi-step inverted trapezoid, and the connection end is disposed on the lower surface of the inverted trapezoid or the step inverted trapezoid.

In some possible implementation manners, the method further includes: attaching a filter on an upper surface of the fingerprint identification chip.

According to a fifth aspect, a terminal device is provided, including a chip packaging structure prepared according to the method for packaging a chip according to the second aspect.

In some possible implementation manners, the terminal device further includes a screen, and the chip package structure is disposed below the screen.

According to a sixth aspect, a terminal device is provided, including a chip packaging structure prepared according to the method for packaging a chip according to the third aspect.

In some possible implementation manners, the terminal device further includes a screen, and the chip package structure is disposed below the screen.

In the embodiment of the present application, the fingerprint identification chip is avoided from being packaged by a conventional wire bonding method. Instead, the first pad of the fingerprint identification chip is pulled to the edge position of the chip packaging structure through a metal layer and / or TSV, so that the package The upper surface of the rear chip can be a flat surface, which reduces the image distance tolerance. Furthermore, the lens-mounted bracket can be directly pasted on a flat surface, effectively reducing the influence of the substrate, chip, and adhesive on the image distance tolerance, greatly optimizing the definition of optical fingerprint imaging, improving the recognition speed and use. Experience.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic structural diagram of a chip package structure according to an embodiment of the present application.

FIG. 2 is a schematic block diagram of a chip package structure integrated with a protective layer and an insulating layer.

FIG. 3 is a schematic block diagram of a chip package structure integrated with a filter.

FIG. 4 is a schematic structural diagram of a connection end placed on a lower surface of a chip package structure.

FIG. 5 is a schematic block diagram of a chip package structure integrated with a lens and a holder.

FIG. 6 is another schematic structural diagram of a chip package structure according to an embodiment of the present application.

FIG. 7 is another schematic block diagram of a chip package structure with an integrated filter.

FIG. 8 is another schematic block diagram of a chip packaging structure integrated with a lens and a holder.

FIG. 9 is a schematic flowchart of a chip packaging method according to an embodiment of the present application.

FIG. 10 is another schematic flowchart of a chip packaging method according to an embodiment of the present application.

FIG. 11 is a schematic block diagram of a terminal device according to an embodiment of the present application.

detailed description

The technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application.

Hereinafter, the chip package structure according to the embodiment of the present application will be described in detail with reference to FIGS. 1 to 8.

It should be noted that, for ease of description, in the embodiments of the present application, the same reference numerals denote the same components, and for the sake of brevity, detailed descriptions of the same components are omitted in different embodiments.

It should be understood that the dimensions, such as the thickness, length, and width of various components, and the overall thickness, length, and width of the chip package structure shown in the embodiments of the application shown in the drawings are only illustrative, and should not constitute any limited.

FIG. 1 is a schematic structural diagram of a chip package structure 100 according to an embodiment of the present application. As shown in FIG. 1, the chip package structure 100 includes: a fingerprint identification chip 101, a substrate 102, and a conductive layer 104, wherein a groove structure is formed on the upper surface of the substrate 102; the fingerprint identification chip 101 is located in the groove structure, and the fingerprint is The identification chip 101 is provided with a first pad 106; the conductive layer 104 is located above the substrate 102.

In the embodiment of the present application, the fingerprint identification chip 101 is embedded in the substrate 102 through a groove structure, so that the upper surface of the packaged chip can be a flat surface, and the lens mount can be directly stuck on the flat surface, which effectively reduces The influence of the substrate 102, the fingerprint identification chip 101, and the adhesive on the image distance tolerance is eliminated, and the purposes of optimizing the definition of the optical fingerprint imaging, improving the identification speed and the use experience are achieved. Further, the first pad 106 of the fingerprint identification chip is pulled to the surface position of the substrate 102 through the conductive layer 104 through the conductive layer 104 to reach the purpose of packaging the fingerprint identification chip 101.

It should be noted that before the fingerprint identification chip 101 enters the packaging factory, a pad (Pad) has been prepared on one surface, for example, the first pad 106 shown in FIG. 1, the first pad 106 passes The conductive layer 104 is electrically connected to a connection terminal 107 of the chip package structure for electrical connection with the outside. The first pad 106 can be understood as a pin of the fingerprint identification chip 101 connected to the outside. In the embodiment of the present application, the upper surface of the fingerprint identification chip 101 is the side on which the pads have been prepared before entering the packaging factory, and the side opposite to the fingerprint identification chip 101 is the lower surface of the fingerprint identification chip 101, so Before the lower surface of the fingerprint identification chip 101 enters the packaging factory, no pads are prepared, and they are used to adhere to the upper surface of the groove in the substrate 102.

The fingerprint identification chip 101 may be, for example, an optical fingerprint identification chip, and may specifically include an optical biometric sensor with an optical sensing array, such as an optical fingerprint sensor; the optical sensing array may include a plurality of optical sensing units for implementing biological features. Induction operation. The optical sensing array of the fingerprint identification chip 101 may also specifically be a photodetector array, which includes a plurality of photodetectors distributed in an array, and the photodetectors may serve as the optical sensing unit as described above. .

Taking the fingerprint recognition technology under the screen as an example, the area where the optical sensing array is located is the sensing area of the fingerprint recognition chip 101. The sensing area may be located below the display area of the display screen. Therefore, when the user needs to unlock the terminal device or verify other biometrics, he only needs to press his finger on the display screen, The optical sensing array of the sensing area can perform fingerprint sensing operation.

It should be understood that the fingerprint identification chip 101 is an optical fingerprint sensor and is merely an example. In other alternative embodiments, the fingerprint identification chip 101 may also use ultrasound or other types of fingerprint identification modules, for example, the optical biometrics. The characteristic sensor may be replaced by an ultrasonic fingerprint sensor or another type of fingerprint sensor. The application does not specifically limit the type and specific structure of the fingerprint identification chip 101 as long as the above-mentioned fingerprint identification chip 101 can meet the performance requirements for fingerprint identification.

The fingerprint identification chip 101 may further include a plurality of chips arranged along a parallel direction and / or a vertical direction of the upper surface of the substrate 102. That is, a plurality of chips arranged along a parallel direction and / or a vertical direction of the upper surface of the substrate 102 can be packaged in a package structure, and the plurality of chips can realize signal transmission through an electrical connection.

The connection terminal 107 may be a second pad or a solder ball, or other connection members for achieving electrical connection with the outside, which is not limited in the embodiment of the present application. For example, the connection terminal 107 may be a solder joint or a pad or a connection terminal in any form for electrically connecting with a flexible printed circuit (FPC), and the fingerprint identification chip 101 may be electrically connected through the connection terminal 107. To the FPC. For example, when the connection terminal 107 is a second pad, the fingerprint identification chip 101 may be soldered to the FPC through the second pad. Therefore, the fingerprint identification chip 101 can implement electrical interconnection and signal transmission with other peripheral circuits or other components of the device to which the fingerprint identification chip 101 belongs through the FPC. For example, the fingerprint identification chip 101 may receive a control signal from a processing order of a device to which the fingerprint identification chip 101 belongs through the FPC, and may further output the fingerprint image to the fingerprint identification chip 101 through the FPC. The processing unit or control unit of the equipment.

The fingerprint identification chip 101 can be fixed in the groove structure by liquid or solid glue. Taking glue as an example, the depth of the groove structure can be the sum of the thickness of the fingerprint identification chip 101 and the thickness of the glue. However, the embodiment of the present application is not limited thereto. For example, in other embodiments, the depth of the groove structure may be greater than or less than the sum of the thickness of the fingerprint identification chip 101 and the thickness of the glue. The glue can be realized, for example, as a hydrogel. The hydrogel may include a single component or multiple components. In a specific implementation thereof, a lower surface of the fingerprint identification chip 101 and an upper surface in the groove structure may be fixedly connected based on a physical process and / or a chemical process of a hydrogel.

It should be understood that the number and positions of the first pads 106 in the chip package structure shown in FIG. 1 are merely examples and are not limiting.

For example, the upper surface of the fingerprint identification chip 101 may include a plurality of first pads 106, and the first pads 106 may be evenly or unevenly distributed on the upper surface of the fingerprint identification chip 101. Correspondingly, the chip package structure 100 may include a plurality of connection terminals 107, and the conductive layer 104 may be configured to connect one or more of the plurality of first pads 106 to the first pads 106 and the first pads 106. One or more of the plurality of connection terminals 107 are electrically connected.

For another example, the first pad 106 shown in FIG. 1 directly protrudes from the surface of the fingerprint identification chip 101 with the same thickness as the conductive layer 104, and is located at the edge of the conductive layer 104, and the side of the first pad 106 is exposed. However, the embodiments of the present application are not limited to this. For example, in other alternative embodiments, the first pad 106 is disposed on the fingerprint identification chip 101, and the upper surface of the fingerprint identification chip 101 is a flat surface.

Take the fingerprint identification chip 101 provided with a plurality of first pads 106 and the chip package structure 100 provided with a plurality of connection terminals 107 as an example. In one implementation, the conductive layer 104 may be formed with an opening directly above the fingerprint identification chip 101 so that the conductive layer 104 may be divided into multiple conductive units, wherein one or more first pads 106 The one or more conductive units are connected to the one or more connection terminals 107, thereby ensuring that the plurality of first pads 106 are electrically connected to the plurality of connection terminals 107 of the chip package structure 100, respectively. In another implementation, the conductive layer 104 may be designed as a redistribution layer (RDL), thereby not only reallocating the first pad 106 on the fingerprint identification chip 101 to the redistribution layer (RDL). The position of the edge of the substrate does not change the layout structure of the first pads 106 of the fingerprint identification chip 101. Correspondingly, when the fingerprint identification chip 101 includes multiple chips, the first pad of each chip may be electrically connected to the connection terminal 107 of the chip package structure 100 through a respective conductive unit.

FIG. 2 is a schematic block diagram of a chip package structure 100 integrated with a protective layer 105 and an insulating layer 103. As shown in FIG. 2, the chip packaging structure 101 may further include a protective layer 105 formed on the upper surface of the conductive layer 104 to prevent the fingerprint identification chip 101 from being damaged during handling and installation. When the chip package structure 100 of the embodiment of the present application performs fingerprint recognition under the screen, a finger presses the display screen, and the reflected light emitted by the display screen and formed by reflection of the finger needs to pass through the protective layer 105 to reach the fingerprint recognition chip 101, that is, a light signal actually received by the fingerprint identification chip 101 is a light signal reflected by a finger and passed through the protective layer 105. Therefore, in order to avoid excessive consumption of the optical signal reflected by the fingers when passing through the protective layer 105, in the embodiment of the present application, an opening may be formed directly above the fingerprint identification chip 101 for the protective layer 105. So that the reflected light formed by the finger reflection passes through the opening of the protective layer 105 and is received by the fingerprint identification chip 101.

Since the protective layer can use any protective type material, for example, an insulating material. In order to ensure that the connection end 107 of the chip packaging structure 100 can be electrically connected to the outside world, in the embodiment of the present application, an opening window may be formed on the protection layer 105, and the connection end 107 may be provided at The window is formed on the conductive layer 104.

Referring to FIG. 2, the chip package structure 101 may further include an insulating layer 103. The insulating layer 103 is disposed between the substrate 102 and the conductive layer 104. The insulating layer 103 can reduce electrical signals in the substrate 102 to the conductive layer 104. For example, when the fingerprint identification chip 101 and the connection terminal 107 perform signal interaction, the current of the conductive layer 104 is prevented from flowing to the substrate 102, thereby ensuring the reliability of the fingerprint identification chip 101 and the connection terminal 107 during signal transmission. Correspondingly, in order to avoid excessive consumption of the optical signal reflected by the fingers when passing through the insulating layer 103, in the embodiment of the present application, similar to the protective layer 105, for the insulating layer 103, the fingerprint identification chip 101 An opening may also be formed directly above, so that the reflected light formed by the finger reflection passes through the opening of the insulating layer 103 and is received by the fingerprint identification chip 101.

It should be understood that the structure shown in FIG. 2 is only an example, and the embodiment of the present application is not limited thereto.

For example, in other alternative embodiments, the chip package structure 101 may not include the insulating layer 103.

For another example, the connection manner between the conductive layer 104 shown in FIG. 2 and the first pad of the fingerprint identification chip 101 is merely an example, and the embodiment of the present application is not limited thereto.

For example, in other alternative embodiments, the first pad 106 is disposed on the fingerprint identification chip 101, and the upper surface of the fingerprint identification chip 101 is a flat surface. In this case, the insulating layer 103 may have conductive holes at the relative positions of the first pads 106. The conductive layer 104 may pass through the conductive holes of the insulating layer 103 and the first pads 106 on the fingerprint identification chip 101. connection.

FIG. 3 is a schematic block diagram of a chip package structure 100 with an integrated filter 109. As shown in FIG. 3, the chip packaging structure 100 may further include a filter 109, which is adhered to the upper surface of the fingerprint identification chip 101 to reduce undesired background light in fingerprint sensing. In order to improve the optical sensing of the fingerprint recognition chip 101 to the received light. The filter 109 can be used to filter out the wavelength of ambient light, for example, near-infrared light and some red light. For example, human fingers absorb most of the energy of light with a wavelength below ~ 580nm. If one or more optical filters or optical filter coatings can be designed to filter light from 580nm to infrared, the ambient light can be greatly reduced Impact on optical detection in fingerprint sensing.

The filter 109 may specifically include one or more optical filters, and the one or more optical filters may be configured as, for example, a band-pass filter to allow transmission of light emitted by the OLED pixels while blocking light in the sunlight. Other light components such as infrared light. This optical filtering can effectively reduce background light caused by sunlight when the device is used outdoors. The one or more optical filters may be implemented, for example, as an optical filter coating, which is formed on one or more continuous interfaces, or may be implemented as one or more discrete interfaces. It should be understood that the filter 109 can be fabricated on the surface of any optical component, or along the optical path of the reflected light formed by finger reflection to the fingerprint identification chip 101. The embodiment of the present application only uses the upper surface of the filter 109 as an example, but the present application is not limited thereto. For example, the filter 109 may be attached to a bottom surface of a display, a prism surface, or the inside of the fingerprint identification chip 101.

It should be understood that the number, position, and specific structure of the protective layer 105 and the insulating layer 103 shown in FIG. 2 and the filter 109 shown in FIG. 3 are merely exemplary descriptions, which are not limited in the embodiment of the present application. For example, whether to add one or more of the protective layer 105, the insulating layer 103, and the filter 109 may be determined according to the actual needs of the fingerprint identification chip 101.

It should also be understood that the connection end 107 shown in FIGS. 1 to 3 on the upper surface of the chip packaging structure 100 is merely an example, and the embodiment of the present application is not limited thereto. For example, the connection end 107 may also be disposed on a lower surface of the chip package structure. In the following, a fan-out advanced packaging process and a fan-in advanced packaging process are used to briefly describe the connection terminal setting method in the embodiment of the present application. In the embodiment of the present application, the so-called Fan-out That is, the pin of the fingerprint identification chip 101 (that is, the first pad 106) is pulled to a via pad through a Through Silicon Via (TSV). Specifically, the conductive layer 104 can be used to draw the pin The first pad 106 is pulled out for a distance, and a TSV is hit at the pulling position of the first pad 106. This TSV can electrically connect the conductive layer 104 to the lower surface of the substrate 102. Thereby, the first pad 106 on the upper surface of the fingerprint identification chip 101 is pulled to the lower surface of the substrate 102 and a connection end 107 is formed. The so-called Fan-in is to pull the pin of the fingerprint identification chip 101 (that is, the first pad 106) to the edge position of the fingerprint identification chip 101 through a Through Silicon Via (TSV), specifically, Ground, a TSV can be directly placed on the position of the first pad 106, and this TSV can electrically connect the first pad 106 to the lower surface of the fingerprint identification chip 101. Thereby, the first pad 106 on the upper surface of the fingerprint identification chip 101 is pulled to the lower surface of the fingerprint identification chip 101 and a connection end 107 is formed.

FIG. 4 is a schematic structural diagram of the connection end 107 placed on the lower surface of the chip packaging structure 100 (ie, the Fan-out advanced packaging process). As shown in FIG. 4, a through silicon via (TSV) is formed between the conductive layer 104 and the lower surface of the substrate 102. The connection terminal 107 is provided at the TSV hole on the lower surface of the substrate 102. The conductive layer 104 passes through The TSV is electrically connected to the connection terminal 107. In some implementations, as shown in FIG. 4, a conductive material may be provided in the TSV, and the conductive layer 104 may be electrically connected to the first TSV hole through the conductive material in the TSV. The three pads 110 may be formed on the third pads 110 with connection ends 107 in the form of solder balls.

It should be understood that the embodiments of the present application are intended to illustrate that the conductive layer 104 can be electrically connected to the connection end 107 provided on the lower surface of the substrate 102 through through silicon vias. The number, location, and specific implementation of the through silicon vias shown in FIG. Not limiting. For example, the upper surface of the fingerprint identification chip 101 may include a plurality of first pads 106. Accordingly, the chip package structure 100 (ie, the lower surface of the substrate 102) may include a plurality of connection ends 107. The TSV may be configured to electrically connect one or more of the plurality of first pads 106 to one or more of the plurality of connection terminals 107.

Taking the chip package structure 100 provided with multiple connection terminals 107 as an example, in one implementation, the chip package structure is provided with multiple TSVs, so that one or more first pads 106 can pass one TSV and one Or a plurality of connection terminals 107 are electrically connected. In another implementation, the chip packaging structure can set TSV on the back of each pad 106, and the conductive material in the TSV can be designed as RDL, thereby not only realizing the fingerprint identification The first pads 106 on the chip 101 are redistributed to the lower surface of the substrate 102, and the layout structure of the first pads 106 on the fingerprint identification chip 101 is not changed.

It should also be understood that the Fan-out advanced packaging process shown in FIG. 4 is only an example of pulling the first pad 106 on the fingerprint identification chip 101 to the lower surface of the substrate 102, but the embodiment of the present application is not It is limited to this packaging process and the specific structure shown in FIG. 4.

FIG. 5 is a schematic block diagram of a chip package structure 100 integrated with a lens 201 and a holder 202. As shown in FIG. 5, the chip packaging structure 100 may further include a bracket 202 and a lens 201; the lens 201 is fixed above the fingerprint identification chip 101 through the bracket 202, and the lens 201 is aligned with the fingerprint identification chip 101.

In the embodiment of the present application, the lens 201 and the bracket 202 may be provided integrally or separately. The so-called integrated arrangement means that the lens 201 and the bracket 202 are integrated. For example, the lens 201 is fixed on the bracket 202 in a non-detachable manner. The so-called separate setting means that the lens 201 and the bracket 202 are detachably fixed to the bracket 202. The integrated setting can simplify processing and assembly, and optimize module yield. The separation setting can make the image distance tolerance originally affected by multi-layers affected only by the deformation and tolerance value of the lens itself, further reducing the image distance tolerance, optimizing the clarity of optical fingerprint imaging, improving the recognition speed and The use experience also reduces the difficulty of replacing the lens 201, which can effectively reduce costs.

The lens 201 may be any device or component for performing optical path modulation, such as a spherical or aspherical lens of a 1P or multiple P lens. Specifically, it may be a transmissive or reflective lens. The lens 201 is used to achieve a desired high imaging resolution. In practice, when the chip package structure 100 is applied to fingerprint recognition under the screen, the lens 201 reflects the reflected light formed by the finger reflection and reflects the reflected light onto the fingerprint recognition chip 101. Taking the lens 201 as an example, the effective aperture of the lens 201 can be designed to be larger than the aperture in the OLED display layer, which allows light to pass through the OLED display layer for optical fingerprint sensing. This design can reduce the undesired effects of the wiring structure and other scattering objects in the OLED display module.

The bracket 202 may be a device or element for supporting or fixing the lens 201. For example, the bracket 202 may be another element for fixing the lens 201 to a terminal device to which the chip package structure 100 belongs. Or device, for example, when the chip package structure 100 is mounted on a mobile phone that can perform fingerprint recognition under the screen, the bracket 202 may be fixedly connected to some devices or components of the mobile phone. For example, the bracket 202 may be fixed to The mobile phone's middle frame, back cover, motherboard, and battery are easy to remove. Furthermore, the bracket 202 can be fixed to the lower surface of the display screen of the mobile phone.

FIG. 6 is a schematic structural diagram of a chip packaging structure 300 according to another embodiment of the present application (that is, a connection end 307 is provided on a lower surface of the fingerprint identification chip 301 by using a Fan-in advanced packaging process). As shown in FIG. 6, the chip package structure 300 includes a fingerprint recognition chip 301, a first pad 306 is provided on an upper surface of the fingerprint recognition chip 301, and a TSV is provided between an upper surface and a lower surface of the fingerprint recognition chip 301. The lower surface of the identification chip 301 is provided with a conductive layer 304. The first pad 306 is electrically connected to one end of the conductive layer 304 through TSV. The other end of the conductive layer 304 is connected to the connection end 307 of the chip package structure 300 for electrical connection with the outside. Electrical connection. In some implementations, a conductive material may be provided in the TSV shown in FIG. 6, and the first pad 306 may be electrically connected to the third TSV opening through the conductive material in the TSV. A pad 310, a connection end 307 similar to a solder ball can be formed on the third pad 310.

In the embodiment of the present application, the first pad 306 of the fingerprint identification chip 301 is pulled to the lower surface of the fingerprint identification photo 301 by TSV, so that the upper surface of the packaged chip can be a flat surface, so that a lens mount can be mounted. Directly pasted on a flat surface, the influence of the substrate, chip, and adhesive on the image distance tolerance is effectively subtracted, and the purposes of optimizing the definition of the optical fingerprint imaging, improving the recognition speed, and using experience are effectively achieved. Further, the TSV aperture on the lower surface of the fingerprint identification chip 301 is pulled to the edge position of the fingerprint identification chip 201 by the conductive layer 304 through the conductive layer 304 to reach the purpose of packaging the fingerprint identification chip 301.

It should be noted that, in the embodiment of the present application, the first pad 306 may be understood as a pad (Pad) prepared on one surface of the fingerprint identification chip 301 before entering the packaging factory, for example, as shown in FIG. 1 The first pad 106 shown in the figure is electrically connected to a connection terminal 307 of the chip package structure 300 for electrical connection with the outside through a TSV. In the embodiment of the present application, the upper surface of the fingerprint identification chip 301 is the side on which the pad is prepared before entering the packaging factory, and the side opposite to the fingerprint identification chip 301 is the lower surface of the fingerprint identification chip 301, so The connection terminal 307 is not prepared on the lower surface of the fingerprint identification chip 301 before entering the packaging factory. In other words, the connection end 307 of the fingerprint identification chip 301 is prepared after the fingerprint identification chip 301 enters a packaging factory. Specifically, the first pad 306 may be first exposed from the lower surface of the fingerprint identification chip 301 by using a TSV process, and then the connection end 307 may be generated at a position where the lower surface of the fingerprint identification chip 301 is exposed, or The first pad 306 may also be guided to a specific position on the lower surface of the fingerprint identification chip 301, and the connection end 307 is generated at the specific position. The embodiment of the present application does not specifically limit the connection end 307 In a specific position on the lower surface of the fingerprint identification chip 301, as long as the first pad 306 on the upper surface of the fingerprint identification chip 301 is electrically connected to the lower surface of the fingerprint identification chip 301, all fall into the embodiment of the present application. Scope of protection.

Referring to FIG. 6, the lower surface of the fingerprint identification chip 301 may be an inverted trapezoid or a multi-step inverted trapezoid, and the connection end 307 may be disposed on the lower surface of the inverted trapezoid or a multi-step inverted trapezoid. But the embodiment itself is not limited to this. For example, in other alternative embodiments, the lower surface of the fingerprint identification chip 301 may also be presented as a plurality of steps or bosses, or may be a part of a polygon or a part of a circle, and so on.

It should be understood that the number, locations, and specific implementations of the TSVs shown in FIG. 6 are merely examples and are not limiting. For example, the upper surface of the fingerprint identification chip 301 may include a plurality of first pads 306, and the first pads 306 may be evenly or unevenly distributed on the upper surface of the fingerprint identification chip 301. Correspondingly, the chip package structure 300 (ie, the lower surface of the fingerprint identification chip 301) may include a plurality of connection terminals 307, and the TSV may be configured to connect the The one or more first pads 306 are electrically connected to one or more of the plurality of connection terminals 307. For another example, the connection end in the embodiment of the present application may be a solder ball generated on the third pad 310 as shown in FIG. 6, or may be the third pad 310 directly. The embodiments of the present application are not specifically limited.

Take the fingerprint identification chip 301 provided with a plurality of first pads 306 and the chip package structure 300 provided with a plurality of connection terminals 307 as an example. In one implementation, a plurality of TSVs are provided between the upper surface and the lower surface of the fingerprint identification chip 301, and the conductive layer 304 is formed with an opening, so that the conductive layer 304 is divided into a plurality of conductive units, one or The plurality of first pads 306 are electrically connected to one or more of the connection terminals 307 through one or more of the TSVs and one or more of the conductive units, thereby ensuring that the plurality of first The pads 306 are electrically connected to a plurality of connection terminals 307, respectively.

It should also be understood that the Fan-in advanced packaging process shown in FIG. 6 is only an example of pulling the first pad 106 on the fingerprint identification chip 101 to the lower surface of the fingerprint identification chip 101, but the embodiment of the present application It is not limited to this packaging process and the specific structure shown in FIG. 6.

FIG. 7 is a schematic block diagram of a chip package structure 300 integrated with a filter 309. As shown in FIG. 7, as shown in FIG. 7, the chip packaging structure 300 may further include a filter 309, and the filter 309 is attached to the upper surface of the fingerprint identification chip 301. As shown in FIG. 7, the filter 309 and the upper surface of the fingerprint identification chip 301 are bonded together by glue 308. FIG. 8 is a schematic block diagram of a chip package structure 300 integrated with a lens 401 and a bracket 402. As shown in FIG. 8, the lens 401 is fixed on the bracket 402, and the bracket is attached to the upper surface of the filter 309.

It should be understood that the fingerprint identification chip 301, the conductive layer 304, the first pad 306, the third pad 310, the connection end 307, the filter 309, the lens 401, and the bracket 402 shown in FIGS. 6 to 8 can be respectively seen in the drawings. The corresponding descriptions of the fingerprint identification chip 101, the conductive layer 104, the first pad 106, the third pad 110, the connection end 107, the filter 109, the lens 201, and the bracket 202 shown in FIGS. 1 to 5 are omitted to avoid repetition. I will not repeat them here.

In summary, the fingerprint identification chip in the embodiment of the present application avoids traditional wire bonding for packaging. Instead, the first pad of the fingerprint identification chip is pulled to the edge of the chip packaging structure through a metal layer and / or TSV. The position allows the upper surface of the packaged chip to be a flat surface, reducing the image distance tolerance. Furthermore, the lens mount is further integrated into the chip package structure, so that the image distance tolerance originally affected by multi-layers is only affected by the deformation and tolerance of the bracket itself, thereby reducing the image distance tolerance. Greatly optimized the clarity of optical fingerprint imaging, improving recognition speed and user experience.

The specific embodiments of the chip packaging structure of the present application are described in detail above with reference to FIGS. 1 to 8, and the following is a detailed description of the chip packaging structure shown in FIG. 1 to FIG. 5 with reference to FIGS. 9 and 10. The structure 100 and a method of manufacturing the chip package structure 300 shown in FIGS. 6 to 8.

FIG. 9 is a schematic flowchart of a chip packaging method 500 according to an embodiment of the present application. The method 500 may be used to prepare the chip package structure 100 shown in FIG. 1 to FIG. 5. The method 500 includes part or all of the following:

S510, a groove structure is formed in the substrate.

S520. The fingerprint identification chip is fixed in the groove structure.

S530, a conductive layer is formed on the substrate by a coating process, and the first pad of the fingerprint identification chip is electrically connected to the connection end of the chip packaging structure for electrical connection with the outside through the conductive layer.

In S510, the basic structure can be first ground to a required size (such as thickness), and then the groove structure required by the process, such as the shape of the groove structure, can be processed by etching, laser, or machine drilling. It may be similar to or the same as the shape of the fingerprint identification chip, and for example, the groove structure needs to accommodate or at least accommodate the fingerprint identification chip and a material (such as glue) for mounting the fingerprint identification chip, wherein the substrate may be Refers to an element or device made of an inorganic material such as silicon wafer, glass, or ceramic. The fingerprint identification chip can be made into an element or device that matches the groove structure by grinding or cutting.

In S520, the fingerprint identification chip may be fixed in the groove structure by using a substance with adhesive properties such as water glue or solid glue. The hydrogel may include a single component or multiple components. In a specific implementation thereof, a lower surface of the fingerprint identification chip and an upper surface in the groove structure may be fixedly connected based on a physical process and / or a chemical process of a hydrogel. In some implementations, the fingerprint recognition chip can be fixed in the groove structure by liquid or solid glue; wherein the depth of the groove structure is the sum of the thickness of the fingerprint recognition chip and the thickness of the glue.

In S530, the processing process of the conductive layer can use metal plating processes such as sputtering, electroplating, and evaporation, and the material can be any metal with good conductivity, such as aluminum, copper, nickel, silver, and gold. In some implementations, the conductive layer is a micro-scale coating

It should be understood that FIG. 9 is only an example of a method for preparing a chip package structure in the embodiment of the present application, and the embodiment of the present application is not limited thereto.

For example, in order to reduce the influence of the substrate on the electrical signals in the conductive layer, the method shown in FIG. 9 may further include: before forming the conductive layer over the substrate, forming an insulating layer on the upper surface of the substrate by a plating process so as to insulate the substrate. The upper surface of the layer forms a conductive layer. Wherein, the coating process of the insulating layer may use organic coating processes such as spray coating, spin coating, film coating, and silk screen printing, and the insulating layer may be made of any insulating material. The insulating layer may be a micro-scale coating.

For another example, in order to avoid damage to the fingerprint identification chip during the transportation and installation process, the method shown in FIG. 9 may further include: forming a protective layer on the upper surface of the conductive layer by using a plating process. The coating process of the protective layer may use an organic film plating process such as spray coating, spin coating, film coating, and silk screen printing. The material of the protective layer may be any insulating material. The protective layer may be a micro-scale coating. In one implementation, in order to realize the design that the connection end is located on the upper surface of the conductive layer, a window may be formed in the protective layer, and the connection end may be generated in the window on the conductive layer. Specifically, the window opening may be formed at a specified position on the substrate, and the upper surface of the conductive layer at the window opening is generated by using a process such as ball implantation, tin printing, tin plating, and copper plating pillars to generate the window. Connection end for subsequent module assembly. In another implementation, in order to realize that the connection end is located on the lower surface of the substrate, a TSV process may be used to set a TSV between the conductive layer and the lower surface of the substrate; and at the TSV aperture of the lower surface of the substrate, Generate the connection end. The TSV process may include, but is not limited to, processes such as etching, laser, and machine drilling.

For another example, in order to avoid excessive consumption of the optical signal reflected by a finger when passing through the protective layer 105 and improve the lighting effect of the fingerprint identification chip, in the embodiment of the present application, the method shown in FIG. 9 may also be used. The method includes: removing the insulation layer directly above the fingerprint identification chip to form an opening, so that the reflected light formed by finger reflection passes through the opening of the insulation layer and is received by the fingerprint identification chip. Similarly, the method shown in FIG. 9 may further include: removing the protective layer directly above the fingerprint identification chip to form an opening, so that the reflected light formed by finger reflection passes through the opening of the protective layer and is received by the fingerprint identification chip.

For another example, in order to reduce the undesired background light received by the fingerprint recognition chip during fingerprint sensing, to improve the optical sensing of the received light by the fingerprint recognition chip. For example, the method shown in FIG. 9 may further include: attaching a filter on an upper surface of the fingerprint identification chip. The optical filter may be a light-transmitting material such as optical glass or a sapphire chip that filters out light of a specified wavelength by coating.

As another example, the method shown in FIG. 9 may further include: setting a bracket and a lens above the substrate; wherein the lens is fixed above the fingerprint recognition chip through the bracket, and the lens is aligned with the fingerprint recognition chip. In a specific implementation, the contact surface bonded to the bracket may be an upper surface of an RDL (for example, a conductive layer), or an upper surface of a passivation layer (for example, a protective layer) and a protective layer, or may be a silicon material The upper surface of the surface (for example, the substrate) may be the upper surface of the filter. This embodiment of the present application does not specifically limit this. The lens and the bracket may be provided integrally or separately. The integrated setting can simplify processing and assembly, and optimize module yield. The separation setting can make the image distance tolerance originally affected by multi-layers affected only by the deformation and tolerance value of the lens itself, further reducing the image distance tolerance, optimizing the clarity of optical fingerprint imaging, improving the recognition speed and Use experience. It also reduces the difficulty of lens replacement, which can effectively reduce costs. The lens may be a spherical or aspherical lens of a 1P or multiple P lens. The preparation process for setting the bracket and the lens may be injection molding, photolithography, or wafer-level packaging (WLO) processes.

In addition, when the fingerprint identification chip is provided with a plurality of first pads, and the chip packaging structure needs to be provided with multiple connection terminals, the method shown in FIG. 9 may further include: removing the conductive layer directly above the fingerprint identification chip to The conductive layer is divided into a plurality of conductive units, and each one or more first pads are connected to one or more connection terminals through one or more conductive units.

FIG. 10 is a schematic flowchart of a chip packaging method 600 according to an embodiment of the present application. As shown in FIG. 10, the method 600 includes all or part of the following:

S610, a TSV process is used to set a TSV between the upper and lower surfaces of the fingerprint recognition chip;

S620, a conductive layer is formed on the lower surface of the fingerprint identification chip by a coating process, and the first pad of the fingerprint identification chip is electrically connected to one end of the conductive layer through TSV;

S630. At the other end of the conductive layer, a connection terminal for generating electrical connection with the outside is generated.

It should be understood that FIG. 10 is merely an example of a method for preparing a chip package structure in the embodiment of the present application, and the embodiment of the present application is not limited thereto.

For example, in order to reduce the undesired background light received by the fingerprint recognition chip during fingerprint sensing, to improve the optical sensing of the received light by the fingerprint recognition chip. For example, the method shown in FIG. 10 may further include: attaching a filter on an upper surface of the fingerprint identification chip. The optical filter may be a light-transmitting material such as optical glass or a sapphire chip that filters out light of a specified wavelength by coating.

As another example, the method shown in FIG. 10 may further include: setting a bracket and a lens above the substrate; wherein the lens is fixed above the fingerprint recognition chip through the bracket, and the lens is aligned with the fingerprint recognition chip. Specifically, the first pad of the fingerprint identification chip may be guided to the lower surface of the fingerprint identification chip by using a through-silicon via operation method, and an optical path bracket lens may be pasted on the surface of the filter. The lens and the bracket may be provided integrally or separately. The integrated setting can simplify processing and assembly, and optimize module yield. The separation setting can make the image distance tolerance originally affected by multi-layers affected only by the deformation and tolerance value of the lens itself, further reducing the image distance tolerance, optimizing the clarity of optical fingerprint imaging, improving the recognition speed and Use experience. At the same time, the replacement difficulty of the lens 201 is also reduced, which can effectively reduce costs. The lens may be a spherical or aspherical lens of a 1P or multiple P lens. The process for setting the bracket and lens can be injection molding, photolithography, or wafer-level packaging (WLO).

In addition, when the fingerprint identification chip is provided with a plurality of first pads and the chip packaging structure needs to be provided with multiple connection terminals, the method shown in FIG. 10 may further include: between the upper surface and the lower surface of the fingerprint identification chip. Set multiple TSVs and divide the conductive layer into multiple conductive units by forming openings in the conductive layer. Each or more first pads are electrically connected to one through one or more TSVs and one or more conductive units. Or multiple connections. In some implementations, the lower surface of the fingerprint recognition chip is an inverted trapezoid or a multi-step inverted trapezoid, and the connection end is disposed on the lower surface of the inverted trapezoid or a multi-step inverted trapezoid.

It should be understood that the method embodiment and the chip package structure embodiment may correspond to each other, and similar descriptions may refer to specific embodiments of the chip package structure. For brevity, I will not repeat them here.

It should also be understood that the embodiments of the chip packaging method listed above can be executed by robots or numerically controlled machining methods, and the device software or process for performing the chip packaging method can be executed by executing computer program code stored in a memory Chip packaging method.

An embodiment of the present application provides a terminal device. FIG. 11 is a side view of the terminal device 700 according to the embodiment of the present application. As shown in FIG. 11, the terminal device may include a chip packaging structure 701 and a screen 702. 701 is disposed below the screen 702, and the chip packaging structure 701 may be the chip packaging structure 100 or 300 described above, or a chip packaging structure prepared according to the chip packaging method 500 or method 600 described above.

In some implementations, the terminal device 700 may be a terminal device such as a mobile phone, a tablet computer, or an e-book.

It should be understood that, in the various embodiments of the present application, the size of the sequence numbers of the above processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not deal with the embodiments of the present application. The implementation process constitutes any limitation.

Those of ordinary skill in the art may realize that the units and algorithm steps of each example described in connection with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments, and are not repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods may be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the unit is only a logical function division. In actual implementation, there may be another division manner. For example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, which may be electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objective of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each of the units may exist separately physically, or two or more units may be integrated into one unit.

The above is only a specific implementation of this application, but the scope of protection of this application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in this application. It should be covered by the protection scope of this application. Therefore, the protection scope of this application shall be subject to the protection scope of the claims.

Claims (36)

A chip packaging structure, comprising: A substrate having a groove structure formed on an upper surface of the substrate; A fingerprint recognition chip, which is located in the groove structure, and the fingerprint recognition chip is provided with a first pad; A conductive layer, the conductive layer is located above the substrate, and the first pad is electrically connected to a connection end of the chip package structure for electrical connection with the outside through the conductive layer. The chip package structure according to claim 1, wherein the fingerprint identification chip is provided with a plurality of the first pads, the chip package structure is provided with a plurality of the connection ends, and the conductive layer is An opening is formed directly above the fingerprint identification chip, so that the conductive layer is divided into a plurality of conductive units, and each or more of the first pads are connected to one or more through one or more of the conductive units. The connection end. The chip package structure according to claim 1 or 2, wherein the chip package structure further comprises: A protective layer is formed on the upper surface of the conductive layer, the protective layer is formed with an opening window, and the connection end is disposed in the opening window on the conductive layer. The chip package structure according to claim 3, wherein the protective layer has an opening formed directly above the fingerprint identification chip, so that the reflected light formed by finger reflection passes through the opening of the protective layer and Received by the fingerprint identification chip. The chip package structure according to claim 1 or 2, wherein a through silicon via (TSV) is formed between the conductive layer and the lower surface of the substrate, and the connection end is provided on the lower surface of the substrate. At the TSV aperture, the conductive layer is electrically connected to the connection terminal through the TSV. The chip package structure according to any one of claims 1 to 5, wherein the chip package structure further comprises: An insulating layer disposed between the substrate and the conductive layer, and an opening is formed directly above the fingerprint identification chip so that the reflected light formed by finger reflection passes through the opening of the insulating layer and Received by the fingerprint identification chip. The chip package structure according to any one of claims 1 to 6, wherein the fingerprint identification chip is fixed in the groove structure by liquid or solid glue, and the depth of the groove structure is the depth of the groove structure. The sum of the thickness of the fingerprint recognition chip and the thickness of the glue. The chip package structure according to any one of claims 1 to 7, wherein the chip package structure further comprises: A filter, which is attached to the upper surface of the fingerprint identification chip. The chip package structure according to any one of claims 1 to 8, wherein the connection end is a second pad or a solder ball. The chip package structure according to any one of claims 1 to 9, wherein the fingerprint identification chip comprises a plurality of chips arranged along a parallel direction and / or a vertical direction of an upper surface of the substrate. The chip package structure according to any one of claims 1 to 10, wherein the chip package structure further comprises: Brackets and lenses; The lens is fixed above the fingerprint identification chip through the bracket, and the lens is aligned with the fingerprint identification chip. The chip package structure according to claim 11, wherein the lens and the bracket are provided integrally or separately. A chip packaging structure, comprising: A fingerprint recognition chip having a first pad provided on an upper surface thereof, a through-silicon via TSV provided between an upper surface and a lower surface of the fingerprint recognition chip, and a conductive surface provided on the lower surface of the fingerprint recognition chip Layer, the first pad is electrically connected to one end of the conductive layer through the TSV TSV, and the other end of the conductive layer is electrically connected to a connection end of the chip package structure for electrical connection with the outside . The chip package structure according to claim 13, wherein the fingerprint recognition chip is provided with a plurality of the first pads, the chip package structure is provided with a plurality of the connection terminals, and the fingerprint recognition chip A plurality of TSVs are provided between the upper surface and the lower surface of the conductive layer, and the conductive layer is formed with an opening, so that the conductive layer is divided into a plurality of conductive units, and each or more of the first pads pass The TSV and one or more of the conductive units are electrically connected to one or more of the connection terminals. The chip package structure according to claim 13 or 14, wherein the lower surface of the fingerprint recognition chip is an inverted trapezoid or a multi-step inverted trapezoid, and the connection end is disposed on the inverted trapezoid or the multi-step inverted trapezoid. The lower surface of the trapezoid. The chip package structure according to any one of claims 13 to 15, wherein the chip package structure further comprises: A filter, which is attached to the upper surface of the fingerprint identification chip. A method for packaging a chip, comprising: Forming a groove structure in the substrate; Fixing a fingerprint identification chip in the groove structure; A coating layer is used to form a conductive layer over the substrate, and the first pad of the fingerprint identification chip is electrically connected to the connection end of the chip packaging structure for electrical connection with the outside through the conductive layer. The method according to claim 17, wherein the fingerprint identification chip is provided with a plurality of the first pads, the chip package structure is provided with a plurality of the connection ends, and the method further comprises: Removing the conductive layer directly above the fingerprint identification chip to divide the conductive layer into a plurality of conductive units, and each or more of the first pads are connected to One or more of said connecting ends. The method according to claim 17 or 18, further comprising: Forming a protective layer on the upper surface of the conductive layer by using a coating process; An opening window is formed in the protective layer, and the connection end is generated in the opening window on the conductive layer. The method according to claim 19, further comprising: The protective layer directly above the fingerprint identification chip is removed to form an opening, so that the reflected light formed by finger reflection passes through the opening of the protective layer and is received by the fingerprint identification chip. The method according to claim 17 or 18, further comprising: A TSV process is used to set a TSV between the conductive layer and the lower surface of the substrate; At the TSV aperture on the lower surface of the substrate, the connection end is generated. The method according to any one of claims 17 to 21, wherein before the forming a conductive layer over the substrate by using a plating process, the method further comprises: Forming an insulating layer on the upper surface of the substrate by using a coating process, so as to form the conductive layer on the upper surface of the insulating layer; The insulating layer directly above the fingerprint identification chip is removed to form an opening, so that the reflected light formed by finger reflection passes through the opening of the insulating layer and is received by the fingerprint identification chip. The method according to any one of claims 17 to 22, wherein the fixing the fingerprint identification chip in the groove structure comprises: Fixing the fingerprint identification chip in the groove structure through liquid or solid glue; The depth of the groove structure is the sum of the thickness of the fingerprint identification chip and the thickness of the glue. The method according to any one of claims 17 to 23, wherein the method further comprises: A filter is attached to the upper surface of the fingerprint identification chip. The method according to any one of claims 17 to 24, wherein the connection end is a second pad or a solder ball. The method according to any one of claims 17 to 25, wherein the fingerprint identification chip comprises a plurality of chips arranged along a parallel direction and / or a vertical direction of an upper surface of the substrate. The method according to any one of claims 17 to 26, wherein the method further comprises: A bracket and a lens are arranged above the substrate; The lens is fixed above the fingerprint recognition chip through the bracket, and the lens is aligned with the fingerprint recognition chip. The method according to claim 27, wherein the lens and the bracket are provided integrally or separately. A method for packaging a chip, comprising: TSV process is used to set TSV between the upper and lower surface of the fingerprint identification chip; Forming a conductive layer on the lower surface of the fingerprint identification chip by a coating process, and a first pad of the fingerprint identification chip is electrically connected to one end of the conductive layer through TSV; At the other end of the conductive layer, a connection end for electrically connecting to the outside is generated. The method according to claim 29, wherein the fingerprint identification chip is provided with a plurality of the first pads, the chip packaging structure is provided with a plurality of the connection ends, and the upper part of the fingerprint identification chip A plurality of TSVs are disposed between the surface and the lower surface, and the method further includes: By forming openings in the conductive layer, the conductive layer is divided into a plurality of conductive units, and each or more of the first pads pass one or more of the TSVs and one or more of the conductive units. Electrically connected to one or more of the connections. The method according to claim 29 or 30, wherein the lower surface of the fingerprint identification chip is an inverted trapezoid or a multi-step inverted trapezoid, and the connection end is disposed on the inverted trapezoid or the multi-step inverted trapezoid. lower surface. The method according to any one of claims 29 to 31, wherein the method further comprises: A filter is attached to the upper surface of the fingerprint identification chip. A terminal device, comprising: A chip packaging structure prepared according to the method for packaging a chip according to any one of claims 17 to 28. The terminal device according to claim 33, wherein the terminal device further comprises a screen, and the chip package structure is disposed below the screen. A terminal device, comprising: A chip packaging structure prepared according to the method of packaging a chip according to any one of claims 29 to 32. The terminal device according to claim 35, wherein the terminal device further comprises a screen, and the chip package structure is disposed below the screen.

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