WO2020062554A1 - Data reading method for memory, display apparatus, and computer readable storage medium - Google Patents

Abstract

Disclosed in the present application are a data reading method for a memory, a display apparatus, and a computer readable storage medium, the method comprising the following steps: according to storage data stored in a first storage region and second storage region, configuring preset storage data; acquiring a logic address sent by a timing controller; when the logic address sent by the timing controller and a stored logic address are the same, comparing the storage data of the first storage region with the preset storage data; and when the storage data is not the same, assigning the storage data of the second storage region to the first storage region, and triggering the timing controller to read the storage data of the first storage region.

Description

Data reading method for memory, display device and computer-readable storage medium Ranch

Related patents

This application claims the priority of a Chinese patent application dated September 30, 2018, with application number 201811165376.2, and entitled "Data reading method for memory, display device, and computer-readable storage medium", which is hereby incorporated in its entirety as reference.

 Technical field

The present application relates to the field of memory technology, and in particular, to a method for reading data from a memory, a display device, and a computer-readable storage medium.

Background technique

In the display device, the static read only memory in the timing controller TCON IC (static read only Data in memory (SROM) cannot be saved after power-off, but Erasable Memory (Electrically Erasable Programmable read only The data stored in the flash memory can be saved even after power off, so the control program of the timing controller will be stored in the erasable memory or flash memory. After power-on, the timing controller will initialize and read timing control data from the external memory through the bus. The data in the memory cannot be modified during the normal operation of the display device. Once modified, it will cause the timing controller to read the timing control data incorrectly, and the display device will display abnormally.

Application content

The main purpose of the present application is to provide a method for reading data from a memory, a display device, and a computer-readable storage medium. occur.

To achieve the above object, the present application proposes a method for reading data from a memory, which is applied to a display device, where the display device includes:

Timing controller

A memory configured to store data or signals, the memory including a first storage area and a second storage area storing the same storage data, the first storage area is electrically connected to the timing controller, wherein data in the memory is read The extraction method includes the following steps:

Setting preset storage data according to storage data stored in the first storage area and the second storage area;

Get the logical address sent by the timing controller;

Comparing the stored data in the first storage area with the preset storage data when the obtained logical address sent by the timing controller is the same as the stored logical address; and,

When the storage data in the first storage area is inconsistent with the preset storage data, assigning the storage data stored in the second storage area to the first storage area, and triggering the timing controller to read all data The second storage area is assigned to the storage data of the first storage area.

Optionally, when the obtained logical address sent by the timing controller is the same as the stored logical address, the step of comparing the stored data of the first storage area with preset stored data specifically includes:

Setting a preset checksum according to the stored data stored in the first storage area and the second storage area;

Calculating a checksum of the first storage area, and recording the checksum as a first detection checksum;

Comparing the first checksum with the preset checksum; and

When the first detection checksum is inconsistent with the preset checksum, it is determined that the storage data of the first storage area is inconsistent with the preset storage data.

Optionally, after the step of assigning the first storage data stored in the second storage area to the first storage area, the method further includes:

Recalculate the stored data after the first storage area is assigned, and record it as the second detection checksum;

Comparing the second detection checksum with a preset checksum; and

When the second checksum is consistent with a preset checksum, a read instruction is output to trigger the timing controller to communicate with the first storage area for reading by the timing controller. The second storage area is assigned to the storage data of the first storage area.

Optionally, the method for reading data from the memory further includes:

When the first checksum is consistent with the preset checksum, a read instruction is output to trigger the timing controller to communicate with the first storage area and provide the timing controller with Reading the stored data of the first storage area.

The present application also proposes a display device, which includes:

The timing controller is configured to send a logical address when the display device is powered on.

A memory configured to store data or signals, the memory including:

The first storage area and the second storage area store the same storage data, and the first storage area is communicatively connected with the book sequence controller; and,

An inspector configured to set preset storage data according to storage data stored in the first storage area and the second storage area;

Comparing the stored data in the first storage area with the preset storage data when the obtained logical address sent by the timing controller is the same as the logical address stored in the memory; and,

When the storage data of the first storage area is inconsistent with the preset storage data, triggering the second storage area to assign the stored data to the first storage area, and triggering the timing controller and the The first storage area is communicatively connected for the timing controller to read the storage data assigned to the first storage area by the second storage area.

Optionally, the checker is specifically configured to:

Setting a preset checksum according to the stored data stored in the first storage area and the second storage area;

Calculating a checksum of the first storage area, and recording the checksum as a first detection checksum;

Comparing the first checksum with the preset checksum; and

When the first detection checksum is inconsistent with the preset checksum, it is determined that the storage data of the first storage area is inconsistent with the preset storage data.

Optionally, the checker is further configured as:

Recalculate the stored data after the first storage area is assigned, and record it as the second detection checksum;

Comparing the second detection checksum with a preset checksum; and,

When the second checksum is consistent with a preset checksum, a read instruction is output, and the timing controller is triggered to communicate with the first storage area for the timing controller to read the The second storage area is assigned to the storage data of the first storage area.

Optionally, the display device further includes a connector and a serial communication bus, the memory is communicatively connected with the timing controller through the serial communication bus, and the memory is further connected through the connector and serial communication The bus is connected to the upper computer.

Optionally, the serial communication bus is an I2C (Inter-Integrated Circuit) communication bus.

Optionally, the connector is a bilateral connector.

Optionally, the memory is an erasable memory or a flash memory.

Optionally, the display device further includes a display panel, and a source driver, a gate driver, and a driving power source driving the display panel;

The timing controller is connected to the gate driver, the source driver, and the driving power source, respectively.

Optionally, the timing controller is configured to read the control signal and the setting signal stored in the memory when the display device is powered on to perform initialization, and receive the data signal, the control signal output from the external circuit module, and The clock signal is converted into a data signal, a control signal, and a clock signal suitable for the gate driver and the source driver, thereby realizing the image display of the liquid crystal panel.

Optionally, the control signals output by the timing controller include a gate control signal and a source control signal.

The present application also proposes a computer-readable storage medium on which a data reading program of a memory is stored, wherein the data reading program of the memory implements a data reading method of the memory when executed by a processor; the data of the memory The reading method is applied to a display device, which includes:

Timing controller

A memory configured to store data or signals, the memory including a first storage area and a second storage area storing the same storage data, the first storage area being electrically connected to a timing controller, and a data reading method of the memory It includes the following steps:

Setting preset storage data according to storage data stored in the first storage area and the second storage area;

Get the logical address sent by the timing controller;

Comparing the stored data in the first storage area with the preset storage data when the obtained logical address sent by the timing controller is the same as the stored logical address; and,

When the storage data in the first storage area is inconsistent with the preset storage data, assigning the storage data stored in the second storage area to the first storage area, and triggering the timing controller to read all data The second storage area is assigned to the storage data of the first storage area.

Optionally, when the obtained logical address sent by the timing controller is the same as the stored logical address, the step of comparing the stored data of the first storage area with the preset stored data specifically includes:

Setting a preset checksum according to the stored data stored in the first storage area and the second storage area;

Calculating a checksum of the first storage area, and recording the checksum as a first detection checksum;

Comparing the first checksum with the preset checksum;

When the first detection checksum is inconsistent with the preset checksum, it is determined that the storage data of the first storage area is inconsistent with the preset storage data.

Optionally, after the step of assigning the first storage data stored in the second storage area to the first storage area, the method further includes:

Recalculate the stored data after the first storage area is assigned, and record it as the second detection checksum;

Comparing the second detection checksum with a preset checksum; and

When the second checksum is consistent with a preset checksum, a read instruction is output to trigger the timing controller to communicate with the first storage area for reading by the timing controller. The second storage area is assigned to the storage data of the first storage area.

Optionally, the method for reading data from the memory further includes:

When the first checksum is consistent with the preset checksum, a read instruction is output to trigger the timing controller to communicate with the first storage area and provide the timing controller with Reading the stored data of the first storage area.

The data reading method of the memory of the present application sets preset storage data according to the storage data stored in the first storage area and the second storage area; and obtains a logical address sent by a timing controller; When the logical address is the same as the stored logical address, the storage data of the first storage area is compared with the first storage data, and when the storage data of the first storage area is not consistent with the preset storage data, the second storage area is stored The stored data is assigned to the first storage area, and the timing controller is triggered to read the stored data after the second storage area is assigned to the first storage area. This application is beneficial to avoid that the timing control data stored in the memory is rewritten by interference signals, or when the memory is performing read and write operations, an unexpected power failure occurs, causing the internal data of the memory to be lost, and the timing control data read by the timing controller being wrong , Causing the phenomenon that the display screen of the display panel cannot be driven normally.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to explain the technical solutions in the embodiments of the present application or the prior art more clearly, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are merely These are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to the structure shown in the drawings without paying creative labor.

FIG. 1 is a schematic flowchart of an embodiment of a data method for a memory of this application;

FIG. 2 is a detailed flowchart of step S200 in the data reading method of the memory of the present application shown in FIG. 1;

FIG. 3 is a schematic flowchart of another embodiment of a data method for a memory;

4 is a schematic diagram of functional modules of an embodiment of a display device of the present application;

5 is a schematic diagram of functional modules of another embodiment of the display device of the present application shown in FIG. 4;

FIG. 6 is a schematic structural diagram of a data reading device in a memory of a hardware operating environment according to an embodiment of the present application.

The implementation, functional features and advantages of the purpose of this application will be further described with reference to the embodiments and the drawings.

detailed description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

It should be noted that if there is a directivity indication (such as up, down, left, right, front, back, etc.) in the embodiment of the present application, the directivity indication is only set to be interpreted in a specific posture (as shown in the accompanying drawings). (Shown) the relative positional relationship, movement, etc. of the various components, if the specific posture changes, the directional indicator will change accordingly.

In addition, if there are descriptions related to "first", "second", etc. in the embodiments of the present application, the descriptions of "first", "second", etc. are only set for description purposes, and cannot be understood as instructions or hints Its relative importance or implicitly indicates the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but must be based on those that can be realized by a person of ordinary skill in the art. When the combination of technical solutions conflicts or cannot be achieved, it should be considered that such a combination of technical solutions does not exist. Is not within the scope of protection claimed in this application.

This application proposes a method for reading data from a memory, which is applied to a display device. The display device is provided with a timing controller and a memory. The display device may be a display device such as a mobile phone, a computer, a television, a tablet computer, or a projector.

Both memory and timing controller can be set in timing control (Timing Controller (TCON) PCB, because the data in the internal static read-only memory SROM of the timing controller cannot be saved after power-down, the erasable memory (Electrically Erasable Programmable read only data stored in memory (EEPROM) or flash memory can be saved even after power failure, so the control program of the timing controller is stored in erasable memory EEPROM or flash memory flash. After the display device is powered on, the timing controller will initialize and read the timing control signals and other setting data from the external memory through the communication bus to perform initial settings. That is, the memory may store a control signal configured to drive the gate driving integrated circuit and the source driving integrated circuit in the display device to work, and communicate with the timing controller through a serial communication bus. When the display device is powered on, the timing controller reads the control signals in the memory and performs other initial settings to generate the corresponding timing control signals to drive the source driver integrated circuit of the display panel in the display device. And gate drive integrated circuits. The data in the memory cannot be modified during the normal operation of the display device. Once modified, the initialization or error of the timing controller will cause the display device to display abnormally. Generally, most of the memory is provided with a write-protect pin (WP pin), and when the input is high, you can control the memory to write data, and at the low level, you cannot write data. At this time, the memory is only for the timing controller to read data.

However, in the communication bus for communication between the memory and the timing controller, or other paths, there will often be noise interference signals. This interference signal will cause the memory to malfunction, and the data written into the interference signal will cause the software data code stored in the memory. When it is rewritten, the display device displays abnormally. Or when the memory EEPROM or flash memory is erased for read and write operations, an accidental power failure will result in the loss of internal data, which will cause the timing control data read by the timing controller to be incorrect, and the timing controller will not be able to properly drive the display Panel display screen.

In order to solve the above phenomenon, referring to FIG. 1, in an embodiment of the present application, the data reading method of the memory includes the following steps:

Step S100: Set preset storage data according to the storage data stored in the first storage area and the second storage area.

In this embodiment, the memory includes a first storage area and a second storage area that respectively store the first storage data, and the first storage area is communicatively connected to the timing controller, that is, the storage area of the memory is divided in this embodiment. In the case of two or more, two can be selected in this embodiment, and they are respectively a first storage area and a second storage area. When data is written to the memory, the first storage area and the second storage area are respectively The same stored data is stored. In this embodiment, the written stored data is defined as the first stored data. The first stored data is also a control signal and other setting data for initialization by the timing controller. The stored data is written by the host computer. After writing, the first storage data needs to be write-protected to ensure that the data in the memory will not be rewritten in the case of non-program updates. In this embodiment, the preset storage data may be set as the first storage data, that is, the storage data written to the first storage area and the second storage area by a host computer.

Step S200: Obtain a logical address sent by the timing controller.

In this embodiment, the timing controller is equivalent to the master device, and the memory and other functional circuits are equivalent to the slave devices. Each slave device passes the communication bus, such as I2C (Inter-Integrated Circuit) The communication bus is in communication with the timing controller. When the timing controller reads the stored data in the memory, the timing controller will send a logical address. When the memory obtains the logical address and matches the logical address stored in the memory, the timing controller communicates with the memory and reads Fetch the data stored in the memory.

Step S300: When the obtained logical address sent by the timing controller is the same as the stored logical address, compare the stored data of the first storage area with the preset stored data;

In this embodiment, the timing controller is communicatively connected to a register in the first storage area of the memory, and is configured to read only the data in the first storage area, but not the data in the second storage area. This setting can prevent Accidental power loss loses data in both storage areas. When the obtained logical address sent by the timing controller is the same as or matches the stored logical address, the register in the first storage area of the control memory is communicatively connected with the timing controller, and the current storage data of the first storage area is now connected. Compare with the preset storage data to prevent the stored data in the first storage area from entering the first storage area due to the parasitic capacitance and impedance generated by the impedance on the I2C bus of the timing controller. The storage data of a storage area is rewritten, and the timing controller reads the rewritten storage data, so that the timing controller cannot normally drive the display panel display screen.

Step S400: When the storage data in the first storage area is inconsistent with the preset storage data, assign the first storage data stored in the second storage area to the first storage area, and trigger the timing The controller reads the storage data assigned to the first storage area by the second storage area.

In this embodiment, the first storage area is connected to the timing controller through a communication bus, and the second storage area is only communicatively connected to the first storage area. Therefore, after the storage data of the first storage area is rewritten, the first storage area is rewritten. When the storage data of one storage area is inconsistent with the first storage data, the storage data of the second storage area may be assigned to the first storage area. At this time, the data read by the timing controller is the first storage data after the second storage area is assigned to the first storage area, that is, the control signals stored in the memory and other setting data are initially set to generate the corresponding Timing control signals to drive the source driving integrated circuit and the gate driving integrated circuit of the display panel in the display device to work.

The data reading method of the present application sets preset storage data according to the storage data stored in the first storage area and the second storage area; and obtains a logical address sent by a timing controller; When the sent logical address is the same as the stored logical address, the stored data of the first storage area is compared with the first stored data, and when the stored data of the first storage area is not consistent with the preset storage data, the second storage area is The stored first storage data is assigned to the first storage area, and the timing controller is triggered to read the first storage data after the second storage area is assigned to the first storage area. This application is beneficial to avoid that the timing control data stored in the memory is rewritten by interference signals, or when the memory is performing read and write operations, an unexpected power failure occurs, causing the internal data of the memory to be lost, and the timing control data read by the timing controller being wrong. , Causing the phenomenon that the display screen of the display panel cannot be driven normally.

Referring to FIG. 2, in an optional embodiment, when the obtained logical address sent by the timing controller is the same as the stored logical address, comparing the stored data in the first storage area with the first storage The steps to compare the data include:

Step S210: Set a preset checksum according to the storage data stored in the first storage area and the second storage area.

Step S220: Calculate a checksum of the first storage area and record the checksum as a first detection checksum;

Step S230: Compare the first checksum with a preset checksum.

Step S240: When the first checksum is inconsistent with the preset checksum, determine that the storage data in the first storage area is inconsistent with the preset storage data.

In this embodiment, the preset checksum may be a communication connection between the memory and the upper computer, and the checksum obtained after the first computer writes the first stored data, that is, the preset checksum, may be specifically written by Add the value to the first storage area register or the second storage area and add the last six digits as the value of the preset checksum. The preset checksum in this embodiment is in the form of a hexadecimal number system. . When the obtained logical address sent by the timing controller is the same as the stored logical address, the values in the first storage area register may be added and the last six digits taken as the checksum value, that is, the first detection Checksum. When the checksum of the data currently stored in the first storage area, that is, the first detection checksum is inconsistent with the preset checksum, it can be determined that the storage data in the first storage area is inconsistent with the first storage data. That is, the data currently stored in the first storage area has been rewritten.

In an optional embodiment, after the step of assigning the first storage data stored in the second storage area to the first storage area, the method further includes:

Step S410: Recalculate the stored data after the first storage area is assigned, and record it as the second detection checksum;

Step S420: Compare the second detection checksum with a preset checksum.

Step S430: When the second checksum is consistent with the preset checksum, output a read instruction to trigger the timing controller to communicate with the first storage area for reading by the timing controller. Fetch the storage data assigned to the first storage area by the second storage area.

In this embodiment, after the second storage area is assigned to the first storage area, the value currently stored in the first storage area register may be added and the last six digits taken as the value of the checksum, that is, the second Check the checksum. When the checksum preset checksum of the data currently stored in the first storage area is consistent, it means that the value assigned to the first storage area by the second storage area is successful, that is, the current value of the first storage area is currently The stored data is the first stored data that has not been rewritten. At this time, the data read by the timing controller is the stored data after the second storage area is assigned to the first storage area, that is, the control signals stored in the memory and other setting data are initially set to generate the corresponding timing. The control signal drives the source driving integrated circuit and the gate driving integrated circuit of the display panel in the display device to operate.

In an optional embodiment, the method for reading data from the memory further includes:

When the first checksum is consistent with a preset checksum, a read instruction is output to trigger the timing controller to communicate with the first storage area and read by the timing controller. Stored data in the first storage area.

In this embodiment, the value of the first storage area register can be added and calculated, and the last six digits can be used as the value of the checksum. The first detection checksum is preset as the checksum of the data currently stored in the first storage area. When the checksums are consistent, it can be determined that the currently stored storage data in the first storage area is consistent with the first storage data, and the data currently stored in the first storage area has not been rewritten. At this time, the timing controller can read the storage data of the first storage area, that is, the control signals stored in the memory, and other setting data to perform initial settings to generate corresponding timing control signals, thereby driving the display in the display device. The source driver IC and the gate driver IC of the panel work.

The present application also proposes a display device.

3 and 4, in an embodiment of the present application, the display device includes:

The timing controller 100 is configured to send a logical address when the display device is powered on.

In this embodiment, the display device further includes a display panel 200, a source driver 300, a gate driver 400, and a driving power source 500 that drive the display panel 200 to work. The timing controller 100 is connected to the gate driver 400 and the source driver 300, respectively. And the driving power supply 500 is connected, and the timing controller 100 is configured to read the control signals and setting signals stored in the memory 600 when the display device is powered on to perform initialization, and receive data signals and control signals output by external circuit modules The signal and the clock signal are converted into data signals, control signals, and clock signals suitable for the gate driver 400 and the source driver 300 to realize the image display of the liquid crystal panel. The control signals output by the timing controller 100 include a gate control signal and a source control signal.

The memory 600 is configured to store data or signals. The memory 600 includes:

The first storage area 610 and the second storage area 620 respectively store first storage data, and the first storage area 610 is communicatively connected with the book sequence controller; and,

The checker 630 is configured to set preset storage data according to the storage data stored in the first storage area and the second storage area; and obtain the logical address sent by the timing controller 100 and the obtained logical address. When the logical address stored in the memory 600 is the same, comparing the stored data of the first storage area 610 with preset storage data;

When the storage data of the first storage area 610 is inconsistent with the preset storage data, trigger the second storage area 620 to assign the storage data to the first storage area 610 and trigger the timing controller 100 Communicate with the first storage area 610 for the timing controller 100 to read the storage data assigned to the first storage area 610 by the second storage area 620.

In this embodiment, the memory 600 may be an electrically erasable memory (Electrically Erasable Programmable read only memory, EEPROM) or flash memory. The data stored in the memory can be saved even after power failure, so the control program of the timing controller is stored in the erasable memory or flash memory. The storage area of the memory 600 may be divided into two or more. In this embodiment, two storage areas may be selected, and they are a first storage area 610 and a second storage area 620, respectively. The first storage area 610 and the second storage area 620 may be implemented by using a circuit module such as a register. When the data is written to the memory 600, the same storage data is stored in the first storage area 610 and the second storage area 620. This embodiment defines the written storage data as the first storage data. A stored data is a control signal and other setting data for initialization of the timing controller 100. The first stored data is written by a host computer. After writing, the first storage data needs to be write-protected to ensure that the data in the memory 600 cannot be rewritten in the case of non-program update. In this embodiment, the preset storage data may be set as the first storage data, that is, the same storage data stored in the first storage area and the second storage area by the upper computer. The timing controller 100 is communicatively connected to a register in the first storage area 610 of the memory 600, and is configured to read only the data of the first storage area 610, but not the data of the second storage area 620. This setting prevents Accidental power loss loses data in both storage areas.

When the obtained logical address sent by the timing controller 100 is the same as or matches the stored logical address, the register in the first storage area 610 of the control memory 600 is communicatively connected with the timing controller 100, and the first storage area is now connected. The current stored data of 610 is compared with the first stored data to prevent the stored data of the first storage area 610 from being disturbed by interference signals generated by the parasitic capacitance and impedance on the I2C bus of the memory 600 and the timing controller 100. The first storage area 610 causes the stored data in the first storage area 610 to be rewritten, and the timing controller 100 reads the rewritten storage data, so that the timing controller 100 cannot normally drive the display panel 200 to display a screen.

In this embodiment, the checker 630 detects whether the data in the first storage area 610 is rewritten. If the data stored in the first storage area 610 is rewritten, the stored data in the first storage area 610 and the preset storage data are caused. When they are not consistent, the second storage area 620 may be controlled to assign the stored storage data to the first storage area 610. If it is not rewritten, the timing controller 100 may be triggered to read the first storage data after the first storage area 610, that is, the control signals stored in the memory 600 and other setting data are initially set to generate corresponding The timing control signals drive the source driving integrated circuit and the gate driving integrated circuit of the display panel 200 in the display device to operate.

The display device of the present application sets a checker 630 in the memory 600 to set preset storage data according to the storage data stored in the first storage area and the second storage area, and obtain a logical address sent by the timing controller 100 ; When the obtained logical address sent by the timing controller 100 is the same as the stored logical address, compare the stored data of the first storage area 610 with the preset storage data, and store the stored data in the first storage area 610 with the first When the stored data is inconsistent, the first storage data stored in the second storage area 620 is assigned to the first storage area 610, and the timing controller 100 is triggered to read the storage data after the second storage area 620 is assigned to the first storage area 610. This application is beneficial to avoid that the timing control data stored in the memory 600 is rewritten by interference signals, or when the memory 600 is performing read and write operations, an unexpected power failure occurs, causing the internal data of the memory 600 to be lost, and the timing read by the timing controller 100. The control data is incorrect, which causes the phenomenon that the display screen of the display panel 200 cannot be driven normally.

Referring to FIG. 3 and FIG. 4, in an optional embodiment, the checker 630 is specifically configured to:

Setting a preset checksum according to the stored data stored in the first storage area and the second storage area;

Calculating a checksum of the first storage area 610 and recording the checksum as a first detection checksum;

Comparing the first detection checksum with a preset checksum; and,

When the first checksum is inconsistent with the preset checksum, it is determined that the stored data in the first storage area 610 is inconsistent with the preset stored data.

In this embodiment, the checker 630 can obtain the checksum after the first computer writes the first stored data, that is, the preset checksum, which can be specifically written to the first storage area register or the second storage area. The numerical values of are added and calculated, and the last six digits are taken as the value of the preset checksum. The preset checksum in this embodiment is in the form of a hexadecimal number system. When the obtained logical address sent by the timing controller 100 is the same as the stored logical address, the values in the first storage area 610 register may be added and the last six digits taken as the checksum value, that is, the first A detection checksum. When the checksum of the data currently stored in the first storage area 610, that is, the first detection checksum is inconsistent with the preset check, the stored data of the first storage area and the preset can be determined. The stored data is inconsistent, that is, the data currently stored in the first storage area has been rewritten.

Referring to FIG. 3 and FIG. 4, in an optional embodiment, the checker 630 is further configured to:

Recalculate the stored data after the first storage area 610 is assigned, and record it as the second detection checksum;

Comparing the second detection checksum with a preset checksum; and

When the second checksum is consistent with a preset checksum, a read instruction is output, and the timing controller is triggered to communicate with the first storage area 610 for communication, so that the timing controller can read all The second storage area 620 is assigned to the storage data of the first storage area 610.

In this embodiment, after the checker 630 is assigned to the first storage area 610 in the second storage area 620, the checker 630 may perform addition calculation on the values currently stored in the first storage area 610 register and take the last six digits as the checksum. Value of the first storage area 610 when the checksum preset checksum of the data currently stored in the first storage area 610 is the same Success, that is, the data currently stored in the first storage area 610 is the first stored data that has not been rewritten.

Referring to FIG. 3 and FIG. 4, in an optional embodiment, the display device further includes a connector (not shown) and I2C (Inter-Integrated Circuit) communication bus, the memory is communicatively connected to the timing controller through the I2C communication bus, and the memory is also connected to a host computer through the connector and the I2C communication bus.

In this embodiment, the connector may be a bilateral connector. Through the connector and the I2C communication bus, the communication connection between the memory and the timing controller and the upper computer can be realized. At the same time, the timing controller and an external controller such as a display device The main controller on the main control board and other communication connections to receive corresponding control signals and data signals, thereby driving the display panel to display the corresponding screen.

The present application also proposes a computer-readable storage medium on which a data reading program of a memory is stored. When the data reading program of the memory is executed by a processor, the data reading method of the memory as described above is implemented.

As shown in FIG. 5, FIG. 5 is a schematic structural diagram of a terminal of a hardware operating environment involved in the solution of the embodiment of the present application, that is, a data reading device of a memory.

In the embodiment of the present application, the terminal may be a server, a PC, or a smart phone, a tablet computer, an e-book reader, or MP3 (Moving Picture Experts Group Audio Layer III, standard audio layer 3) player, MP4 (Moving Picture Experts Group Audio Layer IV, moving picture expert compression standard audio layer 3) Mobile terminal devices with display functions such as players, portable computers.

As shown in FIG. 5, the terminal may include a processor 1001, such as a CPU, a network interface 1004, a user interface 1003, a memory 1005, and a communication bus 1002. The communication bus 1002 is configured to implement connection and communication between these components. The user interface 1003 may include a display, an input unit such as a keyboard, and the optional user interface 1003 may further include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a WI-FI interface). The memory 1005 may be a high-speed RAM memory or a non-volatile memory. memory), such as disk storage. The memory 1005 may optionally be a storage device independent of the foregoing processor 1001.

Those skilled in the art can understand that the terminal structure shown in FIG. 4 does not constitute a limitation on the terminal, and may include more or fewer components than shown in the figure, or combine some components, or arrange different components.

Referring to FIG. 5, the memory 1005 as a computer storage medium may include an operating system, a network communication module, a user interface module, and a data reading program of the memory.

In the terminal shown in FIG. 5, the network interface 1004 is mainly configured to connect to the background server and perform data communication with the background server; the user interface 1003 is mainly configured to connect to the client (user) and perform data communication with the client; and the processor 1001 may be configured to call a data reading program of a memory stored in the memory 1005 and execute the method steps of the embodiments of data reading of the memory as described above.

Through the description of the above embodiments, those skilled in the art can clearly understand that the methods in the above embodiments can be implemented by means of software plus a necessary universal hardware platform, and of course, also by hardware, but in many cases the former is better. Implementation. Based on such an understanding, the technical solution of this application that is essentially or contributes to the existing technology can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM) as described above. , Magnetic disk, optical disc), including a number of instructions for causing a terminal device (which may be a mobile phone, a computer, a server, a display device, or a network device, etc.) to execute the methods described in the embodiments of the present application.

The above description is only an optional embodiment of the present application, and thus does not limit the patent scope of the present application. Any equivalent structural transformation made by using the specification and drawings of the present application under the concept of the application of the present application, or direct / indirect Applications in other related technical fields are covered by the patent protection scope of this application.

Claims (18)

A method for reading data from a memory is applied to a display device. The display device includes: Timing controller A memory configured to store data or signals, the memory including a first storage area and a second storage area storing the same storage data, the first storage area is electrically connected to the timing controller, wherein data in the memory is read The extraction method includes the following steps: Setting preset storage data according to storage data stored in the first storage area and the second storage area; Get the logical address sent by the timing controller; Comparing the stored data in the first storage area with the preset storage data when the obtained logical address sent by the timing controller is the same as the stored logical address; and When the storage data in the first storage area is inconsistent with the preset storage data, assigning the storage data stored in the second storage area to the first storage area, and triggering the timing controller to read all data The second storage area is assigned to the storage data of the first storage area. The method for reading data from a memory according to claim 1, wherein, when the obtained logical address sent by the timing controller is the same as the stored logical address, the stored data in the first storage area is The steps for comparing stored data include: Setting a preset checksum according to the stored data stored in the first storage area and the second storage area; Calculating a checksum of the first storage area, and recording the checksum as a first detection checksum; Comparing the first checksum with the preset checksum; and When the first detection checksum is inconsistent with the preset checksum, it is determined that the storage data of the first storage area is inconsistent with the preset storage data. The method for reading data from a memory according to claim 2, wherein after the step of assigning the first storage data stored in the second storage area to the first storage area, further comprising: Recalculate the stored data after the first storage area is assigned, and record it as the second detection checksum; Comparing the second detection checksum with a preset checksum; and When the second checksum is consistent with a preset checksum, a read instruction is output to trigger the timing controller to communicate with the first storage area for reading by the timing controller. The second storage area is assigned to the storage data of the first storage area. The method for reading data from a memory according to claim 2, wherein the method for reading data from the memory further comprises: When the first checksum is consistent with the preset checksum, a read instruction is output to trigger the timing controller to communicate with the first storage area and provide the timing controller with Reading the stored data of the first storage area. A display device, wherein the display device includes: The timing controller is configured to send a logical address when the display device is powered on. A memory configured to store data or signals, the memory including: The first storage area and the second storage area store the same storage data, and the first storage area is communicatively connected with the book sequence controller; and, An inspector configured to set preset storage data according to storage data stored in the first storage area and the second storage area; When the obtained logical address sent by the timing controller is the same as the logical address stored in the memory, comparing the stored data in the first storage area with the preset storage data; in the first storage, When the stored data in the area is inconsistent with the preset stored data, triggering the second storage area to assign the stored data to the first storage area, and triggering the timing controller to communicate with the first storage area for communication For the timing controller to read the storage data assigned by the second storage area to the first storage area. The display device according to claim 5, wherein the inspector is specifically configured to: Setting a preset checksum according to the stored data stored in the first storage area and the second storage area; Calculating a checksum of the first storage area, and recording the checksum as a first detection checksum; Comparing the first checksum with the preset checksum; and When the first detection checksum is inconsistent with the preset checksum, it is determined that the storage data of the first storage area is inconsistent with the preset storage data. The display device according to claim 5, wherein the inspector is further configured to: Recalculate the stored data after the first storage area is assigned, and record it as the second detection checksum; Comparing the second detection checksum with a preset checksum; and, When the second checksum is consistent with a preset checksum, a read instruction is output, and the timing controller is triggered to communicate with the first storage area for the timing controller to read the The second storage area is assigned to the storage data of the first storage area. The display device according to claim 5, wherein the display device further comprises a connector and a serial communication bus, the memory is communicatively connected to the timing controller through the serial communication bus, and the memory is further connected through The connector and the serial communication bus are connected to a host computer. The display device according to claim 8, wherein the serial communication bus is an I2C communication bus. The display device according to claim 8, wherein the connector is a double-sided connector. The display device according to claim 5, wherein the memory is an erasable memory or a flash memory. The display device according to claim 5, wherein the display device further comprises a display panel, and a source driver, a gate driver, and a driving power source for driving the display panel to work; The timing controller is connected to the gate driver, the source driver, and the driving power source, respectively. The display device according to claim 12, wherein the timing controller is configured to read a control signal and a setting signal stored in the memory when the display device is powered on to perform initialization and receive an external circuit module The output data signal, control signal, and clock signal are converted into data signals, control signals, and clock signals suitable for the gate driver and the source driver, thereby realizing the image display of the liquid crystal panel. The display device according to claim 13, wherein the control signals output by the timing controller include a gate control signal and a source control signal. A computer-readable storage medium storing a data reading program of a memory, wherein when the data reading program of the memory is executed by a processor, the data reading method of the memory is implemented; the data reading method of the memory is applied In the display device, the display device includes: Timing controller A memory configured to store data or signals, the memory including a first storage area and a second storage area storing the same storage data, the first storage area being electrically connected to a timing controller, and a data reading method of the memory It includes the following steps: Setting preset storage data according to storage data stored in the first storage area and the second storage area; Get the logical address sent by the timing controller; Comparing the stored data in the first storage area with the preset storage data when the obtained logical address sent by the timing controller is the same as the stored logical address; and When the storage data in the first storage area is inconsistent with the preset storage data, assigning the storage data stored in the second storage area to the first storage area, and triggering the timing controller to read all data The second storage area is assigned to the storage data of the first storage area. The computer-readable storage medium according to claim 15, wherein, when the obtained logical address sent by the timing controller is the same as the stored logical address, the stored data in the first storage area is preset with the preset data. The steps of storing data for comparison include: Setting a preset checksum according to the stored data stored in the first storage area and the second storage area; Calculating a checksum of the first storage area, and recording the checksum as a first detection checksum; Comparing the first checksum with the preset checksum; When the first detection checksum is inconsistent with the preset checksum, it is determined that the storage data of the first storage area is inconsistent with the preset storage data. The computer-readable storage medium of claim 15, wherein after the step of assigning the first storage data stored in the second storage area to the first storage area, further comprising: Recalculate the stored data after the first storage area is assigned, and record it as the second detection checksum; Comparing the second detection checksum with a preset checksum; and When the second checksum is consistent with a preset checksum, a read instruction is output to trigger the timing controller to communicate with the first storage area for reading by the timing controller. The second storage area is assigned to the storage data of the first storage area. The computer-readable storage medium of claim 15, wherein the data reading method of the memory further comprises: When the first checksum is consistent with the preset checksum, a read instruction is output to trigger the timing controller to communicate with the first storage area and provide the timing controller with Reading the stored data of the first storage area.