WO2019210923A1

WO2019210923A1 - Temperature management of a semiconductor chip

Info

Publication number: WO2019210923A1
Application number: PCT/DK2019/050131
Authority: WO
Inventors: Alireza REZANIAKOLAEI; Lasse ROSENDAHL; Meysam KARIMIRAD; Ali Asghar Enkeshafi
Original assignee: Aalborg Universitet AAU
Current assignee: Aalborg Universitet AAU
Priority date: 2018-05-04
Filing date: 2019-04-30
Publication date: 2019-11-07
Anticipated expiration: 2020-11-04

Abstract

The invention relates to a method of controlling thermal stress of a semiconductor chip, the method comprises the steps of: establishing a modular frequency of the semiconductor chip and thereby a thermal profile of the semiconductor chip and establishing a pulsing current controlling the thermal profile of a thermoelectric cooling device thermally connected to the semiconductor chip. Wherein the pulsing current is generated in response to the modular frequency, so that a super cooling period of the thermal profile of the thermoelectric cooling device is at least partly overlapping a temperature increasing period of the thermal profile of the semiconductor chip,anda recovery period of the thermal profile of the thermoelectric cooling device is at least partly overlapping a temperature decreasing period of the thermal profile of the semiconductor chip.

Description

i

TEMPERATURE MANAGEMENT OF A SEMICONDUCTOR CHIP

Field of the invention

The invention relates to a method of controlling the temperature of a semiconductor chip, a thermoelectric semiconductor module and a system for controlling the temperature of a semiconductor device

Background of the invention

[0001] The problem of deterioration of power module switching devices due to high temperatures caused by current flow through the power module has been known and solved in different ways over the years. One way has been lowering the temperature by use of a powerful heat sink.

[0002] Both passive and active heat sink solutions have been suggested for cooling power modules. One example of an active heat sink solution is thermoelectric coolers, the so-called TECs or TE coolers. TE coolers are known for use in cooling systems for power switching devices such as IGBTs (IGBT; Insulated Gate Bipolar Transistors). One example is EiS9,099,426 disclosing a power module which includes a power switching device the temperature of which is lowered by a spot cooler implemented as an array of TE coolers.

[0003] Another example is US8,995,l34, here a power module includes a plurality of TE coolers for discharging heat away from the electrical component of the power module. Yet another example is US7,893,529, here a chip stack with an intervening TE cooler is disclosed. The TE cooler distributes heat in the stack from hotter chips to cooler chips.

[0004] Hence all prior art cooling systems using TE coolers face the same problem namely to discharge heat generated on the hot side of the TE cooler away from the hot spot, while at the same time the TE cooler is using its cool side to lower the temperature of the hot spot of the power module. Summary of the invention

[0005] In addition to the above-mentioned problem, the present invention also solves the problem of reducing the significant temperature oscillation on critical hot spots i.e. at or close to switching modules of a power module. [0006] Hence, the present invention relates to a method of controlling thermal stress of a semiconductor chip, the method comprises the steps of: establishing a modular frequency of the semiconductor chip and thereby a thermal profile of the semiconductor chip establishing a pulsing current controlling the thermal profile of a thermoelectric cooling device thermally connected to the semiconductor chip, wherein the pulsing current is generated in response to the modular frequency, so that a super cooling period of the thermal profile of the thermoelectric cooling device is at least partly overlapping a temperature increasing period of the thermal profile of the semiconductor chip, and a recovery period of the thermal profile of the thermoelectric cooling device is at least partly overlapping a temperature decreasing period of the thermal profile of the semiconductor chip.

[0007] The modulation frequency (also sometimes referred to as thermal frequency) is may be shaped by the switching of the semiconductor chip or controlled by the external controller. As an example, could be mentioned that is case two or more semiconductor chips are connected in a half or full bridge configuration, the frequency of the output current of such configuration could be referred to as the modulation frequency. Hence in the situation where such configuration of semiconductor chips is connected to the utility grid, the modulation frequency would typically be 50Hz or 60Hz. In other applications the modulation frequency could be lower or higher. A low modulation frequency typically will lead to a high temperature of the semiconductor chip. A frequency up to lOHz is typically defined as a low frequency.

[0008] In the example of a diode or light emitting diode where no modulation frequency would appear, then the pulsing current is controlled by the switching on and off of such diode including light emitting diodes. [0009] The modulation frequency is preferably established simply by receiving information hereof from a controller creating it. Alternatively, it can be determined by analyzing the operation of or output from the semiconductor chip.

[0010] Controlling the pulse of the current to the thermoelectric cooling device is advantageous in that it has the effect that a super cooling period of the thermoelectric cooling device is established. Controlling the pulse of the current to the thermoelectric cooling device in response to the modular frequency is advantages in that it has the effect, that the thermoelectric cooling device generates a super cooling period and a heat generating recovery period so that an overlap is created between the super cooling period and the temperature increasing period and an overlap exists between the recovery period and the temperature decreasing period.

[0011] The thermal profile of the semiconductor chip mirrors the switching and modular frequency of the semiconductor chip and thereby the current through the semiconductor chip. Hence, when current is conducted, temperature of the semiconductor chip is increasing and when no current is conducted, temperature of the semiconductor chip is decreasing. The semiconductor chip is preferably an IGBT (IGBT; Insulated Gate Bipolar Transistor), but could in principle be any type of semiconductor chips for power electronic applications including diodes, MOSFETs, etc. [0012] Controlling the thermal profile of the thermoelectric cooling device in response to the modular frequency and thereby in response to the switching of the semiconductor chip is advantageous in that it has the effect, that its super cooling period is established when temperature is increasing in the semiconductor chip and its recovery period is established when temperature is decreasing in the semiconductor chip.

[0013] Hence, due to the thermal connection between the thermoelectric cooling device and the semiconductor chip the temperature variation and thereby thermal stress of the semiconductor chip and the solder layers is controlled and preferably reduced. A reduction of thermal stress is advantageous in that it has the effect, that the lifetime of the semiconductor chip is increased.

[0014] A further advantage of the present invention, is that by the control of the temperature facilitated by the thermoelectric cooling device, the number of amps the semiconductor chip is able to conduct can be varied. The is especially advantageous in applications where the design needs to comply with rare events of high load current. Accordingly, by the present invention, the average temperature of the semiconductor chip can be lowered facilitating conducting an increased number of amps.

[0015] According to an embodiment of the invention, the modular frequency is received by a controller and the pulsing current is established by the controller based on the received modular frequency.

[0016] Preferably, the modular frequency is generated by a control system controlling a plurality of semiconductor chips of a power module. This modular frequency is then provided to a controller (which in this way establish the modular frequency). The controller is then based here on establishing the pulsing current i.e. the frequency of pulses of the current applied to the thermoelectric cooling device. The control system generating the modular frequency may also generate the pulsing current.

[0017] According to an embodiment of the invention, the pulsing current varies between a pulse bottom current and a pulse top, wherein the value of the pulse bottom current is determined as a fraction of an optimum current.

[0018] According to an embodiment of the invention, the base current is within the range of ±10 % of the optimum current of a TE cooler working under a steady state condition, which cause the maximum temperature difference between the semiconductor chip and hot side of the thermoelectric cooling device or provides maximum (COP). Preferably, the optimum current is the current at which the largest delta temperature is established in that it has the effect of highest cooling effect. The leads to better cooling of the semiconductor switch which therefore can comply with a higher current density i.e. a higher load current through it. [0019] According to an embodiment of the invention, the optimum current is based on a maximum coefficient of performance or maximum temperature difference of the semiconductor chip 1 and the hot side of the TE cooler (4).

[0020] Preferably, the optimum current is the current at which the energy used on cooling is lowest or at least balanced between the cost of energy of establishing a super cooling effect in the thermoelectric cooling device and the need for cooling of the semiconductor chip. It should be mentioned, that a balance between the load current through semiconductor chip, the energy used on cooling and the cooling effect is preferred. [0021] According to an embodiment of the invention, the fraction of the optimum current is established as a base current divided by the optimum current, wherein the base current is larger than 0 A, but smaller or equal than the optimum current. The current pulsing between pulse bottom and pulse top current to the thermoelectric cooling device is establishing the super cooling and recovery effect of the thermal profile hereof. The recovery period of the thermal profile is established when the bottom pulse current is applied to the thermoelectric cooling device. The super cooling period is established when the top pulse current is applied to the thermoelectric cooling device. Matched with the thermal profile of the semiconductor chip, the range of temperature variation of the thermal profile of the semiconductor chip is manageable, preferably reduced.

[0022] According to an embodiment of the invention, the value of the pulse top current is established by multiplying a pulse magnitude constant to the base current, wherein the pulse magnitude constant is between 0.1 and 5. The size of the pulse magnitude (PM) constant is determined by the design of the semiconductor chip, and dimension and material properties between the semiconductor chip and thermoelectric element. The pulse magnitude recommended to be 0 < PM<=5.

[0023] According to an embodiment of the invention, a pulse of the pulsing current is delayed between -50% and 50% of a period of the modulation frequency, preferably between -10% and 10% of a period of the modulation frequency. The exact delay or either the first or control frequency depends on the design of the thermoelectric module including the thickness of the layers hereof, material properties (e.g. thermal diffusion, thermal conductivity etc.) of the layers between the thermoelectric cooling device and the semiconductor chip. [0024] Hence, the delay from start of a period of the modular frequency to start of a current pulse of the pulsing current to the thermoelectric cooling device is determined based on design of the semiconductor chip / thermoelectric cooling device or together a hybrid power electric thermoelectric module, the application in which it is used, the modular frequency, etc. [0025] According to an embodiment of the invention, the duration of a top pulse current is shorter than the duration of the temperature increasing period of the modular frequency.

[0026] According to an embodiment of the invention, the duration of the top pulse current is between 0,1% and 0,95% of the duration of the temperature increasing period of the modular frequency. The temperature increasing period of the modular frequency is understood as the part of a period of the modulation frequency where heat is generated in the semiconductor chip i.e. the output current shaped by the switching of the semiconductor chip.

[0027] Preferably, the top pulse current starts after the start of the temperature increasing period of the modular frequency and terminates before the temperature increasing period of the modular frequency terminates. The start and stop time of the top pulse current is determined by the design of the semiconductor module, the desired cooling effect needed, the energy allowed used on the cooling, etc.

[0028] According to an embodiment of the invention, the control frequency preferably is a square formed control signal. This is advantageous in that it has the effect, that square formed control signals are easy to generate and the most common control signal waveform that exists. It should be mentioned, that any type of waveform can be used to control the current to the thermoelectric cooling device. [0029] According to an embodiment of the invention, the thermoelectric cooling device (4) is a thin film type. The size of the layers relates closely to the thermal frequency hence the lower frequency, the thicker elements the thermoelectric device needs to be built of. As an example, could be mentioned, at a thermal frequency of 50Hz the thickness of the layers should preferably be between 100 and 200 micrometers. At a frequency of lHz, the layer or film thickness preferably is between 400 and 1000 micrometers.

[0030] It is preferred that the thickness of the materials between the thermoelectric cooling device and the semiconductor chip (thickness of the ceramic layer and soldering materials) should be minimized with restriction of mechanical strength and limitations for fabrication.

[0031] According to an embodiment of the invention, the thermoelectric cooling device (4) is a bulk type. The bulk type thermoelectric cooling device is advantageous for lower modular frequencies (sometimes also referred to as thermal frequencies). Especially modular frequencies below lOHz, the bulk type is advantages. Hence, a such low modular frequencies the bulk type is chosen in that they are typically also cheaper than the thin film type.

[0032] Moreover, the invention relates to a thermoelectric semiconductor module configured for adjusting temperature of a semiconductor chip, the thermoelectric semiconductor module comprises a plurality of elements including: a semiconductor chip, a solder layer, a first ceramic layer facilitates electrical insulation and thermal conductance, a second coated layer facilitates both thermal and electrical conductance, thermoelectric elements including both n-type and p- type thermoelectric cooling elements, a third coated layer facilitates both thermal and electrical conductance, a micro-structured heat sink including micro-channels, and a printed circuit board electrically connected to the semiconductor chip by means of bond wires, wherein the semiconductor chip is thermally connected to the thermoelectric elements by means of the solder layer, the first ceramic layer and the second coated layer, wherein the thermoelectric elements are thermally connected to the fluid in the micro-channels of the micro-structured heat sink by means of the third coated layer, thereby creating a thermal connection between the semiconductor chip and the fluid of the micro- channels.

[0033] The elements or at least some of the elements of the semiconductor module is also sometimes referred to as layers. The semiconductor chip could be any type of chip such as a diode, MOSFET, IGBT, Light Emitting Diode, etc.

[0034] The micro-channels are also sometimes referred to as micro-fins. A cover is preferably covering the micro-channels / structures thereby creating passage for cooling fluid.

[0035] The first and second coated layers and the first ceramic layer (43, 44, 45) is sometimes referred to as direct bond copper.

[0036] The thermoelectric elements are adapted to receive a current from a current source or controller, preferably this current source generates a pulsing current the n- type and p-type can be located in any order preferably alternating starting with an n- type or a p-type. This is advantageous in that it has the effect, that a super cooling effect of the thermoelectric elements is established. The thermoelectric elements together are sometimes referred to as thermoelectric cooling device.

[0037] The design of the above thermoelectric semiconductor module is sometimes referred to as hybrid power electric thermoelectric module in that the semiconductor chip and the thermoelectric cooling device is merged together in one compact module. This is advantages in that it has the effect, that the thickness of the module is reduce significant, compared to known semiconductor chip / thermoelectric cooling device designs.

[0038] Preferably, the heat sink is fabricated on the extended ceramic layer 48, leading to the compact design of the hybrid model. If not then as described below two layers are needed: a further coated layer (e.g. metallic heat sink with micro-scale fins) and a further ceramic layer (e.g. ceramic layer as a part of the thermoelectric cooler).

[0039] Metallic interconnector i.e. the coated layers are thermally and electrically conductive. Although conventionally these layers are thermally in parallel and electrically are connected in series, the electrical connection of these layers can be a combination of parallel and series to provide most homogenous temperature distribution on the heated semiconductor chip.

[0040] The soldering material of the soldering layer may e.g. be Sn-Ag-Cu alloy or other solder sheet or paste suitable for range of the operating temperature.

[0041] The ceramic material of the ceramic layer may e.g. be aluminum oxide, aluminum nitride, etc.

[0042] According to an embodiment of the invention, the first ceramic layer connected to the semiconductor chip by the solder layer is coated by a first coated layer, wherein the coated layer is both thermal and electrical conductive. This is advantage in that it has the effect of improved soldering between semiconductor chip and the thermoelectric elements. An example of such coated layer could be Direct Bond Copper (DBC) in the power electronics modules.

[0043] According to an embodiment of the invention, the thermoelectric semiconductor module further comprises a further ceramic layer and a further coated layer located between the third coated layer and the micro-structured heat sink, wherein the further ceramic layer facilitates electrical insulation and thermal conductance and the further coated layer facilitates both thermal and electrical conductance. This is advantageous in that it has the effect, that the semiconductor chip, the thermoelectric cooling device and the heat sink is individual devices which are individually easy to manufacture and easy to combine in and thereby create a thermoelectric semiconductor module. In this embodiment, the module is not a hybrid in that the devices are not merged together as described above into one device.

[0044] According to an embodiment of the invention, the heat sink comprises a cooling fluid passage formed by micro-channels having an inlet allowing a cooling fluid to enter the cooling fluid passage and an outlet allowing the cooling fluid to leave the cooling fluid passage. This is advantages in that it has the effect, that it allows active cooling of the hot side of the thermoelectric cooling device / elements by circulation of cooling fluid. The cooling fluid can be any known refrigerant fluid in gaseous or liquid form including water, carbon dioxide, etc.

[0045] According to an embodiment of the invention, the inlet allowing the cooling fluid to enter the cooling fluid passage is located between two outlets of the cooling fluid passage. This is advantages in that it has the effect, that the cooling flow can enter from middle of the heat sink and exit from two other sides of the heat sink or vice versa. This leads to a better temperature distribution on the thermoelectric cooler surface and then on the chip surface.

[0046] According to an embodiment of the invention, the heat sink is covered by a cover. Preferably, the cover for the heat sink is made of a rigid plastic material, this is advantage in that such plastic material is cheap thereby reducing the cost of the semiconductor module. Further, in a power module comprising a plurality of semiconductor chips, the cover is advantageously used for positioning the heat sink and thereby the thermoelectric cooling device where hot spots of the power module is present.

[0047] According to an embodiment of the invention, the micro-structured heat sink preferably is a ceramic micro-structured heat sink. The is advantages in that it has the effect that the thermal resistance through the hybrid module is reduced and cooling performance of the TE cooler improves. Therefore, the temperature of the hot chip reduces in terms of the temperature oscillation and the average temperature.

[0048] This is advantages in that the heat sink is thermally connected to the semiconductor chip via the thermoelectric cooling device and thereby facilitates removing the heat generated from the semiconductor chip.

[0049] According to an embodiment of the invention, the closed cooling fluid passage enables flow of cooling fluid in opposition directions at the same time. This is advantages in that it has the effect that the area of the heat sink used for effective cooling is increased. [0050] According to an embodiment of the invention, the area of the cooling fluid passage is at least the same size as the area covered by the thermoelectric cooling elements. This is advantageous in that there is effective cooling on the hot side of TE cooler, and there is not hot spots /area on the TE cooler. [0051] According to an embodiment of the invention, the flow of cooling fluid in the cooling fluid passage is dynamic. Preferably, it is dynamic in response the modular frequency and thereby in response to heat generated in the semiconductor chip. This is advantageous in that it has the effect that a periodic mass flow rate imposed into the micro-structured heat sink is aligned with heat generated by the semiconductor chip / hot side of the thermoelectric cooling device.

[0052] The coolant mass flow rate in the heat sink is normally constant. Since the heat generation by the chip or power electronic element and, also, the cooling pulse by the thermoelectric device are transient and periodic. As mentioned in response hereto a periodic mass flow rate imposed into the micro-structured heat sink can be provided. By this technique, the thermal stress on the hot side of the thermoelectric device will be reduced. The cooling pulse is more efficient at lower modular (thermal) frequencies e.g. below lHz. As the pulse cooling of the thermoelectric device should be matched with the heating semiconductor chip for an efficient cooling, the frequency and periodic parameters of the coolant flow rate is preferably matched with pulse cooling of the thermoelectric device.

[0053] According to an embodiment of the invention, the heat sink further comprises a first anchor part and a second anchor part facilitating mounting of electric connections to the semiconductor chip.

[0054] According to an embodiment of the invention, the heat sink further comprises a recess between the first and second anchor parts wherein the size of the recess is larger than the size of the thermoelectric cooling device thereby enabling mounting of the thermoelectric cooling device in the recess.

[0055] According to an embodiment of the invention, the thermoelectric semiconductor module is positioned on a ridged baseplate prior to mounting on the power module. This is advantages in that the bottom of the heat sink then is fixed to ridged baseplate and thereby, the thermoelectric semiconductor module is fixed hereto. The cover 412 of the heat sink prevents leaking of cooling fluid from the heat sink into the ambient environment. [0056] According to an embodiment of the invention, the thermoelectric semiconductor module is attached to the printed circuit board. This is advantages in that it has the effect, that the location can be predetermined e.g. based on simulations to ensure that the thermoelectric cooling devices are positioned at hot spots of the power module. [0057] The base plate is preferably molded or printed in ridged material such as plastic which are cheap.Both ways of fixing the thermoelectric semiconductor module is advantageous in that a plurality of such island systems can be combined in any combination to comply with cooling demands of hotspots of a variety of power module designs. [0058] Preferably, the area of the printed circuit board 410 can be larger than the corner area (anchor parts) of the heat sink in order to make the printed circuit board able to conduct high current to the heating semiconductor chip by the extended area of the printed circuit board.

[0059] According to an embodiment of the invention, a primary heat sink is located between the semiconductor chip and the thermoelectric elements. This is advantageous in that it has the effect that during normal operation of the semiconductor chip, the primary heat sink cools the semiconductor chip without help and thereby energy used by the thermoelectric cooler. When the primary heat sink is not able to keep a desired temperature, the thermoelectric cooler assists in cooling the semiconductor chip. In order to concentrate the cooling from the thermoelctric elements on the semiconductor chip, the coolant flow in the primary heat sink may reduce or become zero when the thermoelctric elements are supercooling the semiconductor chip.

[0060] According to an embodiment of the invention, the semiconductor chip is located between a primary heat sink and the thermoelectric elements. This is advantageous in that it has the effect, that during normal operation of the semiconductor chip heat is removed via the primary heat sink and without electrical energy used by the thermoelectric cooler. When the primary heat sink is not able to keep a desired temperature, the thermoelectric cooler assists in cooling the semiconductor chip and in this embodiment, this is done without the thermoelectric cooler cools the primary heat sink.

[0061] Moreover, the invention relates to a system for thermal control of a semiconductor chip of a power module, the system comprises: a plurality of thermoelectric cooling devices wherein each individual thermoelectric cooling device of the plurality of thermoelectric cooling devices has a cooling area in a first plan, a plurality of semiconductor chips having a semiconductor area in the first plan, wherein the individual semiconductor chips of the plurality of semiconductors devices are located above an individual thermoelectric cooling device so that the semiconductor area and the cooling area is at least partly overlapping, a control system configured for controlling the modular frequency and thereby a thermal profile of at least one of the plurality of semiconductor chips, the thermal profile of the semiconductor chip includes a temperature increasing period and a subsequent temperature decreasing period, wherein, the control system is furthermore configured for controlling the current to and thereby a thermal profile of at least one of the plurality of thermoelectric cooling devices, the thermal profile of the thermoelectric cooling device includes a super cooling period and a subsequent recovery period, wherein heat is generated from the thermoelectric cooling device during the recovery period, and wherein the control of the current to a first thermoelectric cooling device of the plurality of thermoelectric cooling devices is controlled in response to the modular frequency of a first semiconductor chip of the plurality of semiconductor chips, and wherein the semiconductor area of the first semiconductor chip is at least partly overlapping the cooling area of the first thermoelectric cooling device.

[0062] This is advantage in that thermal profiles of the semiconductor chip and the thermoelectric cooling device are aligned so that cooling is applied from the thermoelectric cooling device when heat is generated at the semiconductor chip. Further, heat is applied from the thermoelectric cooling device when no heat is generated in the semiconductor chip. This is advantages in that it has the effect, that it reduces maximum and minimum temperature peaks of the semiconductor chip and thereby the thermal stress. Hence, a key contributor to degradation of the semiconductor chip is reduced. The control system may comprise one or a plurality of independent controllers controlling the semiconductor chips and / or the thermoelectric cooling devices.

[0063] According to an embodiment of the invention, the control of the current to the first thermoelectric cooling device includes allowing the current to flow when the semiconductor chip is in a conducting mode and preventing current from flowing when the semiconductor chip is in a non-conducting mode. This is advantageous in that it has the effect, that the current to the thermoelectric cooling device is a current pulse facilitating the creation of the super cooling period and the recovery period of the thermal profile of the thermoelectric cooling device. [0064] This is advantageous in that it has the effect, that the thermal peak amplitudes of the thermal profile of the semiconductor chip are reduced. The positive peak amplitude i.e. the maximum temperature of the semiconductor chip is reduced do to the super cooling period. The negative peak amplitude i.e. the minimum temperature of the semiconductor chip is increased due to the recovery period. The control strategy is advantageous in that the temperature variation of the semiconductor chip i.e. DT (delta T) is reduce. The effect of reducing delta T is a reduced thermal stress of the semiconductor chip and thereby an increased lifetime of the semiconductor chip. Further, the effect of reducing average temperature is that an increment of the applied current into the semiconductor chip up to the chip average temperature reached its design level is possible. Thereby an increased current density of the semiconductor chip is achieved.

[0065] According to an embodiment of the invention, the number of semiconductor chips of the power module is the same as the number of thermoelectric devices. [0066] According to an embodiment of the invention, one thermoelectric device is thermic connected to more than one semiconductor chip. In a power module comprising a plurality of semiconductor chips located close together, cooling effect from more than one thermoelectric device may cool one or more semiconductor chips [0067] According to an embodiment of the invention, the heat sink comprises a cooling fluid passage having one or more inlets allowing a cooling fluid to enter the closed cooling fluid passage and one or more outlet allowing the cooling fluid to leave the cooling fluid passage. This is advantages in that it has the effect, that a high cooling effect can be obtained be a low mass flow of cooling fluid. [0068] According to an embodiment of the invention, the thermoelectric cooling devices are positioned in a ridged baseplate prior to mounting on the power module. This is advantages in that it has the effect, that the location can be predetermined e.g. based on simulations to ensure that the thermoelectric cooling devices are positioned at hot spots of the power module. [0069] The base plate is preferably molded or printed in ridged material such as plastic which are cheap. Alternatively, a completed island like systems can be mounted on a flexible substrate if the power module has to be applied on the surfaces with curvature. Accordingly, in such embodiment, the baseplate is not ridged as is preferred in most embodiments, [0070] According to an embodiment of the invention, the thermoelectric cooling devices are fixed to a printed circuit board via the heat sink hereof.

The drawings

[0071] For a more complete understanding of this disclosure, reference is now made to the following brief description, taken in connection with the accompanying drawings and detailed description, wherein like reference numerals represent like parts:

Figure 1 illustrates a schematic presentation of elements of the present invention,

Figure 2a and 2b illustrates overlapping of thermal profiles of the semiconductor chip and the thermoelectric cooler,

Figure 3 illustrates thermal gradients in the thermoelectric semiconductor module,

Figure 4a illustrates an embodiment of the thermoelectric semiconductor module

Figure 4b illustrates another embodiment of the thermoelectric semiconductor module

Figure 5 illustrates temperature of a semiconductor chip,

Figure 6 illustrates timing of current, voltage and temperature of the thermoelectric semiconductor module,

Figure 7a and 7b illustrates the pulsing current to the thermoelectric cooler,

Figure 8 illustrates a first embodiment combining the thermoelectric cooler with a primary heat sink, and

Figure 9 illustrates a second embodiment combining the thermoelectric cooler with a primary heat sink.

It should be mentioned, that the plots of some figures are not representing one single simulations or experiment, but is only used to increase understanding of the present invention.

Any of the drawing and embodiments of this description can be combined in any way. Detailed description

[0072] The present invention, represents a major step forward for high reliability of power convertors. The proposed invention can be applied to high power electronic devices such as IGBTs, which are essential in a range of energy devices such as wind turbines and any kind of electronic device with transient temperature variation within short period of time.

[0073] In this document a reference to a semiconductor chip 1 is a reference to a semiconductor chip 1 including IGBT, MOSFET, diodes, Light emitting diodes, etc. Hence, when using the term semiconductor chip 1, a reference to any such semiconductor device is understood.

[0074] Further, in this document a reference to a thermoelectric device is a reference to a TE cooler 4 including an array of thermoelectric elements 3.6 and one or more ceramic, coated and or solder layers. Hence, when using the term TE cooler 4, a reference to such thermoelectric device is understood. [0075] Further, in this document a semiconductor module, thermoelectric semiconductor module and hybrid power electronic-thermoelectric module is used as reference to a module comprising a semiconductor chip 1, a TE cooler 4 and a micro- structured heat sink 8.

[0076] Further, in this document a power module is used as reference to an electronic device comprising a plurality of semiconductor chips 1.

[0077] Figure 1 illustrates schematically the elements of the present invention. These are a semiconductor chip 1, thermally connected to a TE cooler 4 and to a heat sink 8. An external controller 11 is controlling the switching frequency of the semiconductor chip 1 and thereby its sinusoidal modular frequency 5. The modular frequency 5 is provided to a controller 7 which based hereon establishes a pulsing current 6 to the TE cooler 4 via a current source 10. The cold side of the TE cooler 4 is towards the semiconductor switch and the hot side of the TE cooler 4 is towards a heat sink 8. The heat sink comprises micro-structures establishing a cooling passage in which flow of cooling fluid is controlled by a cooling system 12

[0078] Figure 2a illustrates an example of a modulation frequency of current flow through a semiconductor chip 1 controlled by or referred to as the modular frequency 5. As illustrated, the current flow through the semiconductor chip 1 is transient i.e. gives rise to large temporal fluctuations in current and subsequently temperature within the semiconductor chip 1. This is a significant contributor to reduced lifetime of such semiconductor chips 1. With the application of a constant current to the TE cooler 4, as suggested in the prior art, only the average temperature of the semiconductor chip 1 can significantly be reduce, while the inflation of the temperature fluctuation (variation between highest and lowest temperature in the semiconductor chip) remains almost constant.

[0079] Figure 2b is an enlarged view of the thermal profile of the semiconductor chip 2 and the thermal profile of the TE cooler 3. Note that on figure 7b, there is an illustration of the thermal profile of the TE cooler 4 alone (note that figure 7b is found in paper by Yang et. al. Energy Conversion and Management 46 (2005) 1407-1421). As illustrated there is an overlap between part of the super cooling period 3a and part of the temperature increasing period 2a leading to a reduction of the maximum temperature of the semiconductor chip 1. Further, there is an overlap between part of the recovery period 3b and part of the temperature decreasing period 2b leasing to an increase of the minimum temperature of the semiconductor chip 1. This together leads to a reduced temperature variation and thereby thermal stress of the semiconductor chip 1.

[0080] The present invention proposes a novel and inventive technique and hybridization approach limiting temperature stress of the chip 1 substantially, through the implementation of TE cooler 4.

[0081 ] Furthermore, the temperature management technique proposed by the present invention is advantageous in that it has the effect, that it makes it possible to boost the current in the semiconductor chip 1 keeping the average temperature and range of temperature fluctuation lower than possible with known techniques.

[0082] The TE cooler 4 is able to enhance the energy conversion efficiency, life-time and advancements in the power electronic module (particularly in semiconductor chips such as an IGBT) architecture by control of temperature distribution in the semiconductor chips and thereby in the entire power module. The control of the TE cooler 4 may be designed to react immediately to changes in current flow through the semiconductor chip 1 and thereby actively move the high temperature zone away from the critical junctions (at the semiconductor chip 1) to a heat sink 8 through an efficient thermal pathway. This means that there is no delay between the heat generation and active cooling onset.

[0083] This is illustrated in figure 3 where graph 30 illustrates an example of temperature of a semiconductor chip 1 without cooling by the present invention. Graph 31 illustrates that the high temperature zone is moved from the semiconductor chip 1 to the TE cooler 4

[0084] The present invention is advantages in that the TE cooler 4 is controlled to facilitate immediate responds in terms of cooling capacity to current variations to the TE cooler 4 controlled by the pulsing current 6 with no or at least high upper limit to its cooling capacity. This is obtained by controlling the pulsing current 6 to the TE cooler 4 on the same modulation frequency as the semiconductor chip 1 itself i.e. matching current magnitude through the TE cooler (and thus cooling capacity) instantaneously by means of the pulsing current 6 to the temperature increasing period of the thermal profile of the semiconductor chip 1 generated by current flow through the semiconductor chip 1. Hence, any change in the modulation frequency 5 of the semiconductor chip 1 (i.e. the modular frequency 5) will cause an instantaneous change in the cooling capacity of the TE cooler 4, having the effect of a reduced temperature variation compared to prior art system.

[0085] The physical design of the thermoelectric semiconductor module (including the hybrid power electric thermoelectric module) is preferably adapted to the specific modular frequency or range of modular frequencies of operation the semiconductor chip 1. The adaption of the cooling capacity to changes in the modular frequency is therefore possible only due to the changes in the pulsing current 6.

[0086] Figure 4 illustrates time dependent current density imposed to the TE cooler 4 controlled by or referred to as the pulsing current 6. The critical parameters of the pulse shaped current 6, together with the thickness and thermal impedance of the TE cooler 4, are the ratio of the imposed current and the optimum current, pulse width ratio, pulse high and the time pulse starts. The mentioned parameters have significant influence on cooling performance of the TE cooler 4 and, consequently, the temperature distribution of the hot spots generated by the semiconductor chip 1.

[0087] The temperature management can be achived by thermal connecting a TE cooler 4 to the semiconductor chip 1 as illustrated on figure 4a or integrated the TE coller 4 and the semiconductor chip 1 as illustrated in figure 4b.

[0088] Figure 4a illustrates the more simple implementation of the TE cooler 4. The attachment of the TE cooler to the semiconductor chip 1 is preferably made by means of a coated soldering layer 42, 43.

[0089] In order to increase reliability of the temperature management of the present invention, the TE cooler 4 needs to be capable of fast response to changing in the current and thereby temperature variation of the semiconductor chip. To achieve this, a compact thermoelectric semiconductor module design is proposed integrated with the semiconductor chip 1 as illustrated on figure 4b.

[0090] To make this design as compact as possible, the design includes a micro- structured heat sink (pHS) 8 fabricated on the hot ceramic substrate of the TE cooler 4. Fabrication of the micro-channels (or micro-structured fins) of the heat sink 8 on the bottom ceramic substrate of the TE cooler 4, offers a compact design, reduces thermal resistance and helps to further reduce the hot junction temperature of the TE cooler 4. Manufacturing of the coolant fins (micro-structures of the heat sink) on the ceramic layer of the thermoelectric device then the heat sink 8 becomes part of the thermoelectric cooler 4 as an hybrid thermoelectric-heat sink device. This is what is illustrated in figure 4a, the illustration of figure 4b shows the heat sink 8 is preferably connected to the TE cooler 4 by means of a further ceramic layer 413 and a further coated layer 414.

[0091] This design is referred to as a hybrid power electric thermoelectric module (or simply (thermoelectric) semiconductor module) 9 and has the advantage that the thermal resistance of hereof is reduced compared to prior art designs and the design illustrate on figure 4a. The smaller thermal resistance provided in the system, the higher performance of the TE cooler 4 and thereby response to the variations of the operating conditions mainly the temperature variations in the electronic device. Accordingly, by the present invention, the cooling capacity can be varied by varying the pulsing current 6 in response to the modulation frequency i.e. in response to variations of the operation conditions of the semiconductor chip 1.

[0092] The dynamic temperature control of the semiconductor chip 1 hot spots of the present invention provides possibility for the semiconductor chip 1 to operate under the heat sink temperature and even under the ambient temperature, depending on the amount of heat flux that needs to be removed from the semiconductor chip 1.

[0093] To ensure sufficient capability of the TE cooler 4 to discharge the thermal energy during operation of the semiconductor chip 1, efficient enhanced integrated cooling technologies is preferably applied to the hot side of the TE cooler 4 to transfer the large heat flux across the semiconductor module 9 to the ambient environment. The excess heat flux crosses a small area of the semiconductor module 9, therefore for efficient energy collection and a cost-efficient design a micro-structured heat sink 8 can be properly integrated to the hybrid power electronic-thermoelectric module 9.

[0094] In this design, the micro-structured heat sink 8 is fabricated on the bottom (hot side of TE cooler) ceramic substrate of the TE cooler 4. One advantage of using micro-structured heat sink 8 is that, not only there is no need to keep traditional heat sinks; the base plate of the semiconductor chip 1 can be replaced with cheaper materials. The substituted base plate should still be able to be robust enough to keep the semiconductor module elements together, but does not need e.g. to be thermally conductive. Therefore, a cheaper rigid plastic based material can be used instead of the traditional metallic based plates.

[0095] Figure 4b illustrates a side view of a hybrid power electronic-thermoelectric module 9 which according to a preferred embodiment of the invention comprises one or more of the following elements: chip (diode, MOSFET, IGBT, etc.) 41, Solder layer 42, Coated layer (thermal and electrical conductance) 43, Ceramic layer (electrical insulation and thermal conductance) 44, Coated layer (thermal and electrical conductance) 45, Thermoelectric elements (n- and p- types) 46a, 46b (also referred to as so-called Peltier cells), Coated layer (thermal and electrical conductance) 47, Ceramic micro-structured heat sink 4.8, Mico-fms or micro-channels 49, Printed Circuit Boards (PCBs) 410, Inlet and outlet of the heat sink 411 and Plastic cover of the heat sink 412

[0096] Accordingly, the hybrid power electronic thermoelectric module 9 comprise both semiconductor chip elements, TE cooling elements, heat sink elements and structural elements. The flow of cooling fluid in the cooling fluid passage created by the micro-structure of the heat sink 8 is preferably regulated by the same controller 7 as controlling the pulsing current 6. The flow may be controlled by a pump or fan.

[0097] As described above, the generation of the pulsing current 6 to the TE cooler 4 facilitates an intelligent cooling of the semiconductor chip 1. The effect hereof is not only a reduction of the average temperature of the semiconductor chip 1 but also a reduction of the and temperature fluctuation of the semiconductor chip 1 / power module.

[0098] It should by note, that in the present invention, the ceramic substrate of the semiconductor chip 1 is used as the cold side ceramic substrate of TE cooler 4 it is of particular importance that the area only underneath the semiconductor chip 1 is used for implementation of TE cooler elements, not total surface of the ceramic substrate of the semiconductor chip 1. This is an important factor in reduction of price in that in this way, the number of thermoelectric elements are reduced significantly. [0099] Figure 5 illustrates example plots of variations of chip la temperature of the semiconductor chip 1. The top graph of figure 5 illustrates operation of the semiconductor chip 1 with no TE cooler 4. In this example, this leads to an average temperature of 90.86°C with a delta temperature between highest and lowest temperatures of 6.99°K. The bottom graph of figure 5 illustrates operation of the chip la / semiconductor chip 1 with a TE cooler 4 to which a constant current is applied (prior art method). In this example, this leads to an average temperature of 2.06°C with a delta temperature of 6.83°K. Hence, the difference between the operation of the semiconductor chip 1 with no cooling and cooled by a TE cooler 4 receiving a constant current is a reduction of average temperature of 88.8°C and a reduction of delta temperature of only 2.29%.

[0100] Hence the effect of the prior art method is a significant reduction of average temperature, but an almost insignificant reduction of delta temperature and thereby in thermal stress of the semiconductor chip 1. Accordingly, prior art methods are efficient in reducing the average temperature the effect of which is that the flow of current through the semiconductor chip 1 can be increased. However, the degradation of the semiconductor chip 1 due to thermal stress is insignificant.

[0101] By providing a pulsing current to the TE cooler 4 which is aligned with the modulation frequency of the semiconductor chip 1, the average temperature is reduced to 27.8°C and the delta temperature is reduced to 2.55°K illustrated by the middle graph of figure 5. Accordingly, the present invention reduces both the average and delta temperature of the semiconductor chip 1 generated by the periodic heat flux generated by the chip la due to the modular frequency controlled by the modular frequency 5.

[0102] According to the example plots of figure 5 (see the pulsing current 6 and a diode current representing the modular frequency 5 of the heating current through or across the semiconductor chip 1 in figure 6), the heat loss variation follows an absolute value of a sine function with maximum heat loss 180 W/sq.cm with frequency of 50 Hz in the chip. Hence, as illustrated on figure 5 by the middle graph, by implementation of the present temperature management, not only is the average temperature of the chip la reduced about 63 °C, but more important, the temperature fluctuation is reduced about 64.52 %. Hence, a huge reduction of a significant contribution to degradation of the semiconductor chip 1 and thereby an increased lifetime of the semiconductor chip 1 can be expected by implementing the present invention.

[0103] The possibility of adjusting both the average temperature and the delta temperature is of particular relevance in many applications where currents much higher than normal load current through the semiconductor chip 1 only seldom occurs. During normal operation, the delta temperature is controlled (by pulsing current to the TE cooler 4) to be as small as possible to increase life time of the semiconductor chip 1. During the infrequent periods of very high load current through the semiconductor chip 1 the average temperature is controlled (by constant current to the TE cooler 4) to be as low as possible to, during this short period, allow the high load current without damaging the semiconductor chip 1 by the high temperature following the high load current. Hence by implementing the temperature management of the present invention semiconductor designs do not need to be oversized to be able to comply with high temperatures caused by the infrequent very high load currents.

[0104] In other words, applying the TE cooler 4 with pulse current, enhance ability of the semiconductor chip 1 to pass higher current density while the average temperature and the amplitude of temperature difference is the same as the situation where no cooling is applied to the semiconductor chip 1. For example, as shown in figure 6, the heat loss, and consequently the current passing through the chip la can reach up to 450 W/sq.cm when the TE cooler is used, in comparison with 180 W/sq.cm for the case of IGBT-only. Although the current density is increased 2.5 times, the average temperature and range of the temperature fluctuation remains the same. It is worth to noticing (from the graphs on figure 6) that average coefficient of performance (COP) of the TE cooler 4 is 0.57 during the operation.

[0105] As mentioned above in relation to figure 3, the TE cooler 4 can be thermally connected to the semiconductor chip 1 or to a power module comprising a plurality of semiconductor chips. The location of the TE coolers 4 at the power module can be determined based on a thermal analysis of the power module i.e. based on knowledge of where hot spots of the power module are present.

[0106] A plurality of semiconductor cells 1 located together may be referred to as a power module. A power module may be part of a converter e.g. for a wind turbine hence the load current of such power module is high and obviously requires cooling. By the dynamic cooling control obtained by the compact and thermoelectric element reducing design provided by the present invention this control can be made intelligent. In addition to the intelligent control, the physical design of the thermoelectric semiconductor modules 9 can be adapted to the modular frequency of typically 50Hz or 60Hz (with reference to the power module in a wind turbine). In addition, the island like TE coolers 4 and or island like hybrid power electric thermoelectric module 9 can be positioned exactly where the hot spot of the power module is present.

[0107] The pulse dimensions and the geometry of the thermoelectric cooler will preferably be designed based on operation function of the heat source (semiconductor chip 1).

[0108] A so-called optimal steady state current is found as the current to the TE cooler 4 leading to the highest temperature difference between the semiconductor chip 1 and the hot side of the TE cooler 4, or as the current to the TE cooler 4 leading to maximum coefficient of performance (COP) of the TE cooler. A fraction of this optimal current is used as basis current to TE module, this is illustrated on figure 7a. Value of the base current is: 0<I_base/I_opt ^<=l .

[0109] The magnitude of the pulses (PM) is determined based on the modular frequency and thereby the needed cooling capacity as a constant multiplied to the base current. This constant is preferably larger than 0 and smaller than or equal to 5 (0 < PM <= 5).

[0110] Further, the cooling capacity of the TE cooler is controlled by the duration of the top current pulse. The pulse duration (PD) shown in figure 7a is determined as a ratio of imposed current duration into the TE cooler over the heating period of the semiconductor chip. The range of this value is between 0 and 1.5 times of the heating period.

[0111] Further, the cooling capacity of the TE cooler is controlled by the delay of the pulse of the pulsing current 6 relative to the current generating the temperature increase in the semiconductor chip 1. The delay is determined as a fraction of the modular frequency or period of one thermal cycle. The range of this value can be ±50% of the thermal cycle, but the recommended rage is ±10% of the thermal cycle.

[0112] Optimal response time and pulse shape of the pulsing current 6 to the TE cooler 4 strongly depends on the thickness and materials properties (thermal conductivity, thermal diffusion etc.) in between the TE materials and the hot spot, semiconductor chip as an example and a precise controller 7 is required. Along with the controller 7, a DC power supply (current source 10) would be required as source of the current the pulsing shape of which is established by the controller 7.

[0113] Figure 8 and 9 illustrates embodiments of the invention, where efficiency of energy used to establish the cooing effect of the TE cooler 4 is enhanced and thereby overall coefficient of performance of the supercooling system is increased. These embodiments are directed to applications where the operating temperature of the power electronics 1 increases dramatically for a short period updated design of supercooling are suggested. The critical conditions are due to temporary boosting of the current density through the semiconductor switch(es) 1 during acceleration in applications such as trains, electric cars, elevators, etc..

[0114] Tinder these circumstances, a primary heat sink 415 provides constant cooling for the semiconductor chip 1 during regular conditions i.e. normal operation after or before an acceleration or max performance. The primary heat sink 415 may be any kind of known heat sink, that is suitable for conducting heat such as an aluminium plate or grill. During the normal operation period, which may be a short time of the total time of operation, the TE cooler 4 is not activated, i.e. the primary heat sink 415 is able to keep the semiconductor chip 1 within a desired temperature range. The TE cooler 4 starts operating with the adapted current and secondary heat sink, to provide super-cooling for the semiconductor chip 1 in the critical period when the temperature of the device critically increases. This period could as suggested be when a car, elevator or the like accelerates. Therefore, the supercooling is used only in a specific and short period and the overall coefficient of performance of the supercooling system increases in that when not needed, the TE cooler 4 is not in used and thereby does not consume energy.

[0115] Figure 8 illustrates one way of designing a thermoelectric semiconductor module 9 facilitating the temporary supercooling. In figure 8 the primary heat sink 415 is located underneath of the semiconductor chip 1, while the primary heat sink 415 is attached to a TE cooler 4 and the secondary heat sink 8. This embodiment where the primary heat sink 415 is between the semiconductor chip 1 and the TE cooler 4 is advantageous in that the semiconductor chip 1 can be mounted using conventional wire bounding i.e. if it is desired not to change design of the thermoelectric semiconductor module 9.

[0116] Figure 9 illustrates an alternative design where the semiconductor chip 1 is permanently cooled by the primary heat sink 415 from its top, while the supercooling from the TE cooler 4 is applied from the bottom of the semiconductor chip 1 during the critical period. In this design, a copper strip (located between the primary heat sink 415 and the semiconductor chip 1) 416 is required to conduct the power to the semiconductor chip 1. This embodiment where the chip is in between the primary heat sink 415 and the TE cooler 4 is advantageous in that the TE cooler cools the semiconductor chip 1 directly and do not have to remove heat from both the primary heat sink 415 and from the semiconductor chip 1.

[0117] As is now clear from the above description, the present invention disclose integration of a thermoelectric cooler 4 and preferably also a micro-structured heat sink 8 with power electronic / semiconductor chip such as an IGBT 1. The effect hereof is to enhance life-time and reliability of the semiconductor chip 1 and to enhance imposed current density to the power / semiconductor module. As mentioned, these effects are obtained by controlling the temperature fluctuation (temperature variations) in the semiconductor chip 1 relative to / due to the modular frequency of the semiconductor chip 1. By imposing a periodic current to the TE cooler by the control frequency 6, the range of temperature fluctuation is reduced. Further, the present invention discloses how to integrate a micro-structured heat sink (pHS) 8 on the hot ceramic substrate of the TE cooler 4. The integration has a minimum effect on the existing design of semiconductor chip 1.

[0118] It should be mentioned, that the present invention is useful to manage temperature distribution of any kind of heat source where the generated heat is transient within a short period of time.

[0119] Finally, it should be mentioned that an additional advantage, of the present invention is that the TE cooler 4 will also be able to act as active temperature controllers, alleviating problems with cold starts in arctic regions. This is because of the heat generated during the recovery period 3b.

[0120] Further, the present invention is particularly advantageous in applications where a precise temperature of a semiconductor chip is required. Such application includes e.g. DNA analysis.

List

1. Semiconductor chip

2. Thermal profile of semiconductor chip

a. Temperature increasing period of thermal profile of semiconductor chip

b. Temperature decreasing period of thermal profile of semiconductor chip

3. Thermal profile of thermoelectric cooling device

a. Super cooling period of thermal profile of thermoelectric cooling device

b. Recovery period of thermal profile of thermoelectric cooling device

4. Thermoelectric cooling device

5. Modular frequency

6. Pulsing current

7. Controller

8. Heat sink

9. Thermoelectric semiconductor module (also including the hybrid power electric thermoelectric module)

10. Current source

11. External controller

12. Cooling system

30. Graph illustrating the temperature profile of a conventional power module from the semiconductor chip to the heat sink

31. Graph illustrating the temperature profile of a power module of the present invention from the semiconductor chip to the micro-structured heat sink

41. Semiconductor chip (same as reference number 1)

42. Solder layer

43. First coated layer

44. First ceramic layer

45. Second coated layer 46. Thermoelectric elements

46a. and 46b. n-type and p-type thermoelectric cooling elements

47. Third coated layer

48. Micro-structured heat sink

49. Micro-channels

410. Printed circuit board

41 la and 41 lb inlet and outlet to micro-channels

412. Cover

413. Further ceramic layer

414. Further coated layer

415. Primary heat sink

416. Conductive layer

Claims

Patent claims

1. A method of controlling thermal stress of a semiconductor chip (1), the method comprises the steps of:

- establishing a modular frequency of the semiconductor chip (1) and thereby a thermal profile (2) of the semiconductor chip (1),

- establishing a pulsing current (6) controlling the thermal profile (3) of a thermoelectric cooling device (4) thermally connected to the semiconductor chip (1), wherein the pulsing current (6) is generated in response to the modular frequency (5), so that a super cooling period (3a) of the thermal profile (3) of the thermoelectric cooling device (4) is at least partly overlapping a temperature increasing period (2a) of the thermal profile of the semiconductor chip (1), and

a recovery period (3b) of the thermal profile (3) of the thermoelectric cooling device (4) is at least partly overlapping a temperature decreasing period (2b) of the thermal profile (2) of the semiconductor chip (1).

2. A method according to claim 1, wherein the modular frequency (5) is received by a controller (7) and the pulsing current (6) is established by the controller (7) based on the received modular frequency.

3. A method according to any of claims 1 or 2, wherein the pulsing current (6) varies between a pulse bottom current and a pulse top, wherein the value of the pulse bottom current is determined as a fraction of an optimum current.

4. A method of any of the preceding claims, wherein the base current is within the range of ±10 % of the optimum current of a TE cooler working under a steady state condition, which cause the maximum temperature difference between the semiconductor chip (1) and hot side of the thermoelectric cooling device or provides maximum (COP) (4).

5. A method of any of the preceding claims, wherein the optimum current is based on a maximum coefficient of performance or maximum temperature difference of the semiconductor chip 1 and the hot side of the TE cooler (4).

6. A method of any of the preceding claims, wherein the fraction of the optimum current is established as a base current divided by the optimum current, wherein the base current is larger than 0 A, but smaller or equal than the optimum current.

7. A method of any of the preceding claims, wherein the value of the pulse top current is established by multiplying a pulse magnitude constant to the base current, wherein the pulse magnitude constant is between 0.1 and 5.

8. A method of any of the preceding claims, wherein a pulse of the pulsing current is delayed between -50% and 50% of a period of the modulation frequency, preferably between -10% and 10% of a period of the modulation frequency.

9. A method of any of the preceding claims, wherein the duration of a top pulse current is shorter than the duration of the temperature increasing period of the modular frequency.

10. A method of any of the preceding claims, wherein the duration of the top pulse current is between 0,1% and 0,95% of the duration of the temperature increasing period of the modular frequency.

11. A method of any of the preceding claims, wherein the control frequency (6) preferably is a square formed control signal.

12. A method of any of the preceding claims, wherein the thermoelectric cooling device (4) is a thin film type.

13. A method of any of the preceding claims, wherein the thermoelectric cooling device (4) is a bulk type.

14. A thermoelectric semiconductor module configured for adjusting temperature of a semiconductor chip (1), the thermoelectric semiconductor module comprises a plurality of elements including: a semiconductor chip (41),

- a solder layer (42),

a first ceramic layer (44) facilitates electrical insulation and thermal conductance,

a second coated layer (45) facilitates both thermal and electrical conductance,

- thermoelectric elements (46) including both n-type (46. a) and p- type (46. b) thermoelectric cooling elements,

a third coated layer (47) facilitates both thermal and electrical conductance, a micro-structured heat sink (48) including micro-channels (49), and a printed circuit board (410) electrically connected to the semiconductor chip (41) by means of bond wires, wherein the semiconductor chip (41) is thermally connected to the thermoelectric elements (46) by means of the solder layer (42), the first ceramic layer (44) and the second coated layer (45), wherein the thermoelectric elements (46) are thermally connected to the fluid in the micro-channels (49) of the micro-structured heat sink (48) by means of the third coated layer (47), thereby creating a thermal connection between the semiconductor chip (41) and the fluid of the micro-channels (49)

15. A thermoelectric semiconductor module according to claim 14, wherein the first ceramic layer (44) connected to the semiconductor chip (41) by the solder layer (42) is coated by a first coated layer (43), wherein the coated layer is both thermal and electrical conductive.

16. A thermoelectric semiconductor module according to claim 14 or 15, wherein the thermoelectric semiconductor module further comprises a further ceramic layer (413) and a further coated layer (414) located between the third coated layer (47) and the micro-structured heat sink (48), wherein the further ceramic layer (413) facilitates electrical insulation and thermal conductance and the further coated layer (414) facilitates both thermal and electrical conductance.

17. A thermoelectric semiconductor module according to any of the preceding claims 14-16, wherein the heat sink (48) comprises a cooling fluid passage formed by micro- channels (49) having an inlet (41 la) allowing a cooling fluid to enter the cooling fluid passage and an outlet (41 lb) allowing the cooling fluid to leave the cooling fluid passage.

18. A thermoelectric semiconductor module according to any of the preceding claims 14-17, wherein the inlet (41 la) allowing the cooling fluid to enter the cooling fluid passage is located between two outlets (41 lb) of the cooling fluid passage.

19. A thermoelectric semiconductor module according to any of the preceding claims 14-18, wherein the heat sink (48) is covered by a cover (412).

20. A thermoelectric semiconductor module according to any of the preceding claims 14-19, wherein the micro-structured heat sink (48) preferably is a ceramic micro- structured heat sink.

21. A thermoelectric semiconductor module according to any of the preceding claims 14-20, wherein the closed cooling fluid passage enables flow of cooling fluid in opposition directions at the same time.

22. A thermoelectric semiconductor module according to any of the preceding claims 14-21, wherein the area of the cooling fluid passage is at least the same size as the area covered by the thermoelectric cooling elements (46).

23. A thermoelectric semiconductor module according to any of the preceding claims 14-22, wherein the flow of cooling fluid in the cooling fluid passage is dynamic.

24. A thermoelectric semiconductor module according to any of the preceding claims 14-23, wherein the heat sink further comprises a first anchor part and a second anchor part facilitating mounting of electric connections to the semiconductor chip.

25. A thermoelectric semiconductor module according to any of the preceding claims 14-24, wherein the heat sink further comprises a recess between the first and second anchor parts wherein the size of the recess is larger than the size of the thermoelectric cooling device thereby enabling mounting of the thermoelectric cooling device in the recess.

26. A thermoelectric semiconductor module according to any of the preceding claims 14-25, wherein the thermoelectric semiconductor module is positioned on a ridged baseplate prior to mounting on the power module.

27. A thermoelectric semiconductor module according to any of the preceding claims 14-26, wherein the thermoelectric semiconductor module is attached to the printed circuit board (410).

28. A thermoelectric semiconductor module according to any of the preceding claims 14-27, wherein a primary heat sink (415) is located between the semiconductor chip (41) and the thermoelectric elements (46).

29. A thermoelectric semiconductor module according to any of the preceding claims 14-27, wherein the semiconductor chip (41) is located between a primary heat sink (415) and the thermoelectric elements (46).

30. A system for thermal control of a semiconductor chip of a power module, the system comprises:

- a plurality of thermoelectric cooling devices wherein each individual thermoelectric cooling device of the plurality of thermoelectric cooling devices has a cooling area in a first plan,

- a plurality of semiconductor chips having a semiconductor area in the first plan, wherein the individual semiconductor chips of the plurality of semiconductors devices are located above an individual thermoelectric cooling device so that the semiconductor area and the cooling area is at least partly overlapping, - a control system configured for controlling the modular frequency and thereby a thermal profile of at least one of the plurality of semiconductor chips, the thermal profile of the semiconductor chip includes a temperature increasing period and a subsequent temperature decreasing period, wherein, the control system is furthermore configured for controlling the current to and thereby a thermal profile of at least one of the plurality of thermoelectric cooling devices, the thermal profile of the thermoelectric cooling device includes a super cooling period and a subsequent recovery period, wherein heat is generated from the thermoelectric cooling device during the recovery period, and wherein the control of the current to a first thermoelectric cooling device of the plurality of thermoelectric cooling devices is controlled in response to the modular frequency of a first semiconductor chip of the plurality of semiconductor chips, and wherein the semiconductor area of the first semiconductor chip is at least partly overlapping the cooling area of the first thermoelectric cooling device.

31. A system according to claim 30, wherein the control of the current to the first thermoelectric cooling device includes allowing the current to flow when the semiconductor chip is in a conducting mode and preventing current from flowing when the semiconductor chip is in a non-conducting mode.

32. A system according to claims 30 or 31, wherein the number of semiconductor chips of the power module is the same as the number of thermoelectric devices.

33. A system according to any of the claims 30-32, wherein one thermoelectric device is thermic connected to more than one semiconductor chip.

34. A system according to any of the claims 30-33, wherein the heat sink comprises a cooling fluid passage having one or more inlets allowing a cooling fluid to enter the closed cooling fluid passage and one or more outlet allowing the cooling fluid to leave the cooling fluid passage.

35. A system according to any of the claims 30-34, wherein the thermoelectric cooling devices are positioned in a ridged baseplate prior to mounting on the power module.

36. A system according to any of the claims 30-35, wherein the thermoelectric cooling devices are fixed to a printed circuit board via the heat sink hereof.