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WO2019210776A1 - 阵列基板、显示装置、薄膜晶体管及阵列基板的制作方法 - Google Patents

阵列基板、显示装置、薄膜晶体管及阵列基板的制作方法 Download PDF

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Publication number
WO2019210776A1
WO2019210776A1 PCT/CN2019/083096 CN2019083096W WO2019210776A1 WO 2019210776 A1 WO2019210776 A1 WO 2019210776A1 CN 2019083096 W CN2019083096 W CN 2019083096W WO 2019210776 A1 WO2019210776 A1 WO 2019210776A1
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Prior art keywords
layer
array substrate
electrode
metal
active layer
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French (fr)
Inventor
刘宁
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US16/644,261 priority Critical patent/US11177296B2/en
Publication of WO2019210776A1 publication Critical patent/WO2019210776A1/zh
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
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    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
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    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
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    • H10D86/01—Manufacture or treatment
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    • H10D86/01—Manufacture or treatment
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    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10P14/6314—
    • H10P14/6319—
    • H10P14/69392—
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate

Definitions

  • Embodiments of the present disclosure relate to an array substrate, a display device, a thin film transistor, and a method of fabricating an array substrate.
  • a TFT Thin Film Transistor
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the array process is mainly used to fabricate TFT substrates and color filters.
  • At least one embodiment of the present disclosure provides an array substrate including: a base substrate, an active layer, and a cover layer; wherein the active layer is on the base substrate, and the cover layer is located on the active layer Moving away from the substrate substrate side and covering the array substrate, the cover layer comprises a metal conductive portion and a transparent insulating metal oxide portion, the metal conductive portion and the transparent insulating metal oxide portion comprise the same metal element The metal conductive portion is electrically connected to the active layer.
  • the metal conductive portion includes a first electrode and a second electrode, and the first electrode and the second electrode are oppositely disposed and respectively electrically connected to the active layer connection.
  • the metal conductive portion further includes a data line, the first electrode is a source, the second electrode is a drain, and the data line and the source Extremely electrical connection.
  • an array substrate provided by an embodiment of the present disclosure further includes a gate, a gate line, and a gate insulating layer, wherein the gate is located on the substrate and electrically connected to the gate line, the gate The pole insulating layer is located at a side of the gate and the gate line away from the substrate substrate, and the active layer is located at a side of the gate insulating layer away from the gate.
  • the metal conductive portion of the cover layer includes Hf
  • the transparent insulating metal oxide portion of the cover layer includes HfO 2 .
  • the metal conductive portion of the cover layer includes Ta
  • the transparent insulating metal oxide portion of the cover layer includes Ta 2 O 5 .
  • a material of the active layer includes a metal oxide semiconductor including indium gallium zinc oxide, zinc oxide, or zinc oxynitride.
  • an array substrate provided by an embodiment of the present disclosure further includes: a passivation layer, wherein the passivation layer is located on a side of the cover layer away from the active layer.
  • At least one embodiment of the present disclosure also provides a display device including the array substrate of any of the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure further provides a method of fabricating an array substrate, comprising: forming an active layer on a substrate; and forming a surface covering the array substrate on a side of the active layer away from the substrate a cover layer, wherein the cover layer comprises a metal conductive portion and a transparent insulating metal oxide portion, the metal conductive portion and the transparent insulating metal oxide portion comprise the same metal element, the metal conductive portion and the The source layer is electrically connected.
  • the metal conductive portion includes a first electrode and a second electrode, and the first electrode and the second electrode are oppositely disposed and respectively associated with the The source layer is electrically connected, and the covering layer covering the array substrate is formed on a side of the active layer away from the substrate substrate, including: forming a side of the active layer away from the substrate substrate Covering a metal layer of the array substrate; forming a shielding layer corresponding to the first electrode region and the second electrode region on a side of the metal layer away from the active layer; processing the array substrate to The metal layer is not converted into a transparent insulating metal oxide by a region that is not blocked by the shielding layer; and the shielding layer is peeled off.
  • the metal conductive portion further includes a data line
  • the first electrode is a source
  • the second electrode is a drain
  • the data line is The source is electrically connected
  • the covering layer covering the array substrate is formed on a side of the active layer away from the substrate substrate, and further includes: the metal layer is away from the active layer The side forms an occlusion layer corresponding to the data line region.
  • the array substrate is processed to convert a region of the metal layer that is not blocked by the shielding layer into a transparent insulating metal oxide, including : performing an oxygen plasma bombardment treatment on the array substrate to oxidize the region of the metal layer not blocked by the shielding layer to the transparent insulating metal oxide.
  • the occlusion layer is a photoresist layer.
  • the material of the metal layer includes Hf
  • the transparent insulating metal oxide includes HfO 2
  • the material of the metal layer includes Ta
  • the transparent The insulating metal oxide includes Ta 2 O 5 .
  • the material of the active layer includes a metal oxide semiconductor including indium gallium zinc oxide, zinc oxide, or zinc oxynitride.
  • the method for fabricating an array substrate according to an embodiment of the present disclosure further includes: forming a gate electrode and a gate line electrically connected to the gate on the base substrate, and the gate and the gate line A gate insulating layer is formed away from a side of the substrate substrate; wherein the active layer is formed on a side of the gate insulating layer away from the gate.
  • the method for fabricating an array substrate according to an embodiment of the present disclosure further includes forming a passivation layer on a side of the cover layer away from the active layer.
  • At least one embodiment of the present disclosure also provides a thin film transistor including: an active layer, a metal conductive portion, and a transparent insulating metal oxide portion; wherein the metal conductive portion and the transparent insulating metal oxide portion comprise the same metal An element, the metal conductive portion includes a first electrode and a second electrode, the first electrode and the second electrode being oppositely disposed and electrically connected to the active layer, respectively.
  • the metal conductive portion includes Hf, the transparent insulating metal oxide portion includes HfO 2 ; or the metal conductive portion includes Ta, the transparent insulating metal oxide Some include Ta 2 O 5 .
  • FIG. 1 is a schematic diagram of an oxygen plasma bombardment process on an array substrate in the fabrication of an array substrate according to at least one embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of an array substrate according to at least one embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of another array substrate according to at least one embodiment of the present disclosure.
  • FIG. 4 is a schematic plan view showing a pixel unit of an array substrate according to at least one embodiment of the present disclosure
  • FIG. 5 is a flowchart of a method for fabricating an array substrate according to at least one embodiment of the present disclosure
  • FIG. 6 is a flowchart of a method for fabricating a cover layer of an array substrate according to at least one embodiment of the present disclosure.
  • the main processes of the array substrate fabrication process are: glass substrate cleaning ⁇ coating ⁇ cleaning ⁇ photoresist coating ⁇ exposure ⁇ development ⁇ etching ⁇ photoresist stripping ⁇ cleaning ⁇ checking.
  • the coating is divided into a metal film and a non-metal film.
  • the metal film is formed by physical vapor deposition, which is also called sputtering; the non-metal film is formed by chemical vapor deposition.
  • Photoresist coating refers to a process of uniformly coating a photoresist onto a surface of a glass substrate. Exposure is to transfer the pattern on the mask onto the glass substrate coated with photoresist, which requires extremely high precision.
  • the photoresist has positive glue and negative glue.
  • the development is to dissolve and remove the photoresist of the photosensitive portion after the positive glue is exposed, leaving the photoresist of the unphotosensitive portion to form a pattern, or to expose the photosensitive portion after exposure of the negative glue.
  • the photoresist is left to dissolve and remove the photoresist of the unexposed portion to form a pattern.
  • the photoresist left after development becomes a protective mask, and the unprotected film will be removed by an etching process. Stripping of the photoresist means removing the photoresist after the etching process is completed.
  • TFT thin film transistor
  • IGZO Indium Gallium Zinc Oxide
  • the etching solution inevitably damages the formed IGZO active layer, thereby seriously affecting the characteristics of the TFT.
  • At least one embodiment of the present disclosure provides an array substrate, a display device, a thin film transistor, and a method of fabricating an array substrate.
  • the array substrate can prevent the etching liquid from damaging the active layer, and can significantly optimize the characteristics of the TFT.
  • At least one embodiment of the present disclosure provides an array substrate including a substrate substrate, an active layer, and a cap layer.
  • the active layer is on the base substrate, and the cover layer is located on a side of the active layer away from the base substrate and covers the array substrate.
  • the cover layer includes a metal conductive portion and a transparent insulating metal oxide portion, the metal conductive portion and the transparent insulating metal oxide portion including the same metal element, and the metal conductive portion is electrically connected to the active layer.
  • an array substrate provided by some embodiments of the present disclosure includes: a substrate substrate 1; a gate 2 above the substrate substrate 1 and a gate line (not shown) electrically connected to the gate 2; a gate insulating layer 3 on the side of the gate electrode 2 and the gate line away from the substrate 1; an active layer 4 on the side of the gate insulating layer 3 away from the gate 2; and a source layer 4 away from the gate insulating layer 3 is a side (ie, away from the side of the substrate 1) and covers the cover layer 5 of the array substrate.
  • the cover layer 5 includes a metal conductive portion and a transparent insulating metal oxide portion 11 which is the same as the metal element of the transparent insulating metal oxide portion 11.
  • the metal conductive portion includes a first electrode 9 (eg, a source) and a second electrode 10 (eg, a drain) that are oppositely disposed and electrically connected to the active layer 4, respectively.
  • the metallic conductive portion may also include, for example, a data line.
  • the data line is electrically connected to the source 9 (ie, the first electrode).
  • the first electrode 9 is a source
  • the second electrode 10 is a drain.
  • the first electrode 9 may be a drain
  • the second The electrode 10 is a source, and the embodiment of the present disclosure does not limit this.
  • the metal conductive portion may further include a signal line for transmitting other electrical signals, and the signal line may be electrically connected to the first electrode 9 or may be electrically connected to the second electrode 10, and the connection manner may be direct connection or by, for example, The structure of the hole or the like is connected, and the embodiment of the present disclosure does not limit this.
  • the data line or the signal line for transmitting other electrical signals may be additionally prepared by using other materials or other processes, that is, the metal conductive portion may not include a signal line such as a data line, The disclosed embodiments do not limit this.
  • the specific material of the base substrate 1 is not limited.
  • glass, resin, or plastic may be used.
  • the base substrate 1 may be a transparent glass substrate or a transparent plastic substrate.
  • the metal conductive portions of the cover layer 5 (for example, the first electrode 9 and the second electrode 10) and the transparent insulating metal oxide portion 11 include the same metal element, and thus the metal conductive portion and the transparent insulating metal oxide portion 11 can be, for example,
  • the etching process in the process of fabricating the array substrate is omitted, and the etching solution in the wet etching process is avoided.
  • the active layer 4 causes damage, and the characteristics of the TFT are significantly optimized.
  • FIG. 1 is a schematic diagram of an oxygen plasma bombardment process performed on an array substrate in the fabrication of an array substrate according to at least one embodiment of the present disclosure.
  • the forming process of the cap layer 5 may include: forming a metal layer 6 covering the array substrate on a side of the active layer 4 away from the substrate substrate 1.
  • the region where the metal layer 6 is not blocked by the shielding layer 7 is converted into a transparent insulating metal oxide, that is, a transparent insulating metal oxide portion 11; and a peeling barrier layer 7.
  • the formation process of the cover layer 5 further includes: forming a shielding layer corresponding to the data line region on a side of the metal layer 6 away from the active layer 4. 7.
  • the material of the metal layer 6, that is, the material of the metal conductive portion, for example, may be Hf, the material of the transparent insulating metal oxide portion 11 is HfO 2 ; or the material of the metal layer 6, for example.
  • the tantalum (Ta), the material of the transparent insulating metal oxide portion 11 is Ta 2 O 5 .
  • the material of the metal layer 6 may also be a mixture of Hf and Ta, and accordingly, the material of the transparent insulating metal oxide portion 11 is a mixture of HfO 2 and Ta 2 O 5 .
  • the material of the metal layer 6 may also be other metal elements.
  • the material of the transparent insulating metal oxide portion 11 is correspondingly an oxide of the metal element or other types of compounds, which is not limited by the embodiments of the present disclosure.
  • the metal Hf has excellent electrical conductivity and is very stable at normal temperature, and Hf can be oxidized to form a transparent metal oxide HfO 2 at a high temperature.
  • HfO 2 is a ceramic material having a wide band gap and a high dielectric constant, which can well replace an insulating material such as silicon oxide, so that after exposure and development of the metal layer 6 of the array substrate, the unmasked layer of the metal layer 6 7 Protected Hf is converted to HfO 2 to achieve a patterning process. Therefore, the array substrate provided by the embodiment of the present disclosure can avoid damage to the active layer by the etching solution in the wet etching process, thereby significantly optimizing the characteristics of the TFT and improving the yield of the product including the array substrate.
  • the occlusion layer 7 may be a photoresist layer, and may be, for example, a photopolymerization type photoresist layer, a photo-decomposition type photoresist layer, or a photo-crosslinking type photoresist layer.
  • the occlusion layer 7 can also adopt other types of materials, which are not limited by the embodiments of the present disclosure.
  • the active layer 4 may be formed of a semiconductor material.
  • the material of the active layer 4 may be amorphous silicon, microcrystalline silicon, polycrystalline silicon, an oxide semiconductor (eg, a metal oxide semiconductor), or the like.
  • the metal oxide semiconductor includes indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or zinc oxynitride (ZnON).
  • IGZO indium gallium zinc oxide
  • ZnO zinc oxide
  • ZnON zinc oxynitride
  • the metal oxide semiconductor has high carrier mobility and can be driven by a large-sized display device. It is required and is therefore widely used in the fabrication of TFTs. For example, a region where the active layer 4 is in contact with the first electrode 9 and the second electrode 10 can be conductorized by a process of plasma treatment and high-temperature treatment, so that transmission of an electric signal can be better realized.
  • the material of the gate electrode 2 and the gate line may be a copper-based metal, for example, copper (Cu), copper-molybdenum alloy (Cu/Mo), copper-titanium alloy (Cu/Ti), copper-molybdenum-titanium alloy (Cu/Mo/ Ti), copper-molybdenum-tungsten alloy (Cu/Mo/W), copper-molybdenum-niobium alloy (Cu/Mo/Nb), etc.; may also be a chromium-based metal, for example, chromium-molybdenum alloy (Cr/Mo), chrome-titanium alloy ( Cr/Ti), chromium molybdenum titanium alloy (Cr/Mo/Ti), etc. or other suitable materials.
  • Cu copper
  • Cu/Mo copper-molybdenum alloy
  • Cu/Ti copper-titanium alloy
  • Cu/Mo/ Ti copper-molybdenum-titanium alloy
  • Cu/Mo/W
  • the material used as the gate insulating layer 3 may be silicon nitride (SiNx), silicon oxide (SiOx), aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), or other suitable materials.
  • FIG. 3 is a schematic diagram of another array substrate according to at least one embodiment of the present disclosure.
  • the array substrate provided by some embodiments of the present disclosure further includes a passivation layer 8 on a side of the cover layer 5 away from the active layer 4 .
  • the material of the passivation layer 8 may be an organic insulating material (for example, an acrylic resin) or an inorganic insulating material (for example, silicon nitride or silicon oxide).
  • the passivation layer 8 may be a single layer structure composed of silicon nitride or silicon oxide, or a two-layer structure composed of silicon nitride and silicon oxide, which is not limited in the embodiment of the present disclosure.
  • the metal layer 6 where the first electrode 9 and the second electrode 10 are located need not be formed by an etching process, but may be formed by, for example, deposition (for example, sputtering deposition), the metal layer 6 may be distributed over the entire surface.
  • deposition for example, sputtering deposition
  • the array substrate is exemplified by using a bottom gate type structure, that is, a gate electrode and a gate line electrically connected to the gate are disposed on the active layer adjacent to the substrate substrate. One side.
  • the array substrate may also adopt other types of structures, which are not limited in the embodiments of the present disclosure.
  • the array substrate provided by the embodiment of the present disclosure is applied to, for example, a device having a display function
  • a plurality of pixel units arranged in an array may be disposed on the array substrate.
  • FIG. 4 is a schematic diagram of a planar structure of a pixel unit of an array substrate according to at least one embodiment of the present disclosure. As shown in FIG. 4, a plurality of pixel units 20 are disposed in an area on the array substrate defined by the intersection of a plurality of data lines DL and a plurality of gate lines GL.
  • each pixel unit 20 includes a switching transistor including a gate 2, a first electrode 9 (eg, a source), and a second electrode 10 (eg, a drain), a gate 2 of the switching transistor, and a gate line GL Connected, the first electrode 9 of the switching transistor is electrically connected to the data line DL, and the second electrode 10 of the switching transistor is electrically connected to other devices in the pixel unit 20, such as a driving transistor.
  • a switching transistor including a gate 2, a first electrode 9 (eg, a source), and a second electrode 10 (eg, a drain), a gate 2 of the switching transistor, and a gate line GL Connected, the first electrode 9 of the switching transistor is electrically connected to the data line DL, and the second electrode 10 of the switching transistor is electrically connected to other devices in the pixel unit 20, such as a driving transistor.
  • At least one embodiment of the present disclosure also provides a display device including the array substrate of any of the embodiments of the present disclosure. Since the performance of the TFT in the array substrate is better, the display device has better product quality. The technical effect and the implementation principle of the display device are the same as those of the array substrate described in the embodiments of the present disclosure, and details are not described herein again.
  • the specific type of the display device is not limited. For example, it may be a TFT-LCD display device, an AMOLED display device, or the like; the specific product type of the display device is not limited, and may be, for example, an electronic paper, a mobile phone, a display, a display screen, or a flat panel. Any product or component that has a display function, such as a TV, tablet, laptop, digital photo frame, navigator, etc.
  • At least one embodiment of the present disclosure further provides a method of fabricating an array substrate, comprising: forming an active layer on a substrate; and forming a cap layer covering the array substrate on a side of the active layer away from the substrate.
  • the cover layer includes a metal conductive portion and a transparent insulating metal oxide portion, the metal conductive portion and the transparent insulating metal oxide portion including the same metal element, the metal conductive portion being electrically connected to the active layer.
  • the method of fabricating the array substrate will be described below by taking the array substrate shown in FIG. 2 as an example.
  • FIG. 5 is a flowchart of a method for fabricating an array substrate according to at least one embodiment of the present disclosure. As shown in FIG. 2 and FIG. 5, a method for fabricating an array substrate according to some embodiments of the present disclosure includes the following steps:
  • Step S1 forming a gate electrode 2 on the base substrate 1 and a gate line electrically connected to the gate electrode 2;
  • Step S2 forming a gate insulating layer 3 on the side of the gate 2 and the gate line away from the substrate 1;
  • Step S3 forming an active layer 4 on a side of the gate insulating layer 3 away from the gate 2;
  • Step S4 A cover layer 5 covering the array substrate is formed on the side of the active layer 4 away from the gate insulating layer 3 (ie, away from the substrate 1 side).
  • the cover layer 5 includes a metal conductive portion and a transparent insulating metal oxide portion 11 which is the same as the metal element of the transparent insulating metal oxide portion 11.
  • the metal conductive portion includes a source (ie, a first electrode 9) and a drain (ie, a second electrode 10) that are oppositely disposed and electrically connected to the active layer 4, respectively, and a data line electrically connected to the source 9.
  • the gate electrode 2 and the gate insulating layer 3 may be patterned using the same patterning process.
  • the gate insulating layer 3 may be an inorganic insulating layer or an organic insulating layer, and may be formed by physical vapor deposition, chemical vapor deposition, or coating.
  • the active layer 4 may be amorphous silicon, polysilicon, an oxide semiconductor, or the like, and patterned by, for example, a photolithography process.
  • FIG. 6 is a flowchart of a method for fabricating a cover layer of an array substrate according to at least one embodiment of the present disclosure. As shown in FIG. 1 , FIG. 2 and FIG. 6 , a method for fabricating an array substrate according to some embodiments of the present disclosure forms a cover layer 5 covering the array substrate on the side of the active layer 4 away from the gate insulating layer 3 . , including the following steps:
  • Step S401 forming a metal layer 6 covering the array substrate on the side of the active layer 4 away from the gate insulating layer 3 (ie, away from the substrate 1 side);
  • Step S402 forming a shielding layer 7 corresponding to the source (ie, the first electrode 9), the drain (ie, the second electrode 10), and the data line region on the side of the metal layer 6 away from the active layer 4;
  • Step S403 performing an oxygen plasma bombardment treatment on the array substrate, and oxidizing the region of the metal layer 6 that is not blocked by the shielding layer 7 into a transparent insulating metal oxide (ie, the transparent insulating metal oxide portion 11);
  • Step S404 peeling off the occlusion layer 7.
  • the region where the metal layer 6 is not blocked by the shielding layer 7 may be oxidized into a transparent insulating metal oxide by performing an oxygen plasma bombardment treatment on the array substrate, and in other embodiments of the present disclosure, The region in which the metal layer 6 is not blocked by the shielding layer 7 can also be converted into a transparent insulating metal oxide by other treatment methods, which is not limited in the embodiment of the present disclosure.
  • the array substrate fabricated by the method provided in this embodiment is subjected to an oxygen plasma bombardment treatment on the array substrate after forming a shielding layer covering the corresponding source, drain and data line regions on the side of the metal layer away from the active layer.
  • the metal layer not blocked by the shielding layer is oxidized into a transparent insulating metal oxide, and after the stripping mask layer is processed on the array substrate, the array substrate is patterned to correspond to the source, drain and data line regions. This patterning process avoids damage to the active layer by the etching process, and optimizes the characteristics of the TFT, improving the product quality of the display device including the array substrate.
  • the occlusion layer 7 can be a photoresist layer.
  • the data line may be additionally provided by other materials or processes, that is, the data line may not be formed by the above manufacturing method.
  • the disclosed embodiments do not limit this.
  • the method for fabricating the array substrate may further include: forming a passivation layer 8 on a side of the cover layer 5 away from the active layer 4.
  • the material of the passivation layer 8 may be silicon nitride or silicon oxide.
  • the passivation layer 8 can be formed by physical vapor deposition, chemical vapor deposition, or coating.
  • the material of the metal layer 6 of the array substrate may be Hf, and the transparent insulating metal oxide (ie, the material of the transparent insulating metal oxide portion 11) is HfO 2 ;
  • the material of the metal layer 6 may be Ta, and the transparent insulating metal oxide (that is, the material of the transparent insulating metal oxide portion 11) is Ta 2 O 5 .
  • the material of the metal layer 6 may also be a mixture of Hf and Ta, and accordingly, the material of the transparent insulating metal oxide portion 11 is a mixture of HfO 2 and Ta 2 O 5 .
  • the material of the metal layer 6 may also be other metal elements.
  • the material of the transparent insulating metal oxide portion 11 is correspondingly an oxide of the metal element or other types of compounds, which is not limited by the embodiments of the present disclosure.
  • the material of the active layer 4 may be a metal oxide semiconductor.
  • the metal oxide semiconductor includes indium gallium zinc oxide (IGZO), zinc oxide (ZnO) or zinc oxynitride (ZnON), etc., such metal oxide semiconductors are widely used in TFTs because of high carrier mobility. In the production.
  • At least one embodiment of the present disclosure also provides a thin film transistor including: an active layer, a metal conductive portion, and a transparent insulating metal oxide portion.
  • the metal conductive portion and the transparent insulating metal oxide portion comprise the same metal element, the metal conductive portion comprising a first electrode and a second electrode, the first electrode and the second electrode being disposed opposite each other and electrically connected to the active layer, respectively.
  • the metallic conductive portion comprises Hf and the transparent insulating metal oxide portion comprises HfO 2 .
  • the metallic conductive portion comprises Ta
  • the transparent insulating metal oxide portion comprises Ta 2 O 5 .
  • the thin film transistor further includes a gate insulated from the active layer and corresponding to the active layer.
  • the thin film transistor of at least one embodiment of the present disclosure may be used for an array substrate as a switching element in a pixel unit, and may also be used for other electronic devices as, for example, a switching element or a driving element, for example, for a gate driving circuit (for example, a GOA ( Gate on Array-substrate circuit), the embodiment of the present disclosure does not limit this.
  • a gate driving circuit for example, a GOA ( Gate on Array-substrate circuit
  • the technical effect and the implementation principle of the thin film transistor are the same as those of the array substrate described in at least one embodiment of the present disclosure, and details are not described herein again.

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Abstract

一种阵列基板、显示装置、薄膜晶体管及阵列基板的制作方法，该阵列基板包括：衬底基板(1)、有源层(4)和覆盖层(5)。有源层(4)位于衬底基板(1)上，覆盖层(5)位于有源层(4)远离衬底基板(1)一侧且覆盖阵列基板，覆盖层(5)包括金属导电部分(9、10)和透明绝缘金属氧化物部分(11)，金属导电部分(9、10)和透明绝缘金属氧化物部分(11)包括相同的金属元素，金属导电部分(9、10)与有源层(4)电连接。该阵列基板可以避免刻蚀液损伤有源层，并且可以优化薄膜晶体管的特性。

Description

阵列基板、显示装置、薄膜晶体管及阵列基板的制作方法
本申请要求于2018年5月3日递交的中国专利申请第201810415015.2号的优先权，该中国专利申请的全文以引入的方式并入以作为本申请的一部分。
技术领域
本公开的实施例涉及一种阵列基板、显示装置、薄膜晶体管及阵列基板的制作方法。
背景技术
TFT(Thin Film Transistor，薄膜晶体管)是场效应晶体管的种类之一，主要应用于平板显示装置中。在平板显示装置中，薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，简称TFT-LCD)在当前的平板显示器市场占据了主导地位。在TFT-LCD的生产工艺中，阵列工序主要是用来制作TFT基板及彩色滤光片。
发明内容
本公开至少一个实施例提供一种阵列基板，包括：衬底基板、有源层和覆盖层；其中，所述有源层位于所述衬底基板上，所述覆盖层位于所述有源层远离所述衬底基板一侧且覆盖所述阵列基板，所述覆盖层包括金属导电部分和透明绝缘金属氧化物部分，所述金属导电部分和所述透明绝缘金属氧化物部分包括相同的金属元素，所述金属导电部分与所述有源层电连接。
例如，在本公开一实施例提供的阵列基板中，所述金属导电部分包括第一电极和第二电极，所述第一电极和所述第二电极相对设置且分别与所述有源层电连接。
例如，在本公开一实施例提供的阵列基板中，所述金属导电部分还包括数据线，所述第一电极为源极，所述第二电极为漏极，所述数据线与所述源极电连接。
例如，本公开一实施例提供的阵列基板还包括栅极、栅线和栅极绝缘层，其中，所述栅极位于所述衬底基板上，且与所述栅线电连接，所述栅极绝缘层 位于所述栅极和所述栅线远离所述衬底基板一侧，所述有源层位于所述栅极绝缘层远离所述栅极一侧。
例如，在本公开一实施例提供的阵列基板中，所述覆盖层的金属导电部分包括Hf，所述覆盖层的透明绝缘金属氧化物部分包括HfO 2。
例如，在本公开一实施例提供的阵列基板中，所述覆盖层的金属导电部分包括Ta，所述覆盖层的透明绝缘金属氧化物部分包括Ta 2O 5。
例如，在本公开一实施例提供的阵列基板中，所述有源层的材质包括金属氧化物半导体，所述金属氧化物半导体包括氧化铟镓锌、氧化锌或氮氧化锌。
例如，本公开一实施例提供的阵列基板还包括：钝化层，其中，所述钝化层位于所述覆盖层远离所述有源层一侧。
本公开至少一个实施例还提供一种显示装置，包括本公开任一实施例所述的阵列基板。
本公开至少一个实施例还提供一种阵列基板的制作方法，包括：在衬底基板上形成有源层；以及在所述有源层远离所述衬底基板一侧形成覆盖所述阵列基板的覆盖层，其中，所述覆盖层包括金属导电部分和透明绝缘金属氧化物部分，所述金属导电部分和所述透明绝缘金属氧化物部分包括相同的金属元素，所述金属导电部分与所述有源层电连接。
例如，在本公开一实施例提供的阵列基板的制作方法中，所述金属导电部分包括第一电极和第二电极，所述第一电极和所述第二电极相对设置且分别与所述有源层电连接，所述在所述有源层远离所述衬底基板一侧形成覆盖所述阵列基板的所述覆盖层，包括：在所述有源层远离所述衬底基板一侧形成覆盖所述阵列基板的金属层；在所述金属层远离所述有源层一侧形成对应所述第一电极区域和所述第二电极区域的遮挡层；对所述阵列基板进行处理，使所述金属层未被所述遮挡层遮挡的区域转化为透明绝缘金属氧化物；以及剥离所述遮挡层。
例如，在本公开一实施例提供的阵列基板的制作方法中，所述金属导电部分还包括数据线，所述第一电极为源极，所述第二电极为漏极，所述数据线与所述源极电连接，所述在所述有源层远离所述衬底基板一侧形成覆盖所述阵列基板的所述覆盖层，还包括：在所述金属层远离所述有源层一侧形成对应所述数据线区域的遮挡层。
例如，在本公开一实施例提供的阵列基板的制作方法中，所述对所述阵列 基板进行处理，使所述金属层未被所述遮挡层遮挡的区域转化为透明绝缘金属氧化物，包括：对所述阵列基板进行氧等离子体轰击处理，使所述金属层未被所述遮挡层遮挡的区域氧化为所述透明绝缘金属氧化物。
例如，在本公开一实施例提供的阵列基板的制作方法中，所述遮挡层为光刻胶层。
例如，在本公开一实施例提供的阵列基板的制作方法中，所述金属层的材质包括Hf，所述透明绝缘金属氧化物包括HfO 2；或所述金属层的材质包括Ta，所述透明绝缘金属氧化物包括Ta 2O 5。
例如，在本公开一实施例提供的阵列基板的制作方法中，所述有源层的材质包括金属氧化物半导体，所述金属氧化物半导体包括氧化铟镓锌、氧化锌或氮氧化锌。
例如，本公开一实施例提供的阵列基板的制作方法还包括：在所述衬底基板上形成栅极以及与所述栅极电连接的栅线，以及在所述栅极和所述栅线远离所述衬底基板一侧形成栅极绝缘层；其中，所述有源层形成在所述栅极绝缘层远离所述栅极一侧。
例如，本公开一实施例提供的阵列基板的制作方法还包括：在所述覆盖层远离所述有源层一侧形成钝化层。
本公开至少一个实施例还提供一种薄膜晶体管，包括：有源层、金属导电部分和透明绝缘金属氧化物部分；其中，所述金属导电部分和所述透明绝缘金属氧化物部分包括相同的金属元素，所述金属导电部分包括第一电极和第二电极，所述第一电极和所述第二电极相对设置且分别与所述有源层电连接。
例如，在本公开一实施例提供的薄膜晶体管中，所述金属导电部分包括Hf，所述透明绝缘金属氧化物部分包括HfO 2；或所述金属导电部分包括Ta，所述透明绝缘金属氧化物部分包括Ta 2O 5。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开至少一个实施例提供的一种阵列基板制作中对阵列基板进行氧等离子体轰击处理的示意图；
图2为本公开至少一个实施例提供的一种阵列基板的示意图；
图3为本公开至少一个实施例提供的另一种阵列基板的示意图；
图4为本公开至少一个实施例提供的一种阵列基板的像素单元的平面结构示意图；
图5为本公开至少一个实施例提供的一种阵列基板的制作方法的流程图；以及
图6为本公开至少一个实施例提供的一种阵列基板的覆盖层的制作方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
阵列基板制作工艺的主要工序为：玻璃基板清洗→镀膜→清洗→光刻胶涂附→曝光→显影→刻蚀→光刻胶剥离→清洗→检查。镀膜分金属膜和非金属膜，金属膜采用物理气相淀积的方式成膜，又叫溅射；非金属膜采用化学气相淀积法成膜。光刻胶涂附指将光刻胶均匀涂附到玻璃基板表面的工序。曝光就是要将掩模板上的图形转移到涂附好光刻胶的玻璃基板上，精度要求极高。光刻胶有正胶、负胶，显影就是将正胶曝光后感光部分的光刻胶溶解并去除，留下未感光部分的光刻胶，从而形成图形，或是将负胶曝光后感光部分的光刻胶 留下，溶解并去除未感光部分的光刻胶，从而形成图形。经过显影留下来的光刻胶成了保护掩模板，未被保护的薄膜将通过刻蚀工艺去除。光刻胶的剥离是指在刻蚀工艺完成后将光刻胶去除。
在阵列基板的制作工艺中，有刻蚀这一工序，而在薄膜晶体管(TFT)的刻蚀工艺中，背沟道刻蚀由于制程简单经常被采用。目前TFT的制作大都采用具有高载流子迁移率的IGZO(Indium Gallium Zinc Oxide，氧化铟镓锌)做有源层。但是当用IGZO做有源层时，若采用背沟道刻蚀形成源极和漏极，刻蚀液会不可避免地对已形成的IGZO有源层造成损伤，从而严重影响到TFT的特性。
本公开至少一实施例提供了一种阵列基板、显示装置、薄膜晶体管及阵列基板的制作方法。该阵列基板可以避免刻蚀液损伤有源层，并且可以显著地优化TFT的特性。
下面，将参考附图详细地说明本公开的实施例。应当注意的是，不同的附图中相同的附图标记将用于指代已描述的相同的元件。
本公开至少一个实施例提供一种阵列基板，包括衬底基板、有源层和覆盖层。有源层位于衬底基板上，覆盖层位于有源层远离衬底基板的一侧且覆盖阵列基板。覆盖层包括金属导电部分和透明绝缘金属氧化物部分，该金属导电部分和该透明绝缘金属氧化物部分包括相同的金属元素，金属导电部分与有源层电连接。
图2为本公开至少一个实施例提供的一种阵列基板的示意图。如图2所示，本公开一些实施例提供的阵列基板，包括：衬底基板1；位于衬底基板1之上的栅极2以及与栅极2电连接的栅线(未示出)；位于栅极2和栅线远离衬底基板1一侧的栅极绝缘层3；位于栅极绝缘层3远离栅极2一侧的有源层4；以及位于有源层4远离栅极绝缘层3一侧(即远离衬底基板1一侧)且覆盖阵列基板的覆盖层5。该覆盖层5包括金属导电部分和透明绝缘金属氧化物部分11，该金属导电部分和该透明绝缘金属氧化物部分11的金属元素相同。金属导电部分包括相对设置且分别与有源层4电连接的第一电极9(例如源极)和第二电极10(例如漏极)。
例如，在本公开的一些实施例中，该金属导电部分还可以包括例如数据线。在第一电极9为源极，且第二电极10为漏极的情形，该数据线与源极9(即第一电极)电连接。
需要说明的是，在本实施例中，第一电极9为源极，第二电极10为漏极， 而在本公开的其他一些实施例中，还可以第一电极9为漏极，第二电极10为源极，本公开的实施例对此不作限制。
例如，该金属导电部分还可以包括传输其他电信号的信号线，该信号线可以与第一电极9电连接，或者还可以与第二电极10电连接，连接方式可以为直接连接或者通过例如过孔结构等连接，本公开的实施例对此不作限制。
例如，在本公开的其他一些实施例中，数据线或传输其他电信号的信号线还可以采用其他材料或其他工艺另外制备，即该金属导电部分也可以不包括例如数据线等信号线，本公开的实施例对此不作限制。
在本公开的一些实施例中，衬底基板1的具体材质不作限制，例如可以采用玻璃、树脂或塑料等，例如衬底基板1可以为透明的玻璃基板或透明的塑料基板。
例如，覆盖层5的金属导电部分(例如第一电极9和第二电极10)和透明绝缘金属氧化物部分11包括相同的金属元素，因此该金属导电部分和透明绝缘金属氧化物部分11例如可以通过形成包括该相同金属元素的金属层并对该金属层进行例如氧等离子体轰击处理的方法得到，进而省去了阵列基板制作过程中的刻蚀工艺，避免了湿刻制程中刻蚀液对有源层4造成损伤，使TFT的特性得到了显著地优化。
图1为本公开至少一个实施例提供的一种阵列基板制作中对阵列基板进行氧等离子体轰击处理的示意图。例如，结合图1和图2所示，在本公开的一些实施例中，覆盖层5的形成过程可以包括：在有源层4远离衬底基板1的一侧形成覆盖阵列基板的金属层6；在金属层6远离有源层4的一侧形成对应第一电极9区域(例如源极)和第二电极10区域(例如漏极)的遮挡层7；对阵列基板进行氧等离子体轰击处理，使金属层6未被遮挡层7遮挡的区域转化为透明绝缘金属氧化物，即透明绝缘金属氧化物部分11；以及剥离遮挡层7。
例如，在如图2所示的阵列基板的金属导电部分包括数据线的情形，覆盖层5的形成过程还包括：在金属层6远离有源层4的一侧形成对应数据线区域的遮挡层7。
在本公开的一些实施例中，金属层6的材质，即金属导电部分的材质，例如可以为铪(Hf)，透明绝缘金属氧化物部分11的材质为HfO 2；或者例如金属层6的材质为钽(Ta)，透明绝缘金属氧化物部分11的材质为Ta 2O 5。例如，金属层6的材质还可以为Hf和Ta的混合物，相应地，透明绝缘金属氧化物部 分11的材质为HfO 2和Ta 2O 5的混合物。例如，金属层6的材质还可以为其他金属元素，透明绝缘金属氧化物部分11的材质为相应地该金属元素的氧化物或其他类型的化合物，本公开的实施例对此不作限制。
例如，金属Hf具有优异的导电性能，在常温下非常稳定，而在高温时Hf可以被氧化生成透明金属氧化物HfO 2。HfO 2是一种具有宽带隙和高介电常数的陶瓷材料，可以很好地替代例如氧化硅等绝缘材料，因此在对阵列基板的金属层6曝光显影后，金属层6中未被遮挡层7保护的Hf转化成HfO 2，进而实现构图工艺。因而，本公开的实施例提供的阵列基板可以避免湿刻制程中蚀刻液对有源层造成损伤，进而使TFT的特性得到显著地优化，提高包括该阵列基板的产品的良率。
例如，遮挡层7可以为光刻胶层，例如可以为光聚合型光刻胶层、光分解型光刻胶层或光交联型光刻胶层等。例如，遮挡层7还可以采用其他类型的材料，本公开的实施例对此不作限制。
在本公开的一些实施例中，有源层4可以采用半导体材料形成，例如有源层4的材质可以为非晶硅、微晶硅、多晶硅、氧化物半导体(例如金属氧化物半导体)等。该金属氧化物半导体包括氧化铟镓锌(IGZO)、氧化锌(ZnO)或氮氧化锌(ZnON)等，这类金属氧化物半导体具有高载流子迁移率，能够满足大尺寸显示装置的驱动需要，因而被广泛地应用于TFT的制作中。例如，有源层4与第一电极9、第二电极10接触的区域可以通过等离子体处理和高温处理的工序被导体化，从而能够更好地实现电信号的传输。
例如，栅极2和栅线的材料可以为铜基金属，例如，铜(Cu)、铜钼合金(Cu/Mo)、铜钛合金(Cu/Ti)、铜钼钛合金(Cu/Mo/Ti)、铜钼钨合金(Cu/Mo/W)、铜钼铌合金(Cu/Mo/Nb)等；也可以为铬基金属，例如，铬钼合金(Cr/Mo)、铬钛合金(Cr/Ti)、铬钼钛合金(Cr/Mo/Ti)等或者其他适合的材料。
例如，被用作栅极绝缘层3的材料可以为氮化硅(SiNx)、氧化硅(SiOx)、氧化铝(Al 2O 3)、氮化铝(AlN)或其他适合的材料。
图3为本公开至少一个实施例提供的另一种阵列基板的示意图。如图3所示，本公开一些实施例提供的阵列基板还包括位于覆盖层5远离有源层4一侧的钝化层8。该钝化层8的材质可选用有机绝缘材料(例如，丙烯酸类树脂)或者无机绝缘材料(例如，氮化硅或者氧化硅)等。例如，该钝化层8可以为由氮化硅或者氧化硅构成的单层结构，或者由氮化硅和氧化硅构成的双层结 构，本公开的实施例对此不作限制。
例如，由于第一电极9和第二电极10所在的金属层6不需要通过刻蚀工艺形成，而可以通过例如沉积(例如溅射沉积)等方式形成，因此该金属层6可以呈整面分布，使第一电极9及第二电极10与钝化层8之间的断差有效降低，进而使包括该阵列基板的产品的良率显著提高。
需要说明的是，在本公开的一些实施例中，阵列基板以采用底栅型结构为例进行说明，即栅极以及与栅极电连接的栅线均设置在有源层靠近衬底基板的一侧。在本公开的其他一些实施例中，阵列基板还可以采用其他类型的结构，本公开的实施例对此不作限制。
例如，在本公开的实施例提供的阵列基板应用于例如具有显示功能的器件的情形，该阵列基板上还可以设置呈阵列排布的多个像素单元。
图4为本公开至少一个实施例提供的一种阵列基板的像素单元的平面结构示意图。如图4所示，多个像素单元20设置在阵列基板上由多条数据线DL和多条栅线GL交叉限定的区域内。例如，每个像素单元20包括开关晶体管，该开关晶体管包括栅极2、第一电极9(例如源极)和第二电极10(例如漏极)，开关晶体管的栅极2和栅线GL电连接，开关晶体管的第一电极9和数据线DL电连接，开关晶体管的第二电极10和像素单元20中的其他器件例如驱动晶体管电连接。
本公开至少一个实施例还提供一种显示装置，包括本公开任一实施例所述的阵列基板。由于阵列基板中的TFT的性能较佳，因此，该显示装置具有较佳的产品品质。该显示装置的技术效果以及实现原理与本公开实施例所述的阵列基板相同，在此不再赘述。该显示装置的具体类型不限，例如，可以为TFT-LCD显示装置、AMOLED显示装置等等；该显示装置的具体产品类型不限，例如，可以为电子纸、手机、显示器、显示屏、平板电视、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开至少一个实施例还提供一种阵列基板的制作方法，包括：在衬底基板上形成有源层；以及在有源层远离衬底基板一侧形成覆盖阵列基板的覆盖层。该覆盖层包括金属导电部分和透明绝缘金属氧化物部分，该金属导电部分和该透明绝缘金属氧化物部分包括相同的金属元素，该金属导电部分与有源层电连接。
下面以图2中所示的阵列基板为例，对该阵列基板的制作方法进行说明。
图5为本公开至少一个实施例提供的一种阵列基板的制作方法的流程图。结合图2和图5所示，本公开一些实施例提供的一种阵列基板的制作方法，包括以下步骤：
步骤S1：在衬底基板1上形成栅极2以及与栅极2电连接的栅线；
步骤S2：在栅极2和栅线远离衬底基板1一侧形成栅极绝缘层3；
步骤S3：在栅极绝缘层3远离栅极2一侧形成有源层4；以及
步骤S4：在有源层4远离栅极绝缘层3一侧(即远离衬底基板1一侧)形成覆盖阵列基板的覆盖层5。
该覆盖层5包括金属导电部分和透明绝缘金属氧化物部分11，该金属导电部分和透明绝缘金属氧化物部分11的金属元素相同。该金属导电部分包括相对设置且分别与有源层4电连接的源极(即第一电极9)和漏极(即第二电极10)，以及与源极9电连接的数据线。
例如，在步骤S1和步骤S2中，栅极2和栅极绝缘层3可以采用同一个构图工艺被构图。例如，栅极绝缘层3可以为无机绝缘层或有机绝缘层，且可以通过物理气相沉积、化学气相沉积、或涂覆等方法形成。
例如，在步骤S3中，该有源层4可以为非晶硅、多晶硅、氧化物半导体等，并通过例如光刻工艺被构图。
图6为本公开至少一个实施例提供的一种阵列基板的覆盖层的制作方法的流程图。结合图1、图2和图6所示，本公开一些实施例提供的一种阵列基板的制作方法，在有源层4远离栅极绝缘层3一侧形成覆盖阵列基板的覆盖层5的制作，包括以下步骤：
步骤S401：在有源层4远离栅极绝缘层3一侧(即远离衬底基板1一侧)形成覆盖阵列基板的金属层6；
步骤S402：在金属层6远离有源层4一侧形成对应源极(即第一电极9)、漏极(即第二电极10)和数据线区域的遮挡层7；
步骤S403：对阵列基板进行氧等离子体轰击处理，使金属层6未被遮挡层7遮挡的区域氧化为透明绝缘金属氧化物(即透明绝缘金属氧化物部分11)；以及
步骤S404：剥离遮挡层7。
例如，在步骤S403中，可以通过对阵列基板进行氧等离子体轰击处理，将金属层6未被遮挡层7遮挡的区域氧化为透明绝缘金属氧化物，而在本公开 的其他一些实施例中，还可以通过其他处理方式将金属层6未被遮挡层7遮挡的区域转化为透明绝缘金属氧化物，本公开的实施例对此不作限制。
采用本实施例中提供的方法制作的阵列基板，在金属层远离有源层一侧形成覆盖对应源极、漏极和数据线区域的遮挡层后，对阵列基板进行氧等离子体轰击处理，使未被遮挡层遮挡的金属层被氧化成透明绝缘的金属氧化物，进而在对阵列基板进行剥离遮挡层处理后，使阵列基板形成了对应源极、漏极和数据线区域的图案。这种构图工艺避免了通过刻蚀工艺对有源层造成的损伤，并且优化了TFT的特性，提高了包括该阵列基板的显示装置的产品品质。
例如，遮挡层7可以为光刻胶层。
例如，在本公开的其他一些实施例中，例如在金属导电部分不包括数据线的情形，数据线还可以通过其他的材料或工艺方法另外提供，即数据线可以不通过上述制作方法形成，本公开的实施例对此不作限制。
例如，结合图3所示的阵列基板，本公开一些实施例提供的阵列基板的制作方法还可以包括：在覆盖层5远离有源层4一侧形成钝化层8。
例如，该钝化层8的材质可选用氮化硅或氧化硅等。例如，可以通过物理气相沉积、化学气相沉积、或涂覆等方法形成钝化层8。
例如，在通过本公开实施例提供的方法制作的阵列基板中，阵列基板的金属层6的材质可以为Hf，透明绝缘金属氧化物(即透明绝缘金属氧化物部分11的材质)为HfO 2；或者金属层6的材质可以为Ta，透明绝缘金属氧化物(即透明绝缘金属氧化物部分11的材质)为Ta 2O 5。
例如，金属层6的材质还可以为Hf和Ta的混合物，相应地，透明绝缘金属氧化物部分11的材质为HfO 2和Ta 2O 5的混合物。例如，金属层6的材质还可以为其他金属元素，透明绝缘金属氧化物部分11的材质为相应地该金属元素的氧化物或其他类型的化合物，本公开的实施例对此不作限制。
例如，在通过本公开实施例提供的方法制作的阵列基板中，有源层4的材质可以为金属氧化物半导体。该金属氧化物半导体包括氧化铟镓锌(IGZO)、氧化锌(ZnO)或氮氧化锌(ZnON)等，这类金属氧化物半导体因具有高载流子迁移率，而被广泛地应用于TFT的制作中。
本公开至少一个实施例还提供一种薄膜晶体管，包括：有源层、金属导电部分和透明绝缘金属氧化物部分。该金属导电部分和该透明绝缘金属氧化物部分包括相同的金属元素，该金属导电部分包括第一电极和第二电极，第一电极 和第二电极相对设置且分别与有源层电连接。
例如，在本公开的一些实施例中，该金属导电部分包括Hf，该透明绝缘金属氧化物部分包括HfO 2。
例如，在本公开的一些实施例中，该金属导电部分包括Ta，该透明绝缘金属氧化物部分包括Ta 2O 5。
例如，在本公开的一些实施例中，该薄膜晶体管还包括栅极，该栅极与有源层绝缘且与该有源层对应。
本公开至少一实施例的薄膜晶体管可以用于阵列基板，以作为像素单元中的开关元件，也可以用于其他电子装置作为例如开关元件或驱动元件，例如用于栅极驱动电路(例如GOA(Gate on Array-substrate)电路)，本公开的实施例对此不作限制。该薄膜晶体管的技术效果以及实现原理与本公开至少一实施例所述的阵列基板相同，在此不再赘述。
有以下几点需要说明：
(1)本公开实施例附图只涉及到本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种阵列基板，包括：衬底基板、有源层和覆盖层；
    其中，所述有源层位于所述衬底基板上，所述覆盖层位于所述有源层远离所述衬底基板一侧且覆盖所述阵列基板，
    所述覆盖层包括金属导电部分和透明绝缘金属氧化物部分，所述金属导电部分和所述透明绝缘金属氧化物部分包括相同的金属元素，
    所述金属导电部分与所述有源层电连接。
  2. 根据权利要求1所述的阵列基板，其中，所述金属导电部分包括第一电极和第二电极，
    所述第一电极和所述第二电极相对设置且分别与所述有源层电连接。
  3. 根据权利要求2所述的阵列基板，其中，所述金属导电部分还包括数据线，
    所述第一电极为源极，所述第二电极为漏极，所述数据线与所述源极电连接。
  4. 根据权利要求1-3任一所述的阵列基板，还包括栅极、栅线和栅极绝缘层，
    其中，所述栅极位于所述衬底基板上，且与所述栅线电连接，
    所述栅极绝缘层位于所述栅极和所述栅线远离所述衬底基板一侧，
    所述有源层位于所述栅极绝缘层远离所述栅极一侧。
  5. 根据权利要求1-4任一所述的阵列基板，其中，所述覆盖层的金属导电部分包括Hf，所述覆盖层的透明绝缘金属氧化物部分包括HfO 2。
  6. 根据权利要求1-4任一所述的阵列基板，其中，所述覆盖层的金属导电部分包括Ta，所述覆盖层的透明绝缘金属氧化物部分包括Ta 2O 5。
  7. 根据权利要求1-6任一所述的阵列基板，其中，所述有源层的材质包括金属氧化物半导体，
    所述金属氧化物半导体包括氧化铟镓锌、氧化锌或氮氧化锌。
  8. 根据权利要求1-7任一所述的阵列基板，还包括：钝化层，
    其中，所述钝化层位于所述覆盖层远离所述有源层一侧。
  9. 一种显示装置，包括如权利要求1-8任一所述的阵列基板。
  10. 一种阵列基板的制作方法，包括：
    在衬底基板上形成有源层；以及
    在所述有源层远离所述衬底基板一侧形成覆盖所述阵列基板的覆盖层，
    其中，所述覆盖层包括金属导电部分和透明绝缘金属氧化物部分，所述金属导电部分和所述透明绝缘金属氧化物部分包括相同的金属元素，所述金属导电部分与所述有源层电连接。
  11. 根据权利要求10所述的阵列基板的制作方法，其中，所述金属导电部分包括第一电极和第二电极，所述第一电极和所述第二电极相对设置且分别与所述有源层电连接，
    所述在所述有源层远离所述衬底基板一侧形成覆盖所述阵列基板的所述覆盖层，包括：
    在所述有源层远离所述衬底基板一侧形成覆盖所述阵列基板的金属层；
    在所述金属层远离所述有源层一侧形成对应所述第一电极区域和所述第二电极区域的遮挡层；
    对所述阵列基板进行处理，使所述金属层未被所述遮挡层遮挡的区域转化为透明绝缘金属氧化物；以及
    剥离所述遮挡层。
  12. 根据权利要求11所述的阵列基板的制作方法，其中，所述金属导电部分还包括数据线，
    所述第一电极为源极，所述第二电极为漏极，所述数据线与所述源极电连接，
    所述在所述有源层远离所述衬底基板一侧形成覆盖所述阵列基板的所述覆盖层，还包括：
    在所述金属层远离所述有源层一侧形成对应所述数据线区域的遮挡层。
  13. 根据权利要求11或12所述的阵列基板的制作方法，其中，所述对所述阵列基板进行处理，使所述金属层未被所述遮挡层遮挡的区域转化为透明绝缘金属氧化物，包括：
    对所述阵列基板进行氧等离子体轰击处理，使所述金属层未被所述遮挡层遮挡的区域氧化为所述透明绝缘金属氧化物。
  14. 根据权利要求11-13任一所述的阵列基板的制作方法，其中，所述遮挡层为光刻胶层。
  15. 根据权利要求11-14任一所述的阵列基板的制作方法，其中，所述金 属层的材质包括Hf，所述透明绝缘金属氧化物包括HfO 2；或
    所述金属层的材质包括Ta，所述透明绝缘金属氧化物包括Ta 2O 5。
  16. 根据权利要求10-15任一所述的阵列基板的制作方法，其中，所述有源层的材质包括金属氧化物半导体，
    所述金属氧化物半导体包括氧化铟镓锌、氧化锌或氮氧化锌。
  17. 根据权利要求10-16任一所述的阵列基板的制作方法，还包括：
    在所述衬底基板上形成栅极以及与所述栅极电连接的栅线，以及
    在所述栅极和所述栅线远离所述衬底基板一侧形成栅极绝缘层；
    其中，所述有源层形成在所述栅极绝缘层远离所述栅极一侧。
  18. 根据权利要求10-17任一所述的阵列基板的制作方法，还包括：
    在所述覆盖层远离所述有源层一侧形成钝化层。
  19. 一种薄膜晶体管，包括：有源层、金属导电部分和透明绝缘金属氧化物部分；
    其中，所述金属导电部分和所述透明绝缘金属氧化物部分包括相同的金属元素，
    所述金属导电部分包括第一电极和第二电极，所述第一电极和所述第二电极相对设置且分别与所述有源层电连接。
  20. 根据权利要求19所述的薄膜晶体管，其中，所述金属导电部分包括Hf，所述透明绝缘金属氧化物部分包括HfO 2；或
    所述金属导电部分包括Ta，所述透明绝缘金属氧化物部分包括Ta 2O 5。
PCT/CN2019/083096 2018-05-03 2019-04-17 阵列基板、显示装置、薄膜晶体管及阵列基板的制作方法 Ceased WO2019210776A1 (zh)

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