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WO2019135743A1 - Couche de filtre pour un empilement antiferromagnétique synthétique supérieur dans le plan (saf) pour une mémoire à couplage spin-orbite (sot) - Google Patents

Couche de filtre pour un empilement antiferromagnétique synthétique supérieur dans le plan (saf) pour une mémoire à couplage spin-orbite (sot) Download PDF

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Publication number
WO2019135743A1
WO2019135743A1 PCT/US2018/012240 US2018012240W WO2019135743A1 WO 2019135743 A1 WO2019135743 A1 WO 2019135743A1 US 2018012240 W US2018012240 W US 2018012240W WO 2019135743 A1 WO2019135743 A1 WO 2019135743A1
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Prior art keywords
fixed magnet
memory device
multilayer
barrier
filter
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English (en)
Inventor
Kaan OGUZ
Kevin P. O'brien
Mark Doczy
Charles C. Kuo
Gary Allen
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Intel Corp
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Intel Corp
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Priority to PCT/US2018/012240 priority Critical patent/WO2019135743A1/fr
Publication of WO2019135743A1 publication Critical patent/WO2019135743A1/fr
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/18—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using Hall-effect devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H10N50/85—Materials of the active region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors

Definitions

  • Embodiments of the disclosure are in the field of integrated circuit structures and, in particular, a filter layer for an in-plane top SAF stack for a SOT memory.
  • shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased functionality.
  • the drive for ever-more functionality, however, is not without issue.
  • the necessity to optimize the performance of each device becomes increasingly significant.
  • Non-volatile embedded memory e.g., on-chip embedded memory with non-volatility can enable energy and computational efficiency.
  • leading embedded memory options such as spin torque transfer magnetoresistive random access memory (STT-MRAM) can suffer from high voltage and high current-density problems during the programming (writing) of the cell.
  • the density limitations of STT-MRAM may be due to large write switching current and select transistor requirements.
  • traditional STT-MRAM has a cell size limitation due to the drive transistor requirement to provide sufficient spin current.
  • such memory is associated with large write current (>100 mA) and voltage (>0.7 V) requirements of conventional magnetic tunnel junction (MTJ) based devices.
  • MTJ magnetic tunnel junction
  • FIG. 1 A illustrates a typical material stack for a SOT (spin orbit torque) based MTJ (Magnetic Tunnel Junction) MRAM having a top synthetic anti-Ferro-magnet (SAF) stack with in-plane anisotropy, according to one embodiment.
  • SOT spin orbit torque
  • MTJ Magnetic Tunnel Junction
  • SAF synthetic anti-Ferro-magnet
  • FIG. 1B is a top view of the device of FIG. 1A.
  • FIG. 1C is a cross-section of the SOT layer that shows direction of spin currents and charge currents as decided by SOT in metals.
  • FIG. 2 illustrates a material stack for a SOT MTJ memory device having a top SAF stack with in-plane anisotropy and a multilayer barrier filter in accordance with a first embodiment.
  • FIG. 3 illustrates a material stack for a SOT MTJ memory device having a top SAF stack with in-plane anisotropy and a multilayer barrier filter in accordance with a second embodiment.
  • FIG. 4 illustrates a material stack for a SOT MTJ memory device having a top SAF stack with in-plane anisotropy and a multilayer barrier filter in accordance with a third embodiment.
  • FIG. 5 illustrates a material stack for a SOT MTJ memory device having a top SAF stack with in-plane anisotropy and a multilayer barrier filter in accordance with a fourth embodiment.
  • FIG. 6 is a flow diagram representing various operations in a method of fabricating a SOT MTJ memory device with a multilayer barrier filter in accordance with the embodiments disclosed herein.
  • FIGS. 7A and 7B illustrate a wafer composed of semiconductor material and that includes one or more dies having integrated circuit (IC) structures formed on a surface of the wafer.
  • IC integrated circuit
  • FIG. 8 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more embedded non-volatile memory structures having a SOT MTJ memory device with a multilayer barrier filter.
  • IC integrated circuit
  • FIG. 9 illustrates a computing device in accordance with one implementation of the disclosure.
  • Embodiments for a filter layer for an in-plane top SAF stack for a SOT memory are described.
  • numerous specific details are set forth, such as specific material and tooling regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well- known features, such as single or dual damascene processing, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure.
  • the various embodiments shown in the FIGS are illustrative representations and are not necessarily drawn to scale.
  • Embodiments described herein may be directed to front-end-of-line (FEOL)
  • FOL front-end-of-line
  • FEOL is the first portion of integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are paterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).
  • IC integrated circuit
  • Embodiments described herein may be directed to back end of line (BEOL)
  • BEOL is the second portion of IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., the metallization layer or layers.
  • BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections.
  • contacts pads
  • interconnect wires vias and dielectric structures are formed.
  • more than 10 metal layers may be added in the BEOL.
  • Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures.
  • an exemplary processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be applicable to BEOL processing.
  • an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be applicable to FEOL processing.
  • One or embodiments of the present invention is directed to one or more filter layers for an in-plane top SAF MJT stack for a Spin Orbit Torque (SOT) MRAM.
  • SOT Spin Orbit Torque
  • General applications of such an array include, but are not limited to, embedded memory, magnetic tunnel junction architectures, MRAM, non-volatile memory, spin hall effects, spin torque memory, and embedded memory using magnetic memory devices.
  • MTJ based SOT MRAM utilizing the disclosed filter layers reduces diffusion of elements in the SAF stack.
  • a memory device comprises an interconnect having a spin orbit torque (SOT) material.
  • a magnetic tunnel junction (MTJ) device comprises a free layer magnet coupled to the interconnect, a reference fixed magnet, and a barrier material between the free layer magnet and the reference fixed magnet.
  • a material stack is on the MTJ device, wherein the material stack comprises a spacer material, a pinned fixed magnet, and an antiferromagnent.
  • a multilayer filter is located within the material stack, wherein the multilayer filter is configured to reduce effects of diffusion of an element, such as manganese, from the antiferromagnet.
  • FIG. 1 A illustrates a typical material stack for a SOT (spin orbit torque) based MTJ (Magnetic Tunnel Junction) MRAM having a top synthetic anti-Ferro- magnet (SAF) stack with in-plane anisotropy, according to one embodiment.
  • the MTJ device stack stores data as a resistance state value.
  • the MTJ device stack comprises two independent ferromagnetic layers referred to as a free layer nanomagnet (FM1) and a reference fixed magnet (FM2) that are separated by an insulating tunneling barrier material.
  • the barrier material should be sufficiently thin (e.g., ⁇ 1 nm) such that electrons can tunnel there through.
  • the magnetic field of the fee layer magnet FM1 is free to rotate based on a direction of a current, i.e., the spin of the electrons, flowing through the MTJ device stack.
  • the reference fixed magnet FM2 has a fixed magnetization, and is therefore referred to as a fixed or reference layer.
  • the“free” layer magnetic layer is a magnetic layer storing a computational variable.
  • A“fixed” magnetic layer is a magnetic layer with fixed magnetization (magnetically harder than the free magnetic layer).
  • a barrier material such as a tunneling dielectric or oxide layer (e.g., MgO), is one located between free and fixed magnetic layers.
  • the free layer and the fixed layer may be ferromagnetic layers.
  • the MTJ functions essentially as a resistor, where the resistance of an electrical path through the MTJ may exist in two resistive states, either“high” or“low,” depending on the direction or orientation of magnetization in the free layer magnet FM1 and in the fixed magnet FM2.
  • a high resistive state exists in the case that the directions of magnetization in the free layer magnet FM1 and the fixed magnet FM2 closest to it are substantially opposed or anti-parallel with one another.
  • a low resistive state exists. It is to be understood that the terms“low” and“high” with regard to the resistive state of the MTJ are relative to one another.
  • the top synthetic antiferromagnet (SAF) stack includes a non-magnetic spacer material (Ruthenium or Iridium) and a pinned fixed magnet (FM3).
  • the material stack further includes and an antiferromagnetic (AFM).
  • the magnetization of the pinned fixed magnet FM3 is fixed through exchange coupling with the antiferromagnetic AFM.
  • the SAF stack allows for cancelling the dipole fields around the free layer FM1.
  • a top electrode completes the material stack.
  • the free layer magnet FM1, the reference fixed magnet FM2, and the pinned fixed magnet FM3 may comprise Co x FeyB z (Cobalt, Iron, Boron), where‘x,’‘y,’ and‘z’ are integers.
  • the barrier material typically comprises an oxide layer such as magnesium oxide (MgO), and the spacer material typically comprises RU (Ruthenium) or IR (Iridium).
  • the antiferromagnet (AFM) is manganese based and may comprise IrMn (iridium manganese) or PtMn (platinum manganese).
  • the free layer magnet FM1 may have a thickness of approximately 2 to 3 nanometers, while the spacer Ru layer may have a thickness of
  • MTJ device approximately .9 nanometers, for example. In other embodiments, other materials may be used to form the MTJ device.
  • the free layer magnet FM1 of the material stack is in direct contact with an SOT interconnect having a write electrode.
  • Both the SOT interconnect and the write electrode may comprises a Giant Spin Hall Effect (GSHE) metal made of b-Tantalum (b-Ta), b-Tungsten (b- W), Pt, Copper (Cu) doped with elements such as Iridum, bisumuth and any of the elements of 3d, 4d, 5d and 4f, 5f periodic groups in the periodic table.
  • the write electrode transitions into a normal high conductivity metal (e.g., Cu) to minimize write electrode resistance.
  • FIG. 1B is a top view of the device of FIG. 1A.
  • the magnet is oriented along the width of the write electrode for appropriate spin injection.
  • the magnetic cell is written by applying a charge current via the write electrode.
  • the direction of the magnetic writing is decided by the direction of the applied charge current.
  • Positive currents (along+y) produce a spin injection current with transport direction (along+z) and spins pointing to (+x) direction.
  • an SOT- MRAM may also be referred to as a Giant Spin Hall Effect (GSPHE) MRAM.
  • GSPHE Giant Spin Hall Effect
  • FIG. 1C is a cross-section 240 of the SOT layer that shows direction of spin currents and charge currents as decided by SOT in metals.
  • the injected spin current in-tum produces spin torque to align the magnet in the +x or -x direction.
  • PSHE the spin hall injection efficiency, which is the ratio of magnitude of transverse spin current to lateral charge current
  • w is the width of the magnet
  • t is the thickness of the GSHE metal electrode
  • Sf is the spin flip length in the GSHE metal
  • OGSHE is the spin hall angle for the GSHE-metal to FM1 interface.
  • the injected spin angular momentum responsible for spin torque can be determined by first solving equation 1.
  • the SOT stack offers several advantages over devices such as a spin transfer torque (STT) MRAM
  • the SOT stack has a problem with manganese diffusion when the stack is annealed above 300 C.
  • Manganese typically starts to defuse at 300 C, and the diffusion becomes problematic in the SOT stack at 350 C. If the SOT stack is to be implemented in a CMOS process, then the SOT stack needs to survive temperatures approaching 400 C. Once the manganese starts to diffuse, the magnetic properties of the material stack from the AFM to the reference layer FM2 starts to deteriorate. Consequently, high annealing temperatures cause the top SAF stack to suffer from low exchange bias between the AFM and the SAF and a reduction in tunnel magnetoresistance (TMR) due to high magnesium diffusion from the AFM. For example, the manganese diffusion may result in a low exchange bias in terms of yield of approximately 500 oersted and low TMR of less than 100%.
  • TMR tunnel magnetoresistance
  • an improved SOT MRAM memory is described below. More specifically, the problem of manganese diffusion is mitigated through the use of a filter layer placed in various locations in the SOT stack of the memory devices comprising the SOT MRAM, as shown in FIG. 2.
  • FIG. 2 illustrates a material stack for a SOT MTJ memory device 200 having a top SAF stack with in-plane anisotropy and a multilayer barrier filter in accordance with a first embodiment.
  • the SOT MTJ memory device 200 comprises an interconnect 202 having a SOT material, and a MTJ device 204 having a free layer magnet FM1 coupled to the interconnect 202, a reference fixed magnet FM2, and a barrier material between the free layer magnet FM1 and the reference fixed magnet FM2.
  • a material stack 206 is on the MTJ device 204.
  • the material stack 202 comprises a spacer material, an antiferromagnet (AFM), and a top electrode, as described above.
  • the pinned fixed magnet FM3 (of FIG. 1A) in the material stack 206 is divided into two halves, a pinned fixed magnet 1 and a pinned fixed magnet 2.
  • the material stack 206 is further provided with a multilayer barrier filter 208 located within the material stack 206 configured to reduce effects of magnesium diffusion from the antiferromagnet during high temperatures.
  • the multilayer barrier filter 208 comprises three layers of material, a diffusion barrier 1, a ferromagnetic cobalt-based alloy on the diffusion barrier 1, and a diffusion barrier 2 on the cobalt-based alloy.
  • the location of the multilayer barrier filter 208 may vary within the material stack 206.
  • the multilayer barrier filter 208 is located between the pinned fixed magnet 1 and the pinned fixed magnet 2, as shown. In this embodiment, the multilayer barrier filter 208 reduces magnesium diffusion, while maintaining a strong coupling between pinned fixed magnets 1 and 2.
  • the original pinned fixed magnet is divided in two in order to reduce the thickness of the pinned fixed magnets 1 and 2.
  • the pinned fixed magnets 1 and 2 may each have a thickness of approximately .5 to 1 nm.
  • the diffusion barrier 1 and diffusion barrier 2 comprise any heavy metal that acts as a barrier to manganese diffusion such as tantalum, tungsten, iridium, and molybdenum.
  • the diffusion barriers 1 and 2 comprise tantalum (Ta) or tantalum oxide (TaO), and may have a thickness of approximately .1 to .5 nm.
  • the ferromagnetic cobalt-based alloy may comprise Co, Co x Fey, or CoxFeyBz (Cobalt, Iron, Boron), where‘x,’‘y,’ and‘z’ are integers.
  • the ferromagnetic cobalt- based alloy may have a thickness of approximately .2 to 3 nm.
  • the ferromagnetic cobalt-based alloy may comprise binary elements of cobalt with any other transition metal, such as cobalt/tungsten, cobalt/palladium, cobalt/tantalum, and cobalt/platinum, and the like, and alloys thereof.
  • the tantalum diffusion barriers 1 and 2 are sufficiently thin so that the pinned fixed magnet 2 magnetically couples to the cobalt-based ferromagnet, and the cobalt- based ferromagnet magnetically couples to the pinned layer 1.
  • the three magnets, the pinned layers 1 and 2 and the cobalt-based ferromagnet, are parallel, while the reference magnet FM2 is antiparallel.
  • the multilayer barrier filter 208 of the present embodiments should enable the MTJ device 204 to handle temperatures up to 400 to 450 C without debilitating magnesium diffusion damage.
  • FIG. 3 illustrates a material stack for a SOT MTJ memory device 300 having a top SAF stack with in-plane anisotropy and a multilayer barrier filter in accordance with a second embodiment, where like components from FIG. 1 have like reference numerals.
  • the SOT MTJ memory device 200 comprises the interconnect 202 having a SOT material, and the MTJ device 204 having a free layer magnet FM1 coupled to the interconnect 202, a reference fixed magnet FM2, and a barrier material between the free layer magnet FM1 and the reference fixed magnet FM2.
  • a material stack 302 is on the MTJ device 204.
  • the material stack 302 comprises a spacer material, a pinned fixed magnet FM3, an antiferromagnet (AFM), and a top electrode, as described above.
  • AFM antiferromagnet
  • the multilayer barrier filter 304 comprises two layers of material, a diffusion barrier and a ferromagnetic cobalt-based alloy on the diffusion barrier, and the multilayer barrier filter 304 is located between the spacer material and the pinned fixed magnet FM3.
  • the multilayer barrier filter 304 drops the first pinned fixed magnet and the first diffusion barrier of the second embodiment, and instead places the ferromagnetic cobalt- based alloy directly on the spacer material.
  • the spacer material comprises ruthenium (RU) or iridium (Ir) and the diffusion barrier comprises tantalum (Ta) or tantalum oxide (TaO).
  • the ferromagnetic cobalt-based alloy has a thickness of approximately .3 to 1 nm.
  • FIG. 4 illustrates a material stack for a SOT MTJ memory device 400 having a top SAF stack with in-plane anisotropy and a multilayer barrier filter in accordance with a third embodiment, where like components from FIG. 1 have like reference numerals.
  • the SOT MTJ memory device 200 comprises the interconnect 202 having a SOT material, and the MTJ device 204 having a free layer magnet FM1 coupled to the interconnect 202, a reference fixed magnet FM2, and a barrier material between the free layer magnet FM1 and the reference fixed magnet FM2.
  • a material stack 402 is on the MTJ device 204 where the material stack 402 comprises a spacer material, a pinned fixed magnet 1 a pinned fixed magnet 2, an antiferromagnet (AFM), and a top electrode.
  • the material stack 402 comprises a spacer material, a pinned fixed magnet 1 a pinned fixed magnet 2, an antiferromagnet (AFM), and a top electrode.
  • AFM antiferromagnet
  • the multilayer barrier filter 404 comprises three layers of material, a diffusion barrier 1, a ferromagnetic cobalt-based alloy on the diffusion barrier 1, and a diffusion barrier 2 on the cobalt-based alloy.
  • the multilayer barrier filter 404 is located further down the material stack 402 between the reference magnet FM2 and the pinned fixed magnet 1 so that the multilayer barrier filter 404 is in closer proximity to the reference magnet FM2.
  • FIG. 5 illustrates a material stack for a SOT MTJ memory device 500 having a top SAF stack with in-plane anisotropy and a multilayer barrier filter in accordance with a fourth embodiment, where like components from FIG. 1 have like reference numerals.
  • the SOT MTJ memory device 200 comprises the interconnect 202 having a SOT material, and the MTJ device 204 having a free layer magnet FM1 coupled to the interconnect 202, a reference fixed magnet FM2, and a barrier material between the free layer magnet FM1 and the reference fixed magnet FM2.
  • a material stack 502 is on the MTJ device 204 where the material stack 302 comprises a spacer material, a split pinned fixed magnet comprising pinned fixed magnet 1 and a pinned fixed magnet 2, an antiferromagnet (AFM), and a top electrode.
  • the material stack 302 comprises a spacer material, a split pinned fixed magnet comprising pinned fixed magnet 1 and a pinned fixed magnet 2, an antiferromagnet (AFM), and a top electrode.
  • the material stack 502 includes more than one barrier filter, and more particularly, the material stack 502 includes double multilayer barrier filters 504 and 506.
  • Each of the multilayer barrier filters 504 and 506 comprise three layers of material, a diffusion barrier 1, a ferromagnetic cobalt-based alloy on the diffusion barrier 1, and a diffusion barrier 2 on the cobalt-based alloy.
  • the first multilayer barrier filter 504 is located in the material stack 502 between the pinned fixed magnet 1 and pinned fixed magnet 2
  • the second multilayer barrier filter 506 is located between the reference magnet FM2 and the spacer material, as shown.
  • the diffusion barriers 1 and 2 comprise tantalum (Ta) or tantalum oxide (TaO), and may have a thickness of approximately .1 to .5 nm.
  • ferromagnetic cobalt-based alloy may have a thickness of approximately .2 to 3 nm.
  • the advantage of the double multilayer barrier filters 504 and 506 is that it may allow the memory device 500 to handle even higher temperatures. Ideally, the use of double multilayer barrier filters 504 and 506 should enable the memory device to handle temperatures up to 400 to 450 C without degrading manganese diffusion.
  • FIG. 6 is a flow diagram representing various operations in a method of fabricating a SOT MTJ memory device having a top SAF stack with in-plane anisotropy and a multilayer barrier filter in accordance with the embodiments disclosed herein.
  • the process may include forming an SOT interconnect with a write electrode in an opening in a dielectric layer (block 500).
  • the SOT interconnect is formed in an opening in the dielectric layer above a substrate.
  • the substrate may include a suitable semiconductor material such as but not limited to, single crystal silicon, poly crystalline silicon and silicon on insulator (SOI).
  • SOI silicon on insulator
  • the substrate may include other semiconductor materials such as germanium, silicon germanium or a suitable group III-N or a group III-V compound.
  • the SOT interconnect is formed in the dielectric layer by a damascene or a dual damascene process that is well known in the art.
  • both the SOT interconnect and the write electrode may comprise a Giant Spin Hall Effect (GSHE) metal made of b-Tantalum (b-Ta), b-Tungsten (b-W), Pt, Copper (Cu) doped with elements such as Iridium, Bismuth and any of the elements of 3d, 4d, 5d and 4f, 5f periodic groups in the periodic table.
  • the SOT interconnect is electrically connected to a circuit element such as an access transistor (not shown).
  • Logic devices such as access transistors may be integrated with memory devices such as a MTJ device to form embedded memory.
  • a MTJ material stack is formed on the SOT interconnect, and a material layer stack having a multilayer barrier filter is formed over the MTJ material stack (block 502).
  • the multilayer barrier filter may be placed in various locations within the material layer stack, as described with reference to FIGS. 2-5.
  • the MTJ material stack and the material layer stack are blanket deposited.
  • the layers of the MTJ stack may be formed by sputter-deposition techniques with deposition rates in the Angstrom-per-second range. The techniques include physical vapor deposition (PVD), specifically planar magnetron sputtering, and ion-beam deposition.
  • the MTJ stack may be subjected to an annealing process performed at a temperature between 300-400 degrees Celsius.
  • layers of the material layer stack may be respectively blanket deposited by an evaporation process, an atomic layer deposition (ALD) process or by chemical vapor deposition (CVD) process.
  • the chemical vapor deposition process is enhanced by plasma techniques such as RF glow discharge (plasma enhanced CVD) to increase the density and uniformity of the film.
  • an uppermost layer of material layer stack may include the top electrode layer that ultimately acts as a hardmask.
  • the deposition process can be configured to control the magnetic properties of the magnetic layers.
  • the direction of the magnetic anisotropy of the ferromagnetic materials can be set during the deposition of the layer by applying a magnetic field across the wafer.
  • the resulting uniaxial anisotropy is observed as magnetic easy and hard directions in the magnetization of the layer. Since the anisotropy axis affects the switching behavior of the material, the deposition system must be capable of projecting a uniform magnetic field across the wafer, typically in the 20-100 Oe range, during deposition.
  • the deposition process can control other magnetic properties, such as coercivity and magnetorestriction, by the choice of magnetic alloy and deposition conditions. Because the switching field of a patterned bit depends directly on the thickness of the free layer magnet, the thickness uniformity and repeatability must meet strict requirements.
  • a lithography step is performed that forms a photoresist mask on an uppermost surface of the material layer stack (block 504).
  • the photoresist mask is formed at a minimum size required for the memory element MTJ material stack, which is self-aligned with the material layer stack, and defines a location where a memory cell will be subsequently formed.
  • example minimum sizes for the resist could be in the range of 10 nm - 100 nm.
  • the material layer stack and the MTJ material stack is then patterned in alignment with the photoresist mask to form an active memory device/cell (block 506).
  • a plasma etch process is utilized to pattern the material layer stack and the MTJ stack down to the SOT interconnect 202.
  • a second dielectric layer is deposited over the memory device and other interconnect lines (e.g. a bit line) are patterned over the second dielectric layer (block 508).
  • the memory cell may be completed by removing the photoresist mask and then forming the second dielectric layer on the bit line and on the active memory device (on the hardmask, on sidewalls of the memory device, resistive element and memory element).
  • the second dielectric letter is planarized to expose an uppermost surface of the top electrode.
  • the bit line is patterned on the uppermost surface of the top electrode and on the uppermost surface of the second dielectric layer to complete formation of the memory cell.
  • the bit line may comprise conductive material such as W, TiN, TaN or Ru.
  • the bit line is formed by using a dual damascene process (not shown) and includes a barrier layer such as Ru, Ta or Ti and a fill metal such as W or Cu.
  • an underlying semiconductor substrate e.g., as FEOL layer(s).
  • the layers and materials described in association with embodiments herein are formed on or above underlying device layer(s) of an integrated circuit, e.g., as BEOL layer(s).
  • an underlying semiconductor substrate represents a general workpiece object used to manufacture integrated circuits.
  • semiconductor substrate often includes a wafer or other piece of silicon or another
  • Suitable semiconductor substrates include, but are not limited to, single crystal silicon, poly crystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials.
  • SOI silicon on insulator
  • the semiconductor substrate depending on the stage of manufacture, often includes transistors, integrated circuitry, and the like.
  • the substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates.
  • structures described herein may be fabricated on underlying lower level back end of line (BEOL) interconnect layers.
  • BEOL back end of line
  • an embedded non-volatile memory structure is formed on a material composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy -nitride, silicon nitride, or carbon-doped silicon nitride.
  • a dielectric material such as, but not limited to, silicon dioxide, silicon oxy -nitride, silicon nitride, or carbon-doped silicon nitride.
  • an embedded non-volatile memory structure is formed on a low-k dielectric layer of an underlying BEOL layer.
  • a wafer 700 may be composed of semiconductor material and may include one or more dies 702 having integrated circuit (IC) structures formed on a surface of the wafer 700.
  • IC integrated circuit
  • Each of the dies 702 may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including one or more embedded non-volatile memory structures having a SOT MTJ memory device with a multilayer barrier filter, such as described above.
  • the wafer 700 may undergo a singulation process in which each of the dies 702 is separated from one another to provide discrete“chips” of the semiconductor product.
  • structures that include embedded non-volatile memory structures having SOT MTJ memory devices with a multilayer barrier filters as disclosed herein may take the form of the wafer 700 (e.g., not singulated) or the form of the die 702 (e.g., singulated).
  • the die 702 may include one or more embedded non volatile memory structures based on a SOT MTJ memory device with a multilayer barrier filter and/or supporting circuitry to route electrical signals, as well as any other IC components.
  • the wafer 700 or the die 702 may include an additional memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element.
  • SRAM static random access memory
  • logic device e.g., an AND, OR, NAND, or NOR gate
  • a memory array formed by multiple memory devices may be formed on a same die 702 as a processing device or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.
  • Embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers, and the like. In other embodiments, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein.
  • FIG. 8 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more embedded non-volatile memory structures having a SOT MTJ memory device with a multilayer barrier filter, in accordance with one or more of the embodiments disclosed herein.
  • IC integrated circuit
  • an IC device assembly 800 includes components having one or more integrated circuit structures described herein.
  • the IC device assembly 800 includes a number of components disposed on a circuit board 802 (which may be, e.g., a motherboard).
  • the IC device assembly 800 includes components disposed on a first face 840 of the circuit board 802 and an opposing second face 842 of the circuit board 802.
  • components may be disposed on one or both faces 840 and 842.
  • any suitable ones of the components of the IC device assembly 800 may include a number of embedded non-volatile memory structures having a SOT MTJ memory device with a multilayer barrier filter, such as disclosed herein.
  • the circuit board 802 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 802.
  • the circuit board 802 may be a non-PCB substrate.
  • the IC device assembly 800 illustrated in FIG. 8 includes a package-on-interposer structure 836 coupled to the first face 840 of the circuit board 802 by coupling components 816.
  • the coupling components 816 may electrically and mechanically couple the package-on- interposer structure 836 to the circuit board 802, and may include solder balls (as shown in FIG. 8), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.
  • the package-on-interposer structure 836 may include an IC package 820 coupled to an interposer 804 by coupling components 818.
  • the coupling components 818 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 816. Although a single IC package 820 is shown in FIG. 8, multiple IC packages may be coupled to the interposer 804. It is to be appreciated that additional interposers may be coupled to the interposer 804.
  • the interposer 804 may provide an intervening substrate used to bridge the circuit board 802 and the IC package 820.
  • the IC package 820 may be or include, for example, a die (the die 702 of FIG. 7B), or any other suitable component.
  • the interposer 804 may spread a connection to a wider pitch or reroute a connection to a different connection.
  • the interposer 804 may couple the IC package 820 (e.g., a die) to a ball grid array (BGA) of the coupling components 816 for coupling to the circuit board 802.
  • BGA ball grid array
  • the IC package 820 and the circuit board 802 are attached to opposing sides of the interposer 804.
  • the IC package 820 and the circuit board 802 may be attached to a same side of the interposer 804.
  • three or more components may be interconnected by way of the interposer 804.
  • the interposer 804 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 804 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.
  • the interposer 804 may include metal interconnects 810 and vias 808, including but not limited to through-silicon vias (TSVs) 806.
  • TSVs through-silicon vias
  • the interposer 804 may further include embedded devices 814, including both passive and active devices.
  • Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 804.
  • RF radio-frequency
  • MEMS microelectromechanical systems
  • the package-on-interposer structure 836 may take the form of any of the package-on-interposer structures known in the art.
  • the IC device assembly 800 may include an IC package 824 coupled to the first face 840 of the circuit board 802 by coupling components 822.
  • the coupling components 822 may take the form of any of the embodiments discussed above with reference to the coupling components 816
  • the IC package 824 may take the form of any of the embodiments discussed above with reference to the IC package 820.
  • the IC device assembly 800 illustrated in FIG. 8 includes a package-on-package structure 834 coupled to the second face 842 of the circuit board 802 by coupling components 828.
  • the package-on-package structure 834 may include an IC package 826 and an IC package 832 coupled together by coupling components 830 such that the IC package 826 is disposed between the circuit board 802 and the IC package 832.
  • the coupling components 828 and 830 may take the form of any of the embodiments of the coupling components 816 discussed above, and the IC packages 826 and 832 may take the form of any of the embodiments of the IC package 820 discussed above.
  • the package-on-package structure 834 may be configured in accordance with any of the package-on-package structures known in the art.
  • FIG. 9 illustrates a computing device 900 in accordance with one implementation of the disclosure.
  • the computing device 900 houses a board 902.
  • the board 902 may include a number of components, including but not limited to a processor 904 and at least one
  • the processor 904 is physically and electrically coupled to the board 902. In some implementations the at least one communication chip 906 is also physically and electrically coupled to the board 902. In further implementations, the communication chip 906 is part of the processor 904.
  • computing device 900 may include other components that may or may not be physically and electrically coupled to the board 902. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., ROM
  • flash memory e.g., a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna,
  • the communication chip 906 enables wireless communications for the transfer of data to and from the computing device 900.
  • the term“wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 906 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 900 may include a plurality of communication chips 906.
  • a first communication chip 906 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 906 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 904 of the computing device 900 includes an integrated circuit die packaged within the processor 904.
  • the integrated circuit die of the processor includes one or more embedded non-volatile memory structures having a SOT MTJ memory device with a multilayer barrier filter, in accordance with implementations of embodiments of the disclosure.
  • the term“processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communication chip 906 also includes an integrated circuit die packaged within the communication chip 906.
  • the integrated circuit die of the communication chip includes one or more embedded non-volatile memory structures having a SOT MTJ memory device with a multilayer barrier filter, in accordance with implementations of embodiments of the disclosure.
  • another component housed within the computing device 900 may contain an integrated circuit die that includes one or more embedded non-volatile memory structures having a SOT MTJ memory device with a multilayer barrier filter, in accordance with implementations of embodiments of the disclosure.
  • the computing device 900 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device 900 may be any other electronic device that processes data.
  • embodiments described herein include embedded non-volatile memory structures having SOT MTJ memory device with a multilayer barrier filter elements.
  • a memory device comprises an interconnect having a spin orbit torque (SOT) material.
  • a magnetic tunnel junction (MTJ) device comprises a free layer magnet coupled to the interconnect, a reference fixed magnet, and a barrier material between the free layer magnet and the reference fixed magnet.
  • a material stack is on the MTJ device, wherein the material stack comprises a spacer material, a pinned fixed magnet, an antiferromagnet, and a multilayer filter located within the material stack, wherein the multilayer filter is configured to reduce effects of manganese diffusion from the antiferromagnet.
  • Example embodiment 2 the memory device of example embodiment 1, wherein the pinned fixed magnet comprises a first pinned fixed magnet and a second pinned fixed magnet, the multilayer filter comprises: a first diffusion barrier on the first pinned fixed magnet; a ferromagnetic cobalt-based alloy on the first diffusion barrier; and a second diffusion barrier on the cobalt-based alloy.
  • Example embodiment 3 the memory device of example embodiment 2, wherein the multilayer barrier filter is located between the first pinned fixed magnet and the second pinned fixed magnet.
  • Example embodiment 4 the memory device of example embodiment 2, wherein the multilayer barrier filter is located between the reference fixed magnet and the first pinned fixed magnet, and the spacer material is located between the first the pinned fixed magnet and the second pinned fixed magnet.
  • Example embodiment 5 the memory device of example embodiment 2, wherein the multilayer barrier filter comprises a first multilayer barrier filter, the memory device further comprising a second multilayer barrier filter, wherein the first multilayer barrier filter is located between the first pinned fixed magnet and the second pinned fixed magnet, and the second multilayer barrier filter is located between the reference fixed magnet and the spacer material.
  • the multilayer barrier filter comprises a first multilayer barrier filter
  • the memory device further comprising a second multilayer barrier filter
  • the first multilayer barrier filter is located between the first pinned fixed magnet and the second pinned fixed magnet
  • the second multilayer barrier filter is located between the reference fixed magnet and the spacer material.
  • Example embodiment 6 the memory device of example embodiment 2, 3, 4, or 5, wherein the first pinned fixed magnet and the second pinned fixed magnet each have a thickness of approximately .5 to 1 nm.
  • Example embodiment 7 the memory device of example embodiment 2, 3, 4, or 5, wherein the first diffusion barrier and the second diffusion barrier comprise any heavy metal that acts as a barrier to manganese diffusion.
  • Example embodiment 8 the memory device of example embodiment 7, wherein the heavy metal comprises at least one of tantalum, tantalum oxide, tungsten, iridium, and molybdenum, and the first diffusion barrier and the second diffusion barrier have a thickness of approximately .1 to .5 nm.
  • Example embodiment 9 the memory device of example embodiment 2, 3, 4, or 5, wherein the ferromagnetic cobalt-based alloy has a thickness of approximately .2 to 3 nm.
  • Example embodiment 10 the memory device of example embodiment 1, wherein the multilayer barrier filter comprises a ferromagnetic cobalt-based alloy and a diffusion barrier on the multilayer barrier filter.
  • Example embodiment 11 the memory device of example embodiment 10, wherein the multilayer barrier filter is located between the spacer material and the pinned fixed magnet.
  • Example embodiment 12 the memory device of example embodiment 10, or 11, wherein the diffusion barrier comprises tantalum or tantalum oxide, and the spacer material comprises ruthenium or iridium.
  • Example embodiment 13 the memory device of example embodiment 10, or 11 , wherein the ferromagnetic cobalt-based alloy has a thickness of approximately .3 to .4 nm.
  • a memory device comprises an interconnect having a spin orbit torque (SOT) material.
  • a magnetic tunnel junction (MTJ) device comprises a free layer magnet coupled to the interconnect, a reference fixed magnet, and a barrier material between the free layer magnet and the reference fixed magnet.
  • a material stack is on the MTJ device, wherein the material stack comprises a spacer material, a first pinned fixed magnet, a second pinned magnet, an antiferromagnet, and a multilayer filter located within the material stack, wherein the multilayer filter comprises a first diffusion barrier on the first pinned fixed magnet; a ferromagnetic cobalt-based alloy on the first diffusion barrier; and a second diffusion barrier on the cobalt-based alloy.
  • Example embodiment 15 The memory device of claim 14, wherein multilayer filter is located between the first pinned fixed magnet and the second pinned fixed magnet.
  • Example embodiment 16 The memory device of claim 14, wherein the multilayer barrier filter is located between the reference fixed magnet and the first pinned fixed magnet, and the spacer material is located between the first pinned fixed magnet and the second pinned fixed magnet.
  • Example embodiment 17 The memory device of claim 14, wherein the multilayer barrier filter comprises a first multilayer barrier filter, the memory device further comprising a second multilayer barrier filter, wherein the first multilayer barrier filter is located between the first pinned fixed magnet and the second pinned fixed magnet, and the second multilayer barrier filter is located between the reference fixed magnet and the spacer material.
  • Example embodiment 18 The memory device of claim 14, 15, 16, or 17, wherein the first pinned fixed magnet and the second pinned fixed magnet each have a thickness of approximately .5 to 1 nm.
  • Example embodiment 19 The memory device of claim 14, 15, 16, or 17, wherein the first diffusion barrier and second diffusion barrier comprise any heavy metal that acts as a barrier to manganese diffusion.
  • Example embodiment 20 The memory device of claim 19, wherein the first diffusion barrier and the second diffusion barrier comprise tantalum or tantalum oxide having a thickness of approximately .1 to .5 nm.
  • Example embodiment 21 The memory device of claim 14, 15, 16, or 17, wherein the ferromagnetic cobalt-based alloy has a thickness of approximately .2 to 3 nm.
  • Example embodiment 22 A method of fabricating an integrated circuit device comprises forming a SOT interconnect with a write electrode in an opening in a dielectric layer.
  • a MTJ material stack is formed on the SOT interconnect, and a material layer stack having a multilayer barrier filter is formed over the MTJ material stack.
  • a lithography step is performed that forms a photoresist mask on an uppermost surface of the material layer stack.
  • the material layer stack and the MTJ material stack are patterned in alignment with the photoresist mask to form a memory device.
  • a second dielectric layer is deposited over the memory device and patterning another interconnect line over the second dielectric layer.
  • Example embodiment 23 The method of claim 22, further comprises forming the multilayer barrier filter with: a first diffusion barrier; a ferromagnetic cobalt-based alloy on the first diffusion barrier; and a second diffusion barrier on the cobalt-based alloy.
  • Example embodiment 24 The method of claim 23, wherein the first diffusion barrier and the second diffusion barrier comprise tantalum or tantalum oxide having a thickness of approximately .1 to .5 nm.
  • Example embodiment 25 The method of claim 23 or 24, wherein the ferromagnetic cobalt-based alloy has a thickness of approximately .2 to 3 nm.

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  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
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  • Hall/Mr Elements (AREA)

Abstract

L'invention concerne un dispositif de mémoire comprenant une interconnexion comportant un matériau de couplage spin-orbite (SOT). Un dispositif à jonction tunnel magnétique (MTJ) comprend un aimant à couche libre couplé à l'interconnexion, un aimant fixe de référence et un matériau barrière entre l'aimant à couche libre et l'aimant fixe de référence. Un empilement de matériaux se trouve sur le dispositif MTJ, l'empilement de matériaux comprenant un matériau d'espacement, un aimant fixe fixé, un antiferromagnétique, et un filtre multicouche situé à l'intérieur de l'empilement de matériaux, le filtre multicouche étant configuré pour réduire les effets de diffusion de manganèse provenant de l'antiferromagnétique.
PCT/US2018/012240 2018-01-03 2018-01-03 Couche de filtre pour un empilement antiferromagnétique synthétique supérieur dans le plan (saf) pour une mémoire à couplage spin-orbite (sot) Ceased WO2019135743A1 (fr)

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WO2021142817A1 (fr) * 2020-01-19 2021-07-22 北京航空航天大学 Mémoire magnétique

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WO2017160311A1 (fr) * 2016-03-18 2017-09-21 Intel Corporation Approches à base de damasquinage pour l'incorporation de dispositifs à mtj de hall à spin dans un processeur logique et structures résultantes

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WO2017160311A1 (fr) * 2016-03-18 2017-09-21 Intel Corporation Approches à base de damasquinage pour l'incorporation de dispositifs à mtj de hall à spin dans un processeur logique et structures résultantes

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