WO2019121383A1 - Method for self-testing, data bus arrangement and use - Google Patents

Abstract

The invention relates to a method for self-testing a signal transmission for the communication in a data bus arrangement, wherein the data bus arrangement has a first data bus line (3) and a transceiver (1), and the transceiver (1) has a first stage (15) and the first stage (15) is connected to the first data bus line (3), wherein the following further steps are performed: - transmitting a first test signal from the first stage (15) to the first data bus line (3), - measuring a first voltage level (3b-d) on the first data bus line (3), - comparing the measured first voltage level (3b-d) with a first setpoint voltage level, and - ascertaining whether the first stage (15) is functional by means of the result of the comparison. The invention furthermore relates to a data bus arrangement and a use.

Description

 Method for self-test, data bus arrangement and use

The invention relates to a method for self-test according to the preamble of claim 1, a data bus arrangement according to claim 13 and a use according to claim 15.

In conventional data bus arrangements, which correspond to the standard CAN, two data bus lines are present, to each of which several control units are connected. These controllers usually each have a controller and a transceiver housed. The control units are connected to the data bus lines by means of a stub line, one of the data bus lines being a CAN high and a CAN low line in each case. CAN data bus arrangements are e.g. used in motor vehicles to avoid a diverse single wiring between ECUs.

In idle state, the same voltage value is set on both data bus lines or the voltage values on both data bus lines are not far apart. This resting state is also referred to as a recessive state. If the data bus lines are set to a dominant state, the voltage on the CAN high line rises and the voltage on the CAN low line drops. Thus, the two voltage levels of the data bus lines in the dominant state are further apart than in the recessive state. In addition, the input resistance of the CAN high and CAN low lines in the dominant mode of the transceiver is lower.

The transceiver has two connections to the controller: one transmit input (TX) and one receive input (RX). The transceiver receives information about the setting of the dominant or the recessive state via the transmit input. The reception input forms a readback line for the signals. These are going through read the transceiver from the data bus and passed it to the controller.

When CAN transceivers send telegrams to the bus - controlled by the CAN controller - a bit sequence of zeros and ones is present at the transceiver's TX input TX. During the transmission of the individual bits, the transmitting CAN controller reads back the bit via the receive input RX of the transceiver.

In the case of simultaneous communication between the control units, the bits in the data frames determine which control unit is first allowed to send its data ("arbitration"), whereby the priority of the respective control unit is determined in such a way that, for example, safety-relevant messages (for example in the event of failure of the Motor control) can be sent in time before simple warnings (for example, failure of an LED display).

The transceivers comprise at least a first and a second driver, wherein the drivers are each assigned to a data bus line and generate the corresponding signals for the associated bus line and pass on to this bus wei. By reading back the signals via the receiving input RX during the arbitration, the priority can be determined and a malfunctioning driver can be detected - e.g. through the microcontroller (when a recessive is read back when sending a dominant bit).

Currently, there is no way to independently test a CAN transceiver at startup. The only option would be to put the CAN controller in a test mode, to request a dominant level from the TX input TX and a zero to read back to RX. The effort is high, the duration of the dominant level too long and thus disturbed the bus.

The same applies to a LIN bus and Flexray. The LIN bus has only one data bus line and only one stage in the transceiver that controls the voltage on the bus line. With Flexray, however, two data bus lines are provided, but additionally two further stages.

It is thus the object of the invention to provide a test facility for the functionality of the CAN transceiver, in particular the associated driver, in order to detect errors in a timely manner.

The object is solved by the independent claims.

The invention provides a method for self-test Sig nalübertragung for communication in a data bus arrangement, wherein the data bus arrangement comprises a first data bus line and a transceiver and the transceiver has a first stage and the first stage is connected to the first data bus. For the method, a first test signal is transmitted from the first stage to the first data bus. Subsequently, a first voltage level is measured on the first data bus line. Thereafter, this first measured voltage level is compared with a predetermined first target voltage level. From the result of this comparison can then be averaged whether the first stage is functional.

The method provides a cost-effective and inexpensive method for testing the (CAN) transceiver, in particular the drivers (equal stages and identifiable as so-called "dominant driver") of the transceiver. The data bus arrangement is based preferably on the standard LIN, CAN or Flexray.

In a preferred development of the invention, the data bus arrangement has a second data bus line and the transceiver has a second stage, wherein the second stage is connected to the second data bus line. In this case, the data bus arrangement preferably relates to the standard CAN or Flexray.

In developments of the invention, the same steps are carried out based on the second stage. First, a second test signal is transmitted from the second stage to the first data bus line. Thereafter, a second voltage level is measured on the second data bus and then the measured second voltage level is compared with a second nominal voltage level. Then it is determined by means of the result of the comparison, whether the second stage is functional. Due to the development, it is possible to advantageously test both stages for their functionality. The measurement of the voltage level and the comparison with the target voltage levels preferably takes place by means of a comparator or Kom comparators.

In a preferred embodiment of the invention, the transmission of the test signals from the first stage and the second stage takes place in succession. Only when both stages essentially send signals to the bus at the same time, a dominant state is generated. By transmitting the test signals in succession so no dominant state is generated, but only raised or lowered the voltage of the data bus line associated with the respective stage. Via a Termi nierungswiderstand follows the voltage of one line of the other essentially. In an alternative development of the invention, the transmission of the test signals from the first stage and the second stage takes place substantially simultaneously. This corresponds in principle to the normal function for the transmission of data signals, with a monitoring function being added. This can be designed differently. In this development, a CAN bus or Flexray is used.

In a first embodiment of this development, the test signal is designed so short that the test signal does not fall within the sampling period of the own controller or the controller of other participants of the data bus arrangement. In other words, the dominant level is ended before the sampling time. Thus, the connected controller and the other nodes do not detect this level as the beginning of a telegram. However, a voltage change on the bus may become apparent without necessarily detecting a dominant bit on the RX path (sense terminal) because the differential voltage threshold is not exceeded. Preferably, e.g. in a CAN bus system each associated with a comparator of the first and second data bus line (CAN-H and CAN-L) and ge checks whether the voltages change because it raised in the dominant state at CAN-H and lowered at the CAN-L becomes.

A LIN bus is only about the formation of the first test signal, since the LIN bus also includes only one data bus line. With the CAN bus and with Flexray, there is also a second test signal in addition to the first test signal, so that the training of both is meant here. This also applies to the following second embodiment.

In a second embodiment, the test signals are formed so long that a reception of the outgoing from the test signal voltage level on the readback path is feasible. The dominant level on the (CAN) high / low lines is therefore set "long enough" so that it can be detected via the normal receive path (RX), so that no additional comparator is required, but this causes a signal change at the receive input RX Preferably, this signal change in the form of a voltage level on the RX (corresponding to the dominant level on the bus) is set shorter than the sampling time on the controller and therefore has no effect on the controller The advantage of this solution is that the receiver can also be tested ,

In a preferred embodiment of the invention, the data bus arrangement in a transmission of the test signals in succession to two comparators. Preferably, a comparator is provided for each data bus. This can be used to determine whether only the transceiver currently being tested actually transmits or another node. Since no dominant states are generated on the bus with this solution, this method is particularly preferred and is also suitable for use during regular operation. Particularly preferably two comparators are provided for each data bus line. This makes it possible to reduce errors. As an alternative to the comparators, A / D converters can also be used.

In a further preferred embodiment of the invention, a time window is defined in which the voltage is detected and taken into account for further processing. Either the comparators or the A / D converters are active in the time window and detect the voltage or the comparators or A / D converters are continuously active and the results of the comparator are passed in the defined time window. In a development of the two alternative embodiments, a termination of the transmission of the first and / or the second test signal takes place as soon as the first measured voltage level and / or the second measured voltage level exceeds or falls below a threshold value. Thus, both in the first embodiment and in the second embodiment, the activation of the stage can be aborted prematurely as soon as one of the comparators exceeds or falls below the expected threshold. Alternatively, the time of the cancellation may be set to a point in time after a certain period of time, starting from the overshoot or undershooting of the threshold. Furthermore alternatively, the termination can also be triggered by a measured value at the receiving input, which falls below or exceeds a certain threshold.

In a further development, the measured voltage levels and / or the voltage levels exceeded at the comparator are stored and made available to a microcontroller for processing and evaluation.

In a further development, the test signal in the first and the second embodiment is suppressed and / or an error flag is set in the transceiver if a zero is present at the transmit input (ie TX = 0), i. when the CAN controller is transmitting at the same time. This advantageously ensures that the normal func tionality of the transceiver is not disturbed by the self-test.

In a further preferred refinement, the result of the self-test and the bus level are stored and made available to the connected microcontroller for reading via an interface (eg SPI). In a further preferred development of the invention, a dynamic decision is made as to whether the transmission of test signals takes place in succession or simultaneously.

In a further preferred embodiment, the result of the comparators is stored, preferably as a register flag or as multiple register flags. Either the raw data (comparator values) or the logical (processed) response (pass / fail) are stored.

In a further preferred development, the length of the test pulses can be configured. Particularly preferably, the comparator thresholds are also configurable.

In a further preferred development, the method is carried out several times in the case of simultaneously and also in the case of sequential transmission of the test signals to the data bus lines in order to improve the susceptibility to errors. Since the length of a bit is defined, it can be checked by reading the comparator (s) several times (for example, before, after), if only the test signal is present. A transmission of the connected, own controller is diagnosed via TX = 0 and the test is provided with an error flag.

In a further preferred embodiment, the self-test is performed before the actual communication begins; for example, after a wake-up signal at the start of the engine. The test can also be performed to test a failsafe function in which the transceiver should be shut down in the event of a fault. In further tests, the shutdown of the transceiver is preferably suppressed. It is therefore tested whether the transceiver still turns on or not yet turned on. Particularly preferably, the bus biasing is switched on before the transmission of the test signal (s). Bus biasing refers to the switching on of the recessive, high-impedance voltage levels on the high line and the low line.

The invention further relates to a data bus arrangement having a first data bus line and at least one transceiver, wherein the transceiver has a first stage and wherein the first stage is connected to the first data bus line, wherein the transceiver has a communication interface or a control pin, via which commands for executing a Self-tests are transmittable to the transceiver.

In a preferred development of the data bus arrangement, this comprises a second data bus line and the transceiver a second stage, wherein the second stage is connected to the second data bus line.

Preferably, the transceiver transmits the test signal via the said communication interface (e.g., SPI) or the control pin. This allows the test to run completely independently of the controller. Preferably, the transceiver is connected via the interface or the control pin to a microcontroller.

In a preferred embodiment of the invention, the data bus arrangement has a third and a fourth driver in the transceiver, wherein the third driver is connected to the first data bus line and the fourth driver is connected to the second data bus line. The standard of the data bus arrangement or the associated protocol refers to Flexray.

In addition, the invention relates to a use of the Datenbusan Regulation in a motor vehicle. Further preferred embodiments will become apparent from the dependent claims and the following description of exemplary embodiments with reference to FIGS.

 In a schematic representation, by way of example:

1 is a circuit diagram of a transceiver according to the invention on the example CAN,

Fig. 2 shows the waveform in the simultaneous transmission of

 Test signals

3 shows the idealized signal course in the case of non-simultaneous transmission of test signals in the case of many connected control devices (= recessive drivers),

Fig. 4 superimposition of the test pulses on the usual generation of a dominant bit.

Fig. 1 shows the schematic structure of a CAN transceiver 1, which is part of a data bus arrangement. The transceiver 1 is connected to a first data bus line 3 and a second data bus line 5, wherein the first data bus line 3 is designed as a CAN high line and the second data bus 5 as a CAN low line. The transceiver comprises a transmit input TX and a receive input RX and an interface 7 (eg designed as an SPI interface). In the transceiver, a reception module 9 and a transmission module 11 and a test module 13 are arranged. The receiving module 9 receives signals from the data bus lines 3, 5 and can process them, in order to then forward corresponding data via the receiving input RX to the CAN controller. The transmission module 11 receives signals via the transmission input TX and processes them. The transmission module 11 can then send corresponding data to a first Pass stage 15 and a second stage 17. Wherein the first stage 15 is a driver / a stage for the first data bus 3 and is connected to this and the second stage 17 is a driver / a stage for the second data bus 5 and connected thereto. The test module 13 receives data from the microcontroller via the interface 7 and forwards corresponding signals via the transmission module 11 to the first stage 15 and the second stage 17, which are connected to the first data bus line 3 and the second data bus line 5. Thus, test pulses can reach the data bus lines 3, 5 via the interface 7, the test module 13, the transmission module 11 and the first and second stages 15, 17.

In addition, the transceiver 1 comprises a first trigger 19 and a second trigger 21, which are each connected to one of the data bus lines 3, 5 and the test module 13 and preferably formed as comparators. Via the triggers 19, 21 it is possible to read out the voltage on the data bus lines 3, 5 and to process them in the test module 13. To store the data, the test module 13 preferably contains a read-back memory. Furthermore, the transceiver 1 comprises a bus biasing module 23.

2 shows the course of signals on the data bus lines 3, 5 and the associated signal at the receiving input RX when switching on both stages 15, 17 simultaneously. The voltage on the first data bus line 3 is generally designated by the reference numeral 3x, while the voltage on the second data bus line 5 is denoted by the reference numeral 5x. In the first period ZI of the representation, a dominant signal is generated on the data bus lines 3, 5 by increasing the voltage 3a on the first data bus line 3 (CAN high) and reducing the voltage 5a on the second data bus line 5 (CAN low) becomes. At the reception input RX the signal changes from one High ("1"), reference numeral 100, during the recessive state, goes low ("0"), 110, during the dominant state.

In the second period Z2 of the illustration, a test pulse 3b, 5b is applied to the data bus lines 3, 5. In this case, the first and second stages 15, 17 simultaneously transmit test signals 3b, 5b to the first and second data bus lines 3, 5. Here, too, the voltage 3b on the first data bus line 3 (CAN-High) is increased and the voltage 5b on the second data bus 5 (CAN-Low) reduced - but for a shorter period than for the generation of the dominant state. Accordingly, a shorter "0" state also arises at the receiving input RX. The very short turn-on of the two stages 15, 17 makes it possible to test the functionality of the transceiver while minimizing the disturbance on the data bus lines 3, 5 This is done by reading back the voltages from the data bus lines 3, 5 via the triggers 19, 21. A voltage threshold is preferably defined in the two triggers 19, 21. When the voltage threshold is undershot or exceeded by the voltage on the data bus lines 3, 5, an abort of the transmission of the test pulse is preferably carried out, for which purpose the stages 15, 17 are activated accordingly.

Particularly preferably, the test signal 3b, 5b is so short in time that it does not fall within the sampling period of other subscribers in the data bus arrangement. Thus, the test signal on the data bus lines 3, 5 can be well identified and does not interfere with the other participants.

FIG. 3 shows a self-test of the transceiver according to the invention, wherein test signals 3c, 5c, 3d, 5d from the stages 15, 17 are not applied simultaneously to the data bus lines 3, 5 become. In the first period ZI, a test signal 3c, 5c is transmitted from the first stage 17 and the second stage 19 to the first data bus line 3 and the second data bus line 5, so that the voltage 3c, 5c on the data bus lines 3, 5 is increased. In the second period Z2, a test signal 3d, 5d is transmitted from the first stage 17 and the second stage 19 for the first data bus line 3 and the second data bus line 5, so that the voltage 3d, 5d is respectively reduced on the data bus lines 3, 5. Due to the non-simultaneous transmission of the test signals 3c, 5c and 3d, 5d thus no dominant state on the data bus lines 3, 5 is generated, so that at the input RX input is only a high ("1"), which does not change over time ,

At the comparators, an excess of threshold value 120 occurs during the test signal when the voltage on the first data bus lines 3, 5 is undershot and below a threshold value 130 during the test signal when the voltage on the data bus lines 3, 5 is reduced the comparators are caused by falling below or exceeding the threshold values 120, 130, is preferably used to cancel the transmission of the respective test signal in order not to generate unnecessary disturbances on the data bus lines 3, 5. The comparators are preferably configurable in order to be able to set the optimum voltage threshold.

4 shows the superimposition of a test pulse with dominant bits of other receivers, the test signals for increasing and decreasing the voltage not being simultaneously applied to the data bus lines 3, 5, respectively. On the left side in Fig. 4a-d, the superimposition of a test signal is shown by an increase of the voltage on the data bus lines 3,5, while on the right side in Figs. 4e-h the superposition represented by a reduction of the voltage. The time is shown on the X-axis and the voltage on the Y-axes.

In Fig. 4a, a conventional signal transmission for the generation of a dominant bit 3a, 5a to the data bus lines 3, 5 shown, wherein on the first data bus line 3 (CAN-H line), the voltage is increased 3a and on the second data bus 5 (CAN -L line), the voltage 5a is reduced. FIG. 4b shows a test signal 3c, 5c generated by the first stage 15 and the second stage 17. The test signal 3c, 5c can be seen on both data bus lines 3, 5. FIG. 4c shows the superimposition of the signals from FIGS. 4a and 4b. In Fig. 4d, the voltage is applied to the receive input RX, wherein during the recessive state 100, a "1" is present and during the dominant state 110 a "0".

The explanations apply equally to FIGS. 4e-h, with the difference that here a test signal 3d, 5d generated by the first and the second stage 15, 17 leads to a reduction of the voltage on the data bus lines 3, 5 and dominant bit is superimposed. In both examples, the test signal is not visible at the receive input RX. Thus, the transceiver can be tested during operation on its functionality, without that the signals are disturbed on the data bus lines 3,5. Reference sign list:

TX send input

 RX reception input

 I (CAN) transceiver

 3 first data bus line

 5 second data bus line

 3x voltage on the first data bus line (general)

5x voltage on the second data bus line (general)

3a voltage on the first data bus during a dominant bit

 5a voltage on the second data bus during a dominant bit

 3b voltage on the first data bus during a

Test pulses with simultaneous transmission of a signal through the stage 15, 17

 5b voltage on the second data bus during a

Test pulse with simultaneous transmission of a signal through the stages 15, 17

 3c boosts voltage on the first data bus during a test pulse as it passes through the first stage 15 5c increases voltage on the second data bus during a test pulse as it passes through the second stage 17 3d Reduced voltage on the first data bus during a test pulse on transmission through the first stage 15 5d reduced voltage on the second data bus during a test pulse when transmitted through the second stage 17th

 7 interface

9 receiving module

 II transmitter module

13 test module

15 first stage

17 second stage 19 triggers

 21 triggers

 23 bus biasing module

 100 recessive condition

 110 dominant state

 120 Threshold for overshoot

130 Threshold for underrun

Claims

claims A method for self-testing a signal transmission for communication in a data bus arrangement, wherein the data bus arrangement comprises a first data bus line (3) and a transceiver (1) and the transceiver (1) has a first stage (15) and the first stage (15 ) with the first data bus line (3), characterized in that the following further steps are carried out:  Transmitting a first test signal from the first stage (15) to the first data bus line (3),  Measuring a first voltage level (3b-d) on the first data bus line (3),  Comparing the measured first voltage level (3b-d) with a first target voltage level and  - Determine whether the first stage (15) is functional by means of the result of the comparison. 2. The method according to claim 1, characterized in that the data bus arrangement has a second data bus line (5) and a second stage (17) and the second stage (17) is connected to the second data bus line (5) and the following step is carried out:  - Transmitting a second test signal from the second stage (17) to the first data bus (5). 3. The method according to claim 2, characterized in that the following step is carried out:  Measuring a second voltage level (5b-d) on the second data bus line (5), Comparing the measured second voltage level (5b-d) with a second desired voltage level and - Determine whether the second stage (17) is functional by means of the result of the comparison. 4. The method according to any one of claims 2 or 3, characterized in that the transmission of the first and second test signal takes place in succession. 5. The method according to any one of claims 2 or 3, characterized in that the transmission of the first and second test signal takes place simultaneously. 6. The method according to claim 5, characterized in that the first test signal is formed so short in time that the first test signal does not fall on the sampling period of other participants of the data bus arrangement. 7. The method according to any one of claims 5 or 6, characterized in that the second test signal is formed so short in time that the second test signal does not fall on the sampling period of other participants of the data bus arrangement. 8. The method according to claim 5, characterized in that the following step is carried out:  - Receiving signals via the first data bus line (3) by the transceiver (1), wherein receiving the signals of the transceiver (1) via a readback path and the first test signal is formed so long that a reception of the resulting from the first test signal voltage level (3b-d) on the readback path is feasible. 9. The method according to any one of claims 5 or 8, characterized in that the following step is carried out: - Receiving signals via the second data bus line (5) by the transceiver (1), wherein receiving the signals of the transceiver (1) via a readback path and the second test signal is formed so long that a reception of the resulting from the second test signal voltage level (5b-d) via the readback path is feasible. 10. The method according to any one of the preceding claims, characterized in that a termination of the transmission of the first test signal takes place as soon as the first measured voltage level (3b-d) exceeds or falls below a threshold value. 11. The method according to any one of claims 2 to 10, characterized in that a termination of the transmission of the second test signal takes place as soon as the second measured voltage level (5b-d) exceeds or falls below a threshold value. 12. The method according to any one of the preceding claims, characterized in that the measured voltage levels are stored and a microcontroller for processing available ge provides. A data bus arrangement comprising a first data bus line (3) and at least one transceiver (1), wherein the transceiver (1) has a first stage (15) and wherein the first stage (15) is connected to the first data bus line (3) in that the transceiver has a communication interface (7) or a control pin via which commands for carrying out a self-test can be transmitted to the transceiver (1). 14. Data bus arrangement according to claim 13, characterized in that the data bus arrangement has a second data bus line (5) and the transceiver (1) has a second stage (17) and wherein the second stage (17) is connected to the second data bus line (5). 15. Use of the method according to one of claims 1 to 12 in a motor vehicle.