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WO2019113837A1 - 确定抵消支路的控制参数的方法及其装置、触控检测装置 - Google Patents

确定抵消支路的控制参数的方法及其装置、触控检测装置 Download PDF

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Publication number
WO2019113837A1
WO2019113837A1 PCT/CN2017/115935 CN2017115935W WO2019113837A1 WO 2019113837 A1 WO2019113837 A1 WO 2019113837A1 CN 2017115935 W CN2017115935 W CN 2017115935W WO 2019113837 A1 WO2019113837 A1 WO 2019113837A1
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Prior art keywords
branch
self
signal
output signal
capacitance
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Ceased
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PCT/CN2017/115935
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English (en)
French (fr)
Inventor
方军
廖观亮
杨烊
姚志
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Shenzhen Goodix Technology Co Ltd
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Shenzhen Goodix Technology Co Ltd
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Priority to EP17931826.6A priority Critical patent/EP3531143B1/en
Priority to PCT/CN2017/115935 priority patent/WO2019113837A1/zh
Priority to CN201780002250.0A priority patent/CN108124464B/zh
Priority to US16/421,477 priority patent/US10852888B2/en
Publication of WO2019113837A1 publication Critical patent/WO2019113837A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2605—Measuring capacitance
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means

Definitions

  • the embodiments of the present invention relate to the field of circuit technologies, and in particular, to a method, device, and touch detection device for determining control parameters of an offset branch.
  • Touch control such as application on electronic products such as smart terminals, allows the user to operate the terminal by gesture operation, and get rid of the traditional mechanical keyboard, making human-computer interaction more straightforward.
  • the capacitive touch technology Since the touch control can be realized directly based on the influence of the human body on the electric field, the capacitive touch technology has become one of the main means for implementing touch control on electronic products.
  • some are based on mutual-capacitive touch, and some are based on self-capacitive touch. Due to the self-capacitance touch, it can improve the functions of waterproofing, anti-interference and power consumption, and has been widely used. Therefore, most touch control systems are integrated into mutual capacitance detection and self-capacity detection.
  • one of the technical problems to be solved by the embodiments of the present invention is to provide a method for determining a control parameter of an offset branch, a device thereof, and a touch detection device for overcoming or relieving the above-mentioned technical defects in the prior art.
  • the embodiment of the present application provides a method for determining a control parameter of an offset branch, which includes:
  • the back-end processing circuit of the self-capacitance detection branch performs at least differential processing on the output signal of the cancellation branch and the output signal of the self-capacitance detection branch to obtain a second output signal;
  • a control parameter of the cancellation branch is determined based on the sum of the phase delays and a phase delay generated by the back end processing circuit in response to the second excitation signal.
  • the first constant signal is a first DC bias signal
  • the second constant signal is a second DC bias signal
  • the first excitation signal and the second excitation signal have the same frequency and starting phase.
  • control parameter of the offset branch includes a resistance of the adjustable resistor and a capacitance of the adjustable capacitor, and the adjustable resistor and the adjustable capacitor are used The original reference value of the resistance of the front end RC network and the self-capacitance to be detected in the self-capacitance detection branch is cancelled or reduced.
  • setting the RC network in the offset branch to be pure when determining a phase delay generated when the backend processing circuit responds to the second excitation signal Impedance network or near pure impedance network.
  • determining, according to the first output signal, that the self-capacitance detection branch and the back-end processing circuit of the self-capacitance detection branch respond to the first excitation signal includes:
  • determining, according to the first output signal, that the self-capacitance detection branch and the back-end processing circuit of the self-capacitance detection branch respond to the first excitation signal also includes:
  • determining, according to the second output signal, a phase delay generated when the backend processing circuit responds to the second excitation signal includes:
  • a phase delay generated by the back end processing circuit in response to the second excitation signal is determined based on a magnitude and a phase of the second output signal.
  • determining the back according to the second output signal includes:
  • determining a control parameter of the cancellation branch according to the sum of the phase delays and a phase delay generated by the backend processing circuit in response to the second excitation signal include:
  • determining, according to a phase delay generated by the self-capacitance detection branch in response to the first excitation signal, determining a control parameter of the cancellation branch includes:
  • control parameter of the cancellation branch includes a first control parameter and a second control parameter, and correspondingly, according to the self-capacitance detection branch, the front end RC network and the Determining the association relationship of the RC network in the branch, and determining the control parameters of the offset branch includes:
  • the backend processing circuit includes at least one of the following: an amplifier, a filter, an analog to digital converter, and the amplifier is configured to use the self-detecting branch
  • the output signal of the path and the output signal of the canceling branch are subjected to differential processing
  • the filter is used for filtering processing on the differentially processed signal
  • the analog-to-digital converter is configured to perform modulating the filtered signal Number conversion processing.
  • the embodiment of the present application further provides an apparatus for determining a control parameter of an offset branch, which includes: a first phase delay determining unit, a second phase delay determining unit, and a control parameter determining unit, where:
  • the back-end processing circuit of the self-capacitance detecting branch performs at least differential processing on an output signal of the canceling branch and an output signal of the self-capacitance detecting branch to obtain a first output signal, the first phase delay determining unit And determining, according to the first output signal, a sum of phase delays generated when the self-capacitance detection branch and the back-end processing circuit of the self-capacitance detection branch respond to the first excitation signal;
  • the output signal of the self-capacitance detecting branch is at least differentially processed to obtain a second output signal
  • the second phase delay determining unit is configured to determine, according to the second output signal, the response generated by the back-end processing circuit in response to the second excitation signal Phase delay
  • the control parameter determining unit is configured to determine a control parameter of the canceling branch according to the phase delay sum and a phase delay generated by the back end processing circuit in response to the second excitation signal.
  • the embodiment of the present application further provides a touch detection device, including: a self-capacitance detection branch, an offset branch, a back-end processing circuit, and the above-mentioned device for determining a control parameter of an offset branch, the self-capacitance detection Forming a self-capacitance to be detected between the branch and the system ground, the canceling branch is configured to offset at least the original reference value of the self-detecting self-capacitance according to the determined control parameter; the back-end processing circuit is configured to The self-capacitance detection branch and the output signal of the cancellation branch are at least differentially processed to implement touch detection.
  • the back-end processing circuit of the self-capacitance detection branch pairs the offset branch
  • the output signal of the path and the output signal of the self-capacitance detection branch are at least differentially processed to obtain a first output signal; determining, according to the first output signal, a self-capacitance detection branch and a back end processing of the self-capacitance detection branch And summing a phase delay generated by the circuit in response to the first excitation signal; inputting a second constant signal to the self-capacitance detection branch, and inputting a second excitation signal to the cancellation branch, correspondingly, the self-capacitance detection branch
  • the back end processing circuit of the circuit performs at least differential processing on the output signal of the canceling branch and the output signal of the self-capacitance detecting branch to obtain a second output signal; determining, according to the second output signal
  • FIG. 1 is a schematic structural diagram of a touch detection apparatus according to an embodiment of the present application.
  • FIG. 2 is a schematic flowchart of a method for determining control parameters of an offset branch in Embodiment 2 of the present application;
  • FIG. 3 is a schematic diagram showing the dynamic structure of the circuit of FIG. 1 when step S101 is performed in Embodiment 3 of the present application;
  • step S102 in Embodiment 4 of the present application is an exemplary schematic diagram of step S102 in Embodiment 4 of the present application.
  • FIG. 5 is a schematic diagram showing the dynamic structure of the circuit of FIG. 1 when step S103 is performed in Embodiment 5 of the present application;
  • FIG. 6 is an exemplary schematic diagram of step S104 in Embodiment 6 of the present application.
  • FIG. 7 is a schematic structural diagram of an apparatus for determining control parameters of an offset branch in Embodiment 7 of the present application.
  • FIG. 1 is a schematic structural diagram of a touch detection apparatus according to an embodiment of the present invention; as shown in FIG. 1 , the method specifically includes: a self-capacitance detection branch, an offset branch, a back-end processing circuit, and offset by the determination in FIG. 7 described below.
  • a device for controlling parameters of the branch (not shown in FIG. 1), a self-capacitance to be detected is formed between the self-capacitance detecting branch and the system ground, and the canceling branch is used for offsetting or subtracting according to the determined control parameter
  • the original reference value of the self-capacitance to be detected is small;
  • the back-end processing circuit is configured to perform at least differential processing on the output signals of the self-capacitance detection branch and the cancellation branch to implement touch detection.
  • the self-capacitance detection branch includes: a resistor R0, a resistor R of the front-end RC network, and a self-capacitance C to be detected, and the front-end RC network also includes a self-capacitance C to be detected.
  • the resistor R0 is specifically, for example, an output impedance of a touch chip or other chip.
  • the offset branch includes: a resistor R1, and an offset branch formed by the adjustable resistor R_cancle and the adjustable capacitor C_cancle (also referred to as a cancle circuit), and the adjustable resistor R_cancle and the adjustable capacitor C_cancle can be The value is adjusted to offset or reduce the resistance R of the front-end RC network in the self-capacitance detection branch, and the original reference value of the self-capacitance to be detected.
  • the cancellation or reduction can be understood as two possibilities.
  • the adjustable resistor R_cancle cancels or reduces the resistance R of the front-end RC network, and the adjustable capacitor C_cancle cancels or reduces the original reference value of the self-capacitance to be detected, or
  • the original reference value of the self-capacitance to be detected is, for example, a capacitance value formed between the self-capacitance detection branch and the system ground when the touch detection device is shipped. Due to the process or environment or human factors, the capacitance values formed between the different self-capacitance detection branches and the system ground may be different. Therefore, the values of the adjustable resistor R_cancle and the adjustable capacitor C_cancle for the purpose of cancellation or reduction are It can also be different.
  • the back-end processing circuit includes: an amplifier, a filter, and an analog-to-digital converter (ADC), and the amplifier is used to output an output signal of the self-detection branch. And performing differential processing on the output signal of the canceling branch, wherein the filter is further configured to perform filtering processing on the differentially processed signal, and the analog-to-digital converter is configured to perform analog-to-digital conversion processing on the filtered signal.
  • ADC analog-to-digital converter
  • the amplifier may be a Programble Gain Amplifier (PGA), and the filter may be an Anti-alias Filter (AAF).
  • PGA Programble Gain Amplifier
  • AAF Anti-alias Filter
  • the sequence of signal processing by each circuit in the back-end processing circuit is, for example, first performing differential processing, then performing filtering processing, and finally performing analog-to-digital conversion processing.
  • the order of signal processing herein is merely an example and is not a limitation.
  • the output signals of the self-capacitance detection branch and the cancellation branch are input to the back-end processing circuit for at least differential processing, so that the offset branch cancels or reduces the to-be-detected in the self-capacitance detection branch.
  • the original reference value of the self capacitance is the original reference value of the self capacitance.
  • a resistor R1 is provided in the canceling branch to correspond to the resistor R0 in the self-capacitance detecting branch.
  • the resistor R1 may not be provided in the offset branch in other embodiments.
  • FIG. 2 is a schematic flowchart of a method for determining a control parameter of an offset branch in the second embodiment of the present application; for any self-capacitance detection branch, as shown in FIG. 2, the method includes the following steps S101-S105:
  • the first constant signal is a first DC bias signal, for example, the value of the first DC bias signal is equal to an average value V cmi of the excitation signal used in touch detection.
  • the first excitation signal TX1 has a set frequency and phase, such as a frequency of ⁇ and a phase of zero.
  • FIG. 3 is a schematic diagram showing the dynamic structure of the circuit of FIG. 1 when step S101 is performed in the third embodiment of the present application; as shown in FIG. 3, a first constant signal (such as the mean value V cmi of the excitation signal) is input to the canceling branch, and the The self-capacitance detection branch inputs a first excitation signal TX1 having a frequency of w and a starting phase of zero.
  • a first constant signal such as the mean value V cmi of the excitation signal
  • step S102 when the self-capacitance detection branch and the back-end processing circuit of the self-capacitance detection branch respond to the first excitation signal, the phase delay sum is generated according to the first output signal. Specifically, determining, according to the amplitude and phase of the first output signal, a sum of phase delays generated by the self-capacitance detection branch and the back-end processing circuit in response to the first excitation signal.
  • step S102 may specifically include step S112 and step S132.
  • FIG. 4 it is an exemplary schematic diagram of step S102 in the fourth embodiment of the present application:
  • the first excitation signal TX1 is processed by the self-capacitance detection circuit, and then sequentially amplified by the amplifier in the back-end processing circuit with the first constant signal, and the filter processing and the mode of the filter are performed.
  • the analog to digital conversion process of the digital converter results in a first output signal.
  • the first output signal is processed by the back-end processing circuit, and the first output signal is subjected to demodulation integration processing to obtain two orthogonal signals: a first in-phase signal. (also referred to as the first I signal: I 1 ) and the first quadrature signal (also referred to as the first Q signal: Q 1 ).
  • S122 Determine, according to the first in-phase signal and the first orthogonal signal, a magnitude and a phase of the first output signal.
  • S132 Determine, according to the amplitude and phase of the first output signal, a sum of phase delays generated by the self-capacitance detection branch and the back-end processing circuit in response to the first excitation signal.
  • phase delay of the first excitation signal TX1 after the self-capacitance detection of the DC front-end RC network is The phase delay caused by the processing of the amplifier and filter in the processing circuit is After the analog-to-digital conversion process, after the demodulation integral operation, the first in-phase signal I 1 and the first quadrature signal Q 1 can be obtained, and the phase delay sum can be specifically determined by the following formula (1).
  • the second constant signal is a second DC bias signal, for example, the value of the second DC bias signal is also equal to the average value of the excitation signal used in the touch detection, in other words, the first constant signal and
  • the second constant signals may be multiplexed with each other.
  • the second excitation signal TX2 has a set frequency and a starting phase, for example, the frequency of the first excitation signal TX1 is w, and the initial phase is 0.
  • the frequency and the initial phase of the first excitation signal TX1 and the second excitation signal TX2 are respectively the same, so that when the phase delay and the phase delay are determined in the correlation step, the equivalent is substantially equivalent.
  • the excitation signal is based on the same attribute, thereby saving the calculation amount of data processing.
  • the initial phase of the first excitation signal TX1 and the second excitation signal TX2 is preferably 0.
  • the frequency and the starting phase of the first excitation signal TX1 and the second excitation signal TX2 may also be different.
  • FIG. 5 is a schematic diagram showing the dynamic structure of the circuit of FIG. 1 when step S103 is performed in the fifth embodiment of the present application; as shown in FIG. 5, a second constant signal (such as the mean value of the excitation signal V cmi ) is input to the self-capacitance detection branch, and The canceling branch input frequency is ⁇ , and the starting phase is 0, the second excitation signal TX2.
  • a second constant signal such as the mean value of the excitation signal V cmi
  • the RC network in the cancellation branch is set to be an approximately pure impedance network or a pure impedance network, thereby avoiding phase delay caused by the RC network in the cancellation branch.
  • the production can be set to an approximately pure impedance network by adjusting the adjustable resistance and the adjustable capacitance in the RC network in the cancellation branch to a minimum value.
  • the amplitude and phase of the second output signal may be determined according to the second output signal.
  • the phase delay generated by the back end processing circuit in response to the second excitation signal may be determined according to the second output signal.
  • step S104 may specifically include S114 and step S134, as shown in FIG. 6, which is an exemplary schematic diagram of step S104 in Embodiment 6 of the present application:
  • the second excitation signal TX2 is subjected to the offset branch processing and then sequentially subjected to differential amplification with the second constant signal through the amplifier in the back-end processing circuit, filtering processing of the filter, and modulus.
  • the analog to digital conversion process of the converter results in a second output signal.
  • the RC network in the offset branch is approximately a pure impedance network, so that the phase delay is not caused to the second excitation signal TX2 from the perspective of the phase delay caused. Only the back end processing circuit causes a phase delay to the second excitation signal TX2. Pure impedance networks are the easiest to handle, and engineering practices do the same. In fact, since R1R_cancel and C_cancel are known, the phase and amplitude of the second output signal can be calculated and still processed. The following examples are still exemplified by the simplest pure impedance network.
  • the second output signal is subjected to demodulation integration processing to obtain two orthogonal signals: a second in-phase signal (also referred to as a second I signal: I 2 ) and a second Quadrature signal (also referred to as second Q signal: Q 2 ).
  • a second in-phase signal also referred to as a second I signal: I 2
  • a second Quadrature signal also referred to as second Q signal: Q 2
  • the effects of the self-capacitance detection branch and the back-end processing circuit on the amplitude and phase of the first excitation signal TX1 are reflected by the second in-phase signal and the second quadrature signal.
  • the second in-phase signal I 2 and the second quadrature signal Q 2 can be obtained, and the phase delay is determined by the following formula (2).
  • S105 Determine a control parameter of the cancellation branch according to a sum of phase delays caused by the self-capacitance detection branch and the back-end processing circuit and a phase delay caused by the back-end processing circuit.
  • the offset branch actually includes an adjustable resistor and a tunable capacitor.
  • the control parameters of the offset branch include the value of the adjustable resistor and the value of the adjustable capacitor.
  • the adjustable resistor and the adjustable capacitor are sized to cancel or reduce the resistance of the front end RC network in the self-capacitance detection branch and the original reference value of the self-capacitance to be detected.
  • step S105 may specifically include the following steps S115 to S125:
  • determining the control parameters of the cancellation branch in step S125 may include:
  • control parameter of the offset branch includes a first control parameter and a second control parameter, and correspondingly, according to the relationship between the front end RC network in the self-capacitance detection branch and the RC network in the offset branch, Determining, by the self-capacitance detection branch, a control relationship between the front end RC network and the RC network in the offset branch, and presetting a first control parameter of the offset branch, A second control parameter of the cancellation branch is determined.
  • the first control parameter preset in the cancellation branch is located in a set value range, and the set value range is determined according to an original reference value of the self-capacitance to be detected.
  • the experience value is determined.
  • the empirical value is determined by statistically summarizing original reference values in touch detection devices in different processes and environments.
  • the step S105 is further exemplarily explained in conjunction with the above formulas (1) and (2).
  • phase delay caused by the front-end RC network on the self-capacitance detection path Satisfy the following formula (4):
  • the corresponding resistance and capacitance product that is, the RC parameter
  • the constant value is calculated according to the first I signal I 1 , the first Q signal Q 1 , the second I signal I 2 , the second Q signal Q 2 , and the frequency ⁇
  • the self-capacitance detection is established by the constant value.
  • the adjustable gears of the adjustable resistors R_cancle and C_cancle are known, and therefore, as long as the adjustable resistor R_cancle And the value of C_cancle is such that the product of the original reference value of the self-capacitance to be detected after the addition of the resistor R and the resistor R0 (ie, C(R+R 0 )) is equal to the sum of the resistor R0 and the adjustable resistor R_cancle and the adjustable capacitor C_cancle The product (ie (R1+R_cancel)C_cancel) is equal.
  • a constant value const can be obtained by the above steps, and then a value of the adjustable capacitor C_cancle is set by the gear selection, and then an adjustable one is obtained by calculating the formula (5).
  • the theoretical value of the capacitance R_cancle is the closest value to determine the control parameters in the above-mentioned offset branch.
  • the adjustable capacitor C_cancle is selected. Considering the symmetry of the adjustable capacitor C_cancle and the self-capacitance to be detected on the circuit, the value range can be selected in combination to further reduce the data processing, thereby at least canceling or reducing the original reference value of the self-capacitance to be detected. At the same time, and further improve the performance of detecting the auto-coupling capacitor.
  • the values of the adjustable resistor R_cancle and the adjustable capacitor C_cancle may also be determined by looking up the table. Specifically, for example, an adjustable resistor R_cancle and a tunable capacitor C_cancle can be performed. The traversal selection of the values, and the calculation of (R1 + R_cancel) C_cancel values and the values are stored in the form of a table inside the chip. After the constant value const is calculated according to the above formula (5), a value satisfying (R1+R_cancel)C_cancel is selected from the stored table to be closest to or completely equal to the corresponding adjustable resistor R_cancle and the adjustable capacitor. The value of C_cancle can at least cancel or reduce the original reference value of the self-capacitance to be detected, and further improve the performance of detecting the auto-coupling capacitor.
  • the timing relationship between the foregoing steps S101-S104 is only an example. In other embodiments, the timing relationship of the foregoing steps S101-S104 can also be flexibly adjusted, for example, the foregoing steps S103 and S104 are performed first, and then executed. Steps S101 and S102.
  • FIG. 7 is a schematic structural diagram of an apparatus for determining a control parameter of an offset branch in Embodiment 7 of the present application; as shown in FIG. 7, the method includes: a first phase delay determining unit 701, a second phase delay determining unit 702, and a control parameter determining unit. 703; where:
  • An output signal of the back-end processing circuit of the self-capacitance detecting branch to the canceling branch and the self-capacitance when a first constant signal is input to the canceling branch and a first excitation signal is input to the self-capacitance detecting branch The output signal of the detection branch is subjected to differential processing to obtain a first output signal, and the first phase delay determining unit 701 is configured to determine, according to the first output signal, a self-capacitance detection branch and a back end processing of the self-capacitance detection branch. The sum of the phase delays produced by the circuit in response to the first excitation signal;
  • phase delay determining unit 702 is configured to determine, according to the second output signal, that the back-end processing circuit generates a response to the second excitation signal.
  • the control parameter determining unit 703 is configured to determine a control parameter of the canceling branch according to the phase delay sum and a phase delay generated by the back end processing circuit in response to the second excitation signal.
  • the original reference value of the self-capacitance to be detected is offset or reduced by the technical solution of the above embodiment, and the rate of change of the self-capacitance is increased. Further, since the rate of change of the capacitance is increased, the back-end processing single channel is avoided. It is easy to achieve saturation, further increasing the dynamic range of the detection signal and improving the signal to noise ratio.
  • the device embodiments described above are merely illustrative, wherein the modules described as separate components may or may not be physically separate, and the components displayed as modules may or may not be physical modules, ie may be located A place, or it can be distributed to multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the embodiment. Those of ordinary skill in the art can understand and implement without deliberate labor.
  • a machine-readable medium includes read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash storage media, electrical, optical, acoustic, or other forms of propagation signals (eg, carrier waves) , an infrared signal, a digital signal, etc., etc., the computer software product comprising instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform the various embodiments or portions of the embodiments described Methods.
  • ROM read only memory
  • RAM random access memory
  • magnetic disk storage media e.g., magnetic disks, magnetic disk storage media, optical storage media, flash storage media, electrical, optical, acoustic, or other forms of propagation signals (eg, carrier waves) , an infrared signal, a digital signal, etc., etc.
  • the computer software product comprising instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform the various embodiments or portions of the embodiment
  • embodiments of the embodiments of the invention may be provided as a method, apparatus (device), or computer program product.
  • embodiments of the invention may be in the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware.
  • embodiments of the invention may take the form of a computer program product embodied on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • Embodiments of the invention are described with reference to flowchart illustrations and/or block diagrams of methods, apparatus, and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG.
  • These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the device is implemented in a flow or a flow of a flow chart The functions specified in a block or blocks of a block and/or block diagram.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

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Abstract

一种确定抵消支路的控制参数的方法及其装置、触控检测装置。所述方法包括：向抵消支路输入第一恒定信号且向自电容检测支路输入第一激励信号，对应地，所述自电容检测支路的后端处理电路对抵消支路的输出信号和自电容检测支路的输出信号至少进行差分处理得到第一输出信号（S101）；根据第一输出信号确定自电容检测支路以及自电容检测支路的后端处理电路对第一激励信号响应时产生的相位延迟总和（S102）；向所述自电容检测支路输入第二恒定信号，且向抵消支路输入第二激励信号，对应地，所述自电容检测支路的后端处理电路对抵消支路的输出信号和自电容检测支路的输出信号至少进行差分处理得到第二输出信号（S103）；根据第二输出信号确定后端处理电路对第二激励信号响应时产生的相位延迟（S104）；根据相位延迟总和以及后端处理电路对第二激励信号响应时产生的相位延迟，确定所述抵消支路的控制参数（S105），以至少抵消或者减小了待检测自电容的原始基准值。

Description

确定抵消支路的控制参数的方法及其装置、触控检测装置 技术领域
本申请实施例涉及电路技术领域，尤其涉及一种确定抵消支路的控制参数的方法及其装置、触控检测装置。
背景技术
触控控制如应用在电子产品如智能终端上，可以让使用者只要通过手势操作即可实现终端的操作，摆脱了传统的机械键盘，使人机交互更为直截了当。
由于可以直接基于人体对电场的影响实现触控控制，因此，电容触控技术成为目前在电子产品上实现触控控制的主要手段之一。在电容触控技术中，部分是基于互容触控，部分是基于自容触控。由于自容触控，可以提高防水、抗干扰、降低功耗等作用，得到了较为广泛的应用。因此，大多数触摸控制系统是互容检测与自容检测是一体的。
在自容检测中，由于待检测的自电容由检测通道与系统地之间形成，往往存在较大的原始基准值，当有触控发生时，待检测的自电容的电容值的变化量较小或者又称为变化率较小，可能进一步导致触控检测的准确率较低，用户体验差。
发明内容
有鉴于此，本发明实施例所解决的技术问题之一在于提供一种确定抵消支路的控制参数的方法及其装置、触控检测装置，用以克服或者缓解现有技术中上述技术缺陷。
本申请实施例提供了一种确定抵消支路的控制参数的方法，其包括：
向抵消支路输入第一恒定信号，且向自电容检测支路输入第一激励信号，对应地，所述自电容检测支路的后端处理电路对所述抵消支路的输出信号和所述自电容检测支路的输出信号至少进行差分处理得到第一输出信号；
根据所述第一输出信号确定自电容检测支路以及所述自电容检测支路的后端处理电路对第一激励信号响应时产生的相位延迟总和；
向所述自电容检测支路输入第二恒定信号，且向所述抵消支路输入第二激 励信号，对应地，所述自电容检测支路的后端处理电路对所述抵消支路的输出信号和所述自电容检测支路的输出信号至少进行差分处理得到第二输出信号；
根据第二输出信号确定所述后端处理电路对第二激励信号响应时产生的相位延迟；
根据所述相位延迟总和以及所述后端处理电路对所述第二激励信号响应时产生的相位延迟，确定所述抵消支路的控制参数。
可选地，在本申请的任一实施例中，所述第一恒定信号为第一直流偏置信号，和/或，所述第二恒定信号为第二直流偏置信号。
可选地，在本申请的任一实施例中，所述第一激励信号和所述第二激励信号具有相同的频率和起始相位。
可选地，在本申请的任一实施例中，所述抵消支路的控制参数包括可调电阻的阻值以及可调电容的容值，所述可调电阻和所述可调电容用于抵消或者减小所述自电容检测支路中前端RC网络的电阻和待检测自电容的原始基准值。
可选地，在本申请的任一实施例中，在确定所述后端处理电路对所述第二激励信号进行响应时产生的相位延迟时，将所述抵消支路中RC网络设置为纯阻抗网络或者近似纯阻抗网络。
可选地，在本申请的任一实施例中，根据所述第一输出信号，确定所述自电容检测支路以及所述自电容检测支路的后端处理电路对第一激励信号响应时产生的相位延迟总和包括：
根据所述第一输出信号的幅值和相位，确定所述自电容检测支路以及所述后端处理电路对所述第一激励信号响应时产生的相位延迟总和。
可选地，在本申请的任一实施例中，根据所述第一输出信号，确定自电容检测支路以及所述自电容检测支路的后端处理电路对所述第一激励信号响应时产生的相位延迟总和，还包括：
对所述第一输出信号进行解调积分处理得到第一同相信号和第一正交信号；
根据所述第一同相信号和所述第一正交信号，确定所述第一输出信号的幅值和相位。
可选地，在本申请的任一实施例中，根据所述第二输出信号，确定所述后端处理电路对所述第二激励信号响应时产生的相位延迟包括；
根据第二输出信号的幅值和相位确定所述后端处理电路对所述第二激励信号响应时产生的相位延迟。
可选地，在本申请的任一实施例中，根据所述第二输出信号，确定所述后 端处理电路对所述第二激励信号响应时产生的相位延迟包括：
对所述第二输出信号进行解调积分处理得到第二同相信号和第二正交信号；
根据所述第二同相信号和第二正交信号，确定所述第二输出信号的幅值和相位。
可选地，在本申请的任一实施例中，根据所述相位延迟总和以及所述后端处理电路对所述第二激励信号响应时产生的相位延迟，确定所述抵消支路的控制参数包括：
根据所述相位延迟总和以及所述后端处理电路对所述第二激励信号响应产生的相位延迟，确定所述自电容检测支路对所述第一激励信号响应时产生的相位延迟；
根据所述自电容检测支路对所述第一激励信号响应时产生的相位延迟，确定所述抵消支路的控制参数。
可选地，在本申请的任一实施例中，根据所述自电容检测支路对所述第一激励信号响应时产生的相位延迟，确定所述抵消支路的控制参数包括：
根据所述自电容检测支路对所述第一激励信号响应时产生的相位延迟，建立所述自电容检测支路中前端RC网络与所述抵消支路中RC网络的关联关系；
根据所述自电容检测支路中前端RC网络与所述抵消支路中RC网络的关联关系，确定所述抵消支路的控制参数。
可选地，在本申请的任一实施例中，所述抵消支路的控制参数包括第一控制参数和第二控制参数，对应地，根据所述自电容检测支路中前端RC网络与所述抵消支路中RC网络的关联关系，确定所述抵消支路的控制参数包括：
根据所述自电容检测支路中前端RC网络与所述抵消支路中RC网络的关联关系，以及预置所述抵消支路的第一控制参数，确定所述抵消支路的第二控制参数。
可选地，在本申请的任一实施例中，所述后端处理电路包括如下中的至少一种电路：放大器、滤波器、模数转换器，所述放大器用于对所述自检测支路的输出信号和所述抵消支路的输出信号进行差分处理，所述滤波器用于所述差分处理后的信号进行滤波处理，所述模数转换器用于对所述滤波处理后的信号进行模数转换处理。
本申请实施例还提供一种确定抵消支路的控制参数的装置，其包括：第一相位延迟确定单元、第二相位延迟确定单元、控制参数确定单元，其中：
在向抵消支路输入第一恒定信号且向自电容检测支路输入第一激励信号时， 所述自电容检测支路的后端处理电路对所述抵消支路的输出信号和所述自电容检测支路的输出信号至少进行差分处理得到第一输出信号，所述第一相位延迟确定单元用于根据所述第一输出信号确定自电容检测支路以及所述自电容检测支路的后端处理电路对第一激励信号响应时产生的相位延迟总和；
在向所述自电容检测支路输入第二恒定信号且向所述抵消支路输入第二激励信号时，所述自电容检测支路的后端处理电路对所述抵消支路的输出信号和所述自电容检测支路的输出信号至少进行差分处理得到第二输出信号，第二相位延迟确定单元用于以及根据第二输出信号确定所述后端处理电路对第二激励信号响应时产生的相位延迟；
所述控制参数确定单元用于根据所述相位延迟总和以及所述后端处理电路对所述第二激励信号响应时产生的相位延迟，确定所述抵消支路的控制参数。
本申请实施例还提供一种触控检测装置，其包括：自电容检测支路、抵消支路、后端处理电路及上述所述的确定抵消支路的控制参数的装置，所述自电容检测支路与系统地之间形成待检测自电容，所述抵消支路用于根据确定出的控制参数至少抵消所述待检测自电容的原始基准值；所述后端处理电路用于对所述自电容检测支路以及所述抵消支路的输出信号至少进行差分处理以实现触控检测。
本申请实施例中，通过向抵消支路输入第一恒定信号，且向自电容检测支路输入第一激励信号，对应地，所述自电容检测支路的后端处理电路对所述抵消支路的输出信号和所述自电容检测支路的输出信号至少进行差分处理得到第一输出信号；根据所述第一输出信号确定自电容检测支路以及所述自电容检测支路的后端处理电路对第一激励信号响应时产生的相位延迟总和；向所述自电容检测支路输入第二恒定信号，且向所述抵消支路输入第二激励信号，对应地，所述自电容检测支路的后端处理电路对所述抵消支路的输出信号和所述自电容检测支路的输出信号至少进行差分处理得到第二输出信号；根据第二输出信号确定所述后端处理电路对第二激励信号响应时产生的相位延迟；根据所述相位延迟总和以及所述后端处理电路对所述第二激励信号响应时产生的相位延迟，确定所述抵消支路的控制参数，以至少抵消或者减小了待检测自电容的原始基准值，提高了自电容的电容值的变化量或者变化率，可增加触控检测的准确率，进一步地，还可以提高检测自耦电容的性能，从而提高了用户体验。
附图说明
后文将参照附图以示例性而非限制性的方式详细描述本申请实施例的一些具体实施例。附图中相同的附图标记标示了相同或类似的部件或部分。本领域技术人员应该理解，这些附图未必是按比例绘制的。附图中：
图1为本申请实施例一种触控检测装置的结构示意图；
图2为本申请实施例二中确定抵消支路的控制参数的方法流程示意图；
图3为本申请实施例三中执行步骤S101时图1的电路结构动态示意图；
图4为本申请实施例四中步骤S102的示例性示意图；
图5为本申请实施例五中执行步骤S103时图1的电路结构动态示意图；
图6为本申请实施例六中步骤S104的示例性示意图；
图7为本申请实施例七中确定抵消支路的控制参数的装置结构示意图。
具体实施方式
实施本发明实施例的任一技术方案必不一定需要同时达到以上的所有优点。
为了使本领域的人员更好地理解本发明实施例中的技术方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明实施例一部分实施例，而不是全部的实施例。基于本发明实施例中的实施例，本领域普通技术人员所获得的所有其他实施例，都应当属于本发明实施例保护的范围。
下面结合本发明实施例附图进一步说明本发明实施例具体实现。
图1为本申请实施例一种触控检测装置的结构示意图；如图1所示，其具体包括：自电容检测支路、抵消支路、后端处理电路以及以下述图7中的确定抵消支路的控制参数的装置(图1中未示出)，所述自电容检测支路与系统地之间形成待检测自电容，所述抵消支路用于根据确定出的控制参数抵消或减小所述待检测自电容的原始基准值；所述后端处理电路用于对所述自电容检测支路以及所述抵消支路的输出信号至少进行差分处理以实现触控检测。
具体地，本实施例中，自电容检测支路包括：电阻R0、前端RC网络的电阻R以及待检测自电容C，前端RC网络也包括待检测自电容C。电阻R0具体比如为触控芯片或者其他芯片的输出阻抗。
具体地，本实施例中，抵消支路包括：电阻R1、及由可调电阻R_cancle和可调电容C_cancle形成的抵消支路(又称cancle电路)，可调电阻R_cancle和可调电容C_cancle可以根据需求进行数值大小的调整，以抵消或者减小自电容检测支路中前端RC网络的电阻R、所述待检测自电容的原始基准值。这里，抵消或者减小可以理解为两种可能，可调电阻R_cancle抵消或者减小前端RC网络的电阻R，可调电容C_cancle抵消或者减小所述待检测自电容的原始基准值，或者，可调电阻R_cancle和可调电容C_cancle作为整体、前端RC网络的电阻R、所述待检测自电容的原始基准值作为整体，这两个整体之间形成抵消或者减小关系。
需要说明的是，本实施例中，待检测自电容的原始基准值比如为触控检测装置出厂时自电容检测支路与系统地之间形成的电容值。由于工艺或者环境或者人为因素，不同自电容检测支路与系统地之间形成的电容值可能存在差异，因此，起到所述抵消或者减小目的的可调电阻R_cancle和可调电容C_cancle的值也可以不同。
具体地，本实施例中，所述后端处理电路包括：放大器、滤波器、模数转换器(Analog-to-Digital Converter，简称ADC)，所述放大器用于对自检测支路的输出信号和抵消支路的输出信号进行差分处理，所述滤波器用于进一步对差分处理后的信号进行滤波处理，所述模数转换器用于对滤波后的信号进行模数转换处理。
具体地，放大器可以为可编程增益放大器(Programble Gain Amplifier，简称PGA)，滤波器具体可以为抗混叠滤波器(Anti-alias Filter，简称AAF)。所述后端处理电路中各个电路进行信号处理的先后顺序比如为：先进行差分处理，再进行滤波处理，最后进行模数转换处理。但是，这里的信号处理顺序仅仅是示例，并非唯一性限定。
本实施例中，自电容检测支路、抵消支路的输出信号输入到所述后端处理电路中至少进行差分处理，以使得抵消支路抵消或者减小所述自电容检测支路中待检测自电容的原始基准值。
在图1所示的实施例中，为了与自电容检测支路形成对称的结构，在抵消支路中设置了电阻R1，以与自电容检测支路中的电阻R0对应。但是，需要说的是，由于在抵消支路中存在可调电阻，因此，在其他实施例中抵消支路中也可以不用设置电阻R1。
结合上述图1所示的触控检测装置示意图，下述实施例对本申请中如何确 定抵消支路的控制参数进行示例性说明。
图2为本申请实施例二中确定抵消支路的控制参数的方法流程示意图；对于任一自电容检测支路来说，如图2所示，其包括如下步骤S101-S105：
S101、向抵消支路输入第一恒定信号，且向自电容检测支路输入第一激励信号，对应地，所述自电容检测支路的后端处理电路对所述抵消支路的输出信号和所述自电容检测支路的输出信号至少进行差分处理得到第一输出信号；
本实施例中，所述第一恒定信号为第一直流偏置信号，比如该第一直流偏置信号的值等于在触控检测时使用的激励信号的均值Vcmi。所述第一激励信号TX1具有设定的频率和相位，比如频率为ω，相位为0。
图3为本申请实施例三中执行步骤S101时图1的电路结构动态示意图；如图3所示，向抵消支路输入第一恒定信号(如激励信号的均值Vcmi)，同时向所述自电容检测支路输入频率为w、起始相位为0的第一激励信号TX1。
S102、根据所述第一输出信号确定所述自电容检测支路以及所述自电容检测支路的后端处理电路对第一激励信号TX1响应时产生的相位延迟总和；
本实施例中，步骤S102中在根据所述第一输出信号确定所述自电容检测支路以及所述自电容检测支路的后端处理电路对第一激励信号响应时产生的相位延迟总和时，具体可以根据所述第一输出信号的幅值和相位，确定所述自电容检测支路以及所述后端处理电路对所述第一激励信号响应时产生的相位延迟总和。
对应地，上述步骤S102可具体包括步骤S112和步骤S132，具体如图4所示，为本申请实施例四中步骤S102的示例性示意图：
S112、对所述第一输出信号进行解调积分处理得到第一同相信号和第一正交信号；
本实施例中，参见上述图3所示，第一激励信号TX1经过自电容检测电路处理后再与第一恒定信号依次经过后端处理电路中的放大器进行差分放大、滤波器的滤波处理、模数转换器的模数转换处理，从而得到第一输出信号。
本实施例中，经过所述后端处理电路处理得到第一输出信号，所述第一输出信号经过解调积分处理之后得到两路正交的信号即：第一同相(In-phase)信号(又记为第一I信号：I1)以及第一正交(Quadrature)信号(又记为第一Q信号：Q1)。
S122、根据所述第一同相信号和所述第一正交信号，确定所述第一输出信号的幅值和相位；
S132、根据所述第一输出信号的幅值和相位，确定所述自电容检测支路以及所述后端处理电路对所述第一激励信号响应时产生的相位延迟总和。
本实施例中，假设第一激励信号TX1经过自电容检测直流中前端RC网络(即由R0+R，C组成的RC网络)后的相位延迟为
Figure PCTCN2017115935-appb-000001
而经过处理电路中放大器和滤波器处理后导致的相位延迟为
Figure PCTCN2017115935-appb-000002
在模数转换处理后再通过解调积分运算后，可以得到第一同相信号I1和第一正交信号Q1，则具体可以通过如下公式(1)来确定相位延迟总和
Figure PCTCN2017115935-appb-000003
Figure PCTCN2017115935-appb-000004
S103、向所述自电容检测支路输入第二恒定信号，且向所述抵消支路输入第二激励信号，对应地，所述自电容检测支路的后端处理电路对所述抵消支路的输出信号和所述自电容检测支路的输出信号至少进行差分处理得到第二输出信号；
本实施例中，所述第二恒定信号为第二直流偏置信号，比如该第二直流偏置信号的值同样等于在触控检测时使用的激励信号的均值，换言之，第一恒定信号和所述第二恒定信号之间可以相互复用。所述第二激励信号TX2具有设定的频率和起始相位，比如与第一激励信号TX1的频率同为w，起始相位同为0。
本实施例中，优选第一激励信号TX1和第二激励信号TX2的频率和起始相位分别相同，以使得上述相关步骤中在确定所述相位延迟和、所述相位延迟时时，本质上相当于基于同一属性的激励信号，从而节省数据处理的计算量。
另外，为了进一步节省数据处理的计算量，或者降低数据计算的复杂度，第一激励信号TX1和第二激励信号TX2的起始相位优选为0。
当然，在其他实施例中，第一激励信号TX1和第二激励信号TX2的频率和起始相位也可以不同。
图5为本申请实施例五中执行步骤S103时图1的电路结构动态示意图；如图5所示，向自电容检测支路输入第二恒定信号(如激励信号的均值Vcmi)，同时向所述抵消支路输入频率为ω、起始相位为0的第二激励信号TX2。
另外，在步骤S103中，为了确定后端处理电路导致的相位延迟，将所述抵消支路中RC网络设置成近似纯阻抗网络或者纯阻抗网络，从而避免了抵消支路中RC网络导致相位延迟的产生。比如，可以通过将抵消支路中RC网络中的可调电阻和可调电容调整成最小值，以实现将所述抵消支路中RC网络设置成近似纯阻抗网络。
S104、根据第二输出信号确定所述后端处理电路在对所述第二激励信号TX2响应时产生的相位延迟；
本实施例中，步骤S104中在根据第二输出信号确定所述后端处理电路在对所述第二激励信号TX2响应时产生的相位延迟时，可以根据第二输出信号的幅值和相位确定所述后端处理电路对所述第二激励信号响应时产生的相位延迟。
具体地，本实施例中，步骤S104具体可以包括S114和步骤S134，如图6所示，为本申请实施例六中步骤S104的示例性示意图：
S114、对所述第二输出信号进行解调积分处理得到第二同相信号和第二正交信号；
本实施例中，参见上述图5所示，第二激励信号TX2经过抵消支路处理后再与第二恒定信号依次经过后端处理电路中的放大器进行差分放大、滤波器的滤波处理、模数转换器的模数转换处理，从而得到第二输出信号。
需要说明的是，由于在本实施例中，抵消支路中的RC网络近似为纯阻抗网络，因此，从是否导致的相位延迟的角度来看，不会对第二激励信号TX2造成相位延迟，而仅有后端处理电路对第二激励信号TX2造成了相位延迟。纯阻抗网络处理起来是最简单，工程实践会这样去做。实际上，由于R1R_cancel和C_cancel是可知，可以计算出第二输出信号的相位及幅值，依旧可以处理。下面的实例仍以最简单的纯阻抗网络举例。
S124、根据所述第二同相信号和第二正交信号，确定所述第二输出信号的幅值和相位。
S134、根据第二输出信号的幅值和相位确定所述后端处理电路对所述第二激励信号响应时产生的相位延迟。
本实施例中，所述第二输出信号经过解调积分处理之后得到两路正交的信号即：第二同相(In-phase)信号(又记为第二I信号：I2)以及第二正交(Quadrature)信号(又记为第二Q信号：Q2)。通过所述第二同相信号和第二正交信号反应自电容检测支路以及后端处理电路对第一激励信号TX1的幅值和相位的影响。
调节可调电阻R_cancel和可调电容C_cancel到最小值，让抵消支路中的RC网络尽可能近似为纯阻抗网络，这样等效认为后端处理电路中的放大器、滤波器导致了相位延时
Figure PCTCN2017115935-appb-000005
在模数转换处理后再通过解调积分运算后，可以得到第二同相信号I2和第二正交信号Q2，则通过如下公式(2)确定相位延迟
Figure PCTCN2017115935-appb-000006
Figure PCTCN2017115935-appb-000007
S105、根据所述自电容检测支路以及后端处理电路导致的相位延迟总和以及所述后端处理电路导致的相位延迟，确定所述抵消支路的控制参数。
本实施例中，如前所述，所述抵消支路实际上包括可调电阻和可调电容，对应地，抵消支路的控制参数包括可调电阻的值以及可调电容的值，通过调整可调电阻和可调电容的大小，从而抵消或者减小所述自电容检测支路中前端RC网络的电阻和待检测自电容的原始基准值。
本实施例中，步骤S105具体可以包括如下步骤S115至S125：
S115、根据所述相位延迟总和以及所述后端处理电路对所述第二激励信号响应产生的相位延迟，确定所述自电容检测支路对所述第一激励信号响应时产生的相位延迟；
S125、根据所述自电容检测支路对所述第一激励信号响应时产生的相位延迟，确定所述抵消支路的控制参数。
具体地，本实施例中，步骤S125中确定所述抵消支路的控制参数可以包括：
根据所述自电容检测支路对所述第一激励信号响应时产生的相位延迟，建立所述自电容检测支路中前端RC网络与所述抵消支路中RC网络的关联关系；
根据所述自电容检测支路中前端RC网络与所述抵消支路中RC网络的关联关系，确定所述抵消支路的控制参数。
进一步地，所述抵消支路的控制参数包括第一控制参数和第二控制参数，对应地，根据所述自电容检测支路中前端RC网络与所述抵消支路中RC网络的关联关系，确定所述抵消支路的控制参数包括：根据所述自电容检测支路中前端RC网络与所述抵消支路中RC网络的关联关系，以及预置所述抵消支路的第一控制参数，确定所述抵消支路的第二控制参数。
可选地，在本申请的任一实施例中，预置所述抵消支路中的第一控制参数位于设定的数值范围，所述设定的数值范围根据待检测自电容的原始基准值的经验值确定。比如，通过对不同工艺、不同环境下的触控检测装置中的原始基准值进行统计汇总，确定出所述经验值。
结合上述公式(1)、(2)对步骤S105做进一步示例性解释。
根据上述公式(1)和(2)得到如下公式(3)：
Figure PCTCN2017115935-appb-000008
由上述公式(3)可见，通过所述相位延迟和
Figure PCTCN2017115935-appb-000009
以及所述相位延迟
Figure PCTCN2017115935-appb-000010
从而可确定所述自电容检测支路前端RC网络导致的相位延迟
Figure PCTCN2017115935-appb-000011
另外，自电容检测通路上前端RC网络导致的相位延迟
Figure PCTCN2017115935-appb-000012
满足下述公式(4)：
Figure PCTCN2017115935-appb-000013
根据上述公式(3)和(4)得到如下公式(5)：
Figure PCTCN2017115935-appb-000014
参照上述公式(5)可见，通过上述步骤中得到了第一I信号I1、第一Q信号Q1、第二I信号I2、第二Q信号Q2，同时频率ω也是已知的，从而可以计算得到一个常数值const。
对于自电容检测支路和抵消支路来说，其对应电阻和电容乘积即RC参数均等于上述常数值const。即根据第一I信号I1、第一Q信号Q1、第二I信号I2、第二Q信号Q2、频率ω计算得到该常数值，通过所述常数值建立了所述自电容检测支路中前端RC网络与所述抵消支路中RC网络的关联关系，进而根据所述关联关系确定抵消支路中满足可用于抵消或者减小电阻R和待检测自电容的原始基准值的可调电阻和可调电容的值。
在上述公式(5)中，由于电阻R和电阻R0的电阻值已知，而电阻R1的电阻值已知，可调电阻R_cancle和C_cancle的可调档位已知，因此，只要可调电阻R_cancle和C_cancle的值使得电阻R和电阻R0加和后与待检测自电容的原始基准值乘积(即C(R+R0))等于电阻R0和可调电阻R_cancle加和后与可调电容C_cancle的乘积(即(R1+R_cancel)C_cancel)相等即可。
进一步地，在具体实施时，可以通过上述步骤分别得到计算得到一个常数值const，再通过档位选择设定一个可调电容C_cancle的值，再选择一个与通过公式(5)计算得到的可调电容R_cancle的理论值最接近的值，从而确定出上述抵消支路中的控制参数。
如前所述，由于在实际情况中，待检测自电容的原始基准值虽然由于工艺或者环境会有不同，但是，其基本上会处于可预知的数值范围内，因此，在选择可调电容C_cancle时，考虑到可调电容C_cancle与待检测自电容在电路上的对称性，可以结合该数值范围进行选择，从而进一步缩减数据处理，从而可至少抵消或者减小待检测自电容的原始基准值的同时，并进一步提高检测自耦电容的性能。
进一步地，也可以通过查表的方式确定上述可调电阻R_cancle和可调电容C_cancle的值。具体地，比如，可以进行可调电阻R_cancle和可调电容C_cancle 的值的遍历选择，并及计算(R1+R_cancel)C_cancel的值并将这些值以表格的方式存储在芯片内部。当按照上述公式(5)计算得到常数值const后，从存储的表中选择一个满足(R1+R_cancel)C_cancel的值与该常数值const最接近或者完全等于对应的可调电阻R_cancle和可调电容C_cancle的值，从而可至少抵消或者减小待检测自电容的原始基准值的同时，进一步提高检测自耦电容的性能。
在其他实施例中，上述步骤S101-S104之间的时序关系仅仅是示例，在其他实施例中，上述步骤S101-S104的时序关系也可以灵活调整，比如先执行上述步骤S103、S104，再执行步骤S101、S102。
图7为本申请实施例七中确定抵消支路的控制参数的装置结构示意图；如图7所示，其包括：第一相位延迟确定单元701、第二相位延迟确定单元702、控制参数确定单元703；其中：
在向抵消支路输入第一恒定信号且向自电容检测支路输入第一激励信号时，所述自电容检测支路的后端处理电路对所述抵消支路的输出信号和所述自电容检测支路的输出信号至少进行差分处理得到第一输出信号，第一相位延迟确定单元701用于根据所述第一输出信号确定自电容检测支路以及所述自电容检测支路的后端处理电路对第一激励信号响应时产生的相位延迟总和；
在向所述自电容检测支路输入第二恒定信号且向所述抵消支路输入第二激励信号时，所述自电容检测支路的后端处理电路对所述抵消支路的输出信号和所述自电容检测支路的输出信号至少进行差分处理得到第二输出信号，第二相位延迟确定单元702用于以及根据第二输出信号确定所述后端处理电路对第二激励信号响应时产生的相位延迟；
所述控制参数确定单元703用于根据所述相位延迟总和以及所述后端处理电路对所述第二激励信号响应时产生的相位延迟，确定所述抵消支路的控制参数。
在上述实施例中，通过上述实施例的技术方案抵消或者减小待检测自电容的原始基准值，提高自电容的变化率外，进一步由于电容的变化率变大，避免了后端处理单路容易达到饱和，进一步增加了检测信号的动态范围，提高了信噪比。
以上所描述的装置实施例仅仅是示意性的，其中所述作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理模块，即可以位于一个地方，或者也可以分布到多个网络模块上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。 本领域普通技术人员在不付出创造性的劳动的情况下，即可以理解并实施。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到各实施方式可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件。基于这样的理解，上述技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品可以存储在计算机可读存储介质中，所述计算机可读记录介质包括用于以计算机(例如计算机)可读的形式存储或传送信息的任何机制。例如，机器可读介质包括只读存储器(ROM)、随机存取存储器(RAM)、磁盘存储介质、光存储介质、闪速存储介质、电、光、声或其他形式的传播信号(例如，载波、红外信号、数字信号等)等，该计算机软件产品包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行各个实施例或者实施例的某些部分所述的方法。
最后应说明的是：以上实施例仅用以说明本申请实施例的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。
本领域的技术人员应明白，本发明实施例的实施例可提供为方法、装置(设备)、或计算机程序产品。因此，本发明实施例可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明实施例可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本发明实施例是参照根据本发明实施例的方法、装置(设备)和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流 程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。

Claims (15)

  1. 一种确定抵消支路的控制参数的方法，其特征在于，包括：
    向抵消支路输入第一恒定信号，且向自电容检测支路输入第一激励信号，对应地，所述自电容检测支路的后端处理电路对所述抵消支路的输出信号和所述自电容检测支路的输出信号至少进行差分处理得到第一输出信号；
    根据所述第一输出信号确定自电容检测支路以及所述自电容检测支路的后端处理电路对第一激励信号响应时产生的相位延迟总和；
    向所述自电容检测支路输入第二恒定信号，且向所述抵消支路输入第二激励信号，对应地，所述自电容检测支路的后端处理电路对所述抵消支路的输出信号和所述自电容检测支路的输出信号至少进行差分处理得到第二输出信号；
    根据第二输出信号确定所述后端处理电路对第二激励信号响应时产生的相位延迟；
    根据所述相位延迟总和以及所述后端处理电路对所述第二激励信号响应时产生的相位延迟，确定所述抵消支路的控制参数。
  2. 根据权利要求1所述的方法，其特征在于，所述第一恒定信号为第一直流偏置信号，和/或，所述第二恒定信号为第二直流偏置信号。
  3. 根据权利要求1所述的方法，其特征在于，所述第一激励信号和所述第二激励信号具有相同的频率和起始相位。
  4. 根据权利要求1所述的方法，其特征在于，所述抵消支路的控制参数包括可调电阻的阻值以及可调电容的容值，所述可调电阻和所述可调电容用于抵消或者减小所述自电容检测支路中前端RC网络的电阻和待检测自电容的原始基准值。
  5. 根据权利要求1所述的方法，其特征在于，在确定所述后端处理电路对所述第二激励信号进行响应时产生的相位延迟时，将所述抵消支路中RC网络设置为纯阻抗网络或者近似纯阻抗网络。
  6. 根据权利要求1所述的方法，其特征在于，根据所述第一输出信号，确定所述自电容检测支路以及所述自电容检测支路的后端处理电路对第一激励信号响应时产生的相位延迟总和包括：
    根据所述第一输出信号的幅值和相位，确定所述自电容检测支路以及所述后端处理电路对所述第一激励信号响应时产生的相位延迟总和。
  7. 根据权利要求6所述的方法，其特征在于，根据所述第一输出信号，确 定自电容检测支路以及所述自电容检测支路的后端处理电路对所述第一激励信号响应时产生的相位延迟总和，还包括：
    对所述第一输出信号进行解调积分处理得到第一同相信号和第一正交信号；
    根据所述第一同相信号和所述第一正交信号，确定所述第一输出信号的幅值和相位。
  8. 根据权利要求1所述的方法，其特征在于，根据所述第二输出信号，确定所述后端处理电路对所述第二激励信号响应时产生的相位延迟包括；
    根据第二输出信号的幅值和相位确定所述后端处理电路对所述第二激励信号响应时产生的相位延迟。
  9. 根据权利要求8所述的方法，其特征在于，根据所述第二输出信号，确定所述后端处理电路对所述第二激励信号响应时产生的相位延迟包括：
    对所述第二输出信号进行解调积分处理得到第二同相信号和第二正交信号；
    根据所述第二同相信号和第二正交信号，确定所述第二输出信号的幅值和相位。
  10. 根据权利要求1所述的方法，其特征在于，根据所述相位延迟总和以及所述后端处理电路对所述第二激励信号响应时产生的相位延迟，确定所述抵消支路的控制参数包括：
    根据所述相位延迟总和以及所述后端处理电路对所述第二激励信号响应产生的相位延迟，确定所述自电容检测支路对所述第一激励信号响应时产生的相位延迟；
    根据所述自电容检测支路对所述第一激励信号响应时产生的相位延迟，确定所述抵消支路的控制参数。
  11. 根据权利要求10所述的方法，其特征在于，根据所述自电容检测支路对所述第一激励信号响应时产生的相位延迟，确定所述抵消支路的控制参数包括：
    根据所述自电容检测支路对所述第一激励信号响应时产生的相位延迟，建立所述自电容检测支路中前端RC网络与所述抵消支路中RC网络的关联关系；
    根据所述自电容检测支路中前端RC网络与所述抵消支路中RC网络的关联关系，确定所述抵消支路的控制参数。
  12. 根据权利要求11所述的方法，其特征在于，所述抵消支路的控制参数包括第一控制参数和第二控制参数，对应地，根据所述自电容检测支路中前端RC网络与所述抵消支路中RC网络的关联关系，确定所述抵消支路的控制 参数包括：
    根据所述自电容检测支路中前端RC网络与所述抵消支路中RC网络的关联关系，以及预置所述抵消支路的第一控制参数，确定所述抵消支路的第二控制参数。
  13. 抵消支路根据权利要求1-12任一项所述的方法，其特征在于，所述后端处理电路包括如下中的至少一种电路：放大器、滤波器、模数转换器，所述放大器用于对所述自检测支路的输出信号和所述抵消支路的输出信号进行差分处理，所述滤波器用于所述差分处理后的信号进行滤波处理，所述模数转换器用于对所述滤波处理后的信号进行模数转换处理。
  14. 一种确定抵消支路的控制参数的装置，其特征在于，包括：第一相位延迟确定单元、第二相位延迟确定单元、控制参数确定单元，其中：
    在向抵消支路输入第一恒定信号且向自电容检测支路输入第一激励信号时，所述自电容检测支路的后端处理电路对所述抵消支路的输出信号和所述自电容检测支路的输出信号至少进行差分处理得到第一输出信号，所述第一相位延迟确定单元用于根据所述第一输出信号确定自电容检测支路以及所述自电容检测支路的后端处理电路对第一激励信号响应时产生的相位延迟总和；
    在向所述自电容检测支路输入第二恒定信号且向所述抵消支路输入第二激励信号时，所述自电容检测支路的后端处理电路对所述抵消支路的输出信号和所述自电容检测支路的输出信号至少进行差分处理得到第二输出信号，第二相位延迟确定单元用于以及根据第二输出信号确定所述后端处理电路对第二激励信号响应时产生的相位延迟；
    所述控制参数确定单元用于根据所述相位延迟总和以及所述后端处理电路对所述第二激励信号响应时产生的相位延迟，确定所述抵消支路的控制参数。
  15. 一种触控检测装置，其特征在于，包括：自电容检测支路、抵消支路、后端处理电路、及权利要求14所述的确定抵消支路的控制参数的装置，所述自电容检测支路与系统地之间形成待检测自电容，所述抵消支路用于根据确定出的控制参数至少抵消所述待检测自电容的原始基准值；所述后端处理电路用于对所述自电容检测支路以及所述抵消支路的输出信号至少进行差分处理以实现触控检测。
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